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a3a85a76 RW |
1 | #ifndef _ASM_UM_BARRIER_H_ |
2 | #define _ASM_UM_BARRIER_H_ | |
3 | ||
4 | #include <asm/asm.h> | |
5 | #include <asm/segment.h> | |
cd4d09ec | 6 | #include <asm/cpufeatures.h> |
a3a85a76 RW |
7 | #include <asm/cmpxchg.h> |
8 | #include <asm/nops.h> | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/irqflags.h> | |
12 | ||
13 | /* | |
14 | * Force strict CPU ordering. | |
15 | * And yes, this is required on UP too when we're talking | |
16 | * to devices. | |
17 | */ | |
18 | #ifdef CONFIG_X86_32 | |
19 | ||
20 | #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2) | |
21 | #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2) | |
22 | #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM) | |
23 | ||
24 | #else /* CONFIG_X86_32 */ | |
25 | ||
26 | #define mb() asm volatile("mfence" : : : "memory") | |
27 | #define rmb() asm volatile("lfence" : : : "memory") | |
28 | #define wmb() asm volatile("sfence" : : : "memory") | |
29 | ||
30 | #endif /* CONFIG_X86_32 */ | |
31 | ||
a3a85a76 | 32 | #ifdef CONFIG_X86_PPRO_FENCE |
1077fa36 | 33 | #define dma_rmb() rmb() |
a3a85a76 | 34 | #else /* CONFIG_X86_PPRO_FENCE */ |
1077fa36 | 35 | #define dma_rmb() barrier() |
a3a85a76 | 36 | #endif /* CONFIG_X86_PPRO_FENCE */ |
1077fa36 | 37 | #define dma_wmb() barrier() |
a3a85a76 | 38 | |
577f183a | 39 | #include <asm-generic/barrier.h> |
8a449718 | 40 | |
a3a85a76 | 41 | #endif |