Commit | Line | Data |
---|---|---|
084ee1c6 | 1 | #include <linux/io.h> |
5ff3e2c3 | 2 | #include <linux/slab.h> |
084ee1c6 JS |
3 | #include <linux/memblock.h> |
4 | ||
d1163651 | 5 | #include <asm/set_memory.h> |
084ee1c6 JS |
6 | #include <asm/pgtable.h> |
7 | #include <asm/realmode.h> | |
18bc7bd5 | 8 | #include <asm/tlbflush.h> |
084ee1c6 | 9 | |
b429dbf6 | 10 | struct real_mode_header *real_mode_header; |
cda846f1 | 11 | u32 *trampoline_cr4_features; |
084ee1c6 | 12 | |
b234e8a0 TG |
13 | /* Hold the pgd entry used on booting additional CPUs */ |
14 | pgd_t trampoline_pgd_entry; | |
15 | ||
5ff3e2c3 AL |
16 | void __init set_real_mode_mem(phys_addr_t mem, size_t size) |
17 | { | |
18 | void *base = __va(mem); | |
19 | ||
20 | real_mode_header = (struct real_mode_header *) base; | |
21 | printk(KERN_DEBUG "Base memory trampoline at [%p] %llx size %zu\n", | |
22 | base, (unsigned long long)mem, size); | |
23 | } | |
24 | ||
4f7b9226 | 25 | void __init reserve_real_mode(void) |
084ee1c6 JS |
26 | { |
27 | phys_addr_t mem; | |
5ff3e2c3 AL |
28 | size_t size = real_mode_size_needed(); |
29 | ||
30 | if (!size) | |
31 | return; | |
32 | ||
33 | WARN_ON(slab_is_available()); | |
4f7b9226 YL |
34 | |
35 | /* Has to be under 1M so we can execute real-mode AP code. */ | |
36 | mem = memblock_find_in_range(0, 1<<20, size, PAGE_SIZE); | |
5ff3e2c3 AL |
37 | if (!mem) { |
38 | pr_info("No sub-1M memory is available for the trampoline\n"); | |
39 | return; | |
40 | } | |
4f7b9226 | 41 | |
4f7b9226 | 42 | memblock_reserve(mem, size); |
5ff3e2c3 | 43 | set_real_mode_mem(mem, size); |
4f7b9226 YL |
44 | } |
45 | ||
d0de0f68 | 46 | static void __init setup_real_mode(void) |
4f7b9226 | 47 | { |
084ee1c6 | 48 | u16 real_mode_seg; |
7306006f | 49 | const u32 *rel; |
084ee1c6 | 50 | u32 count; |
b429dbf6 | 51 | unsigned char *base; |
7306006f | 52 | unsigned long phys_base; |
f37240f1 | 53 | struct trampoline_header *trampoline_header; |
b429dbf6 | 54 | size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob); |
f37240f1 JS |
55 | #ifdef CONFIG_X86_64 |
56 | u64 *trampoline_pgd; | |
638d957b | 57 | u64 efer; |
f37240f1 | 58 | #endif |
084ee1c6 | 59 | |
4f7b9226 | 60 | base = (unsigned char *)real_mode_header; |
084ee1c6 | 61 | |
b429dbf6 | 62 | memcpy(base, real_mode_blob, size); |
084ee1c6 | 63 | |
7306006f PA |
64 | phys_base = __pa(base); |
65 | real_mode_seg = phys_base >> 4; | |
66 | ||
084ee1c6 JS |
67 | rel = (u32 *) real_mode_relocs; |
68 | ||
69 | /* 16-bit segment relocations. */ | |
7306006f PA |
70 | count = *rel++; |
71 | while (count--) { | |
72 | u16 *seg = (u16 *) (base + *rel++); | |
084ee1c6 JS |
73 | *seg = real_mode_seg; |
74 | } | |
75 | ||
76 | /* 32-bit linear relocations. */ | |
7306006f PA |
77 | count = *rel++; |
78 | while (count--) { | |
79 | u32 *ptr = (u32 *) (base + *rel++); | |
80 | *ptr += phys_base; | |
084ee1c6 JS |
81 | } |
82 | ||
f37240f1 JS |
83 | /* Must be perfomed *after* relocation. */ |
84 | trampoline_header = (struct trampoline_header *) | |
85 | __va(real_mode_header->trampoline_header); | |
86 | ||
48927bbb | 87 | #ifdef CONFIG_X86_32 |
fc8d7826 | 88 | trampoline_header->start = __pa_symbol(startup_32_smp); |
f37240f1 | 89 | trampoline_header->gdt_limit = __BOOT_DS + 7; |
fc8d7826 | 90 | trampoline_header->gdt_base = __pa_symbol(boot_gdt); |
48927bbb | 91 | #else |
79603879 PA |
92 | /* |
93 | * Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR | |
94 | * so we need to mask it out. | |
95 | */ | |
638d957b PA |
96 | rdmsrl(MSR_EFER, efer); |
97 | trampoline_header->efer = efer & ~EFER_LMA; | |
cda846f1 | 98 | |
f37240f1 | 99 | trampoline_header->start = (u64) secondary_startup_64; |
cda846f1 | 100 | trampoline_cr4_features = &trampoline_header->cr4; |
18bc7bd5 | 101 | *trampoline_cr4_features = mmu_cr4_features; |
cda846f1 | 102 | |
f37240f1 | 103 | trampoline_pgd = (u64 *) __va(real_mode_header->trampoline_pgd); |
b234e8a0 | 104 | trampoline_pgd[0] = trampoline_pgd_entry.pgd; |
9735e91e | 105 | trampoline_pgd[511] = init_level4_pgt[511].pgd; |
48927bbb | 106 | #endif |
084ee1c6 JS |
107 | } |
108 | ||
109 | /* | |
4f7b9226 | 110 | * reserve_real_mode() gets called very early, to guarantee the |
231b3642 | 111 | * availability of low memory. This is before the proper kernel page |
084ee1c6 | 112 | * tables are set up, so we cannot set page permissions in that |
231b3642 YL |
113 | * function. Also trampoline code will be executed by APs so we |
114 | * need to mark it executable at do_pre_smp_initcalls() at least, | |
115 | * thus run it as a early_initcall(). | |
084ee1c6 | 116 | */ |
d0de0f68 | 117 | static void __init set_real_mode_permissions(void) |
084ee1c6 | 118 | { |
b429dbf6 JS |
119 | unsigned char *base = (unsigned char *) real_mode_header; |
120 | size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob); | |
084ee1c6 | 121 | |
f156ffc4 | 122 | size_t ro_size = |
b429dbf6 JS |
123 | PAGE_ALIGN(real_mode_header->ro_end) - |
124 | __pa(base); | |
f156ffc4 JS |
125 | |
126 | size_t text_size = | |
b429dbf6 JS |
127 | PAGE_ALIGN(real_mode_header->ro_end) - |
128 | real_mode_header->text_start; | |
f156ffc4 JS |
129 | |
130 | unsigned long text_start = | |
b429dbf6 | 131 | (unsigned long) __va(real_mode_header->text_start); |
f156ffc4 | 132 | |
b429dbf6 JS |
133 | set_memory_nx((unsigned long) base, size >> PAGE_SHIFT); |
134 | set_memory_ro((unsigned long) base, ro_size >> PAGE_SHIFT); | |
f156ffc4 | 135 | set_memory_x((unsigned long) text_start, text_size >> PAGE_SHIFT); |
d0de0f68 AL |
136 | } |
137 | ||
138 | static int __init init_real_mode(void) | |
139 | { | |
140 | if (!real_mode_header) | |
141 | panic("Real mode trampoline was not allocated"); | |
142 | ||
143 | setup_real_mode(); | |
144 | set_real_mode_permissions(); | |
f156ffc4 | 145 | |
084ee1c6 JS |
146 | return 0; |
147 | } | |
d0de0f68 | 148 | early_initcall(init_real_mode); |