Commit | Line | Data |
---|---|---|
9cdeb404 | 1 | /* |
fd19fcd6 BP |
2 | * A simple MCE injection facility for testing different aspects of the RAS |
3 | * code. This driver should be built as module so that it can be loaded | |
4 | * on production kernels for testing purposes. | |
9cdeb404 BP |
5 | * |
6 | * This file may be distributed under the terms of the GNU General Public | |
7 | * License version 2. | |
8 | * | |
6c36dfe9 | 9 | * Copyright (c) 2010-15: Borislav Petkov <bp@alien8.de> |
9cdeb404 BP |
10 | * Advanced Micro Devices Inc. |
11 | */ | |
12 | ||
13 | #include <linux/kobject.h> | |
fd19fcd6 | 14 | #include <linux/debugfs.h> |
51990e82 | 15 | #include <linux/device.h> |
80a2e2e3 | 16 | #include <linux/module.h> |
51756a50 | 17 | #include <linux/cpu.h> |
0451d14d AG |
18 | #include <linux/string.h> |
19 | #include <linux/uaccess.h> | |
fa20a2ed | 20 | #include <linux/pci.h> |
a1300e50 | 21 | |
9cdeb404 | 22 | #include <asm/mce.h> |
ee6825c8 | 23 | #include <asm/smp.h> |
fa20a2ed | 24 | #include <asm/amd_nb.h> |
a1300e50 | 25 | #include <asm/irq_vectors.h> |
9cdeb404 | 26 | |
6c36dfe9 | 27 | #include "../kernel/cpu/mcheck/mce-internal.h" |
9cdeb404 | 28 | |
9cdeb404 BP |
29 | /* |
30 | * Collect all the MCi_XXX settings | |
31 | */ | |
32 | static struct mce i_mce; | |
fd19fcd6 | 33 | static struct dentry *dfs_inj; |
9cdeb404 | 34 | |
685d46d7 AG |
35 | static u8 n_banks; |
36 | ||
0451d14d | 37 | #define MAX_FLAG_OPT_SIZE 3 |
fa20a2ed | 38 | #define NBCFG 0x44 |
0451d14d AG |
39 | |
40 | enum injection_type { | |
41 | SW_INJ = 0, /* SW injection, simply decode the error */ | |
42 | HW_INJ, /* Trigger a #MC */ | |
a1300e50 AG |
43 | DFR_INT_INJ, /* Trigger Deferred error interrupt */ |
44 | THR_INT_INJ, /* Trigger threshold interrupt */ | |
0451d14d AG |
45 | N_INJ_TYPES, |
46 | }; | |
47 | ||
48 | static const char * const flags_options[] = { | |
49 | [SW_INJ] = "sw", | |
50 | [HW_INJ] = "hw", | |
a1300e50 AG |
51 | [DFR_INT_INJ] = "df", |
52 | [THR_INT_INJ] = "th", | |
0451d14d AG |
53 | NULL |
54 | }; | |
55 | ||
56 | /* Set default injection to SW_INJ */ | |
de277678 | 57 | static enum injection_type inj_type = SW_INJ; |
0451d14d | 58 | |
fd19fcd6 BP |
59 | #define MCE_INJECT_SET(reg) \ |
60 | static int inj_##reg##_set(void *data, u64 val) \ | |
9cdeb404 | 61 | { \ |
fd19fcd6 | 62 | struct mce *m = (struct mce *)data; \ |
9cdeb404 | 63 | \ |
fd19fcd6 BP |
64 | m->reg = val; \ |
65 | return 0; \ | |
9cdeb404 BP |
66 | } |
67 | ||
fd19fcd6 BP |
68 | MCE_INJECT_SET(status); |
69 | MCE_INJECT_SET(misc); | |
70 | MCE_INJECT_SET(addr); | |
bad744b7 | 71 | MCE_INJECT_SET(synd); |
9cdeb404 | 72 | |
fd19fcd6 BP |
73 | #define MCE_INJECT_GET(reg) \ |
74 | static int inj_##reg##_get(void *data, u64 *val) \ | |
9cdeb404 | 75 | { \ |
fd19fcd6 BP |
76 | struct mce *m = (struct mce *)data; \ |
77 | \ | |
78 | *val = m->reg; \ | |
79 | return 0; \ | |
9cdeb404 BP |
80 | } |
81 | ||
fd19fcd6 BP |
82 | MCE_INJECT_GET(status); |
83 | MCE_INJECT_GET(misc); | |
84 | MCE_INJECT_GET(addr); | |
bad744b7 | 85 | MCE_INJECT_GET(synd); |
9cdeb404 | 86 | |
fd19fcd6 BP |
87 | DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n"); |
88 | DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n"); | |
89 | DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n"); | |
bad744b7 | 90 | DEFINE_SIMPLE_ATTRIBUTE(synd_fops, inj_synd_get, inj_synd_set, "%llx\n"); |
9cdeb404 | 91 | |
21690934 BP |
92 | /* |
93 | * Caller needs to be make sure this cpu doesn't disappear | |
94 | * from under us, i.e.: get_cpu/put_cpu. | |
95 | */ | |
96 | static int toggle_hw_mce_inject(unsigned int cpu, bool enable) | |
97 | { | |
98 | u32 l, h; | |
99 | int err; | |
100 | ||
101 | err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h); | |
102 | if (err) { | |
103 | pr_err("%s: error reading HWCR\n", __func__); | |
104 | return err; | |
105 | } | |
106 | ||
107 | enable ? (l |= BIT(18)) : (l &= ~BIT(18)); | |
108 | ||
109 | err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h); | |
110 | if (err) | |
111 | pr_err("%s: error writing HWCR\n", __func__); | |
112 | ||
113 | return err; | |
114 | } | |
115 | ||
0451d14d | 116 | static int __set_inj(const char *buf) |
b18f3864 | 117 | { |
0451d14d AG |
118 | int i; |
119 | ||
120 | for (i = 0; i < N_INJ_TYPES; i++) { | |
121 | if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) { | |
122 | inj_type = i; | |
123 | return 0; | |
124 | } | |
125 | } | |
126 | return -EINVAL; | |
127 | } | |
128 | ||
129 | static ssize_t flags_read(struct file *filp, char __user *ubuf, | |
130 | size_t cnt, loff_t *ppos) | |
131 | { | |
132 | char buf[MAX_FLAG_OPT_SIZE]; | |
133 | int n; | |
b18f3864 | 134 | |
0451d14d | 135 | n = sprintf(buf, "%s\n", flags_options[inj_type]); |
b18f3864 | 136 | |
0451d14d | 137 | return simple_read_from_buffer(ubuf, cnt, ppos, buf, n); |
b18f3864 BP |
138 | } |
139 | ||
0451d14d AG |
140 | static ssize_t flags_write(struct file *filp, const char __user *ubuf, |
141 | size_t cnt, loff_t *ppos) | |
b18f3864 | 142 | { |
0451d14d AG |
143 | char buf[MAX_FLAG_OPT_SIZE], *__buf; |
144 | int err; | |
b18f3864 | 145 | |
0451d14d | 146 | if (cnt > MAX_FLAG_OPT_SIZE) |
85c9306d | 147 | return -EINVAL; |
0451d14d AG |
148 | |
149 | if (copy_from_user(&buf, ubuf, cnt)) | |
150 | return -EFAULT; | |
151 | ||
152 | buf[cnt - 1] = 0; | |
153 | ||
154 | /* strip whitespace */ | |
155 | __buf = strstrip(buf); | |
156 | ||
157 | err = __set_inj(__buf); | |
158 | if (err) { | |
159 | pr_err("%s: Invalid flags value: %s\n", __func__, __buf); | |
160 | return err; | |
161 | } | |
162 | ||
85c9306d | 163 | *ppos += cnt; |
0451d14d | 164 | |
85c9306d | 165 | return cnt; |
b18f3864 BP |
166 | } |
167 | ||
0451d14d AG |
168 | static const struct file_operations flags_fops = { |
169 | .read = flags_read, | |
170 | .write = flags_write, | |
171 | .llseek = generic_file_llseek, | |
172 | }; | |
b18f3864 BP |
173 | |
174 | /* | |
175 | * On which CPU to inject? | |
176 | */ | |
177 | MCE_INJECT_GET(extcpu); | |
178 | ||
179 | static int inj_extcpu_set(void *data, u64 val) | |
180 | { | |
181 | struct mce *m = (struct mce *)data; | |
182 | ||
183 | if (val >= nr_cpu_ids || !cpu_online(val)) { | |
184 | pr_err("%s: Invalid CPU: %llu\n", __func__, val); | |
185 | return -EINVAL; | |
186 | } | |
187 | m->extcpu = val; | |
188 | return 0; | |
189 | } | |
190 | ||
191 | DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n"); | |
192 | ||
51756a50 BP |
193 | static void trigger_mce(void *info) |
194 | { | |
195 | asm volatile("int $18"); | |
196 | } | |
197 | ||
a1300e50 AG |
198 | static void trigger_dfr_int(void *info) |
199 | { | |
200 | asm volatile("int %0" :: "i" (DEFERRED_ERROR_VECTOR)); | |
201 | } | |
202 | ||
203 | static void trigger_thr_int(void *info) | |
204 | { | |
205 | asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR)); | |
206 | } | |
207 | ||
fa20a2ed AG |
208 | static u32 get_nbc_for_node(int node_id) |
209 | { | |
210 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
211 | u32 cores_per_node; | |
212 | ||
ee6825c8 | 213 | cores_per_node = (c->x86_max_cores * smp_num_siblings) / amd_get_nodes_per_socket(); |
fa20a2ed AG |
214 | |
215 | return cores_per_node * node_id; | |
216 | } | |
217 | ||
218 | static void toggle_nb_mca_mst_cpu(u16 nid) | |
219 | { | |
220 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; | |
221 | u32 val; | |
222 | int err; | |
223 | ||
224 | if (!F3) | |
225 | return; | |
226 | ||
227 | err = pci_read_config_dword(F3, NBCFG, &val); | |
228 | if (err) { | |
229 | pr_err("%s: Error reading F%dx%03x.\n", | |
230 | __func__, PCI_FUNC(F3->devfn), NBCFG); | |
231 | return; | |
232 | } | |
233 | ||
234 | if (val & BIT(27)) | |
235 | return; | |
236 | ||
237 | pr_err("%s: Set D18F3x44[NbMcaToMstCpuEn] which BIOS hasn't done.\n", | |
238 | __func__); | |
239 | ||
240 | val |= BIT(27); | |
241 | err = pci_write_config_dword(F3, NBCFG, val); | |
242 | if (err) | |
243 | pr_err("%s: Error writing F%dx%03x.\n", | |
244 | __func__, PCI_FUNC(F3->devfn), NBCFG); | |
245 | } | |
246 | ||
340e983a YG |
247 | static void prepare_msrs(void *info) |
248 | { | |
7cc4ef8e BP |
249 | struct mce m = *(struct mce *)info; |
250 | u8 b = m.bank; | |
340e983a | 251 | |
7cc4ef8e | 252 | wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); |
340e983a YG |
253 | |
254 | if (boot_cpu_has(X86_FEATURE_SMCA)) { | |
7cc4ef8e BP |
255 | if (m.inject_flags == DFR_INT_INJ) { |
256 | wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); | |
257 | wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); | |
340e983a | 258 | } else { |
7cc4ef8e BP |
259 | wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); |
260 | wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); | |
340e983a YG |
261 | } |
262 | ||
7cc4ef8e BP |
263 | wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); |
264 | wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); | |
340e983a | 265 | } else { |
7cc4ef8e BP |
266 | wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); |
267 | wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); | |
268 | wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); | |
340e983a | 269 | } |
340e983a YG |
270 | } |
271 | ||
51756a50 BP |
272 | static void do_inject(void) |
273 | { | |
274 | u64 mcg_status = 0; | |
275 | unsigned int cpu = i_mce.extcpu; | |
276 | u8 b = i_mce.bank; | |
277 | ||
cda9459d BP |
278 | if (i_mce.misc) |
279 | i_mce.status |= MCI_STATUS_MISCV; | |
280 | ||
bad744b7 YG |
281 | if (i_mce.synd) |
282 | i_mce.status |= MCI_STATUS_SYNDV; | |
283 | ||
0451d14d | 284 | if (inj_type == SW_INJ) { |
6c36dfe9 | 285 | mce_inject_log(&i_mce); |
51756a50 BP |
286 | return; |
287 | } | |
288 | ||
51756a50 BP |
289 | /* prep MCE global settings for the injection */ |
290 | mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV; | |
291 | ||
292 | if (!(i_mce.status & MCI_STATUS_PCC)) | |
293 | mcg_status |= MCG_STATUS_RIPV; | |
294 | ||
a1300e50 AG |
295 | /* |
296 | * Ensure necessary status bits for deferred errors: | |
297 | * - MCx_STATUS[Deferred]: make sure it is a deferred error | |
298 | * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC | |
299 | */ | |
300 | if (inj_type == DFR_INT_INJ) { | |
301 | i_mce.status |= MCI_STATUS_DEFERRED; | |
302 | i_mce.status |= (i_mce.status & ~MCI_STATUS_UC); | |
303 | } | |
304 | ||
fa20a2ed AG |
305 | /* |
306 | * For multi node CPUs, logging and reporting of bank 4 errors happens | |
307 | * only on the node base core. Refer to D18F3x44[NbMcaToMstCpuEn] for | |
308 | * Fam10h and later BKDGs. | |
309 | */ | |
a884675b YG |
310 | if (static_cpu_has(X86_FEATURE_AMD_DCM) && |
311 | b == 4 && | |
312 | boot_cpu_data.x86 < 0x17) { | |
fa20a2ed AG |
313 | toggle_nb_mca_mst_cpu(amd_get_nb_id(cpu)); |
314 | cpu = get_nbc_for_node(amd_get_nb_id(cpu)); | |
315 | } | |
316 | ||
6d1e9bf5 BP |
317 | get_online_cpus(); |
318 | if (!cpu_online(cpu)) | |
319 | goto err; | |
320 | ||
51756a50 BP |
321 | toggle_hw_mce_inject(cpu, true); |
322 | ||
340e983a YG |
323 | i_mce.mcgstatus = mcg_status; |
324 | i_mce.inject_flags = inj_type; | |
325 | smp_call_function_single(cpu, prepare_msrs, &i_mce, 0); | |
51756a50 BP |
326 | |
327 | toggle_hw_mce_inject(cpu, false); | |
328 | ||
a1300e50 AG |
329 | switch (inj_type) { |
330 | case DFR_INT_INJ: | |
331 | smp_call_function_single(cpu, trigger_dfr_int, NULL, 0); | |
332 | break; | |
333 | case THR_INT_INJ: | |
334 | smp_call_function_single(cpu, trigger_thr_int, NULL, 0); | |
335 | break; | |
336 | default: | |
337 | smp_call_function_single(cpu, trigger_mce, NULL, 0); | |
338 | } | |
51756a50 BP |
339 | |
340 | err: | |
341 | put_online_cpus(); | |
342 | ||
343 | } | |
344 | ||
9cdeb404 BP |
345 | /* |
346 | * This denotes into which bank we're injecting and triggers | |
347 | * the injection, at the same time. | |
348 | */ | |
fd19fcd6 | 349 | static int inj_bank_set(void *data, u64 val) |
9cdeb404 | 350 | { |
fd19fcd6 | 351 | struct mce *m = (struct mce *)data; |
9cdeb404 | 352 | |
685d46d7 AG |
353 | if (val >= n_banks) { |
354 | pr_err("Non-existent MCE bank: %llu\n", val); | |
355 | return -EINVAL; | |
fd19fcd6 | 356 | } |
9cdeb404 | 357 | |
fd19fcd6 | 358 | m->bank = val; |
51756a50 | 359 | do_inject(); |
9cdeb404 | 360 | |
fd19fcd6 | 361 | return 0; |
9cdeb404 BP |
362 | } |
363 | ||
e7f2ea1d | 364 | MCE_INJECT_GET(bank); |
9cdeb404 | 365 | |
fd19fcd6 BP |
366 | DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n"); |
367 | ||
99e21fea | 368 | static const char readme_msg[] = |
f2f3dca1 BP |
369 | "Description of the files and their usages:\n" |
370 | "\n" | |
371 | "Note1: i refers to the bank number below.\n" | |
372 | "Note2: See respective BKDGs for the exact bit definitions of the files below\n" | |
373 | "as they mirror the hardware registers.\n" | |
374 | "\n" | |
375 | "status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n" | |
376 | "\t attributes of the error which caused the MCE.\n" | |
377 | "\n" | |
378 | "misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n" | |
379 | "\t used for error thresholding purposes and its validity is indicated by\n" | |
380 | "\t MCi_STATUS[MiscV].\n" | |
381 | "\n" | |
bad744b7 YG |
382 | "synd:\t Set MCi_SYND: provide syndrome info about the error. Only valid on\n" |
383 | "\t Scalable MCA systems, and its validity is indicated by MCi_STATUS[SyndV].\n" | |
384 | "\n" | |
f2f3dca1 BP |
385 | "addr:\t Error address value to be written to MCi_ADDR. Log address information\n" |
386 | "\t associated with the error.\n" | |
387 | "\n" | |
388 | "cpu:\t The CPU to inject the error on.\n" | |
389 | "\n" | |
390 | "bank:\t Specify the bank you want to inject the error into: the number of\n" | |
391 | "\t banks in a processor varies and is family/model-specific, therefore, the\n" | |
392 | "\t supplied value is sanity-checked. Setting the bank value also triggers the\n" | |
393 | "\t injection.\n" | |
394 | "\n" | |
395 | "flags:\t Injection type to be performed. Writing to this file will trigger a\n" | |
396 | "\t real machine check, an APIC interrupt or invoke the error decoder routines\n" | |
397 | "\t for AMD processors.\n" | |
398 | "\n" | |
399 | "\t Allowed error injection types:\n" | |
400 | "\t - \"sw\": Software error injection. Decode error to a human-readable \n" | |
401 | "\t format only. Safe to use.\n" | |
402 | "\t - \"hw\": Hardware error injection. Causes the #MC exception handler to \n" | |
403 | "\t handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n" | |
404 | "\t is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n" | |
405 | "\t before injecting.\n" | |
a1300e50 AG |
406 | "\t - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n" |
407 | "\t error APIC interrupt handler to handle the error if the feature is \n" | |
408 | "\t is present in hardware. \n" | |
409 | "\t - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n" | |
410 | "\t APIC interrupt handler to handle the error. \n" | |
f2f3dca1 | 411 | "\n"; |
99e21fea AG |
412 | |
413 | static ssize_t | |
414 | inj_readme_read(struct file *filp, char __user *ubuf, | |
415 | size_t cnt, loff_t *ppos) | |
416 | { | |
417 | return simple_read_from_buffer(ubuf, cnt, ppos, | |
418 | readme_msg, strlen(readme_msg)); | |
419 | } | |
420 | ||
421 | static const struct file_operations readme_fops = { | |
422 | .read = inj_readme_read, | |
423 | }; | |
424 | ||
8c2b117f | 425 | static struct dfs_node { |
fd19fcd6 BP |
426 | char *name; |
427 | struct dentry *d; | |
428 | const struct file_operations *fops; | |
4c6034e8 | 429 | umode_t perm; |
fd19fcd6 | 430 | } dfs_fls[] = { |
4c6034e8 AG |
431 | { .name = "status", .fops = &status_fops, .perm = S_IRUSR | S_IWUSR }, |
432 | { .name = "misc", .fops = &misc_fops, .perm = S_IRUSR | S_IWUSR }, | |
433 | { .name = "addr", .fops = &addr_fops, .perm = S_IRUSR | S_IWUSR }, | |
bad744b7 | 434 | { .name = "synd", .fops = &synd_fops, .perm = S_IRUSR | S_IWUSR }, |
4c6034e8 AG |
435 | { .name = "bank", .fops = &bank_fops, .perm = S_IRUSR | S_IWUSR }, |
436 | { .name = "flags", .fops = &flags_fops, .perm = S_IRUSR | S_IWUSR }, | |
437 | { .name = "cpu", .fops = &extcpu_fops, .perm = S_IRUSR | S_IWUSR }, | |
99e21fea | 438 | { .name = "README", .fops = &readme_fops, .perm = S_IRUSR | S_IRGRP | S_IROTH }, |
9cdeb404 BP |
439 | }; |
440 | ||
fd19fcd6 | 441 | static int __init init_mce_inject(void) |
9cdeb404 | 442 | { |
7cc4ef8e | 443 | unsigned int i; |
685d46d7 AG |
444 | u64 cap; |
445 | ||
446 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
447 | n_banks = cap & MCG_BANKCNT_MASK; | |
9cdeb404 | 448 | |
fd19fcd6 BP |
449 | dfs_inj = debugfs_create_dir("mce-inject", NULL); |
450 | if (!dfs_inj) | |
9cdeb404 BP |
451 | return -EINVAL; |
452 | ||
fd19fcd6 BP |
453 | for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) { |
454 | dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name, | |
4c6034e8 | 455 | dfs_fls[i].perm, |
fd19fcd6 BP |
456 | dfs_inj, |
457 | &i_mce, | |
458 | dfs_fls[i].fops); | |
9cdeb404 | 459 | |
fd19fcd6 BP |
460 | if (!dfs_fls[i].d) |
461 | goto err_dfs_add; | |
9cdeb404 | 462 | } |
fd19fcd6 | 463 | |
9cdeb404 BP |
464 | return 0; |
465 | ||
fd19fcd6 | 466 | err_dfs_add: |
8b44f00f | 467 | while (i-- > 0) |
fd19fcd6 | 468 | debugfs_remove(dfs_fls[i].d); |
9cdeb404 | 469 | |
fd19fcd6 BP |
470 | debugfs_remove(dfs_inj); |
471 | dfs_inj = NULL; | |
9cdeb404 | 472 | |
8b44f00f | 473 | return -ENODEV; |
9cdeb404 BP |
474 | } |
475 | ||
fd19fcd6 | 476 | static void __exit exit_mce_inject(void) |
9cdeb404 | 477 | { |
9cdeb404 | 478 | |
b199ac6c BP |
479 | debugfs_remove_recursive(dfs_inj); |
480 | dfs_inj = NULL; | |
9cdeb404 | 481 | |
fd19fcd6 | 482 | memset(&dfs_fls, 0, sizeof(dfs_fls)); |
9cdeb404 | 483 | } |
fd19fcd6 BP |
484 | module_init(init_mce_inject); |
485 | module_exit(exit_mce_inject); | |
9cdeb404 BP |
486 | |
487 | MODULE_LICENSE("GPL"); | |
43aff26c | 488 | MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>"); |
9cdeb404 | 489 | MODULE_AUTHOR("AMD Inc."); |
fd19fcd6 | 490 | MODULE_DESCRIPTION("MCE injection facility for RAS testing"); |