Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Suspend support specific for i386. | |
3 | * | |
4 | * Distribute under GPLv2 | |
5 | * | |
6 | * Copyright (c) 2002 Pavel Machek <pavel@suse.cz> | |
7 | * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org> | |
8 | */ | |
9 | ||
1da177e4 | 10 | #include <linux/module.h> |
1da177e4 | 11 | #include <linux/suspend.h> |
27b07da7 | 12 | #include <asm/mtrr.h> |
a03a3e28 | 13 | #include <asm/mce.h> |
83b8e28b | 14 | #include <asm/xcr.h> |
a8af7898 | 15 | #include <asm/suspend.h> |
1da177e4 LT |
16 | |
17 | static struct saved_context saved_context; | |
18 | ||
19 | unsigned long saved_context_ebx; | |
20 | unsigned long saved_context_esp, saved_context_ebp; | |
21 | unsigned long saved_context_esi, saved_context_edi; | |
22 | unsigned long saved_context_eflags; | |
23 | ||
cae45957 | 24 | static void __save_processor_state(struct saved_context *ctxt) |
1da177e4 | 25 | { |
3ebad590 | 26 | mtrr_save_fixed_ranges(NULL); |
1da177e4 LT |
27 | kernel_fpu_begin(); |
28 | ||
29 | /* | |
30 | * descriptor tables | |
31 | */ | |
db965984 PC |
32 | store_gdt(&ctxt->gdt); |
33 | store_idt(&ctxt->idt); | |
34 | store_tr(ctxt->tr); | |
1da177e4 LT |
35 | |
36 | /* | |
37 | * segment registers | |
38 | */ | |
db965984 PC |
39 | savesegment(es, ctxt->es); |
40 | savesegment(fs, ctxt->fs); | |
41 | savesegment(gs, ctxt->gs); | |
42 | savesegment(ss, ctxt->ss); | |
1da177e4 LT |
43 | |
44 | /* | |
c5759124 | 45 | * control registers |
1da177e4 | 46 | */ |
4bb0d3ec ZA |
47 | ctxt->cr0 = read_cr0(); |
48 | ctxt->cr2 = read_cr2(); | |
49 | ctxt->cr3 = read_cr3(); | |
e532c06f | 50 | ctxt->cr4 = read_cr4_safe(); |
1da177e4 LT |
51 | } |
52 | ||
db965984 | 53 | /* Needed by apm.c */ |
1da177e4 LT |
54 | void save_processor_state(void) |
55 | { | |
56 | __save_processor_state(&saved_context); | |
57 | } | |
db965984 | 58 | EXPORT_SYMBOL(save_processor_state); |
1da177e4 | 59 | |
08967f94 | 60 | static void do_fpu_end(void) |
1da177e4 | 61 | { |
08967f94 SL |
62 | /* |
63 | * Restore FPU regs if necessary. | |
64 | */ | |
65 | kernel_fpu_end(); | |
1da177e4 LT |
66 | } |
67 | ||
1da177e4 LT |
68 | static void fix_processor_context(void) |
69 | { | |
70 | int cpu = smp_processor_id(); | |
db965984 | 71 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
1da177e4 | 72 | |
db965984 PC |
73 | set_tss_desc(cpu, t); /* |
74 | * This just modifies memory; should not be | |
75 | * necessary. But... This is necessary, because | |
76 | * 386 hardware has concept of busy TSS or some | |
77 | * similar stupidity. | |
78 | */ | |
1da177e4 LT |
79 | |
80 | load_TR_desc(); /* This does ltr */ | |
81 | load_LDT(¤t->active_mm->context); /* This does lldt */ | |
82 | ||
83 | /* | |
84 | * Now maybe reload the debug registers | |
85 | */ | |
0f534093 RM |
86 | if (current->thread.debugreg7) { |
87 | set_debugreg(current->thread.debugreg0, 0); | |
88 | set_debugreg(current->thread.debugreg1, 1); | |
89 | set_debugreg(current->thread.debugreg2, 2); | |
90 | set_debugreg(current->thread.debugreg3, 3); | |
1cc6f12e | 91 | /* no 4 and 5 */ |
0f534093 RM |
92 | set_debugreg(current->thread.debugreg6, 6); |
93 | set_debugreg(current->thread.debugreg7, 7); | |
1da177e4 LT |
94 | } |
95 | ||
96 | } | |
97 | ||
cae45957 | 98 | static void __restore_processor_state(struct saved_context *ctxt) |
1da177e4 | 99 | { |
1da177e4 LT |
100 | /* |
101 | * control registers | |
102 | */ | |
e532c06f DF |
103 | /* cr4 was introduced in the Pentium CPU */ |
104 | if (ctxt->cr4) | |
105 | write_cr4(ctxt->cr4); | |
4bb0d3ec ZA |
106 | write_cr3(ctxt->cr3); |
107 | write_cr2(ctxt->cr2); | |
30d6b2f3 | 108 | write_cr0(ctxt->cr0); |
1da177e4 | 109 | |
8d783b3e PM |
110 | /* |
111 | * now restore the descriptor tables to their proper values | |
112 | * ltr is done i fix_processor_context(). | |
113 | */ | |
db965984 PC |
114 | load_gdt(&ctxt->gdt); |
115 | load_idt(&ctxt->idt); | |
8d783b3e | 116 | |
1da177e4 LT |
117 | /* |
118 | * segment registers | |
119 | */ | |
db965984 PC |
120 | loadsegment(es, ctxt->es); |
121 | loadsegment(fs, ctxt->fs); | |
122 | loadsegment(gs, ctxt->gs); | |
123 | loadsegment(ss, ctxt->ss); | |
1da177e4 | 124 | |
1da177e4 LT |
125 | /* |
126 | * sysenter MSRs | |
127 | */ | |
128 | if (boot_cpu_has(X86_FEATURE_SEP)) | |
6fe940d6 | 129 | enable_sep_cpu(); |
1da177e4 | 130 | |
83b8e28b SS |
131 | /* |
132 | * restore XCR0 for xsave capable cpu's. | |
133 | */ | |
134 | if (cpu_has_xsave) | |
135 | xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask); | |
136 | ||
1da177e4 LT |
137 | fix_processor_context(); |
138 | do_fpu_end(); | |
3b520b23 | 139 | mtrr_ap_init(); |
31ab269a | 140 | mcheck_init(&boot_cpu_data); |
1da177e4 LT |
141 | } |
142 | ||
db965984 | 143 | /* Needed by apm.c */ |
1da177e4 LT |
144 | void restore_processor_state(void) |
145 | { | |
146 | __restore_processor_state(&saved_context); | |
147 | } | |
1da177e4 | 148 | EXPORT_SYMBOL(restore_processor_state); |