x86: Clean up cr4 manipulation
[linux-2.6-block.git] / arch / x86 / power / cpu.c
CommitLineData
1da177e4 1/*
6d48becd 2 * Suspend support specific for i386/x86-64.
1da177e4
LT
3 *
4 * Distribute under GPLv2
5 *
cf7700fe 6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
a2531293 7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
1da177e4
LT
8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
9 */
10
1da177e4 11#include <linux/suspend.h>
69c60c88 12#include <linux/export.h>
f6783d20 13#include <linux/smp.h>
1d9d8639 14#include <linux/perf_event.h>
f6783d20 15
3dd08325 16#include <asm/pgtable.h>
f6783d20 17#include <asm/proto.h>
3ebad590 18#include <asm/mtrr.h>
f6783d20
SL
19#include <asm/page.h>
20#include <asm/mce.h>
83b8e28b 21#include <asm/xcr.h>
a8af7898 22#include <asm/suspend.h>
1e350066 23#include <asm/debugreg.h>
1361b83a 24#include <asm/fpu-internal.h> /* pcntxt_mask */
a71c8bc5 25#include <asm/cpu.h>
1da177e4 26
833b2ca0 27#ifdef CONFIG_X86_32
d6efc2f7
AK
28__visible unsigned long saved_context_ebx;
29__visible unsigned long saved_context_esp, saved_context_ebp;
30__visible unsigned long saved_context_esi, saved_context_edi;
31__visible unsigned long saved_context_eflags;
833b2ca0 32#endif
cc456c4e 33struct saved_context saved_context;
1da177e4 34
5c9c9bec
RW
35/**
36 * __save_processor_state - save CPU registers before creating a
37 * hibernation image and before restoring the memory state from it
38 * @ctxt - structure to store the registers contents in
39 *
40 * NOTE: If there is a CPU register the modification of which by the
41 * boot kernel (ie. the kernel used for loading the hibernation image)
42 * might affect the operations of the restored target kernel (ie. the one
43 * saved in the hibernation image), then its contents must be saved by this
44 * function. In other words, if kernel A is hibernated and different
45 * kernel B is used for loading the hibernation image into memory, the
46 * kernel A's __save_processor_state() function must save all registers
47 * needed by kernel A, so that it can operate correctly after the resume
48 * regardless of what kernel B does in the meantime.
49 */
cae45957 50static void __save_processor_state(struct saved_context *ctxt)
1da177e4 51{
f9ebbe53
SL
52#ifdef CONFIG_X86_32
53 mtrr_save_fixed_ranges(NULL);
54#endif
1da177e4
LT
55 kernel_fpu_begin();
56
57 /*
58 * descriptor tables
59 */
f9ebbe53 60#ifdef CONFIG_X86_32
f9ebbe53
SL
61 store_idt(&ctxt->idt);
62#else
63/* CONFIG_X86_64 */
9d1c6e7c 64 store_idt((struct desc_ptr *)&ctxt->idt_limit);
f9ebbe53 65#endif
cc456c4e
KRW
66 /*
67 * We save it here, but restore it only in the hibernate case.
68 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
69 * mode in "secondary_startup_64". In 32-bit mode it is done via
70 * 'pmode_gdt' in wakeup_start.
71 */
72 ctxt->gdt_desc.size = GDT_SIZE - 1;
73 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
74
9d1c6e7c 75 store_tr(ctxt->tr);
1da177e4
LT
76
77 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
1da177e4
LT
78 /*
79 * segment registers
80 */
f9ebbe53
SL
81#ifdef CONFIG_X86_32
82 savesegment(es, ctxt->es);
83 savesegment(fs, ctxt->fs);
84 savesegment(gs, ctxt->gs);
85 savesegment(ss, ctxt->ss);
86#else
87/* CONFIG_X86_64 */
1da177e4
LT
88 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
89 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
90 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
91 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
92 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
93
94 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
95 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
96 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
3ebad590 97 mtrr_save_fixed_ranges(NULL);
1da177e4 98
f9ebbe53
SL
99 rdmsrl(MSR_EFER, ctxt->efer);
100#endif
101
1da177e4 102 /*
cf7700fe 103 * control registers
1da177e4 104 */
f51c9452
GOC
105 ctxt->cr0 = read_cr0();
106 ctxt->cr2 = read_cr2();
107 ctxt->cr3 = read_cr3();
f9ebbe53
SL
108#ifdef CONFIG_X86_32
109 ctxt->cr4 = read_cr4_safe();
110#else
111/* CONFIG_X86_64 */
f51c9452
GOC
112 ctxt->cr4 = read_cr4();
113 ctxt->cr8 = read_cr8();
f9ebbe53 114#endif
85a0e753
OZ
115 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
116 &ctxt->misc_enable);
1da177e4
LT
117}
118
f9ebbe53 119/* Needed by apm.c */
1da177e4
LT
120void save_processor_state(void)
121{
122 __save_processor_state(&saved_context);
b74f05d6 123 x86_platform.save_sched_clock_state();
1da177e4 124}
f9ebbe53
SL
125#ifdef CONFIG_X86_32
126EXPORT_SYMBOL(save_processor_state);
127#endif
1da177e4 128
08967f94 129static void do_fpu_end(void)
1da177e4 130{
08967f94 131 /*
3134d04b 132 * Restore FPU regs if necessary.
08967f94
SL
133 */
134 kernel_fpu_end();
1da177e4
LT
135}
136
3134d04b
SL
137static void fix_processor_context(void)
138{
139 int cpu = smp_processor_id();
140 struct tss_struct *t = &per_cpu(init_tss, cpu);
4d681be3 141#ifdef CONFIG_X86_64
142 struct desc_struct *desc = get_cpu_gdt_table(cpu);
143 tss_desc tss;
144#endif
3134d04b
SL
145 set_tss_desc(cpu, t); /*
146 * This just modifies memory; should not be
147 * necessary. But... This is necessary, because
148 * 386 hardware has concept of busy TSS or some
149 * similar stupidity.
150 */
151
152#ifdef CONFIG_X86_64
4d681be3 153 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
154 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
155 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
3134d04b
SL
156
157 syscall_init(); /* This sets MSR_*STAR and related */
158#endif
159 load_TR_desc(); /* This does ltr */
160 load_LDT(&current->active_mm->context); /* This does lldt */
3134d04b
SL
161}
162
5c9c9bec
RW
163/**
164 * __restore_processor_state - restore the contents of CPU registers saved
165 * by __save_processor_state()
166 * @ctxt - structure to load the registers contents from
167 */
b8f99b3e 168static void notrace __restore_processor_state(struct saved_context *ctxt)
1da177e4 169{
85a0e753
OZ
170 if (ctxt->misc_enable_saved)
171 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
1da177e4
LT
172 /*
173 * control registers
174 */
3134d04b
SL
175 /* cr4 was introduced in the Pentium CPU */
176#ifdef CONFIG_X86_32
177 if (ctxt->cr4)
178 write_cr4(ctxt->cr4);
179#else
180/* CONFIG X86_64 */
3c321bce 181 wrmsrl(MSR_EFER, ctxt->efer);
f51c9452
GOC
182 write_cr8(ctxt->cr8);
183 write_cr4(ctxt->cr4);
3134d04b 184#endif
f51c9452
GOC
185 write_cr3(ctxt->cr3);
186 write_cr2(ctxt->cr2);
187 write_cr0(ctxt->cr0);
1da177e4 188
8d783b3e
PM
189 /*
190 * now restore the descriptor tables to their proper values
191 * ltr is done i fix_processor_context().
192 */
3134d04b 193#ifdef CONFIG_X86_32
3134d04b
SL
194 load_idt(&ctxt->idt);
195#else
196/* CONFIG_X86_64 */
9d1c6e7c 197 load_idt((const struct desc_ptr *)&ctxt->idt_limit);
3134d04b 198#endif
8d783b3e 199
1da177e4
LT
200 /*
201 * segment registers
202 */
3134d04b
SL
203#ifdef CONFIG_X86_32
204 loadsegment(es, ctxt->es);
205 loadsegment(fs, ctxt->fs);
206 loadsegment(gs, ctxt->gs);
207 loadsegment(ss, ctxt->ss);
208
209 /*
210 * sysenter MSRs
211 */
212 if (boot_cpu_has(X86_FEATURE_SEP))
213 enable_sep_cpu();
214#else
215/* CONFIG_X86_64 */
1da177e4
LT
216 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
217 asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
218 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
219 load_gs_index(ctxt->gs);
220 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
221
222 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
223 wrmsrl(MSR_GS_BASE, ctxt->gs_base);
224 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
3134d04b 225#endif
1da177e4 226
83b8e28b
SS
227 /*
228 * restore XCR0 for xsave capable cpu's.
229 */
230 if (cpu_has_xsave)
231 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
232
1da177e4
LT
233 fix_processor_context();
234
235 do_fpu_end();
dba69d10 236 x86_platform.restore_sched_clock_state();
d0af9eed 237 mtrr_bp_restore();
1d9d8639 238 perf_restore_debug_store();
1da177e4
LT
239}
240
3134d04b 241/* Needed by apm.c */
b8f99b3e 242void notrace restore_processor_state(void)
1da177e4
LT
243{
244 __restore_processor_state(&saved_context);
245}
3134d04b
SL
246#ifdef CONFIG_X86_32
247EXPORT_SYMBOL(restore_processor_state);
248#endif
209efae1
FY
249
250/*
251 * When bsp_check() is called in hibernate and suspend, cpu hotplug
252 * is disabled already. So it's unnessary to handle race condition between
253 * cpumask query and cpu hotplug.
254 */
255static int bsp_check(void)
256{
257 if (cpumask_first(cpu_online_mask) != 0) {
258 pr_warn("CPU0 is offline.\n");
259 return -ENODEV;
260 }
261
262 return 0;
263}
264
265static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
266 void *ptr)
267{
268 int ret = 0;
269
270 switch (action) {
271 case PM_SUSPEND_PREPARE:
272 case PM_HIBERNATION_PREPARE:
273 ret = bsp_check();
274 break;
a71c8bc5
FY
275#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
276 case PM_RESTORE_PREPARE:
277 /*
278 * When system resumes from hibernation, online CPU0 because
279 * 1. it's required for resume and
280 * 2. the CPU was online before hibernation
281 */
282 if (!cpu_online(0))
283 _debug_hotplug_cpu(0, 1);
284 break;
285 case PM_POST_RESTORE:
286 /*
287 * When a resume really happens, this code won't be called.
288 *
289 * This code is called only when user space hibernation software
290 * prepares for snapshot device during boot time. So we just
291 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
292 * preparing the snapshot device.
293 *
294 * This works for normal boot case in our CPU0 hotplug debug
295 * mode, i.e. CPU0 is offline and user mode hibernation
296 * software initializes during boot time.
297 *
298 * If CPU0 is online and user application accesses snapshot
299 * device after boot time, this will offline CPU0 and user may
300 * see different CPU0 state before and after accessing
301 * the snapshot device. But hopefully this is not a case when
302 * user debugging CPU0 hotplug. Even if users hit this case,
303 * they can easily online CPU0 back.
304 *
305 * To simplify this debug code, we only consider normal boot
306 * case. Otherwise we need to remember CPU0's state and restore
307 * to that state and resolve racy conditions etc.
308 */
309 _debug_hotplug_cpu(0, 0);
310 break;
311#endif
209efae1
FY
312 default:
313 break;
314 }
315 return notifier_from_errno(ret);
316}
317
318static int __init bsp_pm_check_init(void)
319{
320 /*
321 * Set this bsp_pm_callback as lower priority than
322 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
323 * earlier to disable cpu hotplug before bsp online check.
324 */
325 pm_notifier(bsp_pm_callback, -INT_MAX);
326 return 0;
327}
328
329core_initcall(bsp_pm_check_init);