Commit | Line | Data |
---|---|---|
1812924b CW |
1 | /* |
2 | * SGI UltraViolet TLB flush routines. | |
3 | * | |
a26fd719 | 4 | * (c) 2008-2014 Cliff Wickman <cpw@sgi.com>, SGI. |
1812924b CW |
5 | * |
6 | * This code is released under the GNU General Public License version 2 or | |
7 | * later. | |
8 | */ | |
aef8f5b8 | 9 | #include <linux/seq_file.h> |
1812924b | 10 | #include <linux/proc_fs.h> |
e8e5e8a8 | 11 | #include <linux/debugfs.h> |
1812924b | 12 | #include <linux/kernel.h> |
5a0e3ad6 | 13 | #include <linux/slab.h> |
ca444564 | 14 | #include <linux/delay.h> |
1812924b | 15 | |
1812924b | 16 | #include <asm/mmu_context.h> |
bdbcdd48 | 17 | #include <asm/uv/uv.h> |
1812924b | 18 | #include <asm/uv/uv_mmrs.h> |
b4c286e6 | 19 | #include <asm/uv/uv_hub.h> |
1812924b | 20 | #include <asm/uv/uv_bau.h> |
7b6aa335 | 21 | #include <asm/apic.h> |
b4c286e6 | 22 | #include <asm/idle.h> |
b194b120 | 23 | #include <asm/tsc.h> |
99dd8713 | 24 | #include <asm/irq_vectors.h> |
b8f7fb13 | 25 | #include <asm/timer.h> |
1812924b | 26 | |
5e4f96fe AB |
27 | static struct bau_operations ops; |
28 | ||
29 | static struct bau_operations uv123_bau_ops = { | |
30 | .bau_gpa_to_offset = uv_gpa_to_offset, | |
31 | .read_l_sw_ack = read_mmr_sw_ack, | |
32 | .read_g_sw_ack = read_gmmr_sw_ack, | |
33 | .write_l_sw_ack = write_mmr_sw_ack, | |
34 | .write_g_sw_ack = write_gmmr_sw_ack, | |
35 | .write_payload_first = write_mmr_payload_first, | |
36 | .write_payload_last = write_mmr_payload_last, | |
37 | }; | |
38 | ||
4f059d51 AB |
39 | static struct bau_operations uv4_bau_ops = { |
40 | .bau_gpa_to_offset = uv_gpa_to_soc_phys_ram, | |
41 | .read_l_sw_ack = read_mmr_proc_sw_ack, | |
42 | .read_g_sw_ack = read_gmmr_proc_sw_ack, | |
43 | .write_l_sw_ack = write_mmr_proc_sw_ack, | |
44 | .write_g_sw_ack = write_gmmr_proc_sw_ack, | |
45 | .write_payload_first = write_mmr_proc_payload_first, | |
46 | .write_payload_last = write_mmr_proc_payload_last, | |
47 | }; | |
48 | ||
49 | ||
12a6611f CW |
50 | /* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */ |
51 | static int timeout_base_ns[] = { | |
52 | 20, | |
53 | 160, | |
54 | 1280, | |
55 | 10240, | |
56 | 81920, | |
57 | 655360, | |
58 | 5242880, | |
59 | 167772160 | |
60 | }; | |
f073cc8f | 61 | |
12a6611f | 62 | static int timeout_us; |
1c532e00 | 63 | static bool nobau = true; |
26ef8577 | 64 | static int nobau_perm; |
50fb55ac | 65 | static cycles_t congested_cycles; |
12a6611f | 66 | |
e8e5e8a8 | 67 | /* tunables: */ |
f073cc8f CW |
68 | static int max_concurr = MAX_BAU_CONCURRENT; |
69 | static int max_concurr_const = MAX_BAU_CONCURRENT; | |
70 | static int plugged_delay = PLUGGED_DELAY; | |
71 | static int plugsb4reset = PLUGSB4RESET; | |
8b6e511e | 72 | static int giveup_limit = GIVEUP_LIMIT; |
f073cc8f CW |
73 | static int timeoutsb4reset = TIMEOUTSB4RESET; |
74 | static int ipi_reset_limit = IPI_RESET_LIMIT; | |
75 | static int complete_threshold = COMPLETE_THRESHOLD; | |
76 | static int congested_respns_us = CONGESTED_RESPONSE_US; | |
77 | static int congested_reps = CONGESTED_REPS; | |
8b6e511e | 78 | static int disabled_period = DISABLED_PERIOD; |
f073cc8f CW |
79 | |
80 | static struct tunables tunables[] = { | |
67492c86 AB |
81 | {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */ |
82 | {&plugged_delay, PLUGGED_DELAY}, | |
83 | {&plugsb4reset, PLUGSB4RESET}, | |
84 | {&timeoutsb4reset, TIMEOUTSB4RESET}, | |
85 | {&ipi_reset_limit, IPI_RESET_LIMIT}, | |
86 | {&complete_threshold, COMPLETE_THRESHOLD}, | |
87 | {&congested_respns_us, CONGESTED_RESPONSE_US}, | |
88 | {&congested_reps, CONGESTED_REPS}, | |
89 | {&disabled_period, DISABLED_PERIOD}, | |
90 | {&giveup_limit, GIVEUP_LIMIT} | |
f073cc8f CW |
91 | }; |
92 | ||
e8e5e8a8 CW |
93 | static struct dentry *tunables_dir; |
94 | static struct dentry *tunables_file; | |
b4c286e6 | 95 | |
f073cc8f CW |
96 | /* these correspond to the statistics printed by ptc_seq_show() */ |
97 | static char *stat_description[] = { | |
98 | "sent: number of shootdown messages sent", | |
99 | "stime: time spent sending messages", | |
100 | "numuvhubs: number of hubs targeted with shootdown", | |
101 | "numuvhubs16: number times 16 or more hubs targeted", | |
102 | "numuvhubs8: number times 8 or more hubs targeted", | |
103 | "numuvhubs4: number times 4 or more hubs targeted", | |
104 | "numuvhubs2: number times 2 or more hubs targeted", | |
105 | "numuvhubs1: number times 1 hub targeted", | |
106 | "numcpus: number of cpus targeted with shootdown", | |
107 | "dto: number of destination timeouts", | |
108 | "retries: destination timeout retries sent", | |
109 | "rok: : destination timeouts successfully retried", | |
110 | "resetp: ipi-style resource resets for plugs", | |
111 | "resett: ipi-style resource resets for timeouts", | |
112 | "giveup: fall-backs to ipi-style shootdowns", | |
113 | "sto: number of source timeouts", | |
114 | "bz: number of stay-busy's", | |
115 | "throt: number times spun in throttle", | |
116 | "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE", | |
117 | "recv: shootdown messages received", | |
118 | "rtime: time spent processing messages", | |
119 | "all: shootdown all-tlb messages", | |
120 | "one: shootdown one-tlb messages", | |
121 | "mult: interrupts that found multiple messages", | |
122 | "none: interrupts that found no messages", | |
123 | "retry: number of retry messages processed", | |
124 | "canc: number messages canceled by retries", | |
125 | "nocan: number retries that found nothing to cancel", | |
126 | "reset: number of ipi-style reset requests processed", | |
127 | "rcan: number messages canceled by reset requests", | |
128 | "disable: number times use of the BAU was disabled", | |
129 | "enable: number times use of the BAU was re-enabled" | |
130 | }; | |
131 | ||
1c532e00 | 132 | static int __init setup_bau(char *arg) |
b8f7fb13 | 133 | { |
1c532e00 AT |
134 | int result; |
135 | ||
136 | if (!arg) | |
137 | return -EINVAL; | |
138 | ||
139 | result = strtobool(arg, &nobau); | |
140 | if (result) | |
141 | return result; | |
142 | ||
143 | /* we need to flip the logic here, so that bau=y sets nobau to false */ | |
144 | nobau = !nobau; | |
145 | ||
146 | if (!nobau) | |
147 | pr_info("UV BAU Enabled\n"); | |
148 | else | |
149 | pr_info("UV BAU Disabled\n"); | |
150 | ||
b8f7fb13 CW |
151 | return 0; |
152 | } | |
1c532e00 | 153 | early_param("bau", setup_bau); |
b4c286e6 | 154 | |
b8f7fb13 | 155 | /* base pnode in this partition */ |
f073cc8f | 156 | static int uv_base_pnode __read_mostly; |
1812924b | 157 | |
dc163a41 IM |
158 | static DEFINE_PER_CPU(struct ptc_stats, ptcstats); |
159 | static DEFINE_PER_CPU(struct bau_control, bau_control); | |
b8f7fb13 CW |
160 | static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask); |
161 | ||
26ef8577 CW |
162 | static void |
163 | set_bau_on(void) | |
164 | { | |
165 | int cpu; | |
166 | struct bau_control *bcp; | |
167 | ||
168 | if (nobau_perm) { | |
169 | pr_info("BAU not initialized; cannot be turned on\n"); | |
170 | return; | |
171 | } | |
1c532e00 | 172 | nobau = false; |
26ef8577 CW |
173 | for_each_present_cpu(cpu) { |
174 | bcp = &per_cpu(bau_control, cpu); | |
1c532e00 | 175 | bcp->nobau = false; |
26ef8577 CW |
176 | } |
177 | pr_info("BAU turned on\n"); | |
178 | return; | |
179 | } | |
180 | ||
181 | static void | |
182 | set_bau_off(void) | |
183 | { | |
184 | int cpu; | |
185 | struct bau_control *bcp; | |
186 | ||
1c532e00 | 187 | nobau = true; |
26ef8577 CW |
188 | for_each_present_cpu(cpu) { |
189 | bcp = &per_cpu(bau_control, cpu); | |
1c532e00 | 190 | bcp->nobau = true; |
26ef8577 CW |
191 | } |
192 | pr_info("BAU turned off\n"); | |
193 | return; | |
194 | } | |
195 | ||
9674f35b | 196 | /* |
b8f7fb13 CW |
197 | * Determine the first node on a uvhub. 'Nodes' are used for kernel |
198 | * memory allocation. | |
9674f35b | 199 | */ |
b8f7fb13 | 200 | static int __init uvhub_to_first_node(int uvhub) |
9674f35b CW |
201 | { |
202 | int node, b; | |
203 | ||
204 | for_each_online_node(node) { | |
205 | b = uv_node_to_blade_id(node); | |
b8f7fb13 | 206 | if (uvhub == b) |
9674f35b CW |
207 | return node; |
208 | } | |
b8f7fb13 | 209 | return -1; |
9674f35b CW |
210 | } |
211 | ||
212 | /* | |
b8f7fb13 | 213 | * Determine the apicid of the first cpu on a uvhub. |
9674f35b | 214 | */ |
b8f7fb13 | 215 | static int __init uvhub_to_first_apicid(int uvhub) |
9674f35b CW |
216 | { |
217 | int cpu; | |
218 | ||
219 | for_each_present_cpu(cpu) | |
b8f7fb13 | 220 | if (uvhub == uv_cpu_to_blade_id(cpu)) |
9674f35b CW |
221 | return per_cpu(x86_cpu_to_apicid, cpu); |
222 | return -1; | |
223 | } | |
224 | ||
1812924b CW |
225 | /* |
226 | * Free a software acknowledge hardware resource by clearing its Pending | |
227 | * bit. This will return a reply to the sender. | |
228 | * If the message has timed out, a reply has already been sent by the | |
229 | * hardware but the resource has not been released. In that case our | |
230 | * clear of the Timeout bit (as well) will free the resource. No reply will | |
231 | * be sent (the hardware will only do one reply per message). | |
232 | */ | |
c5d35d39 CW |
233 | static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp, |
234 | int do_acknowledge) | |
1812924b | 235 | { |
b194b120 | 236 | unsigned long dw; |
f073cc8f | 237 | struct bau_pq_entry *msg; |
1812924b | 238 | |
b8f7fb13 | 239 | msg = mdp->msg; |
c5d35d39 | 240 | if (!msg->canceled && do_acknowledge) { |
f073cc8f | 241 | dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec; |
21e3f12f | 242 | ops.write_l_sw_ack(dw); |
b8f7fb13 | 243 | } |
1812924b | 244 | msg->replied_to = 1; |
f073cc8f | 245 | msg->swack_vec = 0; |
1812924b CW |
246 | } |
247 | ||
248 | /* | |
b8f7fb13 | 249 | * Process the receipt of a RETRY message |
1812924b | 250 | */ |
f073cc8f CW |
251 | static void bau_process_retry_msg(struct msg_desc *mdp, |
252 | struct bau_control *bcp) | |
1812924b | 253 | { |
b8f7fb13 CW |
254 | int i; |
255 | int cancel_count = 0; | |
b8f7fb13 CW |
256 | unsigned long msg_res; |
257 | unsigned long mmr = 0; | |
f073cc8f CW |
258 | struct bau_pq_entry *msg = mdp->msg; |
259 | struct bau_pq_entry *msg2; | |
260 | struct ptc_stats *stat = bcp->statp; | |
1812924b | 261 | |
b8f7fb13 CW |
262 | stat->d_retries++; |
263 | /* | |
264 | * cancel any message from msg+1 to the retry itself | |
265 | */ | |
266 | for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) { | |
f073cc8f CW |
267 | if (msg2 > mdp->queue_last) |
268 | msg2 = mdp->queue_first; | |
b8f7fb13 CW |
269 | if (msg2 == msg) |
270 | break; | |
271 | ||
f073cc8f | 272 | /* same conditions for cancellation as do_reset */ |
b8f7fb13 | 273 | if ((msg2->replied_to == 0) && (msg2->canceled == 0) && |
f073cc8f CW |
274 | (msg2->swack_vec) && ((msg2->swack_vec & |
275 | msg->swack_vec) == 0) && | |
b8f7fb13 CW |
276 | (msg2->sending_cpu == msg->sending_cpu) && |
277 | (msg2->msg_type != MSG_NOOP)) { | |
21e3f12f | 278 | mmr = ops.read_l_sw_ack(); |
f073cc8f | 279 | msg_res = msg2->swack_vec; |
b8f7fb13 CW |
280 | /* |
281 | * This is a message retry; clear the resources held | |
282 | * by the previous message only if they timed out. | |
283 | * If it has not timed out we have an unexpected | |
284 | * situation to report. | |
285 | */ | |
39847e7f | 286 | if (mmr & (msg_res << UV_SW_ACK_NPENDING)) { |
f073cc8f | 287 | unsigned long mr; |
b8f7fb13 | 288 | /* |
c5d35d39 CW |
289 | * Is the resource timed out? |
290 | * Make everyone ignore the cancelled message. | |
b8f7fb13 CW |
291 | */ |
292 | msg2->canceled = 1; | |
293 | stat->d_canceled++; | |
294 | cancel_count++; | |
f073cc8f | 295 | mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; |
21e3f12f | 296 | ops.write_l_sw_ack(mr); |
39847e7f | 297 | } |
b8f7fb13 CW |
298 | } |
299 | } | |
300 | if (!cancel_count) | |
301 | stat->d_nocanceled++; | |
302 | } | |
1812924b | 303 | |
b8f7fb13 CW |
304 | /* |
305 | * Do all the things a cpu should do for a TLB shootdown message. | |
306 | * Other cpu's may come here at the same time for this message. | |
307 | */ | |
c5d35d39 CW |
308 | static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp, |
309 | int do_acknowledge) | |
b8f7fb13 | 310 | { |
b8f7fb13 | 311 | short socket_ack_count = 0; |
f073cc8f CW |
312 | short *sp; |
313 | struct atomic_short *asp; | |
314 | struct ptc_stats *stat = bcp->statp; | |
315 | struct bau_pq_entry *msg = mdp->msg; | |
b8f7fb13 | 316 | struct bau_control *smaster = bcp->socket_master; |
1812924b | 317 | |
b8f7fb13 CW |
318 | /* |
319 | * This must be a normal message, or retry of a normal message | |
320 | */ | |
1812924b CW |
321 | if (msg->address == TLB_FLUSH_ALL) { |
322 | local_flush_tlb(); | |
b8f7fb13 | 323 | stat->d_alltlb++; |
1812924b CW |
324 | } else { |
325 | __flush_tlb_one(msg->address); | |
b8f7fb13 | 326 | stat->d_onetlb++; |
1812924b | 327 | } |
b8f7fb13 CW |
328 | stat->d_requestee++; |
329 | ||
330 | /* | |
331 | * One cpu on each uvhub has the additional job on a RETRY | |
332 | * of releasing the resource held by the message that is | |
333 | * being retried. That message is identified by sending | |
334 | * cpu number. | |
335 | */ | |
336 | if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master) | |
f073cc8f | 337 | bau_process_retry_msg(mdp, bcp); |
1812924b | 338 | |
b8f7fb13 | 339 | /* |
f073cc8f | 340 | * This is a swack message, so we have to reply to it. |
b8f7fb13 CW |
341 | * Count each responding cpu on the socket. This avoids |
342 | * pinging the count's cache line back and forth between | |
343 | * the sockets. | |
344 | */ | |
f073cc8f CW |
345 | sp = &smaster->socket_acknowledge_count[mdp->msg_slot]; |
346 | asp = (struct atomic_short *)sp; | |
347 | socket_ack_count = atom_asr(1, asp); | |
b8f7fb13 | 348 | if (socket_ack_count == bcp->cpus_in_socket) { |
f073cc8f | 349 | int msg_ack_count; |
b8f7fb13 CW |
350 | /* |
351 | * Both sockets dump their completed count total into | |
352 | * the message's count. | |
353 | */ | |
8b6e511e | 354 | *sp = 0; |
f073cc8f CW |
355 | asp = (struct atomic_short *)&msg->acknowledge_count; |
356 | msg_ack_count = atom_asr(socket_ack_count, asp); | |
b8f7fb13 CW |
357 | |
358 | if (msg_ack_count == bcp->cpus_in_uvhub) { | |
359 | /* | |
360 | * All cpus in uvhub saw it; reply | |
c5d35d39 | 361 | * (unless we are in the UV2 workaround) |
b8f7fb13 | 362 | */ |
c5d35d39 | 363 | reply_to_message(mdp, bcp, do_acknowledge); |
b8f7fb13 CW |
364 | } |
365 | } | |
1812924b | 366 | |
b8f7fb13 | 367 | return; |
1812924b CW |
368 | } |
369 | ||
370 | /* | |
485f07d3 | 371 | * Determine the first cpu on a pnode. |
b8f7fb13 | 372 | */ |
485f07d3 | 373 | static int pnode_to_first_cpu(int pnode, struct bau_control *smaster) |
b8f7fb13 CW |
374 | { |
375 | int cpu; | |
485f07d3 | 376 | struct hub_and_pnode *hpp; |
377 | ||
378 | for_each_present_cpu(cpu) { | |
379 | hpp = &smaster->thp[cpu]; | |
380 | if (pnode == hpp->pnode) | |
b8f7fb13 | 381 | return cpu; |
485f07d3 | 382 | } |
b8f7fb13 CW |
383 | return -1; |
384 | } | |
385 | ||
386 | /* | |
387 | * Last resort when we get a large number of destination timeouts is | |
388 | * to clear resources held by a given cpu. | |
389 | * Do this with IPI so that all messages in the BAU message queue | |
f073cc8f | 390 | * can be identified by their nonzero swack_vec field. |
1812924b | 391 | * |
b8f7fb13 CW |
392 | * This is entered for a single cpu on the uvhub. |
393 | * The sender want's this uvhub to free a specific message's | |
f073cc8f | 394 | * swack resources. |
1812924b | 395 | */ |
f073cc8f | 396 | static void do_reset(void *ptr) |
1812924b | 397 | { |
b4c286e6 | 398 | int i; |
f073cc8f CW |
399 | struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id()); |
400 | struct reset_args *rap = (struct reset_args *)ptr; | |
401 | struct bau_pq_entry *msg; | |
402 | struct ptc_stats *stat = bcp->statp; | |
1812924b | 403 | |
b8f7fb13 | 404 | stat->d_resets++; |
b8f7fb13 CW |
405 | /* |
406 | * We're looking for the given sender, and | |
f073cc8f | 407 | * will free its swack resource. |
b8f7fb13 CW |
408 | * If all cpu's finally responded after the timeout, its |
409 | * message 'replied_to' was set. | |
410 | */ | |
f073cc8f CW |
411 | for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) { |
412 | unsigned long msg_res; | |
413 | /* do_reset: same conditions for cancellation as | |
414 | bau_process_retry_msg() */ | |
b8f7fb13 CW |
415 | if ((msg->replied_to == 0) && |
416 | (msg->canceled == 0) && | |
417 | (msg->sending_cpu == rap->sender) && | |
f073cc8f | 418 | (msg->swack_vec) && |
b8f7fb13 | 419 | (msg->msg_type != MSG_NOOP)) { |
f073cc8f CW |
420 | unsigned long mmr; |
421 | unsigned long mr; | |
b8f7fb13 CW |
422 | /* |
423 | * make everyone else ignore this message | |
424 | */ | |
425 | msg->canceled = 1; | |
b8f7fb13 CW |
426 | /* |
427 | * only reset the resource if it is still pending | |
428 | */ | |
21e3f12f | 429 | mmr = ops.read_l_sw_ack(); |
f073cc8f CW |
430 | msg_res = msg->swack_vec; |
431 | mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; | |
b8f7fb13 CW |
432 | if (mmr & msg_res) { |
433 | stat->d_rcanceled++; | |
21e3f12f | 434 | ops.write_l_sw_ack(mr); |
dc163a41 | 435 | } |
dc163a41 IM |
436 | } |
437 | } | |
b8f7fb13 | 438 | return; |
dc163a41 IM |
439 | } |
440 | ||
441 | /* | |
b8f7fb13 CW |
442 | * Use IPI to get all target uvhubs to release resources held by |
443 | * a given sending cpu number. | |
dc163a41 | 444 | */ |
a456eaab | 445 | static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp) |
dc163a41 | 446 | { |
485f07d3 | 447 | int pnode; |
448 | int apnode; | |
f073cc8f | 449 | int maskbits; |
485f07d3 | 450 | int sender = bcp->cpu; |
442d3924 | 451 | cpumask_t *mask = bcp->uvhub_master->cpumask; |
485f07d3 | 452 | struct bau_control *smaster = bcp->socket_master; |
b8f7fb13 | 453 | struct reset_args reset_args; |
dc163a41 | 454 | |
b8f7fb13 | 455 | reset_args.sender = sender; |
020b37ac | 456 | cpumask_clear(mask); |
b8f7fb13 | 457 | /* find a single cpu for each uvhub in this distribution mask */ |
a456eaab | 458 | maskbits = sizeof(struct pnmask) * BITSPERBYTE; |
485f07d3 | 459 | /* each bit is a pnode relative to the partition base pnode */ |
460 | for (pnode = 0; pnode < maskbits; pnode++) { | |
f073cc8f | 461 | int cpu; |
485f07d3 | 462 | if (!bau_uvhub_isset(pnode, distribution)) |
b194b120 | 463 | continue; |
485f07d3 | 464 | apnode = pnode + bcp->partition_base_pnode; |
465 | cpu = pnode_to_first_cpu(apnode, smaster); | |
020b37ac | 466 | cpumask_set_cpu(cpu, mask); |
1812924b | 467 | } |
f073cc8f CW |
468 | |
469 | /* IPI all cpus; preemption is already disabled */ | |
442d3924 | 470 | smp_call_function_many(mask, do_reset, (void *)&reset_args, 1); |
b8f7fb13 CW |
471 | return; |
472 | } | |
473 | ||
20d1c86a PZ |
474 | /* |
475 | * Not to be confused with cycles_2_ns() from tsc.c; this gives a relative | |
476 | * number, not an absolute. It converts a duration in cycles to a duration in | |
477 | * ns. | |
478 | */ | |
479 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) | |
b8f7fb13 | 480 | { |
20d1c86a | 481 | struct cyc2ns_data *data = cyc2ns_read_begin(); |
b8f7fb13 | 482 | unsigned long long ns; |
f073cc8f | 483 | |
20d1c86a PZ |
484 | ns = mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift); |
485 | ||
486 | cyc2ns_read_end(data); | |
487 | return ns; | |
488 | } | |
489 | ||
490 | /* | |
491 | * The reverse of the above; converts a duration in ns to a duration in cycles. | |
a26fd719 | 492 | */ |
20d1c86a PZ |
493 | static inline unsigned long long ns_2_cycles(unsigned long long ns) |
494 | { | |
495 | struct cyc2ns_data *data = cyc2ns_read_begin(); | |
496 | unsigned long long cyc; | |
497 | ||
498 | cyc = (ns << data->cyc2ns_shift) / data->cyc2ns_mul; | |
499 | ||
500 | cyc2ns_read_end(data); | |
501 | return cyc; | |
502 | } | |
503 | ||
504 | static inline unsigned long cycles_2_us(unsigned long long cyc) | |
505 | { | |
506 | return cycles_2_ns(cyc) / NSEC_PER_USEC; | |
507 | } | |
508 | ||
509 | static inline cycles_t sec_2_cycles(unsigned long sec) | |
510 | { | |
511 | return ns_2_cycles(sec * NSEC_PER_SEC); | |
512 | } | |
513 | ||
514 | static inline unsigned long long usec_2_cycles(unsigned long usec) | |
515 | { | |
516 | return ns_2_cycles(usec * NSEC_PER_USEC); | |
1812924b CW |
517 | } |
518 | ||
b194b120 | 519 | /* |
b8f7fb13 CW |
520 | * wait for all cpus on this hub to finish their sends and go quiet |
521 | * leaves uvhub_quiesce set so that no new broadcasts are started by | |
522 | * bau_flush_send_and_wait() | |
523 | */ | |
f073cc8f | 524 | static inline void quiesce_local_uvhub(struct bau_control *hmaster) |
b8f7fb13 | 525 | { |
f073cc8f | 526 | atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce); |
b8f7fb13 CW |
527 | } |
528 | ||
529 | /* | |
530 | * mark this quiet-requestor as done | |
531 | */ | |
f073cc8f | 532 | static inline void end_uvhub_quiesce(struct bau_control *hmaster) |
b8f7fb13 | 533 | { |
f073cc8f CW |
534 | atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce); |
535 | } | |
536 | ||
537 | static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift) | |
538 | { | |
539 | unsigned long descriptor_status; | |
540 | ||
541 | descriptor_status = uv_read_local_mmr(mmr_offset); | |
542 | descriptor_status >>= right_shift; | |
543 | descriptor_status &= UV_ACT_STATUS_MASK; | |
544 | return descriptor_status; | |
b8f7fb13 CW |
545 | } |
546 | ||
547 | /* | |
548 | * Wait for completion of a broadcast software ack message | |
549 | * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP | |
b194b120 | 550 | */ |
2a919596 | 551 | static int uv1_wait_completion(struct bau_desc *bau_desc, |
f073cc8f CW |
552 | unsigned long mmr_offset, int right_shift, |
553 | struct bau_control *bcp, long try) | |
b194b120 | 554 | { |
b194b120 | 555 | unsigned long descriptor_status; |
f073cc8f | 556 | cycles_t ttm; |
712157aa | 557 | struct ptc_stats *stat = bcp->statp; |
b194b120 | 558 | |
f073cc8f | 559 | descriptor_status = uv1_read_status(mmr_offset, right_shift); |
b8f7fb13 | 560 | /* spin on the status MMR, waiting for it to go idle */ |
f073cc8f | 561 | while ((descriptor_status != DS_IDLE)) { |
b194b120 | 562 | /* |
2a919596 JS |
563 | * Our software ack messages may be blocked because |
564 | * there are no swack resources available. As long | |
565 | * as none of them has timed out hardware will NACK | |
566 | * our message and its state will stay IDLE. | |
b194b120 | 567 | */ |
f073cc8f | 568 | if (descriptor_status == DS_SOURCE_TIMEOUT) { |
b8f7fb13 CW |
569 | stat->s_stimeout++; |
570 | return FLUSH_GIVEUP; | |
f073cc8f | 571 | } else if (descriptor_status == DS_DESTINATION_TIMEOUT) { |
2a919596 | 572 | stat->s_dtimeout++; |
f073cc8f | 573 | ttm = get_cycles(); |
2a919596 JS |
574 | |
575 | /* | |
576 | * Our retries may be blocked by all destination | |
577 | * swack resources being consumed, and a timeout | |
578 | * pending. In that case hardware returns the | |
579 | * ERROR that looks like a destination timeout. | |
580 | */ | |
f073cc8f | 581 | if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { |
2a919596 JS |
582 | bcp->conseccompletes = 0; |
583 | return FLUSH_RETRY_PLUGGED; | |
584 | } | |
585 | ||
586 | bcp->conseccompletes = 0; | |
587 | return FLUSH_RETRY_TIMEOUT; | |
588 | } else { | |
589 | /* | |
590 | * descriptor_status is still BUSY | |
591 | */ | |
592 | cpu_relax(); | |
593 | } | |
f073cc8f | 594 | descriptor_status = uv1_read_status(mmr_offset, right_shift); |
2a919596 JS |
595 | } |
596 | bcp->conseccompletes++; | |
597 | return FLUSH_COMPLETE; | |
598 | } | |
599 | ||
f073cc8f | 600 | /* |
8b6e511e CW |
601 | * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register. |
602 | * But not currently used. | |
f073cc8f | 603 | */ |
a26fd719 | 604 | static unsigned long uv2_3_read_status(unsigned long offset, int rshft, int desc) |
2a919596 | 605 | { |
f148b41e | 606 | return ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1; |
f073cc8f CW |
607 | } |
608 | ||
c5d35d39 CW |
609 | /* |
610 | * Return whether the status of the descriptor that is normally used for this | |
611 | * cpu (the one indexed by its hub-relative cpu number) is busy. | |
612 | * The status of the original 32 descriptors is always reflected in the 64 | |
613 | * bits of UVH_LB_BAU_SB_ACTIVATION_STATUS_0. | |
614 | * The bit provided by the activation_status_2 register is irrelevant to | |
615 | * the status if it is only being tested for busy or not busy. | |
616 | */ | |
617 | int normal_busy(struct bau_control *bcp) | |
618 | { | |
619 | int cpu = bcp->uvhub_cpu; | |
620 | int mmr_offset; | |
621 | int right_shift; | |
622 | ||
623 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; | |
624 | right_shift = cpu * UV_ACT_STATUS_SIZE; | |
625 | return (((((read_lmmr(mmr_offset) >> right_shift) & | |
626 | UV_ACT_STATUS_MASK)) << 1) == UV2H_DESC_BUSY); | |
627 | } | |
628 | ||
629 | /* | |
630 | * Entered when a bau descriptor has gone into a permanent busy wait because | |
631 | * of a hardware bug. | |
632 | * Workaround the bug. | |
633 | */ | |
634 | int handle_uv2_busy(struct bau_control *bcp) | |
635 | { | |
c5d35d39 | 636 | struct ptc_stats *stat = bcp->statp; |
c5d35d39 CW |
637 | |
638 | stat->s_uv2_wars++; | |
8b6e511e CW |
639 | bcp->busy = 1; |
640 | return FLUSH_GIVEUP; | |
c5d35d39 CW |
641 | } |
642 | ||
a26fd719 | 643 | static int uv2_3_wait_completion(struct bau_desc *bau_desc, |
f073cc8f CW |
644 | unsigned long mmr_offset, int right_shift, |
645 | struct bau_control *bcp, long try) | |
646 | { | |
647 | unsigned long descriptor_stat; | |
648 | cycles_t ttm; | |
8b6e511e | 649 | int desc = bcp->uvhub_cpu; |
c5d35d39 | 650 | long busy_reps = 0; |
2a919596 JS |
651 | struct ptc_stats *stat = bcp->statp; |
652 | ||
a26fd719 | 653 | descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc); |
f073cc8f | 654 | |
2a919596 | 655 | /* spin on the status MMR, waiting for it to go idle */ |
f073cc8f | 656 | while (descriptor_stat != UV2H_DESC_IDLE) { |
8b6e511e CW |
657 | if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT)) { |
658 | /* | |
659 | * A h/w bug on the destination side may | |
660 | * have prevented the message being marked | |
661 | * pending, thus it doesn't get replied to | |
662 | * and gets continually nacked until it times | |
663 | * out with a SOURCE_TIMEOUT. | |
664 | */ | |
2a919596 JS |
665 | stat->s_stimeout++; |
666 | return FLUSH_GIVEUP; | |
f073cc8f | 667 | } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) { |
8b6e511e CW |
668 | ttm = get_cycles(); |
669 | ||
670 | /* | |
671 | * Our retries may be blocked by all destination | |
672 | * swack resources being consumed, and a timeout | |
673 | * pending. In that case hardware returns the | |
674 | * ERROR that looks like a destination timeout. | |
675 | * Without using the extended status we have to | |
676 | * deduce from the short time that this was a | |
677 | * strong nack. | |
678 | */ | |
679 | if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { | |
680 | bcp->conseccompletes = 0; | |
681 | stat->s_plugged++; | |
682 | /* FLUSH_RETRY_PLUGGED causes hang on boot */ | |
683 | return FLUSH_GIVEUP; | |
684 | } | |
b8f7fb13 | 685 | stat->s_dtimeout++; |
b8f7fb13 | 686 | bcp->conseccompletes = 0; |
8b6e511e CW |
687 | /* FLUSH_RETRY_TIMEOUT causes hang on boot */ |
688 | return FLUSH_GIVEUP; | |
b8f7fb13 | 689 | } else { |
c5d35d39 CW |
690 | busy_reps++; |
691 | if (busy_reps > 1000000) { | |
692 | /* not to hammer on the clock */ | |
693 | busy_reps = 0; | |
694 | ttm = get_cycles(); | |
a26fd719 | 695 | if ((ttm - bcp->send_message) > bcp->timeout_interval) |
c5d35d39 | 696 | return handle_uv2_busy(bcp); |
c5d35d39 | 697 | } |
b8f7fb13 | 698 | /* |
f073cc8f | 699 | * descriptor_stat is still BUSY |
b8f7fb13 CW |
700 | */ |
701 | cpu_relax(); | |
b194b120 | 702 | } |
a26fd719 | 703 | descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc); |
b194b120 | 704 | } |
b8f7fb13 | 705 | bcp->conseccompletes++; |
b194b120 CW |
706 | return FLUSH_COMPLETE; |
707 | } | |
708 | ||
f073cc8f CW |
709 | /* |
710 | * There are 2 status registers; each and array[32] of 2 bits. Set up for | |
711 | * which register to read and position in that register based on cpu in | |
712 | * current hub. | |
713 | */ | |
a26fd719 | 714 | static int wait_completion(struct bau_desc *bau_desc, struct bau_control *bcp, long try) |
2a919596 | 715 | { |
f073cc8f CW |
716 | int right_shift; |
717 | unsigned long mmr_offset; | |
8b6e511e | 718 | int desc = bcp->uvhub_cpu; |
f073cc8f | 719 | |
c5d35d39 | 720 | if (desc < UV_CPUS_PER_AS) { |
f073cc8f | 721 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; |
c5d35d39 | 722 | right_shift = desc * UV_ACT_STATUS_SIZE; |
f073cc8f CW |
723 | } else { |
724 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; | |
c5d35d39 | 725 | right_shift = ((desc - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE); |
f073cc8f CW |
726 | } |
727 | ||
da87c937 | 728 | if (bcp->uvhub_version == 1) |
a26fd719 | 729 | return uv1_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try); |
2a919596 | 730 | else |
a26fd719 | 731 | return uv2_3_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try); |
2a919596 JS |
732 | } |
733 | ||
b8f7fb13 | 734 | /* |
f073cc8f | 735 | * Our retries are blocked by all destination sw ack resources being |
f6d8a566 CW |
736 | * in use, and a timeout is pending. In that case hardware immediately |
737 | * returns the ERROR that looks like a destination timeout. | |
738 | */ | |
f073cc8f CW |
739 | static void destination_plugged(struct bau_desc *bau_desc, |
740 | struct bau_control *bcp, | |
f6d8a566 CW |
741 | struct bau_control *hmaster, struct ptc_stats *stat) |
742 | { | |
743 | udelay(bcp->plugged_delay); | |
744 | bcp->plugged_tries++; | |
f073cc8f | 745 | |
f6d8a566 CW |
746 | if (bcp->plugged_tries >= bcp->plugsb4reset) { |
747 | bcp->plugged_tries = 0; | |
f073cc8f | 748 | |
f6d8a566 | 749 | quiesce_local_uvhub(hmaster); |
f073cc8f | 750 | |
f6d8a566 | 751 | spin_lock(&hmaster->queue_lock); |
485f07d3 | 752 | reset_with_ipi(&bau_desc->distribution, bcp); |
f6d8a566 | 753 | spin_unlock(&hmaster->queue_lock); |
f073cc8f | 754 | |
f6d8a566 | 755 | end_uvhub_quiesce(hmaster); |
f073cc8f | 756 | |
f6d8a566 CW |
757 | bcp->ipi_attempts++; |
758 | stat->s_resets_plug++; | |
759 | } | |
760 | } | |
761 | ||
f073cc8f CW |
762 | static void destination_timeout(struct bau_desc *bau_desc, |
763 | struct bau_control *bcp, struct bau_control *hmaster, | |
764 | struct ptc_stats *stat) | |
f6d8a566 | 765 | { |
f073cc8f | 766 | hmaster->max_concurr = 1; |
f6d8a566 CW |
767 | bcp->timeout_tries++; |
768 | if (bcp->timeout_tries >= bcp->timeoutsb4reset) { | |
769 | bcp->timeout_tries = 0; | |
f073cc8f | 770 | |
f6d8a566 | 771 | quiesce_local_uvhub(hmaster); |
f073cc8f | 772 | |
f6d8a566 | 773 | spin_lock(&hmaster->queue_lock); |
485f07d3 | 774 | reset_with_ipi(&bau_desc->distribution, bcp); |
f6d8a566 | 775 | spin_unlock(&hmaster->queue_lock); |
f073cc8f | 776 | |
f6d8a566 | 777 | end_uvhub_quiesce(hmaster); |
f073cc8f | 778 | |
f6d8a566 CW |
779 | bcp->ipi_attempts++; |
780 | stat->s_resets_timeout++; | |
781 | } | |
782 | } | |
783 | ||
50fb55ac | 784 | /* |
8b6e511e CW |
785 | * Stop all cpus on a uvhub from using the BAU for a period of time. |
786 | * This is reversed by check_enable. | |
50fb55ac | 787 | */ |
8b6e511e | 788 | static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat) |
50fb55ac | 789 | { |
8b6e511e CW |
790 | int tcpu; |
791 | struct bau_control *tbcp; | |
792 | struct bau_control *hmaster; | |
793 | cycles_t tm1; | |
794 | ||
795 | hmaster = bcp->uvhub_master; | |
796 | spin_lock(&hmaster->disable_lock); | |
797 | if (!bcp->baudisabled) { | |
50fb55ac | 798 | stat->s_bau_disabled++; |
8b6e511e | 799 | tm1 = get_cycles(); |
50fb55ac CW |
800 | for_each_present_cpu(tcpu) { |
801 | tbcp = &per_cpu(bau_control, tcpu); | |
8b6e511e CW |
802 | if (tbcp->uvhub_master == hmaster) { |
803 | tbcp->baudisabled = 1; | |
804 | tbcp->set_bau_on_time = | |
805 | tm1 + bcp->disabled_period; | |
806 | } | |
50fb55ac CW |
807 | } |
808 | } | |
8b6e511e | 809 | spin_unlock(&hmaster->disable_lock); |
50fb55ac CW |
810 | } |
811 | ||
f073cc8f CW |
812 | static void count_max_concurr(int stat, struct bau_control *bcp, |
813 | struct bau_control *hmaster) | |
814 | { | |
815 | bcp->plugged_tries = 0; | |
816 | bcp->timeout_tries = 0; | |
817 | if (stat != FLUSH_COMPLETE) | |
818 | return; | |
819 | if (bcp->conseccompletes <= bcp->complete_threshold) | |
820 | return; | |
821 | if (hmaster->max_concurr >= hmaster->max_concurr_const) | |
822 | return; | |
823 | hmaster->max_concurr++; | |
824 | } | |
825 | ||
826 | static void record_send_stats(cycles_t time1, cycles_t time2, | |
827 | struct bau_control *bcp, struct ptc_stats *stat, | |
828 | int completion_status, int try) | |
829 | { | |
830 | cycles_t elapsed; | |
831 | ||
832 | if (time2 > time1) { | |
833 | elapsed = time2 - time1; | |
834 | stat->s_time += elapsed; | |
835 | ||
836 | if ((completion_status == FLUSH_COMPLETE) && (try == 1)) { | |
837 | bcp->period_requests++; | |
838 | bcp->period_time += elapsed; | |
839 | if ((elapsed > congested_cycles) && | |
8b6e511e CW |
840 | (bcp->period_requests > bcp->cong_reps) && |
841 | ((bcp->period_time / bcp->period_requests) > | |
842 | congested_cycles)) { | |
843 | stat->s_congested++; | |
844 | disable_for_period(bcp, stat); | |
845 | } | |
f073cc8f CW |
846 | } |
847 | } else | |
848 | stat->s_requestor--; | |
849 | ||
850 | if (completion_status == FLUSH_COMPLETE && try > 1) | |
851 | stat->s_retriesok++; | |
8b6e511e | 852 | else if (completion_status == FLUSH_GIVEUP) { |
f073cc8f | 853 | stat->s_giveup++; |
8b6e511e CW |
854 | if (get_cycles() > bcp->period_end) |
855 | bcp->period_giveups = 0; | |
856 | bcp->period_giveups++; | |
857 | if (bcp->period_giveups == 1) | |
858 | bcp->period_end = get_cycles() + bcp->disabled_period; | |
859 | if (bcp->period_giveups > bcp->giveup_limit) { | |
860 | disable_for_period(bcp, stat); | |
861 | stat->s_giveuplimit++; | |
862 | } | |
863 | } | |
f073cc8f CW |
864 | } |
865 | ||
866 | /* | |
867 | * Because of a uv1 hardware bug only a limited number of concurrent | |
868 | * requests can be made. | |
869 | */ | |
870 | static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat) | |
871 | { | |
872 | spinlock_t *lock = &hmaster->uvhub_lock; | |
873 | atomic_t *v; | |
874 | ||
875 | v = &hmaster->active_descriptor_count; | |
876 | if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) { | |
877 | stat->s_throttles++; | |
878 | do { | |
879 | cpu_relax(); | |
880 | } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)); | |
881 | } | |
882 | } | |
883 | ||
884 | /* | |
885 | * Handle the completion status of a message send. | |
886 | */ | |
887 | static void handle_cmplt(int completion_status, struct bau_desc *bau_desc, | |
888 | struct bau_control *bcp, struct bau_control *hmaster, | |
889 | struct ptc_stats *stat) | |
890 | { | |
891 | if (completion_status == FLUSH_RETRY_PLUGGED) | |
892 | destination_plugged(bau_desc, bcp, hmaster, stat); | |
893 | else if (completion_status == FLUSH_RETRY_TIMEOUT) | |
894 | destination_timeout(bau_desc, bcp, hmaster, stat); | |
895 | } | |
896 | ||
897 | /* | |
b8f7fb13 | 898 | * Send a broadcast and wait for it to complete. |
b194b120 | 899 | * |
f6d8a566 | 900 | * The flush_mask contains the cpus the broadcast is to be sent to including |
b8f7fb13 | 901 | * cpus that are on the local uvhub. |
b194b120 | 902 | * |
450a007e CW |
903 | * Returns 0 if all flushing represented in the mask was done. |
904 | * Returns 1 if it gives up entirely and the original cpu mask is to be | |
905 | * returned to the kernel. | |
b194b120 | 906 | */ |
8b6e511e CW |
907 | int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp, |
908 | struct bau_desc *bau_desc) | |
b194b120 | 909 | { |
b8f7fb13 | 910 | int seq_number = 0; |
f073cc8f | 911 | int completion_stat = 0; |
da87c937 | 912 | int uv1 = 0; |
b8f7fb13 | 913 | long try = 0; |
b4c286e6 | 914 | unsigned long index; |
b194b120 CW |
915 | cycles_t time1; |
916 | cycles_t time2; | |
712157aa | 917 | struct ptc_stats *stat = bcp->statp; |
b8f7fb13 | 918 | struct bau_control *hmaster = bcp->uvhub_master; |
da87c937 | 919 | struct uv1_bau_msg_header *uv1_hdr = NULL; |
a26fd719 | 920 | struct uv2_3_bau_msg_header *uv2_3_hdr = NULL; |
b8f7fb13 | 921 | |
8b6e511e CW |
922 | if (bcp->uvhub_version == 1) { |
923 | uv1 = 1; | |
f073cc8f | 924 | uv1_throttle(hmaster, stat); |
8b6e511e | 925 | } |
f073cc8f | 926 | |
b8f7fb13 CW |
927 | while (hmaster->uvhub_quiesce) |
928 | cpu_relax(); | |
b194b120 | 929 | |
b194b120 | 930 | time1 = get_cycles(); |
8b6e511e CW |
931 | if (uv1) |
932 | uv1_hdr = &bau_desc->header.uv1_hdr; | |
933 | else | |
a26fd719 CW |
934 | /* uv2 and uv3 */ |
935 | uv2_3_hdr = &bau_desc->header.uv2_3_hdr; | |
8b6e511e | 936 | |
b194b120 | 937 | do { |
8b6e511e | 938 | if (try == 0) { |
da87c937 CW |
939 | if (uv1) |
940 | uv1_hdr->msg_type = MSG_REGULAR; | |
941 | else | |
a26fd719 | 942 | uv2_3_hdr->msg_type = MSG_REGULAR; |
b8f7fb13 CW |
943 | seq_number = bcp->message_number++; |
944 | } else { | |
da87c937 CW |
945 | if (uv1) |
946 | uv1_hdr->msg_type = MSG_RETRY; | |
947 | else | |
a26fd719 | 948 | uv2_3_hdr->msg_type = MSG_RETRY; |
b8f7fb13 CW |
949 | stat->s_retry_messages++; |
950 | } | |
f073cc8f | 951 | |
da87c937 CW |
952 | if (uv1) |
953 | uv1_hdr->sequence = seq_number; | |
954 | else | |
a26fd719 | 955 | uv2_3_hdr->sequence = seq_number; |
8b6e511e | 956 | index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu; |
b8f7fb13 | 957 | bcp->send_message = get_cycles(); |
f073cc8f CW |
958 | |
959 | write_mmr_activation(index); | |
960 | ||
b8f7fb13 | 961 | try++; |
f073cc8f CW |
962 | completion_stat = wait_completion(bau_desc, bcp, try); |
963 | ||
964 | handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat); | |
b8f7fb13 | 965 | |
e8e5e8a8 | 966 | if (bcp->ipi_attempts >= bcp->ipi_reset_limit) { |
b8f7fb13 | 967 | bcp->ipi_attempts = 0; |
8b6e511e | 968 | stat->s_overipilimit++; |
f073cc8f | 969 | completion_stat = FLUSH_GIVEUP; |
b8f7fb13 CW |
970 | break; |
971 | } | |
972 | cpu_relax(); | |
f073cc8f CW |
973 | } while ((completion_stat == FLUSH_RETRY_PLUGGED) || |
974 | (completion_stat == FLUSH_RETRY_TIMEOUT)); | |
975 | ||
b194b120 | 976 | time2 = get_cycles(); |
f073cc8f CW |
977 | |
978 | count_max_concurr(completion_stat, bcp, hmaster); | |
979 | ||
b8f7fb13 CW |
980 | while (hmaster->uvhub_quiesce) |
981 | cpu_relax(); | |
f073cc8f | 982 | |
b8f7fb13 | 983 | atomic_dec(&hmaster->active_descriptor_count); |
f073cc8f CW |
984 | |
985 | record_send_stats(time1, time2, bcp, stat, completion_stat, try); | |
986 | ||
987 | if (completion_stat == FLUSH_GIVEUP) | |
c5d35d39 | 988 | /* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */ |
f073cc8f CW |
989 | return 1; |
990 | return 0; | |
991 | } | |
992 | ||
993 | /* | |
8b6e511e CW |
994 | * The BAU is disabled for this uvhub. When the disabled time period has |
995 | * expired re-enable it. | |
996 | * Return 0 if it is re-enabled for all cpus on this uvhub. | |
f073cc8f CW |
997 | */ |
998 | static int check_enable(struct bau_control *bcp, struct ptc_stats *stat) | |
999 | { | |
1000 | int tcpu; | |
1001 | struct bau_control *tbcp; | |
8b6e511e | 1002 | struct bau_control *hmaster; |
f073cc8f | 1003 | |
8b6e511e CW |
1004 | hmaster = bcp->uvhub_master; |
1005 | spin_lock(&hmaster->disable_lock); | |
1006 | if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) { | |
1007 | stat->s_bau_reenabled++; | |
1008 | for_each_present_cpu(tcpu) { | |
1009 | tbcp = &per_cpu(bau_control, tcpu); | |
1010 | if (tbcp->uvhub_master == hmaster) { | |
f073cc8f CW |
1011 | tbcp->baudisabled = 0; |
1012 | tbcp->period_requests = 0; | |
1013 | tbcp->period_time = 0; | |
8b6e511e | 1014 | tbcp->period_giveups = 0; |
50fb55ac CW |
1015 | } |
1016 | } | |
8b6e511e CW |
1017 | spin_unlock(&hmaster->disable_lock); |
1018 | return 0; | |
f073cc8f | 1019 | } |
8b6e511e | 1020 | spin_unlock(&hmaster->disable_lock); |
f073cc8f CW |
1021 | return -1; |
1022 | } | |
1023 | ||
1024 | static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs, | |
1025 | int remotes, struct bau_desc *bau_desc) | |
1026 | { | |
1027 | stat->s_requestor++; | |
1028 | stat->s_ntargcpu += remotes + locals; | |
1029 | stat->s_ntargremotes += remotes; | |
1030 | stat->s_ntarglocals += locals; | |
1031 | ||
1032 | /* uvhub statistics */ | |
1033 | hubs = bau_uvhub_weight(&bau_desc->distribution); | |
1034 | if (locals) { | |
1035 | stat->s_ntarglocaluvhub++; | |
1036 | stat->s_ntargremoteuvhub += (hubs - 1); | |
e8e5e8a8 | 1037 | } else |
f073cc8f CW |
1038 | stat->s_ntargremoteuvhub += hubs; |
1039 | ||
1040 | stat->s_ntarguvhub += hubs; | |
1041 | ||
1042 | if (hubs >= 16) | |
1043 | stat->s_ntarguvhub16++; | |
1044 | else if (hubs >= 8) | |
1045 | stat->s_ntarguvhub8++; | |
1046 | else if (hubs >= 4) | |
1047 | stat->s_ntarguvhub4++; | |
1048 | else if (hubs >= 2) | |
1049 | stat->s_ntarguvhub2++; | |
1050 | else | |
1051 | stat->s_ntarguvhub1++; | |
1052 | } | |
1053 | ||
1054 | /* | |
1055 | * Translate a cpu mask to the uvhub distribution mask in the BAU | |
1056 | * activation descriptor. | |
1057 | */ | |
1058 | static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp, | |
1059 | struct bau_desc *bau_desc, int *localsp, int *remotesp) | |
1060 | { | |
1061 | int cpu; | |
1062 | int pnode; | |
1063 | int cnt = 0; | |
1064 | struct hub_and_pnode *hpp; | |
1065 | ||
1066 | for_each_cpu(cpu, flush_mask) { | |
1067 | /* | |
1068 | * The distribution vector is a bit map of pnodes, relative | |
1069 | * to the partition base pnode (and the partition base nasid | |
1070 | * in the header). | |
1071 | * Translate cpu to pnode and hub using a local memory array. | |
1072 | */ | |
1073 | hpp = &bcp->socket_master->thp[cpu]; | |
1074 | pnode = hpp->pnode - bcp->partition_base_pnode; | |
1075 | bau_uvhub_set(pnode, &bau_desc->distribution); | |
1076 | cnt++; | |
1077 | if (hpp->uvhub == bcp->uvhub) | |
1078 | (*localsp)++; | |
1079 | else | |
1080 | (*remotesp)++; | |
b194b120 | 1081 | } |
f073cc8f CW |
1082 | if (!cnt) |
1083 | return 1; | |
450a007e | 1084 | return 0; |
b194b120 CW |
1085 | } |
1086 | ||
f073cc8f CW |
1087 | /* |
1088 | * globally purge translation cache of a virtual address or all TLB's | |
bdbcdd48 | 1089 | * @cpumask: mask of all cpu's in which the address is to be removed |
1812924b | 1090 | * @mm: mm_struct containing virtual address range |
57c4f430 AS |
1091 | * @start: start virtual address to be removed from TLB |
1092 | * @end: end virtual address to be remove from TLB | |
bdbcdd48 | 1093 | * @cpu: the current cpu |
1812924b CW |
1094 | * |
1095 | * This is the entry point for initiating any UV global TLB shootdown. | |
1096 | * | |
1097 | * Purges the translation caches of all specified processors of the given | |
1098 | * virtual address, or purges all TLB's on specified processors. | |
1099 | * | |
bdbcdd48 TH |
1100 | * The caller has derived the cpumask from the mm_struct. This function |
1101 | * is called only if there are bits set in the mask. (e.g. flush_tlb_page()) | |
1812924b | 1102 | * |
b8f7fb13 CW |
1103 | * The cpumask is converted into a uvhubmask of the uvhubs containing |
1104 | * those cpus. | |
b194b120 | 1105 | * |
bdbcdd48 TH |
1106 | * Note that this function should be called with preemption disabled. |
1107 | * | |
1108 | * Returns NULL if all remote flushing was done. | |
1109 | * Returns pointer to cpumask if some remote flushing remains to be | |
1110 | * done. The returned pointer is valid till preemption is re-enabled. | |
1812924b | 1111 | */ |
bdbcdd48 | 1112 | const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, |
a26fd719 CW |
1113 | struct mm_struct *mm, |
1114 | unsigned long start, | |
1115 | unsigned long end, | |
1116 | unsigned int cpu) | |
1812924b | 1117 | { |
b194b120 | 1118 | int locals = 0; |
450a007e CW |
1119 | int remotes = 0; |
1120 | int hubs = 0; | |
dc163a41 | 1121 | struct bau_desc *bau_desc; |
b8f7fb13 CW |
1122 | struct cpumask *flush_mask; |
1123 | struct ptc_stats *stat; | |
1124 | struct bau_control *bcp; | |
8b6e511e CW |
1125 | unsigned long descriptor_status; |
1126 | unsigned long status; | |
bdbcdd48 | 1127 | |
b8f7fb13 | 1128 | bcp = &per_cpu(bau_control, cpu); |
26ef8577 CW |
1129 | |
1130 | if (bcp->nobau) | |
1131 | return cpumask; | |
50fb55ac | 1132 | |
3eae49ca | 1133 | stat = bcp->statp; |
1134 | stat->s_enters++; | |
1135 | ||
8b6e511e CW |
1136 | if (bcp->busy) { |
1137 | descriptor_status = | |
1138 | read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0); | |
1139 | status = ((descriptor_status >> (bcp->uvhub_cpu * | |
1140 | UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1; | |
1141 | if (status == UV2H_DESC_BUSY) | |
1142 | return cpumask; | |
1143 | bcp->busy = 0; | |
1144 | } | |
1145 | ||
50fb55ac CW |
1146 | /* bau was disabled due to slow response */ |
1147 | if (bcp->baudisabled) { | |
8b6e511e CW |
1148 | if (check_enable(bcp, stat)) { |
1149 | stat->s_ipifordisabled++; | |
f073cc8f | 1150 | return cpumask; |
8b6e511e | 1151 | } |
50fb55ac | 1152 | } |
e8e5e8a8 | 1153 | |
b8f7fb13 CW |
1154 | /* |
1155 | * Each sending cpu has a per-cpu mask which it fills from the caller's | |
450a007e CW |
1156 | * cpu mask. All cpus are converted to uvhubs and copied to the |
1157 | * activation descriptor. | |
b8f7fb13 CW |
1158 | */ |
1159 | flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu); | |
450a007e | 1160 | /* don't actually do a shootdown of the local cpu */ |
b8f7fb13 | 1161 | cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); |
f073cc8f | 1162 | |
020b37ac | 1163 | if (cpumask_test_cpu(cpu, cpumask)) |
450a007e | 1164 | stat->s_ntargself++; |
1812924b | 1165 | |
b8f7fb13 | 1166 | bau_desc = bcp->descriptor_base; |
8b6e511e | 1167 | bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu); |
b8f7fb13 | 1168 | bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); |
f073cc8f | 1169 | if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) |
450a007e | 1170 | return NULL; |
450a007e | 1171 | |
f073cc8f | 1172 | record_send_statistics(stat, locals, hubs, remotes, bau_desc); |
1812924b | 1173 | |
57c4f430 AS |
1174 | if (!end || (end - start) <= PAGE_SIZE) |
1175 | bau_desc->payload.address = start; | |
1176 | else | |
1177 | bau_desc->payload.address = TLB_FLUSH_ALL; | |
bdbcdd48 | 1178 | bau_desc->payload.sending_cpu = cpu; |
b8f7fb13 | 1179 | /* |
450a007e CW |
1180 | * uv_flush_send_and_wait returns 0 if all cpu's were messaged, |
1181 | * or 1 if it gave up and the original cpumask should be returned. | |
b8f7fb13 | 1182 | */ |
8b6e511e | 1183 | if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc)) |
450a007e CW |
1184 | return NULL; |
1185 | else | |
1186 | return cpumask; | |
1812924b CW |
1187 | } |
1188 | ||
c5d35d39 | 1189 | /* |
8b6e511e CW |
1190 | * Search the message queue for any 'other' unprocessed message with the |
1191 | * same software acknowledge resource bit vector as the 'msg' message. | |
c5d35d39 CW |
1192 | */ |
1193 | struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg, | |
8b6e511e | 1194 | struct bau_control *bcp) |
c5d35d39 CW |
1195 | { |
1196 | struct bau_pq_entry *msg_next = msg + 1; | |
8b6e511e | 1197 | unsigned char swack_vec = msg->swack_vec; |
c5d35d39 CW |
1198 | |
1199 | if (msg_next > bcp->queue_last) | |
1200 | msg_next = bcp->queue_first; | |
8b6e511e CW |
1201 | while (msg_next != msg) { |
1202 | if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) && | |
1203 | (msg_next->swack_vec == swack_vec)) | |
c5d35d39 CW |
1204 | return msg_next; |
1205 | msg_next++; | |
1206 | if (msg_next > bcp->queue_last) | |
1207 | msg_next = bcp->queue_first; | |
1208 | } | |
1209 | return NULL; | |
1210 | } | |
1211 | ||
1212 | /* | |
1213 | * UV2 needs to work around a bug in which an arriving message has not | |
1214 | * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register. | |
1215 | * Such a message must be ignored. | |
1216 | */ | |
1217 | void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp) | |
1218 | { | |
1219 | unsigned long mmr_image; | |
1220 | unsigned char swack_vec; | |
1221 | struct bau_pq_entry *msg = mdp->msg; | |
1222 | struct bau_pq_entry *other_msg; | |
1223 | ||
21e3f12f | 1224 | mmr_image = ops.read_l_sw_ack(); |
c5d35d39 CW |
1225 | swack_vec = msg->swack_vec; |
1226 | ||
1227 | if ((swack_vec & mmr_image) == 0) { | |
1228 | /* | |
1229 | * This message was assigned a swack resource, but no | |
1230 | * reserved acknowlegment is pending. | |
1231 | * The bug has prevented this message from setting the MMR. | |
c5d35d39 | 1232 | */ |
c5d35d39 | 1233 | /* |
8b6e511e CW |
1234 | * Some message has set the MMR 'pending' bit; it might have |
1235 | * been another message. Look for that message. | |
c5d35d39 | 1236 | */ |
8b6e511e CW |
1237 | other_msg = find_another_by_swack(msg, bcp); |
1238 | if (other_msg) { | |
1239 | /* | |
1240 | * There is another. Process this one but do not | |
1241 | * ack it. | |
1242 | */ | |
1243 | bau_process_message(mdp, bcp, 0); | |
1244 | /* | |
1245 | * Let the natural processing of that other message | |
1246 | * acknowledge it. Don't get the processing of sw_ack's | |
1247 | * out of order. | |
1248 | */ | |
1249 | return; | |
1250 | } | |
c5d35d39 CW |
1251 | } |
1252 | ||
1253 | /* | |
8b6e511e CW |
1254 | * Either the MMR shows this one pending a reply or there is no |
1255 | * other message using this sw_ack, so it is safe to acknowledge it. | |
c5d35d39 CW |
1256 | */ |
1257 | bau_process_message(mdp, bcp, 1); | |
1258 | ||
1259 | return; | |
1260 | } | |
1261 | ||
1812924b CW |
1262 | /* |
1263 | * The BAU message interrupt comes here. (registered by set_intr_gate) | |
1264 | * See entry_64.S | |
1265 | * | |
1266 | * We received a broadcast assist message. | |
1267 | * | |
b8f7fb13 | 1268 | * Interrupts are disabled; this interrupt could represent |
1812924b CW |
1269 | * the receipt of several messages. |
1270 | * | |
b8f7fb13 CW |
1271 | * All cores/threads on this hub get this interrupt. |
1272 | * The last one to see it does the software ack. | |
1812924b | 1273 | * (the resource will not be freed until noninterruptable cpus see this |
b8f7fb13 | 1274 | * interrupt; hardware may timeout the s/w ack and reply ERROR) |
1812924b | 1275 | */ |
b194b120 | 1276 | void uv_bau_message_interrupt(struct pt_regs *regs) |
1812924b | 1277 | { |
1812924b | 1278 | int count = 0; |
b8f7fb13 | 1279 | cycles_t time_start; |
f073cc8f | 1280 | struct bau_pq_entry *msg; |
b8f7fb13 CW |
1281 | struct bau_control *bcp; |
1282 | struct ptc_stats *stat; | |
1283 | struct msg_desc msgdesc; | |
1284 | ||
88ed9dd7 | 1285 | ack_APIC_irq(); |
b8f7fb13 | 1286 | time_start = get_cycles(); |
f073cc8f | 1287 | |
b8f7fb13 | 1288 | bcp = &per_cpu(bau_control, smp_processor_id()); |
712157aa | 1289 | stat = bcp->statp; |
f073cc8f CW |
1290 | |
1291 | msgdesc.queue_first = bcp->queue_first; | |
1292 | msgdesc.queue_last = bcp->queue_last; | |
1293 | ||
b8f7fb13 | 1294 | msg = bcp->bau_msg_head; |
f073cc8f | 1295 | while (msg->swack_vec) { |
1812924b | 1296 | count++; |
f073cc8f CW |
1297 | |
1298 | msgdesc.msg_slot = msg - msgdesc.queue_first; | |
b8f7fb13 | 1299 | msgdesc.msg = msg; |
c5d35d39 CW |
1300 | if (bcp->uvhub_version == 2) |
1301 | process_uv2_message(&msgdesc, bcp); | |
1302 | else | |
a26fd719 | 1303 | /* no error workaround for uv1 or uv3 */ |
c5d35d39 | 1304 | bau_process_message(&msgdesc, bcp, 1); |
f073cc8f | 1305 | |
1812924b | 1306 | msg++; |
f073cc8f CW |
1307 | if (msg > msgdesc.queue_last) |
1308 | msg = msgdesc.queue_first; | |
b8f7fb13 | 1309 | bcp->bau_msg_head = msg; |
1812924b | 1310 | } |
b8f7fb13 | 1311 | stat->d_time += (get_cycles() - time_start); |
1812924b | 1312 | if (!count) |
b8f7fb13 | 1313 | stat->d_nomsg++; |
1812924b | 1314 | else if (count > 1) |
b8f7fb13 | 1315 | stat->d_multmsg++; |
1812924b CW |
1316 | } |
1317 | ||
c4c4688f | 1318 | /* |
f073cc8f | 1319 | * Each target uvhub (i.e. a uvhub that has cpu's) needs to have |
c4c4688f CW |
1320 | * shootdown message timeouts enabled. The timeout does not cause |
1321 | * an interrupt, but causes an error message to be returned to | |
1322 | * the sender. | |
1323 | */ | |
f073cc8f | 1324 | static void __init enable_timeouts(void) |
1812924b | 1325 | { |
b8f7fb13 CW |
1326 | int uvhub; |
1327 | int nuvhubs; | |
1812924b | 1328 | int pnode; |
c4c4688f | 1329 | unsigned long mmr_image; |
1812924b | 1330 | |
b8f7fb13 | 1331 | nuvhubs = uv_num_possible_blades(); |
1812924b | 1332 | |
b8f7fb13 CW |
1333 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
1334 | if (!uv_blade_nr_possible_cpus(uvhub)) | |
1812924b | 1335 | continue; |
c4c4688f | 1336 | |
b8f7fb13 | 1337 | pnode = uv_blade_to_pnode(uvhub); |
f073cc8f | 1338 | mmr_image = read_mmr_misc_control(pnode); |
c4c4688f CW |
1339 | /* |
1340 | * Set the timeout period and then lock it in, in three | |
1341 | * steps; captures and locks in the period. | |
1342 | * | |
1343 | * To program the period, the SOFT_ACK_MODE must be off. | |
1344 | */ | |
f073cc8f CW |
1345 | mmr_image &= ~(1L << SOFTACK_MSHIFT); |
1346 | write_mmr_misc_control(pnode, mmr_image); | |
c4c4688f CW |
1347 | /* |
1348 | * Set the 4-bit period. | |
1349 | */ | |
f073cc8f CW |
1350 | mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT); |
1351 | mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT); | |
1352 | write_mmr_misc_control(pnode, mmr_image); | |
c4c4688f | 1353 | /* |
2a919596 | 1354 | * UV1: |
c4c4688f CW |
1355 | * Subsequent reversals of the timebase bit (3) cause an |
1356 | * immediate timeout of one or all INTD resources as | |
1357 | * indicated in bits 2:0 (7 causes all of them to timeout). | |
1358 | */ | |
f073cc8f | 1359 | mmr_image |= (1L << SOFTACK_MSHIFT); |
2a919596 | 1360 | if (is_uv2_hub()) { |
a26fd719 | 1361 | /* do not touch the legacy mode bit */ |
8b6e511e CW |
1362 | /* hw bug workaround; do not use extended status */ |
1363 | mmr_image &= ~(1L << UV2_EXT_SHFT); | |
a26fd719 CW |
1364 | } else if (is_uv3_hub()) { |
1365 | mmr_image &= ~(1L << PREFETCH_HINT_SHFT); | |
1366 | mmr_image |= (1L << SB_STATUS_SHFT); | |
2a919596 | 1367 | } |
f073cc8f | 1368 | write_mmr_misc_control(pnode, mmr_image); |
1812924b | 1369 | } |
1812924b CW |
1370 | } |
1371 | ||
f073cc8f | 1372 | static void *ptc_seq_start(struct seq_file *file, loff_t *offset) |
1812924b CW |
1373 | { |
1374 | if (*offset < num_possible_cpus()) | |
1375 | return offset; | |
1376 | return NULL; | |
1377 | } | |
1378 | ||
f073cc8f | 1379 | static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset) |
1812924b CW |
1380 | { |
1381 | (*offset)++; | |
1382 | if (*offset < num_possible_cpus()) | |
1383 | return offset; | |
1384 | return NULL; | |
1385 | } | |
1386 | ||
f073cc8f | 1387 | static void ptc_seq_stop(struct seq_file *file, void *data) |
1812924b CW |
1388 | { |
1389 | } | |
1390 | ||
1391 | /* | |
f073cc8f | 1392 | * Display the statistics thru /proc/sgi_uv/ptc_statistics |
b8f7fb13 | 1393 | * 'data' points to the cpu number |
f073cc8f | 1394 | * Note: see the descriptions in stat_description[]. |
1812924b | 1395 | */ |
f073cc8f | 1396 | static int ptc_seq_show(struct seq_file *file, void *data) |
1812924b CW |
1397 | { |
1398 | struct ptc_stats *stat; | |
26ef8577 | 1399 | struct bau_control *bcp; |
1812924b CW |
1400 | int cpu; |
1401 | ||
1402 | cpu = *(loff_t *)data; | |
1812924b | 1403 | if (!cpu) { |
3736708f RV |
1404 | seq_puts(file, |
1405 | "# cpu bauoff sent stime self locals remotes ncpus localhub "); | |
1406 | seq_puts(file, "remotehub numuvhubs numuvhubs16 numuvhubs8 "); | |
1407 | seq_puts(file, | |
1408 | "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries "); | |
1409 | seq_puts(file, | |
1410 | "rok resetp resett giveup sto bz throt disable "); | |
1411 | seq_puts(file, | |
1412 | "enable wars warshw warwaits enters ipidis plugged "); | |
1413 | seq_puts(file, | |
1414 | "ipiover glim cong swack recv rtime all one mult "); | |
1415 | seq_puts(file, "none retry canc nocan reset rcan\n"); | |
1812924b CW |
1416 | } |
1417 | if (cpu < num_possible_cpus() && cpu_online(cpu)) { | |
26ef8577 | 1418 | bcp = &per_cpu(bau_control, cpu); |
fa2a79ce JC |
1419 | if (bcp->nobau) { |
1420 | seq_printf(file, "cpu %d bau disabled\n", cpu); | |
1421 | return 0; | |
1422 | } | |
26ef8577 | 1423 | stat = bcp->statp; |
b8f7fb13 CW |
1424 | /* source side statistics */ |
1425 | seq_printf(file, | |
8b6e511e | 1426 | "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", |
26ef8577 CW |
1427 | cpu, bcp->nobau, stat->s_requestor, |
1428 | cycles_2_us(stat->s_time), | |
450a007e CW |
1429 | stat->s_ntargself, stat->s_ntarglocals, |
1430 | stat->s_ntargremotes, stat->s_ntargcpu, | |
1431 | stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub, | |
1432 | stat->s_ntarguvhub, stat->s_ntarguvhub16); | |
b54bd9be | 1433 | seq_printf(file, "%ld %ld %ld %ld %ld %ld ", |
b8f7fb13 CW |
1434 | stat->s_ntarguvhub8, stat->s_ntarguvhub4, |
1435 | stat->s_ntarguvhub2, stat->s_ntarguvhub1, | |
b54bd9be | 1436 | stat->s_dtimeout, stat->s_strongnacks); |
8b6e511e | 1437 | seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ", |
b8f7fb13 CW |
1438 | stat->s_retry_messages, stat->s_retriesok, |
1439 | stat->s_resets_plug, stat->s_resets_timeout, | |
1440 | stat->s_giveup, stat->s_stimeout, | |
8b6e511e CW |
1441 | stat->s_busy, stat->s_throttles); |
1442 | seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", | |
1443 | stat->s_bau_disabled, stat->s_bau_reenabled, | |
1444 | stat->s_uv2_wars, stat->s_uv2_wars_hw, | |
1445 | stat->s_uv2_war_waits, stat->s_enters, | |
1446 | stat->s_ipifordisabled, stat->s_plugged, | |
1447 | stat->s_overipilimit, stat->s_giveuplimit, | |
1448 | stat->s_congested); | |
e8e5e8a8 | 1449 | |
b8f7fb13 CW |
1450 | /* destination side statistics */ |
1451 | seq_printf(file, | |
8b6e511e | 1452 | "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", |
21e3f12f | 1453 | ops.read_g_sw_ack(uv_cpu_to_pnode(cpu)), |
b8f7fb13 CW |
1454 | stat->d_requestee, cycles_2_us(stat->d_time), |
1455 | stat->d_alltlb, stat->d_onetlb, stat->d_multmsg, | |
1456 | stat->d_nomsg, stat->d_retries, stat->d_canceled, | |
1457 | stat->d_nocanceled, stat->d_resets, | |
1458 | stat->d_rcanceled); | |
1812924b | 1459 | } |
1812924b CW |
1460 | return 0; |
1461 | } | |
1462 | ||
e8e5e8a8 CW |
1463 | /* |
1464 | * Display the tunables thru debugfs | |
1465 | */ | |
1466 | static ssize_t tunables_read(struct file *file, char __user *userbuf, | |
f073cc8f | 1467 | size_t count, loff_t *ppos) |
e8e5e8a8 | 1468 | { |
b365a85c | 1469 | char *buf; |
e8e5e8a8 CW |
1470 | int ret; |
1471 | ||
8b6e511e CW |
1472 | buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n", |
1473 | "max_concur plugged_delay plugsb4reset timeoutsb4reset", | |
1474 | "ipi_reset_limit complete_threshold congested_response_us", | |
1475 | "congested_reps disabled_period giveup_limit", | |
f073cc8f | 1476 | max_concurr, plugged_delay, plugsb4reset, |
e8e5e8a8 | 1477 | timeoutsb4reset, ipi_reset_limit, complete_threshold, |
8b6e511e CW |
1478 | congested_respns_us, congested_reps, disabled_period, |
1479 | giveup_limit); | |
e8e5e8a8 | 1480 | |
b365a85c DC |
1481 | if (!buf) |
1482 | return -ENOMEM; | |
1483 | ||
1484 | ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); | |
1485 | kfree(buf); | |
1486 | return ret; | |
e8e5e8a8 CW |
1487 | } |
1488 | ||
1812924b | 1489 | /* |
f073cc8f CW |
1490 | * handle a write to /proc/sgi_uv/ptc_statistics |
1491 | * -1: reset the statistics | |
1812924b | 1492 | * 0: display meaning of the statistics |
1812924b | 1493 | */ |
f073cc8f CW |
1494 | static ssize_t ptc_proc_write(struct file *file, const char __user *user, |
1495 | size_t count, loff_t *data) | |
1812924b | 1496 | { |
b8f7fb13 | 1497 | int cpu; |
f073cc8f CW |
1498 | int i; |
1499 | int elements; | |
b8f7fb13 | 1500 | long input_arg; |
1812924b | 1501 | char optstr[64]; |
b8f7fb13 | 1502 | struct ptc_stats *stat; |
1812924b | 1503 | |
e7eb8726 | 1504 | if (count == 0 || count > sizeof(optstr)) |
cef53278 | 1505 | return -EINVAL; |
1812924b CW |
1506 | if (copy_from_user(optstr, user, count)) |
1507 | return -EFAULT; | |
1508 | optstr[count - 1] = '\0'; | |
f073cc8f | 1509 | |
26ef8577 CW |
1510 | if (!strcmp(optstr, "on")) { |
1511 | set_bau_on(); | |
1512 | return count; | |
1513 | } else if (!strcmp(optstr, "off")) { | |
1514 | set_bau_off(); | |
1515 | return count; | |
1516 | } | |
1517 | ||
164109e3 | 1518 | if (kstrtol(optstr, 10, &input_arg) < 0) { |
efa59ab3 | 1519 | pr_debug("%s is invalid\n", optstr); |
1812924b CW |
1520 | return -EINVAL; |
1521 | } | |
1522 | ||
b8f7fb13 | 1523 | if (input_arg == 0) { |
64441745 | 1524 | elements = ARRAY_SIZE(stat_description); |
efa59ab3 AB |
1525 | pr_debug("# cpu: cpu number\n"); |
1526 | pr_debug("Sender statistics:\n"); | |
f073cc8f | 1527 | for (i = 0; i < elements; i++) |
efa59ab3 | 1528 | pr_debug("%s\n", stat_description[i]); |
b8f7fb13 CW |
1529 | } else if (input_arg == -1) { |
1530 | for_each_present_cpu(cpu) { | |
1531 | stat = &per_cpu(ptcstats, cpu); | |
1532 | memset(stat, 0, sizeof(struct ptc_stats)); | |
1533 | } | |
e8e5e8a8 CW |
1534 | } |
1535 | ||
1536 | return count; | |
1537 | } | |
1538 | ||
1539 | static int local_atoi(const char *name) | |
1540 | { | |
1541 | int val = 0; | |
1542 | ||
1543 | for (;; name++) { | |
1544 | switch (*name) { | |
1545 | case '0' ... '9': | |
1546 | val = 10*val+(*name-'0'); | |
1547 | break; | |
1548 | default: | |
1549 | return val; | |
b8f7fb13 | 1550 | } |
1812924b | 1551 | } |
e8e5e8a8 CW |
1552 | } |
1553 | ||
1554 | /* | |
f073cc8f CW |
1555 | * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables. |
1556 | * Zero values reset them to defaults. | |
e8e5e8a8 | 1557 | */ |
f073cc8f CW |
1558 | static int parse_tunables_write(struct bau_control *bcp, char *instr, |
1559 | int count) | |
e8e5e8a8 | 1560 | { |
e8e5e8a8 CW |
1561 | char *p; |
1562 | char *q; | |
f073cc8f CW |
1563 | int cnt = 0; |
1564 | int val; | |
64441745 | 1565 | int e = ARRAY_SIZE(tunables); |
e8e5e8a8 | 1566 | |
e8e5e8a8 CW |
1567 | p = instr + strspn(instr, WHITESPACE); |
1568 | q = p; | |
1569 | for (; *p; p = q + strspn(q, WHITESPACE)) { | |
1570 | q = p + strcspn(p, WHITESPACE); | |
1571 | cnt++; | |
1572 | if (q == p) | |
1573 | break; | |
1574 | } | |
f073cc8f | 1575 | if (cnt != e) { |
efa59ab3 | 1576 | pr_info("bau tunable error: should be %d values\n", e); |
e8e5e8a8 CW |
1577 | return -EINVAL; |
1578 | } | |
1579 | ||
1580 | p = instr + strspn(instr, WHITESPACE); | |
1581 | q = p; | |
1582 | for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) { | |
1583 | q = p + strcspn(p, WHITESPACE); | |
1584 | val = local_atoi(p); | |
1585 | switch (cnt) { | |
1586 | case 0: | |
1587 | if (val == 0) { | |
f073cc8f CW |
1588 | max_concurr = MAX_BAU_CONCURRENT; |
1589 | max_concurr_const = MAX_BAU_CONCURRENT; | |
e8e5e8a8 CW |
1590 | continue; |
1591 | } | |
e8e5e8a8 | 1592 | if (val < 1 || val > bcp->cpus_in_uvhub) { |
efa59ab3 | 1593 | pr_debug( |
e8e5e8a8 CW |
1594 | "Error: BAU max concurrent %d is invalid\n", |
1595 | val); | |
1596 | return -EINVAL; | |
1597 | } | |
f073cc8f CW |
1598 | max_concurr = val; |
1599 | max_concurr_const = val; | |
e8e5e8a8 | 1600 | continue; |
f073cc8f | 1601 | default: |
e8e5e8a8 | 1602 | if (val == 0) |
f073cc8f | 1603 | *tunables[cnt].tunp = tunables[cnt].deflt; |
e8e5e8a8 | 1604 | else |
f073cc8f | 1605 | *tunables[cnt].tunp = val; |
e8e5e8a8 CW |
1606 | continue; |
1607 | } | |
1608 | if (q == p) | |
1609 | break; | |
1610 | } | |
f073cc8f CW |
1611 | return 0; |
1612 | } | |
1613 | ||
1614 | /* | |
1615 | * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables) | |
1616 | */ | |
1617 | static ssize_t tunables_write(struct file *file, const char __user *user, | |
1618 | size_t count, loff_t *data) | |
1619 | { | |
1620 | int cpu; | |
1621 | int ret; | |
1622 | char instr[100]; | |
1623 | struct bau_control *bcp; | |
1624 | ||
1625 | if (count == 0 || count > sizeof(instr)-1) | |
1626 | return -EINVAL; | |
1627 | if (copy_from_user(instr, user, count)) | |
1628 | return -EFAULT; | |
1629 | ||
1630 | instr[count] = '\0'; | |
1631 | ||
00b30cf0 | 1632 | cpu = get_cpu(); |
1633 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f | 1634 | ret = parse_tunables_write(bcp, instr, count); |
00b30cf0 | 1635 | put_cpu(); |
f073cc8f CW |
1636 | if (ret) |
1637 | return ret; | |
1638 | ||
e8e5e8a8 CW |
1639 | for_each_present_cpu(cpu) { |
1640 | bcp = &per_cpu(bau_control, cpu); | |
67492c86 AB |
1641 | bcp->max_concurr = max_concurr; |
1642 | bcp->max_concurr_const = max_concurr; | |
1643 | bcp->plugged_delay = plugged_delay; | |
1644 | bcp->plugsb4reset = plugsb4reset; | |
1645 | bcp->timeoutsb4reset = timeoutsb4reset; | |
1646 | bcp->ipi_reset_limit = ipi_reset_limit; | |
1647 | bcp->complete_threshold = complete_threshold; | |
1648 | bcp->cong_response_us = congested_respns_us; | |
1649 | bcp->cong_reps = congested_reps; | |
1650 | bcp->disabled_period = sec_2_cycles(disabled_period); | |
1651 | bcp->giveup_limit = giveup_limit; | |
e8e5e8a8 | 1652 | } |
1812924b CW |
1653 | return count; |
1654 | } | |
1655 | ||
1656 | static const struct seq_operations uv_ptc_seq_ops = { | |
f073cc8f CW |
1657 | .start = ptc_seq_start, |
1658 | .next = ptc_seq_next, | |
1659 | .stop = ptc_seq_stop, | |
1660 | .show = ptc_seq_show | |
1812924b CW |
1661 | }; |
1662 | ||
f073cc8f | 1663 | static int ptc_proc_open(struct inode *inode, struct file *file) |
1812924b CW |
1664 | { |
1665 | return seq_open(file, &uv_ptc_seq_ops); | |
1666 | } | |
1667 | ||
e8e5e8a8 CW |
1668 | static int tunables_open(struct inode *inode, struct file *file) |
1669 | { | |
1670 | return 0; | |
1671 | } | |
1672 | ||
1812924b | 1673 | static const struct file_operations proc_uv_ptc_operations = { |
f073cc8f | 1674 | .open = ptc_proc_open, |
b194b120 | 1675 | .read = seq_read, |
f073cc8f | 1676 | .write = ptc_proc_write, |
b194b120 CW |
1677 | .llseek = seq_lseek, |
1678 | .release = seq_release, | |
1812924b CW |
1679 | }; |
1680 | ||
e8e5e8a8 CW |
1681 | static const struct file_operations tunables_fops = { |
1682 | .open = tunables_open, | |
1683 | .read = tunables_read, | |
1684 | .write = tunables_write, | |
6038f373 | 1685 | .llseek = default_llseek, |
e8e5e8a8 CW |
1686 | }; |
1687 | ||
b194b120 | 1688 | static int __init uv_ptc_init(void) |
1812924b | 1689 | { |
b194b120 | 1690 | struct proc_dir_entry *proc_uv_ptc; |
1812924b CW |
1691 | |
1692 | if (!is_uv_system()) | |
1693 | return 0; | |
1694 | ||
10f02d11 AD |
1695 | proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL, |
1696 | &proc_uv_ptc_operations); | |
1812924b | 1697 | if (!proc_uv_ptc) { |
efa59ab3 | 1698 | pr_err("unable to create %s proc entry\n", |
1812924b CW |
1699 | UV_PTC_BASENAME); |
1700 | return -EINVAL; | |
1701 | } | |
e8e5e8a8 CW |
1702 | |
1703 | tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL); | |
1704 | if (!tunables_dir) { | |
efa59ab3 | 1705 | pr_err("unable to create debugfs directory %s\n", |
e8e5e8a8 CW |
1706 | UV_BAU_TUNABLES_DIR); |
1707 | return -EINVAL; | |
1708 | } | |
1709 | tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600, | |
f073cc8f | 1710 | tunables_dir, NULL, &tunables_fops); |
e8e5e8a8 | 1711 | if (!tunables_file) { |
efa59ab3 | 1712 | pr_err("unable to create debugfs file %s\n", |
e8e5e8a8 CW |
1713 | UV_BAU_TUNABLES_FILE); |
1714 | return -EINVAL; | |
1715 | } | |
1812924b CW |
1716 | return 0; |
1717 | } | |
1718 | ||
1812924b | 1719 | /* |
77ed23f8 | 1720 | * Initialize the sending side's sending buffers. |
1812924b | 1721 | */ |
f073cc8f | 1722 | static void activation_descriptor_init(int node, int pnode, int base_pnode) |
1812924b CW |
1723 | { |
1724 | int i; | |
b8f7fb13 | 1725 | int cpu; |
da87c937 | 1726 | int uv1 = 0; |
6a469e46 | 1727 | unsigned long gpa; |
1812924b | 1728 | unsigned long m; |
b194b120 | 1729 | unsigned long n; |
f073cc8f | 1730 | size_t dsize; |
b8f7fb13 CW |
1731 | struct bau_desc *bau_desc; |
1732 | struct bau_desc *bd2; | |
da87c937 | 1733 | struct uv1_bau_msg_header *uv1_hdr; |
a26fd719 | 1734 | struct uv2_3_bau_msg_header *uv2_3_hdr; |
b8f7fb13 | 1735 | struct bau_control *bcp; |
b194b120 | 1736 | |
0e2595cd | 1737 | /* |
f073cc8f CW |
1738 | * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC) |
1739 | * per cpu; and one per cpu on the uvhub (ADP_SZ) | |
0e2595cd | 1740 | */ |
f073cc8f CW |
1741 | dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC; |
1742 | bau_desc = kmalloc_node(dsize, GFP_KERNEL, node); | |
b8f7fb13 | 1743 | BUG_ON(!bau_desc); |
b4c286e6 | 1744 | |
6a469e46 JS |
1745 | gpa = uv_gpa(bau_desc); |
1746 | n = uv_gpa_to_gnode(gpa); | |
21e3f12f | 1747 | m = ops.bau_gpa_to_offset(gpa); |
da87c937 CW |
1748 | if (is_uv1_hub()) |
1749 | uv1 = 1; | |
b4c286e6 | 1750 | |
77ed23f8 | 1751 | /* the 14-bit pnode */ |
f073cc8f | 1752 | write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m)); |
0e2595cd | 1753 | /* |
f073cc8f | 1754 | * Initializing all 8 (ITEMS_PER_DESC) descriptors for each |
0e2595cd | 1755 | * cpu even though we only use the first one; one descriptor can |
b8f7fb13 | 1756 | * describe a broadcast to 256 uv hubs. |
0e2595cd | 1757 | */ |
f073cc8f | 1758 | for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) { |
b8f7fb13 | 1759 | memset(bd2, 0, sizeof(struct bau_desc)); |
da87c937 CW |
1760 | if (uv1) { |
1761 | uv1_hdr = &bd2->header.uv1_hdr; | |
67492c86 | 1762 | uv1_hdr->swack_flag = 1; |
da87c937 CW |
1763 | /* |
1764 | * The base_dest_nasid set in the message header | |
1765 | * is the nasid of the first uvhub in the partition. | |
1766 | * The bit map will indicate destination pnode numbers | |
1767 | * relative to that base. They may not be consecutive | |
1768 | * if nasid striding is being used. | |
1769 | */ | |
1770 | uv1_hdr->base_dest_nasid = | |
67492c86 AB |
1771 | UV_PNODE_TO_NASID(base_pnode); |
1772 | uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID; | |
1773 | uv1_hdr->command = UV_NET_ENDPOINT_INTD; | |
1774 | uv1_hdr->int_both = 1; | |
da87c937 CW |
1775 | /* |
1776 | * all others need to be set to zero: | |
1777 | * fairness chaining multilevel count replied_to | |
1778 | */ | |
1779 | } else { | |
8b6e511e | 1780 | /* |
a26fd719 | 1781 | * BIOS uses legacy mode, but uv2 and uv3 hardware always |
8b6e511e CW |
1782 | * uses native mode for selective broadcasts. |
1783 | */ | |
a26fd719 | 1784 | uv2_3_hdr = &bd2->header.uv2_3_hdr; |
67492c86 | 1785 | uv2_3_hdr->swack_flag = 1; |
a26fd719 | 1786 | uv2_3_hdr->base_dest_nasid = |
67492c86 AB |
1787 | UV_PNODE_TO_NASID(base_pnode); |
1788 | uv2_3_hdr->dest_subnodeid = UV_LB_SUBNODEID; | |
1789 | uv2_3_hdr->command = UV_NET_ENDPOINT_INTD; | |
da87c937 | 1790 | } |
b194b120 | 1791 | } |
b8f7fb13 CW |
1792 | for_each_present_cpu(cpu) { |
1793 | if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu))) | |
1794 | continue; | |
1795 | bcp = &per_cpu(bau_control, cpu); | |
1796 | bcp->descriptor_base = bau_desc; | |
1797 | } | |
b194b120 CW |
1798 | } |
1799 | ||
1800 | /* | |
1801 | * initialize the destination side's receiving buffers | |
b8f7fb13 CW |
1802 | * entered for each uvhub in the partition |
1803 | * - node is first node (kernel memory notion) on the uvhub | |
1804 | * - pnode is the uvhub's physical identifier | |
b194b120 | 1805 | */ |
f073cc8f | 1806 | static void pq_init(int node, int pnode) |
b194b120 | 1807 | { |
b8f7fb13 | 1808 | int cpu; |
f073cc8f | 1809 | size_t plsize; |
b4c286e6 | 1810 | char *cp; |
f073cc8f | 1811 | void *vp; |
d2a57afa | 1812 | unsigned long gnode, first, last, tail; |
f073cc8f | 1813 | struct bau_pq_entry *pqp; |
b8f7fb13 | 1814 | struct bau_control *bcp; |
1812924b | 1815 | |
f073cc8f CW |
1816 | plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry); |
1817 | vp = kmalloc_node(plsize, GFP_KERNEL, node); | |
1818 | pqp = (struct bau_pq_entry *)vp; | |
dc163a41 | 1819 | BUG_ON(!pqp); |
b4c286e6 | 1820 | |
b194b120 | 1821 | cp = (char *)pqp + 31; |
f073cc8f | 1822 | pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5); |
b8f7fb13 CW |
1823 | |
1824 | for_each_present_cpu(cpu) { | |
1825 | if (pnode != uv_cpu_to_pnode(cpu)) | |
1826 | continue; | |
1827 | /* for every cpu on this pnode: */ | |
1828 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f CW |
1829 | bcp->queue_first = pqp; |
1830 | bcp->bau_msg_head = pqp; | |
1831 | bcp->queue_last = pqp + (DEST_Q_SIZE - 1); | |
b8f7fb13 | 1832 | } |
d2a57afa | 1833 | |
21e3f12f AB |
1834 | first = ops.bau_gpa_to_offset(uv_gpa(pqp)); |
1835 | last = ops.bau_gpa_to_offset(uv_gpa(pqp + (DEST_Q_SIZE - 1))); | |
d2a57afa | 1836 | |
4ea3c51d | 1837 | /* |
6d78059b AB |
1838 | * Pre UV4, the gnode is required to locate the payload queue |
1839 | * and the payload queue tail must be maintained by the kernel. | |
4ea3c51d | 1840 | */ |
6d78059b AB |
1841 | bcp = &per_cpu(bau_control, smp_processor_id()); |
1842 | if (bcp->uvhub_version <= 3) { | |
1843 | tail = first; | |
1844 | gnode = uv_gpa_to_gnode(uv_gpa(pqp)); | |
1845 | first = (gnode << UV_PAYLOADQ_GNODE_SHIFT) | tail; | |
1846 | write_mmr_payload_tail(pnode, tail); | |
1847 | } | |
1848 | ||
21e3f12f AB |
1849 | ops.write_payload_first(pnode, first); |
1850 | ops.write_payload_last(pnode, last); | |
1851 | ops.write_g_sw_ack(pnode, 0xffffUL); | |
f073cc8f | 1852 | |
b8f7fb13 | 1853 | /* in effect, all msg_type's are set to MSG_NOOP */ |
f073cc8f | 1854 | memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE); |
b194b120 | 1855 | } |
1812924b | 1856 | |
b194b120 | 1857 | /* |
b8f7fb13 | 1858 | * Initialization of each UV hub's structures |
b194b120 | 1859 | */ |
f073cc8f | 1860 | static void __init init_uvhub(int uvhub, int vector, int base_pnode) |
b194b120 | 1861 | { |
9674f35b | 1862 | int node; |
b194b120 | 1863 | int pnode; |
b194b120 | 1864 | unsigned long apicid; |
b8f7fb13 CW |
1865 | |
1866 | node = uvhub_to_first_node(uvhub); | |
1867 | pnode = uv_blade_to_pnode(uvhub); | |
f073cc8f CW |
1868 | |
1869 | activation_descriptor_init(node, pnode, base_pnode); | |
1870 | ||
1871 | pq_init(node, pnode); | |
b194b120 | 1872 | /* |
77ed23f8 CW |
1873 | * The below initialization can't be in firmware because the |
1874 | * messaging IRQ will be determined by the OS. | |
b194b120 | 1875 | */ |
8191c9f6 | 1876 | apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits; |
f073cc8f | 1877 | write_mmr_data_config(pnode, ((apicid << 32) | vector)); |
b8f7fb13 CW |
1878 | } |
1879 | ||
12a6611f CW |
1880 | /* |
1881 | * We will set BAU_MISC_CONTROL with a timeout period. | |
1882 | * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT. | |
f073cc8f | 1883 | * So the destination timeout period has to be calculated from them. |
12a6611f | 1884 | */ |
f073cc8f | 1885 | static int calculate_destination_timeout(void) |
12a6611f CW |
1886 | { |
1887 | unsigned long mmr_image; | |
1888 | int mult1; | |
1889 | int mult2; | |
1890 | int index; | |
1891 | int base; | |
1892 | int ret; | |
1893 | unsigned long ts_ns; | |
1894 | ||
2a919596 | 1895 | if (is_uv1_hub()) { |
f073cc8f | 1896 | mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK; |
2a919596 JS |
1897 | mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); |
1898 | index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK; | |
1899 | mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT); | |
1900 | mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK; | |
11cab711 CW |
1901 | ts_ns = timeout_base_ns[index]; |
1902 | ts_ns *= (mult1 * mult2); | |
2a919596 JS |
1903 | ret = ts_ns / 1000; |
1904 | } else { | |
a26fd719 | 1905 | /* same destination timeout for uv2 and uv3 */ |
d059f9fa CW |
1906 | /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */ |
1907 | mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL); | |
2a919596 | 1908 | mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT; |
f073cc8f | 1909 | if (mmr_image & (1L << UV2_ACK_UNITS_SHFT)) |
d059f9fa | 1910 | base = 80; |
2a919596 | 1911 | else |
d059f9fa CW |
1912 | base = 10; |
1913 | mult1 = mmr_image & UV2_ACK_MASK; | |
2a919596 JS |
1914 | ret = mult1 * base; |
1915 | } | |
12a6611f CW |
1916 | return ret; |
1917 | } | |
1918 | ||
f073cc8f CW |
1919 | static void __init init_per_cpu_tunables(void) |
1920 | { | |
1921 | int cpu; | |
1922 | struct bau_control *bcp; | |
1923 | ||
1924 | for_each_present_cpu(cpu) { | |
1925 | bcp = &per_cpu(bau_control, cpu); | |
1926 | bcp->baudisabled = 0; | |
26ef8577 | 1927 | if (nobau) |
1c532e00 | 1928 | bcp->nobau = true; |
f073cc8f CW |
1929 | bcp->statp = &per_cpu(ptcstats, cpu); |
1930 | /* time interval to catch a hardware stay-busy bug */ | |
1931 | bcp->timeout_interval = usec_2_cycles(2*timeout_us); | |
1932 | bcp->max_concurr = max_concurr; | |
1933 | bcp->max_concurr_const = max_concurr; | |
1934 | bcp->plugged_delay = plugged_delay; | |
1935 | bcp->plugsb4reset = plugsb4reset; | |
1936 | bcp->timeoutsb4reset = timeoutsb4reset; | |
1937 | bcp->ipi_reset_limit = ipi_reset_limit; | |
1938 | bcp->complete_threshold = complete_threshold; | |
1939 | bcp->cong_response_us = congested_respns_us; | |
1940 | bcp->cong_reps = congested_reps; | |
67492c86 AB |
1941 | bcp->disabled_period = sec_2_cycles(disabled_period); |
1942 | bcp->giveup_limit = giveup_limit; | |
d2ebc71d CW |
1943 | spin_lock_init(&bcp->queue_lock); |
1944 | spin_lock_init(&bcp->uvhub_lock); | |
8b6e511e | 1945 | spin_lock_init(&bcp->disable_lock); |
f073cc8f CW |
1946 | } |
1947 | } | |
1948 | ||
b8f7fb13 | 1949 | /* |
f073cc8f | 1950 | * Scan all cpus to collect blade and socket summaries. |
b8f7fb13 | 1951 | */ |
f073cc8f CW |
1952 | static int __init get_cpu_topology(int base_pnode, |
1953 | struct uvhub_desc *uvhub_descs, | |
1954 | unsigned char *uvhub_mask) | |
b8f7fb13 | 1955 | { |
b8f7fb13 CW |
1956 | int cpu; |
1957 | int pnode; | |
1958 | int uvhub; | |
f073cc8f | 1959 | int socket; |
b8f7fb13 CW |
1960 | struct bau_control *bcp; |
1961 | struct uvhub_desc *bdp; | |
1962 | struct socket_desc *sdp; | |
b8f7fb13 | 1963 | |
b8f7fb13 CW |
1964 | for_each_present_cpu(cpu) { |
1965 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f | 1966 | |
b8f7fb13 | 1967 | memset(bcp, 0, sizeof(struct bau_control)); |
f073cc8f | 1968 | |
b8f7fb13 | 1969 | pnode = uv_cpu_hub_info(cpu)->pnode; |
f073cc8f | 1970 | if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) { |
efa59ab3 | 1971 | pr_emerg( |
77ed23f8 | 1972 | "cpu %d pnode %d-%d beyond %d; BAU disabled\n", |
f073cc8f | 1973 | cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE); |
77ed23f8 CW |
1974 | return 1; |
1975 | } | |
f073cc8f | 1976 | |
77ed23f8 | 1977 | bcp->osnode = cpu_to_node(cpu); |
f073cc8f CW |
1978 | bcp->partition_base_pnode = base_pnode; |
1979 | ||
b8f7fb13 | 1980 | uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; |
c4026cfd | 1981 | *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8)); |
b8f7fb13 | 1982 | bdp = &uvhub_descs[uvhub]; |
f073cc8f | 1983 | |
b8f7fb13 CW |
1984 | bdp->num_cpus++; |
1985 | bdp->uvhub = uvhub; | |
1986 | bdp->pnode = pnode; | |
f073cc8f | 1987 | |
a8328ee5 CW |
1988 | /* kludge: 'assuming' one node per socket, and assuming that |
1989 | disabling a socket just leaves a gap in node numbers */ | |
77ed23f8 | 1990 | socket = bcp->osnode & 1; |
a8328ee5 | 1991 | bdp->socket_mask |= (1 << socket); |
b8f7fb13 CW |
1992 | sdp = &bdp->socket[socket]; |
1993 | sdp->cpu_number[sdp->num_cpus] = cpu; | |
1994 | sdp->num_cpus++; | |
cfa60917 | 1995 | if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) { |
efa59ab3 | 1996 | pr_emerg("%d cpus per socket invalid\n", |
f073cc8f | 1997 | sdp->num_cpus); |
cfa60917 CW |
1998 | return 1; |
1999 | } | |
b8f7fb13 | 2000 | } |
f073cc8f CW |
2001 | return 0; |
2002 | } | |
2003 | ||
2004 | /* | |
2005 | * Each socket is to get a local array of pnodes/hubs. | |
2006 | */ | |
2007 | static void make_per_cpu_thp(struct bau_control *smaster) | |
2008 | { | |
2009 | int cpu; | |
2010 | size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus(); | |
2011 | ||
2012 | smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode); | |
2013 | memset(smaster->thp, 0, hpsz); | |
2014 | for_each_present_cpu(cpu) { | |
2015 | smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode; | |
2016 | smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; | |
2017 | } | |
2018 | } | |
2019 | ||
442d3924 | 2020 | /* |
2021 | * Each uvhub is to get a local cpumask. | |
2022 | */ | |
2023 | static void make_per_hub_cpumask(struct bau_control *hmaster) | |
2024 | { | |
2025 | int sz = sizeof(cpumask_t); | |
2026 | ||
2027 | hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode); | |
2028 | } | |
2029 | ||
f073cc8f CW |
2030 | /* |
2031 | * Initialize all the per_cpu information for the cpu's on a given socket, | |
2032 | * given what has been gathered into the socket_desc struct. | |
2033 | * And reports the chosen hub and socket masters back to the caller. | |
2034 | */ | |
2035 | static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp, | |
2036 | struct bau_control **smasterp, | |
2037 | struct bau_control **hmasterp) | |
2038 | { | |
2039 | int i; | |
2040 | int cpu; | |
2041 | struct bau_control *bcp; | |
2042 | ||
2043 | for (i = 0; i < sdp->num_cpus; i++) { | |
2044 | cpu = sdp->cpu_number[i]; | |
2045 | bcp = &per_cpu(bau_control, cpu); | |
2046 | bcp->cpu = cpu; | |
2047 | if (i == 0) { | |
2048 | *smasterp = bcp; | |
2049 | if (!(*hmasterp)) | |
2050 | *hmasterp = bcp; | |
2051 | } | |
2052 | bcp->cpus_in_uvhub = bdp->num_cpus; | |
2053 | bcp->cpus_in_socket = sdp->num_cpus; | |
2054 | bcp->socket_master = *smasterp; | |
2055 | bcp->uvhub = bdp->uvhub; | |
da87c937 CW |
2056 | if (is_uv1_hub()) |
2057 | bcp->uvhub_version = 1; | |
2058 | else if (is_uv2_hub()) | |
2059 | bcp->uvhub_version = 2; | |
a26fd719 CW |
2060 | else if (is_uv3_hub()) |
2061 | bcp->uvhub_version = 3; | |
58d4ab46 AB |
2062 | else if (is_uv4_hub()) |
2063 | bcp->uvhub_version = 4; | |
da87c937 | 2064 | else { |
58d4ab46 | 2065 | pr_emerg("uvhub version not 1, 2, 3, or 4\n"); |
da87c937 CW |
2066 | return 1; |
2067 | } | |
f073cc8f | 2068 | bcp->uvhub_master = *hmasterp; |
5627a825 MT |
2069 | bcp->uvhub_cpu = uv_cpu_blade_processor_id(cpu); |
2070 | ||
f073cc8f | 2071 | if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { |
efa59ab3 | 2072 | pr_emerg("%d cpus per uvhub invalid\n", |
f073cc8f CW |
2073 | bcp->uvhub_cpu); |
2074 | return 1; | |
2075 | } | |
2076 | } | |
2077 | return 0; | |
2078 | } | |
2079 | ||
2080 | /* | |
2081 | * Summarize the blade and socket topology into the per_cpu structures. | |
2082 | */ | |
2083 | static int __init summarize_uvhub_sockets(int nuvhubs, | |
2084 | struct uvhub_desc *uvhub_descs, | |
2085 | unsigned char *uvhub_mask) | |
2086 | { | |
2087 | int socket; | |
2088 | int uvhub; | |
2089 | unsigned short socket_mask; | |
2090 | ||
c4026cfd | 2091 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
f073cc8f CW |
2092 | struct uvhub_desc *bdp; |
2093 | struct bau_control *smaster = NULL; | |
2094 | struct bau_control *hmaster = NULL; | |
2095 | ||
c4026cfd CW |
2096 | if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8)))) |
2097 | continue; | |
f073cc8f | 2098 | |
b8f7fb13 | 2099 | bdp = &uvhub_descs[uvhub]; |
a8328ee5 CW |
2100 | socket_mask = bdp->socket_mask; |
2101 | socket = 0; | |
2102 | while (socket_mask) { | |
f073cc8f CW |
2103 | struct socket_desc *sdp; |
2104 | if ((socket_mask & 1)) { | |
2105 | sdp = &bdp->socket[socket]; | |
2106 | if (scan_sock(sdp, bdp, &smaster, &hmaster)) | |
cfa60917 | 2107 | return 1; |
9c9153db | 2108 | make_per_cpu_thp(smaster); |
b8f7fb13 CW |
2109 | } |
2110 | socket++; | |
a8328ee5 | 2111 | socket_mask = (socket_mask >> 1); |
b8f7fb13 | 2112 | } |
442d3924 | 2113 | make_per_hub_cpumask(hmaster); |
b8f7fb13 | 2114 | } |
f073cc8f CW |
2115 | return 0; |
2116 | } | |
2117 | ||
2118 | /* | |
2119 | * initialize the bau_control structure for each cpu | |
2120 | */ | |
2121 | static int __init init_per_cpu(int nuvhubs, int base_part_pnode) | |
2122 | { | |
2123 | unsigned char *uvhub_mask; | |
2124 | void *vp; | |
2125 | struct uvhub_desc *uvhub_descs; | |
2126 | ||
e879c112 AB |
2127 | if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub()) |
2128 | timeout_us = calculate_destination_timeout(); | |
f073cc8f CW |
2129 | |
2130 | vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL); | |
2131 | uvhub_descs = (struct uvhub_desc *)vp; | |
2132 | memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc)); | |
2133 | uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL); | |
2134 | ||
2135 | if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask)) | |
bbd270e6 | 2136 | goto fail; |
f073cc8f CW |
2137 | |
2138 | if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask)) | |
bbd270e6 | 2139 | goto fail; |
f073cc8f | 2140 | |
b8f7fb13 | 2141 | kfree(uvhub_descs); |
c4026cfd | 2142 | kfree(uvhub_mask); |
f073cc8f | 2143 | init_per_cpu_tunables(); |
cfa60917 | 2144 | return 0; |
bbd270e6 | 2145 | |
2146 | fail: | |
2147 | kfree(uvhub_descs); | |
2148 | kfree(uvhub_mask); | |
2149 | return 1; | |
b194b120 CW |
2150 | } |
2151 | ||
2152 | /* | |
2153 | * Initialization of BAU-related structures | |
2154 | */ | |
2155 | static int __init uv_bau_init(void) | |
2156 | { | |
b8f7fb13 CW |
2157 | int uvhub; |
2158 | int pnode; | |
2159 | int nuvhubs; | |
2c74d666 | 2160 | int cur_cpu; |
f073cc8f | 2161 | int cpus; |
b8f7fb13 | 2162 | int vector; |
f073cc8f | 2163 | cpumask_var_t *mask; |
b194b120 CW |
2164 | |
2165 | if (!is_uv_system()) | |
2166 | return 0; | |
1812924b | 2167 | |
4f059d51 AB |
2168 | if (is_uv4_hub()) |
2169 | ops = uv4_bau_ops; | |
2170 | else if (is_uv3_hub()) | |
5e4f96fe AB |
2171 | ops = uv123_bau_ops; |
2172 | else if (is_uv2_hub()) | |
2173 | ops = uv123_bau_ops; | |
2174 | else if (is_uv1_hub()) | |
2175 | ops = uv123_bau_ops; | |
2176 | ||
f073cc8f CW |
2177 | for_each_possible_cpu(cur_cpu) { |
2178 | mask = &per_cpu(uv_flush_tlb_mask, cur_cpu); | |
2179 | zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu)); | |
2180 | } | |
76ba0ecd | 2181 | |
b8f7fb13 | 2182 | nuvhubs = uv_num_possible_blades(); |
f073cc8f | 2183 | congested_cycles = usec_2_cycles(congested_respns_us); |
9674f35b | 2184 | |
f073cc8f | 2185 | uv_base_pnode = 0x7fffffff; |
77ed23f8 | 2186 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
f073cc8f CW |
2187 | cpus = uv_blade_nr_possible_cpus(uvhub); |
2188 | if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode)) | |
2189 | uv_base_pnode = uv_blade_to_pnode(uvhub); | |
77ed23f8 CW |
2190 | } |
2191 | ||
e879c112 AB |
2192 | /* software timeouts are not supported on UV4 */ |
2193 | if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub()) | |
2194 | enable_timeouts(); | |
d059f9fa | 2195 | |
f073cc8f | 2196 | if (init_per_cpu(nuvhubs, uv_base_pnode)) { |
26ef8577 CW |
2197 | set_bau_off(); |
2198 | nobau_perm = 1; | |
77ed23f8 CW |
2199 | return 0; |
2200 | } | |
b8f7fb13 CW |
2201 | |
2202 | vector = UV_BAU_MESSAGE; | |
a26fd719 | 2203 | for_each_possible_blade(uvhub) { |
b8f7fb13 | 2204 | if (uv_blade_nr_possible_cpus(uvhub)) |
f073cc8f | 2205 | init_uvhub(uvhub, vector, uv_base_pnode); |
a26fd719 | 2206 | } |
b8f7fb13 | 2207 | |
b8f7fb13 CW |
2208 | alloc_intr_gate(vector, uv_bau_message_intr1); |
2209 | ||
2210 | for_each_possible_blade(uvhub) { | |
93a7ca0c | 2211 | if (uv_blade_nr_possible_cpus(uvhub)) { |
f073cc8f CW |
2212 | unsigned long val; |
2213 | unsigned long mmr; | |
93a7ca0c CW |
2214 | pnode = uv_blade_to_pnode(uvhub); |
2215 | /* INIT the bau */ | |
f073cc8f CW |
2216 | val = 1L << 63; |
2217 | write_gmmr_activation(pnode, val); | |
93a7ca0c | 2218 | mmr = 1; /* should be 1 to broadcast to both sockets */ |
da87c937 CW |
2219 | if (!is_uv1_hub()) |
2220 | write_mmr_data_broadcast(pnode, mmr); | |
93a7ca0c | 2221 | } |
b8f7fb13 | 2222 | } |
b4c286e6 | 2223 | |
1812924b CW |
2224 | return 0; |
2225 | } | |
b8f7fb13 | 2226 | core_initcall(uv_bau_init); |
e8e5e8a8 | 2227 | fs_initcall(uv_ptc_init); |