[linux-block.git] / arch / x86 / platform / ce4100 / ce4100.c

/*
 * Intel CE4100  platform specific setup code
 *
 * (C) Copyright 2010 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2
 * of the License.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/serial_reg.h>
#include <linux/serial_8250.h>
#include <linux/reboot.h>

#include <asm/ce4100.h>
#include <asm/prom.h>
#include <asm/setup.h>
#include <asm/i8259.h>
#include <asm/io.h>
#include <asm/io_apic.h>
#include <asm/emergency-restart.h>

static int ce4100_i8042_detect(void)
{
	return 0;
}

/*
 * The CE4100 platform has an internal 8051 Microcontroller which is
 * responsible for signaling to the external Power Management Unit the
 * intention to reset, reboot or power off the system. This 8051 device has
 * its command register mapped at I/O port 0xcf9 and the value 0x4 is used
 * to power off the system.
 */
static void ce4100_power_off(void)
{
	outb(0x4, 0xcf9);
}

#ifdef CONFIG_SERIAL_8250

static unsigned int mem_serial_in(struct uart_port *p, int offset)
{
	offset = offset << p->regshift;
	return readl(p->membase + offset);
}

/*
 * The UART Tx interrupts are not set under some conditions and therefore serial
 * transmission hangs. This is a silicon issue and has not been root caused. The
 * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
 * bit of LSR register in interrupt handler to see whether at least one of these
 * two bits is set, if so then process the transmit request. If this workaround
 * is not applied, then the serial transmission may hang. This workaround is for
 * errata number 9 in Errata - B step.
*/

static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
{
	unsigned int ret, ier, lsr;

	if (offset == UART_IIR) {
		offset = offset << p->regshift;
		ret = readl(p->membase + offset);
		if (ret & UART_IIR_NO_INT) {
			/* see if the TX interrupt should have really set */
			ier = mem_serial_in(p, UART_IER);
			/* see if the UART's XMIT interrupt is enabled */
			if (ier & UART_IER_THRI) {
				lsr = mem_serial_in(p, UART_LSR);
				/* now check to see if the UART should be
				   generating an interrupt (but isn't) */
				if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
					ret &= ~UART_IIR_NO_INT;
			}
		}
	} else
		ret =  mem_serial_in(p, offset);
	return ret;
}

static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
{
	offset = offset << p->regshift;
	writel(value, p->membase + offset);
}

static void ce4100_serial_fixup(int port, struct uart_port *up,
	unsigned short *capabilites)
{
#ifdef CONFIG_EARLY_PRINTK
	/*
	 * Over ride the legacy port configuration that comes from
	 * asm/serial.h. Using the ioport driver then switching to the
	 * PCI memmaped driver hangs the IOAPIC
	 */
	if (up->iotype !=  UPIO_MEM32) {
		up->uartclk  = 14745600;
		up->mapbase = 0xdffe0200;
		set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
				up->mapbase & PAGE_MASK);
		up->membase =
			(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
		up->membase += up->mapbase & ~PAGE_MASK;
		up->mapbase += port * 0x100;
		up->membase += port * 0x100;
		up->iotype   = UPIO_MEM32;
		up->regshift = 2;
		up->irq = 4;
	}
#endif
	up->iobase = 0;
	up->serial_in = ce4100_mem_serial_in;
	up->serial_out = ce4100_mem_serial_out;

	*capabilites |= (1 << 12);
}

static __init void sdv_serial_fixup(void)
{
	serial8250_set_isa_configurator(ce4100_serial_fixup);
}

#else
static inline void sdv_serial_fixup(void) {};
#endif

static void __init sdv_arch_setup(void)
{
	sdv_serial_fixup();
}

#ifdef CONFIG_X86_IO_APIC
static void sdv_pci_init(void)
{
	x86_of_pci_init();
	/* We can't set this earlier, because we need to calibrate the timer */
	legacy_pic = &null_legacy_pic;
}
#endif

/*
 * CE4100 specific x86_init function overrides and early setup
 * calls.
 */
void __init x86_ce4100_early_setup(void)
{
	x86_init.oem.arch_setup = sdv_arch_setup;
	x86_platform.i8042_detect = ce4100_i8042_detect;
	x86_init.resources.probe_roms = x86_init_noop;
	x86_init.mpparse.get_smp_config = x86_init_uint_noop;
	x86_init.mpparse.find_smp_config = x86_init_noop;
	x86_init.pci.init = ce4100_pci_init;

	/*
	 * By default, the reboot method is ACPI which is supported by the
	 * CE4100 bootloader CEFDK using FADT.ResetReg Address and ResetValue
	 * the bootloader will however issue a system power off instead of
	 * reboot. By using BOOT_KBD we ensure proper system reboot as
	 * expected.
	 */
	reboot_type = BOOT_KBD;

#ifdef CONFIG_X86_IO_APIC
	x86_init.pci.init_irq = sdv_pci_init;
	x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
#endif

	pm_power_off = ce4100_power_off;
}
Commit	Line	Data
c751e17b TG	1	/*
	2	* Intel CE4100 platform specific setup code
	3	*
	4	* (C) Copyright 2010 Intel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; version 2
	9	* of the License.
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/irq.h>
	14	#include <linux/module.h>
5ec6960f DB	15	#include <linux/serial_reg.h>
5ec6960f DB	16	#include <linux/serial_8250.h>
ff559981	17	#include <linux/reboot.h>
c751e17b	18
03150171	19	#include <asm/ce4100.h>
1fa4163b	20	#include <asm/prom.h>
c751e17b	21	#include <asm/setup.h>
1fa4163b	22	#include <asm/i8259.h>
5ec6960f	23	#include <asm/io.h>
1fa4163b	24	#include <asm/io_apic.h>
d7959916	25	#include <asm/emergency-restart.h>
c751e17b TG	26
	27	static int ce4100_i8042_detect(void)
	28	{
	29	return 0;
	30	}
	31
f49f4ab9 FF	32	/*
	33	* The CE4100 platform has an internal 8051 Microcontroller which is
	34	* responsible for signaling to the external Power Management Unit the
	35	* intention to reset, reboot or power off the system. This 8051 device has
	36	* its command register mapped at I/O port 0xcf9 and the value 0x4 is used
	37	* to power off the system.
	38	*/
	39	static void ce4100_power_off(void)
	40	{
	41	outb(0x4, 0xcf9);
	42	}
	43
5ec6960f DB	44	#ifdef CONFIG_SERIAL_8250
5ec6960f DB	45
5ec6960f DB	46	static unsigned int mem_serial_in(struct uart_port *p, int offset)
	47	{
	48	offset = offset << p->regshift;
	49	return readl(p->membase + offset);
	50	}
	51
	52	/*
	53	* The UART Tx interrupts are not set under some conditions and therefore serial
	54	* transmission hangs. This is a silicon issue and has not been root caused. The
	55	* workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
	56	* bit of LSR register in interrupt handler to see whether at least one of these
	57	* two bits is set, if so then process the transmit request. If this workaround
	58	* is not applied, then the serial transmission may hang. This workaround is for
	59	* errata number 9 in Errata - B step.
	60	*/
	61
	62	static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
	63	{
	64	unsigned int ret, ier, lsr;
	65
	66	if (offset == UART_IIR) {
	67	offset = offset << p->regshift;
	68	ret = readl(p->membase + offset);
	69	if (ret & UART_IIR_NO_INT) {
	70	/* see if the TX interrupt should have really set */
	71	ier = mem_serial_in(p, UART_IER);
	72	/* see if the UART's XMIT interrupt is enabled */
	73	if (ier & UART_IER_THRI) {
	74	lsr = mem_serial_in(p, UART_LSR);
	75	/* now check to see if the UART should be
	76	generating an interrupt (but isn't) */
	77	if (lsr & (UART_LSR_THRE \| UART_LSR_TEMT))
	78	ret &= ~UART_IIR_NO_INT;
	79	}
	80	}
	81	} else
	82	ret = mem_serial_in(p, offset);
	83	return ret;
	84	}
	85
	86	static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
	87	{
	88	offset = offset << p->regshift;
	89	writel(value, p->membase + offset);
	90	}
	91
	92	static void ce4100_serial_fixup(int port, struct uart_port *up,
	93	unsigned short *capabilites)
	94	{
	95	#ifdef CONFIG_EARLY_PRINTK
	96	/*
	97	* Over ride the legacy port configuration that comes from
	98	* asm/serial.h. Using the ioport driver then switching to the
	99	* PCI memmaped driver hangs the IOAPIC
	100	*/
	101	if (up->iotype != UPIO_MEM32) {
	102	up->uartclk = 14745600;
	103	up->mapbase = 0xdffe0200;
	104	set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
	105	up->mapbase & PAGE_MASK);
	106	up->membase =
	107	(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
	108	up->membase += up->mapbase & ~PAGE_MASK;
08ec212c MB	109	up->mapbase += port * 0x100;
08ec212c MB	110	up->membase += port * 0x100;
5ec6960f DB	111	up->iotype = UPIO_MEM32;
5ec6960f DB	112	up->regshift = 2;
08ec212c	113	up->irq = 4;
5ec6960f DB	114	}
	115	#endif
	116	up->iobase = 0;
	117	up->serial_in = ce4100_mem_serial_in;
	118	up->serial_out = ce4100_mem_serial_out;
	119
	120	*capabilites \|= (1 << 12);
	121	}
	122
	123	static __init void sdv_serial_fixup(void)
	124	{
	125	serial8250_set_isa_configurator(ce4100_serial_fixup);
	126	}
	127
	128	#else
f2ee4421	129	static inline void sdv_serial_fixup(void) {};
5ec6960f DB	130	#endif
	131
	132	static void __init sdv_arch_setup(void)
c751e17b	133	{
5ec6960f	134	sdv_serial_fixup();
c751e17b TG	135	}
c751e17b TG	136
1fa4163b	137	#ifdef CONFIG_X86_IO_APIC
148f9bb8	138	static void sdv_pci_init(void)
1fa4163b SAS	139	{
	140	x86_of_pci_init();
	141	/* We can't set this earlier, because we need to calibrate the timer */
	142	legacy_pic = &null_legacy_pic;
	143	}
	144	#endif
	145
c751e17b TG	146	/*
	147	* CE4100 specific x86_init function overrides and early setup
	148	* calls.
	149	*/
	150	void __init x86_ce4100_early_setup(void)
	151	{
	152	x86_init.oem.arch_setup = sdv_arch_setup;
	153	x86_platform.i8042_detect = ce4100_i8042_detect;
	154	x86_init.resources.probe_roms = x86_init_noop;
	155	x86_init.mpparse.get_smp_config = x86_init_uint_noop;
a906fdaa	156	x86_init.mpparse.find_smp_config = x86_init_noop;
03150171	157	x86_init.pci.init = ce4100_pci_init;
1fa4163b	158
d7959916 MB	159	/*
	160	* By default, the reboot method is ACPI which is supported by the
	161	* CE4100 bootloader CEFDK using FADT.ResetReg Address and ResetValue
	162	* the bootloader will however issue a system power off instead of
	163	* reboot. By using BOOT_KBD we ensure proper system reboot as
	164	* expected.
	165	*/
	166	reboot_type = BOOT_KBD;
	167
1fa4163b SAS	168	#ifdef CONFIG_X86_IO_APIC
	169	x86_init.pci.init_irq = sdv_pci_init;
	170	x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
	171	#endif
f49f4ab9 FF	172
f49f4ab9 FF	173	pm_power_off = ce4100_power_off;
c751e17b	174	}