Commit | Line | Data |
---|---|---|
b5401a96 | 1 | /* |
996c34ae KRW |
2 | * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and |
3 | * initial domain support. We also handle the DSDT _PRT callbacks for GSI's | |
4 | * used in HVM and initial domain mode (PV does not parse ACPI, so it has no | |
5 | * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and | |
6 | * 0xcf8 PCI configuration read/write. | |
b5401a96 AN |
7 | * |
8 | * Author: Ryan Wilson <hap9@epoch.ncsc.mil> | |
996c34ae KRW |
9 | * Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> |
10 | * Stefano Stabellini <stefano.stabellini@eu.citrix.com> | |
b5401a96 AN |
11 | */ |
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/acpi.h> | |
16 | ||
17 | #include <linux/io.h> | |
0e058e52 | 18 | #include <asm/io_apic.h> |
b5401a96 AN |
19 | #include <asm/pci_x86.h> |
20 | ||
21 | #include <asm/xen/hypervisor.h> | |
22 | ||
3942b740 | 23 | #include <xen/features.h> |
b5401a96 AN |
24 | #include <xen/events.h> |
25 | #include <asm/xen/pci.h> | |
14520c92 BO |
26 | #include <asm/xen/cpuid.h> |
27 | #include <asm/apic.h> | |
95d76acc | 28 | #include <asm/i8259.h> |
b5401a96 | 29 | |
fef6e262 KRW |
30 | static int xen_pcifront_enable_irq(struct pci_dev *dev) |
31 | { | |
32 | int rc; | |
33 | int share = 1; | |
34 | int pirq; | |
35 | u8 gsi; | |
36 | ||
37 | rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi); | |
38 | if (rc < 0) { | |
39 | dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n", | |
40 | rc); | |
41 | return rc; | |
42 | } | |
78316ada KRW |
43 | /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/ |
44 | pirq = gsi; | |
fef6e262 | 45 | |
95d76acc | 46 | if (gsi < nr_legacy_irqs()) |
fef6e262 KRW |
47 | share = 0; |
48 | ||
49 | rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront"); | |
50 | if (rc < 0) { | |
51 | dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n", | |
52 | gsi, pirq, rc); | |
53 | return rc; | |
54 | } | |
55 | ||
56 | dev->irq = rc; | |
57 | dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq); | |
58 | return 0; | |
59 | } | |
60 | ||
42a1de56 | 61 | #ifdef CONFIG_ACPI |
ed89eb63 | 62 | static int xen_register_pirq(u32 gsi, int gsi_override, int triggering, |
78316ada | 63 | bool set_pirq) |
42a1de56 | 64 | { |
ed89eb63 | 65 | int rc, pirq = -1, irq = -1; |
42a1de56 SS |
66 | struct physdev_map_pirq map_irq; |
67 | int shareable = 0; | |
68 | char *name; | |
69 | ||
68c2c39a SS |
70 | irq = xen_irq_from_gsi(gsi); |
71 | if (irq > 0) | |
72 | return irq; | |
73 | ||
78316ada KRW |
74 | if (set_pirq) |
75 | pirq = gsi; | |
76 | ||
fef6e262 KRW |
77 | map_irq.domid = DOMID_SELF; |
78 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
79 | map_irq.index = gsi; | |
80 | map_irq.pirq = pirq; | |
81 | ||
82 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
83 | if (rc) { | |
84 | printk(KERN_WARNING "xen map irq failed %d\n", rc); | |
85 | return -1; | |
86 | } | |
87 | ||
30bd35ed KRW |
88 | if (triggering == ACPI_EDGE_SENSITIVE) { |
89 | shareable = 0; | |
90 | name = "ioapic-edge"; | |
91 | } else { | |
92 | shareable = 1; | |
93 | name = "ioapic-level"; | |
94 | } | |
95 | ||
96 | if (gsi_override >= 0) | |
97 | gsi = gsi_override; | |
98 | ||
ed89eb63 | 99 | irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name); |
30bd35ed KRW |
100 | if (irq < 0) |
101 | goto out; | |
102 | ||
ed89eb63 | 103 | printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi); |
fef6e262 KRW |
104 | out: |
105 | return irq; | |
106 | } | |
107 | ||
ed89eb63 KRW |
108 | static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi, |
109 | int trigger, int polarity) | |
110 | { | |
111 | if (!xen_hvm_domain()) | |
112 | return -1; | |
113 | ||
78316ada KRW |
114 | return xen_register_pirq(gsi, -1 /* no GSI override */, trigger, |
115 | false /* no mapping of GSI to PIRQ */); | |
ed89eb63 KRW |
116 | } |
117 | ||
118 | #ifdef CONFIG_XEN_DOM0 | |
fef6e262 KRW |
119 | static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity) |
120 | { | |
121 | int rc, irq; | |
122 | struct physdev_setup_gsi setup_gsi; | |
123 | ||
124 | if (!xen_pv_domain()) | |
125 | return -1; | |
126 | ||
127 | printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n", | |
128 | gsi, triggering, polarity); | |
129 | ||
ed89eb63 | 130 | irq = xen_register_pirq(gsi, gsi_override, triggering, true); |
fef6e262 KRW |
131 | |
132 | setup_gsi.gsi = gsi; | |
133 | setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1); | |
134 | setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
135 | ||
136 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi); | |
137 | if (rc == -EEXIST) | |
138 | printk(KERN_INFO "Already setup the GSI :%d\n", gsi); | |
139 | else if (rc) { | |
140 | printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n", | |
141 | gsi, rc); | |
142 | } | |
143 | ||
144 | return irq; | |
145 | } | |
146 | ||
147 | static int acpi_register_gsi_xen(struct device *dev, u32 gsi, | |
148 | int trigger, int polarity) | |
149 | { | |
150 | return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity); | |
151 | } | |
152 | #endif | |
d92edd81 | 153 | #endif |
fef6e262 | 154 | |
b5401a96 AN |
155 | #if defined(CONFIG_PCI_MSI) |
156 | #include <linux/msi.h> | |
809f9267 | 157 | #include <asm/msidef.h> |
b5401a96 AN |
158 | |
159 | struct xen_pci_frontend_ops *xen_pci_frontend; | |
160 | EXPORT_SYMBOL_GPL(xen_pci_frontend); | |
161 | ||
fef6e262 KRW |
162 | static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
163 | { | |
164 | int irq, ret, i; | |
165 | struct msi_desc *msidesc; | |
166 | int *v; | |
167 | ||
884ac297 KRW |
168 | if (type == PCI_CAP_ID_MSI && nvec > 1) |
169 | return 1; | |
170 | ||
fef6e262 KRW |
171 | v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL); |
172 | if (!v) | |
173 | return -ENOMEM; | |
174 | ||
175 | if (type == PCI_CAP_ID_MSIX) | |
176 | ret = xen_pci_frontend_enable_msix(dev, v, nvec); | |
177 | else | |
178 | ret = xen_pci_frontend_enable_msi(dev, v); | |
179 | if (ret) | |
180 | goto error; | |
181 | i = 0; | |
182 | list_for_each_entry(msidesc, &dev->msi_list, list) { | |
dec02dea | 183 | irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i], |
4892c9b4 | 184 | (type == PCI_CAP_ID_MSI) ? nvec : 1, |
fef6e262 KRW |
185 | (type == PCI_CAP_ID_MSIX) ? |
186 | "pcifront-msi-x" : | |
187 | "pcifront-msi", | |
188 | DOMID_SELF); | |
e6599225 KRW |
189 | if (irq < 0) { |
190 | ret = irq; | |
fef6e262 | 191 | goto free; |
e6599225 | 192 | } |
fef6e262 KRW |
193 | i++; |
194 | } | |
195 | kfree(v); | |
196 | return 0; | |
197 | ||
198 | error: | |
199 | dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n"); | |
200 | free: | |
201 | kfree(v); | |
202 | return ret; | |
203 | } | |
204 | ||
af42b8d1 SS |
205 | #define XEN_PIRQ_MSI_DATA (MSI_DATA_TRIGGER_EDGE | \ |
206 | MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0)) | |
207 | ||
809f9267 SS |
208 | static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq, |
209 | struct msi_msg *msg) | |
210 | { | |
211 | /* We set vector == 0 to tell the hypervisor we don't care about it, | |
212 | * but we want a pirq setup instead. | |
213 | * We use the dest_id field to pass the pirq that we want. */ | |
214 | msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(pirq); | |
215 | msg->address_lo = | |
216 | MSI_ADDR_BASE_LO | | |
217 | MSI_ADDR_DEST_MODE_PHYSICAL | | |
218 | MSI_ADDR_REDIRECTION_CPU | | |
219 | MSI_ADDR_DEST_ID(pirq); | |
220 | ||
af42b8d1 | 221 | msg->data = XEN_PIRQ_MSI_DATA; |
809f9267 SS |
222 | } |
223 | ||
224 | static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
225 | { | |
bf480d95 | 226 | int irq, pirq; |
809f9267 SS |
227 | struct msi_desc *msidesc; |
228 | struct msi_msg msg; | |
229 | ||
884ac297 KRW |
230 | if (type == PCI_CAP_ID_MSI && nvec > 1) |
231 | return 1; | |
232 | ||
809f9267 | 233 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
891d4a48 | 234 | __pci_read_msi_msg(msidesc, &msg); |
af42b8d1 SS |
235 | pirq = MSI_ADDR_EXT_DEST_ID(msg.address_hi) | |
236 | ((msg.address_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xff); | |
bf480d95 IC |
237 | if (msg.data != XEN_PIRQ_MSI_DATA || |
238 | xen_irq_from_pirq(pirq) < 0) { | |
239 | pirq = xen_allocate_pirq_msi(dev, msidesc); | |
e6599225 KRW |
240 | if (pirq < 0) { |
241 | irq = -ENODEV; | |
af42b8d1 | 242 | goto error; |
e6599225 | 243 | } |
bf480d95 | 244 | xen_msi_compose_msg(dev, pirq, &msg); |
83a18912 | 245 | __pci_write_msi_msg(msidesc, &msg); |
bf480d95 IC |
246 | dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq); |
247 | } else { | |
248 | dev_dbg(&dev->dev, | |
249 | "xen: msi already bound to pirq=%d\n", pirq); | |
af42b8d1 | 250 | } |
dec02dea | 251 | irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq, |
4892c9b4 | 252 | (type == PCI_CAP_ID_MSI) ? nvec : 1, |
bf480d95 | 253 | (type == PCI_CAP_ID_MSIX) ? |
beafbdc1 KRW |
254 | "msi-x" : "msi", |
255 | DOMID_SELF); | |
bf480d95 | 256 | if (irq < 0) |
809f9267 | 257 | goto error; |
bf480d95 IC |
258 | dev_dbg(&dev->dev, |
259 | "xen: msi --> pirq=%d --> irq=%d\n", pirq, irq); | |
809f9267 SS |
260 | } |
261 | return 0; | |
262 | ||
809f9267 | 263 | error: |
bf480d95 IC |
264 | dev_err(&dev->dev, |
265 | "Xen PCI frontend has not registered MSI/MSI-X support!\n"); | |
e6599225 | 266 | return irq; |
809f9267 SS |
267 | } |
268 | ||
260a7d4c | 269 | #ifdef CONFIG_XEN_DOM0 |
55e901fc JB |
270 | static bool __read_mostly pci_seg_supported = true; |
271 | ||
f731e3ef QH |
272 | static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
273 | { | |
71eef7d1 | 274 | int ret = 0; |
f731e3ef QH |
275 | struct msi_desc *msidesc; |
276 | ||
277 | list_for_each_entry(msidesc, &dev->msi_list, list) { | |
71eef7d1 | 278 | struct physdev_map_pirq map_irq; |
beafbdc1 KRW |
279 | domid_t domid; |
280 | ||
281 | domid = ret = xen_find_device_domain_owner(dev); | |
282 | /* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED, | |
283 | * hence check ret value for < 0. */ | |
284 | if (ret < 0) | |
285 | domid = DOMID_SELF; | |
71eef7d1 IC |
286 | |
287 | memset(&map_irq, 0, sizeof(map_irq)); | |
beafbdc1 | 288 | map_irq.domid = domid; |
55e901fc | 289 | map_irq.type = MAP_PIRQ_TYPE_MSI_SEG; |
71eef7d1 IC |
290 | map_irq.index = -1; |
291 | map_irq.pirq = -1; | |
55e901fc JB |
292 | map_irq.bus = dev->bus->number | |
293 | (pci_domain_nr(dev->bus) << 16); | |
71eef7d1 IC |
294 | map_irq.devfn = dev->devfn; |
295 | ||
4892c9b4 RPM |
296 | if (type == PCI_CAP_ID_MSI && nvec > 1) { |
297 | map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI; | |
298 | map_irq.entry_nr = nvec; | |
299 | } else if (type == PCI_CAP_ID_MSIX) { | |
71eef7d1 IC |
300 | int pos; |
301 | u32 table_offset, bir; | |
302 | ||
7c86617d | 303 | pos = dev->msix_cap; |
71eef7d1 IC |
304 | pci_read_config_dword(dev, pos + PCI_MSIX_TABLE, |
305 | &table_offset); | |
4be6bfe2 | 306 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
71eef7d1 IC |
307 | |
308 | map_irq.table_base = pci_resource_start(dev, bir); | |
309 | map_irq.entry_nr = msidesc->msi_attrib.entry_nr; | |
310 | } | |
311 | ||
55e901fc JB |
312 | ret = -EINVAL; |
313 | if (pci_seg_supported) | |
314 | ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, | |
315 | &map_irq); | |
4892c9b4 RPM |
316 | if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) { |
317 | /* | |
318 | * If MAP_PIRQ_TYPE_MULTI_MSI is not available | |
319 | * there's nothing else we can do in this case. | |
320 | * Just set ret > 0 so driver can retry with | |
321 | * single MSI. | |
322 | */ | |
323 | ret = 1; | |
324 | goto out; | |
325 | } | |
55e901fc JB |
326 | if (ret == -EINVAL && !pci_domain_nr(dev->bus)) { |
327 | map_irq.type = MAP_PIRQ_TYPE_MSI; | |
328 | map_irq.index = -1; | |
329 | map_irq.pirq = -1; | |
330 | map_irq.bus = dev->bus->number; | |
331 | ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, | |
332 | &map_irq); | |
333 | if (ret != -EINVAL) | |
334 | pci_seg_supported = false; | |
335 | } | |
71eef7d1 | 336 | if (ret) { |
beafbdc1 KRW |
337 | dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n", |
338 | ret, domid); | |
71eef7d1 IC |
339 | goto out; |
340 | } | |
341 | ||
4892c9b4 RPM |
342 | ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq, |
343 | (type == PCI_CAP_ID_MSI) ? nvec : 1, | |
344 | (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi", | |
345 | domid); | |
71eef7d1 IC |
346 | if (ret < 0) |
347 | goto out; | |
f731e3ef | 348 | } |
71eef7d1 IC |
349 | ret = 0; |
350 | out: | |
351 | return ret; | |
f731e3ef | 352 | } |
8605c684 | 353 | |
ac8344c4 | 354 | static void xen_initdom_restore_msi_irqs(struct pci_dev *dev) |
8605c684 TL |
355 | { |
356 | int ret = 0; | |
357 | ||
358 | if (pci_seg_supported) { | |
359 | struct physdev_pci_device restore_ext; | |
360 | ||
361 | restore_ext.seg = pci_domain_nr(dev->bus); | |
362 | restore_ext.bus = dev->bus->number; | |
363 | restore_ext.devfn = dev->devfn; | |
364 | ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext, | |
365 | &restore_ext); | |
366 | if (ret == -ENOSYS) | |
367 | pci_seg_supported = false; | |
368 | WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret); | |
369 | } | |
370 | if (!pci_seg_supported) { | |
371 | struct physdev_restore_msi restore; | |
372 | ||
373 | restore.bus = dev->bus->number; | |
374 | restore.devfn = dev->devfn; | |
375 | ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore); | |
376 | WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret); | |
377 | } | |
378 | } | |
b5401a96 AN |
379 | #endif |
380 | ||
fef6e262 | 381 | static void xen_teardown_msi_irqs(struct pci_dev *dev) |
b5401a96 | 382 | { |
fef6e262 | 383 | struct msi_desc *msidesc; |
b5401a96 | 384 | |
fef6e262 KRW |
385 | msidesc = list_entry(dev->msi_list.next, struct msi_desc, list); |
386 | if (msidesc->msi_attrib.is_msix) | |
387 | xen_pci_frontend_disable_msix(dev); | |
388 | else | |
389 | xen_pci_frontend_disable_msi(dev); | |
b5401a96 | 390 | |
fef6e262 KRW |
391 | /* Free the IRQ's and the msidesc using the generic code. */ |
392 | default_teardown_msi_irqs(dev); | |
393 | } | |
f4d0635b | 394 | |
fef6e262 KRW |
395 | static void xen_teardown_msi_irq(unsigned int irq) |
396 | { | |
397 | xen_destroy_irq(irq); | |
398 | } | |
03f56e42 | 399 | |
fef6e262 | 400 | #endif |
3f2a230c | 401 | |
b5401a96 AN |
402 | int __init pci_xen_init(void) |
403 | { | |
404 | if (!xen_pv_domain() || xen_initial_domain()) | |
405 | return -ENODEV; | |
406 | ||
407 | printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n"); | |
408 | ||
409 | pcibios_set_cache_line_size(); | |
410 | ||
411 | pcibios_enable_irq = xen_pcifront_enable_irq; | |
412 | pcibios_disable_irq = NULL; | |
413 | ||
414 | #ifdef CONFIG_ACPI | |
415 | /* Keep ACPI out of the picture */ | |
416 | acpi_noirq = 1; | |
417 | #endif | |
418 | ||
b5401a96 AN |
419 | #ifdef CONFIG_PCI_MSI |
420 | x86_msi.setup_msi_irqs = xen_setup_msi_irqs; | |
421 | x86_msi.teardown_msi_irq = xen_teardown_msi_irq; | |
422 | x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs; | |
38737d82 | 423 | pci_msi_ignore_mask = 1; |
b5401a96 AN |
424 | #endif |
425 | return 0; | |
426 | } | |
3942b740 | 427 | |
066d79e4 BO |
428 | #ifdef CONFIG_PCI_MSI |
429 | void __init xen_msi_init(void) | |
430 | { | |
14520c92 BO |
431 | if (!disable_apic) { |
432 | /* | |
433 | * If hardware supports (x2)APIC virtualization (as indicated | |
434 | * by hypervisor's leaf 4) then we don't need to use pirqs/ | |
435 | * event channels for MSI handling and instead use regular | |
436 | * APIC processing | |
437 | */ | |
438 | uint32_t eax = cpuid_eax(xen_cpuid_base() + 4); | |
439 | ||
440 | if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) || | |
441 | ((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && cpu_has_apic)) | |
442 | return; | |
443 | } | |
444 | ||
066d79e4 BO |
445 | x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs; |
446 | x86_msi.teardown_msi_irq = xen_teardown_msi_irq; | |
447 | } | |
448 | #endif | |
449 | ||
3942b740 SS |
450 | int __init pci_xen_hvm_init(void) |
451 | { | |
207d543f | 452 | if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs)) |
3942b740 SS |
453 | return 0; |
454 | ||
455 | #ifdef CONFIG_ACPI | |
456 | /* | |
457 | * We don't want to change the actual ACPI delivery model, | |
458 | * just how GSIs get registered. | |
459 | */ | |
460 | __acpi_register_gsi = acpi_register_gsi_xen_hvm; | |
461 | #endif | |
809f9267 SS |
462 | |
463 | #ifdef CONFIG_PCI_MSI | |
066d79e4 BO |
464 | /* |
465 | * We need to wait until after x2apic is initialized | |
466 | * before we can set MSI IRQ ops. | |
467 | */ | |
468 | x86_platform.apic_post_init = xen_msi_init; | |
809f9267 | 469 | #endif |
3942b740 SS |
470 | return 0; |
471 | } | |
38aa66fc JF |
472 | |
473 | #ifdef CONFIG_XEN_DOM0 | |
38aa66fc JF |
474 | static __init void xen_setup_acpi_sci(void) |
475 | { | |
476 | int rc; | |
477 | int trigger, polarity; | |
478 | int gsi = acpi_sci_override_gsi; | |
ee339fe6 KRW |
479 | int irq = -1; |
480 | int gsi_override = -1; | |
38aa66fc JF |
481 | |
482 | if (!gsi) | |
483 | return; | |
484 | ||
485 | rc = acpi_get_override_irq(gsi, &trigger, &polarity); | |
486 | if (rc) { | |
487 | printk(KERN_WARNING "xen: acpi_get_override_irq failed for acpi" | |
488 | " sci, rc=%d\n", rc); | |
489 | return; | |
490 | } | |
491 | trigger = trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE; | |
492 | polarity = polarity ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH; | |
996c34ae | 493 | |
38aa66fc JF |
494 | printk(KERN_INFO "xen: sci override: global_irq=%d trigger=%d " |
495 | "polarity=%d\n", gsi, trigger, polarity); | |
496 | ||
ee339fe6 KRW |
497 | /* Before we bind the GSI to a Linux IRQ, check whether |
498 | * we need to override it with bus_irq (IRQ) value. Usually for | |
499 | * IRQs below IRQ_LEGACY_IRQ this holds IRQ == GSI, as so: | |
500 | * ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) | |
501 | * but there are oddballs where the IRQ != GSI: | |
502 | * ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 20 low level) | |
503 | * which ends up being: gsi_to_irq[9] == 20 | |
504 | * (which is what acpi_gsi_to_irq ends up calling when starting the | |
505 | * the ACPI interpreter and keels over since IRQ 9 has not been | |
506 | * setup as we had setup IRQ 20 for it). | |
507 | */ | |
ee339fe6 | 508 | if (acpi_gsi_to_irq(gsi, &irq) == 0) { |
97ffab1f KRW |
509 | /* Use the provided value if it's valid. */ |
510 | if (irq >= 0) | |
ee339fe6 KRW |
511 | gsi_override = irq; |
512 | } | |
513 | ||
514 | gsi = xen_register_gsi(gsi, gsi_override, trigger, polarity); | |
38aa66fc JF |
515 | printk(KERN_INFO "xen: acpi sci %d\n", gsi); |
516 | ||
517 | return; | |
518 | } | |
a0ee0567 KRW |
519 | |
520 | int __init pci_xen_initial_domain(void) | |
38aa66fc | 521 | { |
78316ada | 522 | int irq; |
a0ee0567 | 523 | |
f731e3ef QH |
524 | #ifdef CONFIG_PCI_MSI |
525 | x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs; | |
526 | x86_msi.teardown_msi_irq = xen_teardown_msi_irq; | |
8605c684 | 527 | x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs; |
38737d82 | 528 | pci_msi_ignore_mask = 1; |
f731e3ef | 529 | #endif |
38aa66fc JF |
530 | xen_setup_acpi_sci(); |
531 | __acpi_register_gsi = acpi_register_gsi_xen; | |
38aa66fc | 532 | /* Pre-allocate legacy irqs */ |
95d76acc | 533 | for (irq = 0; irq < nr_legacy_irqs(); irq++) { |
38aa66fc JF |
534 | int trigger, polarity; |
535 | ||
536 | if (acpi_get_override_irq(irq, &trigger, &polarity) == -1) | |
537 | continue; | |
538 | ||
ee339fe6 | 539 | xen_register_pirq(irq, -1 /* no GSI override */, |
ed89eb63 | 540 | trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE, |
78316ada | 541 | true /* Map GSI to PIRQ */); |
38aa66fc | 542 | } |
9b6519db | 543 | if (0 == nr_ioapics) { |
95d76acc | 544 | for (irq = 0; irq < nr_legacy_irqs(); irq++) |
78316ada | 545 | xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic"); |
9b6519db | 546 | } |
a0ee0567 | 547 | return 0; |
38aa66fc | 548 | } |
c55fa78b KRW |
549 | |
550 | struct xen_device_domain_owner { | |
551 | domid_t domain; | |
552 | struct pci_dev *dev; | |
553 | struct list_head list; | |
554 | }; | |
555 | ||
556 | static DEFINE_SPINLOCK(dev_domain_list_spinlock); | |
557 | static struct list_head dev_domain_list = LIST_HEAD_INIT(dev_domain_list); | |
558 | ||
559 | static struct xen_device_domain_owner *find_device(struct pci_dev *dev) | |
560 | { | |
561 | struct xen_device_domain_owner *owner; | |
562 | ||
563 | list_for_each_entry(owner, &dev_domain_list, list) { | |
564 | if (owner->dev == dev) | |
565 | return owner; | |
566 | } | |
567 | return NULL; | |
568 | } | |
569 | ||
570 | int xen_find_device_domain_owner(struct pci_dev *dev) | |
571 | { | |
572 | struct xen_device_domain_owner *owner; | |
573 | int domain = -ENODEV; | |
574 | ||
575 | spin_lock(&dev_domain_list_spinlock); | |
576 | owner = find_device(dev); | |
577 | if (owner) | |
578 | domain = owner->domain; | |
579 | spin_unlock(&dev_domain_list_spinlock); | |
580 | return domain; | |
581 | } | |
582 | EXPORT_SYMBOL_GPL(xen_find_device_domain_owner); | |
583 | ||
584 | int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain) | |
585 | { | |
586 | struct xen_device_domain_owner *owner; | |
587 | ||
588 | owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL); | |
589 | if (!owner) | |
590 | return -ENODEV; | |
591 | ||
592 | spin_lock(&dev_domain_list_spinlock); | |
593 | if (find_device(dev)) { | |
594 | spin_unlock(&dev_domain_list_spinlock); | |
595 | kfree(owner); | |
596 | return -EEXIST; | |
597 | } | |
598 | owner->domain = domain; | |
599 | owner->dev = dev; | |
600 | list_add_tail(&owner->list, &dev_domain_list); | |
601 | spin_unlock(&dev_domain_list_spinlock); | |
602 | return 0; | |
603 | } | |
604 | EXPORT_SYMBOL_GPL(xen_register_device_domain_owner); | |
605 | ||
606 | int xen_unregister_device_domain_owner(struct pci_dev *dev) | |
607 | { | |
608 | struct xen_device_domain_owner *owner; | |
609 | ||
610 | spin_lock(&dev_domain_list_spinlock); | |
611 | owner = find_device(dev); | |
612 | if (!owner) { | |
613 | spin_unlock(&dev_domain_list_spinlock); | |
614 | return -ENODEV; | |
615 | } | |
616 | list_del(&owner->list); | |
617 | spin_unlock(&dev_domain_list_spinlock); | |
618 | kfree(owner); | |
619 | return 0; | |
620 | } | |
621 | EXPORT_SYMBOL_GPL(xen_unregister_device_domain_owner); | |
7c1bfd68 | 622 | #endif |