[linux-2.6-block.git] / arch / x86 / pci / visws.c

/*
 *	Low-Level PCI Support for SGI Visual Workstation
 *
 *	(c) 1999--2000 Martin Mares <mj@ucw.cz>
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>

#include <asm/setup.h>
#include <asm/pci_x86.h>
#include <asm/visws/cobalt.h>
#include <asm/visws/lithium.h>

static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
static void pci_visws_disable_irq(struct pci_dev *dev) { }

/* int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq; */
/* void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq; */

/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */


unsigned int pci_bus0, pci_bus1;

static int __init visws_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq, bus = dev->bus->number;

	pin--;

	/* Nothing useful at PIIX4 pin 1 */
	if (bus == pci_bus0 && slot == 4 && pin == 0)
		return -1;

	/* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
	if (bus == pci_bus0 && slot == 4 && pin == 3) {
		irq = CO_IRQ(CO_APIC_PIIX4_USB);
		goto out;
	}

	/* First pin spread down 1 APIC entry per slot */
	if (pin == 0) {
		irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
						CO_APIC_PCIA_BASE0) + slot);
		goto out;
	}

	/* lines 1,2,3 from any slot is shared in this twirly pattern */
	if (bus == pci_bus1) {
		/* lines 1-3 from devices 0 1 rotate over 2 apic entries */
		irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
	} else { /* bus == pci_bus0 */
		/* lines 1-3 from devices 0-3 rotate over 3 apic entries */
		if (slot == 0)
			slot = 3; /* same pattern */
		irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
	}
out:
	printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
	return irq;
}

void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

int __init pci_visws_init(void)
{
	pcibios_enable_irq = &pci_visws_enable_irq;
	pcibios_disable_irq = &pci_visws_disable_irq;

	/* The VISWS supports configuration access type 1 only */
	pci_probe = (pci_probe | PCI_PROBE_CONF1) &
		    ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);

	pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
	pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;

	printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
		"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);

	raw_pci_ops = &pci_direct_conf1;
	pci_scan_bus_with_sysdata(pci_bus0);
	pci_scan_bus_with_sysdata(pci_bus1);
	pci_fixup_irqs(pci_common_swizzle, visws_map_irq);
	pcibios_resource_survey();
	/* Request bus scan */
	return 1;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Support for SGI Visual Workstation
	3	*
	4	* (c) 1999--2000 Martin Mares <mj@ucw.cz>
	5	*/
	6
1da177e4 LT	7	#include <linux/kernel.h>
	8	#include <linux/pci.h>
	9	#include <linux/init.h>
	10
5548ed11	11	#include <asm/setup.h>
82487711	12	#include <asm/pci_x86.h>
b4b86416 IM	13	#include <asm/visws/cobalt.h>
b4b86416 IM	14	#include <asm/visws/lithium.h>
1da177e4	15
1da177e4	16	static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
46bdac99	17	static void pci_visws_disable_irq(struct pci_dev *dev) { }
1da177e4	18
22d5c67c IM	19	/* int (pcibios_enable_irq)(struct pci_dev dev) = &pci_visws_enable_irq; */
22d5c67c IM	20	/* void (pcibios_disable_irq)(struct pci_dev dev) = &pci_visws_disable_irq; */
1da177e4	21
22d5c67c	22	/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */
1da177e4 LT	23
	24
	25	unsigned int pci_bus0, pci_bus1;
	26
d5341942	27	static int __init visws_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4 LT	28	{
	29	int irq, bus = dev->bus->number;
	30
	31	pin--;
	32
	33	/* Nothing useful at PIIX4 pin 1 */
	34	if (bus == pci_bus0 && slot == 4 && pin == 0)
	35	return -1;
	36
	37	/* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
	38	if (bus == pci_bus0 && slot == 4 && pin == 3) {
	39	irq = CO_IRQ(CO_APIC_PIIX4_USB);
	40	goto out;
	41	}
	42
	43	/* First pin spread down 1 APIC entry per slot */
	44	if (pin == 0) {
	45	irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
	46	CO_APIC_PCIA_BASE0) + slot);
	47	goto out;
	48	}
	49
	50	/* lines 1,2,3 from any slot is shared in this twirly pattern */
	51	if (bus == pci_bus1) {
	52	/* lines 1-3 from devices 0 1 rotate over 2 apic entries */
	53	irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
	54	} else { /* bus == pci_bus0 */
	55	/* lines 1-3 from devices 0-3 rotate over 3 apic entries */
	56	if (slot == 0)
	57	slot = 3; /* same pattern */
	58	irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
	59	}
	60	out:
	61	printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
	62	return irq;
	63	}
	64
	65	void __init pcibios_update_irq(struct pci_dev *dev, int irq)
	66	{
	67	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	68	}
	69
3cabf37f	70	int __init pci_visws_init(void)
1da177e4	71	{
3cabf37f RR	72	pcibios_enable_irq = &pci_visws_enable_irq;
	73	pcibios_disable_irq = &pci_visws_disable_irq;
	74
1da177e4 LT	75	/* The VISWS supports configuration access type 1 only */
	76	pci_probe = (pci_probe \| PCI_PROBE_CONF1) &
	77	~(PCI_PROBE_BIOS \| PCI_PROBE_CONF2);
	78
	79	pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
	80	pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
	81
	82	printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
	83	"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
	84
	85	raw_pci_ops = &pci_direct_conf1;
73c59afc MBY	86	pci_scan_bus_with_sysdata(pci_bus0);
73c59afc MBY	87	pci_scan_bus_with_sysdata(pci_bus1);
904d6a30	88	pci_fixup_irqs(pci_common_swizzle, visws_map_irq);
1da177e4	89	pcibios_resource_survey();
b72d0db9 TG	90	/* Request bus scan */
b72d0db9 TG	91	return 1;
1da177e4	92	}