[linux-2.6-block.git] / arch / x86 / pci / mmconfig_32.c

/*
 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
 * Copyright (C) 2004 Intel Corp.
 *
 * This code is released under the GNU General Public License version 2.
 */

/*
 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/rcupdate.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>

/* Assume systems with more busses have correct MCFG */
#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))

/* The base address of the last MMCONFIG device accessed */
static u32 mmcfg_last_accessed_device;
static int mmcfg_last_accessed_cpu;

/*
 * Functions for accessing PCI configuration space with MMCONFIG accesses
 */
static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
{
	struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);

	if (cfg)
		return cfg->address;
	return 0;
}

/*
 * This is always called under pci_config_lock
 */
static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
{
	u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12);
	int cpu = smp_processor_id();
	if (dev_base != mmcfg_last_accessed_device ||
	    cpu != mmcfg_last_accessed_cpu) {
		mmcfg_last_accessed_device = dev_base;
		mmcfg_last_accessed_cpu = cpu;
		set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	}
}

static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
err:		*value = -1;
		return -EINVAL;
	}

	rcu_read_lock();
	base = get_base_addr(seg, bus, devfn);
	if (!base) {
		rcu_read_unlock();
		goto err;
	}

	raw_spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		*value = mmio_config_readb(mmcfg_virt_addr + reg);
		break;
	case 2:
		*value = mmio_config_readw(mmcfg_virt_addr + reg);
		break;
	case 4:
		*value = mmio_config_readl(mmcfg_virt_addr + reg);
		break;
	}
	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
	rcu_read_unlock();

	return 0;
}

static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095))
		return -EINVAL;

	rcu_read_lock();
	base = get_base_addr(seg, bus, devfn);
	if (!base) {
		rcu_read_unlock();
		return -EINVAL;
	}

	raw_spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		mmio_config_writeb(mmcfg_virt_addr + reg, value);
		break;
	case 2:
		mmio_config_writew(mmcfg_virt_addr + reg, value);
		break;
	case 4:
		mmio_config_writel(mmcfg_virt_addr + reg, value);
		break;
	}
	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
	rcu_read_unlock();

	return 0;
}

const struct pci_raw_ops pci_mmcfg = {
	.read =		pci_mmcfg_read,
	.write =	pci_mmcfg_write,
};

int __init pci_mmcfg_arch_init(void)
{
	printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n");
	raw_pci_ext_ops = &pci_mmcfg;
	return 1;
}

void __init pci_mmcfg_arch_free(void)
{
}

int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
{
	return 0;
}

void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
{
	unsigned long flags;

	/* Invalidate the cached mmcfg map entry. */
	raw_spin_lock_irqsave(&pci_config_lock, flags);
	mmcfg_last_accessed_device = 0;
	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
	3	* Copyright (C) 2004 Intel Corp.
	4	*
	5	* This code is released under the GNU General Public License version 2.
	6	*/
	7
	8	/*
	9	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
	10	*/
	11
	12	#include <linux/pci.h>
	13	#include <linux/init.h>
376f70ac	14	#include <linux/rcupdate.h>
946f2ee5	15	#include <asm/e820.h>
82487711	16	#include <asm/pci_x86.h>
1da177e4	17
8c30b1a7	18	/* Assume systems with more busses have correct MCFG */
1da177e4 LT	19	#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
	20
	21	/* The base address of the last MMCONFIG device accessed */
	22	static u32 mmcfg_last_accessed_device;
8d1c4819	23	static int mmcfg_last_accessed_cpu;
1da177e4 LT	24
	25	/*
	26	* Functions for accessing PCI configuration space with MMCONFIG accesses
	27	*/
d6ece549	28	static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
d57e26ce	29	{
f6e1d8cc	30	struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
d57e26ce	31
f6e1d8cc BH	32	if (cfg)
f6e1d8cc BH	33	return cfg->address;
3103039c	34	return 0;
d57e26ce	35	}
1da177e4	36
be5b7a89 AM	37	/*
	38	* This is always called under pci_config_lock
	39	*/
	40	static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
1da177e4	41	{
df5eb1d6	42	u32 dev_base = base \| PCI_MMCFG_BUS_OFFSET(bus) \| (devfn << 12);
8d1c4819 OH	43	int cpu = smp_processor_id();
	44	if (dev_base != mmcfg_last_accessed_device \|\|
	45	cpu != mmcfg_last_accessed_cpu) {
1da177e4	46	mmcfg_last_accessed_device = dev_base;
8d1c4819	47	mmcfg_last_accessed_cpu = cpu;
1da177e4 LT	48	set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	49	}
	50	}
	51
	52	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
	53	unsigned int devfn, int reg, int len, u32 *value)
	54	{
	55	unsigned long flags;
928cf8c6	56	u32 base;
1da177e4	57
ecc16ba9	58	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)) {
a0ca9909	59	err: *value = -1;
1da177e4	60	return -EINVAL;
49c93e84	61	}
1da177e4	62
376f70ac	63	rcu_read_lock();
d6ece549	64	base = get_base_addr(seg, bus, devfn);
376f70ac JL	65	if (!base) {
376f70ac JL	66	rcu_read_unlock();
a0ca9909	67	goto err;
376f70ac	68	}
928cf8c6	69
d19f61f0	70	raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4	71
928cf8c6	72	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	73
	74	switch (len) {
	75	case 1:
3320ad99	76	*value = mmio_config_readb(mmcfg_virt_addr + reg);
1da177e4 LT	77	break;
1da177e4 LT	78	case 2:
3320ad99	79	*value = mmio_config_readw(mmcfg_virt_addr + reg);
1da177e4 LT	80	break;
1da177e4 LT	81	case 4:
3320ad99	82	*value = mmio_config_readl(mmcfg_virt_addr + reg);
1da177e4 LT	83	break;
1da177e4 LT	84	}
d19f61f0	85	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
376f70ac	86	rcu_read_unlock();
1da177e4 LT	87
	88	return 0;
	89	}
	90
	91	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
	92	unsigned int devfn, int reg, int len, u32 value)
	93	{
	94	unsigned long flags;
928cf8c6	95	u32 base;
1da177e4	96
15a58ed1	97	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095))
1da177e4 LT	98	return -EINVAL;
1da177e4 LT	99
376f70ac	100	rcu_read_lock();
d6ece549	101	base = get_base_addr(seg, bus, devfn);
376f70ac JL	102	if (!base) {
376f70ac JL	103	rcu_read_unlock();
a0ca9909	104	return -EINVAL;
376f70ac	105	}
928cf8c6	106
d19f61f0	107	raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4	108
928cf8c6	109	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	110
	111	switch (len) {
	112	case 1:
c1502e28	113	mmio_config_writeb(mmcfg_virt_addr + reg, value);
1da177e4 LT	114	break;
1da177e4 LT	115	case 2:
c1502e28	116	mmio_config_writew(mmcfg_virt_addr + reg, value);
1da177e4 LT	117	break;
1da177e4 LT	118	case 4:
c1502e28	119	mmio_config_writel(mmcfg_virt_addr + reg, value);
1da177e4 LT	120	break;
1da177e4 LT	121	}
d19f61f0	122	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
376f70ac	123	rcu_read_unlock();
1da177e4 LT	124
	125	return 0;
	126	}
	127
c0fa4078	128	const struct pci_raw_ops pci_mmcfg = {
1da177e4 LT	129	.read = pci_mmcfg_read,
	130	.write = pci_mmcfg_write,
	131	};
	132
b7867394	133	int __init pci_mmcfg_arch_init(void)
d6ece549	134	{
b6ce068a MW	135	printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n");
b6ce068a MW	136	raw_pci_ext_ops = &pci_mmcfg;
b7867394	137	return 1;
1da177e4	138	}
0b64ad71 YL	139
	140	void __init pci_mmcfg_arch_free(void)
	141	{
	142	}
9cf0105d	143
a18e3690	144	int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
9cf0105d JL	145	{
	146	return 0;
	147	}
	148
	149	void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
	150	{
	151	unsigned long flags;
	152
	153	/* Invalidate the cached mmcfg map entry. */
	154	raw_spin_lock_irqsave(&pci_config_lock, flags);
	155	mmcfg_last_accessed_device = 0;
	156	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
	157	}