[linux-block.git] / arch / x86 / pci / k8-bus_64.c

#include <linux/init.h>
#include <linux/pci.h>
#include <asm/pci-direct.h>
#include <asm/mpspec.h>
#include <linux/cpumask.h>
#include <linux/topology.h>

/*
 * This discovers the pcibus <-> node mapping on AMD K8.
 * also get peer root bus resource for io,mmio
 */


/*
 * sub bus (transparent) will use entres from 3 to store extra from root,
 * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
 */
#define RES_NUM 16
struct pci_root_info {
	char name[12];
	unsigned int res_num;
	struct resource res[RES_NUM];
	int bus_min;
	int bus_max;
	int node;
	int link;
};

/* 4 at this time, it may become to 32 */
#define PCI_ROOT_NR 4
static int pci_root_num;
static struct pci_root_info pci_root_info[PCI_ROOT_NR];

#ifdef CONFIG_NUMA

#define BUS_NR 256

static int mp_bus_to_node[BUS_NR];

void set_mp_bus_to_node(int busnum, int node)
{
	if (busnum >= 0 &&  busnum < BUS_NR)
		mp_bus_to_node[busnum] = node;
}

int get_mp_bus_to_node(int busnum)
{
	int node = -1;

	if (busnum < 0 || busnum > (BUS_NR - 1))
		return node;

	node = mp_bus_to_node[busnum];

	/*
	 * let numa_node_id to decide it later in dma_alloc_pages
	 * if there is no ram on that node
	 */
	if (node != -1 && !node_online(node))
		node = -1;

	return node;
}
#endif

void set_pci_bus_resources_arch_default(struct pci_bus *b)
{
	int i;
	int j;
	struct pci_root_info *info;

	/* if only one root bus, don't need to anything */
	if (pci_root_num < 2)
		return;

	for (i = 0; i < pci_root_num; i++) {
		if (pci_root_info[i].bus_min == b->number)
			break;
	}

	if (i == pci_root_num)
		return;

	info = &pci_root_info[i];
	for (j = 0; j < info->res_num; j++) {
		struct resource *res;
		struct resource *root;

		res = &info->res[j];
		b->resource[j] = res;
		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;
		insert_resource(root, res);
	}
}

#define RANGE_NUM 16

struct res_range {
	size_t start;
	size_t end;
};

static void __init update_range(struct res_range *range, size_t start,
				size_t end)
{
	int i;
	int j;

	for (j = 0; j < RANGE_NUM; j++) {
		if (!range[j].end)
			continue;

		if (start <= range[j].start && end >= range[j].end) {
			range[j].start = 0;
			range[j].end = 0;
			continue;
		}

		if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) {
			range[j].start = end + 1;
			continue;
		}


		if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) {
			range[j].end = start - 1;
			continue;
		}

		if (start > range[j].start && end < range[j].end) {
			/* find the new spare */
			for (i = 0; i < RANGE_NUM; i++) {
				if (range[i].end == 0)
					break;
			}
			if (i < RANGE_NUM) {
				range[i].end = range[j].end;
				range[i].start = end + 1;
			} else {
				printk(KERN_ERR "run of slot in ranges\n");
			}
			range[j].end = start - 1;
			continue;
		}
	}
}

static void __init update_res(struct pci_root_info *info, size_t start,
			      size_t end, unsigned long flags, int merge)
{
	int i;
	struct resource *res;

	if (!merge)
		goto addit;

	/* try to merge it with old one */
	for (i = 0; i < info->res_num; i++) {
		size_t final_start, final_end;
		size_t common_start, common_end;

		res = &info->res[i];
		if (res->flags != flags)
			continue;

		common_start = max((size_t)res->start, start);
		common_end = min((size_t)res->end, end);
		if (common_start > common_end + 1)
			continue;

		final_start = min((size_t)res->start, start);
		final_end = max((size_t)res->end, end);

		res->start = final_start;
		res->end = final_end;
		return;
	}

addit:

	/* need to add that */
	if (info->res_num >= RES_NUM)
		return;

	res = &info->res[info->res_num];
	res->name = info->name;
	res->flags = flags;
	res->start = start;
	res->end = end;
	res->child = NULL;
	info->res_num++;
}

struct pci_hostbridge_probe {
	u32 bus;
	u32 slot;
	u32 vendor;
	u32 device;
};

static struct pci_hostbridge_probe pci_probes[] __initdata = {
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
};

static u64 __initdata fam10h_mmconf_start;
static u64 __initdata fam10h_mmconf_end;
static void __init get_pci_mmcfg_amd_fam10h_range(void)
{
	u32 address;
	u64 base, msr;
	unsigned segn_busn_bits;

	/* assume all cpus from fam10h have mmconf */
        if (boot_cpu_data.x86 < 0x10)
		return;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	rdmsrl(address, msr);

	/* mmconfig is not enable */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	fam10h_mmconf_start = base;
	fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
}

/**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 * Registers found in the K8 northbridge
 */
static int __init early_fill_mp_bus_info(void)
{
	int i;
	int j;
	unsigned bus;
	unsigned slot;
	int found;
	int node;
	int link;
	int def_node;
	int def_link;
	struct pci_root_info *info;
	u32 reg;
	struct resource *res;
	size_t start;
	size_t end;
	struct res_range range[RANGE_NUM];
	u64 val;
	u32 address;

#ifdef CONFIG_NUMA
	for (i = 0; i < BUS_NR; i++)
		mp_bus_to_node[i] = -1;
#endif

	if (!early_pci_allowed())
		return -1;

	found = 0;
	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
		u32 id;
		u16 device;
		u16 vendor;

		bus = pci_probes[i].bus;
		slot = pci_probes[i].slot;
		id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);

		vendor = id & 0xffff;
		device = (id>>16) & 0xffff;
		if (pci_probes[i].vendor == vendor &&
		    pci_probes[i].device == device) {
			found = 1;
			break;
		}
	}

	if (!found)
		return 0;

	pci_root_num = 0;
	for (i = 0; i < 4; i++) {
		int min_bus;
		int max_bus;
		reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));

		/* Check if that register is enabled for bus range */
		if ((reg & 7) != 3)
			continue;

		min_bus = (reg >> 16) & 0xff;
		max_bus = (reg >> 24) & 0xff;
		node = (reg >> 4) & 0x07;
#ifdef CONFIG_NUMA
		for (j = min_bus; j <= max_bus; j++)
			mp_bus_to_node[j] = (unsigned char) node;
#endif
		link = (reg >> 8) & 0x03;

		info = &pci_root_info[pci_root_num];
		info->bus_min = min_bus;
		info->bus_max = max_bus;
		info->node = node;
		info->link = link;
		sprintf(info->name, "PCI Bus #%02x", min_bus);
		pci_root_num++;
	}

	/* get the default node and link for left over res */
	reg = read_pci_config(bus, slot, 0, 0x60);
	def_node = (reg >> 8) & 0x07;
	reg = read_pci_config(bus, slot, 0, 0x64);
	def_link = (reg >> 8) & 0x03;

	memset(range, 0, sizeof(range));
	range[0].end = 0xffff;
	/* io port resource */
	for (i = 0; i < 4; i++) {
		reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xfff000;
		reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xfff000) | 0xfff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];
		printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
		       node, link, (u64)start, (u64)end);

		/* kernel only handle 16 bit only */
		if (end > 0xffff)
			end = 0xffff;
		update_res(info, start, end, IORESOURCE_IO, 1);
		update_range(range, start, end);
	}
	/* add left over io port range to def node/link, [0, 0xffff] */
	/* find the position */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_IO, 1);
		}
	}

	memset(range, 0, sizeof(range));
	/* 0xfd00000000-0xffffffffff for HT */
	range[0].end = (0xfdULL<<32) - 1;

	/* need to take out [0, TOM) for RAM*/
	address = MSR_K8_TOP_MEM1;
	rdmsrl(address, val);
	end = (val & 0xffffff8000000ULL);
	printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
	if (end < (1ULL<<32))
		update_range(range, 0, end - 1);

	/* get mmconfig */
	get_pci_mmcfg_amd_fam10h_range();
	/* need to take out mmconf range */
	if (fam10h_mmconf_end) {
		printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
		update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
	}

	/* mmio resource */
	for (i = 0; i < 8; i++) {
		reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xffffff00; /* 39:16 on 31:8*/
		start <<= 8;
		reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xffffff00);
		end <<= 8;
		end |= 0xffff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];

		printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
		       node, link, (u64)start, (u64)end);
		/*
		 * some sick allocation would have range overlap with fam10h
		 * mmconf range, so need to update start and end.
		 */
		if (fam10h_mmconf_end) {
			int changed = 0;
			u64 endx = 0;
			if (start >= fam10h_mmconf_start &&
			    start <= fam10h_mmconf_end) {
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}

			if (end >= fam10h_mmconf_start &&
			    end <= fam10h_mmconf_end) {
				end = fam10h_mmconf_start - 1;
				changed = 1;
			}

			if (start < fam10h_mmconf_start &&
			    end > fam10h_mmconf_end) {
				/* we got a hole */
				endx = fam10h_mmconf_start - 1;
				update_res(info, start, endx, IORESOURCE_MEM, 0);
				update_range(range, start, endx);
				printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}
			if (changed) {
				if (start <= end) {
					printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
				} else {
					printk(KERN_CONT "%s\n", endx?"":" ==> none");
					continue;
				}
			}
		}

		update_res(info, start, end, IORESOURCE_MEM, 1);
		update_range(range, start, end);
		printk(KERN_CONT "\n");
	}

	/* need to take out [4G, TOM2) for RAM*/
	/* SYS_CFG */
	address = MSR_K8_SYSCFG;
	rdmsrl(address, val);
	/* TOP_MEM2 is enabled? */
	if (val & (1<<21)) {
		/* TOP_MEM2 */
		address = MSR_K8_TOP_MEM2;
		rdmsrl(address, val);
		end = (val & 0xffffff8000000ULL);
		printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
		update_range(range, 1ULL<<32, end - 1);
	}

	/*
	 * add left over mmio range to def node/link ?
	 * that is tricky, just record range in from start_min to 4G
	 */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];

		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_MEM, 1);
		}
	}

	for (i = 0; i < pci_root_num; i++) {
		int res_num;
		int busnum;

		info = &pci_root_info[i];
		res_num = info->res_num;
		busnum = info->bus_min;
		printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
		       info->bus_min, info->bus_max, info->node, info->link);
		for (j = 0; j < res_num; j++) {
			res = &info->res[j];
			printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
			       busnum, j,
			       (res->flags & IORESOURCE_IO)?"io port":"mmio",
			       res->start, res->end);
		}
	}

	return 0;
}

postcore_initcall(early_fill_mp_bus_info);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
1da177e4 LT	2	#include <linux/pci.h>
871d5f8d	3	#include <asm/pci-direct.h>
1da177e4 LT	4	#include <asm/mpspec.h>
1da177e4 LT	5	#include <linux/cpumask.h>
871d5f8d	6	#include <linux/topology.h>
1da177e4 LT	7
	8	/*
	9	* This discovers the pcibus <-> node mapping on AMD K8.
30a18d6c	10	* also get peer root bus resource for io,mmio
1da177e4 LT	11	*/
1da177e4 LT	12
35ddd068	13
30a18d6c YL	14	/*
	15	* sub bus (transparent) will use entres from 3 to store extra from root,
	16	* so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
	17	*/
	18	#define RES_NUM 16
	19	struct pci_root_info {
	20	char name[12];
	21	unsigned int res_num;
	22	struct resource res[RES_NUM];
	23	int bus_min;
	24	int bus_max;
	25	int node;
	26	int link;
	27	};
	28
	29	/* 4 at this time, it may become to 32 */
	30	#define PCI_ROOT_NR 4
	31	static int pci_root_num;
	32	static struct pci_root_info pci_root_info[PCI_ROOT_NR];
1da177e4	33
871d5f8d YL	34	#ifdef CONFIG_NUMA
	35
	36	#define BUS_NR 256
	37
	38	static int mp_bus_to_node[BUS_NR];
	39
	40	void set_mp_bus_to_node(int busnum, int node)
	41	{
	42	if (busnum >= 0 && busnum < BUS_NR)
	43	mp_bus_to_node[busnum] = node;
	44	}
	45
	46	int get_mp_bus_to_node(int busnum)
	47	{
	48	int node = -1;
	49
	50	if (busnum < 0 \|\| busnum > (BUS_NR - 1))
	51	return node;
	52
	53	node = mp_bus_to_node[busnum];
	54
	55	/*
	56	* let numa_node_id to decide it later in dma_alloc_pages
	57	* if there is no ram on that node
	58	*/
	59	if (node != -1 && !node_online(node))
	60	node = -1;
	61
	62	return node;
	63	}
871d5f8d YL	64	#endif
871d5f8d YL	65
30a18d6c YL	66	void set_pci_bus_resources_arch_default(struct pci_bus *b)
	67	{
	68	int i;
	69	int j;
	70	struct pci_root_info *info;
	71
4cf19463 YL	72	/* if only one root bus, don't need to anything */
4cf19463 YL	73	if (pci_root_num < 2)
30a18d6c YL	74	return;
	75
	76	for (i = 0; i < pci_root_num; i++) {
	77	if (pci_root_info[i].bus_min == b->number)
	78	break;
	79	}
	80
	81	if (i == pci_root_num)
	82	return;
	83
	84	info = &pci_root_info[i];
	85	for (j = 0; j < info->res_num; j++) {
	86	struct resource *res;
	87	struct resource *root;
	88
	89	res = &info->res[j];
	90	b->resource[j] = res;
	91	if (res->flags & IORESOURCE_IO)
	92	root = &ioport_resource;
	93	else
	94	root = &iomem_resource;
	95	insert_resource(root, res);
	96	}
	97	}
	98
	99	#define RANGE_NUM 16
	100
	101	struct res_range {
	102	size_t start;
	103	size_t end;
	104	};
	105
	106	static void __init update_range(struct res_range *range, size_t start,
	107	size_t end)
	108	{
	109	int i;
	110	int j;
	111
	112	for (j = 0; j < RANGE_NUM; j++) {
	113	if (!range[j].end)
	114	continue;
e8ee6f0a YL	115
e8ee6f0a YL	116	if (start <= range[j].start && end >= range[j].end) {
30a18d6c YL	117	range[j].start = 0;
30a18d6c YL	118	range[j].end = 0;
e8ee6f0a YL	119	continue;
	120	}
	121
	122	if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) {
	123	range[j].start = end + 1;
	124	continue;
	125	}
	126
	127
	128	if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) {
30a18d6c	129	range[j].end = start - 1;
e8ee6f0a YL	130	continue;
	131	}
	132
	133	if (start > range[j].start && end < range[j].end) {
30a18d6c YL	134	/* find the new spare */
	135	for (i = 0; i < RANGE_NUM; i++) {
	136	if (range[i].end == 0)
	137	break;
	138	}
	139	if (i < RANGE_NUM) {
	140	range[i].end = range[j].end;
	141	range[i].start = end + 1;
	142	} else {
	143	printk(KERN_ERR "run of slot in ranges\n");
	144	}
	145	range[j].end = start - 1;
e8ee6f0a	146	continue;
30a18d6c YL	147	}
	148	}
	149	}
	150
	151	static void __init update_res(struct pci_root_info *info, size_t start,
	152	size_t end, unsigned long flags, int merge)
	153	{
	154	int i;
	155	struct resource *res;
	156
	157	if (!merge)
	158	goto addit;
	159
	160	/* try to merge it with old one */
	161	for (i = 0; i < info->res_num; i++) {
e8ee6f0a YL	162	size_t final_start, final_end;
	163	size_t common_start, common_end;
	164
30a18d6c YL	165	res = &info->res[i];
	166	if (res->flags != flags)
	167	continue;
e8ee6f0a YL	168
	169	common_start = max((size_t)res->start, start);
	170	common_end = min((size_t)res->end, end);
	171	if (common_start > common_end + 1)
	172	continue;
	173
	174	final_start = min((size_t)res->start, start);
	175	final_end = max((size_t)res->end, end);
	176
	177	res->start = final_start;
	178	res->end = final_end;
	179	return;
30a18d6c YL	180	}
	181
	182	addit:
	183
	184	/* need to add that */
	185	if (info->res_num >= RES_NUM)
	186	return;
	187
	188	res = &info->res[info->res_num];
	189	res->name = info->name;
	190	res->flags = flags;
	191	res->start = start;
	192	res->end = end;
	193	res->child = NULL;
	194	info->res_num++;
	195	}
	196
	197	struct pci_hostbridge_probe {
	198	u32 bus;
	199	u32 slot;
	200	u32 vendor;
	201	u32 device;
	202	};
	203
	204	static struct pci_hostbridge_probe pci_probes[] __initdata = {
	205	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	206	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	207	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	208	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
	209	};
	210
6e184f29 YL	211	static u64 __initdata fam10h_mmconf_start;
	212	static u64 __initdata fam10h_mmconf_end;
	213	static void __init get_pci_mmcfg_amd_fam10h_range(void)
	214	{
	215	u32 address;
	216	u64 base, msr;
	217	unsigned segn_busn_bits;
	218
	219	/* assume all cpus from fam10h have mmconf */
	220	if (boot_cpu_data.x86 < 0x10)
	221	return;
	222
	223	address = MSR_FAM10H_MMIO_CONF_BASE;
	224	rdmsrl(address, msr);
	225
	226	/* mmconfig is not enable */
	227	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	228	return;
	229
	230	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	231
	232	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	233	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	234
	235	fam10h_mmconf_start = base;
	236	fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
	237	}
	238
1da177e4	239	/**
871d5f8d YL	240	* early_fill_mp_bus_to_node()
871d5f8d YL	241	* called before pcibios_scan_root and pci_scan_bus
1da177e4 LT	242	* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
	243	* Registers found in the K8 northbridge
	244	*/
30a18d6c	245	static int __init early_fill_mp_bus_info(void)
1da177e4	246	{
30a18d6c YL	247	int i;
	248	int j;
	249	unsigned bus;
871d5f8d	250	unsigned slot;
30a18d6c	251	int found;
35ddd068	252	int node;
30a18d6c YL	253	int link;
	254	int def_node;
	255	int def_link;
	256	struct pci_root_info *info;
	257	u32 reg;
	258	struct resource *res;
	259	size_t start;
	260	size_t end;
	261	struct res_range range[RANGE_NUM];
	262	u64 val;
	263	u32 address;
1da177e4	264
30a18d6c	265	#ifdef CONFIG_NUMA
871d5f8d YL	266	for (i = 0; i < BUS_NR; i++)
871d5f8d YL	267	mp_bus_to_node[i] = -1;
30a18d6c	268	#endif
871d5f8d YL	269
	270	if (!early_pci_allowed())
	271	return -1;
	272
30a18d6c YL	273	found = 0;
	274	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
	275	u32 id;
	276	u16 device;
	277	u16 vendor;
35ddd068	278
30a18d6c YL	279	bus = pci_probes[i].bus;
	280	slot = pci_probes[i].slot;
	281	id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
35ddd068	282
30a18d6c YL	283	vendor = id & 0xffff;
	284	device = (id>>16) & 0xffff;
	285	if (pci_probes[i].vendor == vendor &&
	286	pci_probes[i].device == device) {
	287	found = 1;
	288	break;
	289	}
	290	}
	291
	292	if (!found)
	293	return 0;
35ddd068	294
30a18d6c YL	295	pci_root_num = 0;
	296	for (i = 0; i < 4; i++) {
	297	int min_bus;
	298	int max_bus;
	299	reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
35ddd068 YL	300
35ddd068 YL	301	/* Check if that register is enabled for bus range */
30a18d6c	302	if ((reg & 7) != 3)
35ddd068 YL	303	continue;
35ddd068 YL	304
30a18d6c YL	305	min_bus = (reg >> 16) & 0xff;
	306	max_bus = (reg >> 24) & 0xff;
	307	node = (reg >> 4) & 0x07;
	308	#ifdef CONFIG_NUMA
35ddd068 YL	309	for (j = min_bus; j <= max_bus; j++)
35ddd068 YL	310	mp_bus_to_node[j] = (unsigned char) node;
30a18d6c YL	311	#endif
	312	link = (reg >> 8) & 0x03;
	313
	314	info = &pci_root_info[pci_root_num];
	315	info->bus_min = min_bus;
	316	info->bus_max = max_bus;
	317	info->node = node;
	318	info->link = link;
	319	sprintf(info->name, "PCI Bus #%02x", min_bus);
	320	pci_root_num++;
1da177e4 LT	321	}
1da177e4 LT	322
30a18d6c YL	323	/* get the default node and link for left over res */
	324	reg = read_pci_config(bus, slot, 0, 0x60);
	325	def_node = (reg >> 8) & 0x07;
	326	reg = read_pci_config(bus, slot, 0, 0x64);
	327	def_link = (reg >> 8) & 0x03;
	328
	329	memset(range, 0, sizeof(range));
	330	range[0].end = 0xffff;
	331	/* io port resource */
	332	for (i = 0; i < 4; i++) {
	333	reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
	334	if (!(reg & 3))
	335	continue;
	336
	337	start = reg & 0xfff000;
	338	reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
	339	node = reg & 0x07;
	340	link = (reg >> 4) & 0x03;
	341	end = (reg & 0xfff000) \| 0xfff;
	342
	343	/* find the position */
	344	for (j = 0; j < pci_root_num; j++) {
	345	info = &pci_root_info[j];
	346	if (info->node == node && info->link == link)
	347	break;
	348	}
	349	if (j == pci_root_num)
	350	continue; /* not found */
	351
	352	info = &pci_root_info[j];
6e184f29 YL	353	printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
6e184f29 YL	354	node, link, (u64)start, (u64)end);
e8ee6f0a YL	355
	356	/* kernel only handle 16 bit only */
	357	if (end > 0xffff)
	358	end = 0xffff;
	359	update_res(info, start, end, IORESOURCE_IO, 1);
30a18d6c YL	360	update_range(range, start, end);
	361	}
	362	/* add left over io port range to def node/link, [0, 0xffff] */
	363	/* find the position */
	364	for (j = 0; j < pci_root_num; j++) {
	365	info = &pci_root_info[j];
	366	if (info->node == def_node && info->link == def_link)
	367	break;
	368	}
	369	if (j < pci_root_num) {
	370	info = &pci_root_info[j];
	371	for (i = 0; i < RANGE_NUM; i++) {
	372	if (!range[i].end)
	373	continue;
	374
	375	update_res(info, range[i].start, range[i].end,
	376	IORESOURCE_IO, 1);
	377	}
	378	}
	379
	380	memset(range, 0, sizeof(range));
	381	/* 0xfd00000000-0xffffffffff for HT */
6e184f29	382	range[0].end = (0xfdULL<<32) - 1;
30a18d6c YL	383
	384	/* need to take out [0, TOM) for RAM*/
	385	address = MSR_K8_TOP_MEM1;
	386	rdmsrl(address, val);
	387	end = (val & 0xffffff8000000ULL);
	388	printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
	389	if (end < (1ULL<<32))
	390	update_range(range, 0, end - 1);
	391
6e184f29 YL	392	/* get mmconfig */
	393	get_pci_mmcfg_amd_fam10h_range();
	394	/* need to take out mmconf range */
	395	if (fam10h_mmconf_end) {
	396	printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
	397	update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
	398	}
	399
30a18d6c YL	400	/* mmio resource */
	401	for (i = 0; i < 8; i++) {
	402	reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
	403	if (!(reg & 3))
	404	continue;
	405
	406	start = reg & 0xffffff00; /* 39:16 on 31:8*/
	407	start <<= 8;
	408	reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
	409	node = reg & 0x07;
	410	link = (reg >> 4) & 0x03;
	411	end = (reg & 0xffffff00);
	412	end <<= 8;
	413	end \|= 0xffff;
	414
	415	/* find the position */
	416	for (j = 0; j < pci_root_num; j++) {
	417	info = &pci_root_info[j];
	418	if (info->node == node && info->link == link)
	419	break;
	420	}
	421	if (j == pci_root_num)
	422	continue; /* not found */
	423
	424	info = &pci_root_info[j];
6e184f29 YL	425
	426	printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
	427	node, link, (u64)start, (u64)end);
	428	/*
	429	* some sick allocation would have range overlap with fam10h
	430	* mmconf range, so need to update start and end.
	431	*/
	432	if (fam10h_mmconf_end) {
	433	int changed = 0;
	434	u64 endx = 0;
	435	if (start >= fam10h_mmconf_start &&
	436	start <= fam10h_mmconf_end) {
	437	start = fam10h_mmconf_end + 1;
	438	changed = 1;
	439	}
	440
	441	if (end >= fam10h_mmconf_start &&
	442	end <= fam10h_mmconf_end) {
	443	end = fam10h_mmconf_start - 1;
	444	changed = 1;
	445	}
	446
	447	if (start < fam10h_mmconf_start &&
	448	end > fam10h_mmconf_end) {
	449	/* we got a hole */
	450	endx = fam10h_mmconf_start - 1;
	451	update_res(info, start, endx, IORESOURCE_MEM, 0);
	452	update_range(range, start, endx);
	453	printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
	454	start = fam10h_mmconf_end + 1;
	455	changed = 1;
	456	}
	457	if (changed) {
	458	if (start <= end) {
	459	printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
	460	} else {
	461	printk(KERN_CONT "%s\n", endx?"":" ==> none");
	462	continue;
	463	}
	464	}
	465	}
	466
e8ee6f0a	467	update_res(info, start, end, IORESOURCE_MEM, 1);
30a18d6c	468	update_range(range, start, end);
6e184f29	469	printk(KERN_CONT "\n");
30a18d6c YL	470	}
	471
	472	/* need to take out [4G, TOM2) for RAM*/
	473	/* SYS_CFG */
	474	address = MSR_K8_SYSCFG;
	475	rdmsrl(address, val);
	476	/* TOP_MEM2 is enabled? */
	477	if (val & (1<<21)) {
	478	/* TOP_MEM2 */
	479	address = MSR_K8_TOP_MEM2;
	480	rdmsrl(address, val);
	481	end = (val & 0xffffff8000000ULL);
	482	printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
	483	update_range(range, 1ULL<<32, end - 1);
	484	}
	485
	486	/*
	487	* add left over mmio range to def node/link ?
	488	* that is tricky, just record range in from start_min to 4G
	489	*/
	490	for (j = 0; j < pci_root_num; j++) {
	491	info = &pci_root_info[j];
	492	if (info->node == def_node && info->link == def_link)
	493	break;
	494	}
	495	if (j < pci_root_num) {
	496	info = &pci_root_info[j];
	497
	498	for (i = 0; i < RANGE_NUM; i++) {
	499	if (!range[i].end)
	500	continue;
	501
	502	update_res(info, range[i].start, range[i].end,
	503	IORESOURCE_MEM, 1);
	504	}
	505	}
	506
30a18d6c YL	507	for (i = 0; i < pci_root_num; i++) {
	508	int res_num;
	509	int busnum;
	510
	511	info = &pci_root_info[i];
	512	res_num = info->res_num;
	513	busnum = info->bus_min;
	514	printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
	515	info->bus_min, info->bus_max, info->node, info->link);
	516	for (j = 0; j < res_num; j++) {
	517	res = &info->res[j];
	518	printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
	519	busnum, j,
	520	(res->flags & IORESOURCE_IO)?"io port":"mmio",
	521	res->start, res->end);
	522	}
	523	}
	524
1da177e4 LT	525	return 0;
	526	}
	527
30a18d6c	528	postcore_initcall(early_fill_mp_bus_info);