Commit | Line | Data |
---|---|---|
99935a7a YL |
1 | /* |
2 | * to read io range from IOH pci conf, need to do it after mmconfig is there | |
3 | */ | |
4 | ||
5 | #include <linux/delay.h> | |
6 | #include <linux/dmi.h> | |
7 | #include <linux/pci.h> | |
8 | #include <linux/init.h> | |
9 | #include <asm/pci_x86.h> | |
10 | ||
11 | #include "bus_numa.h" | |
12 | ||
13 | static inline void print_ioh_resources(struct pci_root_info *info) | |
14 | { | |
15 | int res_num; | |
16 | int busnum; | |
17 | int i; | |
18 | ||
19 | printk(KERN_DEBUG "IOH bus: [%02x, %02x]\n", | |
20 | info->bus_min, info->bus_max); | |
21 | res_num = info->res_num; | |
22 | busnum = info->bus_min; | |
23 | for (i = 0; i < res_num; i++) { | |
24 | struct resource *res; | |
25 | ||
26 | res = &info->res[i]; | |
27 | printk(KERN_DEBUG "IOH bus: %02x index %x %s: [%llx, %llx]\n", | |
28 | busnum, i, | |
29 | (res->flags & IORESOURCE_IO) ? "io port" : | |
30 | "mmio", | |
31 | res->start, res->end); | |
32 | } | |
33 | } | |
34 | ||
35 | #define IOH_LIO 0x108 | |
36 | #define IOH_LMMIOL 0x10c | |
37 | #define IOH_LMMIOH 0x110 | |
38 | #define IOH_LMMIOH_BASEU 0x114 | |
39 | #define IOH_LMMIOH_LIMITU 0x118 | |
40 | #define IOH_LCFGBUS 0x11c | |
41 | ||
42 | static void __devinit pci_root_bus_res(struct pci_dev *dev) | |
43 | { | |
44 | u16 word; | |
45 | u32 dword; | |
46 | struct pci_root_info *info; | |
47 | u16 io_base, io_end; | |
48 | u32 mmiol_base, mmiol_end; | |
49 | u64 mmioh_base, mmioh_end; | |
50 | int bus_base, bus_end; | |
51 | ||
a557aae2 YL |
52 | /* some sys doesn't get mmconf enabled */ |
53 | if (dev->cfg_size < 0x120) | |
54 | return; | |
55 | ||
99935a7a YL |
56 | if (pci_root_num >= PCI_ROOT_NR) { |
57 | printk(KERN_DEBUG "intel_bus.c: PCI_ROOT_NR is too small\n"); | |
58 | return; | |
59 | } | |
60 | ||
61 | info = &pci_root_info[pci_root_num]; | |
62 | pci_root_num++; | |
63 | ||
64 | pci_read_config_word(dev, IOH_LCFGBUS, &word); | |
65 | bus_base = (word & 0xff); | |
66 | bus_end = (word & 0xff00) >> 8; | |
67 | sprintf(info->name, "PCI Bus #%02x", bus_base); | |
68 | info->bus_min = bus_base; | |
69 | info->bus_max = bus_end; | |
70 | ||
71 | pci_read_config_word(dev, IOH_LIO, &word); | |
72 | io_base = (word & 0xf0) << (12 - 4); | |
73 | io_end = (word & 0xf000) | 0xfff; | |
74 | update_res(info, io_base, io_end, IORESOURCE_IO, 0); | |
75 | ||
76 | pci_read_config_dword(dev, IOH_LMMIOL, &dword); | |
77 | mmiol_base = (dword & 0xff00) << (24 - 8); | |
78 | mmiol_end = (dword & 0xff000000) | 0xffffff; | |
79 | update_res(info, mmiol_base, mmiol_end, IORESOURCE_MEM, 0); | |
80 | ||
81 | pci_read_config_dword(dev, IOH_LMMIOH, &dword); | |
82 | mmioh_base = ((u64)(dword & 0xfc00)) << (26 - 10); | |
83 | mmioh_end = ((u64)(dword & 0xfc000000) | 0x3ffffff); | |
84 | pci_read_config_dword(dev, IOH_LMMIOH_BASEU, &dword); | |
85 | mmioh_base |= ((u64)(dword & 0x7ffff)) << 32; | |
86 | pci_read_config_dword(dev, IOH_LMMIOH_LIMITU, &dword); | |
87 | mmioh_end |= ((u64)(dword & 0x7ffff)) << 32; | |
88 | update_res(info, mmioh_base, mmioh_end, IORESOURCE_MEM, 0); | |
89 | ||
90 | print_ioh_resources(info); | |
91 | } | |
92 | ||
93 | /* intel IOH */ | |
94 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, pci_root_bus_res); |