Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * direct.c - Low-level direct PCI config space access | |
4 | */ | |
5 | ||
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
ec0f08ee | 8 | #include <linux/dmi.h> |
82487711 | 9 | #include <asm/pci_x86.h> |
1da177e4 LT |
10 | |
11 | /* | |
831d9918 RR |
12 | * Functions for accessing PCI base (first 256 bytes) and extended |
13 | * (4096 bytes per PCI function) configuration space with type 1 | |
14 | * accesses. | |
1da177e4 LT |
15 | */ |
16 | ||
17 | #define PCI_CONF1_ADDRESS(bus, devfn, reg) \ | |
831d9918 RR |
18 | (0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \ |
19 | | (devfn << 8) | (reg & 0xFC)) | |
1da177e4 | 20 | |
b6ce068a | 21 | static int pci_conf1_read(unsigned int seg, unsigned int bus, |
1da177e4 LT |
22 | unsigned int devfn, int reg, int len, u32 *value) |
23 | { | |
24 | unsigned long flags; | |
25 | ||
db34a363 | 26 | if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) { |
49c93e84 | 27 | *value = -1; |
1da177e4 | 28 | return -EINVAL; |
49c93e84 | 29 | } |
1da177e4 | 30 | |
d19f61f0 | 31 | raw_spin_lock_irqsave(&pci_config_lock, flags); |
1da177e4 LT |
32 | |
33 | outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); | |
34 | ||
35 | switch (len) { | |
36 | case 1: | |
37 | *value = inb(0xCFC + (reg & 3)); | |
38 | break; | |
39 | case 2: | |
40 | *value = inw(0xCFC + (reg & 2)); | |
41 | break; | |
42 | case 4: | |
43 | *value = inl(0xCFC); | |
44 | break; | |
45 | } | |
46 | ||
d19f61f0 | 47 | raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
1da177e4 LT |
48 | |
49 | return 0; | |
50 | } | |
51 | ||
b6ce068a | 52 | static int pci_conf1_write(unsigned int seg, unsigned int bus, |
1da177e4 LT |
53 | unsigned int devfn, int reg, int len, u32 value) |
54 | { | |
55 | unsigned long flags; | |
56 | ||
db34a363 | 57 | if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) |
1da177e4 LT |
58 | return -EINVAL; |
59 | ||
d19f61f0 | 60 | raw_spin_lock_irqsave(&pci_config_lock, flags); |
1da177e4 LT |
61 | |
62 | outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); | |
63 | ||
64 | switch (len) { | |
65 | case 1: | |
66 | outb((u8)value, 0xCFC + (reg & 3)); | |
67 | break; | |
68 | case 2: | |
69 | outw((u16)value, 0xCFC + (reg & 2)); | |
70 | break; | |
71 | case 4: | |
72 | outl((u32)value, 0xCFC); | |
73 | break; | |
74 | } | |
75 | ||
d19f61f0 | 76 | raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
1da177e4 LT |
77 | |
78 | return 0; | |
79 | } | |
80 | ||
81 | #undef PCI_CONF1_ADDRESS | |
82 | ||
72da0b07 | 83 | const struct pci_raw_ops pci_direct_conf1 = { |
1da177e4 LT |
84 | .read = pci_conf1_read, |
85 | .write = pci_conf1_write, | |
86 | }; | |
87 | ||
88 | ||
89 | /* | |
90 | * Functions for accessing PCI configuration space with type 2 accesses | |
91 | */ | |
92 | ||
93 | #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg) | |
94 | ||
95 | static int pci_conf2_read(unsigned int seg, unsigned int bus, | |
96 | unsigned int devfn, int reg, int len, u32 *value) | |
97 | { | |
98 | unsigned long flags; | |
99 | int dev, fn; | |
100 | ||
db34a363 | 101 | WARN_ON(seg); |
ecc16ba9 AK |
102 | if ((bus > 255) || (devfn > 255) || (reg > 255)) { |
103 | *value = -1; | |
1da177e4 | 104 | return -EINVAL; |
ecc16ba9 | 105 | } |
1da177e4 LT |
106 | |
107 | dev = PCI_SLOT(devfn); | |
108 | fn = PCI_FUNC(devfn); | |
109 | ||
110 | if (dev & 0x10) | |
111 | return PCIBIOS_DEVICE_NOT_FOUND; | |
112 | ||
d19f61f0 | 113 | raw_spin_lock_irqsave(&pci_config_lock, flags); |
1da177e4 LT |
114 | |
115 | outb((u8)(0xF0 | (fn << 1)), 0xCF8); | |
116 | outb((u8)bus, 0xCFA); | |
117 | ||
118 | switch (len) { | |
119 | case 1: | |
120 | *value = inb(PCI_CONF2_ADDRESS(dev, reg)); | |
121 | break; | |
122 | case 2: | |
123 | *value = inw(PCI_CONF2_ADDRESS(dev, reg)); | |
124 | break; | |
125 | case 4: | |
126 | *value = inl(PCI_CONF2_ADDRESS(dev, reg)); | |
127 | break; | |
128 | } | |
129 | ||
130 | outb(0, 0xCF8); | |
131 | ||
d19f61f0 | 132 | raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
1da177e4 LT |
133 | |
134 | return 0; | |
135 | } | |
136 | ||
137 | static int pci_conf2_write(unsigned int seg, unsigned int bus, | |
138 | unsigned int devfn, int reg, int len, u32 value) | |
139 | { | |
140 | unsigned long flags; | |
141 | int dev, fn; | |
142 | ||
db34a363 | 143 | WARN_ON(seg); |
1da177e4 LT |
144 | if ((bus > 255) || (devfn > 255) || (reg > 255)) |
145 | return -EINVAL; | |
146 | ||
147 | dev = PCI_SLOT(devfn); | |
148 | fn = PCI_FUNC(devfn); | |
149 | ||
150 | if (dev & 0x10) | |
151 | return PCIBIOS_DEVICE_NOT_FOUND; | |
152 | ||
d19f61f0 | 153 | raw_spin_lock_irqsave(&pci_config_lock, flags); |
1da177e4 LT |
154 | |
155 | outb((u8)(0xF0 | (fn << 1)), 0xCF8); | |
156 | outb((u8)bus, 0xCFA); | |
157 | ||
158 | switch (len) { | |
159 | case 1: | |
160 | outb((u8)value, PCI_CONF2_ADDRESS(dev, reg)); | |
161 | break; | |
162 | case 2: | |
163 | outw((u16)value, PCI_CONF2_ADDRESS(dev, reg)); | |
164 | break; | |
165 | case 4: | |
166 | outl((u32)value, PCI_CONF2_ADDRESS(dev, reg)); | |
167 | break; | |
168 | } | |
169 | ||
170 | outb(0, 0xCF8); | |
171 | ||
d19f61f0 | 172 | raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
1da177e4 LT |
173 | |
174 | return 0; | |
175 | } | |
176 | ||
177 | #undef PCI_CONF2_ADDRESS | |
178 | ||
72da0b07 | 179 | static const struct pci_raw_ops pci_direct_conf2 = { |
1da177e4 LT |
180 | .read = pci_conf2_read, |
181 | .write = pci_conf2_write, | |
182 | }; | |
183 | ||
184 | ||
185 | /* | |
186 | * Before we decide to use direct hardware access mechanisms, we try to do some | |
187 | * trivial checks to ensure it at least _seems_ to be working -- we just test | |
188 | * whether bus 00 contains a host bridge (this is similar to checking | |
189 | * techniques used in XFree86, but ours should be more reliable since we | |
190 | * attempt to make use of direct access hints provided by the PCI BIOS). | |
191 | * | |
192 | * This should be close to trivial, but it isn't, because there are buggy | |
193 | * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. | |
194 | */ | |
72da0b07 | 195 | static int __init pci_sanity_check(const struct pci_raw_ops *o) |
1da177e4 LT |
196 | { |
197 | u32 x = 0; | |
69c42d49 | 198 | int devfn; |
1da177e4 LT |
199 | |
200 | if (pci_probe & PCI_NO_CHECKS) | |
201 | return 1; | |
ec0f08ee AK |
202 | /* Assume Type 1 works for newer systems. |
203 | This handles machines that don't have anything on PCI Bus 0. */ | |
69c42d49 | 204 | if (dmi_get_bios_year() >= 2001) |
ec0f08ee | 205 | return 1; |
1da177e4 LT |
206 | |
207 | for (devfn = 0; devfn < 0x100; devfn++) { | |
208 | if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x)) | |
209 | continue; | |
210 | if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA) | |
211 | return 1; | |
212 | ||
213 | if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x)) | |
214 | continue; | |
215 | if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ) | |
216 | return 1; | |
217 | } | |
218 | ||