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91d8037f DB |
1 | /* |
2 | * GPL LICENSE SUMMARY | |
3 | * | |
4 | * Copyright(c) 2010 Intel Corporation. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of version 2 of the GNU General Public License as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | * The full GNU General Public License is included in this distribution | |
19 | * in the file called LICENSE.GPL. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Corporation | |
23 | * 2200 Mission College Blvd. | |
24 | * Santa Clara, CA 97052 | |
25 | * | |
26 | * This provides access methods for PCI registers that mis-behave on | |
27 | * the CE4100. Each register can be assigned a private init, read and | |
28 | * write routine. The exception to this is the bridge device. The | |
29 | * bridge device is the only device on bus zero (0) that requires any | |
30 | * fixup so it is a special case ATM | |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/init.h> | |
36 | ||
03150171 | 37 | #include <asm/ce4100.h> |
91d8037f DB |
38 | #include <asm/pci_x86.h> |
39 | ||
40 | struct sim_reg { | |
41 | u32 value; | |
42 | u32 mask; | |
43 | }; | |
44 | ||
45 | struct sim_dev_reg { | |
46 | int dev_func; | |
47 | int reg; | |
48 | void (*init)(struct sim_dev_reg *reg); | |
49 | void (*read)(struct sim_dev_reg *reg, u32 *value); | |
50 | void (*write)(struct sim_dev_reg *reg, u32 value); | |
51 | struct sim_reg sim_reg; | |
52 | }; | |
53 | ||
54 | struct sim_reg_op { | |
55 | void (*init)(struct sim_dev_reg *reg); | |
56 | void (*read)(struct sim_dev_reg *reg, u32 value); | |
57 | void (*write)(struct sim_dev_reg *reg, u32 value); | |
58 | }; | |
59 | ||
60 | #define MB (1024 * 1024) | |
61 | #define KB (1024) | |
62 | #define SIZE_TO_MASK(size) (~(size - 1)) | |
63 | ||
64 | #define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\ | |
65 | { PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\ | |
66 | {0, SIZE_TO_MASK(size)} }, | |
67 | ||
68 | static void reg_init(struct sim_dev_reg *reg) | |
69 | { | |
70 | pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4, | |
71 | ®->sim_reg.value); | |
72 | } | |
73 | ||
74 | static void reg_read(struct sim_dev_reg *reg, u32 *value) | |
75 | { | |
76 | unsigned long flags; | |
77 | ||
78 | raw_spin_lock_irqsave(&pci_config_lock, flags); | |
79 | *value = reg->sim_reg.value; | |
80 | raw_spin_unlock_irqrestore(&pci_config_lock, flags); | |
81 | } | |
82 | ||
83 | static void reg_write(struct sim_dev_reg *reg, u32 value) | |
84 | { | |
85 | unsigned long flags; | |
86 | ||
87 | raw_spin_lock_irqsave(&pci_config_lock, flags); | |
88 | reg->sim_reg.value = (value & reg->sim_reg.mask) | | |
89 | (reg->sim_reg.value & ~reg->sim_reg.mask); | |
90 | raw_spin_unlock_irqrestore(&pci_config_lock, flags); | |
91 | } | |
92 | ||
93 | static void sata_reg_init(struct sim_dev_reg *reg) | |
94 | { | |
95 | pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4, | |
96 | ®->sim_reg.value); | |
97 | reg->sim_reg.value += 0x400; | |
98 | } | |
99 | ||
100 | static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value) | |
101 | { | |
102 | reg_read(reg, value); | |
103 | if (*value != reg->sim_reg.mask) | |
104 | *value |= 0x100; | |
105 | } | |
106 | ||
107 | void sata_revid_init(struct sim_dev_reg *reg) | |
108 | { | |
109 | reg->sim_reg.value = 0x01060100; | |
110 | reg->sim_reg.mask = 0; | |
111 | } | |
112 | ||
113 | static void sata_revid_read(struct sim_dev_reg *reg, u32 *value) | |
114 | { | |
115 | reg_read(reg, value); | |
116 | } | |
117 | ||
37aeec36 MB |
118 | static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value) |
119 | { | |
120 | unsigned long flags; | |
121 | ||
122 | raw_spin_lock_irqsave(&pci_config_lock, flags); | |
123 | /* force interrupt pin value to 0 */ | |
124 | *value = reg->sim_reg.value & 0xfff00ff; | |
125 | raw_spin_unlock_irqrestore(&pci_config_lock, flags); | |
126 | } | |
127 | ||
91d8037f DB |
128 | static struct sim_dev_reg bus1_fixups[] = { |
129 | DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write) | |
130 | DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write) | |
131 | DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write) | |
132 | DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) | |
133 | DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) | |
134 | DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write) | |
135 | DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write) | |
136 | DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write) | |
137 | DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write) | |
138 | DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write) | |
139 | DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write) | |
140 | DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write) | |
141 | DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write) | |
142 | DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write) | |
143 | DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write) | |
144 | DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write) | |
145 | DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write) | |
146 | DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write) | |
147 | DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write) | |
148 | DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write) | |
149 | DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write) | |
150 | DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write) | |
151 | DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write) | |
152 | DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write) | |
153 | DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write) | |
154 | DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write) | |
155 | DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write) | |
156 | DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write) | |
37aeec36 | 157 | DEFINE_REG(11, 7, 0x3c, 256, reg_init, reg_noirq_read, reg_write) |
91d8037f DB |
158 | DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) |
159 | DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write) | |
160 | DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write) | |
161 | DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write) | |
162 | DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write) | |
163 | DEFINE_REG(14, 0, 0x8, 0, sata_revid_init, sata_revid_read, 0) | |
164 | DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write) | |
165 | DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write) | |
166 | DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write) | |
167 | DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write) | |
168 | DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write) | |
169 | DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write) | |
170 | DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) | |
171 | DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write) | |
172 | DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) | |
173 | DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write) | |
174 | DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write) | |
37aeec36 | 175 | DEFINE_REG(16, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write) |
91d8037f DB |
176 | DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) |
177 | DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write) | |
37aeec36 | 178 | DEFINE_REG(18, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write) |
91d8037f DB |
179 | }; |
180 | ||
181 | static void __init init_sim_regs(void) | |
182 | { | |
183 | int i; | |
184 | ||
185 | for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { | |
186 | if (bus1_fixups[i].init) | |
187 | bus1_fixups[i].init(&bus1_fixups[i]); | |
188 | } | |
189 | } | |
190 | ||
191 | static inline void extract_bytes(u32 *value, int reg, int len) | |
192 | { | |
193 | uint32_t mask; | |
194 | ||
195 | *value >>= ((reg & 3) * 8); | |
196 | mask = 0xFFFFFFFF >> ((4 - len) * 8); | |
197 | *value &= mask; | |
198 | } | |
199 | ||
200 | int bridge_read(unsigned int devfn, int reg, int len, u32 *value) | |
201 | { | |
202 | u32 av_bridge_base, av_bridge_limit; | |
203 | int retval = 0; | |
204 | ||
205 | switch (reg) { | |
206 | /* Make BARs appear to not request any memory. */ | |
207 | case PCI_BASE_ADDRESS_0: | |
208 | case PCI_BASE_ADDRESS_0 + 1: | |
209 | case PCI_BASE_ADDRESS_0 + 2: | |
210 | case PCI_BASE_ADDRESS_0 + 3: | |
211 | *value = 0; | |
212 | break; | |
213 | ||
214 | /* Since subordinate bus number register is hardwired | |
215 | * to zero and read only, so do the simulation. | |
216 | */ | |
217 | case PCI_PRIMARY_BUS: | |
218 | if (len == 4) | |
219 | *value = 0x00010100; | |
220 | break; | |
221 | ||
222 | case PCI_SUBORDINATE_BUS: | |
223 | *value = 1; | |
224 | break; | |
225 | ||
226 | case PCI_MEMORY_BASE: | |
227 | case PCI_MEMORY_LIMIT: | |
228 | /* Get the A/V bridge base address. */ | |
229 | pci_direct_conf1.read(0, 0, devfn, | |
230 | PCI_BASE_ADDRESS_0, 4, &av_bridge_base); | |
231 | ||
232 | av_bridge_limit = av_bridge_base + (512*MB - 1); | |
233 | av_bridge_limit >>= 16; | |
234 | av_bridge_limit &= 0xFFF0; | |
235 | ||
236 | av_bridge_base >>= 16; | |
237 | av_bridge_base &= 0xFFF0; | |
238 | ||
239 | if (reg == PCI_MEMORY_LIMIT) | |
240 | *value = av_bridge_limit; | |
241 | else if (len == 2) | |
242 | *value = av_bridge_base; | |
243 | else | |
244 | *value = (av_bridge_limit << 16) | av_bridge_base; | |
245 | break; | |
246 | /* Make prefetchable memory limit smaller than prefetchable | |
247 | * memory base, so not claim prefetchable memory space. | |
248 | */ | |
249 | case PCI_PREF_MEMORY_BASE: | |
250 | *value = 0xFFF0; | |
251 | break; | |
252 | case PCI_PREF_MEMORY_LIMIT: | |
253 | *value = 0x0; | |
254 | break; | |
255 | /* Make IO limit smaller than IO base, so not claim IO space. */ | |
256 | case PCI_IO_BASE: | |
257 | *value = 0xF0; | |
258 | break; | |
259 | case PCI_IO_LIMIT: | |
260 | *value = 0; | |
261 | break; | |
262 | default: | |
263 | retval = 1; | |
264 | } | |
265 | return retval; | |
266 | } | |
267 | ||
268 | static int ce4100_conf_read(unsigned int seg, unsigned int bus, | |
269 | unsigned int devfn, int reg, int len, u32 *value) | |
270 | { | |
13884c66 | 271 | int i; |
91d8037f | 272 | |
db34a363 | 273 | WARN_ON(seg); |
91d8037f DB |
274 | if (bus == 1) { |
275 | for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { | |
276 | if (bus1_fixups[i].dev_func == devfn && | |
277 | bus1_fixups[i].reg == (reg & ~3) && | |
278 | bus1_fixups[i].read) { | |
279 | bus1_fixups[i].read(&(bus1_fixups[i]), | |
280 | value); | |
281 | extract_bytes(value, reg, len); | |
282 | return 0; | |
283 | } | |
284 | } | |
285 | } | |
286 | ||
287 | if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) && | |
288 | !bridge_read(devfn, reg, len, value)) | |
289 | return 0; | |
290 | ||
291 | return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); | |
292 | } | |
293 | ||
294 | static int ce4100_conf_write(unsigned int seg, unsigned int bus, | |
295 | unsigned int devfn, int reg, int len, u32 value) | |
296 | { | |
297 | int i; | |
298 | ||
db34a363 | 299 | WARN_ON(seg); |
91d8037f DB |
300 | if (bus == 1) { |
301 | for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { | |
302 | if (bus1_fixups[i].dev_func == devfn && | |
303 | bus1_fixups[i].reg == (reg & ~3) && | |
304 | bus1_fixups[i].write) { | |
305 | bus1_fixups[i].write(&(bus1_fixups[i]), | |
306 | value); | |
307 | return 0; | |
308 | } | |
309 | } | |
310 | } | |
311 | ||
312 | /* Discard writes to A/V bridge BAR. */ | |
313 | if (bus == 0 && PCI_DEVFN(1, 0) == devfn && | |
314 | ((reg & ~3) == PCI_BASE_ADDRESS_0)) | |
315 | return 0; | |
316 | ||
317 | return pci_direct_conf1.write(seg, bus, devfn, reg, len, value); | |
318 | } | |
319 | ||
72da0b07 | 320 | static const struct pci_raw_ops ce4100_pci_conf = { |
91d8037f DB |
321 | .read = ce4100_conf_read, |
322 | .write = ce4100_conf_write, | |
323 | }; | |
324 | ||
03150171 | 325 | int __init ce4100_pci_init(void) |
91d8037f DB |
326 | { |
327 | init_sim_regs(); | |
328 | raw_pci_ops = &ce4100_pci_conf; | |
03150171 SAS |
329 | /* Indicate caller that it should invoke pci_legacy_init() */ |
330 | return 1; | |
91d8037f | 331 | } |