[linux-2.6-block.git] / arch / x86 / pci / amd_bus.c

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/topology.h>
#include <linux/cpu.h>
#include <linux/range.h>

#include <asm/amd_nb.h>
#include <asm/pci_x86.h>

#include <asm/pci-direct.h>

#include "bus_numa.h"

/*
 * This discovers the pcibus <-> node mapping on AMD K8.
 * also get peer root bus resource for io,mmio
 */

struct pci_hostbridge_probe {
	u32 bus;
	u32 slot;
	u32 vendor;
	u32 device;
};

static struct pci_hostbridge_probe pci_probes[] __initdata = {
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 }, /* K8 */
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 }, /* Fam10h */
	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 }, /* Fam10h */
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 }, /* Fam11h */
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1600 }, /* Fam15h */
};

#define RANGE_NUM 16

static struct pci_root_info __init *find_pci_root_info(int node, int link)
{
	struct pci_root_info *info;

	/* find the position */
	list_for_each_entry(info, &pci_root_infos, list)
		if (info->node == node && info->link == link)
			return info;

	return NULL;
}

/**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 * Registers found in the K8 northbridge
 */
static int __init early_fill_mp_bus_info(void)
{
	int i;
	unsigned bus;
	unsigned slot;
	int node;
	int link;
	int def_node;
	int def_link;
	struct pci_root_info *info;
	u32 reg;
	u64 start;
	u64 end;
	struct range range[RANGE_NUM];
	u64 val;
	u32 address;
	bool found;
	struct resource fam10h_mmconf_res, *fam10h_mmconf;
	u64 fam10h_mmconf_start;
	u64 fam10h_mmconf_end;

	if (!early_pci_allowed())
		return -1;

	found = false;
	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
		u32 id;
		u16 device;
		u16 vendor;

		bus = pci_probes[i].bus;
		slot = pci_probes[i].slot;
		id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);

		vendor = id & 0xffff;
		device = (id>>16) & 0xffff;
		if (pci_probes[i].vendor == vendor &&
		    pci_probes[i].device == device) {
			found = true;
			break;
		}
	}

	if (!found)
		return 0;

	/*
	 * We should learn topology and routing information from _PXM and
	 * _CRS methods in the ACPI namespace.  We extract node numbers
	 * here to work around BIOSes that don't supply _PXM.
	 */
	for (i = 0; i < 4; i++) {
		int min_bus;
		int max_bus;
		reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));

		/* Check if that register is enabled for bus range */
		if ((reg & 7) != 3)
			continue;

		min_bus = (reg >> 16) & 0xff;
		max_bus = (reg >> 24) & 0xff;
		node = (reg >> 4) & 0x07;
		link = (reg >> 8) & 0x03;

		info = alloc_pci_root_info(min_bus, max_bus, node, link);
	}

	/*
	 * The following code extracts routing information for use on old
	 * systems where Linux doesn't automatically use host bridge _CRS
	 * methods (or when the user specifies "pci=nocrs").
	 *
	 * We only do this through Fam11h, because _CRS should be enough on
	 * newer systems.
	 */
	if (boot_cpu_data.x86 > 0x11)
		return 0;

	/* get the default node and link for left over res */
	reg = read_pci_config(bus, slot, 0, 0x60);
	def_node = (reg >> 8) & 0x07;
	reg = read_pci_config(bus, slot, 0, 0x64);
	def_link = (reg >> 8) & 0x03;

	memset(range, 0, sizeof(range));
	add_range(range, RANGE_NUM, 0, 0, 0xffff + 1);
	/* io port resource */
	for (i = 0; i < 4; i++) {
		reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xfff000;
		reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xfff000) | 0xfff;

		info = find_pci_root_info(node, link);
		if (!info)
			continue; /* not found */

		printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
		       node, link, start, end);

		/* kernel only handle 16 bit only */
		if (end > 0xffff)
			end = 0xffff;
		update_res(info, start, end, IORESOURCE_IO, 1);
		subtract_range(range, RANGE_NUM, start, end + 1);
	}
	/* add left over io port range to def node/link, [0, 0xffff] */
	/* find the position */
	info = find_pci_root_info(def_node, def_link);
	if (info) {
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end - 1,
				   IORESOURCE_IO, 1);
		}
	}

	memset(range, 0, sizeof(range));
	/* 0xfd00000000-0xffffffffff for HT */
	end = cap_resource((0xfdULL<<32) - 1);
	end++;
	add_range(range, RANGE_NUM, 0, 0, end);

	/* need to take out [0, TOM) for RAM*/
	address = MSR_K8_TOP_MEM1;
	rdmsrl(address, val);
	end = (val & 0xffffff800000ULL);
	printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
	if (end < (1ULL<<32))
		subtract_range(range, RANGE_NUM, 0, end);

	/* get mmconfig */
	fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
	/* need to take out mmconf range */
	if (fam10h_mmconf) {
		printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
		fam10h_mmconf_start = fam10h_mmconf->start;
		fam10h_mmconf_end = fam10h_mmconf->end;
		subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
				 fam10h_mmconf_end + 1);
	} else {
		fam10h_mmconf_start = 0;
		fam10h_mmconf_end = 0;
	}

	/* mmio resource */
	for (i = 0; i < 8; i++) {
		reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xffffff00; /* 39:16 on 31:8*/
		start <<= 8;
		reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xffffff00);
		end <<= 8;
		end |= 0xffff;

		info = find_pci_root_info(node, link);

		if (!info)
			continue;

		printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
		       node, link, start, end);
		/*
		 * some sick allocation would have range overlap with fam10h
		 * mmconf range, so need to update start and end.
		 */
		if (fam10h_mmconf_end) {
			int changed = 0;
			u64 endx = 0;
			if (start >= fam10h_mmconf_start &&
			    start <= fam10h_mmconf_end) {
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}

			if (end >= fam10h_mmconf_start &&
			    end <= fam10h_mmconf_end) {
				end = fam10h_mmconf_start - 1;
				changed = 1;
			}

			if (start < fam10h_mmconf_start &&
			    end > fam10h_mmconf_end) {
				/* we got a hole */
				endx = fam10h_mmconf_start - 1;
				update_res(info, start, endx, IORESOURCE_MEM, 0);
				subtract_range(range, RANGE_NUM, start,
						 endx + 1);
				printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}
			if (changed) {
				if (start <= end) {
					printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
				} else {
					printk(KERN_CONT "%s\n", endx?"":" ==> none");
					continue;
				}
			}
		}

		update_res(info, cap_resource(start), cap_resource(end),
				 IORESOURCE_MEM, 1);
		subtract_range(range, RANGE_NUM, start, end + 1);
		printk(KERN_CONT "\n");
	}

	/* need to take out [4G, TOM2) for RAM*/
	/* SYS_CFG */
	address = MSR_K8_SYSCFG;
	rdmsrl(address, val);
	/* TOP_MEM2 is enabled? */
	if (val & (1<<21)) {
		/* TOP_MEM2 */
		address = MSR_K8_TOP_MEM2;
		rdmsrl(address, val);
		end = (val & 0xffffff800000ULL);
		printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
		subtract_range(range, RANGE_NUM, 1ULL<<32, end);
	}

	/*
	 * add left over mmio range to def node/link ?
	 * that is tricky, just record range in from start_min to 4G
	 */
	info = find_pci_root_info(def_node, def_link);
	if (info) {
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, cap_resource(range[i].start),
				   cap_resource(range[i].end - 1),
				   IORESOURCE_MEM, 1);
		}
	}

	list_for_each_entry(info, &pci_root_infos, list) {
		int busnum;
		struct pci_root_res *root_res;

		busnum = info->busn.start;
		printk(KERN_DEBUG "bus: %pR on node %x link %x\n",
		       &info->busn, info->node, info->link);
		list_for_each_entry(root_res, &info->resources, list)
			printk(KERN_DEBUG "bus: %02x %pR\n",
				       busnum, &root_res->res);
	}

	return 0;
}

#define ENABLE_CF8_EXT_CFG      (1ULL << 46)

static void enable_pci_io_ecs(void *unused)
{
	u64 reg;
	rdmsrl(MSR_AMD64_NB_CFG, reg);
	if (!(reg & ENABLE_CF8_EXT_CFG)) {
		reg |= ENABLE_CF8_EXT_CFG;
		wrmsrl(MSR_AMD64_NB_CFG, reg);
	}
}

static int amd_cpu_notify(struct notifier_block *self, unsigned long action,
			  void *hcpu)
{
	int cpu = (long)hcpu;
	switch (action) {
	case CPU_ONLINE:
	case CPU_ONLINE_FROZEN:
		smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
		break;
	default:
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block amd_cpu_notifier = {
	.notifier_call	= amd_cpu_notify,
};

static void __init pci_enable_pci_io_ecs(void)
{
#ifdef CONFIG_AMD_NB
	unsigned int i, n;

	for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
		u8 bus = amd_nb_bus_dev_ranges[i].bus;
		u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
		u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;

		for (; slot < limit; ++slot) {
			u32 val = read_pci_config(bus, slot, 3, 0);

			if (!early_is_amd_nb(val))
				continue;

			val = read_pci_config(bus, slot, 3, 0x8c);
			if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
				val |= ENABLE_CF8_EXT_CFG >> 32;
				write_pci_config(bus, slot, 3, 0x8c, val);
			}
			++n;
		}
	}
#endif
}

static int __init pci_io_ecs_init(void)
{
	int cpu;

	/* assume all cpus from fam10h have IO ECS */
        if (boot_cpu_data.x86 < 0x10)
		return 0;

	/* Try the PCI method first. */
	if (early_pci_allowed())
		pci_enable_pci_io_ecs();

	cpu_notifier_register_begin();
	for_each_online_cpu(cpu)
		amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
			       (void *)(long)cpu);
	__register_cpu_notifier(&amd_cpu_notifier);
	cpu_notifier_register_done();

	pci_probe |= PCI_HAS_IO_ECS;

	return 0;
}

static int __init amd_postcore_init(void)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return 0;

	early_fill_mp_bus_info();
	pci_io_ecs_init();

	return 0;
}

postcore_initcall(amd_postcore_init);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
1da177e4 LT	2	#include <linux/pci.h>
d199a048	3	#include <linux/topology.h>
91ede005	4	#include <linux/cpu.h>
27811d8c YL	5	#include <linux/range.h>
27811d8c YL	6
24d9b70b	7	#include <asm/amd_nb.h>
82487711	8	#include <asm/pci_x86.h>
3a27dd1c	9
871d5f8d	10	#include <asm/pci-direct.h>
1da177e4	11
99935a7a YL	12	#include "bus_numa.h"
99935a7a YL	13
1da177e4 LT	14	/*
1da177e4 LT	15	* This discovers the pcibus <-> node mapping on AMD K8.
30a18d6c	16	* also get peer root bus resource for io,mmio
1da177e4 LT	17	*/
1da177e4 LT	18
30a18d6c YL	19	struct pci_hostbridge_probe {
	20	u32 bus;
	21	u32 slot;
	22	u32 vendor;
	23	u32 device;
	24	};
	25
	26	static struct pci_hostbridge_probe pci_probes[] __initdata = {
94d4bb5b SS	27	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 }, /* K8 */
	28	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 }, /* Fam10h */
	29	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 }, /* Fam10h */
	30	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 }, /* Fam11h */
	31	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1600 }, /* Fam15h */
30a18d6c YL	32	};
30a18d6c YL	33
27811d8c YL	34	#define RANGE_NUM 16
27811d8c YL	35
d28e5ac2 YL	36	static struct pci_root_info __init *find_pci_root_info(int node, int link)
	37	{
	38	struct pci_root_info *info;
	39
	40	/* find the position */
	41	list_for_each_entry(info, &pci_root_infos, list)
	42	if (info->node == node && info->link == link)
	43	return info;
	44
	45	return NULL;
	46	}
	47
1da177e4	48	/**
871d5f8d YL	49	* early_fill_mp_bus_to_node()
871d5f8d YL	50	* called before pcibios_scan_root and pci_scan_bus
1da177e4 LT	51	* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
	52	* Registers found in the K8 northbridge
	53	*/
30a18d6c	54	static int __init early_fill_mp_bus_info(void)
1da177e4	55	{
30a18d6c	56	int i;
30a18d6c	57	unsigned bus;
871d5f8d	58	unsigned slot;
35ddd068	59	int node;
30a18d6c YL	60	int link;
	61	int def_node;
	62	int def_link;
	63	struct pci_root_info *info;
	64	u32 reg;
97445c3b YL	65	u64 start;
97445c3b YL	66	u64 end;
27811d8c	67	struct range range[RANGE_NUM];
30a18d6c YL	68	u64 val;
30a18d6c YL	69	u32 address;
3e3da00c	70	bool found;
24d25dbf BH	71	struct resource fam10h_mmconf_res, *fam10h_mmconf;
	72	u64 fam10h_mmconf_start;
	73	u64 fam10h_mmconf_end;
1da177e4	74
871d5f8d YL	75	if (!early_pci_allowed())
	76	return -1;
	77
3e3da00c	78	found = false;
30a18d6c YL	79	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
	80	u32 id;
	81	u16 device;
	82	u16 vendor;
35ddd068	83
30a18d6c YL	84	bus = pci_probes[i].bus;
	85	slot = pci_probes[i].slot;
	86	id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
35ddd068	87
30a18d6c YL	88	vendor = id & 0xffff;
	89	device = (id>>16) & 0xffff;
	90	if (pci_probes[i].vendor == vendor &&
	91	pci_probes[i].device == device) {
3e3da00c	92	found = true;
30a18d6c YL	93	break;
	94	}
	95	}
	96
3e3da00c	97	if (!found)
30a18d6c	98	return 0;
35ddd068	99
94d4bb5b SS	100	/*
	101	* We should learn topology and routing information from _PXM and
	102	* _CRS methods in the ACPI namespace. We extract node numbers
	103	* here to work around BIOSes that don't supply _PXM.
	104	*/
30a18d6c YL	105	for (i = 0; i < 4; i++) {
	106	int min_bus;
	107	int max_bus;
	108	reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
35ddd068 YL	109
35ddd068 YL	110	/* Check if that register is enabled for bus range */
30a18d6c	111	if ((reg & 7) != 3)
35ddd068 YL	112	continue;
35ddd068 YL	113
30a18d6c YL	114	min_bus = (reg >> 16) & 0xff;
	115	max_bus = (reg >> 24) & 0xff;
	116	node = (reg >> 4) & 0x07;
30a18d6c YL	117	link = (reg >> 8) & 0x03;
30a18d6c YL	118
d28e5ac2	119	info = alloc_pci_root_info(min_bus, max_bus, node, link);
1da177e4 LT	120	}
1da177e4 LT	121
94d4bb5b SS	122	/*
	123	* The following code extracts routing information for use on old
	124	* systems where Linux doesn't automatically use host bridge _CRS
	125	* methods (or when the user specifies "pci=nocrs").
	126	*
	127	* We only do this through Fam11h, because _CRS should be enough on
	128	* newer systems.
	129	*/
	130	if (boot_cpu_data.x86 > 0x11)
	131	return 0;
	132
30a18d6c YL	133	/* get the default node and link for left over res */
	134	reg = read_pci_config(bus, slot, 0, 0x60);
	135	def_node = (reg >> 8) & 0x07;
	136	reg = read_pci_config(bus, slot, 0, 0x64);
	137	def_link = (reg >> 8) & 0x03;
	138
	139	memset(range, 0, sizeof(range));
e9a0064a	140	add_range(range, RANGE_NUM, 0, 0, 0xffff + 1);
30a18d6c YL	141	/* io port resource */
	142	for (i = 0; i < 4; i++) {
	143	reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
	144	if (!(reg & 3))
	145	continue;
	146
	147	start = reg & 0xfff000;
	148	reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
	149	node = reg & 0x07;
	150	link = (reg >> 4) & 0x03;
	151	end = (reg & 0xfff000) \| 0xfff;
	152
d28e5ac2 YL	153	info = find_pci_root_info(node, link);
d28e5ac2 YL	154	if (!info)
30a18d6c YL	155	continue; /* not found */
30a18d6c YL	156
6e184f29	157	printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
97445c3b	158	node, link, start, end);
e8ee6f0a YL	159
	160	/* kernel only handle 16 bit only */
	161	if (end > 0xffff)
	162	end = 0xffff;
	163	update_res(info, start, end, IORESOURCE_IO, 1);
e9a0064a	164	subtract_range(range, RANGE_NUM, start, end + 1);
30a18d6c YL	165	}
	166	/* add left over io port range to def node/link, [0, 0xffff] */
	167	/* find the position */
d28e5ac2 YL	168	info = find_pci_root_info(def_node, def_link);
d28e5ac2 YL	169	if (info) {
30a18d6c YL	170	for (i = 0; i < RANGE_NUM; i++) {
	171	if (!range[i].end)
	172	continue;
	173
e9a0064a	174	update_res(info, range[i].start, range[i].end - 1,
30a18d6c YL	175	IORESOURCE_IO, 1);
	176	}
	177	}
	178
	179	memset(range, 0, sizeof(range));
	180	/* 0xfd00000000-0xffffffffff for HT */
e9a0064a YL	181	end = cap_resource((0xfdULL<<32) - 1);
	182	end++;
	183	add_range(range, RANGE_NUM, 0, 0, end);
30a18d6c YL	184
	185	/* need to take out [0, TOM) for RAM*/
	186	address = MSR_K8_TOP_MEM1;
	187	rdmsrl(address, val);
8004dd96	188	end = (val & 0xffffff800000ULL);
97445c3b	189	printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
30a18d6c	190	if (end < (1ULL<<32))
e9a0064a	191	subtract_range(range, RANGE_NUM, 0, end);
30a18d6c	192
6e184f29	193	/* get mmconfig */
24d25dbf	194	fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
6e184f29	195	/* need to take out mmconf range */
24d25dbf BH	196	if (fam10h_mmconf) {
	197	printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
	198	fam10h_mmconf_start = fam10h_mmconf->start;
	199	fam10h_mmconf_end = fam10h_mmconf->end;
e9a0064a YL	200	subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
e9a0064a YL	201	fam10h_mmconf_end + 1);
24d25dbf BH	202	} else {
	203	fam10h_mmconf_start = 0;
	204	fam10h_mmconf_end = 0;
6e184f29 YL	205	}
6e184f29 YL	206
30a18d6c YL	207	/* mmio resource */
	208	for (i = 0; i < 8; i++) {
	209	reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
	210	if (!(reg & 3))
	211	continue;
	212
	213	start = reg & 0xffffff00; /* 39:16 on 31:8*/
	214	start <<= 8;
	215	reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
	216	node = reg & 0x07;
	217	link = (reg >> 4) & 0x03;
	218	end = (reg & 0xffffff00);
	219	end <<= 8;
	220	end \|= 0xffff;
	221
d28e5ac2	222	info = find_pci_root_info(node, link);
30a18d6c	223
d28e5ac2 YL	224	if (!info)
d28e5ac2 YL	225	continue;
6e184f29 YL	226
6e184f29 YL	227	printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
97445c3b	228	node, link, start, end);
6e184f29 YL	229	/*
	230	* some sick allocation would have range overlap with fam10h
	231	* mmconf range, so need to update start and end.
	232	*/
	233	if (fam10h_mmconf_end) {
	234	int changed = 0;
	235	u64 endx = 0;
	236	if (start >= fam10h_mmconf_start &&
	237	start <= fam10h_mmconf_end) {
	238	start = fam10h_mmconf_end + 1;
	239	changed = 1;
	240	}
	241
	242	if (end >= fam10h_mmconf_start &&
	243	end <= fam10h_mmconf_end) {
	244	end = fam10h_mmconf_start - 1;
	245	changed = 1;
	246	}
	247
	248	if (start < fam10h_mmconf_start &&
	249	end > fam10h_mmconf_end) {
	250	/* we got a hole */
	251	endx = fam10h_mmconf_start - 1;
	252	update_res(info, start, endx, IORESOURCE_MEM, 0);
e9a0064a YL	253	subtract_range(range, RANGE_NUM, start,
e9a0064a YL	254	endx + 1);
97445c3b	255	printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
6e184f29 YL	256	start = fam10h_mmconf_end + 1;
	257	changed = 1;
	258	}
	259	if (changed) {
	260	if (start <= end) {
97445c3b	261	printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
6e184f29 YL	262	} else {
	263	printk(KERN_CONT "%s\n", endx?"":" ==> none");
	264	continue;
	265	}
	266	}
	267	}
	268
9ad3f2c7 YL	269	update_res(info, cap_resource(start), cap_resource(end),
9ad3f2c7 YL	270	IORESOURCE_MEM, 1);
e9a0064a	271	subtract_range(range, RANGE_NUM, start, end + 1);
6e184f29	272	printk(KERN_CONT "\n");
30a18d6c YL	273	}
	274
	275	/* need to take out [4G, TOM2) for RAM*/
	276	/* SYS_CFG */
	277	address = MSR_K8_SYSCFG;
	278	rdmsrl(address, val);
	279	/* TOP_MEM2 is enabled? */
	280	if (val & (1<<21)) {
	281	/* TOP_MEM2 */
	282	address = MSR_K8_TOP_MEM2;
	283	rdmsrl(address, val);
8004dd96	284	end = (val & 0xffffff800000ULL);
97445c3b	285	printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
e9a0064a	286	subtract_range(range, RANGE_NUM, 1ULL<<32, end);
30a18d6c YL	287	}
	288
	289	/*
	290	* add left over mmio range to def node/link ?
	291	* that is tricky, just record range in from start_min to 4G
	292	*/
d28e5ac2 YL	293	info = find_pci_root_info(def_node, def_link);
d28e5ac2 YL	294	if (info) {
30a18d6c YL	295	for (i = 0; i < RANGE_NUM; i++) {
	296	if (!range[i].end)
	297	continue;
	298
9ad3f2c7	299	update_res(info, cap_resource(range[i].start),
e9a0064a	300	cap_resource(range[i].end - 1),
30a18d6c YL	301	IORESOURCE_MEM, 1);
	302	}
	303	}
	304
d28e5ac2	305	list_for_each_entry(info, &pci_root_infos, list) {
30a18d6c	306	int busnum;
d28e5ac2	307	struct pci_root_res *root_res;
30a18d6c	308
a10bb128 YL	309	busnum = info->busn.start;
	310	printk(KERN_DEBUG "bus: %pR on node %x link %x\n",
	311	&info->busn, info->node, info->link);
d28e5ac2 YL	312	list_for_each_entry(root_res, &info->resources, list)
	313	printk(KERN_DEBUG "bus: %02x %pR\n",
	314	busnum, &root_res->res);
30a18d6c YL	315	}
30a18d6c YL	316
1da177e4 LT	317	return 0;
	318	}
	319
3a27dd1c RR	320	#define ENABLE_CF8_EXT_CFG (1ULL << 46)
3a27dd1c RR	321
148f9bb8	322	static void enable_pci_io_ecs(void *unused)
3a27dd1c RR	323	{
	324	u64 reg;
	325	rdmsrl(MSR_AMD64_NB_CFG, reg);
	326	if (!(reg & ENABLE_CF8_EXT_CFG)) {
	327	reg \|= ENABLE_CF8_EXT_CFG;
	328	wrmsrl(MSR_AMD64_NB_CFG, reg);
	329	}
	330	}
	331
148f9bb8 PG	332	static int amd_cpu_notify(struct notifier_block *self, unsigned long action,
148f9bb8 PG	333	void *hcpu)
3a27dd1c	334	{
91ede005	335	int cpu = (long)hcpu;
ed21763e	336	switch (action) {
91ede005 RR	337	case CPU_ONLINE:
	338	case CPU_ONLINE_FROZEN:
	339	smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
	340	break;
	341	default:
	342	break;
	343	}
	344	return NOTIFY_OK;
	345	}
	346
148f9bb8	347	static struct notifier_block amd_cpu_notifier = {
91ede005 RR	348	.notifier_call = amd_cpu_notify,
	349	};
	350
24d9b70b JB	351	static void __init pci_enable_pci_io_ecs(void)
	352	{
	353	#ifdef CONFIG_AMD_NB
	354	unsigned int i, n;
	355
	356	for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
	357	u8 bus = amd_nb_bus_dev_ranges[i].bus;
	358	u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
	359	u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;
	360
	361	for (; slot < limit; ++slot) {
	362	u32 val = read_pci_config(bus, slot, 3, 0);
	363
	364	if (!early_is_amd_nb(val))
	365	continue;
	366
	367	val = read_pci_config(bus, slot, 3, 0x8c);
	368	if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
	369	val \|= ENABLE_CF8_EXT_CFG >> 32;
	370	write_pci_config(bus, slot, 3, 0x8c, val);
	371	}
	372	++n;
	373	}
	374	}
24d9b70b JB	375	#endif
	376	}
	377
91ede005 RR	378	static int __init pci_io_ecs_init(void)
	379	{
	380	int cpu;
	381
3a27dd1c RR	382	/* assume all cpus from fam10h have IO ECS */
	383	if (boot_cpu_data.x86 < 0x10)
	384	return 0;
91ede005	385
24d9b70b JB	386	/* Try the PCI method first. */
	387	if (early_pci_allowed())
	388	pci_enable_pci_io_ecs();
	389
9f668f66	390	cpu_notifier_register_begin();
91ede005 RR	391	for_each_online_cpu(cpu)
	392	amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
	393	(void *)(long)cpu);
9f668f66 SB	394	__register_cpu_notifier(&amd_cpu_notifier);
	395	cpu_notifier_register_done();
	396
3a27dd1c	397	pci_probe \|= PCI_HAS_IO_ECS;
91ede005	398
3a27dd1c RR	399	return 0;
	400	}
	401
9b4e27b5 RR	402	static int __init amd_postcore_init(void)
	403	{
	404	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	405	return 0;
	406
	407	early_fill_mp_bus_info();
91ede005	408	pci_io_ecs_init();
9b4e27b5 RR	409
	410	return 0;
	411	}
	412
	413	postcore_initcall(amd_postcore_init);