[linux-2.6-block.git] / arch / x86 / pci / amd_bus.c

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/topology.h>
#include <linux/cpu.h>
#include <linux/range.h>

#include <asm/amd_nb.h>
#include <asm/pci_x86.h>

#include <asm/pci-direct.h>

#include "bus_numa.h"

/*
 * This discovers the pcibus <-> node mapping on AMD K8.
 * also get peer root bus resource for io,mmio
 */

struct pci_hostbridge_probe {
	u32 bus;
	u32 slot;
	u32 vendor;
	u32 device;
};

static struct pci_hostbridge_probe pci_probes[] __initdata = {
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
};

#define RANGE_NUM 16

/**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 * Registers found in the K8 northbridge
 */
static int __init early_fill_mp_bus_info(void)
{
	int i;
	int j;
	unsigned bus;
	unsigned slot;
	int node;
	int link;
	int def_node;
	int def_link;
	struct pci_root_info *info;
	u32 reg;
	struct resource *res;
	u64 start;
	u64 end;
	struct range range[RANGE_NUM];
	u64 val;
	u32 address;
	bool found;
	struct resource fam10h_mmconf_res, *fam10h_mmconf;
	u64 fam10h_mmconf_start;
	u64 fam10h_mmconf_end;

	if (!early_pci_allowed())
		return -1;

	found = false;
	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
		u32 id;
		u16 device;
		u16 vendor;

		bus = pci_probes[i].bus;
		slot = pci_probes[i].slot;
		id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);

		vendor = id & 0xffff;
		device = (id>>16) & 0xffff;
		if (pci_probes[i].vendor == vendor &&
		    pci_probes[i].device == device) {
			found = true;
			break;
		}
	}

	if (!found)
		return 0;

	pci_root_num = 0;
	for (i = 0; i < 4; i++) {
		int min_bus;
		int max_bus;
		reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));

		/* Check if that register is enabled for bus range */
		if ((reg & 7) != 3)
			continue;

		min_bus = (reg >> 16) & 0xff;
		max_bus = (reg >> 24) & 0xff;
		node = (reg >> 4) & 0x07;
#ifdef CONFIG_NUMA
		for (j = min_bus; j <= max_bus; j++)
			set_mp_bus_to_node(j, node);
#endif
		link = (reg >> 8) & 0x03;

		info = &pci_root_info[pci_root_num];
		info->bus_min = min_bus;
		info->bus_max = max_bus;
		info->node = node;
		info->link = link;
		sprintf(info->name, "PCI Bus #%02x", min_bus);
		pci_root_num++;
	}

	/* get the default node and link for left over res */
	reg = read_pci_config(bus, slot, 0, 0x60);
	def_node = (reg >> 8) & 0x07;
	reg = read_pci_config(bus, slot, 0, 0x64);
	def_link = (reg >> 8) & 0x03;

	memset(range, 0, sizeof(range));
	add_range(range, RANGE_NUM, 0, 0, 0xffff + 1);
	/* io port resource */
	for (i = 0; i < 4; i++) {
		reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xfff000;
		reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xfff000) | 0xfff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];
		printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
		       node, link, start, end);

		/* kernel only handle 16 bit only */
		if (end > 0xffff)
			end = 0xffff;
		update_res(info, start, end, IORESOURCE_IO, 1);
		subtract_range(range, RANGE_NUM, start, end + 1);
	}
	/* add left over io port range to def node/link, [0, 0xffff] */
	/* find the position */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end - 1,
				   IORESOURCE_IO, 1);
		}
	}

	memset(range, 0, sizeof(range));
	/* 0xfd00000000-0xffffffffff for HT */
	end = cap_resource((0xfdULL<<32) - 1);
	end++;
	add_range(range, RANGE_NUM, 0, 0, end);

	/* need to take out [0, TOM) for RAM*/
	address = MSR_K8_TOP_MEM1;
	rdmsrl(address, val);
	end = (val & 0xffffff800000ULL);
	printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
	if (end < (1ULL<<32))
		subtract_range(range, RANGE_NUM, 0, end);

	/* get mmconfig */
	fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
	/* need to take out mmconf range */
	if (fam10h_mmconf) {
		printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
		fam10h_mmconf_start = fam10h_mmconf->start;
		fam10h_mmconf_end = fam10h_mmconf->end;
		subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
				 fam10h_mmconf_end + 1);
	} else {
		fam10h_mmconf_start = 0;
		fam10h_mmconf_end = 0;
	}

	/* mmio resource */
	for (i = 0; i < 8; i++) {
		reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xffffff00; /* 39:16 on 31:8*/
		start <<= 8;
		reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xffffff00);
		end <<= 8;
		end |= 0xffff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];

		printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
		       node, link, start, end);
		/*
		 * some sick allocation would have range overlap with fam10h
		 * mmconf range, so need to update start and end.
		 */
		if (fam10h_mmconf_end) {
			int changed = 0;
			u64 endx = 0;
			if (start >= fam10h_mmconf_start &&
			    start <= fam10h_mmconf_end) {
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}

			if (end >= fam10h_mmconf_start &&
			    end <= fam10h_mmconf_end) {
				end = fam10h_mmconf_start - 1;
				changed = 1;
			}

			if (start < fam10h_mmconf_start &&
			    end > fam10h_mmconf_end) {
				/* we got a hole */
				endx = fam10h_mmconf_start - 1;
				update_res(info, start, endx, IORESOURCE_MEM, 0);
				subtract_range(range, RANGE_NUM, start,
						 endx + 1);
				printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}
			if (changed) {
				if (start <= end) {
					printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
				} else {
					printk(KERN_CONT "%s\n", endx?"":" ==> none");
					continue;
				}
			}
		}

		update_res(info, cap_resource(start), cap_resource(end),
				 IORESOURCE_MEM, 1);
		subtract_range(range, RANGE_NUM, start, end + 1);
		printk(KERN_CONT "\n");
	}

	/* need to take out [4G, TOM2) for RAM*/
	/* SYS_CFG */
	address = MSR_K8_SYSCFG;
	rdmsrl(address, val);
	/* TOP_MEM2 is enabled? */
	if (val & (1<<21)) {
		/* TOP_MEM2 */
		address = MSR_K8_TOP_MEM2;
		rdmsrl(address, val);
		end = (val & 0xffffff800000ULL);
		printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
		subtract_range(range, RANGE_NUM, 1ULL<<32, end);
	}

	/*
	 * add left over mmio range to def node/link ?
	 * that is tricky, just record range in from start_min to 4G
	 */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];

		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, cap_resource(range[i].start),
				   cap_resource(range[i].end - 1),
				   IORESOURCE_MEM, 1);
		}
	}

	for (i = 0; i < pci_root_num; i++) {
		int res_num;
		int busnum;

		info = &pci_root_info[i];
		res_num = info->res_num;
		busnum = info->bus_min;
		printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
		       info->bus_min, info->bus_max, info->node, info->link);
		for (j = 0; j < res_num; j++) {
			res = &info->res[j];
			printk(KERN_DEBUG "bus: %02x index %x %pR\n",
				       busnum, j, res);
		}
	}

	return 0;
}

#define ENABLE_CF8_EXT_CFG      (1ULL << 46)

static void __cpuinit enable_pci_io_ecs(void *unused)
{
	u64 reg;
	rdmsrl(MSR_AMD64_NB_CFG, reg);
	if (!(reg & ENABLE_CF8_EXT_CFG)) {
		reg |= ENABLE_CF8_EXT_CFG;
		wrmsrl(MSR_AMD64_NB_CFG, reg);
	}
}

static int __cpuinit amd_cpu_notify(struct notifier_block *self,
				    unsigned long action, void *hcpu)
{
	int cpu = (long)hcpu;
	switch (action) {
	case CPU_ONLINE:
	case CPU_ONLINE_FROZEN:
		smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
		break;
	default:
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block __cpuinitdata amd_cpu_notifier = {
	.notifier_call	= amd_cpu_notify,
};

static void __init pci_enable_pci_io_ecs(void)
{
#ifdef CONFIG_AMD_NB
	unsigned int i, n;

	for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
		u8 bus = amd_nb_bus_dev_ranges[i].bus;
		u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
		u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;

		for (; slot < limit; ++slot) {
			u32 val = read_pci_config(bus, slot, 3, 0);

			if (!early_is_amd_nb(val))
				continue;

			val = read_pci_config(bus, slot, 3, 0x8c);
			if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
				val |= ENABLE_CF8_EXT_CFG >> 32;
				write_pci_config(bus, slot, 3, 0x8c, val);
			}
			++n;
		}
	}
#endif
}

static int __init pci_io_ecs_init(void)
{
	int cpu;

	/* assume all cpus from fam10h have IO ECS */
        if (boot_cpu_data.x86 < 0x10)
		return 0;

	/* Try the PCI method first. */
	if (early_pci_allowed())
		pci_enable_pci_io_ecs();

	register_cpu_notifier(&amd_cpu_notifier);
	for_each_online_cpu(cpu)
		amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
			       (void *)(long)cpu);
	pci_probe |= PCI_HAS_IO_ECS;

	return 0;
}

static int __init amd_postcore_init(void)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return 0;

	early_fill_mp_bus_info();
	pci_io_ecs_init();

	return 0;
}

postcore_initcall(amd_postcore_init);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
1da177e4 LT	2	#include <linux/pci.h>
d199a048	3	#include <linux/topology.h>
91ede005	4	#include <linux/cpu.h>
27811d8c YL	5	#include <linux/range.h>
27811d8c YL	6
24d9b70b	7	#include <asm/amd_nb.h>
82487711	8	#include <asm/pci_x86.h>
3a27dd1c	9
871d5f8d	10	#include <asm/pci-direct.h>
1da177e4	11
99935a7a YL	12	#include "bus_numa.h"
99935a7a YL	13
1da177e4 LT	14	/*
1da177e4 LT	15	* This discovers the pcibus <-> node mapping on AMD K8.
30a18d6c	16	* also get peer root bus resource for io,mmio
1da177e4 LT	17	*/
1da177e4 LT	18
30a18d6c YL	19	struct pci_hostbridge_probe {
	20	u32 bus;
	21	u32 slot;
	22	u32 vendor;
	23	u32 device;
	24	};
	25
	26	static struct pci_hostbridge_probe pci_probes[] __initdata = {
	27	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	28	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	29	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	30	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
	31	};
	32
27811d8c YL	33	#define RANGE_NUM 16
27811d8c YL	34
1da177e4	35	/**
871d5f8d YL	36	* early_fill_mp_bus_to_node()
871d5f8d YL	37	* called before pcibios_scan_root and pci_scan_bus
1da177e4 LT	38	* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
	39	* Registers found in the K8 northbridge
	40	*/
30a18d6c	41	static int __init early_fill_mp_bus_info(void)
1da177e4	42	{
30a18d6c YL	43	int i;
	44	int j;
	45	unsigned bus;
871d5f8d	46	unsigned slot;
35ddd068	47	int node;
30a18d6c YL	48	int link;
	49	int def_node;
	50	int def_link;
	51	struct pci_root_info *info;
	52	u32 reg;
	53	struct resource *res;
97445c3b YL	54	u64 start;
97445c3b YL	55	u64 end;
27811d8c	56	struct range range[RANGE_NUM];
30a18d6c YL	57	u64 val;
30a18d6c YL	58	u32 address;
3e3da00c	59	bool found;
24d25dbf BH	60	struct resource fam10h_mmconf_res, *fam10h_mmconf;
	61	u64 fam10h_mmconf_start;
	62	u64 fam10h_mmconf_end;
1da177e4	63
871d5f8d YL	64	if (!early_pci_allowed())
	65	return -1;
	66
3e3da00c	67	found = false;
30a18d6c YL	68	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
	69	u32 id;
	70	u16 device;
	71	u16 vendor;
35ddd068	72
30a18d6c YL	73	bus = pci_probes[i].bus;
	74	slot = pci_probes[i].slot;
	75	id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
35ddd068	76
30a18d6c YL	77	vendor = id & 0xffff;
	78	device = (id>>16) & 0xffff;
	79	if (pci_probes[i].vendor == vendor &&
	80	pci_probes[i].device == device) {
3e3da00c	81	found = true;
30a18d6c YL	82	break;
	83	}
	84	}
	85
3e3da00c	86	if (!found)
30a18d6c	87	return 0;
35ddd068	88
30a18d6c YL	89	pci_root_num = 0;
	90	for (i = 0; i < 4; i++) {
	91	int min_bus;
	92	int max_bus;
	93	reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
35ddd068 YL	94
35ddd068 YL	95	/* Check if that register is enabled for bus range */
30a18d6c	96	if ((reg & 7) != 3)
35ddd068 YL	97	continue;
35ddd068 YL	98
30a18d6c YL	99	min_bus = (reg >> 16) & 0xff;
	100	max_bus = (reg >> 24) & 0xff;
	101	node = (reg >> 4) & 0x07;
	102	#ifdef CONFIG_NUMA
35ddd068	103	for (j = min_bus; j <= max_bus; j++)
2547089c	104	set_mp_bus_to_node(j, node);
30a18d6c YL	105	#endif
	106	link = (reg >> 8) & 0x03;
	107
	108	info = &pci_root_info[pci_root_num];
	109	info->bus_min = min_bus;
	110	info->bus_max = max_bus;
	111	info->node = node;
	112	info->link = link;
	113	sprintf(info->name, "PCI Bus #%02x", min_bus);
	114	pci_root_num++;
1da177e4 LT	115	}
1da177e4 LT	116
30a18d6c YL	117	/* get the default node and link for left over res */
	118	reg = read_pci_config(bus, slot, 0, 0x60);
	119	def_node = (reg >> 8) & 0x07;
	120	reg = read_pci_config(bus, slot, 0, 0x64);
	121	def_link = (reg >> 8) & 0x03;
	122
	123	memset(range, 0, sizeof(range));
e9a0064a	124	add_range(range, RANGE_NUM, 0, 0, 0xffff + 1);
30a18d6c YL	125	/* io port resource */
	126	for (i = 0; i < 4; i++) {
	127	reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
	128	if (!(reg & 3))
	129	continue;
	130
	131	start = reg & 0xfff000;
	132	reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
	133	node = reg & 0x07;
	134	link = (reg >> 4) & 0x03;
	135	end = (reg & 0xfff000) \| 0xfff;
	136
	137	/* find the position */
	138	for (j = 0; j < pci_root_num; j++) {
	139	info = &pci_root_info[j];
	140	if (info->node == node && info->link == link)
	141	break;
	142	}
	143	if (j == pci_root_num)
	144	continue; /* not found */
	145
	146	info = &pci_root_info[j];
6e184f29	147	printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
97445c3b	148	node, link, start, end);
e8ee6f0a YL	149
	150	/* kernel only handle 16 bit only */
	151	if (end > 0xffff)
	152	end = 0xffff;
	153	update_res(info, start, end, IORESOURCE_IO, 1);
e9a0064a	154	subtract_range(range, RANGE_NUM, start, end + 1);
30a18d6c YL	155	}
	156	/* add left over io port range to def node/link, [0, 0xffff] */
	157	/* find the position */
	158	for (j = 0; j < pci_root_num; j++) {
	159	info = &pci_root_info[j];
	160	if (info->node == def_node && info->link == def_link)
	161	break;
	162	}
	163	if (j < pci_root_num) {
	164	info = &pci_root_info[j];
	165	for (i = 0; i < RANGE_NUM; i++) {
	166	if (!range[i].end)
	167	continue;
	168
e9a0064a	169	update_res(info, range[i].start, range[i].end - 1,
30a18d6c YL	170	IORESOURCE_IO, 1);
	171	}
	172	}
	173
	174	memset(range, 0, sizeof(range));
	175	/* 0xfd00000000-0xffffffffff for HT */
e9a0064a YL	176	end = cap_resource((0xfdULL<<32) - 1);
	177	end++;
	178	add_range(range, RANGE_NUM, 0, 0, end);
30a18d6c YL	179
	180	/* need to take out [0, TOM) for RAM*/
	181	address = MSR_K8_TOP_MEM1;
	182	rdmsrl(address, val);
8004dd96	183	end = (val & 0xffffff800000ULL);
97445c3b	184	printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
30a18d6c	185	if (end < (1ULL<<32))
e9a0064a	186	subtract_range(range, RANGE_NUM, 0, end);
30a18d6c	187
6e184f29	188	/* get mmconfig */
24d25dbf	189	fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
6e184f29	190	/* need to take out mmconf range */
24d25dbf BH	191	if (fam10h_mmconf) {
	192	printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
	193	fam10h_mmconf_start = fam10h_mmconf->start;
	194	fam10h_mmconf_end = fam10h_mmconf->end;
e9a0064a YL	195	subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
e9a0064a YL	196	fam10h_mmconf_end + 1);
24d25dbf BH	197	} else {
	198	fam10h_mmconf_start = 0;
	199	fam10h_mmconf_end = 0;
6e184f29 YL	200	}
6e184f29 YL	201
30a18d6c YL	202	/* mmio resource */
	203	for (i = 0; i < 8; i++) {
	204	reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
	205	if (!(reg & 3))
	206	continue;
	207
	208	start = reg & 0xffffff00; /* 39:16 on 31:8*/
	209	start <<= 8;
	210	reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
	211	node = reg & 0x07;
	212	link = (reg >> 4) & 0x03;
	213	end = (reg & 0xffffff00);
	214	end <<= 8;
	215	end \|= 0xffff;
	216
	217	/* find the position */
	218	for (j = 0; j < pci_root_num; j++) {
	219	info = &pci_root_info[j];
	220	if (info->node == node && info->link == link)
	221	break;
	222	}
	223	if (j == pci_root_num)
	224	continue; /* not found */
	225
	226	info = &pci_root_info[j];
6e184f29 YL	227
6e184f29 YL	228	printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
97445c3b	229	node, link, start, end);
6e184f29 YL	230	/*
	231	* some sick allocation would have range overlap with fam10h
	232	* mmconf range, so need to update start and end.
	233	*/
	234	if (fam10h_mmconf_end) {
	235	int changed = 0;
	236	u64 endx = 0;
	237	if (start >= fam10h_mmconf_start &&
	238	start <= fam10h_mmconf_end) {
	239	start = fam10h_mmconf_end + 1;
	240	changed = 1;
	241	}
	242
	243	if (end >= fam10h_mmconf_start &&
	244	end <= fam10h_mmconf_end) {
	245	end = fam10h_mmconf_start - 1;
	246	changed = 1;
	247	}
	248
	249	if (start < fam10h_mmconf_start &&
	250	end > fam10h_mmconf_end) {
	251	/* we got a hole */
	252	endx = fam10h_mmconf_start - 1;
	253	update_res(info, start, endx, IORESOURCE_MEM, 0);
e9a0064a YL	254	subtract_range(range, RANGE_NUM, start,
e9a0064a YL	255	endx + 1);
97445c3b	256	printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
6e184f29 YL	257	start = fam10h_mmconf_end + 1;
	258	changed = 1;
	259	}
	260	if (changed) {
	261	if (start <= end) {
97445c3b	262	printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
6e184f29 YL	263	} else {
	264	printk(KERN_CONT "%s\n", endx?"":" ==> none");
	265	continue;
	266	}
	267	}
	268	}
	269
9ad3f2c7 YL	270	update_res(info, cap_resource(start), cap_resource(end),
9ad3f2c7 YL	271	IORESOURCE_MEM, 1);
e9a0064a	272	subtract_range(range, RANGE_NUM, start, end + 1);
6e184f29	273	printk(KERN_CONT "\n");
30a18d6c YL	274	}
	275
	276	/* need to take out [4G, TOM2) for RAM*/
	277	/* SYS_CFG */
	278	address = MSR_K8_SYSCFG;
	279	rdmsrl(address, val);
	280	/* TOP_MEM2 is enabled? */
	281	if (val & (1<<21)) {
	282	/* TOP_MEM2 */
	283	address = MSR_K8_TOP_MEM2;
	284	rdmsrl(address, val);
8004dd96	285	end = (val & 0xffffff800000ULL);
97445c3b	286	printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
e9a0064a	287	subtract_range(range, RANGE_NUM, 1ULL<<32, end);
30a18d6c YL	288	}
	289
	290	/*
	291	* add left over mmio range to def node/link ?
	292	* that is tricky, just record range in from start_min to 4G
	293	*/
	294	for (j = 0; j < pci_root_num; j++) {
	295	info = &pci_root_info[j];
	296	if (info->node == def_node && info->link == def_link)
	297	break;
	298	}
	299	if (j < pci_root_num) {
	300	info = &pci_root_info[j];
	301
	302	for (i = 0; i < RANGE_NUM; i++) {
	303	if (!range[i].end)
	304	continue;
	305
9ad3f2c7	306	update_res(info, cap_resource(range[i].start),
e9a0064a	307	cap_resource(range[i].end - 1),
30a18d6c YL	308	IORESOURCE_MEM, 1);
	309	}
	310	}
	311
30a18d6c YL	312	for (i = 0; i < pci_root_num; i++) {
	313	int res_num;
	314	int busnum;
	315
	316	info = &pci_root_info[i];
	317	res_num = info->res_num;
	318	busnum = info->bus_min;
99935a7a	319	printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
30a18d6c YL	320	info->bus_min, info->bus_max, info->node, info->link);
	321	for (j = 0; j < res_num; j++) {
	322	res = &info->res[j];
284f933d YL	323	printk(KERN_DEBUG "bus: %02x index %x %pR\n",
284f933d YL	324	busnum, j, res);
30a18d6c YL	325	}
	326	}
	327
1da177e4 LT	328	return 0;
	329	}
	330
3a27dd1c RR	331	#define ENABLE_CF8_EXT_CFG (1ULL << 46)
3a27dd1c RR	332
691269f0	333	static void __cpuinit enable_pci_io_ecs(void *unused)
3a27dd1c RR	334	{
	335	u64 reg;
	336	rdmsrl(MSR_AMD64_NB_CFG, reg);
	337	if (!(reg & ENABLE_CF8_EXT_CFG)) {
	338	reg \|= ENABLE_CF8_EXT_CFG;
	339	wrmsrl(MSR_AMD64_NB_CFG, reg);
	340	}
	341	}
	342
91ede005 RR	343	static int __cpuinit amd_cpu_notify(struct notifier_block *self,
91ede005 RR	344	unsigned long action, void *hcpu)
3a27dd1c	345	{
91ede005	346	int cpu = (long)hcpu;
ed21763e	347	switch (action) {
91ede005 RR	348	case CPU_ONLINE:
	349	case CPU_ONLINE_FROZEN:
	350	smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
	351	break;
	352	default:
	353	break;
	354	}
	355	return NOTIFY_OK;
	356	}
	357
	358	static struct notifier_block __cpuinitdata amd_cpu_notifier = {
	359	.notifier_call = amd_cpu_notify,
	360	};
	361
24d9b70b JB	362	static void __init pci_enable_pci_io_ecs(void)
	363	{
	364	#ifdef CONFIG_AMD_NB
	365	unsigned int i, n;
	366
	367	for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
	368	u8 bus = amd_nb_bus_dev_ranges[i].bus;
	369	u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
	370	u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;
	371
	372	for (; slot < limit; ++slot) {
	373	u32 val = read_pci_config(bus, slot, 3, 0);
	374
	375	if (!early_is_amd_nb(val))
	376	continue;
	377
	378	val = read_pci_config(bus, slot, 3, 0x8c);
	379	if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
	380	val \|= ENABLE_CF8_EXT_CFG >> 32;
	381	write_pci_config(bus, slot, 3, 0x8c, val);
	382	}
	383	++n;
	384	}
	385	}
24d9b70b JB	386	#endif
	387	}
	388
91ede005 RR	389	static int __init pci_io_ecs_init(void)
	390	{
	391	int cpu;
	392
3a27dd1c RR	393	/* assume all cpus from fam10h have IO ECS */
	394	if (boot_cpu_data.x86 < 0x10)
	395	return 0;
91ede005	396
24d9b70b JB	397	/* Try the PCI method first. */
	398	if (early_pci_allowed())
	399	pci_enable_pci_io_ecs();
	400
91ede005 RR	401	register_cpu_notifier(&amd_cpu_notifier);
	402	for_each_online_cpu(cpu)
	403	amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
	404	(void *)(long)cpu);
3a27dd1c	405	pci_probe \|= PCI_HAS_IO_ECS;
91ede005	406
3a27dd1c RR	407	return 0;
	408	}
	409
9b4e27b5 RR	410	static int __init amd_postcore_init(void)
	411	{
	412	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	413	return 0;
	414
	415	early_fill_mp_bus_info();
91ede005	416	pci_io_ecs_init();
9b4e27b5 RR	417
	418	return 0;
	419	}
	420
	421	postcore_initcall(amd_postcore_init);