Commit | Line | Data |
---|---|---|
8b45b72b | 1 | /* |
1da177e4 | 2 | * @file op_model_ppro.h |
b9917028 | 3 | * Family 6 perfmon and architectural perfmon MSR operations |
1da177e4 LT |
4 | * |
5 | * @remark Copyright 2002 OProfile authors | |
b9917028 | 6 | * @remark Copyright 2008 Intel Corporation |
1da177e4 LT |
7 | * @remark Read the file COPYING |
8 | * | |
9 | * @author John Levon | |
10 | * @author Philippe Elie | |
11 | * @author Graydon Hoare | |
b9917028 | 12 | * @author Andi Kleen |
1da177e4 LT |
13 | */ |
14 | ||
15 | #include <linux/oprofile.h> | |
b9917028 | 16 | #include <linux/slab.h> |
1da177e4 LT |
17 | #include <asm/ptrace.h> |
18 | #include <asm/msr.h> | |
19 | #include <asm/apic.h> | |
3e4ff115 | 20 | #include <asm/nmi.h> |
b9917028 | 21 | #include <asm/intel_arch_perfmon.h> |
8b45b72b | 22 | |
1da177e4 LT |
23 | #include "op_x86_model.h" |
24 | #include "op_counter.h" | |
25 | ||
b9917028 AK |
26 | static int num_counters = 2; |
27 | static int counter_width = 32; | |
1da177e4 | 28 | |
8b45b72b | 29 | #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0) |
7c64ade5 | 30 | #define CTR_OVERFLOWED(n) (!((n) & (1ULL<<(counter_width-1)))) |
1da177e4 | 31 | |
8b45b72b PC |
32 | #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0) |
33 | #define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0) | |
34 | #define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls[(c)].addr), (l), (h)); } while (0) | |
1da177e4 LT |
35 | #define CTRL_SET_ACTIVE(n) (n |= (1<<22)) |
36 | #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22)) | |
37 | #define CTRL_CLEAR(x) (x &= (1<<21)) | |
38 | #define CTRL_SET_ENABLE(val) (val |= 1<<20) | |
8b45b72b PC |
39 | #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16)) |
40 | #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17)) | |
1da177e4 LT |
41 | #define CTRL_SET_UM(val, m) (val |= (m << 8)) |
42 | #define CTRL_SET_EVENT(val, e) (val |= e) | |
43 | ||
b9917028 | 44 | static u64 *reset_value; |
8b45b72b | 45 | |
1da177e4 LT |
46 | static void ppro_fill_in_addresses(struct op_msrs * const msrs) |
47 | { | |
cb9c448c DZ |
48 | int i; |
49 | ||
b9917028 | 50 | for (i = 0; i < num_counters; i++) { |
cb9c448c DZ |
51 | if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i)) |
52 | msrs->counters[i].addr = MSR_P6_PERFCTR0 + i; | |
53 | else | |
54 | msrs->counters[i].addr = 0; | |
55 | } | |
8b45b72b | 56 | |
b9917028 | 57 | for (i = 0; i < num_counters; i++) { |
cb9c448c DZ |
58 | if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) |
59 | msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i; | |
60 | else | |
61 | msrs->controls[i].addr = 0; | |
62 | } | |
1da177e4 LT |
63 | } |
64 | ||
65 | ||
66 | static void ppro_setup_ctrs(struct op_msrs const * const msrs) | |
67 | { | |
68 | unsigned int low, high; | |
69 | int i; | |
70 | ||
b9917028 | 71 | if (!reset_value) { |
a4a16bea | 72 | reset_value = kmalloc(sizeof(reset_value[0]) * num_counters, |
b9917028 AK |
73 | GFP_ATOMIC); |
74 | if (!reset_value) | |
75 | return; | |
76 | } | |
77 | ||
78 | if (cpu_has_arch_perfmon) { | |
79 | union cpuid10_eax eax; | |
80 | eax.full = cpuid_eax(0xa); | |
81 | if (counter_width < eax.split.bit_width) | |
82 | counter_width = eax.split.bit_width; | |
83 | } | |
84 | ||
1da177e4 | 85 | /* clear all counters */ |
b9917028 | 86 | for (i = 0 ; i < num_counters; ++i) { |
8b45b72b | 87 | if (unlikely(!CTRL_IS_RESERVED(msrs, i))) |
cb9c448c | 88 | continue; |
1da177e4 LT |
89 | CTRL_READ(low, high, msrs, i); |
90 | CTRL_CLEAR(low); | |
91 | CTRL_WRITE(low, high, msrs, i); | |
92 | } | |
8b45b72b | 93 | |
1da177e4 | 94 | /* avoid a false detection of ctr overflows in NMI handler */ |
b9917028 | 95 | for (i = 0; i < num_counters; ++i) { |
8b45b72b | 96 | if (unlikely(!CTR_IS_RESERVED(msrs, i))) |
cb9c448c | 97 | continue; |
b9917028 | 98 | wrmsrl(msrs->counters[i].addr, -1LL); |
1da177e4 LT |
99 | } |
100 | ||
101 | /* enable active counters */ | |
b9917028 | 102 | for (i = 0; i < num_counters; ++i) { |
8b45b72b | 103 | if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) { |
1da177e4 LT |
104 | reset_value[i] = counter_config[i].count; |
105 | ||
b9917028 | 106 | wrmsrl(msrs->counters[i].addr, -reset_value[i]); |
1da177e4 LT |
107 | |
108 | CTRL_READ(low, high, msrs, i); | |
109 | CTRL_CLEAR(low); | |
110 | CTRL_SET_ENABLE(low); | |
111 | CTRL_SET_USR(low, counter_config[i].user); | |
112 | CTRL_SET_KERN(low, counter_config[i].kernel); | |
113 | CTRL_SET_UM(low, counter_config[i].unit_mask); | |
114 | CTRL_SET_EVENT(low, counter_config[i].event); | |
115 | CTRL_WRITE(low, high, msrs, i); | |
cb9c448c DZ |
116 | } else { |
117 | reset_value[i] = 0; | |
1da177e4 LT |
118 | } |
119 | } | |
120 | } | |
121 | ||
8b45b72b | 122 | |
1da177e4 LT |
123 | static int ppro_check_ctrs(struct pt_regs * const regs, |
124 | struct op_msrs const * const msrs) | |
125 | { | |
7c64ade5 | 126 | u64 val; |
1da177e4 | 127 | int i; |
8b45b72b | 128 | |
b9917028 | 129 | for (i = 0 ; i < num_counters; ++i) { |
cb9c448c DZ |
130 | if (!reset_value[i]) |
131 | continue; | |
7c64ade5 AK |
132 | rdmsrl(msrs->counters[i].addr, val); |
133 | if (CTR_OVERFLOWED(val)) { | |
1da177e4 | 134 | oprofile_add_sample(regs, i); |
b9917028 | 135 | wrmsrl(msrs->counters[i].addr, -reset_value[i]); |
1da177e4 LT |
136 | } |
137 | } | |
138 | ||
139 | /* Only P6 based Pentium M need to re-unmask the apic vector but it | |
140 | * doesn't hurt other P6 variant */ | |
141 | apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED); | |
142 | ||
143 | /* We can't work out if we really handled an interrupt. We | |
144 | * might have caught a *second* counter just after overflowing | |
145 | * the interrupt for this counter then arrives | |
146 | * and we don't find a counter that's overflowed, so we | |
147 | * would return 0 and get dazed + confused. Instead we always | |
148 | * assume we found an overflow. This sucks. | |
149 | */ | |
150 | return 1; | |
151 | } | |
152 | ||
8b45b72b | 153 | |
1da177e4 LT |
154 | static void ppro_start(struct op_msrs const * const msrs) |
155 | { | |
8b45b72b | 156 | unsigned int low, high; |
6b77df08 | 157 | int i; |
cb9c448c | 158 | |
b9917028 | 159 | for (i = 0; i < num_counters; ++i) { |
6b77df08 AS |
160 | if (reset_value[i]) { |
161 | CTRL_READ(low, high, msrs, i); | |
162 | CTRL_SET_ACTIVE(low); | |
163 | CTRL_WRITE(low, high, msrs, i); | |
164 | } | |
cb9c448c | 165 | } |
1da177e4 LT |
166 | } |
167 | ||
168 | ||
169 | static void ppro_stop(struct op_msrs const * const msrs) | |
170 | { | |
8b45b72b | 171 | unsigned int low, high; |
6b77df08 | 172 | int i; |
cb9c448c | 173 | |
b9917028 | 174 | for (i = 0; i < num_counters; ++i) { |
6b77df08 AS |
175 | if (!reset_value[i]) |
176 | continue; | |
177 | CTRL_READ(low, high, msrs, i); | |
cb9c448c | 178 | CTRL_SET_INACTIVE(low); |
6b77df08 | 179 | CTRL_WRITE(low, high, msrs, i); |
cb9c448c DZ |
180 | } |
181 | } | |
182 | ||
183 | static void ppro_shutdown(struct op_msrs const * const msrs) | |
184 | { | |
185 | int i; | |
186 | ||
b9917028 | 187 | for (i = 0 ; i < num_counters ; ++i) { |
8b45b72b | 188 | if (CTR_IS_RESERVED(msrs, i)) |
cb9c448c DZ |
189 | release_perfctr_nmi(MSR_P6_PERFCTR0 + i); |
190 | } | |
b9917028 | 191 | for (i = 0 ; i < num_counters ; ++i) { |
8b45b72b | 192 | if (CTRL_IS_RESERVED(msrs, i)) |
cb9c448c DZ |
193 | release_evntsel_nmi(MSR_P6_EVNTSEL0 + i); |
194 | } | |
b9917028 AK |
195 | if (reset_value) { |
196 | kfree(reset_value); | |
197 | reset_value = NULL; | |
198 | } | |
1da177e4 LT |
199 | } |
200 | ||
201 | ||
59512900 | 202 | struct op_x86_model_spec op_ppro_spec = { |
5a289395 RR |
203 | .num_counters = 2, /* can be overriden */ |
204 | .num_controls = 2, /* dito */ | |
205 | .fill_in_addresses = &ppro_fill_in_addresses, | |
206 | .setup_ctrs = &ppro_setup_ctrs, | |
207 | .check_ctrs = &ppro_check_ctrs, | |
208 | .start = &ppro_start, | |
209 | .stop = &ppro_stop, | |
210 | .shutdown = &ppro_shutdown | |
b9917028 AK |
211 | }; |
212 | ||
213 | /* | |
214 | * Architectural performance monitoring. | |
215 | * | |
216 | * Newer Intel CPUs (Core1+) have support for architectural | |
217 | * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details. | |
218 | * The advantage of this is that it can be done without knowing about | |
219 | * the specific CPU. | |
220 | */ | |
221 | ||
222 | void arch_perfmon_setup_counters(void) | |
223 | { | |
224 | union cpuid10_eax eax; | |
225 | ||
226 | eax.full = cpuid_eax(0xa); | |
227 | ||
228 | /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */ | |
229 | if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 && | |
230 | current_cpu_data.x86_model == 15) { | |
231 | eax.split.version_id = 2; | |
232 | eax.split.num_counters = 2; | |
233 | eax.split.bit_width = 40; | |
234 | } | |
235 | ||
236 | num_counters = eax.split.num_counters; | |
237 | ||
238 | op_arch_perfmon_spec.num_counters = num_counters; | |
239 | op_arch_perfmon_spec.num_controls = num_counters; | |
59512900 AK |
240 | op_ppro_spec.num_counters = num_counters; |
241 | op_ppro_spec.num_controls = num_counters; | |
b9917028 AK |
242 | } |
243 | ||
244 | struct op_x86_model_spec op_arch_perfmon_spec = { | |
245 | /* num_counters/num_controls filled in at runtime */ | |
c92960fc | 246 | .fill_in_addresses = &ppro_fill_in_addresses, |
b9917028 | 247 | /* user space does the cpuid check for available events */ |
c92960fc RR |
248 | .setup_ctrs = &ppro_setup_ctrs, |
249 | .check_ctrs = &ppro_check_ctrs, | |
250 | .start = &ppro_start, | |
251 | .stop = &ppro_stop, | |
252 | .shutdown = &ppro_shutdown | |
1da177e4 | 253 | }; |