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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c048fdfe GC |
2 | #include <linux/init.h> |
3 | ||
4 | #include <linux/mm.h> | |
c048fdfe GC |
5 | #include <linux/spinlock.h> |
6 | #include <linux/smp.h> | |
c048fdfe | 7 | #include <linux/interrupt.h> |
4b599fed | 8 | #include <linux/export.h> |
93296720 | 9 | #include <linux/cpu.h> |
18bf3c3e | 10 | #include <linux/debugfs.h> |
b5f06f64 | 11 | #include <linux/sched/smt.h> |
8ca07e17 | 12 | #include <linux/task_work.h> |
c048fdfe | 13 | |
c048fdfe | 14 | #include <asm/tlbflush.h> |
c048fdfe | 15 | #include <asm/mmu_context.h> |
18bf3c3e | 16 | #include <asm/nospec-branch.h> |
350f8f56 | 17 | #include <asm/cache.h> |
b5f06f64 | 18 | #include <asm/cacheflush.h> |
6dd01bed | 19 | #include <asm/apic.h> |
5471eea5 | 20 | #include <asm/perf_event.h> |
5af5573e | 21 | |
935f5839 PZ |
22 | #include "mm_internal.h" |
23 | ||
2faf153b TG |
24 | #ifdef CONFIG_PARAVIRT |
25 | # define STATIC_NOPV | |
26 | #else | |
27 | # define STATIC_NOPV static | |
28 | # define __flush_tlb_local native_flush_tlb_local | |
cd30d26c | 29 | # define __flush_tlb_global native_flush_tlb_global |
127ac915 | 30 | # define __flush_tlb_one_user(addr) native_flush_tlb_one_user(addr) |
4ce94eab | 31 | # define __flush_tlb_multi(msk, info) native_flush_tlb_multi(msk, info) |
2faf153b TG |
32 | #endif |
33 | ||
c048fdfe | 34 | /* |
ce4a4e56 | 35 | * TLB flushing, formerly SMP-only |
c048fdfe GC |
36 | * c/o Linus Torvalds. |
37 | * | |
38 | * These mean you can really definitely utterly forget about | |
39 | * writing to user space from interrupts. (Its not allowed anyway). | |
40 | * | |
41 | * Optimizations Manfred Spraul <manfred@colorfullife.com> | |
42 | * | |
43 | * More scalable flush, from Andi Kleen | |
44 | * | |
52aec330 | 45 | * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi |
c048fdfe GC |
46 | */ |
47 | ||
4c71a2b6 | 48 | /* |
b5f06f64 | 49 | * Bits to mangle the TIF_SPEC_* state into the mm pointer which is |
371b09c6 | 50 | * stored in cpu_tlb_state.last_user_mm_spec. |
4c71a2b6 TG |
51 | */ |
52 | #define LAST_USER_MM_IBPB 0x1UL | |
b5f06f64 BS |
53 | #define LAST_USER_MM_L1D_FLUSH 0x2UL |
54 | #define LAST_USER_MM_SPEC_MASK (LAST_USER_MM_IBPB | LAST_USER_MM_L1D_FLUSH) | |
371b09c6 BS |
55 | |
56 | /* Bits to set when tlbstate and flush is (re)initialized */ | |
57 | #define LAST_USER_MM_INIT LAST_USER_MM_IBPB | |
4c71a2b6 | 58 | |
6c9b7d79 TG |
59 | /* |
60 | * The x86 feature is called PCID (Process Context IDentifier). It is similar | |
61 | * to what is traditionally called ASID on the RISC processors. | |
62 | * | |
63 | * We don't use the traditional ASID implementation, where each process/mm gets | |
64 | * its own ASID and flush/restart when we run out of ASID space. | |
65 | * | |
66 | * Instead we have a small per-cpu array of ASIDs and cache the last few mm's | |
67 | * that came by on this CPU, allowing cheaper switch_mm between processes on | |
68 | * this CPU. | |
69 | * | |
70 | * We end up with different spaces for different things. To avoid confusion we | |
71 | * use different names for each of them: | |
72 | * | |
73 | * ASID - [0, TLB_NR_DYN_ASIDS-1] | |
74 | * the canonical identifier for an mm | |
75 | * | |
76 | * kPCID - [1, TLB_NR_DYN_ASIDS] | |
77 | * the value we write into the PCID part of CR3; corresponds to the | |
78 | * ASID+1, because PCID 0 is special. | |
79 | * | |
80 | * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS] | |
81 | * for KPTI each mm has two address spaces and thus needs two | |
82 | * PCID values, but we can still do with a single ASID denomination | |
83 | * for each mm. Corresponds to kPCID + 2048. | |
84 | * | |
85 | */ | |
86 | ||
87 | /* There are 12 bits of space for ASIDS in CR3 */ | |
88 | #define CR3_HW_ASID_BITS 12 | |
89 | ||
90 | /* | |
91 | * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for | |
92 | * user/kernel switches | |
93 | */ | |
94 | #ifdef CONFIG_PAGE_TABLE_ISOLATION | |
95 | # define PTI_CONSUMED_PCID_BITS 1 | |
96 | #else | |
97 | # define PTI_CONSUMED_PCID_BITS 0 | |
98 | #endif | |
99 | ||
100 | #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS) | |
101 | ||
102 | /* | |
103 | * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account | |
104 | * for them being zero-based. Another -1 is because PCID 0 is reserved for | |
105 | * use by non-PCID-aware users. | |
106 | */ | |
107 | #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2) | |
108 | ||
109 | /* | |
110 | * Given @asid, compute kPCID | |
111 | */ | |
112 | static inline u16 kern_pcid(u16 asid) | |
113 | { | |
114 | VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE); | |
115 | ||
116 | #ifdef CONFIG_PAGE_TABLE_ISOLATION | |
117 | /* | |
d9f6e12f | 118 | * Make sure that the dynamic ASID space does not conflict with the |
6c9b7d79 TG |
119 | * bit we are using to switch between user and kernel ASIDs. |
120 | */ | |
121 | BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT)); | |
122 | ||
123 | /* | |
124 | * The ASID being passed in here should have respected the | |
125 | * MAX_ASID_AVAILABLE and thus never have the switch bit set. | |
126 | */ | |
127 | VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT)); | |
128 | #endif | |
129 | /* | |
130 | * The dynamically-assigned ASIDs that get passed in are small | |
131 | * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set, | |
132 | * so do not bother to clear it. | |
133 | * | |
134 | * If PCID is on, ASID-aware code paths put the ASID+1 into the | |
135 | * PCID bits. This serves two purposes. It prevents a nasty | |
136 | * situation in which PCID-unaware code saves CR3, loads some other | |
137 | * value (with PCID == 0), and then restores CR3, thus corrupting | |
138 | * the TLB for ASID 0 if the saved ASID was nonzero. It also means | |
139 | * that any bugs involving loading a PCID-enabled CR3 with | |
140 | * CR4.PCIDE off will trigger deterministically. | |
141 | */ | |
142 | return asid + 1; | |
143 | } | |
144 | ||
145 | /* | |
146 | * Given @asid, compute uPCID | |
147 | */ | |
148 | static inline u16 user_pcid(u16 asid) | |
149 | { | |
150 | u16 ret = kern_pcid(asid); | |
151 | #ifdef CONFIG_PAGE_TABLE_ISOLATION | |
152 | ret |= 1 << X86_CR3_PTI_PCID_USER_BIT; | |
153 | #endif | |
154 | return ret; | |
155 | } | |
156 | ||
157 | static inline unsigned long build_cr3(pgd_t *pgd, u16 asid) | |
158 | { | |
159 | if (static_cpu_has(X86_FEATURE_PCID)) { | |
160 | return __sme_pa(pgd) | kern_pcid(asid); | |
161 | } else { | |
162 | VM_WARN_ON_ONCE(asid != 0); | |
163 | return __sme_pa(pgd); | |
164 | } | |
165 | } | |
166 | ||
167 | static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid) | |
168 | { | |
169 | VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE); | |
170 | /* | |
171 | * Use boot_cpu_has() instead of this_cpu_has() as this function | |
172 | * might be called during early boot. This should work even after | |
173 | * boot because all CPU's the have same capabilities: | |
174 | */ | |
175 | VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID)); | |
176 | return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH; | |
177 | } | |
178 | ||
2ea907c4 DH |
179 | /* |
180 | * We get here when we do something requiring a TLB invalidation | |
181 | * but could not go invalidate all of the contexts. We do the | |
182 | * necessary invalidation by clearing out the 'ctx_id' which | |
183 | * forces a TLB flush when the context is loaded. | |
184 | */ | |
387048f5 | 185 | static void clear_asid_other(void) |
2ea907c4 DH |
186 | { |
187 | u16 asid; | |
188 | ||
189 | /* | |
190 | * This is only expected to be set if we have disabled | |
191 | * kernel _PAGE_GLOBAL pages. | |
192 | */ | |
193 | if (!static_cpu_has(X86_FEATURE_PTI)) { | |
194 | WARN_ON_ONCE(1); | |
195 | return; | |
196 | } | |
197 | ||
198 | for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) { | |
199 | /* Do not need to flush the current asid */ | |
200 | if (asid == this_cpu_read(cpu_tlbstate.loaded_mm_asid)) | |
201 | continue; | |
202 | /* | |
203 | * Make sure the next time we go to switch to | |
204 | * this asid, we do a flush: | |
205 | */ | |
206 | this_cpu_write(cpu_tlbstate.ctxs[asid].ctx_id, 0); | |
207 | } | |
208 | this_cpu_write(cpu_tlbstate.invalidate_other, false); | |
209 | } | |
210 | ||
f39681ed AL |
211 | atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1); |
212 | ||
b956575b | 213 | |
10af6235 AL |
214 | static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, |
215 | u16 *new_asid, bool *need_flush) | |
216 | { | |
217 | u16 asid; | |
218 | ||
219 | if (!static_cpu_has(X86_FEATURE_PCID)) { | |
220 | *new_asid = 0; | |
221 | *need_flush = true; | |
222 | return; | |
223 | } | |
224 | ||
2ea907c4 DH |
225 | if (this_cpu_read(cpu_tlbstate.invalidate_other)) |
226 | clear_asid_other(); | |
227 | ||
10af6235 AL |
228 | for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) { |
229 | if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) != | |
230 | next->context.ctx_id) | |
231 | continue; | |
232 | ||
233 | *new_asid = asid; | |
234 | *need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) < | |
235 | next_tlb_gen); | |
236 | return; | |
237 | } | |
238 | ||
239 | /* | |
240 | * We don't currently own an ASID slot on this CPU. | |
241 | * Allocate a slot. | |
242 | */ | |
243 | *new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1; | |
244 | if (*new_asid >= TLB_NR_DYN_ASIDS) { | |
245 | *new_asid = 0; | |
246 | this_cpu_write(cpu_tlbstate.next_asid, 1); | |
247 | } | |
248 | *need_flush = true; | |
249 | } | |
250 | ||
127ac915 TG |
251 | /* |
252 | * Given an ASID, flush the corresponding user ASID. We can delay this | |
253 | * until the next time we switch to it. | |
254 | * | |
255 | * See SWITCH_TO_USER_CR3. | |
256 | */ | |
257 | static inline void invalidate_user_asid(u16 asid) | |
258 | { | |
259 | /* There is no user ASID if address space separation is off */ | |
260 | if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION)) | |
261 | return; | |
262 | ||
263 | /* | |
264 | * We only have a single ASID if PCID is off and the CR3 | |
265 | * write will have flushed it. | |
266 | */ | |
267 | if (!cpu_feature_enabled(X86_FEATURE_PCID)) | |
268 | return; | |
269 | ||
270 | if (!static_cpu_has(X86_FEATURE_PTI)) | |
271 | return; | |
272 | ||
273 | __set_bit(kern_pcid(asid), | |
274 | (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask)); | |
275 | } | |
276 | ||
48e11198 DH |
277 | static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush) |
278 | { | |
279 | unsigned long new_mm_cr3; | |
280 | ||
281 | if (need_flush) { | |
6fd166aa | 282 | invalidate_user_asid(new_asid); |
48e11198 DH |
283 | new_mm_cr3 = build_cr3(pgdir, new_asid); |
284 | } else { | |
285 | new_mm_cr3 = build_cr3_noflush(pgdir, new_asid); | |
286 | } | |
287 | ||
288 | /* | |
289 | * Caution: many callers of this function expect | |
290 | * that load_cr3() is serializing and orders TLB | |
291 | * fills with respect to the mm_cpumask writes. | |
292 | */ | |
293 | write_cr3(new_mm_cr3); | |
294 | } | |
295 | ||
c048fdfe GC |
296 | void leave_mm(int cpu) |
297 | { | |
3d28ebce AL |
298 | struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); |
299 | ||
300 | /* | |
301 | * It's plausible that we're in lazy TLB mode while our mm is init_mm. | |
302 | * If so, our callers still expect us to flush the TLB, but there | |
303 | * aren't any user TLB entries in init_mm to worry about. | |
304 | * | |
305 | * This needs to happen before any other sanity checks due to | |
306 | * intel_idle's shenanigans. | |
307 | */ | |
308 | if (loaded_mm == &init_mm) | |
309 | return; | |
310 | ||
94b1b03b | 311 | /* Warn if we're not lazy. */ |
2f4305b1 | 312 | WARN_ON(!this_cpu_read(cpu_tlbstate_shared.is_lazy)); |
3d28ebce AL |
313 | |
314 | switch_mm(NULL, &init_mm, NULL); | |
c048fdfe | 315 | } |
67535736 | 316 | EXPORT_SYMBOL_GPL(leave_mm); |
c048fdfe | 317 | |
69c0319a AL |
318 | void switch_mm(struct mm_struct *prev, struct mm_struct *next, |
319 | struct task_struct *tsk) | |
078194f8 AL |
320 | { |
321 | unsigned long flags; | |
322 | ||
323 | local_irq_save(flags); | |
324 | switch_mm_irqs_off(prev, next, tsk); | |
325 | local_irq_restore(flags); | |
326 | } | |
327 | ||
b5f06f64 BS |
328 | /* |
329 | * Invoked from return to user/guest by a task that opted-in to L1D | |
330 | * flushing but ended up running on an SMT enabled core due to wrong | |
331 | * affinity settings or CPU hotplug. This is part of the paranoid L1D flush | |
332 | * contract which this task requested. | |
333 | */ | |
334 | static void l1d_flush_force_sigbus(struct callback_head *ch) | |
335 | { | |
336 | force_sig(SIGBUS); | |
337 | } | |
338 | ||
339 | static void l1d_flush_evaluate(unsigned long prev_mm, unsigned long next_mm, | |
340 | struct task_struct *next) | |
341 | { | |
342 | /* Flush L1D if the outgoing task requests it */ | |
343 | if (prev_mm & LAST_USER_MM_L1D_FLUSH) | |
344 | wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); | |
345 | ||
346 | /* Check whether the incoming task opted in for L1D flush */ | |
347 | if (likely(!(next_mm & LAST_USER_MM_L1D_FLUSH))) | |
348 | return; | |
349 | ||
350 | /* | |
351 | * Validate that it is not running on an SMT sibling as this would | |
352 | * make the excercise pointless because the siblings share L1D. If | |
353 | * it runs on a SMT sibling, notify it with SIGBUS on return to | |
354 | * user/guest | |
355 | */ | |
356 | if (this_cpu_read(cpu_info.smt_active)) { | |
357 | clear_ti_thread_flag(&next->thread_info, TIF_SPEC_L1D_FLUSH); | |
358 | next->l1d_flush_kill.func = l1d_flush_force_sigbus; | |
359 | task_work_add(next, &next->l1d_flush_kill, TWA_RESUME); | |
360 | } | |
361 | } | |
362 | ||
371b09c6 | 363 | static unsigned long mm_mangle_tif_spec_bits(struct task_struct *next) |
4c71a2b6 | 364 | { |
dca99fb6 | 365 | unsigned long next_tif = read_task_thread_flags(next); |
371b09c6 | 366 | unsigned long spec_bits = (next_tif >> TIF_SPEC_IB) & LAST_USER_MM_SPEC_MASK; |
4c71a2b6 | 367 | |
b5f06f64 BS |
368 | /* |
369 | * Ensure that the bit shift above works as expected and the two flags | |
370 | * end up in bit 0 and 1. | |
371 | */ | |
372 | BUILD_BUG_ON(TIF_SPEC_L1D_FLUSH != TIF_SPEC_IB + 1); | |
373 | ||
371b09c6 | 374 | return (unsigned long)next->mm | spec_bits; |
4c71a2b6 TG |
375 | } |
376 | ||
371b09c6 | 377 | static void cond_mitigation(struct task_struct *next) |
dbfe2953 | 378 | { |
371b09c6 BS |
379 | unsigned long prev_mm, next_mm; |
380 | ||
4c71a2b6 TG |
381 | if (!next || !next->mm) |
382 | return; | |
383 | ||
371b09c6 BS |
384 | next_mm = mm_mangle_tif_spec_bits(next); |
385 | prev_mm = this_cpu_read(cpu_tlbstate.last_user_mm_spec); | |
386 | ||
dbfe2953 | 387 | /* |
371b09c6 BS |
388 | * Avoid user/user BTB poisoning by flushing the branch predictor |
389 | * when switching between processes. This stops one process from | |
390 | * doing Spectre-v2 attacks on another. | |
391 | * | |
4c71a2b6 TG |
392 | * Both, the conditional and the always IBPB mode use the mm |
393 | * pointer to avoid the IBPB when switching between tasks of the | |
394 | * same process. Using the mm pointer instead of mm->context.ctx_id | |
395 | * opens a hypothetical hole vs. mm_struct reuse, which is more or | |
396 | * less impossible to control by an attacker. Aside of that it | |
397 | * would only affect the first schedule so the theoretically | |
398 | * exposed data is not really interesting. | |
dbfe2953 | 399 | */ |
4c71a2b6 | 400 | if (static_branch_likely(&switch_mm_cond_ibpb)) { |
4c71a2b6 TG |
401 | /* |
402 | * This is a bit more complex than the always mode because | |
403 | * it has to handle two cases: | |
404 | * | |
405 | * 1) Switch from a user space task (potential attacker) | |
406 | * which has TIF_SPEC_IB set to a user space task | |
407 | * (potential victim) which has TIF_SPEC_IB not set. | |
408 | * | |
409 | * 2) Switch from a user space task (potential attacker) | |
410 | * which has TIF_SPEC_IB not set to a user space task | |
411 | * (potential victim) which has TIF_SPEC_IB set. | |
412 | * | |
413 | * This could be done by unconditionally issuing IBPB when | |
414 | * a task which has TIF_SPEC_IB set is either scheduled in | |
415 | * or out. Though that results in two flushes when: | |
416 | * | |
417 | * - the same user space task is scheduled out and later | |
418 | * scheduled in again and only a kernel thread ran in | |
419 | * between. | |
420 | * | |
421 | * - a user space task belonging to the same process is | |
422 | * scheduled in after a kernel thread ran in between | |
423 | * | |
424 | * - a user space task belonging to the same process is | |
425 | * scheduled in immediately. | |
426 | * | |
427 | * Optimize this with reasonably small overhead for the | |
428 | * above cases. Mangle the TIF_SPEC_IB bit into the mm | |
429 | * pointer of the incoming task which is stored in | |
371b09c6 BS |
430 | * cpu_tlbstate.last_user_mm_spec for comparison. |
431 | * | |
4c71a2b6 TG |
432 | * Issue IBPB only if the mm's are different and one or |
433 | * both have the IBPB bit set. | |
434 | */ | |
435 | if (next_mm != prev_mm && | |
436 | (next_mm | prev_mm) & LAST_USER_MM_IBPB) | |
437 | indirect_branch_prediction_barrier(); | |
4c71a2b6 TG |
438 | } |
439 | ||
440 | if (static_branch_unlikely(&switch_mm_always_ibpb)) { | |
441 | /* | |
442 | * Only flush when switching to a user space task with a | |
443 | * different context than the user space task which ran | |
444 | * last on this CPU. | |
445 | */ | |
371b09c6 BS |
446 | if ((prev_mm & ~LAST_USER_MM_SPEC_MASK) != |
447 | (unsigned long)next->mm) | |
4c71a2b6 | 448 | indirect_branch_prediction_barrier(); |
4c71a2b6 | 449 | } |
371b09c6 | 450 | |
b5f06f64 BS |
451 | if (static_branch_unlikely(&switch_mm_cond_l1d_flush)) { |
452 | /* | |
453 | * Flush L1D when the outgoing task requested it and/or | |
454 | * check whether the incoming task requested L1D flushing | |
455 | * and ended up on an SMT sibling. | |
456 | */ | |
457 | if (unlikely((prev_mm | next_mm) & LAST_USER_MM_L1D_FLUSH)) | |
458 | l1d_flush_evaluate(prev_mm, next_mm, next); | |
459 | } | |
460 | ||
371b09c6 | 461 | this_cpu_write(cpu_tlbstate.last_user_mm_spec, next_mm); |
dbfe2953 JK |
462 | } |
463 | ||
cb2a0235 TG |
464 | #ifdef CONFIG_PERF_EVENTS |
465 | static inline void cr4_update_pce_mm(struct mm_struct *mm) | |
466 | { | |
467 | if (static_branch_unlikely(&rdpmc_always_available_key) || | |
468 | (!static_branch_unlikely(&rdpmc_never_available_key) && | |
5471eea5 KL |
469 | atomic_read(&mm->context.perf_rdpmc_allowed))) { |
470 | /* | |
471 | * Clear the existing dirty counters to | |
472 | * prevent the leak for an RDPMC task. | |
473 | */ | |
474 | perf_clear_dirty_counters(); | |
cb2a0235 | 475 | cr4_set_bits_irqsoff(X86_CR4_PCE); |
5471eea5 | 476 | } else |
cb2a0235 TG |
477 | cr4_clear_bits_irqsoff(X86_CR4_PCE); |
478 | } | |
479 | ||
480 | void cr4_update_pce(void *ignored) | |
481 | { | |
482 | cr4_update_pce_mm(this_cpu_read(cpu_tlbstate.loaded_mm)); | |
483 | } | |
484 | ||
485 | #else | |
486 | static inline void cr4_update_pce_mm(struct mm_struct *mm) { } | |
487 | #endif | |
488 | ||
078194f8 AL |
489 | void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, |
490 | struct task_struct *tsk) | |
69c0319a | 491 | { |
3d28ebce | 492 | struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm); |
10af6235 | 493 | u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); |
2f4305b1 | 494 | bool was_lazy = this_cpu_read(cpu_tlbstate_shared.is_lazy); |
94b1b03b AL |
495 | unsigned cpu = smp_processor_id(); |
496 | u64 next_tlb_gen; | |
12c4d978 RR |
497 | bool need_flush; |
498 | u16 new_asid; | |
69c0319a | 499 | |
3d28ebce | 500 | /* |
94b1b03b AL |
501 | * NB: The scheduler will call us with prev == next when switching |
502 | * from lazy TLB mode to normal mode if active_mm isn't changing. | |
503 | * When this happens, we don't assume that CR3 (and hence | |
504 | * cpu_tlbstate.loaded_mm) matches next. | |
3d28ebce AL |
505 | * |
506 | * NB: leave_mm() calls us with prev == NULL and tsk == NULL. | |
507 | */ | |
e37e43a4 | 508 | |
4c1ba392 | 509 | /* We don't want flush_tlb_func() to run concurrently with us. */ |
94b1b03b AL |
510 | if (IS_ENABLED(CONFIG_PROVE_LOCKING)) |
511 | WARN_ON_ONCE(!irqs_disabled()); | |
512 | ||
513 | /* | |
514 | * Verify that CR3 is what we think it is. This will catch | |
515 | * hypothetical buggy code that directly switches to swapper_pg_dir | |
10af6235 AL |
516 | * without going through leave_mm() / switch_mm_irqs_off() or that |
517 | * does something like write_cr3(read_cr3_pa()). | |
a376e7f9 AL |
518 | * |
519 | * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3() | |
520 | * isn't free. | |
94b1b03b | 521 | */ |
a376e7f9 | 522 | #ifdef CONFIG_DEBUG_VM |
50fb83a6 | 523 | if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) { |
a376e7f9 AL |
524 | /* |
525 | * If we were to BUG here, we'd be very likely to kill | |
526 | * the system so hard that we don't see the call trace. | |
527 | * Try to recover instead by ignoring the error and doing | |
528 | * a global flush to minimize the chance of corruption. | |
529 | * | |
530 | * (This is far from being a fully correct recovery. | |
531 | * Architecturally, the CPU could prefetch something | |
532 | * back into an incorrect ASID slot and leave it there | |
533 | * to cause trouble down the road. It's better than | |
534 | * nothing, though.) | |
535 | */ | |
536 | __flush_tlb_all(); | |
537 | } | |
538 | #endif | |
09c5272e NA |
539 | if (was_lazy) |
540 | this_cpu_write(cpu_tlbstate_shared.is_lazy, false); | |
e37e43a4 | 541 | |
306e0604 | 542 | /* |
10bcc80e MD |
543 | * The membarrier system call requires a full memory barrier and |
544 | * core serialization before returning to user-space, after | |
a493d1ca AL |
545 | * storing to rq->curr, when changing mm. This is because |
546 | * membarrier() sends IPIs to all CPUs that are in the target mm | |
547 | * to make them issue memory barriers. However, if another CPU | |
548 | * switches to/from the target mm concurrently with | |
549 | * membarrier(), it can cause that CPU not to receive an IPI | |
550 | * when it really should issue a memory barrier. Writing to CR3 | |
551 | * provides that full memory barrier and core serializing | |
552 | * instruction. | |
306e0604 | 553 | */ |
3d28ebce | 554 | if (real_prev == next) { |
e8b9b0cc AL |
555 | VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != |
556 | next->context.ctx_id); | |
94b1b03b | 557 | |
69c0319a | 558 | /* |
145f573b RR |
559 | * Even in lazy TLB mode, the CPU should stay set in the |
560 | * mm_cpumask. The TLB shootdown code can figure out from | |
2f4305b1 | 561 | * cpu_tlbstate_shared.is_lazy whether or not to send an IPI. |
69c0319a | 562 | */ |
b956575b AL |
563 | if (WARN_ON_ONCE(real_prev != &init_mm && |
564 | !cpumask_test_cpu(cpu, mm_cpumask(next)))) | |
565 | cpumask_set_cpu(cpu, mm_cpumask(next)); | |
566 | ||
145f573b RR |
567 | /* |
568 | * If the CPU is not in lazy TLB mode, we are just switching | |
569 | * from one thread in a process to another thread in the same | |
570 | * process. No TLB flush required. | |
571 | */ | |
572 | if (!was_lazy) | |
573 | return; | |
574 | ||
575 | /* | |
576 | * Read the tlb_gen to check whether a flush is needed. | |
577 | * If the TLB is up to date, just use it. | |
578 | * The barrier synchronizes with the tlb_gen increment in | |
579 | * the TLB shootdown code. | |
580 | */ | |
581 | smp_mb(); | |
582 | next_tlb_gen = atomic64_read(&next->context.tlb_gen); | |
583 | if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) == | |
584 | next_tlb_gen) | |
585 | return; | |
586 | ||
587 | /* | |
588 | * TLB contents went out of date while we were in lazy | |
589 | * mode. Fall through to the TLB switching code below. | |
590 | */ | |
591 | new_asid = prev_asid; | |
592 | need_flush = true; | |
94b1b03b | 593 | } else { |
18bf3c3e | 594 | /* |
371b09c6 BS |
595 | * Apply process to process speculation vulnerability |
596 | * mitigations if applicable. | |
18bf3c3e | 597 | */ |
371b09c6 | 598 | cond_mitigation(tsk); |
94b1b03b | 599 | |
e9d8c615 RR |
600 | /* |
601 | * Stop remote flushes for the previous mm. | |
602 | * Skip kernel threads; we never send init_mm TLB flushing IPIs, | |
603 | * but the bitmap manipulation can cause cache line contention. | |
604 | */ | |
605 | if (real_prev != &init_mm) { | |
606 | VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu, | |
607 | mm_cpumask(real_prev))); | |
608 | cpumask_clear_cpu(cpu, mm_cpumask(real_prev)); | |
609 | } | |
3d28ebce | 610 | |
94b1b03b AL |
611 | /* |
612 | * Start remote flushes and then read tlb_gen. | |
613 | */ | |
e9d8c615 RR |
614 | if (next != &init_mm) |
615 | cpumask_set_cpu(cpu, mm_cpumask(next)); | |
94b1b03b | 616 | next_tlb_gen = atomic64_read(&next->context.tlb_gen); |
3d28ebce | 617 | |
10af6235 | 618 | choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); |
3d28ebce | 619 | |
4012e77a AL |
620 | /* Let nmi_uaccess_okay() know that we're changing CR3. */ |
621 | this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING); | |
622 | barrier(); | |
12c4d978 | 623 | } |
4012e77a | 624 | |
12c4d978 RR |
625 | if (need_flush) { |
626 | this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); | |
627 | this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); | |
628 | load_new_mm_cr3(next->pgd, new_asid, true); | |
10af6235 | 629 | |
bf9282dc | 630 | trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL); |
12c4d978 RR |
631 | } else { |
632 | /* The new ASID is already up to date. */ | |
633 | load_new_mm_cr3(next->pgd, new_asid, false); | |
4012e77a | 634 | |
bf9282dc | 635 | trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0); |
94b1b03b | 636 | } |
3d28ebce | 637 | |
12c4d978 RR |
638 | /* Make sure we write CR3 before loaded_mm. */ |
639 | barrier(); | |
640 | ||
641 | this_cpu_write(cpu_tlbstate.loaded_mm, next); | |
642 | this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid); | |
643 | ||
145f573b | 644 | if (next != real_prev) { |
cb2a0235 | 645 | cr4_update_pce_mm(next); |
145f573b RR |
646 | switch_ldt(real_prev, next); |
647 | } | |
69c0319a AL |
648 | } |
649 | ||
b956575b | 650 | /* |
4e57b946 AL |
651 | * Please ignore the name of this function. It should be called |
652 | * switch_to_kernel_thread(). | |
653 | * | |
b956575b AL |
654 | * enter_lazy_tlb() is a hint from the scheduler that we are entering a |
655 | * kernel thread or other context without an mm. Acceptable implementations | |
656 | * include doing nothing whatsoever, switching to init_mm, or various clever | |
657 | * lazy tricks to try to minimize TLB flushes. | |
658 | * | |
659 | * The scheduler reserves the right to call enter_lazy_tlb() several times | |
660 | * in a row. It will notify us that we're going back to a real mm by | |
661 | * calling switch_mm_irqs_off(). | |
662 | */ | |
663 | void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | |
664 | { | |
665 | if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm) | |
666 | return; | |
667 | ||
2f4305b1 | 668 | this_cpu_write(cpu_tlbstate_shared.is_lazy, true); |
b956575b AL |
669 | } |
670 | ||
72c0098d AL |
671 | /* |
672 | * Call this when reinitializing a CPU. It fixes the following potential | |
673 | * problems: | |
674 | * | |
675 | * - The ASID changed from what cpu_tlbstate thinks it is (most likely | |
676 | * because the CPU was taken down and came back up with CR3's PCID | |
677 | * bits clear. CPU hotplug can do this. | |
678 | * | |
679 | * - The TLB contains junk in slots corresponding to inactive ASIDs. | |
680 | * | |
681 | * - The CPU went so far out to lunch that it may have missed a TLB | |
682 | * flush. | |
683 | */ | |
684 | void initialize_tlbstate_and_flush(void) | |
685 | { | |
686 | int i; | |
687 | struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm); | |
688 | u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen); | |
689 | unsigned long cr3 = __read_cr3(); | |
690 | ||
691 | /* Assert that CR3 already references the right mm. */ | |
692 | WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd)); | |
693 | ||
694 | /* | |
695 | * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization | |
696 | * doesn't work like other CR4 bits because it can only be set from | |
697 | * long mode.) | |
698 | */ | |
7898f796 | 699 | WARN_ON(boot_cpu_has(X86_FEATURE_PCID) && |
72c0098d AL |
700 | !(cr4_read_shadow() & X86_CR4_PCIDE)); |
701 | ||
702 | /* Force ASID 0 and force a TLB flush. */ | |
50fb83a6 | 703 | write_cr3(build_cr3(mm->pgd, 0)); |
72c0098d AL |
704 | |
705 | /* Reinitialize tlbstate. */ | |
371b09c6 | 706 | this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_INIT); |
72c0098d AL |
707 | this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0); |
708 | this_cpu_write(cpu_tlbstate.next_asid, 1); | |
709 | this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id); | |
710 | this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen); | |
711 | ||
712 | for (i = 1; i < TLB_NR_DYN_ASIDS; i++) | |
713 | this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0); | |
714 | } | |
715 | ||
b0579ade | 716 | /* |
4c1ba392 | 717 | * flush_tlb_func()'s memory ordering requirement is that any |
b0579ade AL |
718 | * TLB fills that happen after we flush the TLB are ordered after we |
719 | * read active_mm's tlb_gen. We don't need any explicit barriers | |
720 | * because all x86 flush operations are serializing and the | |
721 | * atomic64_read operation won't be reordered by the compiler. | |
722 | */ | |
4c1ba392 | 723 | static void flush_tlb_func(void *info) |
c048fdfe | 724 | { |
b0579ade AL |
725 | /* |
726 | * We have three different tlb_gen values in here. They are: | |
727 | * | |
728 | * - mm_tlb_gen: the latest generation. | |
729 | * - local_tlb_gen: the generation that this CPU has already caught | |
730 | * up to. | |
731 | * - f->new_tlb_gen: the generation that the requester of the flush | |
732 | * wants us to catch up to. | |
733 | */ | |
4c1ba392 | 734 | const struct flush_tlb_info *f = info; |
b0579ade | 735 | struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); |
10af6235 | 736 | u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); |
b0579ade | 737 | u64 mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen); |
10af6235 | 738 | u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); |
4c1ba392 NA |
739 | bool local = smp_processor_id() == f->initiating_cpu; |
740 | unsigned long nr_invalidate = 0; | |
b0579ade | 741 | |
bc0d5a89 AL |
742 | /* This code cannot presently handle being reentered. */ |
743 | VM_WARN_ON(!irqs_disabled()); | |
744 | ||
4c1ba392 NA |
745 | if (!local) { |
746 | inc_irq_stat(irq_tlb_count); | |
747 | count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); | |
748 | ||
749 | /* Can only happen on remote CPUs */ | |
750 | if (f->mm && f->mm != loaded_mm) | |
751 | return; | |
752 | } | |
753 | ||
b956575b AL |
754 | if (unlikely(loaded_mm == &init_mm)) |
755 | return; | |
756 | ||
10af6235 | 757 | VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) != |
b0579ade AL |
758 | loaded_mm->context.ctx_id); |
759 | ||
2f4305b1 | 760 | if (this_cpu_read(cpu_tlbstate_shared.is_lazy)) { |
b0579ade | 761 | /* |
b956575b AL |
762 | * We're in lazy mode. We need to at least flush our |
763 | * paging-structure cache to avoid speculatively reading | |
764 | * garbage into our TLB. Since switching to init_mm is barely | |
765 | * slower than a minimal flush, just switch to init_mm. | |
145f573b | 766 | * |
4ce94eab | 767 | * This should be rare, with native_flush_tlb_multi() skipping |
145f573b | 768 | * IPIs to lazy TLB mode CPUs. |
b0579ade | 769 | */ |
b956575b | 770 | switch_mm_irqs_off(NULL, &init_mm, NULL); |
b3b90e5a AL |
771 | return; |
772 | } | |
c048fdfe | 773 | |
b0579ade AL |
774 | if (unlikely(local_tlb_gen == mm_tlb_gen)) { |
775 | /* | |
776 | * There's nothing to do: we're already up to date. This can | |
777 | * happen if two concurrent flushes happen -- the first flush to | |
778 | * be handled can catch us all the way up, leaving no work for | |
779 | * the second flush. | |
780 | */ | |
4c1ba392 | 781 | goto done; |
b0579ade AL |
782 | } |
783 | ||
784 | WARN_ON_ONCE(local_tlb_gen > mm_tlb_gen); | |
785 | WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen); | |
786 | ||
787 | /* | |
788 | * If we get to this point, we know that our TLB is out of date. | |
789 | * This does not strictly imply that we need to flush (it's | |
790 | * possible that f->new_tlb_gen <= local_tlb_gen), but we're | |
791 | * going to need to flush in the very near future, so we might | |
792 | * as well get it over with. | |
793 | * | |
794 | * The only question is whether to do a full or partial flush. | |
795 | * | |
796 | * We do a partial flush if requested and two extra conditions | |
797 | * are met: | |
798 | * | |
799 | * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that | |
800 | * we've always done all needed flushes to catch up to | |
801 | * local_tlb_gen. If, for example, local_tlb_gen == 2 and | |
802 | * f->new_tlb_gen == 3, then we know that the flush needed to bring | |
803 | * us up to date for tlb_gen 3 is the partial flush we're | |
804 | * processing. | |
805 | * | |
806 | * As an example of why this check is needed, suppose that there | |
807 | * are two concurrent flushes. The first is a full flush that | |
808 | * changes context.tlb_gen from 1 to 2. The second is a partial | |
809 | * flush that changes context.tlb_gen from 2 to 3. If they get | |
810 | * processed on this CPU in reverse order, we'll see | |
811 | * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL. | |
1299ef1d | 812 | * If we were to use __flush_tlb_one_user() and set local_tlb_gen to |
b0579ade AL |
813 | * 3, we'd be break the invariant: we'd update local_tlb_gen above |
814 | * 1 without the full flush that's needed for tlb_gen 2. | |
815 | * | |
d9f6e12f | 816 | * 2. f->new_tlb_gen == mm_tlb_gen. This is purely an optimization. |
b0579ade AL |
817 | * Partial TLB flushes are not all that much cheaper than full TLB |
818 | * flushes, so it seems unlikely that it would be a performance win | |
819 | * to do a partial flush if that won't bring our TLB fully up to | |
820 | * date. By doing a full flush instead, we can increase | |
821 | * local_tlb_gen all the way to mm_tlb_gen and we can probably | |
822 | * avoid another flush in the very near future. | |
823 | */ | |
824 | if (f->end != TLB_FLUSH_ALL && | |
825 | f->new_tlb_gen == local_tlb_gen + 1 && | |
826 | f->new_tlb_gen == mm_tlb_gen) { | |
827 | /* Partial flush */ | |
a31acd3e | 828 | unsigned long addr = f->start; |
b0579ade | 829 | |
4c1ba392 NA |
830 | nr_invalidate = (f->end - f->start) >> f->stride_shift; |
831 | ||
a2055abe | 832 | while (addr < f->end) { |
127ac915 | 833 | flush_tlb_one_user(addr); |
a31acd3e | 834 | addr += 1UL << f->stride_shift; |
b3b90e5a | 835 | } |
454bbad9 | 836 | if (local) |
a31acd3e | 837 | count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE, nr_invalidate); |
b0579ade AL |
838 | } else { |
839 | /* Full flush. */ | |
4c1ba392 NA |
840 | nr_invalidate = TLB_FLUSH_ALL; |
841 | ||
2faf153b | 842 | flush_tlb_local(); |
b0579ade AL |
843 | if (local) |
844 | count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); | |
b3b90e5a | 845 | } |
b0579ade AL |
846 | |
847 | /* Both paths above update our state to mm_tlb_gen. */ | |
10af6235 | 848 | this_cpu_write(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen, mm_tlb_gen); |
454bbad9 | 849 | |
4c1ba392 NA |
850 | /* Tracing is done in a unified manner to reduce the code size */ |
851 | done: | |
852 | trace_tlb_flush(!local ? TLB_REMOTE_SHOOTDOWN : | |
853 | (f->mm == NULL) ? TLB_LOCAL_SHOOTDOWN : | |
854 | TLB_LOCAL_MM_SHOOTDOWN, | |
855 | nr_invalidate); | |
454bbad9 AL |
856 | } |
857 | ||
d39268ad | 858 | static bool tlb_is_not_lazy(int cpu, void *data) |
454bbad9 | 859 | { |
2f4305b1 | 860 | return !per_cpu(cpu_tlbstate_shared.is_lazy, cpu); |
454bbad9 AL |
861 | } |
862 | ||
2f4305b1 NA |
863 | DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared); |
864 | EXPORT_PER_CPU_SYMBOL(cpu_tlbstate_shared); | |
145f573b | 865 | |
4ce94eab | 866 | STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask, |
29def599 | 867 | const struct flush_tlb_info *info) |
4595f962 | 868 | { |
4ce94eab NA |
869 | /* |
870 | * Do accounting and tracing. Note that there are (and have always been) | |
871 | * cases in which a remote TLB flush will be traced, but eventually | |
872 | * would not happen. | |
873 | */ | |
ec659934 | 874 | count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); |
a2055abe | 875 | if (info->end == TLB_FLUSH_ALL) |
18c98243 NA |
876 | trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL); |
877 | else | |
878 | trace_tlb_flush(TLB_REMOTE_SEND_IPI, | |
a2055abe | 879 | (info->end - info->start) >> PAGE_SHIFT); |
18c98243 | 880 | |
145f573b RR |
881 | /* |
882 | * If no page tables were freed, we can skip sending IPIs to | |
883 | * CPUs in lazy TLB mode. They will flush the CPU themselves | |
884 | * at the next context switch. | |
885 | * | |
886 | * However, if page tables are getting freed, we need to send the | |
887 | * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping | |
888 | * up on the new contents of what used to be page tables, while | |
889 | * doing a speculative memory access. | |
890 | */ | |
d39268ad | 891 | if (info->freed_tables) |
4ce94eab | 892 | on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true); |
d39268ad DH |
893 | else |
894 | on_each_cpu_cond_mask(tlb_is_not_lazy, flush_tlb_func, | |
895 | (void *)info, 1, cpumask); | |
c048fdfe | 896 | } |
c048fdfe | 897 | |
4ce94eab | 898 | void flush_tlb_multi(const struct cpumask *cpumask, |
29def599 TG |
899 | const struct flush_tlb_info *info) |
900 | { | |
4ce94eab | 901 | __flush_tlb_multi(cpumask, info); |
29def599 TG |
902 | } |
903 | ||
a5102476 | 904 | /* |
cb1aaebe | 905 | * See Documentation/x86/tlb.rst for details. We choose 33 |
a5102476 DH |
906 | * because it is large enough to cover the vast majority (at |
907 | * least 95%) of allocations, and is small enough that we are | |
908 | * confident it will not cause too much overhead. Each single | |
909 | * flush is about 100 ns, so this caps the maximum overhead at | |
910 | * _about_ 3,000 ns. | |
911 | * | |
912 | * This is in units of pages. | |
913 | */ | |
935f5839 | 914 | unsigned long tlb_single_page_flush_ceiling __read_mostly = 33; |
e9f4e0a9 | 915 | |
3db6d5a5 NA |
916 | static DEFINE_PER_CPU_SHARED_ALIGNED(struct flush_tlb_info, flush_tlb_info); |
917 | ||
918 | #ifdef CONFIG_DEBUG_VM | |
919 | static DEFINE_PER_CPU(unsigned int, flush_tlb_info_idx); | |
920 | #endif | |
921 | ||
1608e4cf | 922 | static struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm, |
3db6d5a5 NA |
923 | unsigned long start, unsigned long end, |
924 | unsigned int stride_shift, bool freed_tables, | |
925 | u64 new_tlb_gen) | |
926 | { | |
927 | struct flush_tlb_info *info = this_cpu_ptr(&flush_tlb_info); | |
928 | ||
929 | #ifdef CONFIG_DEBUG_VM | |
930 | /* | |
931 | * Ensure that the following code is non-reentrant and flush_tlb_info | |
932 | * is not overwritten. This means no TLB flushing is initiated by | |
933 | * interrupt handlers and machine-check exception handlers. | |
934 | */ | |
935 | BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) != 1); | |
936 | #endif | |
937 | ||
938 | info->start = start; | |
939 | info->end = end; | |
940 | info->mm = mm; | |
941 | info->stride_shift = stride_shift; | |
942 | info->freed_tables = freed_tables; | |
943 | info->new_tlb_gen = new_tlb_gen; | |
4c1ba392 | 944 | info->initiating_cpu = smp_processor_id(); |
3db6d5a5 NA |
945 | |
946 | return info; | |
947 | } | |
948 | ||
1608e4cf | 949 | static void put_flush_tlb_info(void) |
3db6d5a5 NA |
950 | { |
951 | #ifdef CONFIG_DEBUG_VM | |
d9f6e12f | 952 | /* Complete reentrancy prevention checks */ |
3db6d5a5 NA |
953 | barrier(); |
954 | this_cpu_dec(flush_tlb_info_idx); | |
955 | #endif | |
956 | } | |
957 | ||
611ae8e3 | 958 | void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, |
016c4d92 RR |
959 | unsigned long end, unsigned int stride_shift, |
960 | bool freed_tables) | |
611ae8e3 | 961 | { |
3db6d5a5 NA |
962 | struct flush_tlb_info *info; |
963 | u64 new_tlb_gen; | |
454bbad9 | 964 | int cpu; |
ce27374f | 965 | |
454bbad9 | 966 | cpu = get_cpu(); |
71b3c126 | 967 | |
454bbad9 | 968 | /* Should we flush just the requested range? */ |
3db6d5a5 NA |
969 | if ((end == TLB_FLUSH_ALL) || |
970 | ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) { | |
971 | start = 0; | |
972 | end = TLB_FLUSH_ALL; | |
4995ab9c | 973 | } |
454bbad9 | 974 | |
3db6d5a5 NA |
975 | /* This is also a barrier that synchronizes with switch_mm(). */ |
976 | new_tlb_gen = inc_mm_tlb_gen(mm); | |
977 | ||
978 | info = get_flush_tlb_info(mm, start, end, stride_shift, freed_tables, | |
979 | new_tlb_gen); | |
980 | ||
4ce94eab NA |
981 | /* |
982 | * flush_tlb_multi() is not optimized for the common case in which only | |
983 | * a local TLB flush is needed. Optimize this use-case by calling | |
984 | * flush_tlb_func_local() directly in this case. | |
985 | */ | |
986 | if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) { | |
987 | flush_tlb_multi(mm_cpumask(mm), info); | |
988 | } else if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) { | |
3db6d5a5 | 989 | lockdep_assert_irqs_enabled(); |
bc0d5a89 | 990 | local_irq_disable(); |
4c1ba392 | 991 | flush_tlb_func(info); |
bc0d5a89 AL |
992 | local_irq_enable(); |
993 | } | |
994 | ||
3db6d5a5 | 995 | put_flush_tlb_info(); |
454bbad9 | 996 | put_cpu(); |
c048fdfe GC |
997 | } |
998 | ||
a2055abe | 999 | |
c048fdfe GC |
1000 | static void do_flush_tlb_all(void *info) |
1001 | { | |
ec659934 | 1002 | count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); |
c048fdfe | 1003 | __flush_tlb_all(); |
c048fdfe GC |
1004 | } |
1005 | ||
1006 | void flush_tlb_all(void) | |
1007 | { | |
ec659934 | 1008 | count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); |
15c8b6c1 | 1009 | on_each_cpu(do_flush_tlb_all, NULL, 1); |
c048fdfe | 1010 | } |
3df3212f | 1011 | |
effee4b9 AS |
1012 | static void do_kernel_range_flush(void *info) |
1013 | { | |
1014 | struct flush_tlb_info *f = info; | |
1015 | unsigned long addr; | |
1016 | ||
1017 | /* flush range by one by one 'invlpg' */ | |
a2055abe | 1018 | for (addr = f->start; addr < f->end; addr += PAGE_SIZE) |
58430c5d | 1019 | flush_tlb_one_kernel(addr); |
effee4b9 AS |
1020 | } |
1021 | ||
1022 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
1023 | { | |
effee4b9 | 1024 | /* Balance as user space task's flush, a bit conservative */ |
e9f4e0a9 | 1025 | if (end == TLB_FLUSH_ALL || |
be4ffc0d | 1026 | (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) { |
effee4b9 | 1027 | on_each_cpu(do_flush_tlb_all, NULL, 1); |
e9f4e0a9 | 1028 | } else { |
3db6d5a5 NA |
1029 | struct flush_tlb_info *info; |
1030 | ||
1031 | preempt_disable(); | |
1032 | info = get_flush_tlb_info(NULL, start, end, 0, false, 0); | |
1033 | ||
1034 | on_each_cpu(do_kernel_range_flush, info, 1); | |
1035 | ||
1036 | put_flush_tlb_info(); | |
1037 | preempt_enable(); | |
effee4b9 AS |
1038 | } |
1039 | } | |
2d040a1c | 1040 | |
8c5cc19e TG |
1041 | /* |
1042 | * This can be used from process context to figure out what the value of | |
1043 | * CR3 is without needing to do a (slow) __read_cr3(). | |
1044 | * | |
1045 | * It's intended to be used for code like KVM that sneakily changes CR3 | |
1046 | * and needs to restore it. It needs to be used very carefully. | |
1047 | */ | |
1048 | unsigned long __get_current_cr3_fast(void) | |
1049 | { | |
1050 | unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd, | |
1051 | this_cpu_read(cpu_tlbstate.loaded_mm_asid)); | |
1052 | ||
1053 | /* For now, be very restrictive about when this can be called. */ | |
1054 | VM_WARN_ON(in_nmi() || preemptible()); | |
1055 | ||
1056 | VM_BUG_ON(cr3 != __read_cr3()); | |
1057 | return cr3; | |
1058 | } | |
1059 | EXPORT_SYMBOL_GPL(__get_current_cr3_fast); | |
1060 | ||
58430c5d TG |
1061 | /* |
1062 | * Flush one page in the kernel mapping | |
1063 | */ | |
1064 | void flush_tlb_one_kernel(unsigned long addr) | |
1065 | { | |
1066 | count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); | |
1067 | ||
1068 | /* | |
1069 | * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its | |
1070 | * paravirt equivalent. Even with PCID, this is sufficient: we only | |
1071 | * use PCID if we also use global PTEs for the kernel mapping, and | |
1072 | * INVLPG flushes global translations across all address spaces. | |
1073 | * | |
1074 | * If PTI is on, then the kernel is mapped with non-global PTEs, and | |
1075 | * __flush_tlb_one_user() will flush the given address for the current | |
1076 | * kernel address space and for its usermode counterpart, but it does | |
1077 | * not flush it for other address spaces. | |
1078 | */ | |
1079 | flush_tlb_one_user(addr); | |
1080 | ||
1081 | if (!static_cpu_has(X86_FEATURE_PTI)) | |
1082 | return; | |
1083 | ||
1084 | /* | |
1085 | * See above. We need to propagate the flush to all other address | |
1086 | * spaces. In principle, we only need to propagate it to kernelmode | |
1087 | * address spaces, but the extra bookkeeping we would need is not | |
1088 | * worth it. | |
1089 | */ | |
1090 | this_cpu_write(cpu_tlbstate.invalidate_other, true); | |
1091 | } | |
1092 | ||
127ac915 TG |
1093 | /* |
1094 | * Flush one page in the user mapping | |
1095 | */ | |
1096 | STATIC_NOPV void native_flush_tlb_one_user(unsigned long addr) | |
1097 | { | |
1098 | u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); | |
1099 | ||
1100 | asm volatile("invlpg (%0)" ::"r" (addr) : "memory"); | |
1101 | ||
1102 | if (!static_cpu_has(X86_FEATURE_PTI)) | |
1103 | return; | |
1104 | ||
1105 | /* | |
1106 | * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1. | |
1107 | * Just use invalidate_user_asid() in case we are called early. | |
1108 | */ | |
1109 | if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE)) | |
1110 | invalidate_user_asid(loaded_mm_asid); | |
1111 | else | |
1112 | invpcid_flush_one(user_pcid(loaded_mm_asid), addr); | |
1113 | } | |
1114 | ||
1115 | void flush_tlb_one_user(unsigned long addr) | |
1116 | { | |
1117 | __flush_tlb_one_user(addr); | |
1118 | } | |
1119 | ||
cd30d26c TG |
1120 | /* |
1121 | * Flush everything | |
1122 | */ | |
1123 | STATIC_NOPV void native_flush_tlb_global(void) | |
1124 | { | |
f154f290 | 1125 | unsigned long flags; |
cd30d26c TG |
1126 | |
1127 | if (static_cpu_has(X86_FEATURE_INVPCID)) { | |
1128 | /* | |
1129 | * Using INVPCID is considerably faster than a pair of writes | |
1130 | * to CR4 sandwiched inside an IRQ flag save/restore. | |
1131 | * | |
1132 | * Note, this works with CR4.PCIDE=0 or 1. | |
1133 | */ | |
1134 | invpcid_flush_all(); | |
1135 | return; | |
1136 | } | |
1137 | ||
1138 | /* | |
1139 | * Read-modify-write to CR4 - protect it from preemption and | |
1140 | * from interrupts. (Use the raw variant because this code can | |
1141 | * be called from deep inside debugging code.) | |
1142 | */ | |
1143 | raw_local_irq_save(flags); | |
1144 | ||
f154f290 | 1145 | __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4)); |
cd30d26c TG |
1146 | |
1147 | raw_local_irq_restore(flags); | |
1148 | } | |
1149 | ||
2faf153b TG |
1150 | /* |
1151 | * Flush the entire current user mapping | |
1152 | */ | |
1153 | STATIC_NOPV void native_flush_tlb_local(void) | |
1154 | { | |
1155 | /* | |
1156 | * Preemption or interrupts must be disabled to protect the access | |
1157 | * to the per CPU variable and to prevent being preempted between | |
1158 | * read_cr3() and write_cr3(). | |
1159 | */ | |
1160 | WARN_ON_ONCE(preemptible()); | |
1161 | ||
1162 | invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid)); | |
1163 | ||
1164 | /* If current->mm == NULL then the read_cr3() "borrows" an mm */ | |
1165 | native_write_cr3(__native_read_cr3()); | |
1166 | } | |
1167 | ||
1168 | void flush_tlb_local(void) | |
1169 | { | |
1170 | __flush_tlb_local(); | |
1171 | } | |
4b04e6c2 TG |
1172 | |
1173 | /* | |
1174 | * Flush everything | |
1175 | */ | |
1176 | void __flush_tlb_all(void) | |
1177 | { | |
1178 | /* | |
1179 | * This is to catch users with enabled preemption and the PGE feature | |
1180 | * and don't trigger the warning in __native_flush_tlb(). | |
1181 | */ | |
1182 | VM_WARN_ON_ONCE(preemptible()); | |
1183 | ||
1184 | if (boot_cpu_has(X86_FEATURE_PGE)) { | |
1185 | __flush_tlb_global(); | |
1186 | } else { | |
1187 | /* | |
1188 | * !PGE -> !PCID (setup_pcid()), thus every flush is total. | |
1189 | */ | |
1190 | flush_tlb_local(); | |
1191 | } | |
1192 | } | |
1193 | EXPORT_SYMBOL_GPL(__flush_tlb_all); | |
2faf153b | 1194 | |
e73ad5ff AL |
1195 | void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) |
1196 | { | |
4c1ba392 NA |
1197 | struct flush_tlb_info *info; |
1198 | ||
e73ad5ff AL |
1199 | int cpu = get_cpu(); |
1200 | ||
4c1ba392 | 1201 | info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false, 0); |
4ce94eab NA |
1202 | /* |
1203 | * flush_tlb_multi() is not optimized for the common case in which only | |
1204 | * a local TLB flush is needed. Optimize this use-case by calling | |
1205 | * flush_tlb_func_local() directly in this case. | |
1206 | */ | |
1207 | if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { | |
1208 | flush_tlb_multi(&batch->cpumask, info); | |
1209 | } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { | |
3db6d5a5 | 1210 | lockdep_assert_irqs_enabled(); |
bc0d5a89 | 1211 | local_irq_disable(); |
4c1ba392 | 1212 | flush_tlb_func(info); |
bc0d5a89 AL |
1213 | local_irq_enable(); |
1214 | } | |
1215 | ||
e73ad5ff AL |
1216 | cpumask_clear(&batch->cpumask); |
1217 | ||
4c1ba392 | 1218 | put_flush_tlb_info(); |
e73ad5ff AL |
1219 | put_cpu(); |
1220 | } | |
1221 | ||
af5c40c6 TG |
1222 | /* |
1223 | * Blindly accessing user memory from NMI context can be dangerous | |
1224 | * if we're in the middle of switching the current user task or | |
1225 | * switching the loaded mm. It can also be dangerous if we | |
1226 | * interrupted some kernel code that was temporarily using a | |
1227 | * different mm. | |
1228 | */ | |
1229 | bool nmi_uaccess_okay(void) | |
1230 | { | |
1231 | struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); | |
1232 | struct mm_struct *current_mm = current->mm; | |
1233 | ||
1234 | VM_WARN_ON_ONCE(!loaded_mm); | |
1235 | ||
1236 | /* | |
1237 | * The condition we want to check is | |
1238 | * current_mm->pgd == __va(read_cr3_pa()). This may be slow, though, | |
1239 | * if we're running in a VM with shadow paging, and nmi_uaccess_okay() | |
1240 | * is supposed to be reasonably fast. | |
1241 | * | |
1242 | * Instead, we check the almost equivalent but somewhat conservative | |
1243 | * condition below, and we rely on the fact that switch_mm_irqs_off() | |
1244 | * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3. | |
1245 | */ | |
1246 | if (loaded_mm != current_mm) | |
1247 | return false; | |
1248 | ||
1249 | VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa())); | |
1250 | ||
1251 | return true; | |
1252 | } | |
1253 | ||
2d040a1c DH |
1254 | static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf, |
1255 | size_t count, loff_t *ppos) | |
1256 | { | |
1257 | char buf[32]; | |
1258 | unsigned int len; | |
1259 | ||
1260 | len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling); | |
1261 | return simple_read_from_buffer(user_buf, count, ppos, buf, len); | |
1262 | } | |
1263 | ||
1264 | static ssize_t tlbflush_write_file(struct file *file, | |
1265 | const char __user *user_buf, size_t count, loff_t *ppos) | |
1266 | { | |
1267 | char buf[32]; | |
1268 | ssize_t len; | |
1269 | int ceiling; | |
1270 | ||
1271 | len = min(count, sizeof(buf) - 1); | |
1272 | if (copy_from_user(buf, user_buf, len)) | |
1273 | return -EFAULT; | |
1274 | ||
1275 | buf[len] = '\0'; | |
1276 | if (kstrtoint(buf, 0, &ceiling)) | |
1277 | return -EINVAL; | |
1278 | ||
1279 | if (ceiling < 0) | |
1280 | return -EINVAL; | |
1281 | ||
1282 | tlb_single_page_flush_ceiling = ceiling; | |
1283 | return count; | |
1284 | } | |
1285 | ||
1286 | static const struct file_operations fops_tlbflush = { | |
1287 | .read = tlbflush_read_file, | |
1288 | .write = tlbflush_write_file, | |
1289 | .llseek = default_llseek, | |
1290 | }; | |
1291 | ||
1292 | static int __init create_tlb_single_page_flush_ceiling(void) | |
1293 | { | |
1294 | debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR, | |
1295 | arch_debugfs_dir, NULL, &fops_tlbflush); | |
1296 | return 0; | |
1297 | } | |
1298 | late_initcall(create_tlb_single_page_flush_ceiling); |