Commit | Line | Data |
---|---|---|
2e5d9c85 | 1 | /* |
2 | * Handle caching attributes in page tables (PAT) | |
3 | * | |
4 | * Authors: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> | |
5 | * Suresh B Siddha <suresh.b.siddha@intel.com> | |
6 | * | |
7 | * Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen. | |
8 | */ | |
9 | ||
10 | #include <linux/mm.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/gfp.h> | |
13 | #include <linux/fs.h> | |
e7f260a2 | 14 | #include <linux/bootmem.h> |
2e5d9c85 | 15 | |
16 | #include <asm/msr.h> | |
17 | #include <asm/tlbflush.h> | |
18 | #include <asm/processor.h> | |
0124cecf | 19 | #include <asm/page.h> |
2e5d9c85 | 20 | #include <asm/pgtable.h> |
21 | #include <asm/pat.h> | |
22 | #include <asm/e820.h> | |
23 | #include <asm/cacheflush.h> | |
24 | #include <asm/fcntl.h> | |
25 | #include <asm/mtrr.h> | |
e7f260a2 | 26 | #include <asm/io.h> |
2e5d9c85 | 27 | |
8d4a4300 | 28 | #ifdef CONFIG_X86_PAT |
499f8f84 | 29 | int __read_mostly pat_enabled = 1; |
2e5d9c85 | 30 | |
31f4d870 | 31 | void __cpuinit pat_disable(char *reason) |
2e5d9c85 | 32 | { |
499f8f84 | 33 | pat_enabled = 0; |
8d4a4300 | 34 | printk(KERN_INFO "%s\n", reason); |
2e5d9c85 | 35 | } |
2e5d9c85 | 36 | |
be524fb9 | 37 | static int __init nopat(char *str) |
2e5d9c85 | 38 | { |
8d4a4300 | 39 | pat_disable("PAT support disabled."); |
2e5d9c85 | 40 | return 0; |
41 | } | |
8d4a4300 TG |
42 | early_param("nopat", nopat); |
43 | #endif | |
44 | ||
77b52b4c VP |
45 | |
46 | static int debug_enable; | |
47 | static int __init pat_debug_setup(char *str) | |
48 | { | |
49 | debug_enable = 1; | |
50 | return 0; | |
51 | } | |
52 | __setup("debugpat", pat_debug_setup); | |
53 | ||
54 | #define dprintk(fmt, arg...) \ | |
55 | do { if (debug_enable) printk(KERN_INFO fmt, ##arg); } while (0) | |
56 | ||
57 | ||
8d4a4300 | 58 | static u64 __read_mostly boot_pat_state; |
2e5d9c85 | 59 | |
60 | enum { | |
61 | PAT_UC = 0, /* uncached */ | |
62 | PAT_WC = 1, /* Write combining */ | |
63 | PAT_WT = 4, /* Write Through */ | |
64 | PAT_WP = 5, /* Write Protected */ | |
65 | PAT_WB = 6, /* Write Back (default) */ | |
66 | PAT_UC_MINUS = 7, /* UC, but can be overriden by MTRR */ | |
67 | }; | |
68 | ||
cd7a4e93 | 69 | #define PAT(x, y) ((u64)PAT_ ## y << ((x)*8)) |
2e5d9c85 | 70 | |
71 | void pat_init(void) | |
72 | { | |
73 | u64 pat; | |
74 | ||
499f8f84 | 75 | if (!pat_enabled) |
2e5d9c85 | 76 | return; |
77 | ||
8d4a4300 | 78 | /* Paranoia check. */ |
97cfab6a | 79 | if (!cpu_has_pat && boot_pat_state) { |
8d4a4300 | 80 | /* |
97cfab6a | 81 | * If this happens we are on a secondary CPU, but |
8d4a4300 TG |
82 | * switched to PAT on the boot CPU. We have no way to |
83 | * undo PAT. | |
97cfab6a AH |
84 | */ |
85 | printk(KERN_ERR "PAT enabled, " | |
86 | "but not supported by secondary CPU\n"); | |
87 | BUG(); | |
8d4a4300 | 88 | } |
2e5d9c85 | 89 | |
90 | /* Set PWT to Write-Combining. All other bits stay the same */ | |
91 | /* | |
92 | * PTE encoding used in Linux: | |
93 | * PAT | |
94 | * |PCD | |
95 | * ||PWT | |
96 | * ||| | |
97 | * 000 WB _PAGE_CACHE_WB | |
98 | * 001 WC _PAGE_CACHE_WC | |
99 | * 010 UC- _PAGE_CACHE_UC_MINUS | |
100 | * 011 UC _PAGE_CACHE_UC | |
101 | * PAT bit unused | |
102 | */ | |
cd7a4e93 AH |
103 | pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) | |
104 | PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC); | |
2e5d9c85 | 105 | |
106 | /* Boot CPU check */ | |
8d4a4300 | 107 | if (!boot_pat_state) |
2e5d9c85 | 108 | rdmsrl(MSR_IA32_CR_PAT, boot_pat_state); |
2e5d9c85 | 109 | |
110 | wrmsrl(MSR_IA32_CR_PAT, pat); | |
111 | printk(KERN_INFO "x86 PAT enabled: cpu %d, old 0x%Lx, new 0x%Lx\n", | |
112 | smp_processor_id(), boot_pat_state, pat); | |
113 | } | |
114 | ||
115 | #undef PAT | |
116 | ||
117 | static char *cattr_name(unsigned long flags) | |
118 | { | |
119 | switch (flags & _PAGE_CACHE_MASK) { | |
cd7a4e93 AH |
120 | case _PAGE_CACHE_UC: return "uncached"; |
121 | case _PAGE_CACHE_UC_MINUS: return "uncached-minus"; | |
122 | case _PAGE_CACHE_WB: return "write-back"; | |
123 | case _PAGE_CACHE_WC: return "write-combining"; | |
124 | default: return "broken"; | |
2e5d9c85 | 125 | } |
126 | } | |
127 | ||
128 | /* | |
129 | * The global memtype list keeps track of memory type for specific | |
130 | * physical memory areas. Conflicting memory types in different | |
131 | * mappings can cause CPU cache corruption. To avoid this we keep track. | |
132 | * | |
133 | * The list is sorted based on starting address and can contain multiple | |
134 | * entries for each address (this allows reference counting for overlapping | |
135 | * areas). All the aliases have the same cache attributes of course. | |
136 | * Zero attributes are represented as holes. | |
137 | * | |
138 | * Currently the data structure is a list because the number of mappings | |
139 | * are expected to be relatively small. If this should be a problem | |
140 | * it could be changed to a rbtree or similar. | |
141 | * | |
142 | * memtype_lock protects the whole list. | |
143 | */ | |
144 | ||
145 | struct memtype { | |
146 | u64 start; | |
147 | u64 end; | |
148 | unsigned long type; | |
149 | struct list_head nd; | |
150 | }; | |
151 | ||
152 | static LIST_HEAD(memtype_list); | |
153 | static DEFINE_SPINLOCK(memtype_lock); /* protects memtype list */ | |
154 | ||
155 | /* | |
156 | * Does intersection of PAT memory type and MTRR memory type and returns | |
157 | * the resulting memory type as PAT understands it. | |
158 | * (Type in pat and mtrr will not have same value) | |
159 | * The intersection is based on "Effective Memory Type" tables in IA-32 | |
160 | * SDM vol 3a | |
161 | */ | |
6cf514fc | 162 | static unsigned long pat_x_mtrr_type(u64 start, u64 end, unsigned long req_type) |
2e5d9c85 | 163 | { |
c26421d0 VP |
164 | /* |
165 | * Look for MTRR hint to get the effective type in case where PAT | |
166 | * request is for WB. | |
167 | */ | |
dd0c7c49 AH |
168 | if (req_type == _PAGE_CACHE_WB) { |
169 | u8 mtrr_type; | |
170 | ||
171 | mtrr_type = mtrr_type_lookup(start, end); | |
172 | if (mtrr_type == MTRR_TYPE_UNCACHABLE) | |
173 | return _PAGE_CACHE_UC; | |
174 | if (mtrr_type == MTRR_TYPE_WRCOMB) | |
175 | return _PAGE_CACHE_WC; | |
176 | } | |
177 | ||
178 | return req_type; | |
2e5d9c85 | 179 | } |
180 | ||
64fe44c3 AH |
181 | static int chk_conflict(struct memtype *new, struct memtype *entry, |
182 | unsigned long *type) | |
183 | { | |
184 | if (new->type != entry->type) { | |
185 | if (type) { | |
186 | new->type = entry->type; | |
187 | *type = entry->type; | |
188 | } else | |
189 | goto conflict; | |
190 | } | |
191 | ||
192 | /* check overlaps with more than one entry in the list */ | |
193 | list_for_each_entry_continue(entry, &memtype_list, nd) { | |
194 | if (new->end <= entry->start) | |
195 | break; | |
196 | else if (new->type != entry->type) | |
197 | goto conflict; | |
198 | } | |
199 | return 0; | |
200 | ||
201 | conflict: | |
202 | printk(KERN_INFO "%s:%d conflicting memory types " | |
203 | "%Lx-%Lx %s<->%s\n", current->comm, current->pid, new->start, | |
204 | new->end, cattr_name(new->type), cattr_name(entry->type)); | |
205 | return -EBUSY; | |
206 | } | |
207 | ||
e7f260a2 | 208 | /* |
209 | * req_type typically has one of the: | |
210 | * - _PAGE_CACHE_WB | |
211 | * - _PAGE_CACHE_WC | |
212 | * - _PAGE_CACHE_UC_MINUS | |
213 | * - _PAGE_CACHE_UC | |
214 | * | |
215 | * req_type will have a special case value '-1', when requester want to inherit | |
216 | * the memory type from mtrr (if WB), existing PAT, defaulting to UC_MINUS. | |
217 | * | |
ac97991e AH |
218 | * If new_type is NULL, function will return an error if it cannot reserve the |
219 | * region with req_type. If new_type is non-NULL, function will return | |
220 | * available type in new_type in case of no error. In case of any error | |
e7f260a2 | 221 | * it will return a negative return value. |
222 | */ | |
2e5d9c85 | 223 | int reserve_memtype(u64 start, u64 end, unsigned long req_type, |
ac97991e | 224 | unsigned long *new_type) |
2e5d9c85 | 225 | { |
ac97991e | 226 | struct memtype *new, *entry; |
2e5d9c85 | 227 | unsigned long actual_type; |
f6887264 | 228 | struct list_head *where; |
2e5d9c85 | 229 | int err = 0; |
230 | ||
69e26be9 AH |
231 | BUG_ON(start >= end); /* end is exclusive */ |
232 | ||
499f8f84 | 233 | if (!pat_enabled) { |
e7f260a2 | 234 | /* This is identical to page table setting without PAT */ |
ac97991e AH |
235 | if (new_type) { |
236 | if (req_type == -1) | |
237 | *new_type = _PAGE_CACHE_WB; | |
238 | else | |
239 | *new_type = req_type & _PAGE_CACHE_MASK; | |
e7f260a2 | 240 | } |
2e5d9c85 | 241 | return 0; |
242 | } | |
243 | ||
244 | /* Low ISA region is always mapped WB in page table. No need to track */ | |
bcc643dc | 245 | if (is_ISA_range(start, end - 1)) { |
ac97991e AH |
246 | if (new_type) |
247 | *new_type = _PAGE_CACHE_WB; | |
2e5d9c85 | 248 | return 0; |
249 | } | |
250 | ||
e7f260a2 | 251 | if (req_type == -1) { |
252 | /* | |
c26421d0 VP |
253 | * Call mtrr_lookup to get the type hint. This is an |
254 | * optimization for /dev/mem mmap'ers into WB memory (BIOS | |
255 | * tools and ACPI tools). Use WB request for WB memory and use | |
256 | * UC_MINUS otherwise. | |
e7f260a2 | 257 | */ |
258 | u8 mtrr_type = mtrr_type_lookup(start, end); | |
e7f260a2 | 259 | |
69e26be9 | 260 | if (mtrr_type == MTRR_TYPE_WRBACK) |
e7f260a2 | 261 | actual_type = _PAGE_CACHE_WB; |
69e26be9 | 262 | else |
e7f260a2 | 263 | actual_type = _PAGE_CACHE_UC_MINUS; |
69e26be9 AH |
264 | } else |
265 | actual_type = pat_x_mtrr_type(start, end, | |
266 | req_type & _PAGE_CACHE_MASK); | |
2e5d9c85 | 267 | |
ac97991e AH |
268 | new = kmalloc(sizeof(struct memtype), GFP_KERNEL); |
269 | if (!new) | |
2e5d9c85 | 270 | return -ENOMEM; |
271 | ||
ac97991e AH |
272 | new->start = start; |
273 | new->end = end; | |
274 | new->type = actual_type; | |
2e5d9c85 | 275 | |
ac97991e AH |
276 | if (new_type) |
277 | *new_type = actual_type; | |
2e5d9c85 | 278 | |
279 | spin_lock(&memtype_lock); | |
280 | ||
281 | /* Search for existing mapping that overlaps the current range */ | |
f6887264 | 282 | where = NULL; |
ac97991e | 283 | list_for_each_entry(entry, &memtype_list, nd) { |
33af9039 | 284 | if (end <= entry->start) { |
f6887264 | 285 | where = entry->nd.prev; |
2e5d9c85 | 286 | break; |
33af9039 | 287 | } else if (start <= entry->start) { /* end > entry->start */ |
64fe44c3 | 288 | err = chk_conflict(new, entry, new_type); |
33af9039 AH |
289 | if (!err) { |
290 | dprintk("Overlap at 0x%Lx-0x%Lx\n", | |
291 | entry->start, entry->end); | |
292 | where = entry->nd.prev; | |
2e5d9c85 | 293 | } |
2e5d9c85 | 294 | break; |
33af9039 | 295 | } else if (start < entry->end) { /* start > entry->start */ |
64fe44c3 | 296 | err = chk_conflict(new, entry, new_type); |
33af9039 AH |
297 | if (!err) { |
298 | dprintk("Overlap at 0x%Lx-0x%Lx\n", | |
299 | entry->start, entry->end); | |
300 | where = &entry->nd; | |
2e5d9c85 | 301 | } |
2e5d9c85 | 302 | break; |
303 | } | |
304 | } | |
305 | ||
306 | if (err) { | |
3e9c83b3 AH |
307 | printk(KERN_INFO "reserve_memtype failed 0x%Lx-0x%Lx, " |
308 | "track %s, req %s\n", | |
309 | start, end, cattr_name(new->type), cattr_name(req_type)); | |
ac97991e | 310 | kfree(new); |
2e5d9c85 | 311 | spin_unlock(&memtype_lock); |
312 | return err; | |
313 | } | |
314 | ||
f6887264 AH |
315 | if (where) |
316 | list_add(&new->nd, where); | |
317 | else | |
ac97991e | 318 | list_add_tail(&new->nd, &memtype_list); |
6997ab49 | 319 | |
2e5d9c85 | 320 | spin_unlock(&memtype_lock); |
3e9c83b3 AH |
321 | |
322 | dprintk("reserve_memtype added 0x%Lx-0x%Lx, track %s, req %s, ret %s\n", | |
323 | start, end, cattr_name(new->type), cattr_name(req_type), | |
324 | new_type ? cattr_name(*new_type) : "-"); | |
325 | ||
2e5d9c85 | 326 | return err; |
327 | } | |
328 | ||
329 | int free_memtype(u64 start, u64 end) | |
330 | { | |
ac97991e | 331 | struct memtype *entry; |
2e5d9c85 | 332 | int err = -EINVAL; |
333 | ||
69e26be9 | 334 | if (!pat_enabled) |
2e5d9c85 | 335 | return 0; |
2e5d9c85 | 336 | |
337 | /* Low ISA region is always mapped WB. No need to track */ | |
bcc643dc | 338 | if (is_ISA_range(start, end - 1)) |
2e5d9c85 | 339 | return 0; |
2e5d9c85 | 340 | |
341 | spin_lock(&memtype_lock); | |
ac97991e AH |
342 | list_for_each_entry(entry, &memtype_list, nd) { |
343 | if (entry->start == start && entry->end == end) { | |
344 | list_del(&entry->nd); | |
345 | kfree(entry); | |
2e5d9c85 | 346 | err = 0; |
347 | break; | |
348 | } | |
349 | } | |
350 | spin_unlock(&memtype_lock); | |
351 | ||
352 | if (err) { | |
28eb559b | 353 | printk(KERN_INFO "%s:%d freeing invalid memtype %Lx-%Lx\n", |
2e5d9c85 | 354 | current->comm, current->pid, start, end); |
355 | } | |
6997ab49 | 356 | |
77b52b4c | 357 | dprintk("free_memtype request 0x%Lx-0x%Lx\n", start, end); |
2e5d9c85 | 358 | return err; |
359 | } | |
360 | ||
f0970c13 | 361 | |
e7f260a2 | 362 | /* |
363 | * /dev/mem mmap interface. The memtype used for mapping varies: | |
364 | * - Use UC for mappings with O_SYNC flag | |
365 | * - Without O_SYNC flag, if there is any conflict in reserve_memtype, | |
366 | * inherit the memtype from existing mapping. | |
367 | * - Else use UC_MINUS memtype (for backward compatibility with existing | |
368 | * X drivers. | |
369 | */ | |
f0970c13 | 370 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |
371 | unsigned long size, pgprot_t vma_prot) | |
372 | { | |
373 | return vma_prot; | |
374 | } | |
375 | ||
0124cecf VP |
376 | #ifdef CONFIG_NONPROMISC_DEVMEM |
377 | /* This check is done in drivers/char/mem.c in case of NONPROMISC_DEVMEM*/ | |
378 | static inline int range_is_allowed(unsigned long pfn, unsigned long size) | |
379 | { | |
380 | return 1; | |
381 | } | |
382 | #else | |
383 | static inline int range_is_allowed(unsigned long pfn, unsigned long size) | |
384 | { | |
385 | u64 from = ((u64)pfn) << PAGE_SHIFT; | |
386 | u64 to = from + size; | |
387 | u64 cursor = from; | |
388 | ||
389 | while (cursor < to) { | |
390 | if (!devmem_is_allowed(pfn)) { | |
391 | printk(KERN_INFO | |
392 | "Program %s tried to access /dev/mem between %Lx->%Lx.\n", | |
393 | current->comm, from, to); | |
394 | return 0; | |
395 | } | |
396 | cursor += PAGE_SIZE; | |
397 | pfn++; | |
398 | } | |
399 | return 1; | |
400 | } | |
401 | #endif /* CONFIG_NONPROMISC_DEVMEM */ | |
402 | ||
f0970c13 | 403 | int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, |
404 | unsigned long size, pgprot_t *vma_prot) | |
405 | { | |
e7f260a2 | 406 | u64 offset = ((u64) pfn) << PAGE_SHIFT; |
407 | unsigned long flags = _PAGE_CACHE_UC_MINUS; | |
e7f260a2 | 408 | int retval; |
f0970c13 | 409 | |
0124cecf VP |
410 | if (!range_is_allowed(pfn, size)) |
411 | return 0; | |
412 | ||
f0970c13 | 413 | if (file->f_flags & O_SYNC) { |
e7f260a2 | 414 | flags = _PAGE_CACHE_UC; |
f0970c13 | 415 | } |
416 | ||
417 | #ifdef CONFIG_X86_32 | |
418 | /* | |
419 | * On the PPro and successors, the MTRRs are used to set | |
420 | * memory types for physical addresses outside main memory, | |
421 | * so blindly setting UC or PWT on those pages is wrong. | |
422 | * For Pentiums and earlier, the surround logic should disable | |
423 | * caching for the high addresses through the KEN pin, but | |
424 | * we maintain the tradition of paranoia in this code. | |
425 | */ | |
499f8f84 | 426 | if (!pat_enabled && |
cd7a4e93 AH |
427 | !(boot_cpu_has(X86_FEATURE_MTRR) || |
428 | boot_cpu_has(X86_FEATURE_K6_MTRR) || | |
429 | boot_cpu_has(X86_FEATURE_CYRIX_ARR) || | |
430 | boot_cpu_has(X86_FEATURE_CENTAUR_MCR)) && | |
431 | (pfn << PAGE_SHIFT) >= __pa(high_memory)) { | |
e7f260a2 | 432 | flags = _PAGE_CACHE_UC; |
f0970c13 | 433 | } |
434 | #endif | |
435 | ||
e7f260a2 | 436 | /* |
437 | * With O_SYNC, we can only take UC mapping. Fail if we cannot. | |
438 | * Without O_SYNC, we want to get | |
439 | * - WB for WB-able memory and no other conflicting mappings | |
440 | * - UC_MINUS for non-WB-able memory with no other conflicting mappings | |
441 | * - Inherit from confliting mappings otherwise | |
442 | */ | |
443 | if (flags != _PAGE_CACHE_UC_MINUS) { | |
444 | retval = reserve_memtype(offset, offset + size, flags, NULL); | |
445 | } else { | |
f022bfd5 | 446 | retval = reserve_memtype(offset, offset + size, -1, &flags); |
e7f260a2 | 447 | } |
448 | ||
449 | if (retval < 0) | |
450 | return 0; | |
451 | ||
965194c1 YL |
452 | if (((pfn < max_low_pfn_mapped) || |
453 | (pfn >= (1UL<<(32 - PAGE_SHIFT)) && pfn < max_pfn_mapped)) && | |
cd7a4e93 | 454 | ioremap_change_attr((unsigned long)__va(offset), size, flags) < 0) { |
e7f260a2 | 455 | free_memtype(offset, offset + size); |
28eb559b | 456 | printk(KERN_INFO |
e7f260a2 | 457 | "%s:%d /dev/mem ioremap_change_attr failed %s for %Lx-%Lx\n", |
458 | current->comm, current->pid, | |
459 | cattr_name(flags), | |
afc85343 | 460 | offset, (unsigned long long)(offset + size)); |
e7f260a2 | 461 | return 0; |
462 | } | |
463 | ||
464 | *vma_prot = __pgprot((pgprot_val(*vma_prot) & ~_PAGE_CACHE_MASK) | | |
465 | flags); | |
f0970c13 | 466 | return 1; |
467 | } | |
e7f260a2 | 468 | |
469 | void map_devmem(unsigned long pfn, unsigned long size, pgprot_t vma_prot) | |
470 | { | |
471 | u64 addr = (u64)pfn << PAGE_SHIFT; | |
472 | unsigned long flags; | |
473 | unsigned long want_flags = (pgprot_val(vma_prot) & _PAGE_CACHE_MASK); | |
474 | ||
475 | reserve_memtype(addr, addr + size, want_flags, &flags); | |
476 | if (flags != want_flags) { | |
28eb559b | 477 | printk(KERN_INFO |
e7f260a2 | 478 | "%s:%d /dev/mem expected mapping type %s for %Lx-%Lx, got %s\n", |
479 | current->comm, current->pid, | |
480 | cattr_name(want_flags), | |
afc85343 | 481 | addr, (unsigned long long)(addr + size), |
e7f260a2 | 482 | cattr_name(flags)); |
483 | } | |
484 | } | |
485 | ||
486 | void unmap_devmem(unsigned long pfn, unsigned long size, pgprot_t vma_prot) | |
487 | { | |
488 | u64 addr = (u64)pfn << PAGE_SHIFT; | |
489 | ||
490 | free_memtype(addr, addr + size); | |
491 | } |