Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c | 10 | #include <linux/mm.h> |
76ebd054 | 11 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
12 | #include <linux/seq_file.h> |
13 | #include <linux/debugfs.h> | |
e59a1bb2 | 14 | #include <linux/pfn.h> |
9f4c815c | 15 | |
950f9d95 | 16 | #include <asm/e820.h> |
1da177e4 LT |
17 | #include <asm/processor.h> |
18 | #include <asm/tlbflush.h> | |
f8af095d | 19 | #include <asm/sections.h> |
93dbda7c | 20 | #include <asm/setup.h> |
9f4c815c IM |
21 | #include <asm/uaccess.h> |
22 | #include <asm/pgalloc.h> | |
c31c7d48 | 23 | #include <asm/proto.h> |
1219333d | 24 | #include <asm/pat.h> |
1da177e4 | 25 | |
9df84993 IM |
26 | /* |
27 | * The current flushing context - we pass it instead of 5 arguments: | |
28 | */ | |
72e458df | 29 | struct cpa_data { |
d75586ad | 30 | unsigned long *vaddr; |
72e458df TG |
31 | pgprot_t mask_set; |
32 | pgprot_t mask_clr; | |
65e074df | 33 | int numpages; |
d75586ad | 34 | int flags; |
c31c7d48 | 35 | unsigned long pfn; |
c9caa02c | 36 | unsigned force_split : 1; |
d75586ad | 37 | int curpage; |
9ae28475 | 38 | struct page **pages; |
72e458df TG |
39 | }; |
40 | ||
ad5ca55f SS |
41 | /* |
42 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
43 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
44 | * entries change the page attribute in parallel to some other cpu | |
45 | * splitting a large page entry along with changing the attribute. | |
46 | */ | |
47 | static DEFINE_SPINLOCK(cpa_lock); | |
48 | ||
d75586ad SL |
49 | #define CPA_FLUSHTLB 1 |
50 | #define CPA_ARRAY 2 | |
9ae28475 | 51 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 52 | |
65280e61 | 53 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
54 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
55 | ||
65280e61 | 56 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 57 | { |
ce0c0e50 | 58 | unsigned long flags; |
65280e61 | 59 | |
ce0c0e50 AK |
60 | /* Protect against CPA */ |
61 | spin_lock_irqsave(&pgd_lock, flags); | |
62 | direct_pages_count[level] += pages; | |
63 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
64 | } |
65 | ||
66 | static void split_page_count(int level) | |
67 | { | |
68 | direct_pages_count[level]--; | |
69 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
70 | } | |
71 | ||
e1759c21 | 72 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 73 | { |
b9c3bfc2 | 74 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
75 | direct_pages_count[PG_LEVEL_4K] << 2); |
76 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 77 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
78 | direct_pages_count[PG_LEVEL_2M] << 11); |
79 | #else | |
b9c3bfc2 | 80 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
81 | direct_pages_count[PG_LEVEL_2M] << 12); |
82 | #endif | |
65280e61 | 83 | #ifdef CONFIG_X86_64 |
a06de630 | 84 | if (direct_gbpages) |
b9c3bfc2 | 85 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 86 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
87 | #endif |
88 | } | |
65280e61 TG |
89 | #else |
90 | static inline void split_page_count(int level) { } | |
91 | #endif | |
ce0c0e50 | 92 | |
c31c7d48 TG |
93 | #ifdef CONFIG_X86_64 |
94 | ||
95 | static inline unsigned long highmap_start_pfn(void) | |
96 | { | |
97 | return __pa(_text) >> PAGE_SHIFT; | |
98 | } | |
99 | ||
100 | static inline unsigned long highmap_end_pfn(void) | |
101 | { | |
93dbda7c | 102 | return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
103 | } |
104 | ||
105 | #endif | |
106 | ||
92cb54a3 IM |
107 | #ifdef CONFIG_DEBUG_PAGEALLOC |
108 | # define debug_pagealloc 1 | |
109 | #else | |
110 | # define debug_pagealloc 0 | |
111 | #endif | |
112 | ||
ed724be6 AV |
113 | static inline int |
114 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 115 | { |
ed724be6 AV |
116 | return addr >= start && addr < end; |
117 | } | |
118 | ||
d7c8f21a TG |
119 | /* |
120 | * Flushing functions | |
121 | */ | |
cd8ddf1a | 122 | |
cd8ddf1a TG |
123 | /** |
124 | * clflush_cache_range - flush a cache range with clflush | |
125 | * @addr: virtual start address | |
126 | * @size: number of bytes to flush | |
127 | * | |
128 | * clflush is an unordered instruction which needs fencing with mfence | |
129 | * to avoid ordering issues. | |
130 | */ | |
4c61afcd | 131 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 132 | { |
4c61afcd | 133 | void *vend = vaddr + size - 1; |
d7c8f21a | 134 | |
cd8ddf1a | 135 | mb(); |
4c61afcd IM |
136 | |
137 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
138 | clflush(vaddr); | |
139 | /* | |
140 | * Flush any possible final partial cacheline: | |
141 | */ | |
142 | clflush(vend); | |
143 | ||
cd8ddf1a | 144 | mb(); |
d7c8f21a TG |
145 | } |
146 | ||
af1e6844 | 147 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 148 | { |
6bb8383b AK |
149 | unsigned long cache = (unsigned long)arg; |
150 | ||
d7c8f21a TG |
151 | /* |
152 | * Flush all to work around Errata in early athlons regarding | |
153 | * large page flushing. | |
154 | */ | |
155 | __flush_tlb_all(); | |
156 | ||
0b827537 | 157 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
158 | wbinvd(); |
159 | } | |
160 | ||
6bb8383b | 161 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
162 | { |
163 | BUG_ON(irqs_disabled()); | |
164 | ||
15c8b6c1 | 165 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
166 | } |
167 | ||
57a6a46a TG |
168 | static void __cpa_flush_range(void *arg) |
169 | { | |
57a6a46a TG |
170 | /* |
171 | * We could optimize that further and do individual per page | |
172 | * tlb invalidates for a low number of pages. Caveat: we must | |
173 | * flush the high aliases on 64bit as well. | |
174 | */ | |
175 | __flush_tlb_all(); | |
57a6a46a TG |
176 | } |
177 | ||
6bb8383b | 178 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 179 | { |
4c61afcd IM |
180 | unsigned int i, level; |
181 | unsigned long addr; | |
182 | ||
57a6a46a | 183 | BUG_ON(irqs_disabled()); |
4c61afcd | 184 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 185 | |
15c8b6c1 | 186 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 187 | |
6bb8383b AK |
188 | if (!cache) |
189 | return; | |
190 | ||
3b233e52 TG |
191 | /* |
192 | * We only need to flush on one CPU, | |
193 | * clflush is a MESI-coherent instruction that | |
194 | * will cause all other CPUs to flush the same | |
195 | * cachelines: | |
196 | */ | |
4c61afcd IM |
197 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
198 | pte_t *pte = lookup_address(addr, &level); | |
199 | ||
200 | /* | |
201 | * Only flush present addresses: | |
202 | */ | |
7bfb72e8 | 203 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
204 | clflush_cache_range((void *) addr, PAGE_SIZE); |
205 | } | |
57a6a46a TG |
206 | } |
207 | ||
9ae28475 | 208 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
209 | int in_flags, struct page **pages) | |
d75586ad SL |
210 | { |
211 | unsigned int i, level; | |
2171787b | 212 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
213 | |
214 | BUG_ON(irqs_disabled()); | |
215 | ||
2171787b | 216 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 217 | |
2171787b | 218 | if (!cache || do_wbinvd) |
d75586ad SL |
219 | return; |
220 | ||
d75586ad SL |
221 | /* |
222 | * We only need to flush on one CPU, | |
223 | * clflush is a MESI-coherent instruction that | |
224 | * will cause all other CPUs to flush the same | |
225 | * cachelines: | |
226 | */ | |
9ae28475 | 227 | for (i = 0; i < numpages; i++) { |
228 | unsigned long addr; | |
229 | pte_t *pte; | |
230 | ||
231 | if (in_flags & CPA_PAGES_ARRAY) | |
232 | addr = (unsigned long)page_address(pages[i]); | |
233 | else | |
234 | addr = start[i]; | |
235 | ||
236 | pte = lookup_address(addr, &level); | |
d75586ad SL |
237 | |
238 | /* | |
239 | * Only flush present addresses: | |
240 | */ | |
241 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 242 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
243 | } |
244 | } | |
245 | ||
ed724be6 AV |
246 | /* |
247 | * Certain areas of memory on x86 require very specific protection flags, | |
248 | * for example the BIOS area or kernel text. Callers don't always get this | |
249 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
250 | * checks and fixes these known static required protection bits. | |
251 | */ | |
c31c7d48 TG |
252 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
253 | unsigned long pfn) | |
ed724be6 AV |
254 | { |
255 | pgprot_t forbidden = __pgprot(0); | |
256 | ||
687c4825 | 257 | /* |
ed724be6 AV |
258 | * The BIOS area between 640k and 1Mb needs to be executable for |
259 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 260 | */ |
c31c7d48 | 261 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
262 | pgprot_val(forbidden) |= _PAGE_NX; |
263 | ||
264 | /* | |
265 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
266 | * Does not cover __inittext since that is gone later on. On |
267 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
268 | */ |
269 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
270 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 271 | |
cc0f21bb | 272 | /* |
c31c7d48 TG |
273 | * The .rodata section needs to be read-only. Using the pfn |
274 | * catches all aliases. | |
cc0f21bb | 275 | */ |
c31c7d48 TG |
276 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
277 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 278 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 AV |
279 | |
280 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
281 | |
282 | return prot; | |
283 | } | |
284 | ||
9a14aefc TG |
285 | /* |
286 | * Lookup the page table entry for a virtual address. Return a pointer | |
287 | * to the entry and the level of the mapping. | |
288 | * | |
289 | * Note: We return pud and pmd either when the entry is marked large | |
290 | * or when the present bit is not set. Otherwise we would return a | |
291 | * pointer to a nonexisting mapping. | |
292 | */ | |
da7bfc50 | 293 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 294 | { |
1da177e4 LT |
295 | pgd_t *pgd = pgd_offset_k(address); |
296 | pud_t *pud; | |
297 | pmd_t *pmd; | |
9f4c815c | 298 | |
30551bb3 TG |
299 | *level = PG_LEVEL_NONE; |
300 | ||
1da177e4 LT |
301 | if (pgd_none(*pgd)) |
302 | return NULL; | |
9df84993 | 303 | |
1da177e4 LT |
304 | pud = pud_offset(pgd, address); |
305 | if (pud_none(*pud)) | |
306 | return NULL; | |
c2f71ee2 AK |
307 | |
308 | *level = PG_LEVEL_1G; | |
309 | if (pud_large(*pud) || !pud_present(*pud)) | |
310 | return (pte_t *)pud; | |
311 | ||
1da177e4 LT |
312 | pmd = pmd_offset(pud, address); |
313 | if (pmd_none(*pmd)) | |
314 | return NULL; | |
30551bb3 TG |
315 | |
316 | *level = PG_LEVEL_2M; | |
9a14aefc | 317 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 318 | return (pte_t *)pmd; |
1da177e4 | 319 | |
30551bb3 | 320 | *level = PG_LEVEL_4K; |
9df84993 | 321 | |
9f4c815c IM |
322 | return pte_offset_kernel(pmd, address); |
323 | } | |
75bb8835 | 324 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 325 | |
9df84993 IM |
326 | /* |
327 | * Set the new pmd in all the pgds we know about: | |
328 | */ | |
9a3dc780 | 329 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 330 | { |
9f4c815c IM |
331 | /* change init_mm */ |
332 | set_pte_atomic(kpte, pte); | |
44af6c41 | 333 | #ifdef CONFIG_X86_32 |
e4b71dcf | 334 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
335 | struct page *page; |
336 | ||
e3ed910d | 337 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
338 | pgd_t *pgd; |
339 | pud_t *pud; | |
340 | pmd_t *pmd; | |
341 | ||
342 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
343 | pud = pud_offset(pgd, address); | |
344 | pmd = pmd_offset(pud, address); | |
345 | set_pte_atomic((pte_t *)pmd, pte); | |
346 | } | |
1da177e4 | 347 | } |
44af6c41 | 348 | #endif |
1da177e4 LT |
349 | } |
350 | ||
9df84993 IM |
351 | static int |
352 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
353 | struct cpa_data *cpa) | |
65e074df | 354 | { |
c31c7d48 | 355 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
356 | pte_t new_pte, old_pte, *tmp; |
357 | pgprot_t old_prot, new_prot; | |
fac84939 | 358 | int i, do_split = 1; |
da7bfc50 | 359 | unsigned int level; |
65e074df | 360 | |
c9caa02c AK |
361 | if (cpa->force_split) |
362 | return 1; | |
363 | ||
65e074df TG |
364 | spin_lock_irqsave(&pgd_lock, flags); |
365 | /* | |
366 | * Check for races, another CPU might have split this page | |
367 | * up already: | |
368 | */ | |
369 | tmp = lookup_address(address, &level); | |
370 | if (tmp != kpte) | |
371 | goto out_unlock; | |
372 | ||
373 | switch (level) { | |
374 | case PG_LEVEL_2M: | |
31422c51 AK |
375 | psize = PMD_PAGE_SIZE; |
376 | pmask = PMD_PAGE_MASK; | |
65e074df | 377 | break; |
f07333fd | 378 | #ifdef CONFIG_X86_64 |
65e074df | 379 | case PG_LEVEL_1G: |
5d3c8b21 AK |
380 | psize = PUD_PAGE_SIZE; |
381 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
382 | break; |
383 | #endif | |
65e074df | 384 | default: |
beaff633 | 385 | do_split = -EINVAL; |
65e074df TG |
386 | goto out_unlock; |
387 | } | |
388 | ||
389 | /* | |
390 | * Calculate the number of pages, which fit into this large | |
391 | * page starting at address: | |
392 | */ | |
393 | nextpage_addr = (address + psize) & pmask; | |
394 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
395 | if (numpages < cpa->numpages) |
396 | cpa->numpages = numpages; | |
65e074df TG |
397 | |
398 | /* | |
399 | * We are safe now. Check whether the new pgprot is the same: | |
400 | */ | |
401 | old_pte = *kpte; | |
402 | old_prot = new_prot = pte_pgprot(old_pte); | |
403 | ||
404 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
405 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
406 | |
407 | /* | |
408 | * old_pte points to the large page base address. So we need | |
409 | * to add the offset of the virtual address: | |
410 | */ | |
411 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
412 | cpa->pfn = pfn; | |
413 | ||
414 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 415 | |
fac84939 TG |
416 | /* |
417 | * We need to check the full range, whether | |
418 | * static_protection() requires a different pgprot for one of | |
419 | * the pages in the range we try to preserve: | |
420 | */ | |
421 | addr = address + PAGE_SIZE; | |
c31c7d48 | 422 | pfn++; |
9b5cf48b | 423 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 424 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
425 | |
426 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
427 | goto out_unlock; | |
428 | } | |
429 | ||
65e074df TG |
430 | /* |
431 | * If there are no changes, return. maxpages has been updated | |
432 | * above: | |
433 | */ | |
434 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 435 | do_split = 0; |
65e074df TG |
436 | goto out_unlock; |
437 | } | |
438 | ||
439 | /* | |
440 | * We need to change the attributes. Check, whether we can | |
441 | * change the large page in one go. We request a split, when | |
442 | * the address is not aligned and the number of pages is | |
443 | * smaller than the number of pages in the large page. Note | |
444 | * that we limited the number of possible pages already to | |
445 | * the number of pages in the large page. | |
446 | */ | |
9b5cf48b | 447 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
448 | /* |
449 | * The address is aligned and the number of pages | |
450 | * covers the full page. | |
451 | */ | |
452 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
453 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 454 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 455 | do_split = 0; |
65e074df TG |
456 | } |
457 | ||
458 | out_unlock: | |
459 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 460 | |
beaff633 | 461 | return do_split; |
65e074df TG |
462 | } |
463 | ||
7afe15b9 | 464 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 465 | { |
7b610eec | 466 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 467 | unsigned int i, level; |
bb5c2dbd | 468 | pte_t *pbase, *tmp; |
9df84993 | 469 | pgprot_t ref_prot; |
ad5ca55f SS |
470 | struct page *base; |
471 | ||
472 | if (!debug_pagealloc) | |
473 | spin_unlock(&cpa_lock); | |
9e730237 | 474 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); |
ad5ca55f SS |
475 | if (!debug_pagealloc) |
476 | spin_lock(&cpa_lock); | |
8311eb84 SS |
477 | if (!base) |
478 | return -ENOMEM; | |
bb5c2dbd | 479 | |
eb5b5f02 | 480 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
481 | /* |
482 | * Check for races, another CPU might have split this page | |
483 | * up for us already: | |
484 | */ | |
485 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 486 | if (tmp != kpte) |
bb5c2dbd IM |
487 | goto out_unlock; |
488 | ||
bb5c2dbd | 489 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 490 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 491 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
492 | /* |
493 | * If we ever want to utilize the PAT bit, we need to | |
494 | * update this function to make sure it's converted from | |
495 | * bit 12 to bit 7 when we cross from the 2MB level to | |
496 | * the 4K level: | |
497 | */ | |
498 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 499 | |
f07333fd AK |
500 | #ifdef CONFIG_X86_64 |
501 | if (level == PG_LEVEL_1G) { | |
502 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
503 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
504 | } |
505 | #endif | |
506 | ||
63c1dcf4 TG |
507 | /* |
508 | * Get the target pfn from the original entry: | |
509 | */ | |
510 | pfn = pte_pfn(*kpte); | |
f07333fd | 511 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 512 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 513 | |
ce0c0e50 | 514 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
515 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
516 | split_page_count(level); | |
517 | ||
518 | #ifdef CONFIG_X86_64 | |
519 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
520 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
521 | split_page_count(level); | |
f361a450 | 522 | #endif |
ce0c0e50 | 523 | |
bb5c2dbd | 524 | /* |
07a66d7c | 525 | * Install the new, split up pagetable. |
4c881ca1 | 526 | * |
07a66d7c IM |
527 | * We use the standard kernel pagetable protections for the new |
528 | * pagetable protections, the actual ptes set above control the | |
529 | * primary protection behavior: | |
bb5c2dbd | 530 | */ |
07a66d7c | 531 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
532 | |
533 | /* | |
534 | * Intel Atom errata AAH41 workaround. | |
535 | * | |
536 | * The real fix should be in hw or in a microcode update, but | |
537 | * we also probabilistically try to reduce the window of having | |
538 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
539 | * going on. | |
540 | */ | |
541 | __flush_tlb_all(); | |
542 | ||
bb5c2dbd IM |
543 | base = NULL; |
544 | ||
545 | out_unlock: | |
eb5b5f02 TG |
546 | /* |
547 | * If we dropped out via the lookup_address check under | |
548 | * pgd_lock then stick the page back into the pool: | |
549 | */ | |
8311eb84 SS |
550 | if (base) |
551 | __free_page(base); | |
9a3dc780 | 552 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 553 | |
bb5c2dbd IM |
554 | return 0; |
555 | } | |
556 | ||
a1e46212 SS |
557 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
558 | int primary) | |
559 | { | |
560 | /* | |
561 | * Ignore all non primary paths. | |
562 | */ | |
563 | if (!primary) | |
564 | return 0; | |
565 | ||
566 | /* | |
567 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
568 | * to have holes. | |
569 | * Also set numpages to '1' indicating that we processed cpa req for | |
570 | * one virtual address page and its pfn. TBD: numpages can be set based | |
571 | * on the initial value and the level returned by lookup_address(). | |
572 | */ | |
573 | if (within(vaddr, PAGE_OFFSET, | |
574 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
575 | cpa->numpages = 1; | |
576 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
577 | return 0; | |
578 | } else { | |
579 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
580 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
581 | *cpa->vaddr); | |
582 | ||
583 | return -EFAULT; | |
584 | } | |
585 | } | |
586 | ||
c31c7d48 | 587 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 588 | { |
d75586ad | 589 | unsigned long address; |
da7bfc50 HH |
590 | int do_split, err; |
591 | unsigned int level; | |
c31c7d48 | 592 | pte_t *kpte, old_pte; |
1da177e4 | 593 | |
8523acfe TH |
594 | if (cpa->flags & CPA_PAGES_ARRAY) { |
595 | struct page *page = cpa->pages[cpa->curpage]; | |
596 | if (unlikely(PageHighMem(page))) | |
597 | return 0; | |
598 | address = (unsigned long)page_address(page); | |
599 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
600 | address = cpa->vaddr[cpa->curpage]; |
601 | else | |
602 | address = *cpa->vaddr; | |
97f99fed | 603 | repeat: |
f0646e43 | 604 | kpte = lookup_address(address, &level); |
1da177e4 | 605 | if (!kpte) |
a1e46212 | 606 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
607 | |
608 | old_pte = *kpte; | |
a1e46212 SS |
609 | if (!pte_val(old_pte)) |
610 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 611 | |
30551bb3 | 612 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 613 | pte_t new_pte; |
626c2c9d | 614 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 615 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 616 | |
72e458df TG |
617 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
618 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 619 | |
c31c7d48 | 620 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 621 | |
626c2c9d AV |
622 | /* |
623 | * We need to keep the pfn from the existing PTE, | |
624 | * after all we're only going to change it's attributes | |
625 | * not the memory it points to | |
626 | */ | |
c31c7d48 TG |
627 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
628 | cpa->pfn = pfn; | |
f4ae5da0 TG |
629 | /* |
630 | * Do we really change anything ? | |
631 | */ | |
632 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
633 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 634 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 635 | } |
9b5cf48b | 636 | cpa->numpages = 1; |
65e074df | 637 | return 0; |
1da177e4 | 638 | } |
65e074df TG |
639 | |
640 | /* | |
641 | * Check, whether we can keep the large page intact | |
642 | * and just change the pte: | |
643 | */ | |
beaff633 | 644 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
645 | /* |
646 | * When the range fits into the existing large page, | |
9b5cf48b | 647 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
648 | * try_large_page: |
649 | */ | |
87f7f8fe IM |
650 | if (do_split <= 0) |
651 | return do_split; | |
65e074df TG |
652 | |
653 | /* | |
654 | * We have to split the large page: | |
655 | */ | |
87f7f8fe IM |
656 | err = split_large_page(kpte, address); |
657 | if (!err) { | |
ad5ca55f SS |
658 | /* |
659 | * Do a global flush tlb after splitting the large page | |
660 | * and before we do the actual change page attribute in the PTE. | |
661 | * | |
662 | * With out this, we violate the TLB application note, that says | |
663 | * "The TLBs may contain both ordinary and large-page | |
664 | * translations for a 4-KByte range of linear addresses. This | |
665 | * may occur if software modifies the paging structures so that | |
666 | * the page size used for the address range changes. If the two | |
667 | * translations differ with respect to page frame or attributes | |
668 | * (e.g., permissions), processor behavior is undefined and may | |
669 | * be implementation-specific." | |
670 | * | |
671 | * We do this global tlb flush inside the cpa_lock, so that we | |
672 | * don't allow any other cpu, with stale tlb entries change the | |
673 | * page attribute in parallel, that also falls into the | |
674 | * just split large page entry. | |
675 | */ | |
676 | flush_tlb_all(); | |
87f7f8fe IM |
677 | goto repeat; |
678 | } | |
beaff633 | 679 | |
87f7f8fe | 680 | return err; |
9f4c815c | 681 | } |
1da177e4 | 682 | |
c31c7d48 TG |
683 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
684 | ||
685 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 686 | { |
c31c7d48 | 687 | struct cpa_data alias_cpa; |
992f4c1c | 688 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e59a1bb2 | 689 | unsigned long vaddr, remapped; |
992f4c1c | 690 | int ret; |
44af6c41 | 691 | |
965194c1 | 692 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 693 | return 0; |
626c2c9d | 694 | |
f361a450 | 695 | #ifdef CONFIG_X86_64 |
965194c1 | 696 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
697 | return 0; |
698 | #endif | |
f34b439f TG |
699 | /* |
700 | * No need to redo, when the primary call touched the direct | |
701 | * mapping already: | |
702 | */ | |
8523acfe TH |
703 | if (cpa->flags & CPA_PAGES_ARRAY) { |
704 | struct page *page = cpa->pages[cpa->curpage]; | |
705 | if (unlikely(PageHighMem(page))) | |
706 | return 0; | |
707 | vaddr = (unsigned long)page_address(page); | |
708 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
709 | vaddr = cpa->vaddr[cpa->curpage]; |
710 | else | |
711 | vaddr = *cpa->vaddr; | |
712 | ||
713 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 714 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 715 | |
f34b439f | 716 | alias_cpa = *cpa; |
992f4c1c | 717 | alias_cpa.vaddr = &laddr; |
9ae28475 | 718 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 719 | |
f34b439f | 720 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
721 | if (ret) |
722 | return ret; | |
f34b439f | 723 | } |
44af6c41 | 724 | |
44af6c41 | 725 | #ifdef CONFIG_X86_64 |
488fd995 | 726 | /* |
992f4c1c TH |
727 | * If the primary call didn't touch the high mapping already |
728 | * and the physical address is inside the kernel map, we need | |
0879750f | 729 | * to touch the high mapped kernel as well: |
488fd995 | 730 | */ |
992f4c1c TH |
731 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
732 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
733 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
734 | __START_KERNEL_map - phys_base; | |
735 | alias_cpa = *cpa; | |
736 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
737 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 738 | |
992f4c1c TH |
739 | /* |
740 | * The high mapping range is imprecise, so ignore the | |
741 | * return value. | |
742 | */ | |
743 | __change_page_attr_set_clr(&alias_cpa, 0); | |
744 | } | |
488fd995 | 745 | #endif |
992f4c1c | 746 | |
e59a1bb2 TH |
747 | /* |
748 | * If the PMD page was partially used for per-cpu remapping, | |
749 | * the recycled area needs to be split and modified. Because | |
750 | * the area is always proper subset of a PMD page | |
751 | * cpa->numpages is guaranteed to be 1 for these areas, so | |
752 | * there's no need to loop over and check for further remaps. | |
753 | */ | |
754 | remapped = (unsigned long)pcpu_lpage_remapped((void *)laddr); | |
755 | if (remapped) { | |
756 | WARN_ON(cpa->numpages > 1); | |
757 | alias_cpa = *cpa; | |
758 | alias_cpa.vaddr = &remapped; | |
759 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
760 | ret = __change_page_attr_set_clr(&alias_cpa, 0); | |
761 | if (ret) | |
762 | return ret; | |
763 | } | |
764 | ||
992f4c1c | 765 | return 0; |
1da177e4 LT |
766 | } |
767 | ||
c31c7d48 | 768 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 769 | { |
65e074df | 770 | int ret, numpages = cpa->numpages; |
ff31452b | 771 | |
65e074df TG |
772 | while (numpages) { |
773 | /* | |
774 | * Store the remaining nr of pages for the large page | |
775 | * preservation check. | |
776 | */ | |
9b5cf48b | 777 | cpa->numpages = numpages; |
d75586ad | 778 | /* for array changes, we can't use large page */ |
9ae28475 | 779 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 780 | cpa->numpages = 1; |
c31c7d48 | 781 | |
ad5ca55f SS |
782 | if (!debug_pagealloc) |
783 | spin_lock(&cpa_lock); | |
c31c7d48 | 784 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
785 | if (!debug_pagealloc) |
786 | spin_unlock(&cpa_lock); | |
ff31452b TG |
787 | if (ret) |
788 | return ret; | |
ff31452b | 789 | |
c31c7d48 TG |
790 | if (checkalias) { |
791 | ret = cpa_process_alias(cpa); | |
792 | if (ret) | |
793 | return ret; | |
794 | } | |
795 | ||
65e074df TG |
796 | /* |
797 | * Adjust the number of pages with the result of the | |
798 | * CPA operation. Either a large page has been | |
799 | * preserved or a single page update happened. | |
800 | */ | |
9b5cf48b RW |
801 | BUG_ON(cpa->numpages > numpages); |
802 | numpages -= cpa->numpages; | |
9ae28475 | 803 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
804 | cpa->curpage++; |
805 | else | |
806 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
807 | ||
65e074df | 808 | } |
ff31452b TG |
809 | return 0; |
810 | } | |
811 | ||
6bb8383b AK |
812 | static inline int cache_attr(pgprot_t attr) |
813 | { | |
814 | return pgprot_val(attr) & | |
815 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
816 | } | |
817 | ||
d75586ad | 818 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 819 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 820 | int force_split, int in_flag, |
821 | struct page **pages) | |
ff31452b | 822 | { |
72e458df | 823 | struct cpa_data cpa; |
cacf8906 | 824 | int ret, cache, checkalias; |
331e4065 TG |
825 | |
826 | /* | |
827 | * Check, if we are requested to change a not supported | |
828 | * feature: | |
829 | */ | |
830 | mask_set = canon_pgprot(mask_set); | |
831 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 832 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
833 | return 0; |
834 | ||
69b1415e | 835 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 836 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
837 | int i; |
838 | for (i = 0; i < numpages; i++) { | |
839 | if (addr[i] & ~PAGE_MASK) { | |
840 | addr[i] &= PAGE_MASK; | |
841 | WARN_ON_ONCE(1); | |
842 | } | |
843 | } | |
9ae28475 | 844 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
845 | /* | |
846 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
847 | * No need to cehck in that case | |
848 | */ | |
849 | if (*addr & ~PAGE_MASK) { | |
850 | *addr &= PAGE_MASK; | |
851 | /* | |
852 | * People should not be passing in unaligned addresses: | |
853 | */ | |
854 | WARN_ON_ONCE(1); | |
855 | } | |
69b1415e TG |
856 | } |
857 | ||
5843d9a4 NP |
858 | /* Must avoid aliasing mappings in the highmem code */ |
859 | kmap_flush_unused(); | |
860 | ||
db64fe02 NP |
861 | vm_unmap_aliases(); |
862 | ||
72e458df | 863 | cpa.vaddr = addr; |
9ae28475 | 864 | cpa.pages = pages; |
72e458df TG |
865 | cpa.numpages = numpages; |
866 | cpa.mask_set = mask_set; | |
867 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
868 | cpa.flags = 0; |
869 | cpa.curpage = 0; | |
c9caa02c | 870 | cpa.force_split = force_split; |
72e458df | 871 | |
9ae28475 | 872 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
873 | cpa.flags |= in_flag; | |
d75586ad | 874 | |
af96e443 TG |
875 | /* No alias checking for _NX bit modifications */ |
876 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
877 | ||
878 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 879 | |
f4ae5da0 TG |
880 | /* |
881 | * Check whether we really changed something: | |
882 | */ | |
d75586ad | 883 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 884 | goto out; |
cacf8906 | 885 | |
6bb8383b AK |
886 | /* |
887 | * No need to flush, when we did not set any of the caching | |
888 | * attributes: | |
889 | */ | |
890 | cache = cache_attr(mask_set); | |
891 | ||
57a6a46a TG |
892 | /* |
893 | * On success we use clflush, when the CPU supports it to | |
894 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 895 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
896 | * wbindv): |
897 | */ | |
d75586ad | 898 | if (!ret && cpu_has_clflush) { |
9ae28475 | 899 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
900 | cpa_flush_array(addr, numpages, cache, | |
901 | cpa.flags, pages); | |
902 | } else | |
d75586ad SL |
903 | cpa_flush_range(*addr, numpages, cache); |
904 | } else | |
6bb8383b | 905 | cpa_flush_all(cache); |
cacf8906 | 906 | |
76ebd054 | 907 | out: |
ff31452b TG |
908 | return ret; |
909 | } | |
910 | ||
d75586ad SL |
911 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
912 | pgprot_t mask, int array) | |
75cbade8 | 913 | { |
d75586ad | 914 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 915 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
916 | } |
917 | ||
d75586ad SL |
918 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
919 | pgprot_t mask, int array) | |
72932c7a | 920 | { |
d75586ad | 921 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 922 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
923 | } |
924 | ||
0f350755 | 925 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
926 | pgprot_t mask) | |
927 | { | |
928 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
929 | CPA_PAGES_ARRAY, pages); | |
930 | } | |
931 | ||
932 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
933 | pgprot_t mask) | |
934 | { | |
935 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
936 | CPA_PAGES_ARRAY, pages); | |
937 | } | |
938 | ||
1219333d | 939 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 940 | { |
de33c442 SS |
941 | /* |
942 | * for now UC MINUS. see comments in ioremap_nocache() | |
943 | */ | |
d75586ad SL |
944 | return change_page_attr_set(&addr, numpages, |
945 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 946 | } |
1219333d | 947 | |
948 | int set_memory_uc(unsigned long addr, int numpages) | |
949 | { | |
9fa3ab39 | 950 | int ret; |
951 | ||
de33c442 SS |
952 | /* |
953 | * for now UC MINUS. see comments in ioremap_nocache() | |
954 | */ | |
9fa3ab39 | 955 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
956 | _PAGE_CACHE_UC_MINUS, NULL); | |
957 | if (ret) | |
958 | goto out_err; | |
959 | ||
960 | ret = _set_memory_uc(addr, numpages); | |
961 | if (ret) | |
962 | goto out_free; | |
963 | ||
964 | return 0; | |
1219333d | 965 | |
9fa3ab39 | 966 | out_free: |
967 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
968 | out_err: | |
969 | return ret; | |
1219333d | 970 | } |
75cbade8 AV |
971 | EXPORT_SYMBOL(set_memory_uc); |
972 | ||
d75586ad SL |
973 | int set_memory_array_uc(unsigned long *addr, int addrinarray) |
974 | { | |
9fa3ab39 | 975 | int i, j; |
976 | int ret; | |
977 | ||
d75586ad SL |
978 | /* |
979 | * for now UC MINUS. see comments in ioremap_nocache() | |
980 | */ | |
981 | for (i = 0; i < addrinarray; i++) { | |
9fa3ab39 | 982 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
983 | _PAGE_CACHE_UC_MINUS, NULL); | |
984 | if (ret) | |
985 | goto out_free; | |
d75586ad SL |
986 | } |
987 | ||
9fa3ab39 | 988 | ret = change_page_attr_set(addr, addrinarray, |
d75586ad | 989 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); |
9fa3ab39 | 990 | if (ret) |
991 | goto out_free; | |
992 | ||
993 | return 0; | |
994 | ||
995 | out_free: | |
996 | for (j = 0; j < i; j++) | |
997 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
998 | ||
999 | return ret; | |
d75586ad SL |
1000 | } |
1001 | EXPORT_SYMBOL(set_memory_array_uc); | |
1002 | ||
ef354af4 | 1003 | int _set_memory_wc(unsigned long addr, int numpages) |
1004 | { | |
3869c4aa | 1005 | int ret; |
bdc6340f PV |
1006 | unsigned long addr_copy = addr; |
1007 | ||
3869c4aa | 1008 | ret = change_page_attr_set(&addr, numpages, |
1009 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
3869c4aa | 1010 | if (!ret) { |
bdc6340f PV |
1011 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
1012 | __pgprot(_PAGE_CACHE_WC), | |
1013 | __pgprot(_PAGE_CACHE_MASK), | |
1014 | 0, 0, NULL); | |
3869c4aa | 1015 | } |
1016 | return ret; | |
ef354af4 | 1017 | } |
1018 | ||
1019 | int set_memory_wc(unsigned long addr, int numpages) | |
1020 | { | |
9fa3ab39 | 1021 | int ret; |
1022 | ||
499f8f84 | 1023 | if (!pat_enabled) |
ef354af4 | 1024 | return set_memory_uc(addr, numpages); |
1025 | ||
9fa3ab39 | 1026 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1027 | _PAGE_CACHE_WC, NULL); | |
1028 | if (ret) | |
1029 | goto out_err; | |
ef354af4 | 1030 | |
9fa3ab39 | 1031 | ret = _set_memory_wc(addr, numpages); |
1032 | if (ret) | |
1033 | goto out_free; | |
1034 | ||
1035 | return 0; | |
1036 | ||
1037 | out_free: | |
1038 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1039 | out_err: | |
1040 | return ret; | |
ef354af4 | 1041 | } |
1042 | EXPORT_SYMBOL(set_memory_wc); | |
1043 | ||
1219333d | 1044 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1045 | { |
d75586ad SL |
1046 | return change_page_attr_clear(&addr, numpages, |
1047 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1048 | } |
1219333d | 1049 | |
1050 | int set_memory_wb(unsigned long addr, int numpages) | |
1051 | { | |
9fa3ab39 | 1052 | int ret; |
1053 | ||
1054 | ret = _set_memory_wb(addr, numpages); | |
1055 | if (ret) | |
1056 | return ret; | |
1057 | ||
c15238df | 1058 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1059 | return 0; |
1219333d | 1060 | } |
75cbade8 AV |
1061 | EXPORT_SYMBOL(set_memory_wb); |
1062 | ||
d75586ad SL |
1063 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1064 | { | |
1065 | int i; | |
a5593e0b | 1066 | int ret; |
1067 | ||
1068 | ret = change_page_attr_clear(addr, addrinarray, | |
1069 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1070 | if (ret) |
1071 | return ret; | |
d75586ad | 1072 | |
9fa3ab39 | 1073 | for (i = 0; i < addrinarray; i++) |
1074 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1075 | |
9fa3ab39 | 1076 | return 0; |
d75586ad SL |
1077 | } |
1078 | EXPORT_SYMBOL(set_memory_array_wb); | |
1079 | ||
75cbade8 AV |
1080 | int set_memory_x(unsigned long addr, int numpages) |
1081 | { | |
d75586ad | 1082 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1083 | } |
1084 | EXPORT_SYMBOL(set_memory_x); | |
1085 | ||
1086 | int set_memory_nx(unsigned long addr, int numpages) | |
1087 | { | |
d75586ad | 1088 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1089 | } |
1090 | EXPORT_SYMBOL(set_memory_nx); | |
1091 | ||
1092 | int set_memory_ro(unsigned long addr, int numpages) | |
1093 | { | |
d75586ad | 1094 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1095 | } |
a03352d2 | 1096 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1097 | |
1098 | int set_memory_rw(unsigned long addr, int numpages) | |
1099 | { | |
d75586ad | 1100 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1101 | } |
a03352d2 | 1102 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1103 | |
1104 | int set_memory_np(unsigned long addr, int numpages) | |
1105 | { | |
d75586ad | 1106 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1107 | } |
75cbade8 | 1108 | |
c9caa02c AK |
1109 | int set_memory_4k(unsigned long addr, int numpages) |
1110 | { | |
d75586ad | 1111 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1112 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1113 | } |
1114 | ||
75cbade8 AV |
1115 | int set_pages_uc(struct page *page, int numpages) |
1116 | { | |
1117 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1118 | |
d7c8f21a | 1119 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1120 | } |
1121 | EXPORT_SYMBOL(set_pages_uc); | |
1122 | ||
0f350755 | 1123 | int set_pages_array_uc(struct page **pages, int addrinarray) |
1124 | { | |
1125 | unsigned long start; | |
1126 | unsigned long end; | |
1127 | int i; | |
1128 | int free_idx; | |
1129 | ||
1130 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1131 | if (PageHighMem(pages[i])) |
1132 | continue; | |
1133 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1134 | end = start + PAGE_SIZE; |
1135 | if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL)) | |
1136 | goto err_out; | |
1137 | } | |
1138 | ||
1139 | if (cpa_set_pages_array(pages, addrinarray, | |
1140 | __pgprot(_PAGE_CACHE_UC_MINUS)) == 0) { | |
1141 | return 0; /* Success */ | |
1142 | } | |
1143 | err_out: | |
1144 | free_idx = i; | |
1145 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1146 | if (PageHighMem(pages[i])) |
1147 | continue; | |
1148 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1149 | end = start + PAGE_SIZE; |
1150 | free_memtype(start, end); | |
1151 | } | |
1152 | return -EINVAL; | |
1153 | } | |
1154 | EXPORT_SYMBOL(set_pages_array_uc); | |
1155 | ||
75cbade8 AV |
1156 | int set_pages_wb(struct page *page, int numpages) |
1157 | { | |
1158 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1159 | |
d7c8f21a | 1160 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1161 | } |
1162 | EXPORT_SYMBOL(set_pages_wb); | |
1163 | ||
0f350755 | 1164 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1165 | { | |
1166 | int retval; | |
1167 | unsigned long start; | |
1168 | unsigned long end; | |
1169 | int i; | |
1170 | ||
1171 | retval = cpa_clear_pages_array(pages, addrinarray, | |
1172 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1173 | if (retval) |
1174 | return retval; | |
0f350755 | 1175 | |
1176 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1177 | if (PageHighMem(pages[i])) |
1178 | continue; | |
1179 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1180 | end = start + PAGE_SIZE; |
1181 | free_memtype(start, end); | |
1182 | } | |
1183 | ||
9fa3ab39 | 1184 | return 0; |
0f350755 | 1185 | } |
1186 | EXPORT_SYMBOL(set_pages_array_wb); | |
1187 | ||
75cbade8 AV |
1188 | int set_pages_x(struct page *page, int numpages) |
1189 | { | |
1190 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1191 | |
d7c8f21a | 1192 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1193 | } |
1194 | EXPORT_SYMBOL(set_pages_x); | |
1195 | ||
1196 | int set_pages_nx(struct page *page, int numpages) | |
1197 | { | |
1198 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1199 | |
d7c8f21a | 1200 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1201 | } |
1202 | EXPORT_SYMBOL(set_pages_nx); | |
1203 | ||
1204 | int set_pages_ro(struct page *page, int numpages) | |
1205 | { | |
1206 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1207 | |
d7c8f21a | 1208 | return set_memory_ro(addr, numpages); |
75cbade8 | 1209 | } |
75cbade8 AV |
1210 | |
1211 | int set_pages_rw(struct page *page, int numpages) | |
1212 | { | |
1213 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1214 | |
d7c8f21a | 1215 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1216 | } |
1217 | ||
1da177e4 | 1218 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1219 | |
1220 | static int __set_pages_p(struct page *page, int numpages) | |
1221 | { | |
d75586ad SL |
1222 | unsigned long tempaddr = (unsigned long) page_address(page); |
1223 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1224 | .numpages = numpages, |
1225 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1226 | .mask_clr = __pgprot(0), |
1227 | .flags = 0}; | |
72932c7a | 1228 | |
55121b43 SS |
1229 | /* |
1230 | * No alias checking needed for setting present flag. otherwise, | |
1231 | * we may need to break large pages for 64-bit kernel text | |
1232 | * mappings (this adds to complexity if we want to do this from | |
1233 | * atomic context especially). Let's keep it simple! | |
1234 | */ | |
1235 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1236 | } |
1237 | ||
1238 | static int __set_pages_np(struct page *page, int numpages) | |
1239 | { | |
d75586ad SL |
1240 | unsigned long tempaddr = (unsigned long) page_address(page); |
1241 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1242 | .numpages = numpages, |
1243 | .mask_set = __pgprot(0), | |
d75586ad SL |
1244 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1245 | .flags = 0}; | |
72932c7a | 1246 | |
55121b43 SS |
1247 | /* |
1248 | * No alias checking needed for setting not present flag. otherwise, | |
1249 | * we may need to break large pages for 64-bit kernel text | |
1250 | * mappings (this adds to complexity if we want to do this from | |
1251 | * atomic context especially). Let's keep it simple! | |
1252 | */ | |
1253 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1254 | } |
1255 | ||
1da177e4 LT |
1256 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1257 | { | |
1258 | if (PageHighMem(page)) | |
1259 | return; | |
9f4c815c | 1260 | if (!enable) { |
f9b8404c IM |
1261 | debug_check_no_locks_freed(page_address(page), |
1262 | numpages * PAGE_SIZE); | |
9f4c815c | 1263 | } |
de5097c2 | 1264 | |
12d6f21e IM |
1265 | /* |
1266 | * If page allocator is not up yet then do not call c_p_a(): | |
1267 | */ | |
1268 | if (!debug_pagealloc_enabled) | |
1269 | return; | |
1270 | ||
9f4c815c | 1271 | /* |
f8d8406b | 1272 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1273 | * Large pages for identity mappings are not used at boot time |
1274 | * and hence no memory allocations during large page split. | |
1da177e4 | 1275 | */ |
f62d0f00 IM |
1276 | if (enable) |
1277 | __set_pages_p(page, numpages); | |
1278 | else | |
1279 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1280 | |
1281 | /* | |
e4b71dcf IM |
1282 | * We should perform an IPI and flush all tlbs, |
1283 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1284 | */ |
1285 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1286 | } |
1287 | ||
8a235efa RW |
1288 | #ifdef CONFIG_HIBERNATION |
1289 | ||
1290 | bool kernel_page_present(struct page *page) | |
1291 | { | |
1292 | unsigned int level; | |
1293 | pte_t *pte; | |
1294 | ||
1295 | if (PageHighMem(page)) | |
1296 | return false; | |
1297 | ||
1298 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1299 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1300 | } | |
1301 | ||
1302 | #endif /* CONFIG_HIBERNATION */ | |
1303 | ||
1304 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1305 | |
1306 | /* | |
1307 | * The testcases use internal knowledge of the implementation that shouldn't | |
1308 | * be exposed to the rest of the kernel. Include these directly here. | |
1309 | */ | |
1310 | #ifdef CONFIG_CPA_DEBUG | |
1311 | #include "pageattr-test.c" | |
1312 | #endif |