Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c | 10 | #include <linux/mm.h> |
76ebd054 | 11 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
12 | #include <linux/seq_file.h> |
13 | #include <linux/debugfs.h> | |
9f4c815c | 14 | |
950f9d95 | 15 | #include <asm/e820.h> |
1da177e4 LT |
16 | #include <asm/processor.h> |
17 | #include <asm/tlbflush.h> | |
f8af095d | 18 | #include <asm/sections.h> |
9f4c815c IM |
19 | #include <asm/uaccess.h> |
20 | #include <asm/pgalloc.h> | |
c31c7d48 | 21 | #include <asm/proto.h> |
1219333d | 22 | #include <asm/pat.h> |
1da177e4 | 23 | |
9df84993 IM |
24 | /* |
25 | * The current flushing context - we pass it instead of 5 arguments: | |
26 | */ | |
72e458df TG |
27 | struct cpa_data { |
28 | unsigned long vaddr; | |
72e458df TG |
29 | pgprot_t mask_set; |
30 | pgprot_t mask_clr; | |
65e074df | 31 | int numpages; |
f4ae5da0 | 32 | int flushtlb; |
c31c7d48 | 33 | unsigned long pfn; |
c9caa02c | 34 | unsigned force_split : 1; |
72e458df TG |
35 | }; |
36 | ||
65280e61 | 37 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
38 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
39 | ||
65280e61 | 40 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 41 | { |
ce0c0e50 | 42 | unsigned long flags; |
65280e61 | 43 | |
ce0c0e50 AK |
44 | /* Protect against CPA */ |
45 | spin_lock_irqsave(&pgd_lock, flags); | |
46 | direct_pages_count[level] += pages; | |
47 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
48 | } |
49 | ||
50 | static void split_page_count(int level) | |
51 | { | |
52 | direct_pages_count[level]--; | |
53 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
54 | } | |
55 | ||
56 | int arch_report_meminfo(char *page) | |
57 | { | |
58 | int n = sprintf(page, "DirectMap4k: %8lu\n" | |
59 | "DirectMap2M: %8lu\n", | |
60 | direct_pages_count[PG_LEVEL_4K], | |
61 | direct_pages_count[PG_LEVEL_2M]); | |
62 | #ifdef CONFIG_X86_64 | |
63 | n += sprintf(page + n, "DirectMap1G: %8lu\n", | |
64 | direct_pages_count[PG_LEVEL_1G]); | |
ce0c0e50 | 65 | #endif |
65280e61 | 66 | return n; |
ce0c0e50 | 67 | } |
65280e61 TG |
68 | #else |
69 | static inline void split_page_count(int level) { } | |
70 | #endif | |
ce0c0e50 | 71 | |
c31c7d48 TG |
72 | #ifdef CONFIG_X86_64 |
73 | ||
74 | static inline unsigned long highmap_start_pfn(void) | |
75 | { | |
76 | return __pa(_text) >> PAGE_SHIFT; | |
77 | } | |
78 | ||
79 | static inline unsigned long highmap_end_pfn(void) | |
80 | { | |
81 | return __pa(round_up((unsigned long)_end, PMD_SIZE)) >> PAGE_SHIFT; | |
82 | } | |
83 | ||
84 | #endif | |
85 | ||
92cb54a3 IM |
86 | #ifdef CONFIG_DEBUG_PAGEALLOC |
87 | # define debug_pagealloc 1 | |
88 | #else | |
89 | # define debug_pagealloc 0 | |
90 | #endif | |
91 | ||
ed724be6 AV |
92 | static inline int |
93 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 94 | { |
ed724be6 AV |
95 | return addr >= start && addr < end; |
96 | } | |
97 | ||
d7c8f21a TG |
98 | /* |
99 | * Flushing functions | |
100 | */ | |
cd8ddf1a | 101 | |
cd8ddf1a TG |
102 | /** |
103 | * clflush_cache_range - flush a cache range with clflush | |
104 | * @addr: virtual start address | |
105 | * @size: number of bytes to flush | |
106 | * | |
107 | * clflush is an unordered instruction which needs fencing with mfence | |
108 | * to avoid ordering issues. | |
109 | */ | |
4c61afcd | 110 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 111 | { |
4c61afcd | 112 | void *vend = vaddr + size - 1; |
d7c8f21a | 113 | |
cd8ddf1a | 114 | mb(); |
4c61afcd IM |
115 | |
116 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
117 | clflush(vaddr); | |
118 | /* | |
119 | * Flush any possible final partial cacheline: | |
120 | */ | |
121 | clflush(vend); | |
122 | ||
cd8ddf1a | 123 | mb(); |
d7c8f21a TG |
124 | } |
125 | ||
af1e6844 | 126 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 127 | { |
6bb8383b AK |
128 | unsigned long cache = (unsigned long)arg; |
129 | ||
d7c8f21a TG |
130 | /* |
131 | * Flush all to work around Errata in early athlons regarding | |
132 | * large page flushing. | |
133 | */ | |
134 | __flush_tlb_all(); | |
135 | ||
6bb8383b | 136 | if (cache && boot_cpu_data.x86_model >= 4) |
d7c8f21a TG |
137 | wbinvd(); |
138 | } | |
139 | ||
6bb8383b | 140 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
141 | { |
142 | BUG_ON(irqs_disabled()); | |
143 | ||
15c8b6c1 | 144 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
145 | } |
146 | ||
57a6a46a TG |
147 | static void __cpa_flush_range(void *arg) |
148 | { | |
57a6a46a TG |
149 | /* |
150 | * We could optimize that further and do individual per page | |
151 | * tlb invalidates for a low number of pages. Caveat: we must | |
152 | * flush the high aliases on 64bit as well. | |
153 | */ | |
154 | __flush_tlb_all(); | |
57a6a46a TG |
155 | } |
156 | ||
6bb8383b | 157 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 158 | { |
4c61afcd IM |
159 | unsigned int i, level; |
160 | unsigned long addr; | |
161 | ||
57a6a46a | 162 | BUG_ON(irqs_disabled()); |
4c61afcd | 163 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 164 | |
15c8b6c1 | 165 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 166 | |
6bb8383b AK |
167 | if (!cache) |
168 | return; | |
169 | ||
3b233e52 TG |
170 | /* |
171 | * We only need to flush on one CPU, | |
172 | * clflush is a MESI-coherent instruction that | |
173 | * will cause all other CPUs to flush the same | |
174 | * cachelines: | |
175 | */ | |
4c61afcd IM |
176 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
177 | pte_t *pte = lookup_address(addr, &level); | |
178 | ||
179 | /* | |
180 | * Only flush present addresses: | |
181 | */ | |
7bfb72e8 | 182 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
183 | clflush_cache_range((void *) addr, PAGE_SIZE); |
184 | } | |
57a6a46a TG |
185 | } |
186 | ||
ed724be6 AV |
187 | /* |
188 | * Certain areas of memory on x86 require very specific protection flags, | |
189 | * for example the BIOS area or kernel text. Callers don't always get this | |
190 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
191 | * checks and fixes these known static required protection bits. | |
192 | */ | |
c31c7d48 TG |
193 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
194 | unsigned long pfn) | |
ed724be6 AV |
195 | { |
196 | pgprot_t forbidden = __pgprot(0); | |
197 | ||
687c4825 | 198 | /* |
ed724be6 AV |
199 | * The BIOS area between 640k and 1Mb needs to be executable for |
200 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 201 | */ |
c31c7d48 | 202 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
203 | pgprot_val(forbidden) |= _PAGE_NX; |
204 | ||
205 | /* | |
206 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
207 | * Does not cover __inittext since that is gone later on. On |
208 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
209 | */ |
210 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
211 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 212 | |
cc0f21bb | 213 | /* |
c31c7d48 TG |
214 | * The .rodata section needs to be read-only. Using the pfn |
215 | * catches all aliases. | |
cc0f21bb | 216 | */ |
c31c7d48 TG |
217 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
218 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 219 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 AV |
220 | |
221 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
222 | |
223 | return prot; | |
224 | } | |
225 | ||
9a14aefc TG |
226 | /* |
227 | * Lookup the page table entry for a virtual address. Return a pointer | |
228 | * to the entry and the level of the mapping. | |
229 | * | |
230 | * Note: We return pud and pmd either when the entry is marked large | |
231 | * or when the present bit is not set. Otherwise we would return a | |
232 | * pointer to a nonexisting mapping. | |
233 | */ | |
da7bfc50 | 234 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 235 | { |
1da177e4 LT |
236 | pgd_t *pgd = pgd_offset_k(address); |
237 | pud_t *pud; | |
238 | pmd_t *pmd; | |
9f4c815c | 239 | |
30551bb3 TG |
240 | *level = PG_LEVEL_NONE; |
241 | ||
1da177e4 LT |
242 | if (pgd_none(*pgd)) |
243 | return NULL; | |
9df84993 | 244 | |
1da177e4 LT |
245 | pud = pud_offset(pgd, address); |
246 | if (pud_none(*pud)) | |
247 | return NULL; | |
c2f71ee2 AK |
248 | |
249 | *level = PG_LEVEL_1G; | |
250 | if (pud_large(*pud) || !pud_present(*pud)) | |
251 | return (pte_t *)pud; | |
252 | ||
1da177e4 LT |
253 | pmd = pmd_offset(pud, address); |
254 | if (pmd_none(*pmd)) | |
255 | return NULL; | |
30551bb3 TG |
256 | |
257 | *level = PG_LEVEL_2M; | |
9a14aefc | 258 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 259 | return (pte_t *)pmd; |
1da177e4 | 260 | |
30551bb3 | 261 | *level = PG_LEVEL_4K; |
9df84993 | 262 | |
9f4c815c IM |
263 | return pte_offset_kernel(pmd, address); |
264 | } | |
75bb8835 | 265 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 266 | |
9df84993 IM |
267 | /* |
268 | * Set the new pmd in all the pgds we know about: | |
269 | */ | |
9a3dc780 | 270 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 271 | { |
9f4c815c IM |
272 | /* change init_mm */ |
273 | set_pte_atomic(kpte, pte); | |
44af6c41 | 274 | #ifdef CONFIG_X86_32 |
e4b71dcf | 275 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
276 | struct page *page; |
277 | ||
e3ed910d | 278 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
279 | pgd_t *pgd; |
280 | pud_t *pud; | |
281 | pmd_t *pmd; | |
282 | ||
283 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
284 | pud = pud_offset(pgd, address); | |
285 | pmd = pmd_offset(pud, address); | |
286 | set_pte_atomic((pte_t *)pmd, pte); | |
287 | } | |
1da177e4 | 288 | } |
44af6c41 | 289 | #endif |
1da177e4 LT |
290 | } |
291 | ||
9df84993 IM |
292 | static int |
293 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
294 | struct cpa_data *cpa) | |
65e074df | 295 | { |
c31c7d48 | 296 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
297 | pte_t new_pte, old_pte, *tmp; |
298 | pgprot_t old_prot, new_prot; | |
fac84939 | 299 | int i, do_split = 1; |
da7bfc50 | 300 | unsigned int level; |
65e074df | 301 | |
c9caa02c AK |
302 | if (cpa->force_split) |
303 | return 1; | |
304 | ||
65e074df TG |
305 | spin_lock_irqsave(&pgd_lock, flags); |
306 | /* | |
307 | * Check for races, another CPU might have split this page | |
308 | * up already: | |
309 | */ | |
310 | tmp = lookup_address(address, &level); | |
311 | if (tmp != kpte) | |
312 | goto out_unlock; | |
313 | ||
314 | switch (level) { | |
315 | case PG_LEVEL_2M: | |
31422c51 AK |
316 | psize = PMD_PAGE_SIZE; |
317 | pmask = PMD_PAGE_MASK; | |
65e074df | 318 | break; |
f07333fd | 319 | #ifdef CONFIG_X86_64 |
65e074df | 320 | case PG_LEVEL_1G: |
5d3c8b21 AK |
321 | psize = PUD_PAGE_SIZE; |
322 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
323 | break; |
324 | #endif | |
65e074df | 325 | default: |
beaff633 | 326 | do_split = -EINVAL; |
65e074df TG |
327 | goto out_unlock; |
328 | } | |
329 | ||
330 | /* | |
331 | * Calculate the number of pages, which fit into this large | |
332 | * page starting at address: | |
333 | */ | |
334 | nextpage_addr = (address + psize) & pmask; | |
335 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
336 | if (numpages < cpa->numpages) |
337 | cpa->numpages = numpages; | |
65e074df TG |
338 | |
339 | /* | |
340 | * We are safe now. Check whether the new pgprot is the same: | |
341 | */ | |
342 | old_pte = *kpte; | |
343 | old_prot = new_prot = pte_pgprot(old_pte); | |
344 | ||
345 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
346 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
347 | |
348 | /* | |
349 | * old_pte points to the large page base address. So we need | |
350 | * to add the offset of the virtual address: | |
351 | */ | |
352 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
353 | cpa->pfn = pfn; | |
354 | ||
355 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 356 | |
fac84939 TG |
357 | /* |
358 | * We need to check the full range, whether | |
359 | * static_protection() requires a different pgprot for one of | |
360 | * the pages in the range we try to preserve: | |
361 | */ | |
362 | addr = address + PAGE_SIZE; | |
c31c7d48 | 363 | pfn++; |
9b5cf48b | 364 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 365 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
366 | |
367 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
368 | goto out_unlock; | |
369 | } | |
370 | ||
65e074df TG |
371 | /* |
372 | * If there are no changes, return. maxpages has been updated | |
373 | * above: | |
374 | */ | |
375 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 376 | do_split = 0; |
65e074df TG |
377 | goto out_unlock; |
378 | } | |
379 | ||
380 | /* | |
381 | * We need to change the attributes. Check, whether we can | |
382 | * change the large page in one go. We request a split, when | |
383 | * the address is not aligned and the number of pages is | |
384 | * smaller than the number of pages in the large page. Note | |
385 | * that we limited the number of possible pages already to | |
386 | * the number of pages in the large page. | |
387 | */ | |
9b5cf48b | 388 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
389 | /* |
390 | * The address is aligned and the number of pages | |
391 | * covers the full page. | |
392 | */ | |
393 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
394 | __set_pmd_pte(kpte, address, new_pte); | |
395 | cpa->flushtlb = 1; | |
beaff633 | 396 | do_split = 0; |
65e074df TG |
397 | } |
398 | ||
399 | out_unlock: | |
400 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 401 | |
beaff633 | 402 | return do_split; |
65e074df TG |
403 | } |
404 | ||
76ebd054 TG |
405 | static LIST_HEAD(page_pool); |
406 | static unsigned long pool_size, pool_pages, pool_low; | |
92cb54a3 | 407 | static unsigned long pool_used, pool_failed; |
76ebd054 | 408 | |
92cb54a3 | 409 | static void cpa_fill_pool(struct page **ret) |
76ebd054 | 410 | { |
76ebd054 | 411 | gfp_t gfp = GFP_KERNEL; |
92cb54a3 IM |
412 | unsigned long flags; |
413 | struct page *p; | |
76ebd054 | 414 | |
76ebd054 | 415 | /* |
92cb54a3 IM |
416 | * Avoid recursion (on debug-pagealloc) and also signal |
417 | * our priority to get to these pagetables: | |
76ebd054 | 418 | */ |
92cb54a3 | 419 | if (current->flags & PF_MEMALLOC) |
76ebd054 | 420 | return; |
92cb54a3 | 421 | current->flags |= PF_MEMALLOC; |
76ebd054 | 422 | |
76ebd054 | 423 | /* |
92cb54a3 | 424 | * Allocate atomically from atomic contexts: |
76ebd054 | 425 | */ |
92cb54a3 IM |
426 | if (in_atomic() || irqs_disabled() || debug_pagealloc) |
427 | gfp = GFP_ATOMIC | __GFP_NORETRY | __GFP_NOWARN; | |
76ebd054 | 428 | |
92cb54a3 | 429 | while (pool_pages < pool_size || (ret && !*ret)) { |
76ebd054 TG |
430 | p = alloc_pages(gfp, 0); |
431 | if (!p) { | |
432 | pool_failed++; | |
433 | break; | |
434 | } | |
92cb54a3 IM |
435 | /* |
436 | * If the call site needs a page right now, provide it: | |
437 | */ | |
438 | if (ret && !*ret) { | |
439 | *ret = p; | |
440 | continue; | |
441 | } | |
442 | spin_lock_irqsave(&pgd_lock, flags); | |
76ebd054 TG |
443 | list_add(&p->lru, &page_pool); |
444 | pool_pages++; | |
92cb54a3 | 445 | spin_unlock_irqrestore(&pgd_lock, flags); |
76ebd054 | 446 | } |
92cb54a3 IM |
447 | |
448 | current->flags &= ~PF_MEMALLOC; | |
76ebd054 TG |
449 | } |
450 | ||
451 | #define SHIFT_MB (20 - PAGE_SHIFT) | |
452 | #define ROUND_MB_GB ((1 << 10) - 1) | |
453 | #define SHIFT_MB_GB 10 | |
454 | #define POOL_PAGES_PER_GB 16 | |
455 | ||
456 | void __init cpa_init(void) | |
457 | { | |
458 | struct sysinfo si; | |
459 | unsigned long gb; | |
460 | ||
461 | si_meminfo(&si); | |
462 | /* | |
463 | * Calculate the number of pool pages: | |
464 | * | |
465 | * Convert totalram (nr of pages) to MiB and round to the next | |
466 | * GiB. Shift MiB to Gib and multiply the result by | |
467 | * POOL_PAGES_PER_GB: | |
468 | */ | |
92cb54a3 IM |
469 | if (debug_pagealloc) { |
470 | gb = ((si.totalram >> SHIFT_MB) + ROUND_MB_GB) >> SHIFT_MB_GB; | |
471 | pool_size = POOL_PAGES_PER_GB * gb; | |
472 | } else { | |
473 | pool_size = 1; | |
474 | } | |
76ebd054 TG |
475 | pool_low = pool_size; |
476 | ||
92cb54a3 | 477 | cpa_fill_pool(NULL); |
76ebd054 TG |
478 | printk(KERN_DEBUG |
479 | "CPA: page pool initialized %lu of %lu pages preallocated\n", | |
480 | pool_pages, pool_size); | |
481 | } | |
482 | ||
7afe15b9 | 483 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 484 | { |
7b610eec | 485 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 486 | unsigned int i, level; |
bb5c2dbd | 487 | pte_t *pbase, *tmp; |
9df84993 | 488 | pgprot_t ref_prot; |
bb5c2dbd IM |
489 | struct page *base; |
490 | ||
eb5b5f02 TG |
491 | /* |
492 | * Get a page from the pool. The pool list is protected by the | |
493 | * pgd_lock, which we have to take anyway for the split | |
494 | * operation: | |
495 | */ | |
496 | spin_lock_irqsave(&pgd_lock, flags); | |
497 | if (list_empty(&page_pool)) { | |
498 | spin_unlock_irqrestore(&pgd_lock, flags); | |
92cb54a3 IM |
499 | base = NULL; |
500 | cpa_fill_pool(&base); | |
501 | if (!base) | |
502 | return -ENOMEM; | |
503 | spin_lock_irqsave(&pgd_lock, flags); | |
504 | } else { | |
505 | base = list_first_entry(&page_pool, struct page, lru); | |
506 | list_del(&base->lru); | |
507 | pool_pages--; | |
508 | ||
509 | if (pool_pages < pool_low) | |
510 | pool_low = pool_pages; | |
eb5b5f02 TG |
511 | } |
512 | ||
bb5c2dbd IM |
513 | /* |
514 | * Check for races, another CPU might have split this page | |
515 | * up for us already: | |
516 | */ | |
517 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 518 | if (tmp != kpte) |
bb5c2dbd IM |
519 | goto out_unlock; |
520 | ||
bb5c2dbd | 521 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 522 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 523 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
bb5c2dbd | 524 | |
f07333fd AK |
525 | #ifdef CONFIG_X86_64 |
526 | if (level == PG_LEVEL_1G) { | |
527 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
528 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
529 | } |
530 | #endif | |
531 | ||
63c1dcf4 TG |
532 | /* |
533 | * Get the target pfn from the original entry: | |
534 | */ | |
535 | pfn = pte_pfn(*kpte); | |
f07333fd | 536 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 537 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 538 | |
ce0c0e50 | 539 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
540 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
541 | split_page_count(level); | |
542 | ||
543 | #ifdef CONFIG_X86_64 | |
544 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
545 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
546 | split_page_count(level); | |
f361a450 | 547 | #endif |
ce0c0e50 | 548 | |
bb5c2dbd | 549 | /* |
07cf89c0 | 550 | * Install the new, split up pagetable. Important details here: |
4c881ca1 HY |
551 | * |
552 | * On Intel the NX bit of all levels must be cleared to make a | |
553 | * page executable. See section 4.13.2 of Intel 64 and IA-32 | |
554 | * Architectures Software Developer's Manual). | |
07cf89c0 TG |
555 | * |
556 | * Mark the entry present. The current mapping might be | |
557 | * set to not present, which we preserved above. | |
bb5c2dbd | 558 | */ |
4c881ca1 | 559 | ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte))); |
07cf89c0 | 560 | pgprot_val(ref_prot) |= _PAGE_PRESENT; |
9a3dc780 | 561 | __set_pmd_pte(kpte, address, mk_pte(base, ref_prot)); |
bb5c2dbd IM |
562 | base = NULL; |
563 | ||
564 | out_unlock: | |
eb5b5f02 TG |
565 | /* |
566 | * If we dropped out via the lookup_address check under | |
567 | * pgd_lock then stick the page back into the pool: | |
568 | */ | |
569 | if (base) { | |
570 | list_add(&base->lru, &page_pool); | |
571 | pool_pages++; | |
572 | } else | |
573 | pool_used++; | |
9a3dc780 | 574 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 575 | |
bb5c2dbd IM |
576 | return 0; |
577 | } | |
578 | ||
c31c7d48 | 579 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 580 | { |
c31c7d48 | 581 | unsigned long address = cpa->vaddr; |
da7bfc50 HH |
582 | int do_split, err; |
583 | unsigned int level; | |
c31c7d48 | 584 | pte_t *kpte, old_pte; |
1da177e4 | 585 | |
97f99fed | 586 | repeat: |
f0646e43 | 587 | kpte = lookup_address(address, &level); |
1da177e4 | 588 | if (!kpte) |
d1a4be63 | 589 | return 0; |
c31c7d48 TG |
590 | |
591 | old_pte = *kpte; | |
592 | if (!pte_val(old_pte)) { | |
593 | if (!primary) | |
594 | return 0; | |
595 | printk(KERN_WARNING "CPA: called for zero pte. " | |
596 | "vaddr = %lx cpa->vaddr = %lx\n", address, | |
597 | cpa->vaddr); | |
598 | WARN_ON(1); | |
1da177e4 | 599 | return -EINVAL; |
c31c7d48 | 600 | } |
9f4c815c | 601 | |
30551bb3 | 602 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 603 | pte_t new_pte; |
626c2c9d | 604 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 605 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 606 | |
72e458df TG |
607 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
608 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 609 | |
c31c7d48 | 610 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 611 | |
626c2c9d AV |
612 | /* |
613 | * We need to keep the pfn from the existing PTE, | |
614 | * after all we're only going to change it's attributes | |
615 | * not the memory it points to | |
616 | */ | |
c31c7d48 TG |
617 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
618 | cpa->pfn = pfn; | |
f4ae5da0 TG |
619 | /* |
620 | * Do we really change anything ? | |
621 | */ | |
622 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
623 | set_pte_atomic(kpte, new_pte); | |
624 | cpa->flushtlb = 1; | |
625 | } | |
9b5cf48b | 626 | cpa->numpages = 1; |
65e074df | 627 | return 0; |
1da177e4 | 628 | } |
65e074df TG |
629 | |
630 | /* | |
631 | * Check, whether we can keep the large page intact | |
632 | * and just change the pte: | |
633 | */ | |
beaff633 | 634 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
635 | /* |
636 | * When the range fits into the existing large page, | |
9b5cf48b | 637 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
638 | * try_large_page: |
639 | */ | |
87f7f8fe IM |
640 | if (do_split <= 0) |
641 | return do_split; | |
65e074df TG |
642 | |
643 | /* | |
644 | * We have to split the large page: | |
645 | */ | |
87f7f8fe IM |
646 | err = split_large_page(kpte, address); |
647 | if (!err) { | |
648 | cpa->flushtlb = 1; | |
649 | goto repeat; | |
650 | } | |
beaff633 | 651 | |
87f7f8fe | 652 | return err; |
9f4c815c | 653 | } |
1da177e4 | 654 | |
c31c7d48 TG |
655 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
656 | ||
657 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 658 | { |
c31c7d48 | 659 | struct cpa_data alias_cpa; |
f34b439f | 660 | int ret = 0; |
44af6c41 | 661 | |
965194c1 | 662 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 663 | return 0; |
626c2c9d | 664 | |
f361a450 | 665 | #ifdef CONFIG_X86_64 |
965194c1 | 666 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
667 | return 0; |
668 | #endif | |
f34b439f TG |
669 | /* |
670 | * No need to redo, when the primary call touched the direct | |
671 | * mapping already: | |
672 | */ | |
f361a450 YL |
673 | if (!(within(cpa->vaddr, PAGE_OFFSET, |
674 | PAGE_OFFSET + (max_low_pfn_mapped << PAGE_SHIFT)) | |
675 | #ifdef CONFIG_X86_64 | |
676 | || within(cpa->vaddr, PAGE_OFFSET + (1UL<<32), | |
677 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)) | |
678 | #endif | |
679 | )) { | |
44af6c41 | 680 | |
f34b439f TG |
681 | alias_cpa = *cpa; |
682 | alias_cpa.vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT); | |
683 | ||
684 | ret = __change_page_attr_set_clr(&alias_cpa, 0); | |
685 | } | |
44af6c41 | 686 | |
44af6c41 | 687 | #ifdef CONFIG_X86_64 |
c31c7d48 TG |
688 | if (ret) |
689 | return ret; | |
f34b439f TG |
690 | /* |
691 | * No need to redo, when the primary call touched the high | |
692 | * mapping already: | |
693 | */ | |
694 | if (within(cpa->vaddr, (unsigned long) _text, (unsigned long) _end)) | |
695 | return 0; | |
696 | ||
488fd995 | 697 | /* |
0879750f TG |
698 | * If the physical address is inside the kernel map, we need |
699 | * to touch the high mapped kernel as well: | |
488fd995 | 700 | */ |
c31c7d48 TG |
701 | if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) |
702 | return 0; | |
0879750f | 703 | |
c31c7d48 TG |
704 | alias_cpa = *cpa; |
705 | alias_cpa.vaddr = | |
706 | (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base; | |
707 | ||
708 | /* | |
709 | * The high mapping range is imprecise, so ignore the return value. | |
710 | */ | |
711 | __change_page_attr_set_clr(&alias_cpa, 0); | |
488fd995 | 712 | #endif |
c31c7d48 | 713 | return ret; |
1da177e4 LT |
714 | } |
715 | ||
c31c7d48 | 716 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 717 | { |
65e074df | 718 | int ret, numpages = cpa->numpages; |
ff31452b | 719 | |
65e074df TG |
720 | while (numpages) { |
721 | /* | |
722 | * Store the remaining nr of pages for the large page | |
723 | * preservation check. | |
724 | */ | |
9b5cf48b | 725 | cpa->numpages = numpages; |
c31c7d48 TG |
726 | |
727 | ret = __change_page_attr(cpa, checkalias); | |
ff31452b TG |
728 | if (ret) |
729 | return ret; | |
ff31452b | 730 | |
c31c7d48 TG |
731 | if (checkalias) { |
732 | ret = cpa_process_alias(cpa); | |
733 | if (ret) | |
734 | return ret; | |
735 | } | |
736 | ||
65e074df TG |
737 | /* |
738 | * Adjust the number of pages with the result of the | |
739 | * CPA operation. Either a large page has been | |
740 | * preserved or a single page update happened. | |
741 | */ | |
9b5cf48b RW |
742 | BUG_ON(cpa->numpages > numpages); |
743 | numpages -= cpa->numpages; | |
744 | cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
65e074df | 745 | } |
ff31452b TG |
746 | return 0; |
747 | } | |
748 | ||
6bb8383b AK |
749 | static inline int cache_attr(pgprot_t attr) |
750 | { | |
751 | return pgprot_val(attr) & | |
752 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
753 | } | |
754 | ||
1ac2f7d5 | 755 | static int do_change_page_attr_set_clr(unsigned long addr, int numpages, |
c9caa02c | 756 | pgprot_t mask_set, pgprot_t mask_clr, |
1ac2f7d5 | 757 | int force_split, int *tlb_flush) |
ff31452b | 758 | { |
72e458df | 759 | struct cpa_data cpa; |
1ac2f7d5 | 760 | int ret, checkalias; |
331e4065 TG |
761 | |
762 | /* | |
763 | * Check, if we are requested to change a not supported | |
764 | * feature: | |
765 | */ | |
766 | mask_set = canon_pgprot(mask_set); | |
767 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 768 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
769 | return 0; |
770 | ||
69b1415e TG |
771 | /* Ensure we are PAGE_SIZE aligned */ |
772 | if (addr & ~PAGE_MASK) { | |
773 | addr &= PAGE_MASK; | |
774 | /* | |
775 | * People should not be passing in unaligned addresses: | |
776 | */ | |
777 | WARN_ON_ONCE(1); | |
778 | } | |
779 | ||
5843d9a4 NP |
780 | /* Must avoid aliasing mappings in the highmem code */ |
781 | kmap_flush_unused(); | |
782 | ||
72e458df TG |
783 | cpa.vaddr = addr; |
784 | cpa.numpages = numpages; | |
785 | cpa.mask_set = mask_set; | |
786 | cpa.mask_clr = mask_clr; | |
f4ae5da0 | 787 | cpa.flushtlb = 0; |
c9caa02c | 788 | cpa.force_split = force_split; |
72e458df | 789 | |
af96e443 TG |
790 | /* No alias checking for _NX bit modifications */ |
791 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
792 | ||
793 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 794 | |
f4ae5da0 TG |
795 | /* |
796 | * Check whether we really changed something: | |
797 | */ | |
1ac2f7d5 SL |
798 | *tlb_flush = cpa.flushtlb; |
799 | cpa_fill_pool(NULL); | |
800 | ||
801 | return ret; | |
802 | } | |
803 | ||
804 | static int change_page_attr_set_clr(unsigned long addr, int numpages, | |
805 | pgprot_t mask_set, pgprot_t mask_clr, | |
806 | int force_split) | |
807 | { | |
808 | int cache, flush_cache = 0, ret; | |
f4ae5da0 | 809 | |
1ac2f7d5 SL |
810 | ret = do_change_page_attr_set_clr(addr, numpages, mask_set, mask_clr, |
811 | force_split, &flush_cache); | |
812 | if (!flush_cache) | |
813 | goto out; | |
6bb8383b AK |
814 | /* |
815 | * No need to flush, when we did not set any of the caching | |
816 | * attributes: | |
817 | */ | |
818 | cache = cache_attr(mask_set); | |
819 | ||
57a6a46a TG |
820 | /* |
821 | * On success we use clflush, when the CPU supports it to | |
822 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 823 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
824 | * wbindv): |
825 | */ | |
826 | if (!ret && cpu_has_clflush) | |
6bb8383b | 827 | cpa_flush_range(addr, numpages, cache); |
57a6a46a | 828 | else |
6bb8383b | 829 | cpa_flush_all(cache); |
76ebd054 | 830 | out: |
ff31452b TG |
831 | return ret; |
832 | } | |
833 | ||
56744546 TG |
834 | static inline int change_page_attr_set(unsigned long addr, int numpages, |
835 | pgprot_t mask) | |
75cbade8 | 836 | { |
c9caa02c | 837 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0); |
75cbade8 AV |
838 | } |
839 | ||
56744546 TG |
840 | static inline int change_page_attr_clear(unsigned long addr, int numpages, |
841 | pgprot_t mask) | |
72932c7a | 842 | { |
c9caa02c | 843 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0); |
72932c7a TG |
844 | } |
845 | ||
1219333d | 846 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 847 | { |
de33c442 SS |
848 | /* |
849 | * for now UC MINUS. see comments in ioremap_nocache() | |
850 | */ | |
72932c7a | 851 | return change_page_attr_set(addr, numpages, |
de33c442 | 852 | __pgprot(_PAGE_CACHE_UC_MINUS)); |
75cbade8 | 853 | } |
1219333d | 854 | |
855 | int set_memory_uc(unsigned long addr, int numpages) | |
856 | { | |
de33c442 SS |
857 | /* |
858 | * for now UC MINUS. see comments in ioremap_nocache() | |
859 | */ | |
1219333d | 860 | if (reserve_memtype(addr, addr + numpages * PAGE_SIZE, |
de33c442 | 861 | _PAGE_CACHE_UC_MINUS, NULL)) |
1219333d | 862 | return -EINVAL; |
863 | ||
864 | return _set_memory_uc(addr, numpages); | |
865 | } | |
75cbade8 AV |
866 | EXPORT_SYMBOL(set_memory_uc); |
867 | ||
1ac2f7d5 SL |
868 | int set_memory_uc_noflush(unsigned long addr, int numpages) |
869 | { | |
870 | int flush; | |
871 | /* | |
872 | * for now UC MINUS. see comments in ioremap_nocache() | |
873 | */ | |
874 | if (reserve_memtype(addr, addr + numpages * PAGE_SIZE, | |
875 | _PAGE_CACHE_UC_MINUS, NULL)) | |
876 | return -EINVAL; | |
877 | /* | |
878 | * for now UC MINUS. see comments in ioremap_nocache() | |
879 | */ | |
880 | return do_change_page_attr_set_clr(addr, numpages, | |
881 | __pgprot(_PAGE_CACHE_UC_MINUS), | |
882 | __pgprot(0), 0, &flush); | |
883 | } | |
884 | EXPORT_SYMBOL(set_memory_uc_noflush); | |
885 | ||
886 | void set_memory_flush_all(void) | |
887 | { | |
888 | cpa_flush_all(1); | |
889 | } | |
890 | EXPORT_SYMBOL(set_memory_flush_all); | |
891 | ||
ef354af4 | 892 | int _set_memory_wc(unsigned long addr, int numpages) |
893 | { | |
894 | return change_page_attr_set(addr, numpages, | |
895 | __pgprot(_PAGE_CACHE_WC)); | |
896 | } | |
897 | ||
898 | int set_memory_wc(unsigned long addr, int numpages) | |
899 | { | |
499f8f84 | 900 | if (!pat_enabled) |
ef354af4 | 901 | return set_memory_uc(addr, numpages); |
902 | ||
903 | if (reserve_memtype(addr, addr + numpages * PAGE_SIZE, | |
904 | _PAGE_CACHE_WC, NULL)) | |
905 | return -EINVAL; | |
906 | ||
907 | return _set_memory_wc(addr, numpages); | |
908 | } | |
909 | EXPORT_SYMBOL(set_memory_wc); | |
910 | ||
1219333d | 911 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 912 | { |
72932c7a | 913 | return change_page_attr_clear(addr, numpages, |
2e5d9c85 | 914 | __pgprot(_PAGE_CACHE_MASK)); |
75cbade8 | 915 | } |
1219333d | 916 | |
917 | int set_memory_wb(unsigned long addr, int numpages) | |
918 | { | |
919 | free_memtype(addr, addr + numpages * PAGE_SIZE); | |
920 | ||
921 | return _set_memory_wb(addr, numpages); | |
922 | } | |
75cbade8 AV |
923 | EXPORT_SYMBOL(set_memory_wb); |
924 | ||
925 | int set_memory_x(unsigned long addr, int numpages) | |
926 | { | |
72932c7a | 927 | return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX)); |
75cbade8 AV |
928 | } |
929 | EXPORT_SYMBOL(set_memory_x); | |
930 | ||
931 | int set_memory_nx(unsigned long addr, int numpages) | |
932 | { | |
72932c7a | 933 | return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX)); |
75cbade8 AV |
934 | } |
935 | EXPORT_SYMBOL(set_memory_nx); | |
936 | ||
937 | int set_memory_ro(unsigned long addr, int numpages) | |
938 | { | |
72932c7a | 939 | return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW)); |
75cbade8 | 940 | } |
75cbade8 AV |
941 | |
942 | int set_memory_rw(unsigned long addr, int numpages) | |
943 | { | |
72932c7a | 944 | return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW)); |
75cbade8 | 945 | } |
f62d0f00 IM |
946 | |
947 | int set_memory_np(unsigned long addr, int numpages) | |
948 | { | |
72932c7a | 949 | return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT)); |
f62d0f00 | 950 | } |
75cbade8 | 951 | |
c9caa02c AK |
952 | int set_memory_4k(unsigned long addr, int numpages) |
953 | { | |
954 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), | |
955 | __pgprot(0), 1); | |
956 | } | |
957 | ||
75cbade8 AV |
958 | int set_pages_uc(struct page *page, int numpages) |
959 | { | |
960 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 961 | |
d7c8f21a | 962 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
963 | } |
964 | EXPORT_SYMBOL(set_pages_uc); | |
965 | ||
1ac2f7d5 SL |
966 | int set_pages_uc_noflush(struct page *page, int numpages) |
967 | { | |
968 | unsigned long addr = (unsigned long)page_address(page); | |
969 | ||
970 | return set_memory_uc_noflush(addr, numpages); | |
971 | } | |
972 | EXPORT_SYMBOL(set_pages_uc_noflush); | |
973 | ||
75cbade8 AV |
974 | int set_pages_wb(struct page *page, int numpages) |
975 | { | |
976 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 977 | |
d7c8f21a | 978 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
979 | } |
980 | EXPORT_SYMBOL(set_pages_wb); | |
981 | ||
982 | int set_pages_x(struct page *page, int numpages) | |
983 | { | |
984 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 985 | |
d7c8f21a | 986 | return set_memory_x(addr, numpages); |
75cbade8 AV |
987 | } |
988 | EXPORT_SYMBOL(set_pages_x); | |
989 | ||
990 | int set_pages_nx(struct page *page, int numpages) | |
991 | { | |
992 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 993 | |
d7c8f21a | 994 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
995 | } |
996 | EXPORT_SYMBOL(set_pages_nx); | |
997 | ||
998 | int set_pages_ro(struct page *page, int numpages) | |
999 | { | |
1000 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1001 | |
d7c8f21a | 1002 | return set_memory_ro(addr, numpages); |
75cbade8 | 1003 | } |
75cbade8 AV |
1004 | |
1005 | int set_pages_rw(struct page *page, int numpages) | |
1006 | { | |
1007 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1008 | |
d7c8f21a | 1009 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1010 | } |
1011 | ||
1da177e4 | 1012 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1013 | |
1014 | static int __set_pages_p(struct page *page, int numpages) | |
1015 | { | |
72e458df TG |
1016 | struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page), |
1017 | .numpages = numpages, | |
1018 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
1019 | .mask_clr = __pgprot(0)}; | |
72932c7a | 1020 | |
c31c7d48 | 1021 | return __change_page_attr_set_clr(&cpa, 1); |
f62d0f00 IM |
1022 | } |
1023 | ||
1024 | static int __set_pages_np(struct page *page, int numpages) | |
1025 | { | |
72e458df TG |
1026 | struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page), |
1027 | .numpages = numpages, | |
1028 | .mask_set = __pgprot(0), | |
1029 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW)}; | |
72932c7a | 1030 | |
c31c7d48 | 1031 | return __change_page_attr_set_clr(&cpa, 1); |
f62d0f00 IM |
1032 | } |
1033 | ||
1da177e4 LT |
1034 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1035 | { | |
1036 | if (PageHighMem(page)) | |
1037 | return; | |
9f4c815c | 1038 | if (!enable) { |
f9b8404c IM |
1039 | debug_check_no_locks_freed(page_address(page), |
1040 | numpages * PAGE_SIZE); | |
9f4c815c | 1041 | } |
de5097c2 | 1042 | |
12d6f21e IM |
1043 | /* |
1044 | * If page allocator is not up yet then do not call c_p_a(): | |
1045 | */ | |
1046 | if (!debug_pagealloc_enabled) | |
1047 | return; | |
1048 | ||
9f4c815c | 1049 | /* |
f8d8406b IM |
1050 | * The return value is ignored as the calls cannot fail. |
1051 | * Large pages are kept enabled at boot time, and are | |
1052 | * split up quickly with DEBUG_PAGEALLOC. If a splitup | |
1053 | * fails here (due to temporary memory shortage) no damage | |
1054 | * is done because we just keep the largepage intact up | |
1055 | * to the next attempt when it will likely be split up: | |
1da177e4 | 1056 | */ |
f62d0f00 IM |
1057 | if (enable) |
1058 | __set_pages_p(page, numpages); | |
1059 | else | |
1060 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1061 | |
1062 | /* | |
e4b71dcf IM |
1063 | * We should perform an IPI and flush all tlbs, |
1064 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1065 | */ |
1066 | __flush_tlb_all(); | |
76ebd054 TG |
1067 | |
1068 | /* | |
1069 | * Try to refill the page pool here. We can do this only after | |
1070 | * the tlb flush. | |
1071 | */ | |
92cb54a3 | 1072 | cpa_fill_pool(NULL); |
1da177e4 | 1073 | } |
8a235efa | 1074 | |
ee7ae7a1 TG |
1075 | #ifdef CONFIG_DEBUG_FS |
1076 | static int dpa_show(struct seq_file *m, void *v) | |
1077 | { | |
1078 | seq_puts(m, "DEBUG_PAGEALLOC\n"); | |
1079 | seq_printf(m, "pool_size : %lu\n", pool_size); | |
1080 | seq_printf(m, "pool_pages : %lu\n", pool_pages); | |
1081 | seq_printf(m, "pool_low : %lu\n", pool_low); | |
1082 | seq_printf(m, "pool_used : %lu\n", pool_used); | |
1083 | seq_printf(m, "pool_failed : %lu\n", pool_failed); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static int dpa_open(struct inode *inode, struct file *filp) | |
1089 | { | |
1090 | return single_open(filp, dpa_show, NULL); | |
1091 | } | |
1092 | ||
1093 | static const struct file_operations dpa_fops = { | |
1094 | .open = dpa_open, | |
1095 | .read = seq_read, | |
1096 | .llseek = seq_lseek, | |
1097 | .release = single_release, | |
1098 | }; | |
1099 | ||
a4928cff | 1100 | static int __init debug_pagealloc_proc_init(void) |
ee7ae7a1 TG |
1101 | { |
1102 | struct dentry *de; | |
1103 | ||
1104 | de = debugfs_create_file("debug_pagealloc", 0600, NULL, NULL, | |
1105 | &dpa_fops); | |
1106 | if (!de) | |
1107 | return -ENOMEM; | |
1108 | ||
1109 | return 0; | |
1110 | } | |
1111 | __initcall(debug_pagealloc_proc_init); | |
1112 | #endif | |
1113 | ||
8a235efa RW |
1114 | #ifdef CONFIG_HIBERNATION |
1115 | ||
1116 | bool kernel_page_present(struct page *page) | |
1117 | { | |
1118 | unsigned int level; | |
1119 | pte_t *pte; | |
1120 | ||
1121 | if (PageHighMem(page)) | |
1122 | return false; | |
1123 | ||
1124 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1125 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1126 | } | |
1127 | ||
1128 | #endif /* CONFIG_HIBERNATION */ | |
1129 | ||
1130 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1131 | |
1132 | /* | |
1133 | * The testcases use internal knowledge of the implementation that shouldn't | |
1134 | * be exposed to the rest of the kernel. Include these directly here. | |
1135 | */ | |
1136 | #ifdef CONFIG_CPA_DEBUG | |
1137 | #include "pageattr-test.c" | |
1138 | #endif |