Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
57c8a661 | 6 | #include <linux/memblock.h> |
9f4c815c | 7 | #include <linux/sched.h> |
9f4c815c | 8 | #include <linux/mm.h> |
76ebd054 | 9 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
10 | #include <linux/seq_file.h> |
11 | #include <linux/debugfs.h> | |
e59a1bb2 | 12 | #include <linux/pfn.h> |
8c4bfc6e | 13 | #include <linux/percpu.h> |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
5bd5a452 | 15 | #include <linux/pci.h> |
d6472302 | 16 | #include <linux/vmalloc.h> |
9f4c815c | 17 | |
66441bd3 | 18 | #include <asm/e820/api.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
7c0f6ba6 | 23 | #include <linux/uaccess.h> |
9f4c815c | 24 | #include <asm/pgalloc.h> |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
d1163651 | 27 | #include <asm/set_memory.h> |
1da177e4 | 28 | |
935f5839 PZ |
29 | #include "mm_internal.h" |
30 | ||
9df84993 IM |
31 | /* |
32 | * The current flushing context - we pass it instead of 5 arguments: | |
33 | */ | |
72e458df | 34 | struct cpa_data { |
d75586ad | 35 | unsigned long *vaddr; |
0fd64c23 | 36 | pgd_t *pgd; |
72e458df TG |
37 | pgprot_t mask_set; |
38 | pgprot_t mask_clr; | |
74256377 | 39 | unsigned long numpages; |
98bfc9b0 | 40 | unsigned long curpage; |
c31c7d48 | 41 | unsigned long pfn; |
98bfc9b0 PZ |
42 | unsigned int flags; |
43 | unsigned int force_split : 1, | |
f61c5ba2 | 44 | force_static_prot : 1; |
9ae28475 | 45 | struct page **pages; |
72e458df TG |
46 | }; |
47 | ||
4046460b | 48 | enum cpa_warn { |
f61c5ba2 | 49 | CPA_CONFLICT, |
4046460b TG |
50 | CPA_PROTECT, |
51 | CPA_DETECT, | |
52 | }; | |
53 | ||
54 | static const int cpa_warn_level = CPA_PROTECT; | |
55 | ||
ad5ca55f SS |
56 | /* |
57 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
58 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
59 | * entries change the page attribute in parallel to some other cpu | |
60 | * splitting a large page entry along with changing the attribute. | |
61 | */ | |
62 | static DEFINE_SPINLOCK(cpa_lock); | |
63 | ||
d75586ad SL |
64 | #define CPA_FLUSHTLB 1 |
65 | #define CPA_ARRAY 2 | |
9ae28475 | 66 | #define CPA_PAGES_ARRAY 4 |
c40a56a7 | 67 | #define CPA_NO_CHECK_ALIAS 8 /* Do not search for aliases */ |
d75586ad | 68 | |
65280e61 | 69 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
70 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
71 | ||
65280e61 | 72 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 73 | { |
ce0c0e50 | 74 | /* Protect against CPA */ |
a79e53d8 | 75 | spin_lock(&pgd_lock); |
ce0c0e50 | 76 | direct_pages_count[level] += pages; |
a79e53d8 | 77 | spin_unlock(&pgd_lock); |
65280e61 TG |
78 | } |
79 | ||
80 | static void split_page_count(int level) | |
81 | { | |
c9e0d391 DJ |
82 | if (direct_pages_count[level] == 0) |
83 | return; | |
84 | ||
65280e61 TG |
85 | direct_pages_count[level]--; |
86 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
87 | } | |
88 | ||
e1759c21 | 89 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 90 | { |
b9c3bfc2 | 91 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
92 | direct_pages_count[PG_LEVEL_4K] << 2); |
93 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 94 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
95 | direct_pages_count[PG_LEVEL_2M] << 11); |
96 | #else | |
b9c3bfc2 | 97 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
98 | direct_pages_count[PG_LEVEL_2M] << 12); |
99 | #endif | |
a06de630 | 100 | if (direct_gbpages) |
b9c3bfc2 | 101 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 102 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 | 103 | } |
65280e61 TG |
104 | #else |
105 | static inline void split_page_count(int level) { } | |
106 | #endif | |
ce0c0e50 | 107 | |
5c280cf6 TG |
108 | #ifdef CONFIG_X86_CPA_STATISTICS |
109 | ||
110 | static unsigned long cpa_1g_checked; | |
111 | static unsigned long cpa_1g_sameprot; | |
112 | static unsigned long cpa_1g_preserved; | |
113 | static unsigned long cpa_2m_checked; | |
114 | static unsigned long cpa_2m_sameprot; | |
115 | static unsigned long cpa_2m_preserved; | |
5c280cf6 TG |
116 | static unsigned long cpa_4k_install; |
117 | ||
118 | static inline void cpa_inc_1g_checked(void) | |
119 | { | |
120 | cpa_1g_checked++; | |
121 | } | |
122 | ||
123 | static inline void cpa_inc_2m_checked(void) | |
124 | { | |
125 | cpa_2m_checked++; | |
126 | } | |
127 | ||
5c280cf6 TG |
128 | static inline void cpa_inc_4k_install(void) |
129 | { | |
130 | cpa_4k_install++; | |
131 | } | |
132 | ||
133 | static inline void cpa_inc_lp_sameprot(int level) | |
134 | { | |
135 | if (level == PG_LEVEL_1G) | |
136 | cpa_1g_sameprot++; | |
137 | else | |
138 | cpa_2m_sameprot++; | |
139 | } | |
140 | ||
141 | static inline void cpa_inc_lp_preserved(int level) | |
142 | { | |
143 | if (level == PG_LEVEL_1G) | |
144 | cpa_1g_preserved++; | |
145 | else | |
146 | cpa_2m_preserved++; | |
147 | } | |
148 | ||
149 | static int cpastats_show(struct seq_file *m, void *p) | |
150 | { | |
151 | seq_printf(m, "1G pages checked: %16lu\n", cpa_1g_checked); | |
152 | seq_printf(m, "1G pages sameprot: %16lu\n", cpa_1g_sameprot); | |
153 | seq_printf(m, "1G pages preserved: %16lu\n", cpa_1g_preserved); | |
154 | seq_printf(m, "2M pages checked: %16lu\n", cpa_2m_checked); | |
155 | seq_printf(m, "2M pages sameprot: %16lu\n", cpa_2m_sameprot); | |
156 | seq_printf(m, "2M pages preserved: %16lu\n", cpa_2m_preserved); | |
5c280cf6 TG |
157 | seq_printf(m, "4K pages set-checked: %16lu\n", cpa_4k_install); |
158 | return 0; | |
159 | } | |
160 | ||
161 | static int cpastats_open(struct inode *inode, struct file *file) | |
162 | { | |
163 | return single_open(file, cpastats_show, NULL); | |
164 | } | |
165 | ||
166 | static const struct file_operations cpastats_fops = { | |
167 | .open = cpastats_open, | |
168 | .read = seq_read, | |
169 | .llseek = seq_lseek, | |
170 | .release = single_release, | |
171 | }; | |
172 | ||
173 | static int __init cpa_stats_init(void) | |
174 | { | |
175 | debugfs_create_file("cpa_stats", S_IRUSR, arch_debugfs_dir, NULL, | |
176 | &cpastats_fops); | |
177 | return 0; | |
178 | } | |
179 | late_initcall(cpa_stats_init); | |
180 | #else | |
181 | static inline void cpa_inc_1g_checked(void) { } | |
182 | static inline void cpa_inc_2m_checked(void) { } | |
5c280cf6 TG |
183 | static inline void cpa_inc_4k_install(void) { } |
184 | static inline void cpa_inc_lp_sameprot(int level) { } | |
185 | static inline void cpa_inc_lp_preserved(int level) { } | |
186 | #endif | |
187 | ||
188 | ||
58e65b51 DH |
189 | static inline int |
190 | within(unsigned long addr, unsigned long start, unsigned long end) | |
191 | { | |
192 | return addr >= start && addr < end; | |
193 | } | |
194 | ||
195 | static inline int | |
196 | within_inclusive(unsigned long addr, unsigned long start, unsigned long end) | |
197 | { | |
198 | return addr >= start && addr <= end; | |
199 | } | |
200 | ||
c31c7d48 TG |
201 | #ifdef CONFIG_X86_64 |
202 | ||
203 | static inline unsigned long highmap_start_pfn(void) | |
204 | { | |
fc8d7826 | 205 | return __pa_symbol(_text) >> PAGE_SHIFT; |
c31c7d48 TG |
206 | } |
207 | ||
208 | static inline unsigned long highmap_end_pfn(void) | |
209 | { | |
4ff53087 TG |
210 | /* Do not reference physical address outside the kernel. */ |
211 | return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT; | |
c31c7d48 TG |
212 | } |
213 | ||
58e65b51 | 214 | static bool __cpa_pfn_in_highmap(unsigned long pfn) |
687c4825 | 215 | { |
58e65b51 DH |
216 | /* |
217 | * Kernel text has an alias mapping at a high address, known | |
218 | * here as "highmap". | |
219 | */ | |
220 | return within_inclusive(pfn, highmap_start_pfn(), highmap_end_pfn()); | |
ed724be6 AV |
221 | } |
222 | ||
58e65b51 DH |
223 | #else |
224 | ||
225 | static bool __cpa_pfn_in_highmap(unsigned long pfn) | |
4ff53087 | 226 | { |
58e65b51 DH |
227 | /* There is no highmap on 32-bit */ |
228 | return false; | |
4ff53087 TG |
229 | } |
230 | ||
58e65b51 DH |
231 | #endif |
232 | ||
98bfc9b0 | 233 | static unsigned long __cpa_addr(struct cpa_data *cpa, unsigned long idx) |
16ebf031 PZ |
234 | { |
235 | if (cpa->flags & CPA_PAGES_ARRAY) { | |
236 | struct page *page = cpa->pages[idx]; | |
237 | ||
238 | if (unlikely(PageHighMem(page))) | |
239 | return 0; | |
240 | ||
241 | return (unsigned long)page_address(page); | |
242 | } | |
243 | ||
244 | if (cpa->flags & CPA_ARRAY) | |
245 | return cpa->vaddr[idx]; | |
246 | ||
98bfc9b0 | 247 | return *cpa->vaddr + idx * PAGE_SIZE; |
16ebf031 PZ |
248 | } |
249 | ||
d7c8f21a TG |
250 | /* |
251 | * Flushing functions | |
252 | */ | |
cd8ddf1a | 253 | |
cd8ddf1a TG |
254 | /** |
255 | * clflush_cache_range - flush a cache range with clflush | |
9efc31b8 | 256 | * @vaddr: virtual start address |
cd8ddf1a TG |
257 | * @size: number of bytes to flush |
258 | * | |
8b80fd8b RZ |
259 | * clflushopt is an unordered instruction which needs fencing with mfence or |
260 | * sfence to avoid ordering issues. | |
cd8ddf1a | 261 | */ |
4c61afcd | 262 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 263 | { |
1f1a89ac CW |
264 | const unsigned long clflush_size = boot_cpu_data.x86_clflush_size; |
265 | void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1)); | |
6c434d61 | 266 | void *vend = vaddr + size; |
1f1a89ac CW |
267 | |
268 | if (p >= vend) | |
269 | return; | |
d7c8f21a | 270 | |
cd8ddf1a | 271 | mb(); |
4c61afcd | 272 | |
1f1a89ac | 273 | for (; p < vend; p += clflush_size) |
6c434d61 | 274 | clflushopt(p); |
4c61afcd | 275 | |
cd8ddf1a | 276 | mb(); |
d7c8f21a | 277 | } |
e517a5e9 | 278 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 279 | |
f2b61257 DW |
280 | void arch_invalidate_pmem(void *addr, size_t size) |
281 | { | |
282 | clflush_cache_range(addr, size); | |
283 | } | |
284 | EXPORT_SYMBOL_GPL(arch_invalidate_pmem); | |
285 | ||
af1e6844 | 286 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 287 | { |
6bb8383b AK |
288 | unsigned long cache = (unsigned long)arg; |
289 | ||
d7c8f21a TG |
290 | /* |
291 | * Flush all to work around Errata in early athlons regarding | |
292 | * large page flushing. | |
293 | */ | |
294 | __flush_tlb_all(); | |
295 | ||
0b827537 | 296 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
297 | wbinvd(); |
298 | } | |
299 | ||
6bb8383b | 300 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a | 301 | { |
d2479a30 | 302 | BUG_ON(irqs_disabled() && !early_boot_irqs_disabled); |
d7c8f21a | 303 | |
15c8b6c1 | 304 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
305 | } |
306 | ||
721066df | 307 | static bool __inv_flush_all(int cache) |
57a6a46a | 308 | { |
a53276e2 | 309 | BUG_ON(irqs_disabled() && !early_boot_irqs_disabled); |
47e262ac | 310 | |
7904ba8a | 311 | if (cache && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
5f464b33 | 312 | cpa_flush_all(cache); |
47e262ac | 313 | return true; |
5f464b33 PZ |
314 | } |
315 | ||
721066df | 316 | return false; |
47e262ac PZ |
317 | } |
318 | ||
319 | static void cpa_flush_range(unsigned long start, int numpages, int cache) | |
320 | { | |
321 | unsigned int i, level; | |
322 | unsigned long addr; | |
323 | ||
721066df PZ |
324 | WARN_ON(PAGE_ALIGN(start) != start); |
325 | ||
326 | if (__inv_flush_all(cache)) | |
327 | return; | |
328 | ||
329 | flush_tlb_kernel_range(start, start + PAGE_SIZE * numpages); | |
330 | ||
331 | if (!cache) | |
6bb8383b AK |
332 | return; |
333 | ||
3b233e52 TG |
334 | /* |
335 | * We only need to flush on one CPU, | |
336 | * clflush is a MESI-coherent instruction that | |
337 | * will cause all other CPUs to flush the same | |
338 | * cachelines: | |
339 | */ | |
4c61afcd IM |
340 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
341 | pte_t *pte = lookup_address(addr, &level); | |
342 | ||
343 | /* | |
344 | * Only flush present addresses: | |
345 | */ | |
7bfb72e8 | 346 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
347 | clflush_cache_range((void *) addr, PAGE_SIZE); |
348 | } | |
57a6a46a TG |
349 | } |
350 | ||
935f5839 | 351 | void __cpa_flush_array(void *data) |
d75586ad | 352 | { |
935f5839 PZ |
353 | struct cpa_data *cpa = data; |
354 | unsigned int i; | |
d75586ad | 355 | |
935f5839 PZ |
356 | for (i = 0; i < cpa->numpages; i++) |
357 | __flush_tlb_one_kernel(__cpa_addr(cpa, i)); | |
358 | } | |
359 | ||
360 | static void cpa_flush_array(struct cpa_data *cpa, int cache) | |
361 | { | |
362 | unsigned int i; | |
363 | ||
364 | if (cpa_check_flush_all(cache)) | |
721066df PZ |
365 | return; |
366 | ||
935f5839 PZ |
367 | if (cpa->numpages <= tlb_single_page_flush_ceiling) |
368 | on_each_cpu(__cpa_flush_array, cpa, 1); | |
369 | else | |
370 | flush_tlb_all(); | |
721066df PZ |
371 | |
372 | if (!cache) | |
d75586ad SL |
373 | return; |
374 | ||
d75586ad SL |
375 | /* |
376 | * We only need to flush on one CPU, | |
377 | * clflush is a MESI-coherent instruction that | |
378 | * will cause all other CPUs to flush the same | |
379 | * cachelines: | |
380 | */ | |
935f5839 PZ |
381 | for (i = 0; i < cpa->numpages; i++) { |
382 | unsigned long addr = __cpa_addr(cpa, i); | |
383 | unsigned int level; | |
9ae28475 | 384 | pte_t *pte; |
385 | ||
9ae28475 | 386 | pte = lookup_address(addr, &level); |
d75586ad SL |
387 | |
388 | /* | |
389 | * Only flush present addresses: | |
390 | */ | |
391 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 392 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
393 | } |
394 | } | |
395 | ||
91ee8f5c TG |
396 | static bool overlaps(unsigned long r1_start, unsigned long r1_end, |
397 | unsigned long r2_start, unsigned long r2_end) | |
398 | { | |
399 | return (r1_start <= r2_end && r1_end >= r2_start) || | |
400 | (r2_start <= r1_end && r2_end >= r1_start); | |
401 | } | |
402 | ||
afd7969a | 403 | #ifdef CONFIG_PCI_BIOS |
ed724be6 | 404 | /* |
afd7969a TG |
405 | * The BIOS area between 640k and 1Mb needs to be executable for PCI BIOS |
406 | * based config access (CONFIG_PCI_GOBIOS) support. | |
ed724be6 | 407 | */ |
afd7969a | 408 | #define BIOS_PFN PFN_DOWN(BIOS_BEGIN) |
91ee8f5c | 409 | #define BIOS_PFN_END PFN_DOWN(BIOS_END - 1) |
ed724be6 | 410 | |
91ee8f5c | 411 | static pgprotval_t protect_pci_bios(unsigned long spfn, unsigned long epfn) |
afd7969a | 412 | { |
91ee8f5c | 413 | if (pcibios_enabled && overlaps(spfn, epfn, BIOS_PFN, BIOS_PFN_END)) |
afd7969a TG |
414 | return _PAGE_NX; |
415 | return 0; | |
416 | } | |
417 | #else | |
91ee8f5c | 418 | static pgprotval_t protect_pci_bios(unsigned long spfn, unsigned long epfn) |
afd7969a TG |
419 | { |
420 | return 0; | |
421 | } | |
5bd5a452 | 422 | #endif |
ed724be6 | 423 | |
afd7969a TG |
424 | /* |
425 | * The .rodata section needs to be read-only. Using the pfn catches all | |
426 | * aliases. This also includes __ro_after_init, so do not enforce until | |
427 | * kernel_set_to_readonly is true. | |
428 | */ | |
91ee8f5c | 429 | static pgprotval_t protect_rodata(unsigned long spfn, unsigned long epfn) |
afd7969a | 430 | { |
91ee8f5c TG |
431 | unsigned long epfn_ro, spfn_ro = PFN_DOWN(__pa_symbol(__start_rodata)); |
432 | ||
433 | /* | |
434 | * Note: __end_rodata is at page aligned and not inclusive, so | |
435 | * subtract 1 to get the last enforced PFN in the rodata area. | |
436 | */ | |
437 | epfn_ro = PFN_DOWN(__pa_symbol(__end_rodata)) - 1; | |
cc0f21bb | 438 | |
91ee8f5c | 439 | if (kernel_set_to_readonly && overlaps(spfn, epfn, spfn_ro, epfn_ro)) |
afd7969a TG |
440 | return _PAGE_RW; |
441 | return 0; | |
442 | } | |
443 | ||
444 | /* | |
445 | * Protect kernel text against becoming non executable by forbidding | |
446 | * _PAGE_NX. This protects only the high kernel mapping (_text -> _etext) | |
447 | * out of which the kernel actually executes. Do not protect the low | |
448 | * mapping. | |
449 | * | |
450 | * This does not cover __inittext since that is gone after boot. | |
451 | */ | |
91ee8f5c | 452 | static pgprotval_t protect_kernel_text(unsigned long start, unsigned long end) |
afd7969a | 453 | { |
91ee8f5c TG |
454 | unsigned long t_end = (unsigned long)_etext - 1; |
455 | unsigned long t_start = (unsigned long)_text; | |
456 | ||
457 | if (overlaps(start, end, t_start, t_end)) | |
afd7969a TG |
458 | return _PAGE_NX; |
459 | return 0; | |
460 | } | |
ed724be6 | 461 | |
9ccaf77c | 462 | #if defined(CONFIG_X86_64) |
afd7969a TG |
463 | /* |
464 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), | |
465 | * kernel text mappings for the large page aligned text, rodata sections | |
466 | * will be always read-only. For the kernel identity mappings covering the | |
467 | * holes caused by this alignment can be anything that user asks. | |
468 | * | |
469 | * This will preserve the large page mappings for kernel text/data at no | |
470 | * extra cost. | |
471 | */ | |
91ee8f5c TG |
472 | static pgprotval_t protect_kernel_text_ro(unsigned long start, |
473 | unsigned long end) | |
afd7969a | 474 | { |
91ee8f5c TG |
475 | unsigned long t_end = (unsigned long)__end_rodata_hpage_align - 1; |
476 | unsigned long t_start = (unsigned long)_text; | |
afd7969a TG |
477 | unsigned int level; |
478 | ||
91ee8f5c | 479 | if (!kernel_set_to_readonly || !overlaps(start, end, t_start, t_end)) |
afd7969a | 480 | return 0; |
74e08179 | 481 | /* |
afd7969a TG |
482 | * Don't enforce the !RW mapping for the kernel text mapping, if |
483 | * the current mapping is already using small page mapping. No | |
484 | * need to work hard to preserve large page mappings in this case. | |
74e08179 | 485 | * |
afd7969a TG |
486 | * This also fixes the Linux Xen paravirt guest boot failure caused |
487 | * by unexpected read-only mappings for kernel identity | |
488 | * mappings. In this paravirt guest case, the kernel text mapping | |
489 | * and the kernel identity mapping share the same page-table pages, | |
490 | * so the protections for kernel text and identity mappings have to | |
491 | * be the same. | |
74e08179 | 492 | */ |
91ee8f5c | 493 | if (lookup_address(start, &level) && (level != PG_LEVEL_4K)) |
afd7969a TG |
494 | return _PAGE_RW; |
495 | return 0; | |
496 | } | |
497 | #else | |
91ee8f5c TG |
498 | static pgprotval_t protect_kernel_text_ro(unsigned long start, |
499 | unsigned long end) | |
afd7969a TG |
500 | { |
501 | return 0; | |
502 | } | |
74e08179 SS |
503 | #endif |
504 | ||
4046460b TG |
505 | static inline bool conflicts(pgprot_t prot, pgprotval_t val) |
506 | { | |
507 | return (pgprot_val(prot) & ~val) != pgprot_val(prot); | |
508 | } | |
509 | ||
510 | static inline void check_conflict(int warnlvl, pgprot_t prot, pgprotval_t val, | |
511 | unsigned long start, unsigned long end, | |
512 | unsigned long pfn, const char *txt) | |
513 | { | |
514 | static const char *lvltxt[] = { | |
f61c5ba2 | 515 | [CPA_CONFLICT] = "conflict", |
4046460b TG |
516 | [CPA_PROTECT] = "protect", |
517 | [CPA_DETECT] = "detect", | |
518 | }; | |
519 | ||
520 | if (warnlvl > cpa_warn_level || !conflicts(prot, val)) | |
521 | return; | |
522 | ||
523 | pr_warn("CPA %8s %10s: 0x%016lx - 0x%016lx PFN %lx req %016llx prevent %016llx\n", | |
524 | lvltxt[warnlvl], txt, start, end, pfn, (unsigned long long)pgprot_val(prot), | |
525 | (unsigned long long)val); | |
526 | } | |
527 | ||
afd7969a TG |
528 | /* |
529 | * Certain areas of memory on x86 require very specific protection flags, | |
530 | * for example the BIOS area or kernel text. Callers don't always get this | |
531 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
532 | * checks and fixes these known static required protection bits. | |
533 | */ | |
91ee8f5c | 534 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long start, |
4046460b TG |
535 | unsigned long pfn, unsigned long npg, |
536 | int warnlvl) | |
afd7969a | 537 | { |
4046460b | 538 | pgprotval_t forbidden, res; |
91ee8f5c | 539 | unsigned long end; |
afd7969a | 540 | |
69c31e69 TG |
541 | /* |
542 | * There is no point in checking RW/NX conflicts when the requested | |
543 | * mapping is setting the page !PRESENT. | |
544 | */ | |
545 | if (!(pgprot_val(prot) & _PAGE_PRESENT)) | |
546 | return prot; | |
547 | ||
afd7969a | 548 | /* Operate on the virtual address */ |
91ee8f5c | 549 | end = start + npg * PAGE_SIZE - 1; |
4046460b TG |
550 | |
551 | res = protect_kernel_text(start, end); | |
552 | check_conflict(warnlvl, prot, res, start, end, pfn, "Text NX"); | |
553 | forbidden = res; | |
554 | ||
555 | res = protect_kernel_text_ro(start, end); | |
556 | check_conflict(warnlvl, prot, res, start, end, pfn, "Text RO"); | |
557 | forbidden |= res; | |
afd7969a TG |
558 | |
559 | /* Check the PFN directly */ | |
4046460b TG |
560 | res = protect_pci_bios(pfn, pfn + npg - 1); |
561 | check_conflict(warnlvl, prot, res, start, end, pfn, "PCIBIOS NX"); | |
562 | forbidden |= res; | |
563 | ||
564 | res = protect_rodata(pfn, pfn + npg - 1); | |
565 | check_conflict(warnlvl, prot, res, start, end, pfn, "Rodata RO"); | |
566 | forbidden |= res; | |
687c4825 | 567 | |
afd7969a | 568 | return __pgprot(pgprot_val(prot) & ~forbidden); |
687c4825 IM |
569 | } |
570 | ||
426e34cc MF |
571 | /* |
572 | * Lookup the page table entry for a virtual address in a specific pgd. | |
573 | * Return a pointer to the entry and the level of the mapping. | |
574 | */ | |
575 | pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, | |
576 | unsigned int *level) | |
9f4c815c | 577 | { |
45478336 | 578 | p4d_t *p4d; |
1da177e4 LT |
579 | pud_t *pud; |
580 | pmd_t *pmd; | |
9f4c815c | 581 | |
30551bb3 TG |
582 | *level = PG_LEVEL_NONE; |
583 | ||
1da177e4 LT |
584 | if (pgd_none(*pgd)) |
585 | return NULL; | |
9df84993 | 586 | |
45478336 KS |
587 | p4d = p4d_offset(pgd, address); |
588 | if (p4d_none(*p4d)) | |
589 | return NULL; | |
590 | ||
591 | *level = PG_LEVEL_512G; | |
592 | if (p4d_large(*p4d) || !p4d_present(*p4d)) | |
593 | return (pte_t *)p4d; | |
594 | ||
595 | pud = pud_offset(p4d, address); | |
1da177e4 LT |
596 | if (pud_none(*pud)) |
597 | return NULL; | |
c2f71ee2 AK |
598 | |
599 | *level = PG_LEVEL_1G; | |
600 | if (pud_large(*pud) || !pud_present(*pud)) | |
601 | return (pte_t *)pud; | |
602 | ||
1da177e4 LT |
603 | pmd = pmd_offset(pud, address); |
604 | if (pmd_none(*pmd)) | |
605 | return NULL; | |
30551bb3 TG |
606 | |
607 | *level = PG_LEVEL_2M; | |
9a14aefc | 608 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 609 | return (pte_t *)pmd; |
1da177e4 | 610 | |
30551bb3 | 611 | *level = PG_LEVEL_4K; |
9df84993 | 612 | |
9f4c815c IM |
613 | return pte_offset_kernel(pmd, address); |
614 | } | |
0fd64c23 BP |
615 | |
616 | /* | |
617 | * Lookup the page table entry for a virtual address. Return a pointer | |
618 | * to the entry and the level of the mapping. | |
619 | * | |
620 | * Note: We return pud and pmd either when the entry is marked large | |
621 | * or when the present bit is not set. Otherwise we would return a | |
622 | * pointer to a nonexisting mapping. | |
623 | */ | |
624 | pte_t *lookup_address(unsigned long address, unsigned int *level) | |
625 | { | |
8679de09 | 626 | return lookup_address_in_pgd(pgd_offset_k(address), address, level); |
0fd64c23 | 627 | } |
75bb8835 | 628 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 629 | |
0fd64c23 BP |
630 | static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address, |
631 | unsigned int *level) | |
632 | { | |
8679de09 | 633 | if (cpa->pgd) |
426e34cc | 634 | return lookup_address_in_pgd(cpa->pgd + pgd_index(address), |
0fd64c23 BP |
635 | address, level); |
636 | ||
8679de09 | 637 | return lookup_address(address, level); |
0fd64c23 BP |
638 | } |
639 | ||
792230c3 JG |
640 | /* |
641 | * Lookup the PMD entry for a virtual address. Return a pointer to the entry | |
642 | * or NULL if not present. | |
643 | */ | |
644 | pmd_t *lookup_pmd_address(unsigned long address) | |
645 | { | |
646 | pgd_t *pgd; | |
45478336 | 647 | p4d_t *p4d; |
792230c3 JG |
648 | pud_t *pud; |
649 | ||
650 | pgd = pgd_offset_k(address); | |
651 | if (pgd_none(*pgd)) | |
652 | return NULL; | |
653 | ||
45478336 KS |
654 | p4d = p4d_offset(pgd, address); |
655 | if (p4d_none(*p4d) || p4d_large(*p4d) || !p4d_present(*p4d)) | |
656 | return NULL; | |
657 | ||
658 | pud = pud_offset(p4d, address); | |
792230c3 JG |
659 | if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud)) |
660 | return NULL; | |
661 | ||
662 | return pmd_offset(pud, address); | |
663 | } | |
664 | ||
d7656534 DH |
665 | /* |
666 | * This is necessary because __pa() does not work on some | |
667 | * kinds of memory, like vmalloc() or the alloc_remap() | |
668 | * areas on 32-bit NUMA systems. The percpu areas can | |
669 | * end up in this kind of memory, for instance. | |
670 | * | |
671 | * This could be optimized, but it is only intended to be | |
672 | * used at inititalization time, and keeping it | |
673 | * unoptimized should increase the testing coverage for | |
674 | * the more obscure platforms. | |
675 | */ | |
676 | phys_addr_t slow_virt_to_phys(void *__virt_addr) | |
677 | { | |
678 | unsigned long virt_addr = (unsigned long)__virt_addr; | |
bf70e551 DC |
679 | phys_addr_t phys_addr; |
680 | unsigned long offset; | |
d7656534 | 681 | enum pg_level level; |
d7656534 DH |
682 | pte_t *pte; |
683 | ||
684 | pte = lookup_address(virt_addr, &level); | |
685 | BUG_ON(!pte); | |
34437e67 | 686 | |
bf70e551 DC |
687 | /* |
688 | * pXX_pfn() returns unsigned long, which must be cast to phys_addr_t | |
689 | * before being left-shifted PAGE_SHIFT bits -- this trick is to | |
690 | * make 32-PAE kernel work correctly. | |
691 | */ | |
34437e67 TK |
692 | switch (level) { |
693 | case PG_LEVEL_1G: | |
bf70e551 | 694 | phys_addr = (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
695 | offset = virt_addr & ~PUD_PAGE_MASK; |
696 | break; | |
697 | case PG_LEVEL_2M: | |
bf70e551 | 698 | phys_addr = (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
699 | offset = virt_addr & ~PMD_PAGE_MASK; |
700 | break; | |
701 | default: | |
bf70e551 | 702 | phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT; |
34437e67 TK |
703 | offset = virt_addr & ~PAGE_MASK; |
704 | } | |
705 | ||
706 | return (phys_addr_t)(phys_addr | offset); | |
d7656534 DH |
707 | } |
708 | EXPORT_SYMBOL_GPL(slow_virt_to_phys); | |
709 | ||
9df84993 IM |
710 | /* |
711 | * Set the new pmd in all the pgds we know about: | |
712 | */ | |
9a3dc780 | 713 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 714 | { |
9f4c815c IM |
715 | /* change init_mm */ |
716 | set_pte_atomic(kpte, pte); | |
44af6c41 | 717 | #ifdef CONFIG_X86_32 |
e4b71dcf | 718 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
719 | struct page *page; |
720 | ||
e3ed910d | 721 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 | 722 | pgd_t *pgd; |
45478336 | 723 | p4d_t *p4d; |
44af6c41 IM |
724 | pud_t *pud; |
725 | pmd_t *pmd; | |
726 | ||
727 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
45478336 KS |
728 | p4d = p4d_offset(pgd, address); |
729 | pud = pud_offset(p4d, address); | |
44af6c41 IM |
730 | pmd = pmd_offset(pud, address); |
731 | set_pte_atomic((pte_t *)pmd, pte); | |
732 | } | |
1da177e4 | 733 | } |
44af6c41 | 734 | #endif |
1da177e4 LT |
735 | } |
736 | ||
d1440b23 DH |
737 | static pgprot_t pgprot_clear_protnone_bits(pgprot_t prot) |
738 | { | |
739 | /* | |
740 | * _PAGE_GLOBAL means "global page" for present PTEs. | |
741 | * But, it is also used to indicate _PAGE_PROTNONE | |
742 | * for non-present PTEs. | |
743 | * | |
744 | * This ensures that a _PAGE_GLOBAL PTE going from | |
745 | * present to non-present is not confused as | |
746 | * _PAGE_PROTNONE. | |
747 | */ | |
748 | if (!(pgprot_val(prot) & _PAGE_PRESENT)) | |
749 | pgprot_val(prot) &= ~_PAGE_GLOBAL; | |
750 | ||
751 | return prot; | |
752 | } | |
753 | ||
8679de09 TG |
754 | static int __should_split_large_page(pte_t *kpte, unsigned long address, |
755 | struct cpa_data *cpa) | |
65e074df | 756 | { |
585948f4 | 757 | unsigned long numpages, pmask, psize, lpaddr, pfn, old_pfn; |
f61c5ba2 | 758 | pgprot_t old_prot, new_prot, req_prot, chk_prot; |
8679de09 | 759 | pte_t new_pte, old_pte, *tmp; |
f3c4fbb6 | 760 | enum pg_level level; |
65e074df | 761 | |
65e074df TG |
762 | /* |
763 | * Check for races, another CPU might have split this page | |
764 | * up already: | |
765 | */ | |
82f0712c | 766 | tmp = _lookup_address_cpa(cpa, address, &level); |
65e074df | 767 | if (tmp != kpte) |
8679de09 | 768 | return 1; |
65e074df TG |
769 | |
770 | switch (level) { | |
771 | case PG_LEVEL_2M: | |
3a19109e TK |
772 | old_prot = pmd_pgprot(*(pmd_t *)kpte); |
773 | old_pfn = pmd_pfn(*(pmd_t *)kpte); | |
5c280cf6 | 774 | cpa_inc_2m_checked(); |
3a19109e | 775 | break; |
65e074df | 776 | case PG_LEVEL_1G: |
3a19109e TK |
777 | old_prot = pud_pgprot(*(pud_t *)kpte); |
778 | old_pfn = pud_pfn(*(pud_t *)kpte); | |
5c280cf6 | 779 | cpa_inc_1g_checked(); |
f3c4fbb6 | 780 | break; |
65e074df | 781 | default: |
8679de09 | 782 | return -EINVAL; |
65e074df TG |
783 | } |
784 | ||
3a19109e TK |
785 | psize = page_level_size(level); |
786 | pmask = page_level_mask(level); | |
787 | ||
65e074df TG |
788 | /* |
789 | * Calculate the number of pages, which fit into this large | |
790 | * page starting at address: | |
791 | */ | |
8679de09 TG |
792 | lpaddr = (address + psize) & pmask; |
793 | numpages = (lpaddr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
794 | if (numpages < cpa->numpages) |
795 | cpa->numpages = numpages; | |
65e074df TG |
796 | |
797 | /* | |
798 | * We are safe now. Check whether the new pgprot is the same: | |
f5b2831d JG |
799 | * Convert protection attributes to 4k-format, as cpa->mask* are set |
800 | * up accordingly. | |
65e074df TG |
801 | */ |
802 | old_pte = *kpte; | |
606c7193 | 803 | /* Clear PSE (aka _PAGE_PAT) and move PAT bit to correct position */ |
55696b1f | 804 | req_prot = pgprot_large_2_4k(old_prot); |
65e074df | 805 | |
64edc8ed | 806 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
807 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 | 808 | |
f5b2831d JG |
809 | /* |
810 | * req_prot is in format of 4k pages. It must be converted to large | |
811 | * page format: the caching mode includes the PAT bit located at | |
812 | * different bit positions in the two formats. | |
813 | */ | |
814 | req_prot = pgprot_4k_2_large(req_prot); | |
d1440b23 | 815 | req_prot = pgprot_clear_protnone_bits(req_prot); |
f76cfa3c | 816 | if (pgprot_val(req_prot) & _PAGE_PRESENT) |
d1440b23 | 817 | pgprot_val(req_prot) |= _PAGE_PSE; |
a8aed3e0 | 818 | |
c31c7d48 | 819 | /* |
8679de09 TG |
820 | * old_pfn points to the large page base pfn. So we need to add the |
821 | * offset of the virtual address: | |
c31c7d48 | 822 | */ |
3a19109e | 823 | pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT); |
c31c7d48 TG |
824 | cpa->pfn = pfn; |
825 | ||
8679de09 TG |
826 | /* |
827 | * Calculate the large page base address and the number of 4K pages | |
828 | * in the large page | |
829 | */ | |
830 | lpaddr = address & pmask; | |
831 | numpages = psize >> PAGE_SHIFT; | |
65e074df | 832 | |
f61c5ba2 TG |
833 | /* |
834 | * Sanity check that the existing mapping is correct versus the static | |
835 | * protections. static_protections() guards against !PRESENT, so no | |
836 | * extra conditional required here. | |
837 | */ | |
838 | chk_prot = static_protections(old_prot, lpaddr, old_pfn, numpages, | |
839 | CPA_CONFLICT); | |
840 | ||
841 | if (WARN_ON_ONCE(pgprot_val(chk_prot) != pgprot_val(old_prot))) { | |
842 | /* | |
843 | * Split the large page and tell the split code to | |
844 | * enforce static protections. | |
845 | */ | |
846 | cpa->force_static_prot = 1; | |
847 | return 1; | |
848 | } | |
849 | ||
1c4b406e TG |
850 | /* |
851 | * Optimization: If the requested pgprot is the same as the current | |
852 | * pgprot, then the large page can be preserved and no updates are | |
853 | * required independent of alignment and length of the requested | |
854 | * range. The above already established that the current pgprot is | |
855 | * correct, which in consequence makes the requested pgprot correct | |
856 | * as well if it is the same. The static protection scan below will | |
857 | * not come to a different conclusion. | |
858 | */ | |
859 | if (pgprot_val(req_prot) == pgprot_val(old_prot)) { | |
860 | cpa_inc_lp_sameprot(level); | |
861 | return 0; | |
862 | } | |
863 | ||
fac84939 | 864 | /* |
585948f4 | 865 | * If the requested range does not cover the full page, split it up |
9cc9f17a | 866 | */ |
585948f4 TG |
867 | if (address != lpaddr || cpa->numpages != numpages) |
868 | return 1; | |
9cc9f17a TG |
869 | |
870 | /* | |
585948f4 TG |
871 | * Check whether the requested pgprot is conflicting with a static |
872 | * protection requirement in the large page. | |
fac84939 | 873 | */ |
585948f4 TG |
874 | new_prot = static_protections(req_prot, lpaddr, old_pfn, numpages, |
875 | CPA_DETECT); | |
65e074df TG |
876 | |
877 | /* | |
585948f4 TG |
878 | * If there is a conflict, split the large page. |
879 | * | |
880 | * There used to be a 4k wise evaluation trying really hard to | |
881 | * preserve the large pages, but experimentation has shown, that this | |
882 | * does not help at all. There might be corner cases which would | |
883 | * preserve one large page occasionally, but it's really not worth the | |
884 | * extra code and cycles for the common case. | |
65e074df | 885 | */ |
585948f4 | 886 | if (pgprot_val(req_prot) != pgprot_val(new_prot)) |
8679de09 TG |
887 | return 1; |
888 | ||
889 | /* All checks passed. Update the large page mapping. */ | |
890 | new_pte = pfn_pte(old_pfn, new_prot); | |
891 | __set_pmd_pte(kpte, address, new_pte); | |
892 | cpa->flags |= CPA_FLUSHTLB; | |
5c280cf6 | 893 | cpa_inc_lp_preserved(level); |
8679de09 TG |
894 | return 0; |
895 | } | |
896 | ||
897 | static int should_split_large_page(pte_t *kpte, unsigned long address, | |
898 | struct cpa_data *cpa) | |
899 | { | |
900 | int do_split; | |
901 | ||
902 | if (cpa->force_split) | |
903 | return 1; | |
65e074df | 904 | |
8679de09 TG |
905 | spin_lock(&pgd_lock); |
906 | do_split = __should_split_large_page(kpte, address, cpa); | |
a79e53d8 | 907 | spin_unlock(&pgd_lock); |
9df84993 | 908 | |
beaff633 | 909 | return do_split; |
65e074df TG |
910 | } |
911 | ||
f61c5ba2 TG |
912 | static void split_set_pte(struct cpa_data *cpa, pte_t *pte, unsigned long pfn, |
913 | pgprot_t ref_prot, unsigned long address, | |
914 | unsigned long size) | |
915 | { | |
916 | unsigned int npg = PFN_DOWN(size); | |
917 | pgprot_t prot; | |
918 | ||
919 | /* | |
920 | * If should_split_large_page() discovered an inconsistent mapping, | |
921 | * remove the invalid protection in the split mapping. | |
922 | */ | |
923 | if (!cpa->force_static_prot) | |
924 | goto set; | |
925 | ||
926 | prot = static_protections(ref_prot, address, pfn, npg, CPA_PROTECT); | |
927 | ||
928 | if (pgprot_val(prot) == pgprot_val(ref_prot)) | |
929 | goto set; | |
930 | ||
931 | /* | |
932 | * If this is splitting a PMD, fix it up. PUD splits cannot be | |
933 | * fixed trivially as that would require to rescan the newly | |
934 | * installed PMD mappings after returning from split_large_page() | |
935 | * so an eventual further split can allocate the necessary PTE | |
936 | * pages. Warn for now and revisit it in case this actually | |
937 | * happens. | |
938 | */ | |
939 | if (size == PAGE_SIZE) | |
940 | ref_prot = prot; | |
941 | else | |
942 | pr_warn_once("CPA: Cannot fixup static protections for PUD split\n"); | |
943 | set: | |
944 | set_pte(pte, pfn_pte(pfn, ref_prot)); | |
945 | } | |
946 | ||
5952886b | 947 | static int |
82f0712c BP |
948 | __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address, |
949 | struct page *base) | |
bb5c2dbd | 950 | { |
f61c5ba2 | 951 | unsigned long lpaddr, lpinc, ref_pfn, pfn, pfninc = 1; |
5952886b | 952 | pte_t *pbase = (pte_t *)page_address(base); |
9df84993 | 953 | unsigned int i, level; |
9df84993 | 954 | pgprot_t ref_prot; |
f61c5ba2 | 955 | pte_t *tmp; |
bb5c2dbd | 956 | |
a79e53d8 | 957 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
958 | /* |
959 | * Check for races, another CPU might have split this page | |
960 | * up for us already: | |
961 | */ | |
82f0712c | 962 | tmp = _lookup_address_cpa(cpa, address, &level); |
ae9aae9e WC |
963 | if (tmp != kpte) { |
964 | spin_unlock(&pgd_lock); | |
965 | return 1; | |
966 | } | |
bb5c2dbd | 967 | |
6944a9c8 | 968 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
f5b2831d | 969 | |
d551aaa2 TK |
970 | switch (level) { |
971 | case PG_LEVEL_2M: | |
972 | ref_prot = pmd_pgprot(*(pmd_t *)kpte); | |
606c7193 DH |
973 | /* |
974 | * Clear PSE (aka _PAGE_PAT) and move | |
975 | * PAT bit to correct position. | |
976 | */ | |
f5b2831d | 977 | ref_prot = pgprot_large_2_4k(ref_prot); |
d551aaa2 | 978 | ref_pfn = pmd_pfn(*(pmd_t *)kpte); |
f61c5ba2 TG |
979 | lpaddr = address & PMD_MASK; |
980 | lpinc = PAGE_SIZE; | |
d551aaa2 | 981 | break; |
bb5c2dbd | 982 | |
d551aaa2 TK |
983 | case PG_LEVEL_1G: |
984 | ref_prot = pud_pgprot(*(pud_t *)kpte); | |
985 | ref_pfn = pud_pfn(*(pud_t *)kpte); | |
f07333fd | 986 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; |
f61c5ba2 TG |
987 | lpaddr = address & PUD_MASK; |
988 | lpinc = PMD_SIZE; | |
a8aed3e0 | 989 | /* |
d551aaa2 | 990 | * Clear the PSE flags if the PRESENT flag is not set |
a8aed3e0 AA |
991 | * otherwise pmd_present/pmd_huge will return true |
992 | * even on a non present pmd. | |
993 | */ | |
d551aaa2 | 994 | if (!(pgprot_val(ref_prot) & _PAGE_PRESENT)) |
a8aed3e0 | 995 | pgprot_val(ref_prot) &= ~_PAGE_PSE; |
d551aaa2 TK |
996 | break; |
997 | ||
998 | default: | |
999 | spin_unlock(&pgd_lock); | |
1000 | return 1; | |
f07333fd | 1001 | } |
f07333fd | 1002 | |
d1440b23 | 1003 | ref_prot = pgprot_clear_protnone_bits(ref_prot); |
a8aed3e0 | 1004 | |
63c1dcf4 TG |
1005 | /* |
1006 | * Get the target pfn from the original entry: | |
1007 | */ | |
d551aaa2 | 1008 | pfn = ref_pfn; |
f61c5ba2 TG |
1009 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc, lpaddr += lpinc) |
1010 | split_set_pte(cpa, pbase + i, pfn, ref_prot, lpaddr, lpinc); | |
bb5c2dbd | 1011 | |
2c66e24d SP |
1012 | if (virt_addr_valid(address)) { |
1013 | unsigned long pfn = PFN_DOWN(__pa(address)); | |
1014 | ||
1015 | if (pfn_range_is_mapped(pfn, pfn + 1)) | |
1016 | split_page_count(level); | |
1017 | } | |
f361a450 | 1018 | |
bb5c2dbd | 1019 | /* |
07a66d7c | 1020 | * Install the new, split up pagetable. |
4c881ca1 | 1021 | * |
07a66d7c IM |
1022 | * We use the standard kernel pagetable protections for the new |
1023 | * pagetable protections, the actual ptes set above control the | |
1024 | * primary protection behavior: | |
bb5c2dbd | 1025 | */ |
07a66d7c | 1026 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
1027 | |
1028 | /* | |
c0a759ab PZ |
1029 | * Do a global flush tlb after splitting the large page |
1030 | * and before we do the actual change page attribute in the PTE. | |
211b3d03 | 1031 | * |
c0a759ab PZ |
1032 | * Without this, we violate the TLB application note, that says: |
1033 | * "The TLBs may contain both ordinary and large-page | |
1034 | * translations for a 4-KByte range of linear addresses. This | |
1035 | * may occur if software modifies the paging structures so that | |
1036 | * the page size used for the address range changes. If the two | |
1037 | * translations differ with respect to page frame or attributes | |
1038 | * (e.g., permissions), processor behavior is undefined and may | |
1039 | * be implementation-specific." | |
1040 | * | |
1041 | * We do this global tlb flush inside the cpa_lock, so that we | |
1042 | * don't allow any other cpu, with stale tlb entries change the | |
1043 | * page attribute in parallel, that also falls into the | |
1044 | * just split large page entry. | |
211b3d03 | 1045 | */ |
c0a759ab | 1046 | flush_tlb_all(); |
ae9aae9e | 1047 | spin_unlock(&pgd_lock); |
211b3d03 | 1048 | |
ae9aae9e WC |
1049 | return 0; |
1050 | } | |
bb5c2dbd | 1051 | |
82f0712c BP |
1052 | static int split_large_page(struct cpa_data *cpa, pte_t *kpte, |
1053 | unsigned long address) | |
ae9aae9e | 1054 | { |
ae9aae9e WC |
1055 | struct page *base; |
1056 | ||
288cf3c6 | 1057 | if (!debug_pagealloc_enabled()) |
ae9aae9e | 1058 | spin_unlock(&cpa_lock); |
75f296d9 | 1059 | base = alloc_pages(GFP_KERNEL, 0); |
288cf3c6 | 1060 | if (!debug_pagealloc_enabled()) |
ae9aae9e WC |
1061 | spin_lock(&cpa_lock); |
1062 | if (!base) | |
1063 | return -ENOMEM; | |
1064 | ||
82f0712c | 1065 | if (__split_large_page(cpa, kpte, address, base)) |
8311eb84 | 1066 | __free_page(base); |
bb5c2dbd | 1067 | |
bb5c2dbd IM |
1068 | return 0; |
1069 | } | |
1070 | ||
52a628fb BP |
1071 | static bool try_to_free_pte_page(pte_t *pte) |
1072 | { | |
1073 | int i; | |
1074 | ||
1075 | for (i = 0; i < PTRS_PER_PTE; i++) | |
1076 | if (!pte_none(pte[i])) | |
1077 | return false; | |
1078 | ||
1079 | free_page((unsigned long)pte); | |
1080 | return true; | |
1081 | } | |
1082 | ||
1083 | static bool try_to_free_pmd_page(pmd_t *pmd) | |
1084 | { | |
1085 | int i; | |
1086 | ||
1087 | for (i = 0; i < PTRS_PER_PMD; i++) | |
1088 | if (!pmd_none(pmd[i])) | |
1089 | return false; | |
1090 | ||
1091 | free_page((unsigned long)pmd); | |
1092 | return true; | |
1093 | } | |
1094 | ||
1095 | static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end) | |
1096 | { | |
1097 | pte_t *pte = pte_offset_kernel(pmd, start); | |
1098 | ||
1099 | while (start < end) { | |
1100 | set_pte(pte, __pte(0)); | |
1101 | ||
1102 | start += PAGE_SIZE; | |
1103 | pte++; | |
1104 | } | |
1105 | ||
1106 | if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) { | |
1107 | pmd_clear(pmd); | |
1108 | return true; | |
1109 | } | |
1110 | return false; | |
1111 | } | |
1112 | ||
1113 | static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd, | |
1114 | unsigned long start, unsigned long end) | |
1115 | { | |
1116 | if (unmap_pte_range(pmd, start, end)) | |
1117 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
1118 | pud_clear(pud); | |
1119 | } | |
1120 | ||
1121 | static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end) | |
1122 | { | |
1123 | pmd_t *pmd = pmd_offset(pud, start); | |
1124 | ||
1125 | /* | |
1126 | * Not on a 2MB page boundary? | |
1127 | */ | |
1128 | if (start & (PMD_SIZE - 1)) { | |
1129 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
1130 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
1131 | ||
1132 | __unmap_pmd_range(pud, pmd, start, pre_end); | |
1133 | ||
1134 | start = pre_end; | |
1135 | pmd++; | |
1136 | } | |
1137 | ||
1138 | /* | |
1139 | * Try to unmap in 2M chunks. | |
1140 | */ | |
1141 | while (end - start >= PMD_SIZE) { | |
1142 | if (pmd_large(*pmd)) | |
1143 | pmd_clear(pmd); | |
1144 | else | |
1145 | __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE); | |
1146 | ||
1147 | start += PMD_SIZE; | |
1148 | pmd++; | |
1149 | } | |
1150 | ||
1151 | /* | |
1152 | * 4K leftovers? | |
1153 | */ | |
1154 | if (start < end) | |
1155 | return __unmap_pmd_range(pud, pmd, start, end); | |
1156 | ||
1157 | /* | |
1158 | * Try again to free the PMD page if haven't succeeded above. | |
1159 | */ | |
1160 | if (!pud_none(*pud)) | |
1161 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
1162 | pud_clear(pud); | |
1163 | } | |
0bb8aeee | 1164 | |
45478336 | 1165 | static void unmap_pud_range(p4d_t *p4d, unsigned long start, unsigned long end) |
0bb8aeee | 1166 | { |
45478336 | 1167 | pud_t *pud = pud_offset(p4d, start); |
0bb8aeee BP |
1168 | |
1169 | /* | |
1170 | * Not on a GB page boundary? | |
1171 | */ | |
1172 | if (start & (PUD_SIZE - 1)) { | |
1173 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
1174 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
1175 | ||
1176 | unmap_pmd_range(pud, start, pre_end); | |
1177 | ||
1178 | start = pre_end; | |
1179 | pud++; | |
1180 | } | |
1181 | ||
1182 | /* | |
1183 | * Try to unmap in 1G chunks? | |
1184 | */ | |
1185 | while (end - start >= PUD_SIZE) { | |
1186 | ||
1187 | if (pud_large(*pud)) | |
1188 | pud_clear(pud); | |
1189 | else | |
1190 | unmap_pmd_range(pud, start, start + PUD_SIZE); | |
1191 | ||
1192 | start += PUD_SIZE; | |
1193 | pud++; | |
1194 | } | |
1195 | ||
1196 | /* | |
1197 | * 2M leftovers? | |
1198 | */ | |
1199 | if (start < end) | |
1200 | unmap_pmd_range(pud, start, end); | |
1201 | ||
1202 | /* | |
1203 | * No need to try to free the PUD page because we'll free it in | |
1204 | * populate_pgd's error path | |
1205 | */ | |
1206 | } | |
1207 | ||
f900a4b8 BP |
1208 | static int alloc_pte_page(pmd_t *pmd) |
1209 | { | |
75f296d9 | 1210 | pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL); |
f900a4b8 BP |
1211 | if (!pte) |
1212 | return -1; | |
1213 | ||
1214 | set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE)); | |
1215 | return 0; | |
1216 | } | |
1217 | ||
4b23538d BP |
1218 | static int alloc_pmd_page(pud_t *pud) |
1219 | { | |
75f296d9 | 1220 | pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL); |
4b23538d BP |
1221 | if (!pmd) |
1222 | return -1; | |
1223 | ||
1224 | set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); | |
1225 | return 0; | |
1226 | } | |
1227 | ||
c6b6f363 BP |
1228 | static void populate_pte(struct cpa_data *cpa, |
1229 | unsigned long start, unsigned long end, | |
1230 | unsigned num_pages, pmd_t *pmd, pgprot_t pgprot) | |
1231 | { | |
1232 | pte_t *pte; | |
1233 | ||
1234 | pte = pte_offset_kernel(pmd, start); | |
1235 | ||
d1440b23 | 1236 | pgprot = pgprot_clear_protnone_bits(pgprot); |
c6b6f363 | 1237 | |
c6b6f363 | 1238 | while (num_pages-- && start < end) { |
edc3b912 | 1239 | set_pte(pte, pfn_pte(cpa->pfn, pgprot)); |
c6b6f363 BP |
1240 | |
1241 | start += PAGE_SIZE; | |
edc3b912 | 1242 | cpa->pfn++; |
c6b6f363 BP |
1243 | pte++; |
1244 | } | |
1245 | } | |
f900a4b8 | 1246 | |
e535ec08 MF |
1247 | static long populate_pmd(struct cpa_data *cpa, |
1248 | unsigned long start, unsigned long end, | |
1249 | unsigned num_pages, pud_t *pud, pgprot_t pgprot) | |
f900a4b8 | 1250 | { |
e535ec08 | 1251 | long cur_pages = 0; |
f900a4b8 | 1252 | pmd_t *pmd; |
f5b2831d | 1253 | pgprot_t pmd_pgprot; |
f900a4b8 BP |
1254 | |
1255 | /* | |
1256 | * Not on a 2M boundary? | |
1257 | */ | |
1258 | if (start & (PMD_SIZE - 1)) { | |
1259 | unsigned long pre_end = start + (num_pages << PAGE_SHIFT); | |
1260 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
1261 | ||
1262 | pre_end = min_t(unsigned long, pre_end, next_page); | |
1263 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
1264 | cur_pages = min_t(unsigned int, num_pages, cur_pages); | |
1265 | ||
1266 | /* | |
1267 | * Need a PTE page? | |
1268 | */ | |
1269 | pmd = pmd_offset(pud, start); | |
1270 | if (pmd_none(*pmd)) | |
1271 | if (alloc_pte_page(pmd)) | |
1272 | return -1; | |
1273 | ||
1274 | populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot); | |
1275 | ||
1276 | start = pre_end; | |
1277 | } | |
1278 | ||
1279 | /* | |
1280 | * We mapped them all? | |
1281 | */ | |
1282 | if (num_pages == cur_pages) | |
1283 | return cur_pages; | |
1284 | ||
f5b2831d JG |
1285 | pmd_pgprot = pgprot_4k_2_large(pgprot); |
1286 | ||
f900a4b8 BP |
1287 | while (end - start >= PMD_SIZE) { |
1288 | ||
1289 | /* | |
1290 | * We cannot use a 1G page so allocate a PMD page if needed. | |
1291 | */ | |
1292 | if (pud_none(*pud)) | |
1293 | if (alloc_pmd_page(pud)) | |
1294 | return -1; | |
1295 | ||
1296 | pmd = pmd_offset(pud, start); | |
1297 | ||
958f79b9 AK |
1298 | set_pmd(pmd, pmd_mkhuge(pfn_pmd(cpa->pfn, |
1299 | canon_pgprot(pmd_pgprot)))); | |
f900a4b8 BP |
1300 | |
1301 | start += PMD_SIZE; | |
edc3b912 | 1302 | cpa->pfn += PMD_SIZE >> PAGE_SHIFT; |
f900a4b8 BP |
1303 | cur_pages += PMD_SIZE >> PAGE_SHIFT; |
1304 | } | |
1305 | ||
1306 | /* | |
1307 | * Map trailing 4K pages. | |
1308 | */ | |
1309 | if (start < end) { | |
1310 | pmd = pmd_offset(pud, start); | |
1311 | if (pmd_none(*pmd)) | |
1312 | if (alloc_pte_page(pmd)) | |
1313 | return -1; | |
1314 | ||
1315 | populate_pte(cpa, start, end, num_pages - cur_pages, | |
1316 | pmd, pgprot); | |
1317 | } | |
1318 | return num_pages; | |
1319 | } | |
4b23538d | 1320 | |
45478336 KS |
1321 | static int populate_pud(struct cpa_data *cpa, unsigned long start, p4d_t *p4d, |
1322 | pgprot_t pgprot) | |
4b23538d BP |
1323 | { |
1324 | pud_t *pud; | |
1325 | unsigned long end; | |
e535ec08 | 1326 | long cur_pages = 0; |
f5b2831d | 1327 | pgprot_t pud_pgprot; |
4b23538d BP |
1328 | |
1329 | end = start + (cpa->numpages << PAGE_SHIFT); | |
1330 | ||
1331 | /* | |
1332 | * Not on a Gb page boundary? => map everything up to it with | |
1333 | * smaller pages. | |
1334 | */ | |
1335 | if (start & (PUD_SIZE - 1)) { | |
1336 | unsigned long pre_end; | |
1337 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
1338 | ||
1339 | pre_end = min_t(unsigned long, end, next_page); | |
1340 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
1341 | cur_pages = min_t(int, (int)cpa->numpages, cur_pages); | |
1342 | ||
45478336 | 1343 | pud = pud_offset(p4d, start); |
4b23538d BP |
1344 | |
1345 | /* | |
1346 | * Need a PMD page? | |
1347 | */ | |
1348 | if (pud_none(*pud)) | |
1349 | if (alloc_pmd_page(pud)) | |
1350 | return -1; | |
1351 | ||
1352 | cur_pages = populate_pmd(cpa, start, pre_end, cur_pages, | |
1353 | pud, pgprot); | |
1354 | if (cur_pages < 0) | |
1355 | return cur_pages; | |
1356 | ||
1357 | start = pre_end; | |
1358 | } | |
1359 | ||
1360 | /* We mapped them all? */ | |
1361 | if (cpa->numpages == cur_pages) | |
1362 | return cur_pages; | |
1363 | ||
45478336 | 1364 | pud = pud_offset(p4d, start); |
f5b2831d | 1365 | pud_pgprot = pgprot_4k_2_large(pgprot); |
4b23538d BP |
1366 | |
1367 | /* | |
1368 | * Map everything starting from the Gb boundary, possibly with 1G pages | |
1369 | */ | |
b8291adc | 1370 | while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) { |
958f79b9 AK |
1371 | set_pud(pud, pud_mkhuge(pfn_pud(cpa->pfn, |
1372 | canon_pgprot(pud_pgprot)))); | |
4b23538d BP |
1373 | |
1374 | start += PUD_SIZE; | |
edc3b912 | 1375 | cpa->pfn += PUD_SIZE >> PAGE_SHIFT; |
4b23538d BP |
1376 | cur_pages += PUD_SIZE >> PAGE_SHIFT; |
1377 | pud++; | |
1378 | } | |
1379 | ||
1380 | /* Map trailing leftover */ | |
1381 | if (start < end) { | |
e535ec08 | 1382 | long tmp; |
4b23538d | 1383 | |
45478336 | 1384 | pud = pud_offset(p4d, start); |
4b23538d BP |
1385 | if (pud_none(*pud)) |
1386 | if (alloc_pmd_page(pud)) | |
1387 | return -1; | |
1388 | ||
1389 | tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages, | |
1390 | pud, pgprot); | |
1391 | if (tmp < 0) | |
1392 | return cur_pages; | |
1393 | ||
1394 | cur_pages += tmp; | |
1395 | } | |
1396 | return cur_pages; | |
1397 | } | |
f3f72966 BP |
1398 | |
1399 | /* | |
1400 | * Restrictions for kernel page table do not necessarily apply when mapping in | |
1401 | * an alternate PGD. | |
1402 | */ | |
1403 | static int populate_pgd(struct cpa_data *cpa, unsigned long addr) | |
1404 | { | |
1405 | pgprot_t pgprot = __pgprot(_KERNPG_TABLE); | |
f3f72966 | 1406 | pud_t *pud = NULL; /* shut up gcc */ |
45478336 | 1407 | p4d_t *p4d; |
42a54772 | 1408 | pgd_t *pgd_entry; |
e535ec08 | 1409 | long ret; |
f3f72966 BP |
1410 | |
1411 | pgd_entry = cpa->pgd + pgd_index(addr); | |
1412 | ||
45478336 | 1413 | if (pgd_none(*pgd_entry)) { |
75f296d9 | 1414 | p4d = (p4d_t *)get_zeroed_page(GFP_KERNEL); |
45478336 KS |
1415 | if (!p4d) |
1416 | return -1; | |
1417 | ||
1418 | set_pgd(pgd_entry, __pgd(__pa(p4d) | _KERNPG_TABLE)); | |
1419 | } | |
1420 | ||
f3f72966 BP |
1421 | /* |
1422 | * Allocate a PUD page and hand it down for mapping. | |
1423 | */ | |
45478336 KS |
1424 | p4d = p4d_offset(pgd_entry, addr); |
1425 | if (p4d_none(*p4d)) { | |
75f296d9 | 1426 | pud = (pud_t *)get_zeroed_page(GFP_KERNEL); |
f3f72966 BP |
1427 | if (!pud) |
1428 | return -1; | |
530dd8d4 | 1429 | |
45478336 | 1430 | set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE)); |
f3f72966 BP |
1431 | } |
1432 | ||
1433 | pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr); | |
1434 | pgprot_val(pgprot) |= pgprot_val(cpa->mask_set); | |
1435 | ||
45478336 | 1436 | ret = populate_pud(cpa, addr, p4d, pgprot); |
0bb8aeee | 1437 | if (ret < 0) { |
55920d31 AL |
1438 | /* |
1439 | * Leave the PUD page in place in case some other CPU or thread | |
1440 | * already found it, but remove any useless entries we just | |
1441 | * added to it. | |
1442 | */ | |
45478336 | 1443 | unmap_pud_range(p4d, addr, |
0bb8aeee | 1444 | addr + (cpa->numpages << PAGE_SHIFT)); |
f3f72966 | 1445 | return ret; |
0bb8aeee | 1446 | } |
42a54772 | 1447 | |
f3f72966 BP |
1448 | cpa->numpages = ret; |
1449 | return 0; | |
1450 | } | |
1451 | ||
a1e46212 SS |
1452 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
1453 | int primary) | |
1454 | { | |
7fc8442f MF |
1455 | if (cpa->pgd) { |
1456 | /* | |
1457 | * Right now, we only execute this code path when mapping | |
1458 | * the EFI virtual memory map regions, no other users | |
1459 | * provide a ->pgd value. This may change in the future. | |
1460 | */ | |
82f0712c | 1461 | return populate_pgd(cpa, vaddr); |
7fc8442f | 1462 | } |
82f0712c | 1463 | |
a1e46212 SS |
1464 | /* |
1465 | * Ignore all non primary paths. | |
1466 | */ | |
405e1133 JB |
1467 | if (!primary) { |
1468 | cpa->numpages = 1; | |
a1e46212 | 1469 | return 0; |
405e1133 | 1470 | } |
a1e46212 SS |
1471 | |
1472 | /* | |
1473 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
1474 | * to have holes. | |
1475 | * Also set numpages to '1' indicating that we processed cpa req for | |
1476 | * one virtual address page and its pfn. TBD: numpages can be set based | |
1477 | * on the initial value and the level returned by lookup_address(). | |
1478 | */ | |
1479 | if (within(vaddr, PAGE_OFFSET, | |
1480 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
1481 | cpa->numpages = 1; | |
1482 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
1483 | return 0; | |
58e65b51 DH |
1484 | |
1485 | } else if (__cpa_pfn_in_highmap(cpa->pfn)) { | |
1486 | /* Faults in the highmap are OK, so do not warn: */ | |
1487 | return -EFAULT; | |
a1e46212 SS |
1488 | } else { |
1489 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
1490 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
1491 | *cpa->vaddr); | |
1492 | ||
1493 | return -EFAULT; | |
1494 | } | |
1495 | } | |
1496 | ||
c31c7d48 | 1497 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 1498 | { |
d75586ad | 1499 | unsigned long address; |
da7bfc50 HH |
1500 | int do_split, err; |
1501 | unsigned int level; | |
c31c7d48 | 1502 | pte_t *kpte, old_pte; |
1da177e4 | 1503 | |
16ebf031 | 1504 | address = __cpa_addr(cpa, cpa->curpage); |
97f99fed | 1505 | repeat: |
82f0712c | 1506 | kpte = _lookup_address_cpa(cpa, address, &level); |
1da177e4 | 1507 | if (!kpte) |
a1e46212 | 1508 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
1509 | |
1510 | old_pte = *kpte; | |
dcb32d99 | 1511 | if (pte_none(old_pte)) |
a1e46212 | 1512 | return __cpa_process_fault(cpa, address, primary); |
9f4c815c | 1513 | |
30551bb3 | 1514 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 1515 | pte_t new_pte; |
626c2c9d | 1516 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 1517 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 1518 | |
72e458df TG |
1519 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
1520 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 1521 | |
5c280cf6 | 1522 | cpa_inc_4k_install(); |
4046460b TG |
1523 | new_prot = static_protections(new_prot, address, pfn, 1, |
1524 | CPA_PROTECT); | |
86f03989 | 1525 | |
d1440b23 | 1526 | new_prot = pgprot_clear_protnone_bits(new_prot); |
a8aed3e0 | 1527 | |
626c2c9d AV |
1528 | /* |
1529 | * We need to keep the pfn from the existing PTE, | |
1530 | * after all we're only going to change it's attributes | |
1531 | * not the memory it points to | |
1532 | */ | |
1a54420a | 1533 | new_pte = pfn_pte(pfn, new_prot); |
c31c7d48 | 1534 | cpa->pfn = pfn; |
f4ae5da0 TG |
1535 | /* |
1536 | * Do we really change anything ? | |
1537 | */ | |
1538 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
1539 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 1540 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 1541 | } |
9b5cf48b | 1542 | cpa->numpages = 1; |
65e074df | 1543 | return 0; |
1da177e4 | 1544 | } |
65e074df TG |
1545 | |
1546 | /* | |
1547 | * Check, whether we can keep the large page intact | |
1548 | * and just change the pte: | |
1549 | */ | |
8679de09 | 1550 | do_split = should_split_large_page(kpte, address, cpa); |
65e074df TG |
1551 | /* |
1552 | * When the range fits into the existing large page, | |
9b5cf48b | 1553 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
1554 | * try_large_page: |
1555 | */ | |
87f7f8fe IM |
1556 | if (do_split <= 0) |
1557 | return do_split; | |
65e074df TG |
1558 | |
1559 | /* | |
1560 | * We have to split the large page: | |
1561 | */ | |
82f0712c | 1562 | err = split_large_page(cpa, kpte, address); |
c0a759ab | 1563 | if (!err) |
87f7f8fe | 1564 | goto repeat; |
beaff633 | 1565 | |
87f7f8fe | 1566 | return err; |
9f4c815c | 1567 | } |
1da177e4 | 1568 | |
c31c7d48 TG |
1569 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
1570 | ||
1571 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 1572 | { |
c31c7d48 | 1573 | struct cpa_data alias_cpa; |
992f4c1c | 1574 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 1575 | unsigned long vaddr; |
992f4c1c | 1576 | int ret; |
44af6c41 | 1577 | |
8eb5779f | 1578 | if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1)) |
c31c7d48 | 1579 | return 0; |
626c2c9d | 1580 | |
f34b439f TG |
1581 | /* |
1582 | * No need to redo, when the primary call touched the direct | |
1583 | * mapping already: | |
1584 | */ | |
16ebf031 | 1585 | vaddr = __cpa_addr(cpa, cpa->curpage); |
d75586ad | 1586 | if (!(within(vaddr, PAGE_OFFSET, |
a1e46212 | 1587 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 1588 | |
f34b439f | 1589 | alias_cpa = *cpa; |
992f4c1c | 1590 | alias_cpa.vaddr = &laddr; |
9ae28475 | 1591 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
98bfc9b0 | 1592 | alias_cpa.curpage = 0; |
d75586ad | 1593 | |
f34b439f | 1594 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
1595 | if (ret) |
1596 | return ret; | |
f34b439f | 1597 | } |
44af6c41 | 1598 | |
44af6c41 | 1599 | #ifdef CONFIG_X86_64 |
488fd995 | 1600 | /* |
992f4c1c TH |
1601 | * If the primary call didn't touch the high mapping already |
1602 | * and the physical address is inside the kernel map, we need | |
0879750f | 1603 | * to touch the high mapped kernel as well: |
488fd995 | 1604 | */ |
992f4c1c | 1605 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
58e65b51 | 1606 | __cpa_pfn_in_highmap(cpa->pfn)) { |
992f4c1c TH |
1607 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + |
1608 | __START_KERNEL_map - phys_base; | |
1609 | alias_cpa = *cpa; | |
1610 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
1611 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
98bfc9b0 | 1612 | alias_cpa.curpage = 0; |
c31c7d48 | 1613 | |
992f4c1c TH |
1614 | /* |
1615 | * The high mapping range is imprecise, so ignore the | |
1616 | * return value. | |
1617 | */ | |
1618 | __change_page_attr_set_clr(&alias_cpa, 0); | |
1619 | } | |
488fd995 | 1620 | #endif |
992f4c1c TH |
1621 | |
1622 | return 0; | |
1da177e4 LT |
1623 | } |
1624 | ||
c31c7d48 | 1625 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 1626 | { |
e535ec08 | 1627 | unsigned long numpages = cpa->numpages; |
83b4e391 PZ |
1628 | unsigned long rempages = numpages; |
1629 | int ret = 0; | |
ff31452b | 1630 | |
83b4e391 | 1631 | while (rempages) { |
65e074df TG |
1632 | /* |
1633 | * Store the remaining nr of pages for the large page | |
1634 | * preservation check. | |
1635 | */ | |
83b4e391 | 1636 | cpa->numpages = rempages; |
d75586ad | 1637 | /* for array changes, we can't use large page */ |
9ae28475 | 1638 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 1639 | cpa->numpages = 1; |
c31c7d48 | 1640 | |
288cf3c6 | 1641 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1642 | spin_lock(&cpa_lock); |
c31c7d48 | 1643 | ret = __change_page_attr(cpa, checkalias); |
288cf3c6 | 1644 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1645 | spin_unlock(&cpa_lock); |
ff31452b | 1646 | if (ret) |
83b4e391 | 1647 | goto out; |
ff31452b | 1648 | |
c31c7d48 TG |
1649 | if (checkalias) { |
1650 | ret = cpa_process_alias(cpa); | |
1651 | if (ret) | |
83b4e391 | 1652 | goto out; |
c31c7d48 TG |
1653 | } |
1654 | ||
65e074df TG |
1655 | /* |
1656 | * Adjust the number of pages with the result of the | |
1657 | * CPA operation. Either a large page has been | |
1658 | * preserved or a single page update happened. | |
1659 | */ | |
83b4e391 PZ |
1660 | BUG_ON(cpa->numpages > rempages || !cpa->numpages); |
1661 | rempages -= cpa->numpages; | |
98bfc9b0 | 1662 | cpa->curpage += cpa->numpages; |
65e074df | 1663 | } |
83b4e391 PZ |
1664 | |
1665 | out: | |
1666 | /* Restore the original numpages */ | |
1667 | cpa->numpages = numpages; | |
1668 | return ret; | |
ff31452b TG |
1669 | } |
1670 | ||
c7486104 L |
1671 | /* |
1672 | * Machine check recovery code needs to change cache mode of poisoned | |
1673 | * pages to UC to avoid speculative access logging another error. But | |
1674 | * passing the address of the 1:1 mapping to set_memory_uc() is a fine | |
1675 | * way to encourage a speculative access. So we cheat and flip the top | |
1676 | * bit of the address. This works fine for the code that updates the | |
1677 | * page tables. But at the end of the process we need to flush the cache | |
1678 | * and the non-canonical address causes a #GP fault when used by the | |
1679 | * CLFLUSH instruction. | |
1680 | * | |
1681 | * But in the common case we already have a canonical address. This code | |
1682 | * will fix the top bit if needed and is a no-op otherwise. | |
1683 | */ | |
1684 | static inline unsigned long make_addr_canonical_again(unsigned long addr) | |
1685 | { | |
1686 | #ifdef CONFIG_X86_64 | |
1687 | return (long)(addr << 1) >> 1; | |
1688 | #else | |
1689 | return addr; | |
1690 | #endif | |
1691 | } | |
1692 | ||
1693 | ||
d75586ad | 1694 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 1695 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 1696 | int force_split, int in_flag, |
1697 | struct page **pages) | |
ff31452b | 1698 | { |
72e458df | 1699 | struct cpa_data cpa; |
cacf8906 | 1700 | int ret, cache, checkalias; |
fa526d0d | 1701 | unsigned long baddr = 0; |
331e4065 | 1702 | |
82f0712c BP |
1703 | memset(&cpa, 0, sizeof(cpa)); |
1704 | ||
331e4065 | 1705 | /* |
39114b7a DH |
1706 | * Check, if we are requested to set a not supported |
1707 | * feature. Clearing non-supported features is OK. | |
331e4065 TG |
1708 | */ |
1709 | mask_set = canon_pgprot(mask_set); | |
39114b7a | 1710 | |
c9caa02c | 1711 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
1712 | return 0; |
1713 | ||
69b1415e | 1714 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 1715 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
1716 | int i; |
1717 | for (i = 0; i < numpages; i++) { | |
1718 | if (addr[i] & ~PAGE_MASK) { | |
1719 | addr[i] &= PAGE_MASK; | |
1720 | WARN_ON_ONCE(1); | |
1721 | } | |
1722 | } | |
9ae28475 | 1723 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
1724 | /* | |
1725 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
1726 | * No need to cehck in that case | |
1727 | */ | |
1728 | if (*addr & ~PAGE_MASK) { | |
1729 | *addr &= PAGE_MASK; | |
1730 | /* | |
1731 | * People should not be passing in unaligned addresses: | |
1732 | */ | |
1733 | WARN_ON_ONCE(1); | |
1734 | } | |
fa526d0d JS |
1735 | /* |
1736 | * Save address for cache flush. *addr is modified in the call | |
1737 | * to __change_page_attr_set_clr() below. | |
1738 | */ | |
c7486104 | 1739 | baddr = make_addr_canonical_again(*addr); |
69b1415e TG |
1740 | } |
1741 | ||
5843d9a4 NP |
1742 | /* Must avoid aliasing mappings in the highmem code */ |
1743 | kmap_flush_unused(); | |
1744 | ||
db64fe02 NP |
1745 | vm_unmap_aliases(); |
1746 | ||
72e458df | 1747 | cpa.vaddr = addr; |
9ae28475 | 1748 | cpa.pages = pages; |
72e458df TG |
1749 | cpa.numpages = numpages; |
1750 | cpa.mask_set = mask_set; | |
1751 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
1752 | cpa.flags = 0; |
1753 | cpa.curpage = 0; | |
c9caa02c | 1754 | cpa.force_split = force_split; |
72e458df | 1755 | |
9ae28475 | 1756 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
1757 | cpa.flags |= in_flag; | |
d75586ad | 1758 | |
af96e443 TG |
1759 | /* No alias checking for _NX bit modifications */ |
1760 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
c40a56a7 DH |
1761 | /* Has caller explicitly disabled alias checking? */ |
1762 | if (in_flag & CPA_NO_CHECK_ALIAS) | |
1763 | checkalias = 0; | |
af96e443 TG |
1764 | |
1765 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 1766 | |
f4ae5da0 TG |
1767 | /* |
1768 | * Check whether we really changed something: | |
1769 | */ | |
d75586ad | 1770 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 1771 | goto out; |
cacf8906 | 1772 | |
6bb8383b AK |
1773 | /* |
1774 | * No need to flush, when we did not set any of the caching | |
1775 | * attributes: | |
1776 | */ | |
c06814d8 | 1777 | cache = !!pgprot2cachemode(mask_set); |
6bb8383b | 1778 | |
57a6a46a | 1779 | /* |
fce2ce95 | 1780 | * On error; flush everything to be sure. |
57a6a46a | 1781 | */ |
fce2ce95 | 1782 | if (ret) { |
6bb8383b | 1783 | cpa_flush_all(cache); |
fce2ce95 PZ |
1784 | goto out; |
1785 | } | |
1786 | ||
935f5839 PZ |
1787 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
1788 | cpa_flush_array(&cpa, cache); | |
1789 | else | |
fce2ce95 | 1790 | cpa_flush_range(baddr, numpages, cache); |
cacf8906 | 1791 | |
76ebd054 | 1792 | out: |
ff31452b TG |
1793 | return ret; |
1794 | } | |
1795 | ||
d75586ad SL |
1796 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
1797 | pgprot_t mask, int array) | |
75cbade8 | 1798 | { |
d75586ad | 1799 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 1800 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
1801 | } |
1802 | ||
d75586ad SL |
1803 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
1804 | pgprot_t mask, int array) | |
72932c7a | 1805 | { |
d75586ad | 1806 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 1807 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
1808 | } |
1809 | ||
0f350755 | 1810 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
1811 | pgprot_t mask) | |
1812 | { | |
1813 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
1814 | CPA_PAGES_ARRAY, pages); | |
1815 | } | |
1816 | ||
1817 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
1818 | pgprot_t mask) | |
1819 | { | |
1820 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
1821 | CPA_PAGES_ARRAY, pages); | |
1822 | } | |
1823 | ||
1219333d | 1824 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 1825 | { |
de33c442 SS |
1826 | /* |
1827 | * for now UC MINUS. see comments in ioremap_nocache() | |
e4b6be33 LR |
1828 | * If you really need strong UC use ioremap_uc(), but note |
1829 | * that you cannot override IO areas with set_memory_*() as | |
1830 | * these helpers cannot work with IO memory. | |
de33c442 | 1831 | */ |
d75586ad | 1832 | return change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1833 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1834 | 0); | |
75cbade8 | 1835 | } |
1219333d | 1836 | |
1837 | int set_memory_uc(unsigned long addr, int numpages) | |
1838 | { | |
9fa3ab39 | 1839 | int ret; |
1840 | ||
de33c442 SS |
1841 | /* |
1842 | * for now UC MINUS. see comments in ioremap_nocache() | |
1843 | */ | |
9fa3ab39 | 1844 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1845 | _PAGE_CACHE_MODE_UC_MINUS, NULL); |
9fa3ab39 | 1846 | if (ret) |
1847 | goto out_err; | |
1848 | ||
1849 | ret = _set_memory_uc(addr, numpages); | |
1850 | if (ret) | |
1851 | goto out_free; | |
1852 | ||
1853 | return 0; | |
1219333d | 1854 | |
9fa3ab39 | 1855 | out_free: |
1856 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1857 | out_err: | |
1858 | return ret; | |
1219333d | 1859 | } |
75cbade8 AV |
1860 | EXPORT_SYMBOL(set_memory_uc); |
1861 | ||
2d070eff | 1862 | static int _set_memory_array(unsigned long *addr, int addrinarray, |
c06814d8 | 1863 | enum page_cache_mode new_type) |
d75586ad | 1864 | { |
623dffb2 | 1865 | enum page_cache_mode set_type; |
9fa3ab39 | 1866 | int i, j; |
1867 | int ret; | |
1868 | ||
d75586ad | 1869 | for (i = 0; i < addrinarray; i++) { |
9fa3ab39 | 1870 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1871 | new_type, NULL); |
9fa3ab39 | 1872 | if (ret) |
1873 | goto out_free; | |
d75586ad SL |
1874 | } |
1875 | ||
623dffb2 TK |
1876 | /* If WC, set to UC- first and then WC */ |
1877 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1878 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1879 | ||
9fa3ab39 | 1880 | ret = change_page_attr_set(addr, addrinarray, |
623dffb2 | 1881 | cachemode2pgprot(set_type), 1); |
4f646254 | 1882 | |
c06814d8 | 1883 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1884 | ret = change_page_attr_set_clr(addr, addrinarray, |
c06814d8 JG |
1885 | cachemode2pgprot( |
1886 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1887 | __pgprot(_PAGE_CACHE_MASK), |
1888 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1889 | if (ret) |
1890 | goto out_free; | |
1891 | ||
1892 | return 0; | |
1893 | ||
1894 | out_free: | |
1895 | for (j = 0; j < i; j++) | |
1896 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1897 | ||
1898 | return ret; | |
d75586ad | 1899 | } |
4f646254 PN |
1900 | |
1901 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1902 | { | |
c06814d8 | 1903 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1904 | } |
d75586ad SL |
1905 | EXPORT_SYMBOL(set_memory_array_uc); |
1906 | ||
4f646254 PN |
1907 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1908 | { | |
c06814d8 | 1909 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1910 | } |
1911 | EXPORT_SYMBOL(set_memory_array_wc); | |
1912 | ||
623dffb2 TK |
1913 | int set_memory_array_wt(unsigned long *addr, int addrinarray) |
1914 | { | |
1915 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT); | |
1916 | } | |
1917 | EXPORT_SYMBOL_GPL(set_memory_array_wt); | |
1918 | ||
ef354af4 | 1919 | int _set_memory_wc(unsigned long addr, int numpages) |
1920 | { | |
3869c4aa | 1921 | int ret; |
bdc6340f | 1922 | |
3869c4aa | 1923 | ret = change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1924 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1925 | 0); | |
3869c4aa | 1926 | if (!ret) { |
5fe26b7a PZ |
1927 | ret = change_page_attr_set_clr(&addr, numpages, |
1928 | cachemode2pgprot(_PAGE_CACHE_MODE_WC), | |
bdc6340f PV |
1929 | __pgprot(_PAGE_CACHE_MASK), |
1930 | 0, 0, NULL); | |
3869c4aa | 1931 | } |
1932 | return ret; | |
ef354af4 | 1933 | } |
1934 | ||
1935 | int set_memory_wc(unsigned long addr, int numpages) | |
1936 | { | |
9fa3ab39 | 1937 | int ret; |
1938 | ||
9fa3ab39 | 1939 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1940 | _PAGE_CACHE_MODE_WC, NULL); |
9fa3ab39 | 1941 | if (ret) |
623dffb2 | 1942 | return ret; |
ef354af4 | 1943 | |
9fa3ab39 | 1944 | ret = _set_memory_wc(addr, numpages); |
1945 | if (ret) | |
623dffb2 | 1946 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1947 | |
9fa3ab39 | 1948 | return ret; |
ef354af4 | 1949 | } |
1950 | EXPORT_SYMBOL(set_memory_wc); | |
1951 | ||
623dffb2 TK |
1952 | int _set_memory_wt(unsigned long addr, int numpages) |
1953 | { | |
1954 | return change_page_attr_set(&addr, numpages, | |
1955 | cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0); | |
1956 | } | |
1957 | ||
1958 | int set_memory_wt(unsigned long addr, int numpages) | |
1959 | { | |
1960 | int ret; | |
1961 | ||
1962 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, | |
1963 | _PAGE_CACHE_MODE_WT, NULL); | |
1964 | if (ret) | |
1965 | return ret; | |
1966 | ||
1967 | ret = _set_memory_wt(addr, numpages); | |
1968 | if (ret) | |
1969 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1970 | ||
1971 | return ret; | |
1972 | } | |
1973 | EXPORT_SYMBOL_GPL(set_memory_wt); | |
1974 | ||
1219333d | 1975 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1976 | { |
c06814d8 | 1977 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
d75586ad SL |
1978 | return change_page_attr_clear(&addr, numpages, |
1979 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1980 | } |
1219333d | 1981 | |
1982 | int set_memory_wb(unsigned long addr, int numpages) | |
1983 | { | |
9fa3ab39 | 1984 | int ret; |
1985 | ||
1986 | ret = _set_memory_wb(addr, numpages); | |
1987 | if (ret) | |
1988 | return ret; | |
1989 | ||
c15238df | 1990 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1991 | return 0; |
1219333d | 1992 | } |
75cbade8 AV |
1993 | EXPORT_SYMBOL(set_memory_wb); |
1994 | ||
d75586ad SL |
1995 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1996 | { | |
1997 | int i; | |
a5593e0b | 1998 | int ret; |
1999 | ||
c06814d8 | 2000 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
a5593e0b | 2001 | ret = change_page_attr_clear(addr, addrinarray, |
2002 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 2003 | if (ret) |
2004 | return ret; | |
d75586ad | 2005 | |
9fa3ab39 | 2006 | for (i = 0; i < addrinarray; i++) |
2007 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 2008 | |
9fa3ab39 | 2009 | return 0; |
d75586ad SL |
2010 | } |
2011 | EXPORT_SYMBOL(set_memory_array_wb); | |
2012 | ||
75cbade8 AV |
2013 | int set_memory_x(unsigned long addr, int numpages) |
2014 | { | |
583140af PA |
2015 | if (!(__supported_pte_mask & _PAGE_NX)) |
2016 | return 0; | |
2017 | ||
d75586ad | 2018 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
2019 | } |
2020 | EXPORT_SYMBOL(set_memory_x); | |
2021 | ||
2022 | int set_memory_nx(unsigned long addr, int numpages) | |
2023 | { | |
583140af PA |
2024 | if (!(__supported_pte_mask & _PAGE_NX)) |
2025 | return 0; | |
2026 | ||
d75586ad | 2027 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
2028 | } |
2029 | EXPORT_SYMBOL(set_memory_nx); | |
2030 | ||
2031 | int set_memory_ro(unsigned long addr, int numpages) | |
2032 | { | |
d75586ad | 2033 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 2034 | } |
75cbade8 AV |
2035 | |
2036 | int set_memory_rw(unsigned long addr, int numpages) | |
2037 | { | |
d75586ad | 2038 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 2039 | } |
f62d0f00 IM |
2040 | |
2041 | int set_memory_np(unsigned long addr, int numpages) | |
2042 | { | |
d75586ad | 2043 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 2044 | } |
75cbade8 | 2045 | |
c40a56a7 DH |
2046 | int set_memory_np_noalias(unsigned long addr, int numpages) |
2047 | { | |
2048 | int cpa_flags = CPA_NO_CHECK_ALIAS; | |
2049 | ||
2050 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), | |
2051 | __pgprot(_PAGE_PRESENT), 0, | |
2052 | cpa_flags, NULL); | |
2053 | } | |
2054 | ||
c9caa02c AK |
2055 | int set_memory_4k(unsigned long addr, int numpages) |
2056 | { | |
d75586ad | 2057 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 2058 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
2059 | } |
2060 | ||
39114b7a DH |
2061 | int set_memory_nonglobal(unsigned long addr, int numpages) |
2062 | { | |
2063 | return change_page_attr_clear(&addr, numpages, | |
2064 | __pgprot(_PAGE_GLOBAL), 0); | |
2065 | } | |
2066 | ||
eac7073a DH |
2067 | int set_memory_global(unsigned long addr, int numpages) |
2068 | { | |
2069 | return change_page_attr_set(&addr, numpages, | |
2070 | __pgprot(_PAGE_GLOBAL), 0); | |
2071 | } | |
2072 | ||
77bd2342 TL |
2073 | static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) |
2074 | { | |
2075 | struct cpa_data cpa; | |
77bd2342 TL |
2076 | int ret; |
2077 | ||
a72ec5a3 TL |
2078 | /* Nothing to do if memory encryption is not active */ |
2079 | if (!mem_encrypt_active()) | |
77bd2342 TL |
2080 | return 0; |
2081 | ||
2082 | /* Should not be working on unaligned addresses */ | |
2083 | if (WARN_ONCE(addr & ~PAGE_MASK, "misaligned address: %#lx\n", addr)) | |
2084 | addr &= PAGE_MASK; | |
2085 | ||
77bd2342 TL |
2086 | memset(&cpa, 0, sizeof(cpa)); |
2087 | cpa.vaddr = &addr; | |
2088 | cpa.numpages = numpages; | |
2089 | cpa.mask_set = enc ? __pgprot(_PAGE_ENC) : __pgprot(0); | |
2090 | cpa.mask_clr = enc ? __pgprot(0) : __pgprot(_PAGE_ENC); | |
2091 | cpa.pgd = init_mm.pgd; | |
2092 | ||
2093 | /* Must avoid aliasing mappings in the highmem code */ | |
2094 | kmap_flush_unused(); | |
2095 | vm_unmap_aliases(); | |
2096 | ||
2097 | /* | |
2098 | * Before changing the encryption attribute, we need to flush caches. | |
2099 | */ | |
5fe26b7a | 2100 | cpa_flush_range(addr, numpages, 1); |
77bd2342 TL |
2101 | |
2102 | ret = __change_page_attr_set_clr(&cpa, 1); | |
2103 | ||
2104 | /* | |
2105 | * After changing the encryption attribute, we need to flush TLBs | |
2106 | * again in case any speculative TLB caching occurred (but no need | |
2107 | * to flush caches again). We could just use cpa_flush_all(), but | |
2108 | * in case TLB flushing gets optimized in the cpa_flush_range() | |
2109 | * path use the same logic as above. | |
2110 | */ | |
5fe26b7a | 2111 | cpa_flush_range(addr, numpages, 0); |
77bd2342 TL |
2112 | |
2113 | return ret; | |
2114 | } | |
2115 | ||
2116 | int set_memory_encrypted(unsigned long addr, int numpages) | |
2117 | { | |
2118 | return __set_memory_enc_dec(addr, numpages, true); | |
2119 | } | |
95cf9264 | 2120 | EXPORT_SYMBOL_GPL(set_memory_encrypted); |
77bd2342 TL |
2121 | |
2122 | int set_memory_decrypted(unsigned long addr, int numpages) | |
2123 | { | |
2124 | return __set_memory_enc_dec(addr, numpages, false); | |
2125 | } | |
95cf9264 | 2126 | EXPORT_SYMBOL_GPL(set_memory_decrypted); |
77bd2342 | 2127 | |
75cbade8 AV |
2128 | int set_pages_uc(struct page *page, int numpages) |
2129 | { | |
2130 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 2131 | |
d7c8f21a | 2132 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
2133 | } |
2134 | EXPORT_SYMBOL(set_pages_uc); | |
2135 | ||
4f646254 | 2136 | static int _set_pages_array(struct page **pages, int addrinarray, |
c06814d8 | 2137 | enum page_cache_mode new_type) |
0f350755 | 2138 | { |
2139 | unsigned long start; | |
2140 | unsigned long end; | |
623dffb2 | 2141 | enum page_cache_mode set_type; |
0f350755 | 2142 | int i; |
2143 | int free_idx; | |
4f646254 | 2144 | int ret; |
0f350755 | 2145 | |
2146 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
2147 | if (PageHighMem(pages[i])) |
2148 | continue; | |
2149 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 2150 | end = start + PAGE_SIZE; |
4f646254 | 2151 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 2152 | goto err_out; |
2153 | } | |
2154 | ||
623dffb2 TK |
2155 | /* If WC, set to UC- first and then WC */ |
2156 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
2157 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
2158 | ||
4f646254 | 2159 | ret = cpa_set_pages_array(pages, addrinarray, |
623dffb2 | 2160 | cachemode2pgprot(set_type)); |
c06814d8 | 2161 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 2162 | ret = change_page_attr_set_clr(NULL, addrinarray, |
c06814d8 JG |
2163 | cachemode2pgprot( |
2164 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
2165 | __pgprot(_PAGE_CACHE_MASK), |
2166 | 0, CPA_PAGES_ARRAY, pages); | |
2167 | if (ret) | |
2168 | goto err_out; | |
2169 | return 0; /* Success */ | |
0f350755 | 2170 | err_out: |
2171 | free_idx = i; | |
2172 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
2173 | if (PageHighMem(pages[i])) |
2174 | continue; | |
2175 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 2176 | end = start + PAGE_SIZE; |
2177 | free_memtype(start, end); | |
2178 | } | |
2179 | return -EINVAL; | |
2180 | } | |
4f646254 PN |
2181 | |
2182 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
2183 | { | |
c06814d8 | 2184 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 2185 | } |
0f350755 | 2186 | EXPORT_SYMBOL(set_pages_array_uc); |
2187 | ||
4f646254 PN |
2188 | int set_pages_array_wc(struct page **pages, int addrinarray) |
2189 | { | |
c06814d8 | 2190 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
2191 | } |
2192 | EXPORT_SYMBOL(set_pages_array_wc); | |
2193 | ||
623dffb2 TK |
2194 | int set_pages_array_wt(struct page **pages, int addrinarray) |
2195 | { | |
2196 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT); | |
2197 | } | |
2198 | EXPORT_SYMBOL_GPL(set_pages_array_wt); | |
2199 | ||
75cbade8 AV |
2200 | int set_pages_wb(struct page *page, int numpages) |
2201 | { | |
2202 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 2203 | |
d7c8f21a | 2204 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
2205 | } |
2206 | EXPORT_SYMBOL(set_pages_wb); | |
2207 | ||
0f350755 | 2208 | int set_pages_array_wb(struct page **pages, int addrinarray) |
2209 | { | |
2210 | int retval; | |
2211 | unsigned long start; | |
2212 | unsigned long end; | |
2213 | int i; | |
2214 | ||
c06814d8 | 2215 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
0f350755 | 2216 | retval = cpa_clear_pages_array(pages, addrinarray, |
2217 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 2218 | if (retval) |
2219 | return retval; | |
0f350755 | 2220 | |
2221 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
2222 | if (PageHighMem(pages[i])) |
2223 | continue; | |
2224 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 2225 | end = start + PAGE_SIZE; |
2226 | free_memtype(start, end); | |
2227 | } | |
2228 | ||
9fa3ab39 | 2229 | return 0; |
0f350755 | 2230 | } |
2231 | EXPORT_SYMBOL(set_pages_array_wb); | |
2232 | ||
75cbade8 AV |
2233 | int set_pages_x(struct page *page, int numpages) |
2234 | { | |
2235 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 2236 | |
d7c8f21a | 2237 | return set_memory_x(addr, numpages); |
75cbade8 AV |
2238 | } |
2239 | EXPORT_SYMBOL(set_pages_x); | |
2240 | ||
2241 | int set_pages_nx(struct page *page, int numpages) | |
2242 | { | |
2243 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 2244 | |
d7c8f21a | 2245 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
2246 | } |
2247 | EXPORT_SYMBOL(set_pages_nx); | |
2248 | ||
2249 | int set_pages_ro(struct page *page, int numpages) | |
2250 | { | |
2251 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 2252 | |
d7c8f21a | 2253 | return set_memory_ro(addr, numpages); |
75cbade8 | 2254 | } |
75cbade8 AV |
2255 | |
2256 | int set_pages_rw(struct page *page, int numpages) | |
2257 | { | |
2258 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 2259 | |
d7c8f21a | 2260 | return set_memory_rw(addr, numpages); |
78c94aba IM |
2261 | } |
2262 | ||
1da177e4 | 2263 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
2264 | |
2265 | static int __set_pages_p(struct page *page, int numpages) | |
2266 | { | |
d75586ad SL |
2267 | unsigned long tempaddr = (unsigned long) page_address(page); |
2268 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 2269 | .pgd = NULL, |
72e458df TG |
2270 | .numpages = numpages, |
2271 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
2272 | .mask_clr = __pgprot(0), |
2273 | .flags = 0}; | |
72932c7a | 2274 | |
55121b43 SS |
2275 | /* |
2276 | * No alias checking needed for setting present flag. otherwise, | |
2277 | * we may need to break large pages for 64-bit kernel text | |
2278 | * mappings (this adds to complexity if we want to do this from | |
2279 | * atomic context especially). Let's keep it simple! | |
2280 | */ | |
2281 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
2282 | } |
2283 | ||
2284 | static int __set_pages_np(struct page *page, int numpages) | |
2285 | { | |
d75586ad SL |
2286 | unsigned long tempaddr = (unsigned long) page_address(page); |
2287 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 2288 | .pgd = NULL, |
72e458df TG |
2289 | .numpages = numpages, |
2290 | .mask_set = __pgprot(0), | |
d75586ad SL |
2291 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
2292 | .flags = 0}; | |
72932c7a | 2293 | |
55121b43 SS |
2294 | /* |
2295 | * No alias checking needed for setting not present flag. otherwise, | |
2296 | * we may need to break large pages for 64-bit kernel text | |
2297 | * mappings (this adds to complexity if we want to do this from | |
2298 | * atomic context especially). Let's keep it simple! | |
2299 | */ | |
2300 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
2301 | } |
2302 | ||
031bc574 | 2303 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
1da177e4 LT |
2304 | { |
2305 | if (PageHighMem(page)) | |
2306 | return; | |
9f4c815c | 2307 | if (!enable) { |
f9b8404c IM |
2308 | debug_check_no_locks_freed(page_address(page), |
2309 | numpages * PAGE_SIZE); | |
9f4c815c | 2310 | } |
de5097c2 | 2311 | |
9f4c815c | 2312 | /* |
f8d8406b | 2313 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
2314 | * Large pages for identity mappings are not used at boot time |
2315 | * and hence no memory allocations during large page split. | |
1da177e4 | 2316 | */ |
f62d0f00 IM |
2317 | if (enable) |
2318 | __set_pages_p(page, numpages); | |
2319 | else | |
2320 | __set_pages_np(page, numpages); | |
9f4c815c IM |
2321 | |
2322 | /* | |
e4b71dcf | 2323 | * We should perform an IPI and flush all tlbs, |
f77084d9 SAS |
2324 | * but that can deadlock->flush only current cpu. |
2325 | * Preemption needs to be disabled around __flush_tlb_all() due to | |
2326 | * CR3 reload in __native_flush_tlb(). | |
1da177e4 | 2327 | */ |
f77084d9 | 2328 | preempt_disable(); |
1da177e4 | 2329 | __flush_tlb_all(); |
f77084d9 | 2330 | preempt_enable(); |
26564600 BO |
2331 | |
2332 | arch_flush_lazy_mmu_mode(); | |
ee7ae7a1 TG |
2333 | } |
2334 | ||
8a235efa RW |
2335 | #ifdef CONFIG_HIBERNATION |
2336 | ||
2337 | bool kernel_page_present(struct page *page) | |
2338 | { | |
2339 | unsigned int level; | |
2340 | pte_t *pte; | |
2341 | ||
2342 | if (PageHighMem(page)) | |
2343 | return false; | |
2344 | ||
2345 | pte = lookup_address((unsigned long)page_address(page), &level); | |
2346 | return (pte_val(*pte) & _PAGE_PRESENT); | |
2347 | } | |
2348 | ||
2349 | #endif /* CONFIG_HIBERNATION */ | |
2350 | ||
2351 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 | 2352 | |
82f0712c BP |
2353 | int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address, |
2354 | unsigned numpages, unsigned long page_flags) | |
2355 | { | |
2356 | int retval = -EINVAL; | |
2357 | ||
2358 | struct cpa_data cpa = { | |
2359 | .vaddr = &address, | |
2360 | .pfn = pfn, | |
2361 | .pgd = pgd, | |
2362 | .numpages = numpages, | |
2363 | .mask_set = __pgprot(0), | |
2364 | .mask_clr = __pgprot(0), | |
2365 | .flags = 0, | |
2366 | }; | |
2367 | ||
2368 | if (!(__supported_pte_mask & _PAGE_NX)) | |
2369 | goto out; | |
2370 | ||
2371 | if (!(page_flags & _PAGE_NX)) | |
2372 | cpa.mask_clr = __pgprot(_PAGE_NX); | |
2373 | ||
15f003d2 SP |
2374 | if (!(page_flags & _PAGE_RW)) |
2375 | cpa.mask_clr = __pgprot(_PAGE_RW); | |
2376 | ||
21729f81 TL |
2377 | if (!(page_flags & _PAGE_ENC)) |
2378 | cpa.mask_clr = pgprot_encrypted(cpa.mask_clr); | |
2379 | ||
82f0712c BP |
2380 | cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags); |
2381 | ||
2382 | retval = __change_page_attr_set_clr(&cpa, 0); | |
2383 | __flush_tlb_all(); | |
2384 | ||
2385 | out: | |
2386 | return retval; | |
2387 | } | |
2388 | ||
d1028a15 AV |
2389 | /* |
2390 | * The testcases use internal knowledge of the implementation that shouldn't | |
2391 | * be exposed to the rest of the kernel. Include these directly here. | |
2392 | */ | |
2393 | #ifdef CONFIG_CPA_DEBUG | |
2394 | #include "pageattr-test.c" | |
2395 | #endif |