Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c | 10 | #include <linux/mm.h> |
76ebd054 | 11 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
12 | #include <linux/seq_file.h> |
13 | #include <linux/debugfs.h> | |
9f4c815c | 14 | |
950f9d95 | 15 | #include <asm/e820.h> |
1da177e4 LT |
16 | #include <asm/processor.h> |
17 | #include <asm/tlbflush.h> | |
f8af095d | 18 | #include <asm/sections.h> |
93dbda7c | 19 | #include <asm/setup.h> |
9f4c815c IM |
20 | #include <asm/uaccess.h> |
21 | #include <asm/pgalloc.h> | |
c31c7d48 | 22 | #include <asm/proto.h> |
1219333d | 23 | #include <asm/pat.h> |
1da177e4 | 24 | |
9df84993 IM |
25 | /* |
26 | * The current flushing context - we pass it instead of 5 arguments: | |
27 | */ | |
72e458df | 28 | struct cpa_data { |
d75586ad | 29 | unsigned long *vaddr; |
72e458df TG |
30 | pgprot_t mask_set; |
31 | pgprot_t mask_clr; | |
65e074df | 32 | int numpages; |
d75586ad | 33 | int flags; |
c31c7d48 | 34 | unsigned long pfn; |
c9caa02c | 35 | unsigned force_split : 1; |
d75586ad | 36 | int curpage; |
72e458df TG |
37 | }; |
38 | ||
ad5ca55f SS |
39 | /* |
40 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
41 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
42 | * entries change the page attribute in parallel to some other cpu | |
43 | * splitting a large page entry along with changing the attribute. | |
44 | */ | |
45 | static DEFINE_SPINLOCK(cpa_lock); | |
46 | ||
d75586ad SL |
47 | #define CPA_FLUSHTLB 1 |
48 | #define CPA_ARRAY 2 | |
49 | ||
65280e61 | 50 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
51 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
52 | ||
65280e61 | 53 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 54 | { |
ce0c0e50 | 55 | unsigned long flags; |
65280e61 | 56 | |
ce0c0e50 AK |
57 | /* Protect against CPA */ |
58 | spin_lock_irqsave(&pgd_lock, flags); | |
59 | direct_pages_count[level] += pages; | |
60 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
61 | } |
62 | ||
63 | static void split_page_count(int level) | |
64 | { | |
65 | direct_pages_count[level]--; | |
66 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
67 | } | |
68 | ||
e1759c21 | 69 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 70 | { |
b9c3bfc2 | 71 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
72 | direct_pages_count[PG_LEVEL_4K] << 2); |
73 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 74 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
75 | direct_pages_count[PG_LEVEL_2M] << 11); |
76 | #else | |
b9c3bfc2 | 77 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
78 | direct_pages_count[PG_LEVEL_2M] << 12); |
79 | #endif | |
65280e61 | 80 | #ifdef CONFIG_X86_64 |
a06de630 | 81 | if (direct_gbpages) |
b9c3bfc2 | 82 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 83 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
84 | #endif |
85 | } | |
65280e61 TG |
86 | #else |
87 | static inline void split_page_count(int level) { } | |
88 | #endif | |
ce0c0e50 | 89 | |
c31c7d48 TG |
90 | #ifdef CONFIG_X86_64 |
91 | ||
92 | static inline unsigned long highmap_start_pfn(void) | |
93 | { | |
94 | return __pa(_text) >> PAGE_SHIFT; | |
95 | } | |
96 | ||
97 | static inline unsigned long highmap_end_pfn(void) | |
98 | { | |
93dbda7c | 99 | return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
100 | } |
101 | ||
102 | #endif | |
103 | ||
92cb54a3 IM |
104 | #ifdef CONFIG_DEBUG_PAGEALLOC |
105 | # define debug_pagealloc 1 | |
106 | #else | |
107 | # define debug_pagealloc 0 | |
108 | #endif | |
109 | ||
ed724be6 AV |
110 | static inline int |
111 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 112 | { |
ed724be6 AV |
113 | return addr >= start && addr < end; |
114 | } | |
115 | ||
d7c8f21a TG |
116 | /* |
117 | * Flushing functions | |
118 | */ | |
cd8ddf1a | 119 | |
cd8ddf1a TG |
120 | /** |
121 | * clflush_cache_range - flush a cache range with clflush | |
122 | * @addr: virtual start address | |
123 | * @size: number of bytes to flush | |
124 | * | |
125 | * clflush is an unordered instruction which needs fencing with mfence | |
126 | * to avoid ordering issues. | |
127 | */ | |
4c61afcd | 128 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 129 | { |
4c61afcd | 130 | void *vend = vaddr + size - 1; |
d7c8f21a | 131 | |
cd8ddf1a | 132 | mb(); |
4c61afcd IM |
133 | |
134 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
135 | clflush(vaddr); | |
136 | /* | |
137 | * Flush any possible final partial cacheline: | |
138 | */ | |
139 | clflush(vend); | |
140 | ||
cd8ddf1a | 141 | mb(); |
d7c8f21a TG |
142 | } |
143 | ||
af1e6844 | 144 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 145 | { |
6bb8383b AK |
146 | unsigned long cache = (unsigned long)arg; |
147 | ||
d7c8f21a TG |
148 | /* |
149 | * Flush all to work around Errata in early athlons regarding | |
150 | * large page flushing. | |
151 | */ | |
152 | __flush_tlb_all(); | |
153 | ||
6bb8383b | 154 | if (cache && boot_cpu_data.x86_model >= 4) |
d7c8f21a TG |
155 | wbinvd(); |
156 | } | |
157 | ||
6bb8383b | 158 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
159 | { |
160 | BUG_ON(irqs_disabled()); | |
161 | ||
15c8b6c1 | 162 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
163 | } |
164 | ||
57a6a46a TG |
165 | static void __cpa_flush_range(void *arg) |
166 | { | |
57a6a46a TG |
167 | /* |
168 | * We could optimize that further and do individual per page | |
169 | * tlb invalidates for a low number of pages. Caveat: we must | |
170 | * flush the high aliases on 64bit as well. | |
171 | */ | |
172 | __flush_tlb_all(); | |
57a6a46a TG |
173 | } |
174 | ||
6bb8383b | 175 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 176 | { |
4c61afcd IM |
177 | unsigned int i, level; |
178 | unsigned long addr; | |
179 | ||
57a6a46a | 180 | BUG_ON(irqs_disabled()); |
4c61afcd | 181 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 182 | |
15c8b6c1 | 183 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 184 | |
6bb8383b AK |
185 | if (!cache) |
186 | return; | |
187 | ||
3b233e52 TG |
188 | /* |
189 | * We only need to flush on one CPU, | |
190 | * clflush is a MESI-coherent instruction that | |
191 | * will cause all other CPUs to flush the same | |
192 | * cachelines: | |
193 | */ | |
4c61afcd IM |
194 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
195 | pte_t *pte = lookup_address(addr, &level); | |
196 | ||
197 | /* | |
198 | * Only flush present addresses: | |
199 | */ | |
7bfb72e8 | 200 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
201 | clflush_cache_range((void *) addr, PAGE_SIZE); |
202 | } | |
57a6a46a TG |
203 | } |
204 | ||
d75586ad SL |
205 | static void cpa_flush_array(unsigned long *start, int numpages, int cache) |
206 | { | |
207 | unsigned int i, level; | |
208 | unsigned long *addr; | |
209 | ||
210 | BUG_ON(irqs_disabled()); | |
211 | ||
212 | on_each_cpu(__cpa_flush_range, NULL, 1); | |
213 | ||
214 | if (!cache) | |
215 | return; | |
216 | ||
217 | /* 4M threshold */ | |
218 | if (numpages >= 1024) { | |
219 | if (boot_cpu_data.x86_model >= 4) | |
220 | wbinvd(); | |
221 | return; | |
222 | } | |
223 | /* | |
224 | * We only need to flush on one CPU, | |
225 | * clflush is a MESI-coherent instruction that | |
226 | * will cause all other CPUs to flush the same | |
227 | * cachelines: | |
228 | */ | |
229 | for (i = 0, addr = start; i < numpages; i++, addr++) { | |
230 | pte_t *pte = lookup_address(*addr, &level); | |
231 | ||
232 | /* | |
233 | * Only flush present addresses: | |
234 | */ | |
235 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
236 | clflush_cache_range((void *) *addr, PAGE_SIZE); | |
237 | } | |
238 | } | |
239 | ||
ed724be6 AV |
240 | /* |
241 | * Certain areas of memory on x86 require very specific protection flags, | |
242 | * for example the BIOS area or kernel text. Callers don't always get this | |
243 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
244 | * checks and fixes these known static required protection bits. | |
245 | */ | |
c31c7d48 TG |
246 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
247 | unsigned long pfn) | |
ed724be6 AV |
248 | { |
249 | pgprot_t forbidden = __pgprot(0); | |
250 | ||
687c4825 | 251 | /* |
ed724be6 AV |
252 | * The BIOS area between 640k and 1Mb needs to be executable for |
253 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 254 | */ |
c31c7d48 | 255 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
256 | pgprot_val(forbidden) |= _PAGE_NX; |
257 | ||
258 | /* | |
259 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
260 | * Does not cover __inittext since that is gone later on. On |
261 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
262 | */ |
263 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
264 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 265 | |
cc0f21bb | 266 | /* |
c31c7d48 TG |
267 | * The .rodata section needs to be read-only. Using the pfn |
268 | * catches all aliases. | |
cc0f21bb | 269 | */ |
c31c7d48 TG |
270 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
271 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 272 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 AV |
273 | |
274 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
275 | |
276 | return prot; | |
277 | } | |
278 | ||
9a14aefc TG |
279 | /* |
280 | * Lookup the page table entry for a virtual address. Return a pointer | |
281 | * to the entry and the level of the mapping. | |
282 | * | |
283 | * Note: We return pud and pmd either when the entry is marked large | |
284 | * or when the present bit is not set. Otherwise we would return a | |
285 | * pointer to a nonexisting mapping. | |
286 | */ | |
da7bfc50 | 287 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 288 | { |
1da177e4 LT |
289 | pgd_t *pgd = pgd_offset_k(address); |
290 | pud_t *pud; | |
291 | pmd_t *pmd; | |
9f4c815c | 292 | |
30551bb3 TG |
293 | *level = PG_LEVEL_NONE; |
294 | ||
1da177e4 LT |
295 | if (pgd_none(*pgd)) |
296 | return NULL; | |
9df84993 | 297 | |
1da177e4 LT |
298 | pud = pud_offset(pgd, address); |
299 | if (pud_none(*pud)) | |
300 | return NULL; | |
c2f71ee2 AK |
301 | |
302 | *level = PG_LEVEL_1G; | |
303 | if (pud_large(*pud) || !pud_present(*pud)) | |
304 | return (pte_t *)pud; | |
305 | ||
1da177e4 LT |
306 | pmd = pmd_offset(pud, address); |
307 | if (pmd_none(*pmd)) | |
308 | return NULL; | |
30551bb3 TG |
309 | |
310 | *level = PG_LEVEL_2M; | |
9a14aefc | 311 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 312 | return (pte_t *)pmd; |
1da177e4 | 313 | |
30551bb3 | 314 | *level = PG_LEVEL_4K; |
9df84993 | 315 | |
9f4c815c IM |
316 | return pte_offset_kernel(pmd, address); |
317 | } | |
75bb8835 | 318 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 319 | |
9df84993 IM |
320 | /* |
321 | * Set the new pmd in all the pgds we know about: | |
322 | */ | |
9a3dc780 | 323 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 324 | { |
9f4c815c IM |
325 | /* change init_mm */ |
326 | set_pte_atomic(kpte, pte); | |
44af6c41 | 327 | #ifdef CONFIG_X86_32 |
e4b71dcf | 328 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
329 | struct page *page; |
330 | ||
e3ed910d | 331 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
332 | pgd_t *pgd; |
333 | pud_t *pud; | |
334 | pmd_t *pmd; | |
335 | ||
336 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
337 | pud = pud_offset(pgd, address); | |
338 | pmd = pmd_offset(pud, address); | |
339 | set_pte_atomic((pte_t *)pmd, pte); | |
340 | } | |
1da177e4 | 341 | } |
44af6c41 | 342 | #endif |
1da177e4 LT |
343 | } |
344 | ||
9df84993 IM |
345 | static int |
346 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
347 | struct cpa_data *cpa) | |
65e074df | 348 | { |
c31c7d48 | 349 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
350 | pte_t new_pte, old_pte, *tmp; |
351 | pgprot_t old_prot, new_prot; | |
fac84939 | 352 | int i, do_split = 1; |
da7bfc50 | 353 | unsigned int level; |
65e074df | 354 | |
c9caa02c AK |
355 | if (cpa->force_split) |
356 | return 1; | |
357 | ||
65e074df TG |
358 | spin_lock_irqsave(&pgd_lock, flags); |
359 | /* | |
360 | * Check for races, another CPU might have split this page | |
361 | * up already: | |
362 | */ | |
363 | tmp = lookup_address(address, &level); | |
364 | if (tmp != kpte) | |
365 | goto out_unlock; | |
366 | ||
367 | switch (level) { | |
368 | case PG_LEVEL_2M: | |
31422c51 AK |
369 | psize = PMD_PAGE_SIZE; |
370 | pmask = PMD_PAGE_MASK; | |
65e074df | 371 | break; |
f07333fd | 372 | #ifdef CONFIG_X86_64 |
65e074df | 373 | case PG_LEVEL_1G: |
5d3c8b21 AK |
374 | psize = PUD_PAGE_SIZE; |
375 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
376 | break; |
377 | #endif | |
65e074df | 378 | default: |
beaff633 | 379 | do_split = -EINVAL; |
65e074df TG |
380 | goto out_unlock; |
381 | } | |
382 | ||
383 | /* | |
384 | * Calculate the number of pages, which fit into this large | |
385 | * page starting at address: | |
386 | */ | |
387 | nextpage_addr = (address + psize) & pmask; | |
388 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
389 | if (numpages < cpa->numpages) |
390 | cpa->numpages = numpages; | |
65e074df TG |
391 | |
392 | /* | |
393 | * We are safe now. Check whether the new pgprot is the same: | |
394 | */ | |
395 | old_pte = *kpte; | |
396 | old_prot = new_prot = pte_pgprot(old_pte); | |
397 | ||
398 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
399 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
400 | |
401 | /* | |
402 | * old_pte points to the large page base address. So we need | |
403 | * to add the offset of the virtual address: | |
404 | */ | |
405 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
406 | cpa->pfn = pfn; | |
407 | ||
408 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 409 | |
fac84939 TG |
410 | /* |
411 | * We need to check the full range, whether | |
412 | * static_protection() requires a different pgprot for one of | |
413 | * the pages in the range we try to preserve: | |
414 | */ | |
415 | addr = address + PAGE_SIZE; | |
c31c7d48 | 416 | pfn++; |
9b5cf48b | 417 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 418 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
419 | |
420 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
421 | goto out_unlock; | |
422 | } | |
423 | ||
65e074df TG |
424 | /* |
425 | * If there are no changes, return. maxpages has been updated | |
426 | * above: | |
427 | */ | |
428 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 429 | do_split = 0; |
65e074df TG |
430 | goto out_unlock; |
431 | } | |
432 | ||
433 | /* | |
434 | * We need to change the attributes. Check, whether we can | |
435 | * change the large page in one go. We request a split, when | |
436 | * the address is not aligned and the number of pages is | |
437 | * smaller than the number of pages in the large page. Note | |
438 | * that we limited the number of possible pages already to | |
439 | * the number of pages in the large page. | |
440 | */ | |
9b5cf48b | 441 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
442 | /* |
443 | * The address is aligned and the number of pages | |
444 | * covers the full page. | |
445 | */ | |
446 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
447 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 448 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 449 | do_split = 0; |
65e074df TG |
450 | } |
451 | ||
452 | out_unlock: | |
453 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 454 | |
beaff633 | 455 | return do_split; |
65e074df TG |
456 | } |
457 | ||
7afe15b9 | 458 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 459 | { |
7b610eec | 460 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 461 | unsigned int i, level; |
bb5c2dbd | 462 | pte_t *pbase, *tmp; |
9df84993 | 463 | pgprot_t ref_prot; |
ad5ca55f SS |
464 | struct page *base; |
465 | ||
466 | if (!debug_pagealloc) | |
467 | spin_unlock(&cpa_lock); | |
468 | base = alloc_pages(GFP_KERNEL, 0); | |
469 | if (!debug_pagealloc) | |
470 | spin_lock(&cpa_lock); | |
8311eb84 SS |
471 | if (!base) |
472 | return -ENOMEM; | |
bb5c2dbd | 473 | |
eb5b5f02 | 474 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
475 | /* |
476 | * Check for races, another CPU might have split this page | |
477 | * up for us already: | |
478 | */ | |
479 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 480 | if (tmp != kpte) |
bb5c2dbd IM |
481 | goto out_unlock; |
482 | ||
bb5c2dbd | 483 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 484 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 485 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
486 | /* |
487 | * If we ever want to utilize the PAT bit, we need to | |
488 | * update this function to make sure it's converted from | |
489 | * bit 12 to bit 7 when we cross from the 2MB level to | |
490 | * the 4K level: | |
491 | */ | |
492 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 493 | |
f07333fd AK |
494 | #ifdef CONFIG_X86_64 |
495 | if (level == PG_LEVEL_1G) { | |
496 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
497 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
498 | } |
499 | #endif | |
500 | ||
63c1dcf4 TG |
501 | /* |
502 | * Get the target pfn from the original entry: | |
503 | */ | |
504 | pfn = pte_pfn(*kpte); | |
f07333fd | 505 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 506 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 507 | |
ce0c0e50 | 508 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
509 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
510 | split_page_count(level); | |
511 | ||
512 | #ifdef CONFIG_X86_64 | |
513 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
514 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
515 | split_page_count(level); | |
f361a450 | 516 | #endif |
ce0c0e50 | 517 | |
bb5c2dbd | 518 | /* |
07a66d7c | 519 | * Install the new, split up pagetable. |
4c881ca1 | 520 | * |
07a66d7c IM |
521 | * We use the standard kernel pagetable protections for the new |
522 | * pagetable protections, the actual ptes set above control the | |
523 | * primary protection behavior: | |
bb5c2dbd | 524 | */ |
07a66d7c | 525 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
526 | |
527 | /* | |
528 | * Intel Atom errata AAH41 workaround. | |
529 | * | |
530 | * The real fix should be in hw or in a microcode update, but | |
531 | * we also probabilistically try to reduce the window of having | |
532 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
533 | * going on. | |
534 | */ | |
535 | __flush_tlb_all(); | |
536 | ||
bb5c2dbd IM |
537 | base = NULL; |
538 | ||
539 | out_unlock: | |
eb5b5f02 TG |
540 | /* |
541 | * If we dropped out via the lookup_address check under | |
542 | * pgd_lock then stick the page back into the pool: | |
543 | */ | |
8311eb84 SS |
544 | if (base) |
545 | __free_page(base); | |
9a3dc780 | 546 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 547 | |
bb5c2dbd IM |
548 | return 0; |
549 | } | |
550 | ||
a1e46212 SS |
551 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
552 | int primary) | |
553 | { | |
554 | /* | |
555 | * Ignore all non primary paths. | |
556 | */ | |
557 | if (!primary) | |
558 | return 0; | |
559 | ||
560 | /* | |
561 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
562 | * to have holes. | |
563 | * Also set numpages to '1' indicating that we processed cpa req for | |
564 | * one virtual address page and its pfn. TBD: numpages can be set based | |
565 | * on the initial value and the level returned by lookup_address(). | |
566 | */ | |
567 | if (within(vaddr, PAGE_OFFSET, | |
568 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
569 | cpa->numpages = 1; | |
570 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
571 | return 0; | |
572 | } else { | |
573 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
574 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
575 | *cpa->vaddr); | |
576 | ||
577 | return -EFAULT; | |
578 | } | |
579 | } | |
580 | ||
c31c7d48 | 581 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 582 | { |
d75586ad | 583 | unsigned long address; |
da7bfc50 HH |
584 | int do_split, err; |
585 | unsigned int level; | |
c31c7d48 | 586 | pte_t *kpte, old_pte; |
1da177e4 | 587 | |
d75586ad SL |
588 | if (cpa->flags & CPA_ARRAY) |
589 | address = cpa->vaddr[cpa->curpage]; | |
590 | else | |
591 | address = *cpa->vaddr; | |
97f99fed | 592 | repeat: |
f0646e43 | 593 | kpte = lookup_address(address, &level); |
1da177e4 | 594 | if (!kpte) |
a1e46212 | 595 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
596 | |
597 | old_pte = *kpte; | |
a1e46212 SS |
598 | if (!pte_val(old_pte)) |
599 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 600 | |
30551bb3 | 601 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 602 | pte_t new_pte; |
626c2c9d | 603 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 604 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 605 | |
72e458df TG |
606 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
607 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 608 | |
c31c7d48 | 609 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 610 | |
626c2c9d AV |
611 | /* |
612 | * We need to keep the pfn from the existing PTE, | |
613 | * after all we're only going to change it's attributes | |
614 | * not the memory it points to | |
615 | */ | |
c31c7d48 TG |
616 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
617 | cpa->pfn = pfn; | |
f4ae5da0 TG |
618 | /* |
619 | * Do we really change anything ? | |
620 | */ | |
621 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
622 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 623 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 624 | } |
9b5cf48b | 625 | cpa->numpages = 1; |
65e074df | 626 | return 0; |
1da177e4 | 627 | } |
65e074df TG |
628 | |
629 | /* | |
630 | * Check, whether we can keep the large page intact | |
631 | * and just change the pte: | |
632 | */ | |
beaff633 | 633 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
634 | /* |
635 | * When the range fits into the existing large page, | |
9b5cf48b | 636 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
637 | * try_large_page: |
638 | */ | |
87f7f8fe IM |
639 | if (do_split <= 0) |
640 | return do_split; | |
65e074df TG |
641 | |
642 | /* | |
643 | * We have to split the large page: | |
644 | */ | |
87f7f8fe IM |
645 | err = split_large_page(kpte, address); |
646 | if (!err) { | |
ad5ca55f SS |
647 | /* |
648 | * Do a global flush tlb after splitting the large page | |
649 | * and before we do the actual change page attribute in the PTE. | |
650 | * | |
651 | * With out this, we violate the TLB application note, that says | |
652 | * "The TLBs may contain both ordinary and large-page | |
653 | * translations for a 4-KByte range of linear addresses. This | |
654 | * may occur if software modifies the paging structures so that | |
655 | * the page size used for the address range changes. If the two | |
656 | * translations differ with respect to page frame or attributes | |
657 | * (e.g., permissions), processor behavior is undefined and may | |
658 | * be implementation-specific." | |
659 | * | |
660 | * We do this global tlb flush inside the cpa_lock, so that we | |
661 | * don't allow any other cpu, with stale tlb entries change the | |
662 | * page attribute in parallel, that also falls into the | |
663 | * just split large page entry. | |
664 | */ | |
665 | flush_tlb_all(); | |
87f7f8fe IM |
666 | goto repeat; |
667 | } | |
beaff633 | 668 | |
87f7f8fe | 669 | return err; |
9f4c815c | 670 | } |
1da177e4 | 671 | |
c31c7d48 TG |
672 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
673 | ||
674 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 675 | { |
c31c7d48 | 676 | struct cpa_data alias_cpa; |
f34b439f | 677 | int ret = 0; |
d75586ad | 678 | unsigned long temp_cpa_vaddr, vaddr; |
44af6c41 | 679 | |
965194c1 | 680 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 681 | return 0; |
626c2c9d | 682 | |
f361a450 | 683 | #ifdef CONFIG_X86_64 |
965194c1 | 684 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
685 | return 0; |
686 | #endif | |
f34b439f TG |
687 | /* |
688 | * No need to redo, when the primary call touched the direct | |
689 | * mapping already: | |
690 | */ | |
d75586ad SL |
691 | if (cpa->flags & CPA_ARRAY) |
692 | vaddr = cpa->vaddr[cpa->curpage]; | |
693 | else | |
694 | vaddr = *cpa->vaddr; | |
695 | ||
696 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 697 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 698 | |
f34b439f | 699 | alias_cpa = *cpa; |
d75586ad SL |
700 | temp_cpa_vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT); |
701 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
702 | alias_cpa.flags &= ~CPA_ARRAY; | |
703 | ||
f34b439f TG |
704 | |
705 | ret = __change_page_attr_set_clr(&alias_cpa, 0); | |
706 | } | |
44af6c41 | 707 | |
44af6c41 | 708 | #ifdef CONFIG_X86_64 |
c31c7d48 TG |
709 | if (ret) |
710 | return ret; | |
f34b439f TG |
711 | /* |
712 | * No need to redo, when the primary call touched the high | |
713 | * mapping already: | |
714 | */ | |
93dbda7c | 715 | if (within(vaddr, (unsigned long) _text, _brk_end)) |
f34b439f TG |
716 | return 0; |
717 | ||
488fd995 | 718 | /* |
0879750f TG |
719 | * If the physical address is inside the kernel map, we need |
720 | * to touch the high mapped kernel as well: | |
488fd995 | 721 | */ |
c31c7d48 TG |
722 | if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) |
723 | return 0; | |
0879750f | 724 | |
c31c7d48 | 725 | alias_cpa = *cpa; |
d75586ad SL |
726 | temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base; |
727 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
728 | alias_cpa.flags &= ~CPA_ARRAY; | |
c31c7d48 TG |
729 | |
730 | /* | |
731 | * The high mapping range is imprecise, so ignore the return value. | |
732 | */ | |
733 | __change_page_attr_set_clr(&alias_cpa, 0); | |
488fd995 | 734 | #endif |
c31c7d48 | 735 | return ret; |
1da177e4 LT |
736 | } |
737 | ||
c31c7d48 | 738 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 739 | { |
65e074df | 740 | int ret, numpages = cpa->numpages; |
ff31452b | 741 | |
65e074df TG |
742 | while (numpages) { |
743 | /* | |
744 | * Store the remaining nr of pages for the large page | |
745 | * preservation check. | |
746 | */ | |
9b5cf48b | 747 | cpa->numpages = numpages; |
d75586ad SL |
748 | /* for array changes, we can't use large page */ |
749 | if (cpa->flags & CPA_ARRAY) | |
750 | cpa->numpages = 1; | |
c31c7d48 | 751 | |
ad5ca55f SS |
752 | if (!debug_pagealloc) |
753 | spin_lock(&cpa_lock); | |
c31c7d48 | 754 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
755 | if (!debug_pagealloc) |
756 | spin_unlock(&cpa_lock); | |
ff31452b TG |
757 | if (ret) |
758 | return ret; | |
ff31452b | 759 | |
c31c7d48 TG |
760 | if (checkalias) { |
761 | ret = cpa_process_alias(cpa); | |
762 | if (ret) | |
763 | return ret; | |
764 | } | |
765 | ||
65e074df TG |
766 | /* |
767 | * Adjust the number of pages with the result of the | |
768 | * CPA operation. Either a large page has been | |
769 | * preserved or a single page update happened. | |
770 | */ | |
9b5cf48b RW |
771 | BUG_ON(cpa->numpages > numpages); |
772 | numpages -= cpa->numpages; | |
d75586ad SL |
773 | if (cpa->flags & CPA_ARRAY) |
774 | cpa->curpage++; | |
775 | else | |
776 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
777 | ||
65e074df | 778 | } |
ff31452b TG |
779 | return 0; |
780 | } | |
781 | ||
6bb8383b AK |
782 | static inline int cache_attr(pgprot_t attr) |
783 | { | |
784 | return pgprot_val(attr) & | |
785 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
786 | } | |
787 | ||
d75586ad | 788 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 789 | pgprot_t mask_set, pgprot_t mask_clr, |
728c9518 | 790 | int force_split, int in_flag) |
ff31452b | 791 | { |
72e458df | 792 | struct cpa_data cpa; |
cacf8906 | 793 | int ret, cache, checkalias; |
331e4065 TG |
794 | |
795 | /* | |
796 | * Check, if we are requested to change a not supported | |
797 | * feature: | |
798 | */ | |
799 | mask_set = canon_pgprot(mask_set); | |
800 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 801 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
802 | return 0; |
803 | ||
69b1415e | 804 | /* Ensure we are PAGE_SIZE aligned */ |
728c9518 | 805 | if (!(in_flag & CPA_ARRAY)) { |
d75586ad SL |
806 | if (*addr & ~PAGE_MASK) { |
807 | *addr &= PAGE_MASK; | |
808 | /* | |
809 | * People should not be passing in unaligned addresses: | |
810 | */ | |
811 | WARN_ON_ONCE(1); | |
812 | } | |
813 | } else { | |
814 | int i; | |
815 | for (i = 0; i < numpages; i++) { | |
816 | if (addr[i] & ~PAGE_MASK) { | |
817 | addr[i] &= PAGE_MASK; | |
818 | WARN_ON_ONCE(1); | |
819 | } | |
820 | } | |
69b1415e TG |
821 | } |
822 | ||
5843d9a4 NP |
823 | /* Must avoid aliasing mappings in the highmem code */ |
824 | kmap_flush_unused(); | |
825 | ||
db64fe02 NP |
826 | vm_unmap_aliases(); |
827 | ||
7ad9de6a TG |
828 | /* |
829 | * If we're called with lazy mmu updates enabled, the | |
830 | * in-memory pte state may be stale. Flush pending updates to | |
831 | * bring them up to date. | |
832 | */ | |
833 | arch_flush_lazy_mmu_mode(); | |
834 | ||
72e458df TG |
835 | cpa.vaddr = addr; |
836 | cpa.numpages = numpages; | |
837 | cpa.mask_set = mask_set; | |
838 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
839 | cpa.flags = 0; |
840 | cpa.curpage = 0; | |
c9caa02c | 841 | cpa.force_split = force_split; |
72e458df | 842 | |
728c9518 | 843 | if (in_flag & CPA_ARRAY) |
d75586ad SL |
844 | cpa.flags |= CPA_ARRAY; |
845 | ||
af96e443 TG |
846 | /* No alias checking for _NX bit modifications */ |
847 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
848 | ||
849 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 850 | |
f4ae5da0 TG |
851 | /* |
852 | * Check whether we really changed something: | |
853 | */ | |
d75586ad | 854 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 855 | goto out; |
cacf8906 | 856 | |
6bb8383b AK |
857 | /* |
858 | * No need to flush, when we did not set any of the caching | |
859 | * attributes: | |
860 | */ | |
861 | cache = cache_attr(mask_set); | |
862 | ||
57a6a46a TG |
863 | /* |
864 | * On success we use clflush, when the CPU supports it to | |
865 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 866 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
867 | * wbindv): |
868 | */ | |
d75586ad SL |
869 | if (!ret && cpu_has_clflush) { |
870 | if (cpa.flags & CPA_ARRAY) | |
871 | cpa_flush_array(addr, numpages, cache); | |
872 | else | |
873 | cpa_flush_range(*addr, numpages, cache); | |
874 | } else | |
6bb8383b | 875 | cpa_flush_all(cache); |
cacf8906 | 876 | |
4f06b043 JF |
877 | /* |
878 | * If we've been called with lazy mmu updates enabled, then | |
879 | * make sure that everything gets flushed out before we | |
880 | * return. | |
881 | */ | |
882 | arch_flush_lazy_mmu_mode(); | |
883 | ||
76ebd054 | 884 | out: |
ff31452b TG |
885 | return ret; |
886 | } | |
887 | ||
d75586ad SL |
888 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
889 | pgprot_t mask, int array) | |
75cbade8 | 890 | { |
d75586ad | 891 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
728c9518 | 892 | (array ? CPA_ARRAY : 0)); |
75cbade8 AV |
893 | } |
894 | ||
d75586ad SL |
895 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
896 | pgprot_t mask, int array) | |
72932c7a | 897 | { |
d75586ad | 898 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
728c9518 | 899 | (array ? CPA_ARRAY : 0)); |
72932c7a TG |
900 | } |
901 | ||
1219333d | 902 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 903 | { |
de33c442 SS |
904 | /* |
905 | * for now UC MINUS. see comments in ioremap_nocache() | |
906 | */ | |
d75586ad SL |
907 | return change_page_attr_set(&addr, numpages, |
908 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 909 | } |
1219333d | 910 | |
911 | int set_memory_uc(unsigned long addr, int numpages) | |
912 | { | |
de33c442 SS |
913 | /* |
914 | * for now UC MINUS. see comments in ioremap_nocache() | |
915 | */ | |
c15238df | 916 | if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
de33c442 | 917 | _PAGE_CACHE_UC_MINUS, NULL)) |
1219333d | 918 | return -EINVAL; |
919 | ||
920 | return _set_memory_uc(addr, numpages); | |
921 | } | |
75cbade8 AV |
922 | EXPORT_SYMBOL(set_memory_uc); |
923 | ||
d75586ad SL |
924 | int set_memory_array_uc(unsigned long *addr, int addrinarray) |
925 | { | |
c5e147cf RH |
926 | unsigned long start; |
927 | unsigned long end; | |
d75586ad SL |
928 | int i; |
929 | /* | |
930 | * for now UC MINUS. see comments in ioremap_nocache() | |
931 | */ | |
932 | for (i = 0; i < addrinarray; i++) { | |
c5e147cf RH |
933 | start = __pa(addr[i]); |
934 | for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { | |
935 | if (end != __pa(addr[i + 1])) | |
936 | break; | |
937 | i++; | |
938 | } | |
939 | if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL)) | |
d75586ad SL |
940 | goto out; |
941 | } | |
942 | ||
943 | return change_page_attr_set(addr, addrinarray, | |
944 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); | |
945 | out: | |
c5e147cf RH |
946 | for (i = 0; i < addrinarray; i++) { |
947 | unsigned long tmp = __pa(addr[i]); | |
948 | ||
949 | if (tmp == start) | |
950 | break; | |
01de05af | 951 | for (end = tmp + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { |
c5e147cf RH |
952 | if (end != __pa(addr[i + 1])) |
953 | break; | |
954 | i++; | |
955 | } | |
956 | free_memtype(tmp, end); | |
957 | } | |
d75586ad SL |
958 | return -EINVAL; |
959 | } | |
960 | EXPORT_SYMBOL(set_memory_array_uc); | |
961 | ||
ef354af4 | 962 | int _set_memory_wc(unsigned long addr, int numpages) |
963 | { | |
d75586ad SL |
964 | return change_page_attr_set(&addr, numpages, |
965 | __pgprot(_PAGE_CACHE_WC), 0); | |
ef354af4 | 966 | } |
967 | ||
968 | int set_memory_wc(unsigned long addr, int numpages) | |
969 | { | |
499f8f84 | 970 | if (!pat_enabled) |
ef354af4 | 971 | return set_memory_uc(addr, numpages); |
972 | ||
c15238df | 973 | if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
ef354af4 | 974 | _PAGE_CACHE_WC, NULL)) |
975 | return -EINVAL; | |
976 | ||
977 | return _set_memory_wc(addr, numpages); | |
978 | } | |
979 | EXPORT_SYMBOL(set_memory_wc); | |
980 | ||
1219333d | 981 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 982 | { |
d75586ad SL |
983 | return change_page_attr_clear(&addr, numpages, |
984 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 985 | } |
1219333d | 986 | |
987 | int set_memory_wb(unsigned long addr, int numpages) | |
988 | { | |
c15238df | 989 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
1219333d | 990 | |
991 | return _set_memory_wb(addr, numpages); | |
992 | } | |
75cbade8 AV |
993 | EXPORT_SYMBOL(set_memory_wb); |
994 | ||
d75586ad SL |
995 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
996 | { | |
997 | int i; | |
d75586ad | 998 | |
c5e147cf RH |
999 | for (i = 0; i < addrinarray; i++) { |
1000 | unsigned long start = __pa(addr[i]); | |
1001 | unsigned long end; | |
1002 | ||
1003 | for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { | |
1004 | if (end != __pa(addr[i + 1])) | |
1005 | break; | |
1006 | i++; | |
1007 | } | |
1008 | free_memtype(start, end); | |
1009 | } | |
d75586ad SL |
1010 | return change_page_attr_clear(addr, addrinarray, |
1011 | __pgprot(_PAGE_CACHE_MASK), 1); | |
1012 | } | |
1013 | EXPORT_SYMBOL(set_memory_array_wb); | |
1014 | ||
75cbade8 AV |
1015 | int set_memory_x(unsigned long addr, int numpages) |
1016 | { | |
d75586ad | 1017 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1018 | } |
1019 | EXPORT_SYMBOL(set_memory_x); | |
1020 | ||
1021 | int set_memory_nx(unsigned long addr, int numpages) | |
1022 | { | |
d75586ad | 1023 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1024 | } |
1025 | EXPORT_SYMBOL(set_memory_nx); | |
1026 | ||
1027 | int set_memory_ro(unsigned long addr, int numpages) | |
1028 | { | |
d75586ad | 1029 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1030 | } |
a03352d2 | 1031 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1032 | |
1033 | int set_memory_rw(unsigned long addr, int numpages) | |
1034 | { | |
d75586ad | 1035 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1036 | } |
a03352d2 | 1037 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1038 | |
1039 | int set_memory_np(unsigned long addr, int numpages) | |
1040 | { | |
d75586ad | 1041 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1042 | } |
75cbade8 | 1043 | |
c9caa02c AK |
1044 | int set_memory_4k(unsigned long addr, int numpages) |
1045 | { | |
d75586ad SL |
1046 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
1047 | __pgprot(0), 1, 0); | |
c9caa02c AK |
1048 | } |
1049 | ||
75cbade8 AV |
1050 | int set_pages_uc(struct page *page, int numpages) |
1051 | { | |
1052 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1053 | |
d7c8f21a | 1054 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1055 | } |
1056 | EXPORT_SYMBOL(set_pages_uc); | |
1057 | ||
1058 | int set_pages_wb(struct page *page, int numpages) | |
1059 | { | |
1060 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1061 | |
d7c8f21a | 1062 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1063 | } |
1064 | EXPORT_SYMBOL(set_pages_wb); | |
1065 | ||
1066 | int set_pages_x(struct page *page, int numpages) | |
1067 | { | |
1068 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1069 | |
d7c8f21a | 1070 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1071 | } |
1072 | EXPORT_SYMBOL(set_pages_x); | |
1073 | ||
1074 | int set_pages_nx(struct page *page, int numpages) | |
1075 | { | |
1076 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1077 | |
d7c8f21a | 1078 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1079 | } |
1080 | EXPORT_SYMBOL(set_pages_nx); | |
1081 | ||
1082 | int set_pages_ro(struct page *page, int numpages) | |
1083 | { | |
1084 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1085 | |
d7c8f21a | 1086 | return set_memory_ro(addr, numpages); |
75cbade8 | 1087 | } |
75cbade8 AV |
1088 | |
1089 | int set_pages_rw(struct page *page, int numpages) | |
1090 | { | |
1091 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1092 | |
d7c8f21a | 1093 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1094 | } |
1095 | ||
1da177e4 | 1096 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1097 | |
1098 | static int __set_pages_p(struct page *page, int numpages) | |
1099 | { | |
d75586ad SL |
1100 | unsigned long tempaddr = (unsigned long) page_address(page); |
1101 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1102 | .numpages = numpages, |
1103 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1104 | .mask_clr = __pgprot(0), |
1105 | .flags = 0}; | |
72932c7a | 1106 | |
55121b43 SS |
1107 | /* |
1108 | * No alias checking needed for setting present flag. otherwise, | |
1109 | * we may need to break large pages for 64-bit kernel text | |
1110 | * mappings (this adds to complexity if we want to do this from | |
1111 | * atomic context especially). Let's keep it simple! | |
1112 | */ | |
1113 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1114 | } |
1115 | ||
1116 | static int __set_pages_np(struct page *page, int numpages) | |
1117 | { | |
d75586ad SL |
1118 | unsigned long tempaddr = (unsigned long) page_address(page); |
1119 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1120 | .numpages = numpages, |
1121 | .mask_set = __pgprot(0), | |
d75586ad SL |
1122 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1123 | .flags = 0}; | |
72932c7a | 1124 | |
55121b43 SS |
1125 | /* |
1126 | * No alias checking needed for setting not present flag. otherwise, | |
1127 | * we may need to break large pages for 64-bit kernel text | |
1128 | * mappings (this adds to complexity if we want to do this from | |
1129 | * atomic context especially). Let's keep it simple! | |
1130 | */ | |
1131 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1132 | } |
1133 | ||
1da177e4 LT |
1134 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1135 | { | |
1136 | if (PageHighMem(page)) | |
1137 | return; | |
9f4c815c | 1138 | if (!enable) { |
f9b8404c IM |
1139 | debug_check_no_locks_freed(page_address(page), |
1140 | numpages * PAGE_SIZE); | |
9f4c815c | 1141 | } |
de5097c2 | 1142 | |
12d6f21e IM |
1143 | /* |
1144 | * If page allocator is not up yet then do not call c_p_a(): | |
1145 | */ | |
1146 | if (!debug_pagealloc_enabled) | |
1147 | return; | |
1148 | ||
9f4c815c | 1149 | /* |
f8d8406b | 1150 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1151 | * Large pages for identity mappings are not used at boot time |
1152 | * and hence no memory allocations during large page split. | |
1da177e4 | 1153 | */ |
f62d0f00 IM |
1154 | if (enable) |
1155 | __set_pages_p(page, numpages); | |
1156 | else | |
1157 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1158 | |
1159 | /* | |
e4b71dcf IM |
1160 | * We should perform an IPI and flush all tlbs, |
1161 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1162 | */ |
1163 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1164 | } |
1165 | ||
8a235efa RW |
1166 | #ifdef CONFIG_HIBERNATION |
1167 | ||
1168 | bool kernel_page_present(struct page *page) | |
1169 | { | |
1170 | unsigned int level; | |
1171 | pte_t *pte; | |
1172 | ||
1173 | if (PageHighMem(page)) | |
1174 | return false; | |
1175 | ||
1176 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1177 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1178 | } | |
1179 | ||
1180 | #endif /* CONFIG_HIBERNATION */ | |
1181 | ||
1182 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1183 | |
1184 | /* | |
1185 | * The testcases use internal knowledge of the implementation that shouldn't | |
1186 | * be exposed to the rest of the kernel. Include these directly here. | |
1187 | */ | |
1188 | #ifdef CONFIG_CPA_DEBUG | |
1189 | #include "pageattr-test.c" | |
1190 | #endif |