Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
9f4c815c | 7 | #include <linux/sched.h> |
9f4c815c | 8 | #include <linux/mm.h> |
76ebd054 | 9 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
10 | #include <linux/seq_file.h> |
11 | #include <linux/debugfs.h> | |
e59a1bb2 | 12 | #include <linux/pfn.h> |
8c4bfc6e | 13 | #include <linux/percpu.h> |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
5bd5a452 | 15 | #include <linux/pci.h> |
d6472302 | 16 | #include <linux/vmalloc.h> |
9f4c815c | 17 | |
66441bd3 | 18 | #include <asm/e820/api.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
7c0f6ba6 | 23 | #include <linux/uaccess.h> |
9f4c815c | 24 | #include <asm/pgalloc.h> |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
d1163651 | 27 | #include <asm/set_memory.h> |
1da177e4 | 28 | |
9df84993 IM |
29 | /* |
30 | * The current flushing context - we pass it instead of 5 arguments: | |
31 | */ | |
72e458df | 32 | struct cpa_data { |
d75586ad | 33 | unsigned long *vaddr; |
0fd64c23 | 34 | pgd_t *pgd; |
72e458df TG |
35 | pgprot_t mask_set; |
36 | pgprot_t mask_clr; | |
74256377 | 37 | unsigned long numpages; |
d75586ad | 38 | int flags; |
c31c7d48 | 39 | unsigned long pfn; |
c9caa02c | 40 | unsigned force_split : 1; |
d75586ad | 41 | int curpage; |
9ae28475 | 42 | struct page **pages; |
72e458df TG |
43 | }; |
44 | ||
ad5ca55f SS |
45 | /* |
46 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
47 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
48 | * entries change the page attribute in parallel to some other cpu | |
49 | * splitting a large page entry along with changing the attribute. | |
50 | */ | |
51 | static DEFINE_SPINLOCK(cpa_lock); | |
52 | ||
d75586ad SL |
53 | #define CPA_FLUSHTLB 1 |
54 | #define CPA_ARRAY 2 | |
9ae28475 | 55 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 56 | |
65280e61 | 57 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
58 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
59 | ||
65280e61 | 60 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 61 | { |
ce0c0e50 | 62 | /* Protect against CPA */ |
a79e53d8 | 63 | spin_lock(&pgd_lock); |
ce0c0e50 | 64 | direct_pages_count[level] += pages; |
a79e53d8 | 65 | spin_unlock(&pgd_lock); |
65280e61 TG |
66 | } |
67 | ||
68 | static void split_page_count(int level) | |
69 | { | |
c9e0d391 DJ |
70 | if (direct_pages_count[level] == 0) |
71 | return; | |
72 | ||
65280e61 TG |
73 | direct_pages_count[level]--; |
74 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
75 | } | |
76 | ||
e1759c21 | 77 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 78 | { |
b9c3bfc2 | 79 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
80 | direct_pages_count[PG_LEVEL_4K] << 2); |
81 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 82 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
83 | direct_pages_count[PG_LEVEL_2M] << 11); |
84 | #else | |
b9c3bfc2 | 85 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
86 | direct_pages_count[PG_LEVEL_2M] << 12); |
87 | #endif | |
a06de630 | 88 | if (direct_gbpages) |
b9c3bfc2 | 89 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 90 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 | 91 | } |
65280e61 TG |
92 | #else |
93 | static inline void split_page_count(int level) { } | |
94 | #endif | |
ce0c0e50 | 95 | |
58e65b51 DH |
96 | static inline int |
97 | within(unsigned long addr, unsigned long start, unsigned long end) | |
98 | { | |
99 | return addr >= start && addr < end; | |
100 | } | |
101 | ||
102 | static inline int | |
103 | within_inclusive(unsigned long addr, unsigned long start, unsigned long end) | |
104 | { | |
105 | return addr >= start && addr <= end; | |
106 | } | |
107 | ||
c31c7d48 TG |
108 | #ifdef CONFIG_X86_64 |
109 | ||
110 | static inline unsigned long highmap_start_pfn(void) | |
111 | { | |
fc8d7826 | 112 | return __pa_symbol(_text) >> PAGE_SHIFT; |
c31c7d48 TG |
113 | } |
114 | ||
115 | static inline unsigned long highmap_end_pfn(void) | |
116 | { | |
4ff53087 TG |
117 | /* Do not reference physical address outside the kernel. */ |
118 | return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT; | |
c31c7d48 TG |
119 | } |
120 | ||
58e65b51 | 121 | static bool __cpa_pfn_in_highmap(unsigned long pfn) |
687c4825 | 122 | { |
58e65b51 DH |
123 | /* |
124 | * Kernel text has an alias mapping at a high address, known | |
125 | * here as "highmap". | |
126 | */ | |
127 | return within_inclusive(pfn, highmap_start_pfn(), highmap_end_pfn()); | |
ed724be6 AV |
128 | } |
129 | ||
58e65b51 DH |
130 | #else |
131 | ||
132 | static bool __cpa_pfn_in_highmap(unsigned long pfn) | |
4ff53087 | 133 | { |
58e65b51 DH |
134 | /* There is no highmap on 32-bit */ |
135 | return false; | |
4ff53087 TG |
136 | } |
137 | ||
58e65b51 DH |
138 | #endif |
139 | ||
d7c8f21a TG |
140 | /* |
141 | * Flushing functions | |
142 | */ | |
cd8ddf1a | 143 | |
cd8ddf1a TG |
144 | /** |
145 | * clflush_cache_range - flush a cache range with clflush | |
9efc31b8 | 146 | * @vaddr: virtual start address |
cd8ddf1a TG |
147 | * @size: number of bytes to flush |
148 | * | |
8b80fd8b RZ |
149 | * clflushopt is an unordered instruction which needs fencing with mfence or |
150 | * sfence to avoid ordering issues. | |
cd8ddf1a | 151 | */ |
4c61afcd | 152 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 153 | { |
1f1a89ac CW |
154 | const unsigned long clflush_size = boot_cpu_data.x86_clflush_size; |
155 | void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1)); | |
6c434d61 | 156 | void *vend = vaddr + size; |
1f1a89ac CW |
157 | |
158 | if (p >= vend) | |
159 | return; | |
d7c8f21a | 160 | |
cd8ddf1a | 161 | mb(); |
4c61afcd | 162 | |
1f1a89ac | 163 | for (; p < vend; p += clflush_size) |
6c434d61 | 164 | clflushopt(p); |
4c61afcd | 165 | |
cd8ddf1a | 166 | mb(); |
d7c8f21a | 167 | } |
e517a5e9 | 168 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 169 | |
f2b61257 DW |
170 | void arch_invalidate_pmem(void *addr, size_t size) |
171 | { | |
172 | clflush_cache_range(addr, size); | |
173 | } | |
174 | EXPORT_SYMBOL_GPL(arch_invalidate_pmem); | |
175 | ||
af1e6844 | 176 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 177 | { |
6bb8383b AK |
178 | unsigned long cache = (unsigned long)arg; |
179 | ||
d7c8f21a TG |
180 | /* |
181 | * Flush all to work around Errata in early athlons regarding | |
182 | * large page flushing. | |
183 | */ | |
184 | __flush_tlb_all(); | |
185 | ||
0b827537 | 186 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
187 | wbinvd(); |
188 | } | |
189 | ||
6bb8383b | 190 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a | 191 | { |
d2479a30 | 192 | BUG_ON(irqs_disabled() && !early_boot_irqs_disabled); |
d7c8f21a | 193 | |
15c8b6c1 | 194 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
195 | } |
196 | ||
57a6a46a TG |
197 | static void __cpa_flush_range(void *arg) |
198 | { | |
57a6a46a TG |
199 | /* |
200 | * We could optimize that further and do individual per page | |
201 | * tlb invalidates for a low number of pages. Caveat: we must | |
202 | * flush the high aliases on 64bit as well. | |
203 | */ | |
204 | __flush_tlb_all(); | |
57a6a46a TG |
205 | } |
206 | ||
6bb8383b | 207 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 208 | { |
4c61afcd IM |
209 | unsigned int i, level; |
210 | unsigned long addr; | |
211 | ||
a53276e2 | 212 | BUG_ON(irqs_disabled() && !early_boot_irqs_disabled); |
4c61afcd | 213 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 214 | |
15c8b6c1 | 215 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 216 | |
6bb8383b AK |
217 | if (!cache) |
218 | return; | |
219 | ||
3b233e52 TG |
220 | /* |
221 | * We only need to flush on one CPU, | |
222 | * clflush is a MESI-coherent instruction that | |
223 | * will cause all other CPUs to flush the same | |
224 | * cachelines: | |
225 | */ | |
4c61afcd IM |
226 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
227 | pte_t *pte = lookup_address(addr, &level); | |
228 | ||
229 | /* | |
230 | * Only flush present addresses: | |
231 | */ | |
7bfb72e8 | 232 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
233 | clflush_cache_range((void *) addr, PAGE_SIZE); |
234 | } | |
57a6a46a TG |
235 | } |
236 | ||
9ae28475 | 237 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
238 | int in_flags, struct page **pages) | |
d75586ad SL |
239 | { |
240 | unsigned int i, level; | |
459fbe00 JO |
241 | #ifdef CONFIG_PREEMPT |
242 | /* | |
243 | * Avoid wbinvd() because it causes latencies on all CPUs, | |
244 | * regardless of any CPU isolation that may be in effect. | |
245 | * | |
246 | * This should be extended for CAT enabled systems independent of | |
247 | * PREEMPT because wbinvd() does not respect the CAT partitions and | |
248 | * this is exposed to unpriviledged users through the graphics | |
249 | * subsystem. | |
250 | */ | |
251 | unsigned long do_wbinvd = 0; | |
252 | #else | |
2171787b | 253 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
459fbe00 | 254 | #endif |
d75586ad | 255 | |
d2479a30 | 256 | BUG_ON(irqs_disabled() && !early_boot_irqs_disabled); |
d75586ad | 257 | |
2171787b | 258 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 259 | |
2171787b | 260 | if (!cache || do_wbinvd) |
d75586ad SL |
261 | return; |
262 | ||
d75586ad SL |
263 | /* |
264 | * We only need to flush on one CPU, | |
265 | * clflush is a MESI-coherent instruction that | |
266 | * will cause all other CPUs to flush the same | |
267 | * cachelines: | |
268 | */ | |
9ae28475 | 269 | for (i = 0; i < numpages; i++) { |
270 | unsigned long addr; | |
271 | pte_t *pte; | |
272 | ||
273 | if (in_flags & CPA_PAGES_ARRAY) | |
274 | addr = (unsigned long)page_address(pages[i]); | |
275 | else | |
276 | addr = start[i]; | |
277 | ||
278 | pte = lookup_address(addr, &level); | |
d75586ad SL |
279 | |
280 | /* | |
281 | * Only flush present addresses: | |
282 | */ | |
283 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 284 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
285 | } |
286 | } | |
287 | ||
ed724be6 AV |
288 | /* |
289 | * Certain areas of memory on x86 require very specific protection flags, | |
290 | * for example the BIOS area or kernel text. Callers don't always get this | |
291 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
292 | * checks and fixes these known static required protection bits. | |
293 | */ | |
c31c7d48 TG |
294 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
295 | unsigned long pfn) | |
ed724be6 AV |
296 | { |
297 | pgprot_t forbidden = __pgprot(0); | |
298 | ||
687c4825 | 299 | /* |
ed724be6 AV |
300 | * The BIOS area between 640k and 1Mb needs to be executable for |
301 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 302 | */ |
5bd5a452 MC |
303 | #ifdef CONFIG_PCI_BIOS |
304 | if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) | |
ed724be6 | 305 | pgprot_val(forbidden) |= _PAGE_NX; |
5bd5a452 | 306 | #endif |
ed724be6 AV |
307 | |
308 | /* | |
309 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
310 | * Does not cover __inittext since that is gone later on. On |
311 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
312 | */ |
313 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
314 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 315 | |
cc0f21bb | 316 | /* |
c31c7d48 | 317 | * The .rodata section needs to be read-only. Using the pfn |
639d6aaf DH |
318 | * catches all aliases. This also includes __ro_after_init, |
319 | * so do not enforce until kernel_set_to_readonly is true. | |
cc0f21bb | 320 | */ |
639d6aaf DH |
321 | if (kernel_set_to_readonly && |
322 | within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT, | |
fc8d7826 | 323 | __pa_symbol(__end_rodata) >> PAGE_SHIFT)) |
cc0f21bb | 324 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 325 | |
9ccaf77c | 326 | #if defined(CONFIG_X86_64) |
74e08179 | 327 | /* |
502f6604 SS |
328 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
329 | * kernel text mappings for the large page aligned text, rodata sections | |
330 | * will be always read-only. For the kernel identity mappings covering | |
331 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
332 | * |
333 | * This will preserve the large page mappings for kernel text/data | |
334 | * at no extra cost. | |
335 | */ | |
502f6604 SS |
336 | if (kernel_set_to_readonly && |
337 | within(address, (unsigned long)_text, | |
281ff33b SS |
338 | (unsigned long)__end_rodata_hpage_align)) { |
339 | unsigned int level; | |
340 | ||
341 | /* | |
342 | * Don't enforce the !RW mapping for the kernel text mapping, | |
343 | * if the current mapping is already using small page mapping. | |
344 | * No need to work hard to preserve large page mappings in this | |
345 | * case. | |
346 | * | |
347 | * This also fixes the Linux Xen paravirt guest boot failure | |
348 | * (because of unexpected read-only mappings for kernel identity | |
349 | * mappings). In this paravirt guest case, the kernel text | |
350 | * mapping and the kernel identity mapping share the same | |
351 | * page-table pages. Thus we can't really use different | |
352 | * protections for the kernel text and identity mappings. Also, | |
353 | * these shared mappings are made of small page mappings. | |
354 | * Thus this don't enforce !RW mapping for small page kernel | |
355 | * text mapping logic will help Linux Xen parvirt guest boot | |
0d2eb44f | 356 | * as well. |
281ff33b SS |
357 | */ |
358 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
359 | pgprot_val(forbidden) |= _PAGE_RW; | |
360 | } | |
74e08179 SS |
361 | #endif |
362 | ||
ed724be6 | 363 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
364 | |
365 | return prot; | |
366 | } | |
367 | ||
426e34cc MF |
368 | /* |
369 | * Lookup the page table entry for a virtual address in a specific pgd. | |
370 | * Return a pointer to the entry and the level of the mapping. | |
371 | */ | |
372 | pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, | |
373 | unsigned int *level) | |
9f4c815c | 374 | { |
45478336 | 375 | p4d_t *p4d; |
1da177e4 LT |
376 | pud_t *pud; |
377 | pmd_t *pmd; | |
9f4c815c | 378 | |
30551bb3 TG |
379 | *level = PG_LEVEL_NONE; |
380 | ||
1da177e4 LT |
381 | if (pgd_none(*pgd)) |
382 | return NULL; | |
9df84993 | 383 | |
45478336 KS |
384 | p4d = p4d_offset(pgd, address); |
385 | if (p4d_none(*p4d)) | |
386 | return NULL; | |
387 | ||
388 | *level = PG_LEVEL_512G; | |
389 | if (p4d_large(*p4d) || !p4d_present(*p4d)) | |
390 | return (pte_t *)p4d; | |
391 | ||
392 | pud = pud_offset(p4d, address); | |
1da177e4 LT |
393 | if (pud_none(*pud)) |
394 | return NULL; | |
c2f71ee2 AK |
395 | |
396 | *level = PG_LEVEL_1G; | |
397 | if (pud_large(*pud) || !pud_present(*pud)) | |
398 | return (pte_t *)pud; | |
399 | ||
1da177e4 LT |
400 | pmd = pmd_offset(pud, address); |
401 | if (pmd_none(*pmd)) | |
402 | return NULL; | |
30551bb3 TG |
403 | |
404 | *level = PG_LEVEL_2M; | |
9a14aefc | 405 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 406 | return (pte_t *)pmd; |
1da177e4 | 407 | |
30551bb3 | 408 | *level = PG_LEVEL_4K; |
9df84993 | 409 | |
9f4c815c IM |
410 | return pte_offset_kernel(pmd, address); |
411 | } | |
0fd64c23 BP |
412 | |
413 | /* | |
414 | * Lookup the page table entry for a virtual address. Return a pointer | |
415 | * to the entry and the level of the mapping. | |
416 | * | |
417 | * Note: We return pud and pmd either when the entry is marked large | |
418 | * or when the present bit is not set. Otherwise we would return a | |
419 | * pointer to a nonexisting mapping. | |
420 | */ | |
421 | pte_t *lookup_address(unsigned long address, unsigned int *level) | |
422 | { | |
426e34cc | 423 | return lookup_address_in_pgd(pgd_offset_k(address), address, level); |
0fd64c23 | 424 | } |
75bb8835 | 425 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 426 | |
0fd64c23 BP |
427 | static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address, |
428 | unsigned int *level) | |
429 | { | |
430 | if (cpa->pgd) | |
426e34cc | 431 | return lookup_address_in_pgd(cpa->pgd + pgd_index(address), |
0fd64c23 BP |
432 | address, level); |
433 | ||
434 | return lookup_address(address, level); | |
435 | } | |
436 | ||
792230c3 JG |
437 | /* |
438 | * Lookup the PMD entry for a virtual address. Return a pointer to the entry | |
439 | * or NULL if not present. | |
440 | */ | |
441 | pmd_t *lookup_pmd_address(unsigned long address) | |
442 | { | |
443 | pgd_t *pgd; | |
45478336 | 444 | p4d_t *p4d; |
792230c3 JG |
445 | pud_t *pud; |
446 | ||
447 | pgd = pgd_offset_k(address); | |
448 | if (pgd_none(*pgd)) | |
449 | return NULL; | |
450 | ||
45478336 KS |
451 | p4d = p4d_offset(pgd, address); |
452 | if (p4d_none(*p4d) || p4d_large(*p4d) || !p4d_present(*p4d)) | |
453 | return NULL; | |
454 | ||
455 | pud = pud_offset(p4d, address); | |
792230c3 JG |
456 | if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud)) |
457 | return NULL; | |
458 | ||
459 | return pmd_offset(pud, address); | |
460 | } | |
461 | ||
d7656534 DH |
462 | /* |
463 | * This is necessary because __pa() does not work on some | |
464 | * kinds of memory, like vmalloc() or the alloc_remap() | |
465 | * areas on 32-bit NUMA systems. The percpu areas can | |
466 | * end up in this kind of memory, for instance. | |
467 | * | |
468 | * This could be optimized, but it is only intended to be | |
469 | * used at inititalization time, and keeping it | |
470 | * unoptimized should increase the testing coverage for | |
471 | * the more obscure platforms. | |
472 | */ | |
473 | phys_addr_t slow_virt_to_phys(void *__virt_addr) | |
474 | { | |
475 | unsigned long virt_addr = (unsigned long)__virt_addr; | |
bf70e551 DC |
476 | phys_addr_t phys_addr; |
477 | unsigned long offset; | |
d7656534 | 478 | enum pg_level level; |
d7656534 DH |
479 | pte_t *pte; |
480 | ||
481 | pte = lookup_address(virt_addr, &level); | |
482 | BUG_ON(!pte); | |
34437e67 | 483 | |
bf70e551 DC |
484 | /* |
485 | * pXX_pfn() returns unsigned long, which must be cast to phys_addr_t | |
486 | * before being left-shifted PAGE_SHIFT bits -- this trick is to | |
487 | * make 32-PAE kernel work correctly. | |
488 | */ | |
34437e67 TK |
489 | switch (level) { |
490 | case PG_LEVEL_1G: | |
bf70e551 | 491 | phys_addr = (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
492 | offset = virt_addr & ~PUD_PAGE_MASK; |
493 | break; | |
494 | case PG_LEVEL_2M: | |
bf70e551 | 495 | phys_addr = (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
496 | offset = virt_addr & ~PMD_PAGE_MASK; |
497 | break; | |
498 | default: | |
bf70e551 | 499 | phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT; |
34437e67 TK |
500 | offset = virt_addr & ~PAGE_MASK; |
501 | } | |
502 | ||
503 | return (phys_addr_t)(phys_addr | offset); | |
d7656534 DH |
504 | } |
505 | EXPORT_SYMBOL_GPL(slow_virt_to_phys); | |
506 | ||
9df84993 IM |
507 | /* |
508 | * Set the new pmd in all the pgds we know about: | |
509 | */ | |
9a3dc780 | 510 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 511 | { |
9f4c815c IM |
512 | /* change init_mm */ |
513 | set_pte_atomic(kpte, pte); | |
44af6c41 | 514 | #ifdef CONFIG_X86_32 |
e4b71dcf | 515 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
516 | struct page *page; |
517 | ||
e3ed910d | 518 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 | 519 | pgd_t *pgd; |
45478336 | 520 | p4d_t *p4d; |
44af6c41 IM |
521 | pud_t *pud; |
522 | pmd_t *pmd; | |
523 | ||
524 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
45478336 KS |
525 | p4d = p4d_offset(pgd, address); |
526 | pud = pud_offset(p4d, address); | |
44af6c41 IM |
527 | pmd = pmd_offset(pud, address); |
528 | set_pte_atomic((pte_t *)pmd, pte); | |
529 | } | |
1da177e4 | 530 | } |
44af6c41 | 531 | #endif |
1da177e4 LT |
532 | } |
533 | ||
d1440b23 DH |
534 | static pgprot_t pgprot_clear_protnone_bits(pgprot_t prot) |
535 | { | |
536 | /* | |
537 | * _PAGE_GLOBAL means "global page" for present PTEs. | |
538 | * But, it is also used to indicate _PAGE_PROTNONE | |
539 | * for non-present PTEs. | |
540 | * | |
541 | * This ensures that a _PAGE_GLOBAL PTE going from | |
542 | * present to non-present is not confused as | |
543 | * _PAGE_PROTNONE. | |
544 | */ | |
545 | if (!(pgprot_val(prot) & _PAGE_PRESENT)) | |
546 | pgprot_val(prot) &= ~_PAGE_GLOBAL; | |
547 | ||
548 | return prot; | |
549 | } | |
550 | ||
9df84993 IM |
551 | static int |
552 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
553 | struct cpa_data *cpa) | |
65e074df | 554 | { |
3a19109e | 555 | unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn, old_pfn; |
65e074df | 556 | pte_t new_pte, old_pte, *tmp; |
64edc8ed | 557 | pgprot_t old_prot, new_prot, req_prot; |
fac84939 | 558 | int i, do_split = 1; |
f3c4fbb6 | 559 | enum pg_level level; |
65e074df | 560 | |
c9caa02c AK |
561 | if (cpa->force_split) |
562 | return 1; | |
563 | ||
a79e53d8 | 564 | spin_lock(&pgd_lock); |
65e074df TG |
565 | /* |
566 | * Check for races, another CPU might have split this page | |
567 | * up already: | |
568 | */ | |
82f0712c | 569 | tmp = _lookup_address_cpa(cpa, address, &level); |
65e074df TG |
570 | if (tmp != kpte) |
571 | goto out_unlock; | |
572 | ||
573 | switch (level) { | |
574 | case PG_LEVEL_2M: | |
3a19109e TK |
575 | old_prot = pmd_pgprot(*(pmd_t *)kpte); |
576 | old_pfn = pmd_pfn(*(pmd_t *)kpte); | |
577 | break; | |
65e074df | 578 | case PG_LEVEL_1G: |
3a19109e TK |
579 | old_prot = pud_pgprot(*(pud_t *)kpte); |
580 | old_pfn = pud_pfn(*(pud_t *)kpte); | |
f3c4fbb6 | 581 | break; |
65e074df | 582 | default: |
beaff633 | 583 | do_split = -EINVAL; |
65e074df TG |
584 | goto out_unlock; |
585 | } | |
586 | ||
3a19109e TK |
587 | psize = page_level_size(level); |
588 | pmask = page_level_mask(level); | |
589 | ||
65e074df TG |
590 | /* |
591 | * Calculate the number of pages, which fit into this large | |
592 | * page starting at address: | |
593 | */ | |
594 | nextpage_addr = (address + psize) & pmask; | |
595 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
596 | if (numpages < cpa->numpages) |
597 | cpa->numpages = numpages; | |
65e074df TG |
598 | |
599 | /* | |
600 | * We are safe now. Check whether the new pgprot is the same: | |
f5b2831d JG |
601 | * Convert protection attributes to 4k-format, as cpa->mask* are set |
602 | * up accordingly. | |
65e074df TG |
603 | */ |
604 | old_pte = *kpte; | |
606c7193 | 605 | /* Clear PSE (aka _PAGE_PAT) and move PAT bit to correct position */ |
55696b1f | 606 | req_prot = pgprot_large_2_4k(old_prot); |
65e074df | 607 | |
64edc8ed | 608 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
609 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 | 610 | |
f5b2831d JG |
611 | /* |
612 | * req_prot is in format of 4k pages. It must be converted to large | |
613 | * page format: the caching mode includes the PAT bit located at | |
614 | * different bit positions in the two formats. | |
615 | */ | |
616 | req_prot = pgprot_4k_2_large(req_prot); | |
d1440b23 | 617 | req_prot = pgprot_clear_protnone_bits(req_prot); |
f76cfa3c | 618 | if (pgprot_val(req_prot) & _PAGE_PRESENT) |
d1440b23 | 619 | pgprot_val(req_prot) |= _PAGE_PSE; |
a8aed3e0 | 620 | |
c31c7d48 | 621 | /* |
3a19109e | 622 | * old_pfn points to the large page base pfn. So we need |
c31c7d48 TG |
623 | * to add the offset of the virtual address: |
624 | */ | |
3a19109e | 625 | pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT); |
c31c7d48 TG |
626 | cpa->pfn = pfn; |
627 | ||
64edc8ed | 628 | new_prot = static_protections(req_prot, address, pfn); |
65e074df | 629 | |
fac84939 TG |
630 | /* |
631 | * We need to check the full range, whether | |
632 | * static_protection() requires a different pgprot for one of | |
633 | * the pages in the range we try to preserve: | |
634 | */ | |
64edc8ed | 635 | addr = address & pmask; |
3a19109e | 636 | pfn = old_pfn; |
64edc8ed | 637 | for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) { |
638 | pgprot_t chk_prot = static_protections(req_prot, addr, pfn); | |
fac84939 TG |
639 | |
640 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
641 | goto out_unlock; | |
642 | } | |
643 | ||
65e074df TG |
644 | /* |
645 | * If there are no changes, return. maxpages has been updated | |
646 | * above: | |
647 | */ | |
648 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 649 | do_split = 0; |
65e074df TG |
650 | goto out_unlock; |
651 | } | |
652 | ||
653 | /* | |
654 | * We need to change the attributes. Check, whether we can | |
655 | * change the large page in one go. We request a split, when | |
656 | * the address is not aligned and the number of pages is | |
657 | * smaller than the number of pages in the large page. Note | |
658 | * that we limited the number of possible pages already to | |
659 | * the number of pages in the large page. | |
660 | */ | |
64edc8ed | 661 | if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) { |
65e074df TG |
662 | /* |
663 | * The address is aligned and the number of pages | |
664 | * covers the full page. | |
665 | */ | |
3a19109e | 666 | new_pte = pfn_pte(old_pfn, new_prot); |
65e074df | 667 | __set_pmd_pte(kpte, address, new_pte); |
d75586ad | 668 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 669 | do_split = 0; |
65e074df TG |
670 | } |
671 | ||
672 | out_unlock: | |
a79e53d8 | 673 | spin_unlock(&pgd_lock); |
9df84993 | 674 | |
beaff633 | 675 | return do_split; |
65e074df TG |
676 | } |
677 | ||
5952886b | 678 | static int |
82f0712c BP |
679 | __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address, |
680 | struct page *base) | |
bb5c2dbd | 681 | { |
5952886b | 682 | pte_t *pbase = (pte_t *)page_address(base); |
d551aaa2 | 683 | unsigned long ref_pfn, pfn, pfninc = 1; |
9df84993 | 684 | unsigned int i, level; |
ae9aae9e | 685 | pte_t *tmp; |
9df84993 | 686 | pgprot_t ref_prot; |
bb5c2dbd | 687 | |
a79e53d8 | 688 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
689 | /* |
690 | * Check for races, another CPU might have split this page | |
691 | * up for us already: | |
692 | */ | |
82f0712c | 693 | tmp = _lookup_address_cpa(cpa, address, &level); |
ae9aae9e WC |
694 | if (tmp != kpte) { |
695 | spin_unlock(&pgd_lock); | |
696 | return 1; | |
697 | } | |
bb5c2dbd | 698 | |
6944a9c8 | 699 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
f5b2831d | 700 | |
d551aaa2 TK |
701 | switch (level) { |
702 | case PG_LEVEL_2M: | |
703 | ref_prot = pmd_pgprot(*(pmd_t *)kpte); | |
606c7193 DH |
704 | /* |
705 | * Clear PSE (aka _PAGE_PAT) and move | |
706 | * PAT bit to correct position. | |
707 | */ | |
f5b2831d | 708 | ref_prot = pgprot_large_2_4k(ref_prot); |
606c7193 | 709 | |
d551aaa2 TK |
710 | ref_pfn = pmd_pfn(*(pmd_t *)kpte); |
711 | break; | |
bb5c2dbd | 712 | |
d551aaa2 TK |
713 | case PG_LEVEL_1G: |
714 | ref_prot = pud_pgprot(*(pud_t *)kpte); | |
715 | ref_pfn = pud_pfn(*(pud_t *)kpte); | |
f07333fd | 716 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; |
d551aaa2 | 717 | |
a8aed3e0 | 718 | /* |
d551aaa2 | 719 | * Clear the PSE flags if the PRESENT flag is not set |
a8aed3e0 AA |
720 | * otherwise pmd_present/pmd_huge will return true |
721 | * even on a non present pmd. | |
722 | */ | |
d551aaa2 | 723 | if (!(pgprot_val(ref_prot) & _PAGE_PRESENT)) |
a8aed3e0 | 724 | pgprot_val(ref_prot) &= ~_PAGE_PSE; |
d551aaa2 TK |
725 | break; |
726 | ||
727 | default: | |
728 | spin_unlock(&pgd_lock); | |
729 | return 1; | |
f07333fd | 730 | } |
f07333fd | 731 | |
d1440b23 | 732 | ref_prot = pgprot_clear_protnone_bits(ref_prot); |
a8aed3e0 | 733 | |
63c1dcf4 TG |
734 | /* |
735 | * Get the target pfn from the original entry: | |
736 | */ | |
d551aaa2 | 737 | pfn = ref_pfn; |
f07333fd | 738 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
1a54420a | 739 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 740 | |
2c66e24d SP |
741 | if (virt_addr_valid(address)) { |
742 | unsigned long pfn = PFN_DOWN(__pa(address)); | |
743 | ||
744 | if (pfn_range_is_mapped(pfn, pfn + 1)) | |
745 | split_page_count(level); | |
746 | } | |
f361a450 | 747 | |
bb5c2dbd | 748 | /* |
07a66d7c | 749 | * Install the new, split up pagetable. |
4c881ca1 | 750 | * |
07a66d7c IM |
751 | * We use the standard kernel pagetable protections for the new |
752 | * pagetable protections, the actual ptes set above control the | |
753 | * primary protection behavior: | |
bb5c2dbd | 754 | */ |
07a66d7c | 755 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
756 | |
757 | /* | |
758 | * Intel Atom errata AAH41 workaround. | |
759 | * | |
760 | * The real fix should be in hw or in a microcode update, but | |
761 | * we also probabilistically try to reduce the window of having | |
762 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
763 | * going on. | |
764 | */ | |
765 | __flush_tlb_all(); | |
ae9aae9e | 766 | spin_unlock(&pgd_lock); |
211b3d03 | 767 | |
ae9aae9e WC |
768 | return 0; |
769 | } | |
bb5c2dbd | 770 | |
82f0712c BP |
771 | static int split_large_page(struct cpa_data *cpa, pte_t *kpte, |
772 | unsigned long address) | |
ae9aae9e | 773 | { |
ae9aae9e WC |
774 | struct page *base; |
775 | ||
288cf3c6 | 776 | if (!debug_pagealloc_enabled()) |
ae9aae9e | 777 | spin_unlock(&cpa_lock); |
75f296d9 | 778 | base = alloc_pages(GFP_KERNEL, 0); |
288cf3c6 | 779 | if (!debug_pagealloc_enabled()) |
ae9aae9e WC |
780 | spin_lock(&cpa_lock); |
781 | if (!base) | |
782 | return -ENOMEM; | |
783 | ||
82f0712c | 784 | if (__split_large_page(cpa, kpte, address, base)) |
8311eb84 | 785 | __free_page(base); |
bb5c2dbd | 786 | |
bb5c2dbd IM |
787 | return 0; |
788 | } | |
789 | ||
52a628fb BP |
790 | static bool try_to_free_pte_page(pte_t *pte) |
791 | { | |
792 | int i; | |
793 | ||
794 | for (i = 0; i < PTRS_PER_PTE; i++) | |
795 | if (!pte_none(pte[i])) | |
796 | return false; | |
797 | ||
798 | free_page((unsigned long)pte); | |
799 | return true; | |
800 | } | |
801 | ||
802 | static bool try_to_free_pmd_page(pmd_t *pmd) | |
803 | { | |
804 | int i; | |
805 | ||
806 | for (i = 0; i < PTRS_PER_PMD; i++) | |
807 | if (!pmd_none(pmd[i])) | |
808 | return false; | |
809 | ||
810 | free_page((unsigned long)pmd); | |
811 | return true; | |
812 | } | |
813 | ||
814 | static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end) | |
815 | { | |
816 | pte_t *pte = pte_offset_kernel(pmd, start); | |
817 | ||
818 | while (start < end) { | |
819 | set_pte(pte, __pte(0)); | |
820 | ||
821 | start += PAGE_SIZE; | |
822 | pte++; | |
823 | } | |
824 | ||
825 | if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) { | |
826 | pmd_clear(pmd); | |
827 | return true; | |
828 | } | |
829 | return false; | |
830 | } | |
831 | ||
832 | static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd, | |
833 | unsigned long start, unsigned long end) | |
834 | { | |
835 | if (unmap_pte_range(pmd, start, end)) | |
836 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
837 | pud_clear(pud); | |
838 | } | |
839 | ||
840 | static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end) | |
841 | { | |
842 | pmd_t *pmd = pmd_offset(pud, start); | |
843 | ||
844 | /* | |
845 | * Not on a 2MB page boundary? | |
846 | */ | |
847 | if (start & (PMD_SIZE - 1)) { | |
848 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
849 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
850 | ||
851 | __unmap_pmd_range(pud, pmd, start, pre_end); | |
852 | ||
853 | start = pre_end; | |
854 | pmd++; | |
855 | } | |
856 | ||
857 | /* | |
858 | * Try to unmap in 2M chunks. | |
859 | */ | |
860 | while (end - start >= PMD_SIZE) { | |
861 | if (pmd_large(*pmd)) | |
862 | pmd_clear(pmd); | |
863 | else | |
864 | __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE); | |
865 | ||
866 | start += PMD_SIZE; | |
867 | pmd++; | |
868 | } | |
869 | ||
870 | /* | |
871 | * 4K leftovers? | |
872 | */ | |
873 | if (start < end) | |
874 | return __unmap_pmd_range(pud, pmd, start, end); | |
875 | ||
876 | /* | |
877 | * Try again to free the PMD page if haven't succeeded above. | |
878 | */ | |
879 | if (!pud_none(*pud)) | |
880 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
881 | pud_clear(pud); | |
882 | } | |
0bb8aeee | 883 | |
45478336 | 884 | static void unmap_pud_range(p4d_t *p4d, unsigned long start, unsigned long end) |
0bb8aeee | 885 | { |
45478336 | 886 | pud_t *pud = pud_offset(p4d, start); |
0bb8aeee BP |
887 | |
888 | /* | |
889 | * Not on a GB page boundary? | |
890 | */ | |
891 | if (start & (PUD_SIZE - 1)) { | |
892 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
893 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
894 | ||
895 | unmap_pmd_range(pud, start, pre_end); | |
896 | ||
897 | start = pre_end; | |
898 | pud++; | |
899 | } | |
900 | ||
901 | /* | |
902 | * Try to unmap in 1G chunks? | |
903 | */ | |
904 | while (end - start >= PUD_SIZE) { | |
905 | ||
906 | if (pud_large(*pud)) | |
907 | pud_clear(pud); | |
908 | else | |
909 | unmap_pmd_range(pud, start, start + PUD_SIZE); | |
910 | ||
911 | start += PUD_SIZE; | |
912 | pud++; | |
913 | } | |
914 | ||
915 | /* | |
916 | * 2M leftovers? | |
917 | */ | |
918 | if (start < end) | |
919 | unmap_pmd_range(pud, start, end); | |
920 | ||
921 | /* | |
922 | * No need to try to free the PUD page because we'll free it in | |
923 | * populate_pgd's error path | |
924 | */ | |
925 | } | |
926 | ||
f900a4b8 BP |
927 | static int alloc_pte_page(pmd_t *pmd) |
928 | { | |
75f296d9 | 929 | pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL); |
f900a4b8 BP |
930 | if (!pte) |
931 | return -1; | |
932 | ||
933 | set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE)); | |
934 | return 0; | |
935 | } | |
936 | ||
4b23538d BP |
937 | static int alloc_pmd_page(pud_t *pud) |
938 | { | |
75f296d9 | 939 | pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL); |
4b23538d BP |
940 | if (!pmd) |
941 | return -1; | |
942 | ||
943 | set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); | |
944 | return 0; | |
945 | } | |
946 | ||
c6b6f363 BP |
947 | static void populate_pte(struct cpa_data *cpa, |
948 | unsigned long start, unsigned long end, | |
949 | unsigned num_pages, pmd_t *pmd, pgprot_t pgprot) | |
950 | { | |
951 | pte_t *pte; | |
952 | ||
953 | pte = pte_offset_kernel(pmd, start); | |
954 | ||
d1440b23 | 955 | pgprot = pgprot_clear_protnone_bits(pgprot); |
c6b6f363 | 956 | |
c6b6f363 | 957 | while (num_pages-- && start < end) { |
edc3b912 | 958 | set_pte(pte, pfn_pte(cpa->pfn, pgprot)); |
c6b6f363 BP |
959 | |
960 | start += PAGE_SIZE; | |
edc3b912 | 961 | cpa->pfn++; |
c6b6f363 BP |
962 | pte++; |
963 | } | |
964 | } | |
f900a4b8 | 965 | |
e535ec08 MF |
966 | static long populate_pmd(struct cpa_data *cpa, |
967 | unsigned long start, unsigned long end, | |
968 | unsigned num_pages, pud_t *pud, pgprot_t pgprot) | |
f900a4b8 | 969 | { |
e535ec08 | 970 | long cur_pages = 0; |
f900a4b8 | 971 | pmd_t *pmd; |
f5b2831d | 972 | pgprot_t pmd_pgprot; |
f900a4b8 BP |
973 | |
974 | /* | |
975 | * Not on a 2M boundary? | |
976 | */ | |
977 | if (start & (PMD_SIZE - 1)) { | |
978 | unsigned long pre_end = start + (num_pages << PAGE_SHIFT); | |
979 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
980 | ||
981 | pre_end = min_t(unsigned long, pre_end, next_page); | |
982 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
983 | cur_pages = min_t(unsigned int, num_pages, cur_pages); | |
984 | ||
985 | /* | |
986 | * Need a PTE page? | |
987 | */ | |
988 | pmd = pmd_offset(pud, start); | |
989 | if (pmd_none(*pmd)) | |
990 | if (alloc_pte_page(pmd)) | |
991 | return -1; | |
992 | ||
993 | populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot); | |
994 | ||
995 | start = pre_end; | |
996 | } | |
997 | ||
998 | /* | |
999 | * We mapped them all? | |
1000 | */ | |
1001 | if (num_pages == cur_pages) | |
1002 | return cur_pages; | |
1003 | ||
f5b2831d JG |
1004 | pmd_pgprot = pgprot_4k_2_large(pgprot); |
1005 | ||
f900a4b8 BP |
1006 | while (end - start >= PMD_SIZE) { |
1007 | ||
1008 | /* | |
1009 | * We cannot use a 1G page so allocate a PMD page if needed. | |
1010 | */ | |
1011 | if (pud_none(*pud)) | |
1012 | if (alloc_pmd_page(pud)) | |
1013 | return -1; | |
1014 | ||
1015 | pmd = pmd_offset(pud, start); | |
1016 | ||
edc3b912 | 1017 | set_pmd(pmd, __pmd(cpa->pfn << PAGE_SHIFT | _PAGE_PSE | |
f5b2831d | 1018 | massage_pgprot(pmd_pgprot))); |
f900a4b8 BP |
1019 | |
1020 | start += PMD_SIZE; | |
edc3b912 | 1021 | cpa->pfn += PMD_SIZE >> PAGE_SHIFT; |
f900a4b8 BP |
1022 | cur_pages += PMD_SIZE >> PAGE_SHIFT; |
1023 | } | |
1024 | ||
1025 | /* | |
1026 | * Map trailing 4K pages. | |
1027 | */ | |
1028 | if (start < end) { | |
1029 | pmd = pmd_offset(pud, start); | |
1030 | if (pmd_none(*pmd)) | |
1031 | if (alloc_pte_page(pmd)) | |
1032 | return -1; | |
1033 | ||
1034 | populate_pte(cpa, start, end, num_pages - cur_pages, | |
1035 | pmd, pgprot); | |
1036 | } | |
1037 | return num_pages; | |
1038 | } | |
4b23538d | 1039 | |
45478336 KS |
1040 | static int populate_pud(struct cpa_data *cpa, unsigned long start, p4d_t *p4d, |
1041 | pgprot_t pgprot) | |
4b23538d BP |
1042 | { |
1043 | pud_t *pud; | |
1044 | unsigned long end; | |
e535ec08 | 1045 | long cur_pages = 0; |
f5b2831d | 1046 | pgprot_t pud_pgprot; |
4b23538d BP |
1047 | |
1048 | end = start + (cpa->numpages << PAGE_SHIFT); | |
1049 | ||
1050 | /* | |
1051 | * Not on a Gb page boundary? => map everything up to it with | |
1052 | * smaller pages. | |
1053 | */ | |
1054 | if (start & (PUD_SIZE - 1)) { | |
1055 | unsigned long pre_end; | |
1056 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
1057 | ||
1058 | pre_end = min_t(unsigned long, end, next_page); | |
1059 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
1060 | cur_pages = min_t(int, (int)cpa->numpages, cur_pages); | |
1061 | ||
45478336 | 1062 | pud = pud_offset(p4d, start); |
4b23538d BP |
1063 | |
1064 | /* | |
1065 | * Need a PMD page? | |
1066 | */ | |
1067 | if (pud_none(*pud)) | |
1068 | if (alloc_pmd_page(pud)) | |
1069 | return -1; | |
1070 | ||
1071 | cur_pages = populate_pmd(cpa, start, pre_end, cur_pages, | |
1072 | pud, pgprot); | |
1073 | if (cur_pages < 0) | |
1074 | return cur_pages; | |
1075 | ||
1076 | start = pre_end; | |
1077 | } | |
1078 | ||
1079 | /* We mapped them all? */ | |
1080 | if (cpa->numpages == cur_pages) | |
1081 | return cur_pages; | |
1082 | ||
45478336 | 1083 | pud = pud_offset(p4d, start); |
f5b2831d | 1084 | pud_pgprot = pgprot_4k_2_large(pgprot); |
4b23538d BP |
1085 | |
1086 | /* | |
1087 | * Map everything starting from the Gb boundary, possibly with 1G pages | |
1088 | */ | |
b8291adc | 1089 | while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) { |
edc3b912 | 1090 | set_pud(pud, __pud(cpa->pfn << PAGE_SHIFT | _PAGE_PSE | |
f5b2831d | 1091 | massage_pgprot(pud_pgprot))); |
4b23538d BP |
1092 | |
1093 | start += PUD_SIZE; | |
edc3b912 | 1094 | cpa->pfn += PUD_SIZE >> PAGE_SHIFT; |
4b23538d BP |
1095 | cur_pages += PUD_SIZE >> PAGE_SHIFT; |
1096 | pud++; | |
1097 | } | |
1098 | ||
1099 | /* Map trailing leftover */ | |
1100 | if (start < end) { | |
e535ec08 | 1101 | long tmp; |
4b23538d | 1102 | |
45478336 | 1103 | pud = pud_offset(p4d, start); |
4b23538d BP |
1104 | if (pud_none(*pud)) |
1105 | if (alloc_pmd_page(pud)) | |
1106 | return -1; | |
1107 | ||
1108 | tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages, | |
1109 | pud, pgprot); | |
1110 | if (tmp < 0) | |
1111 | return cur_pages; | |
1112 | ||
1113 | cur_pages += tmp; | |
1114 | } | |
1115 | return cur_pages; | |
1116 | } | |
f3f72966 BP |
1117 | |
1118 | /* | |
1119 | * Restrictions for kernel page table do not necessarily apply when mapping in | |
1120 | * an alternate PGD. | |
1121 | */ | |
1122 | static int populate_pgd(struct cpa_data *cpa, unsigned long addr) | |
1123 | { | |
1124 | pgprot_t pgprot = __pgprot(_KERNPG_TABLE); | |
f3f72966 | 1125 | pud_t *pud = NULL; /* shut up gcc */ |
45478336 | 1126 | p4d_t *p4d; |
42a54772 | 1127 | pgd_t *pgd_entry; |
e535ec08 | 1128 | long ret; |
f3f72966 BP |
1129 | |
1130 | pgd_entry = cpa->pgd + pgd_index(addr); | |
1131 | ||
45478336 | 1132 | if (pgd_none(*pgd_entry)) { |
75f296d9 | 1133 | p4d = (p4d_t *)get_zeroed_page(GFP_KERNEL); |
45478336 KS |
1134 | if (!p4d) |
1135 | return -1; | |
1136 | ||
1137 | set_pgd(pgd_entry, __pgd(__pa(p4d) | _KERNPG_TABLE)); | |
1138 | } | |
1139 | ||
f3f72966 BP |
1140 | /* |
1141 | * Allocate a PUD page and hand it down for mapping. | |
1142 | */ | |
45478336 KS |
1143 | p4d = p4d_offset(pgd_entry, addr); |
1144 | if (p4d_none(*p4d)) { | |
75f296d9 | 1145 | pud = (pud_t *)get_zeroed_page(GFP_KERNEL); |
f3f72966 BP |
1146 | if (!pud) |
1147 | return -1; | |
530dd8d4 | 1148 | |
45478336 | 1149 | set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE)); |
f3f72966 BP |
1150 | } |
1151 | ||
1152 | pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr); | |
1153 | pgprot_val(pgprot) |= pgprot_val(cpa->mask_set); | |
1154 | ||
45478336 | 1155 | ret = populate_pud(cpa, addr, p4d, pgprot); |
0bb8aeee | 1156 | if (ret < 0) { |
55920d31 AL |
1157 | /* |
1158 | * Leave the PUD page in place in case some other CPU or thread | |
1159 | * already found it, but remove any useless entries we just | |
1160 | * added to it. | |
1161 | */ | |
45478336 | 1162 | unmap_pud_range(p4d, addr, |
0bb8aeee | 1163 | addr + (cpa->numpages << PAGE_SHIFT)); |
f3f72966 | 1164 | return ret; |
0bb8aeee | 1165 | } |
42a54772 | 1166 | |
f3f72966 BP |
1167 | cpa->numpages = ret; |
1168 | return 0; | |
1169 | } | |
1170 | ||
a1e46212 SS |
1171 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
1172 | int primary) | |
1173 | { | |
7fc8442f MF |
1174 | if (cpa->pgd) { |
1175 | /* | |
1176 | * Right now, we only execute this code path when mapping | |
1177 | * the EFI virtual memory map regions, no other users | |
1178 | * provide a ->pgd value. This may change in the future. | |
1179 | */ | |
82f0712c | 1180 | return populate_pgd(cpa, vaddr); |
7fc8442f | 1181 | } |
82f0712c | 1182 | |
a1e46212 SS |
1183 | /* |
1184 | * Ignore all non primary paths. | |
1185 | */ | |
405e1133 JB |
1186 | if (!primary) { |
1187 | cpa->numpages = 1; | |
a1e46212 | 1188 | return 0; |
405e1133 | 1189 | } |
a1e46212 SS |
1190 | |
1191 | /* | |
1192 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
1193 | * to have holes. | |
1194 | * Also set numpages to '1' indicating that we processed cpa req for | |
1195 | * one virtual address page and its pfn. TBD: numpages can be set based | |
1196 | * on the initial value and the level returned by lookup_address(). | |
1197 | */ | |
1198 | if (within(vaddr, PAGE_OFFSET, | |
1199 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
1200 | cpa->numpages = 1; | |
1201 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
1202 | return 0; | |
58e65b51 DH |
1203 | |
1204 | } else if (__cpa_pfn_in_highmap(cpa->pfn)) { | |
1205 | /* Faults in the highmap are OK, so do not warn: */ | |
1206 | return -EFAULT; | |
a1e46212 SS |
1207 | } else { |
1208 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
1209 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
1210 | *cpa->vaddr); | |
1211 | ||
1212 | return -EFAULT; | |
1213 | } | |
1214 | } | |
1215 | ||
c31c7d48 | 1216 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 1217 | { |
d75586ad | 1218 | unsigned long address; |
da7bfc50 HH |
1219 | int do_split, err; |
1220 | unsigned int level; | |
c31c7d48 | 1221 | pte_t *kpte, old_pte; |
1da177e4 | 1222 | |
8523acfe TH |
1223 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1224 | struct page *page = cpa->pages[cpa->curpage]; | |
1225 | if (unlikely(PageHighMem(page))) | |
1226 | return 0; | |
1227 | address = (unsigned long)page_address(page); | |
1228 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1229 | address = cpa->vaddr[cpa->curpage]; |
1230 | else | |
1231 | address = *cpa->vaddr; | |
97f99fed | 1232 | repeat: |
82f0712c | 1233 | kpte = _lookup_address_cpa(cpa, address, &level); |
1da177e4 | 1234 | if (!kpte) |
a1e46212 | 1235 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
1236 | |
1237 | old_pte = *kpte; | |
dcb32d99 | 1238 | if (pte_none(old_pte)) |
a1e46212 | 1239 | return __cpa_process_fault(cpa, address, primary); |
9f4c815c | 1240 | |
30551bb3 | 1241 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 1242 | pte_t new_pte; |
626c2c9d | 1243 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 1244 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 1245 | |
72e458df TG |
1246 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
1247 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 1248 | |
c31c7d48 | 1249 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 1250 | |
d1440b23 | 1251 | new_prot = pgprot_clear_protnone_bits(new_prot); |
a8aed3e0 | 1252 | |
626c2c9d AV |
1253 | /* |
1254 | * We need to keep the pfn from the existing PTE, | |
1255 | * after all we're only going to change it's attributes | |
1256 | * not the memory it points to | |
1257 | */ | |
1a54420a | 1258 | new_pte = pfn_pte(pfn, new_prot); |
c31c7d48 | 1259 | cpa->pfn = pfn; |
f4ae5da0 TG |
1260 | /* |
1261 | * Do we really change anything ? | |
1262 | */ | |
1263 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
1264 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 1265 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 1266 | } |
9b5cf48b | 1267 | cpa->numpages = 1; |
65e074df | 1268 | return 0; |
1da177e4 | 1269 | } |
65e074df TG |
1270 | |
1271 | /* | |
1272 | * Check, whether we can keep the large page intact | |
1273 | * and just change the pte: | |
1274 | */ | |
beaff633 | 1275 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
1276 | /* |
1277 | * When the range fits into the existing large page, | |
9b5cf48b | 1278 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
1279 | * try_large_page: |
1280 | */ | |
87f7f8fe IM |
1281 | if (do_split <= 0) |
1282 | return do_split; | |
65e074df TG |
1283 | |
1284 | /* | |
1285 | * We have to split the large page: | |
1286 | */ | |
82f0712c | 1287 | err = split_large_page(cpa, kpte, address); |
87f7f8fe | 1288 | if (!err) { |
ad5ca55f SS |
1289 | /* |
1290 | * Do a global flush tlb after splitting the large page | |
1291 | * and before we do the actual change page attribute in the PTE. | |
1292 | * | |
1293 | * With out this, we violate the TLB application note, that says | |
1294 | * "The TLBs may contain both ordinary and large-page | |
1295 | * translations for a 4-KByte range of linear addresses. This | |
1296 | * may occur if software modifies the paging structures so that | |
1297 | * the page size used for the address range changes. If the two | |
1298 | * translations differ with respect to page frame or attributes | |
1299 | * (e.g., permissions), processor behavior is undefined and may | |
1300 | * be implementation-specific." | |
1301 | * | |
1302 | * We do this global tlb flush inside the cpa_lock, so that we | |
1303 | * don't allow any other cpu, with stale tlb entries change the | |
1304 | * page attribute in parallel, that also falls into the | |
1305 | * just split large page entry. | |
1306 | */ | |
1307 | flush_tlb_all(); | |
87f7f8fe IM |
1308 | goto repeat; |
1309 | } | |
beaff633 | 1310 | |
87f7f8fe | 1311 | return err; |
9f4c815c | 1312 | } |
1da177e4 | 1313 | |
c31c7d48 TG |
1314 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
1315 | ||
1316 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 1317 | { |
c31c7d48 | 1318 | struct cpa_data alias_cpa; |
992f4c1c | 1319 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 1320 | unsigned long vaddr; |
992f4c1c | 1321 | int ret; |
44af6c41 | 1322 | |
8eb5779f | 1323 | if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1)) |
c31c7d48 | 1324 | return 0; |
626c2c9d | 1325 | |
f34b439f TG |
1326 | /* |
1327 | * No need to redo, when the primary call touched the direct | |
1328 | * mapping already: | |
1329 | */ | |
8523acfe TH |
1330 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1331 | struct page *page = cpa->pages[cpa->curpage]; | |
1332 | if (unlikely(PageHighMem(page))) | |
1333 | return 0; | |
1334 | vaddr = (unsigned long)page_address(page); | |
1335 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1336 | vaddr = cpa->vaddr[cpa->curpage]; |
1337 | else | |
1338 | vaddr = *cpa->vaddr; | |
1339 | ||
1340 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 1341 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 1342 | |
f34b439f | 1343 | alias_cpa = *cpa; |
992f4c1c | 1344 | alias_cpa.vaddr = &laddr; |
9ae28475 | 1345 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 1346 | |
f34b439f | 1347 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
1348 | if (ret) |
1349 | return ret; | |
f34b439f | 1350 | } |
44af6c41 | 1351 | |
44af6c41 | 1352 | #ifdef CONFIG_X86_64 |
488fd995 | 1353 | /* |
992f4c1c TH |
1354 | * If the primary call didn't touch the high mapping already |
1355 | * and the physical address is inside the kernel map, we need | |
0879750f | 1356 | * to touch the high mapped kernel as well: |
488fd995 | 1357 | */ |
992f4c1c | 1358 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
58e65b51 | 1359 | __cpa_pfn_in_highmap(cpa->pfn)) { |
992f4c1c TH |
1360 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + |
1361 | __START_KERNEL_map - phys_base; | |
1362 | alias_cpa = *cpa; | |
1363 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
1364 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 1365 | |
992f4c1c TH |
1366 | /* |
1367 | * The high mapping range is imprecise, so ignore the | |
1368 | * return value. | |
1369 | */ | |
1370 | __change_page_attr_set_clr(&alias_cpa, 0); | |
1371 | } | |
488fd995 | 1372 | #endif |
992f4c1c TH |
1373 | |
1374 | return 0; | |
1da177e4 LT |
1375 | } |
1376 | ||
c31c7d48 | 1377 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 1378 | { |
e535ec08 MF |
1379 | unsigned long numpages = cpa->numpages; |
1380 | int ret; | |
ff31452b | 1381 | |
65e074df TG |
1382 | while (numpages) { |
1383 | /* | |
1384 | * Store the remaining nr of pages for the large page | |
1385 | * preservation check. | |
1386 | */ | |
9b5cf48b | 1387 | cpa->numpages = numpages; |
d75586ad | 1388 | /* for array changes, we can't use large page */ |
9ae28475 | 1389 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 1390 | cpa->numpages = 1; |
c31c7d48 | 1391 | |
288cf3c6 | 1392 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1393 | spin_lock(&cpa_lock); |
c31c7d48 | 1394 | ret = __change_page_attr(cpa, checkalias); |
288cf3c6 | 1395 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1396 | spin_unlock(&cpa_lock); |
ff31452b TG |
1397 | if (ret) |
1398 | return ret; | |
ff31452b | 1399 | |
c31c7d48 TG |
1400 | if (checkalias) { |
1401 | ret = cpa_process_alias(cpa); | |
1402 | if (ret) | |
1403 | return ret; | |
1404 | } | |
1405 | ||
65e074df TG |
1406 | /* |
1407 | * Adjust the number of pages with the result of the | |
1408 | * CPA operation. Either a large page has been | |
1409 | * preserved or a single page update happened. | |
1410 | */ | |
74256377 | 1411 | BUG_ON(cpa->numpages > numpages || !cpa->numpages); |
9b5cf48b | 1412 | numpages -= cpa->numpages; |
9ae28475 | 1413 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
1414 | cpa->curpage++; |
1415 | else | |
1416 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
1417 | ||
65e074df | 1418 | } |
ff31452b TG |
1419 | return 0; |
1420 | } | |
1421 | ||
d75586ad | 1422 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 1423 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 1424 | int force_split, int in_flag, |
1425 | struct page **pages) | |
ff31452b | 1426 | { |
72e458df | 1427 | struct cpa_data cpa; |
cacf8906 | 1428 | int ret, cache, checkalias; |
fa526d0d | 1429 | unsigned long baddr = 0; |
331e4065 | 1430 | |
82f0712c BP |
1431 | memset(&cpa, 0, sizeof(cpa)); |
1432 | ||
331e4065 | 1433 | /* |
39114b7a DH |
1434 | * Check, if we are requested to set a not supported |
1435 | * feature. Clearing non-supported features is OK. | |
331e4065 TG |
1436 | */ |
1437 | mask_set = canon_pgprot(mask_set); | |
39114b7a | 1438 | |
c9caa02c | 1439 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
1440 | return 0; |
1441 | ||
69b1415e | 1442 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 1443 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
1444 | int i; |
1445 | for (i = 0; i < numpages; i++) { | |
1446 | if (addr[i] & ~PAGE_MASK) { | |
1447 | addr[i] &= PAGE_MASK; | |
1448 | WARN_ON_ONCE(1); | |
1449 | } | |
1450 | } | |
9ae28475 | 1451 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
1452 | /* | |
1453 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
1454 | * No need to cehck in that case | |
1455 | */ | |
1456 | if (*addr & ~PAGE_MASK) { | |
1457 | *addr &= PAGE_MASK; | |
1458 | /* | |
1459 | * People should not be passing in unaligned addresses: | |
1460 | */ | |
1461 | WARN_ON_ONCE(1); | |
1462 | } | |
fa526d0d JS |
1463 | /* |
1464 | * Save address for cache flush. *addr is modified in the call | |
1465 | * to __change_page_attr_set_clr() below. | |
1466 | */ | |
1467 | baddr = *addr; | |
69b1415e TG |
1468 | } |
1469 | ||
5843d9a4 NP |
1470 | /* Must avoid aliasing mappings in the highmem code */ |
1471 | kmap_flush_unused(); | |
1472 | ||
db64fe02 NP |
1473 | vm_unmap_aliases(); |
1474 | ||
72e458df | 1475 | cpa.vaddr = addr; |
9ae28475 | 1476 | cpa.pages = pages; |
72e458df TG |
1477 | cpa.numpages = numpages; |
1478 | cpa.mask_set = mask_set; | |
1479 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
1480 | cpa.flags = 0; |
1481 | cpa.curpage = 0; | |
c9caa02c | 1482 | cpa.force_split = force_split; |
72e458df | 1483 | |
9ae28475 | 1484 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
1485 | cpa.flags |= in_flag; | |
d75586ad | 1486 | |
af96e443 TG |
1487 | /* No alias checking for _NX bit modifications */ |
1488 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
1489 | ||
1490 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 1491 | |
f4ae5da0 TG |
1492 | /* |
1493 | * Check whether we really changed something: | |
1494 | */ | |
d75586ad | 1495 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 1496 | goto out; |
cacf8906 | 1497 | |
6bb8383b AK |
1498 | /* |
1499 | * No need to flush, when we did not set any of the caching | |
1500 | * attributes: | |
1501 | */ | |
c06814d8 | 1502 | cache = !!pgprot2cachemode(mask_set); |
6bb8383b | 1503 | |
57a6a46a | 1504 | /* |
b82ad3d3 BP |
1505 | * On success we use CLFLUSH, when the CPU supports it to |
1506 | * avoid the WBINVD. If the CPU does not support it and in the | |
f026cfa8 | 1507 | * error case we fall back to cpa_flush_all (which uses |
b82ad3d3 | 1508 | * WBINVD): |
57a6a46a | 1509 | */ |
906bf7fd | 1510 | if (!ret && boot_cpu_has(X86_FEATURE_CLFLUSH)) { |
9ae28475 | 1511 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
1512 | cpa_flush_array(addr, numpages, cache, | |
1513 | cpa.flags, pages); | |
1514 | } else | |
fa526d0d | 1515 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 1516 | } else |
6bb8383b | 1517 | cpa_flush_all(cache); |
cacf8906 | 1518 | |
76ebd054 | 1519 | out: |
ff31452b TG |
1520 | return ret; |
1521 | } | |
1522 | ||
d75586ad SL |
1523 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
1524 | pgprot_t mask, int array) | |
75cbade8 | 1525 | { |
d75586ad | 1526 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 1527 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
1528 | } |
1529 | ||
d75586ad SL |
1530 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
1531 | pgprot_t mask, int array) | |
72932c7a | 1532 | { |
d75586ad | 1533 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 1534 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
1535 | } |
1536 | ||
0f350755 | 1537 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
1538 | pgprot_t mask) | |
1539 | { | |
1540 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
1541 | CPA_PAGES_ARRAY, pages); | |
1542 | } | |
1543 | ||
1544 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
1545 | pgprot_t mask) | |
1546 | { | |
1547 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
1548 | CPA_PAGES_ARRAY, pages); | |
1549 | } | |
1550 | ||
1219333d | 1551 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 1552 | { |
de33c442 SS |
1553 | /* |
1554 | * for now UC MINUS. see comments in ioremap_nocache() | |
e4b6be33 LR |
1555 | * If you really need strong UC use ioremap_uc(), but note |
1556 | * that you cannot override IO areas with set_memory_*() as | |
1557 | * these helpers cannot work with IO memory. | |
de33c442 | 1558 | */ |
d75586ad | 1559 | return change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1560 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1561 | 0); | |
75cbade8 | 1562 | } |
1219333d | 1563 | |
1564 | int set_memory_uc(unsigned long addr, int numpages) | |
1565 | { | |
9fa3ab39 | 1566 | int ret; |
1567 | ||
de33c442 SS |
1568 | /* |
1569 | * for now UC MINUS. see comments in ioremap_nocache() | |
1570 | */ | |
9fa3ab39 | 1571 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1572 | _PAGE_CACHE_MODE_UC_MINUS, NULL); |
9fa3ab39 | 1573 | if (ret) |
1574 | goto out_err; | |
1575 | ||
1576 | ret = _set_memory_uc(addr, numpages); | |
1577 | if (ret) | |
1578 | goto out_free; | |
1579 | ||
1580 | return 0; | |
1219333d | 1581 | |
9fa3ab39 | 1582 | out_free: |
1583 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1584 | out_err: | |
1585 | return ret; | |
1219333d | 1586 | } |
75cbade8 AV |
1587 | EXPORT_SYMBOL(set_memory_uc); |
1588 | ||
2d070eff | 1589 | static int _set_memory_array(unsigned long *addr, int addrinarray, |
c06814d8 | 1590 | enum page_cache_mode new_type) |
d75586ad | 1591 | { |
623dffb2 | 1592 | enum page_cache_mode set_type; |
9fa3ab39 | 1593 | int i, j; |
1594 | int ret; | |
1595 | ||
d75586ad | 1596 | for (i = 0; i < addrinarray; i++) { |
9fa3ab39 | 1597 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1598 | new_type, NULL); |
9fa3ab39 | 1599 | if (ret) |
1600 | goto out_free; | |
d75586ad SL |
1601 | } |
1602 | ||
623dffb2 TK |
1603 | /* If WC, set to UC- first and then WC */ |
1604 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1605 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1606 | ||
9fa3ab39 | 1607 | ret = change_page_attr_set(addr, addrinarray, |
623dffb2 | 1608 | cachemode2pgprot(set_type), 1); |
4f646254 | 1609 | |
c06814d8 | 1610 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1611 | ret = change_page_attr_set_clr(addr, addrinarray, |
c06814d8 JG |
1612 | cachemode2pgprot( |
1613 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1614 | __pgprot(_PAGE_CACHE_MASK), |
1615 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1616 | if (ret) |
1617 | goto out_free; | |
1618 | ||
1619 | return 0; | |
1620 | ||
1621 | out_free: | |
1622 | for (j = 0; j < i; j++) | |
1623 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1624 | ||
1625 | return ret; | |
d75586ad | 1626 | } |
4f646254 PN |
1627 | |
1628 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1629 | { | |
c06814d8 | 1630 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1631 | } |
d75586ad SL |
1632 | EXPORT_SYMBOL(set_memory_array_uc); |
1633 | ||
4f646254 PN |
1634 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1635 | { | |
c06814d8 | 1636 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1637 | } |
1638 | EXPORT_SYMBOL(set_memory_array_wc); | |
1639 | ||
623dffb2 TK |
1640 | int set_memory_array_wt(unsigned long *addr, int addrinarray) |
1641 | { | |
1642 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT); | |
1643 | } | |
1644 | EXPORT_SYMBOL_GPL(set_memory_array_wt); | |
1645 | ||
ef354af4 | 1646 | int _set_memory_wc(unsigned long addr, int numpages) |
1647 | { | |
3869c4aa | 1648 | int ret; |
bdc6340f PV |
1649 | unsigned long addr_copy = addr; |
1650 | ||
3869c4aa | 1651 | ret = change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1652 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1653 | 0); | |
3869c4aa | 1654 | if (!ret) { |
bdc6340f | 1655 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
c06814d8 JG |
1656 | cachemode2pgprot( |
1657 | _PAGE_CACHE_MODE_WC), | |
bdc6340f PV |
1658 | __pgprot(_PAGE_CACHE_MASK), |
1659 | 0, 0, NULL); | |
3869c4aa | 1660 | } |
1661 | return ret; | |
ef354af4 | 1662 | } |
1663 | ||
1664 | int set_memory_wc(unsigned long addr, int numpages) | |
1665 | { | |
9fa3ab39 | 1666 | int ret; |
1667 | ||
9fa3ab39 | 1668 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1669 | _PAGE_CACHE_MODE_WC, NULL); |
9fa3ab39 | 1670 | if (ret) |
623dffb2 | 1671 | return ret; |
ef354af4 | 1672 | |
9fa3ab39 | 1673 | ret = _set_memory_wc(addr, numpages); |
1674 | if (ret) | |
623dffb2 | 1675 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1676 | |
9fa3ab39 | 1677 | return ret; |
ef354af4 | 1678 | } |
1679 | EXPORT_SYMBOL(set_memory_wc); | |
1680 | ||
623dffb2 TK |
1681 | int _set_memory_wt(unsigned long addr, int numpages) |
1682 | { | |
1683 | return change_page_attr_set(&addr, numpages, | |
1684 | cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0); | |
1685 | } | |
1686 | ||
1687 | int set_memory_wt(unsigned long addr, int numpages) | |
1688 | { | |
1689 | int ret; | |
1690 | ||
1691 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, | |
1692 | _PAGE_CACHE_MODE_WT, NULL); | |
1693 | if (ret) | |
1694 | return ret; | |
1695 | ||
1696 | ret = _set_memory_wt(addr, numpages); | |
1697 | if (ret) | |
1698 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1699 | ||
1700 | return ret; | |
1701 | } | |
1702 | EXPORT_SYMBOL_GPL(set_memory_wt); | |
1703 | ||
1219333d | 1704 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1705 | { |
c06814d8 | 1706 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
d75586ad SL |
1707 | return change_page_attr_clear(&addr, numpages, |
1708 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1709 | } |
1219333d | 1710 | |
1711 | int set_memory_wb(unsigned long addr, int numpages) | |
1712 | { | |
9fa3ab39 | 1713 | int ret; |
1714 | ||
1715 | ret = _set_memory_wb(addr, numpages); | |
1716 | if (ret) | |
1717 | return ret; | |
1718 | ||
c15238df | 1719 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1720 | return 0; |
1219333d | 1721 | } |
75cbade8 AV |
1722 | EXPORT_SYMBOL(set_memory_wb); |
1723 | ||
d75586ad SL |
1724 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1725 | { | |
1726 | int i; | |
a5593e0b | 1727 | int ret; |
1728 | ||
c06814d8 | 1729 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
a5593e0b | 1730 | ret = change_page_attr_clear(addr, addrinarray, |
1731 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1732 | if (ret) |
1733 | return ret; | |
d75586ad | 1734 | |
9fa3ab39 | 1735 | for (i = 0; i < addrinarray; i++) |
1736 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1737 | |
9fa3ab39 | 1738 | return 0; |
d75586ad SL |
1739 | } |
1740 | EXPORT_SYMBOL(set_memory_array_wb); | |
1741 | ||
75cbade8 AV |
1742 | int set_memory_x(unsigned long addr, int numpages) |
1743 | { | |
583140af PA |
1744 | if (!(__supported_pte_mask & _PAGE_NX)) |
1745 | return 0; | |
1746 | ||
d75586ad | 1747 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1748 | } |
1749 | EXPORT_SYMBOL(set_memory_x); | |
1750 | ||
1751 | int set_memory_nx(unsigned long addr, int numpages) | |
1752 | { | |
583140af PA |
1753 | if (!(__supported_pte_mask & _PAGE_NX)) |
1754 | return 0; | |
1755 | ||
d75586ad | 1756 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1757 | } |
1758 | EXPORT_SYMBOL(set_memory_nx); | |
1759 | ||
1760 | int set_memory_ro(unsigned long addr, int numpages) | |
1761 | { | |
d75586ad | 1762 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1763 | } |
75cbade8 AV |
1764 | |
1765 | int set_memory_rw(unsigned long addr, int numpages) | |
1766 | { | |
d75586ad | 1767 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1768 | } |
f62d0f00 IM |
1769 | |
1770 | int set_memory_np(unsigned long addr, int numpages) | |
1771 | { | |
d75586ad | 1772 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1773 | } |
75cbade8 | 1774 | |
c9caa02c AK |
1775 | int set_memory_4k(unsigned long addr, int numpages) |
1776 | { | |
d75586ad | 1777 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1778 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1779 | } |
1780 | ||
39114b7a DH |
1781 | int set_memory_nonglobal(unsigned long addr, int numpages) |
1782 | { | |
1783 | return change_page_attr_clear(&addr, numpages, | |
1784 | __pgprot(_PAGE_GLOBAL), 0); | |
1785 | } | |
1786 | ||
eac7073a DH |
1787 | int set_memory_global(unsigned long addr, int numpages) |
1788 | { | |
1789 | return change_page_attr_set(&addr, numpages, | |
1790 | __pgprot(_PAGE_GLOBAL), 0); | |
1791 | } | |
1792 | ||
77bd2342 TL |
1793 | static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) |
1794 | { | |
1795 | struct cpa_data cpa; | |
1796 | unsigned long start; | |
1797 | int ret; | |
1798 | ||
a72ec5a3 TL |
1799 | /* Nothing to do if memory encryption is not active */ |
1800 | if (!mem_encrypt_active()) | |
77bd2342 TL |
1801 | return 0; |
1802 | ||
1803 | /* Should not be working on unaligned addresses */ | |
1804 | if (WARN_ONCE(addr & ~PAGE_MASK, "misaligned address: %#lx\n", addr)) | |
1805 | addr &= PAGE_MASK; | |
1806 | ||
1807 | start = addr; | |
1808 | ||
1809 | memset(&cpa, 0, sizeof(cpa)); | |
1810 | cpa.vaddr = &addr; | |
1811 | cpa.numpages = numpages; | |
1812 | cpa.mask_set = enc ? __pgprot(_PAGE_ENC) : __pgprot(0); | |
1813 | cpa.mask_clr = enc ? __pgprot(0) : __pgprot(_PAGE_ENC); | |
1814 | cpa.pgd = init_mm.pgd; | |
1815 | ||
1816 | /* Must avoid aliasing mappings in the highmem code */ | |
1817 | kmap_flush_unused(); | |
1818 | vm_unmap_aliases(); | |
1819 | ||
1820 | /* | |
1821 | * Before changing the encryption attribute, we need to flush caches. | |
1822 | */ | |
1823 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) | |
1824 | cpa_flush_range(start, numpages, 1); | |
1825 | else | |
1826 | cpa_flush_all(1); | |
1827 | ||
1828 | ret = __change_page_attr_set_clr(&cpa, 1); | |
1829 | ||
1830 | /* | |
1831 | * After changing the encryption attribute, we need to flush TLBs | |
1832 | * again in case any speculative TLB caching occurred (but no need | |
1833 | * to flush caches again). We could just use cpa_flush_all(), but | |
1834 | * in case TLB flushing gets optimized in the cpa_flush_range() | |
1835 | * path use the same logic as above. | |
1836 | */ | |
1837 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) | |
1838 | cpa_flush_range(start, numpages, 0); | |
1839 | else | |
1840 | cpa_flush_all(0); | |
1841 | ||
1842 | return ret; | |
1843 | } | |
1844 | ||
1845 | int set_memory_encrypted(unsigned long addr, int numpages) | |
1846 | { | |
1847 | return __set_memory_enc_dec(addr, numpages, true); | |
1848 | } | |
95cf9264 | 1849 | EXPORT_SYMBOL_GPL(set_memory_encrypted); |
77bd2342 TL |
1850 | |
1851 | int set_memory_decrypted(unsigned long addr, int numpages) | |
1852 | { | |
1853 | return __set_memory_enc_dec(addr, numpages, false); | |
1854 | } | |
95cf9264 | 1855 | EXPORT_SYMBOL_GPL(set_memory_decrypted); |
77bd2342 | 1856 | |
75cbade8 AV |
1857 | int set_pages_uc(struct page *page, int numpages) |
1858 | { | |
1859 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1860 | |
d7c8f21a | 1861 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1862 | } |
1863 | EXPORT_SYMBOL(set_pages_uc); | |
1864 | ||
4f646254 | 1865 | static int _set_pages_array(struct page **pages, int addrinarray, |
c06814d8 | 1866 | enum page_cache_mode new_type) |
0f350755 | 1867 | { |
1868 | unsigned long start; | |
1869 | unsigned long end; | |
623dffb2 | 1870 | enum page_cache_mode set_type; |
0f350755 | 1871 | int i; |
1872 | int free_idx; | |
4f646254 | 1873 | int ret; |
0f350755 | 1874 | |
1875 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1876 | if (PageHighMem(pages[i])) |
1877 | continue; | |
1878 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1879 | end = start + PAGE_SIZE; |
4f646254 | 1880 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 1881 | goto err_out; |
1882 | } | |
1883 | ||
623dffb2 TK |
1884 | /* If WC, set to UC- first and then WC */ |
1885 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1886 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1887 | ||
4f646254 | 1888 | ret = cpa_set_pages_array(pages, addrinarray, |
623dffb2 | 1889 | cachemode2pgprot(set_type)); |
c06814d8 | 1890 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1891 | ret = change_page_attr_set_clr(NULL, addrinarray, |
c06814d8 JG |
1892 | cachemode2pgprot( |
1893 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1894 | __pgprot(_PAGE_CACHE_MASK), |
1895 | 0, CPA_PAGES_ARRAY, pages); | |
1896 | if (ret) | |
1897 | goto err_out; | |
1898 | return 0; /* Success */ | |
0f350755 | 1899 | err_out: |
1900 | free_idx = i; | |
1901 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1902 | if (PageHighMem(pages[i])) |
1903 | continue; | |
1904 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1905 | end = start + PAGE_SIZE; |
1906 | free_memtype(start, end); | |
1907 | } | |
1908 | return -EINVAL; | |
1909 | } | |
4f646254 PN |
1910 | |
1911 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
1912 | { | |
c06814d8 | 1913 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1914 | } |
0f350755 | 1915 | EXPORT_SYMBOL(set_pages_array_uc); |
1916 | ||
4f646254 PN |
1917 | int set_pages_array_wc(struct page **pages, int addrinarray) |
1918 | { | |
c06814d8 | 1919 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1920 | } |
1921 | EXPORT_SYMBOL(set_pages_array_wc); | |
1922 | ||
623dffb2 TK |
1923 | int set_pages_array_wt(struct page **pages, int addrinarray) |
1924 | { | |
1925 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT); | |
1926 | } | |
1927 | EXPORT_SYMBOL_GPL(set_pages_array_wt); | |
1928 | ||
75cbade8 AV |
1929 | int set_pages_wb(struct page *page, int numpages) |
1930 | { | |
1931 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1932 | |
d7c8f21a | 1933 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1934 | } |
1935 | EXPORT_SYMBOL(set_pages_wb); | |
1936 | ||
0f350755 | 1937 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1938 | { | |
1939 | int retval; | |
1940 | unsigned long start; | |
1941 | unsigned long end; | |
1942 | int i; | |
1943 | ||
c06814d8 | 1944 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
0f350755 | 1945 | retval = cpa_clear_pages_array(pages, addrinarray, |
1946 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1947 | if (retval) |
1948 | return retval; | |
0f350755 | 1949 | |
1950 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1951 | if (PageHighMem(pages[i])) |
1952 | continue; | |
1953 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1954 | end = start + PAGE_SIZE; |
1955 | free_memtype(start, end); | |
1956 | } | |
1957 | ||
9fa3ab39 | 1958 | return 0; |
0f350755 | 1959 | } |
1960 | EXPORT_SYMBOL(set_pages_array_wb); | |
1961 | ||
75cbade8 AV |
1962 | int set_pages_x(struct page *page, int numpages) |
1963 | { | |
1964 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1965 | |
d7c8f21a | 1966 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1967 | } |
1968 | EXPORT_SYMBOL(set_pages_x); | |
1969 | ||
1970 | int set_pages_nx(struct page *page, int numpages) | |
1971 | { | |
1972 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1973 | |
d7c8f21a | 1974 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1975 | } |
1976 | EXPORT_SYMBOL(set_pages_nx); | |
1977 | ||
1978 | int set_pages_ro(struct page *page, int numpages) | |
1979 | { | |
1980 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1981 | |
d7c8f21a | 1982 | return set_memory_ro(addr, numpages); |
75cbade8 | 1983 | } |
75cbade8 AV |
1984 | |
1985 | int set_pages_rw(struct page *page, int numpages) | |
1986 | { | |
1987 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1988 | |
d7c8f21a | 1989 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1990 | } |
1991 | ||
1da177e4 | 1992 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1993 | |
1994 | static int __set_pages_p(struct page *page, int numpages) | |
1995 | { | |
d75586ad SL |
1996 | unsigned long tempaddr = (unsigned long) page_address(page); |
1997 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 1998 | .pgd = NULL, |
72e458df TG |
1999 | .numpages = numpages, |
2000 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
2001 | .mask_clr = __pgprot(0), |
2002 | .flags = 0}; | |
72932c7a | 2003 | |
55121b43 SS |
2004 | /* |
2005 | * No alias checking needed for setting present flag. otherwise, | |
2006 | * we may need to break large pages for 64-bit kernel text | |
2007 | * mappings (this adds to complexity if we want to do this from | |
2008 | * atomic context especially). Let's keep it simple! | |
2009 | */ | |
2010 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
2011 | } |
2012 | ||
2013 | static int __set_pages_np(struct page *page, int numpages) | |
2014 | { | |
d75586ad SL |
2015 | unsigned long tempaddr = (unsigned long) page_address(page); |
2016 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 2017 | .pgd = NULL, |
72e458df TG |
2018 | .numpages = numpages, |
2019 | .mask_set = __pgprot(0), | |
d75586ad SL |
2020 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
2021 | .flags = 0}; | |
72932c7a | 2022 | |
55121b43 SS |
2023 | /* |
2024 | * No alias checking needed for setting not present flag. otherwise, | |
2025 | * we may need to break large pages for 64-bit kernel text | |
2026 | * mappings (this adds to complexity if we want to do this from | |
2027 | * atomic context especially). Let's keep it simple! | |
2028 | */ | |
2029 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
2030 | } |
2031 | ||
031bc574 | 2032 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
1da177e4 LT |
2033 | { |
2034 | if (PageHighMem(page)) | |
2035 | return; | |
9f4c815c | 2036 | if (!enable) { |
f9b8404c IM |
2037 | debug_check_no_locks_freed(page_address(page), |
2038 | numpages * PAGE_SIZE); | |
9f4c815c | 2039 | } |
de5097c2 | 2040 | |
9f4c815c | 2041 | /* |
f8d8406b | 2042 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
2043 | * Large pages for identity mappings are not used at boot time |
2044 | * and hence no memory allocations during large page split. | |
1da177e4 | 2045 | */ |
f62d0f00 IM |
2046 | if (enable) |
2047 | __set_pages_p(page, numpages); | |
2048 | else | |
2049 | __set_pages_np(page, numpages); | |
9f4c815c IM |
2050 | |
2051 | /* | |
e4b71dcf IM |
2052 | * We should perform an IPI and flush all tlbs, |
2053 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
2054 | */ |
2055 | __flush_tlb_all(); | |
26564600 BO |
2056 | |
2057 | arch_flush_lazy_mmu_mode(); | |
ee7ae7a1 TG |
2058 | } |
2059 | ||
8a235efa RW |
2060 | #ifdef CONFIG_HIBERNATION |
2061 | ||
2062 | bool kernel_page_present(struct page *page) | |
2063 | { | |
2064 | unsigned int level; | |
2065 | pte_t *pte; | |
2066 | ||
2067 | if (PageHighMem(page)) | |
2068 | return false; | |
2069 | ||
2070 | pte = lookup_address((unsigned long)page_address(page), &level); | |
2071 | return (pte_val(*pte) & _PAGE_PRESENT); | |
2072 | } | |
2073 | ||
2074 | #endif /* CONFIG_HIBERNATION */ | |
2075 | ||
2076 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 | 2077 | |
82f0712c BP |
2078 | int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address, |
2079 | unsigned numpages, unsigned long page_flags) | |
2080 | { | |
2081 | int retval = -EINVAL; | |
2082 | ||
2083 | struct cpa_data cpa = { | |
2084 | .vaddr = &address, | |
2085 | .pfn = pfn, | |
2086 | .pgd = pgd, | |
2087 | .numpages = numpages, | |
2088 | .mask_set = __pgprot(0), | |
2089 | .mask_clr = __pgprot(0), | |
2090 | .flags = 0, | |
2091 | }; | |
2092 | ||
2093 | if (!(__supported_pte_mask & _PAGE_NX)) | |
2094 | goto out; | |
2095 | ||
2096 | if (!(page_flags & _PAGE_NX)) | |
2097 | cpa.mask_clr = __pgprot(_PAGE_NX); | |
2098 | ||
15f003d2 SP |
2099 | if (!(page_flags & _PAGE_RW)) |
2100 | cpa.mask_clr = __pgprot(_PAGE_RW); | |
2101 | ||
21729f81 TL |
2102 | if (!(page_flags & _PAGE_ENC)) |
2103 | cpa.mask_clr = pgprot_encrypted(cpa.mask_clr); | |
2104 | ||
82f0712c BP |
2105 | cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags); |
2106 | ||
2107 | retval = __change_page_attr_set_clr(&cpa, 0); | |
2108 | __flush_tlb_all(); | |
2109 | ||
2110 | out: | |
2111 | return retval; | |
2112 | } | |
2113 | ||
d1028a15 AV |
2114 | /* |
2115 | * The testcases use internal knowledge of the implementation that shouldn't | |
2116 | * be exposed to the rest of the kernel. Include these directly here. | |
2117 | */ | |
2118 | #ifdef CONFIG_CPA_DEBUG | |
2119 | #include "pageattr-test.c" | |
2120 | #endif |