agp: enable optimized agp_alloc_pages methods
[linux-2.6-block.git] / arch / x86 / mm / pageattr.c
CommitLineData
9f4c815c
IM
1/*
2 * Copyright 2002 Andi Kleen, SuSE Labs.
1da177e4 3 * Thanks to Ben LaHaise for precious feedback.
9f4c815c 4 */
1da177e4 5#include <linux/highmem.h>
8192206d 6#include <linux/bootmem.h>
1da177e4 7#include <linux/module.h>
9f4c815c 8#include <linux/sched.h>
1da177e4 9#include <linux/slab.h>
9f4c815c 10#include <linux/mm.h>
76ebd054 11#include <linux/interrupt.h>
ee7ae7a1
TG
12#include <linux/seq_file.h>
13#include <linux/debugfs.h>
9f4c815c 14
950f9d95 15#include <asm/e820.h>
1da177e4
LT
16#include <asm/processor.h>
17#include <asm/tlbflush.h>
f8af095d 18#include <asm/sections.h>
9f4c815c
IM
19#include <asm/uaccess.h>
20#include <asm/pgalloc.h>
c31c7d48 21#include <asm/proto.h>
1219333d 22#include <asm/pat.h>
1da177e4 23
9df84993
IM
24/*
25 * The current flushing context - we pass it instead of 5 arguments:
26 */
72e458df 27struct cpa_data {
d75586ad 28 unsigned long *vaddr;
72e458df
TG
29 pgprot_t mask_set;
30 pgprot_t mask_clr;
65e074df 31 int numpages;
d75586ad 32 int flags;
c31c7d48 33 unsigned long pfn;
c9caa02c 34 unsigned force_split : 1;
d75586ad 35 int curpage;
72e458df
TG
36};
37
d75586ad
SL
38#define CPA_FLUSHTLB 1
39#define CPA_ARRAY 2
40
65280e61 41#ifdef CONFIG_PROC_FS
ce0c0e50
AK
42static unsigned long direct_pages_count[PG_LEVEL_NUM];
43
65280e61 44void update_page_count(int level, unsigned long pages)
ce0c0e50 45{
ce0c0e50 46 unsigned long flags;
65280e61 47
ce0c0e50
AK
48 /* Protect against CPA */
49 spin_lock_irqsave(&pgd_lock, flags);
50 direct_pages_count[level] += pages;
51 spin_unlock_irqrestore(&pgd_lock, flags);
65280e61
TG
52}
53
54static void split_page_count(int level)
55{
56 direct_pages_count[level]--;
57 direct_pages_count[level - 1] += PTRS_PER_PTE;
58}
59
60int arch_report_meminfo(char *page)
61{
a06de630
HD
62 int n = sprintf(page, "DirectMap4k: %8lu kB\n",
63 direct_pages_count[PG_LEVEL_4K] << 2);
64#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
65 n += sprintf(page + n, "DirectMap2M: %8lu kB\n",
66 direct_pages_count[PG_LEVEL_2M] << 11);
67#else
68 n += sprintf(page + n, "DirectMap4M: %8lu kB\n",
69 direct_pages_count[PG_LEVEL_2M] << 12);
70#endif
65280e61 71#ifdef CONFIG_X86_64
a06de630
HD
72 if (direct_gbpages)
73 n += sprintf(page + n, "DirectMap1G: %8lu kB\n",
74 direct_pages_count[PG_LEVEL_1G] << 20);
ce0c0e50 75#endif
65280e61 76 return n;
ce0c0e50 77}
65280e61
TG
78#else
79static inline void split_page_count(int level) { }
80#endif
ce0c0e50 81
c31c7d48
TG
82#ifdef CONFIG_X86_64
83
84static inline unsigned long highmap_start_pfn(void)
85{
86 return __pa(_text) >> PAGE_SHIFT;
87}
88
89static inline unsigned long highmap_end_pfn(void)
90{
91 return __pa(round_up((unsigned long)_end, PMD_SIZE)) >> PAGE_SHIFT;
92}
93
94#endif
95
92cb54a3
IM
96#ifdef CONFIG_DEBUG_PAGEALLOC
97# define debug_pagealloc 1
98#else
99# define debug_pagealloc 0
100#endif
101
ed724be6
AV
102static inline int
103within(unsigned long addr, unsigned long start, unsigned long end)
687c4825 104{
ed724be6
AV
105 return addr >= start && addr < end;
106}
107
d7c8f21a
TG
108/*
109 * Flushing functions
110 */
cd8ddf1a 111
cd8ddf1a
TG
112/**
113 * clflush_cache_range - flush a cache range with clflush
114 * @addr: virtual start address
115 * @size: number of bytes to flush
116 *
117 * clflush is an unordered instruction which needs fencing with mfence
118 * to avoid ordering issues.
119 */
4c61afcd 120void clflush_cache_range(void *vaddr, unsigned int size)
d7c8f21a 121{
4c61afcd 122 void *vend = vaddr + size - 1;
d7c8f21a 123
cd8ddf1a 124 mb();
4c61afcd
IM
125
126 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
127 clflush(vaddr);
128 /*
129 * Flush any possible final partial cacheline:
130 */
131 clflush(vend);
132
cd8ddf1a 133 mb();
d7c8f21a
TG
134}
135
af1e6844 136static void __cpa_flush_all(void *arg)
d7c8f21a 137{
6bb8383b
AK
138 unsigned long cache = (unsigned long)arg;
139
d7c8f21a
TG
140 /*
141 * Flush all to work around Errata in early athlons regarding
142 * large page flushing.
143 */
144 __flush_tlb_all();
145
6bb8383b 146 if (cache && boot_cpu_data.x86_model >= 4)
d7c8f21a
TG
147 wbinvd();
148}
149
6bb8383b 150static void cpa_flush_all(unsigned long cache)
d7c8f21a
TG
151{
152 BUG_ON(irqs_disabled());
153
15c8b6c1 154 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
d7c8f21a
TG
155}
156
57a6a46a
TG
157static void __cpa_flush_range(void *arg)
158{
57a6a46a
TG
159 /*
160 * We could optimize that further and do individual per page
161 * tlb invalidates for a low number of pages. Caveat: we must
162 * flush the high aliases on 64bit as well.
163 */
164 __flush_tlb_all();
57a6a46a
TG
165}
166
6bb8383b 167static void cpa_flush_range(unsigned long start, int numpages, int cache)
57a6a46a 168{
4c61afcd
IM
169 unsigned int i, level;
170 unsigned long addr;
171
57a6a46a 172 BUG_ON(irqs_disabled());
4c61afcd 173 WARN_ON(PAGE_ALIGN(start) != start);
57a6a46a 174
15c8b6c1 175 on_each_cpu(__cpa_flush_range, NULL, 1);
57a6a46a 176
6bb8383b
AK
177 if (!cache)
178 return;
179
3b233e52
TG
180 /*
181 * We only need to flush on one CPU,
182 * clflush is a MESI-coherent instruction that
183 * will cause all other CPUs to flush the same
184 * cachelines:
185 */
4c61afcd
IM
186 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
187 pte_t *pte = lookup_address(addr, &level);
188
189 /*
190 * Only flush present addresses:
191 */
7bfb72e8 192 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
4c61afcd
IM
193 clflush_cache_range((void *) addr, PAGE_SIZE);
194 }
57a6a46a
TG
195}
196
d75586ad
SL
197static void cpa_flush_array(unsigned long *start, int numpages, int cache)
198{
199 unsigned int i, level;
200 unsigned long *addr;
201
202 BUG_ON(irqs_disabled());
203
204 on_each_cpu(__cpa_flush_range, NULL, 1);
205
206 if (!cache)
207 return;
208
209 /* 4M threshold */
210 if (numpages >= 1024) {
211 if (boot_cpu_data.x86_model >= 4)
212 wbinvd();
213 return;
214 }
215 /*
216 * We only need to flush on one CPU,
217 * clflush is a MESI-coherent instruction that
218 * will cause all other CPUs to flush the same
219 * cachelines:
220 */
221 for (i = 0, addr = start; i < numpages; i++, addr++) {
222 pte_t *pte = lookup_address(*addr, &level);
223
224 /*
225 * Only flush present addresses:
226 */
227 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
228 clflush_cache_range((void *) *addr, PAGE_SIZE);
229 }
230}
231
ed724be6
AV
232/*
233 * Certain areas of memory on x86 require very specific protection flags,
234 * for example the BIOS area or kernel text. Callers don't always get this
235 * right (again, ioremap() on BIOS memory is not uncommon) so this function
236 * checks and fixes these known static required protection bits.
237 */
c31c7d48
TG
238static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
239 unsigned long pfn)
ed724be6
AV
240{
241 pgprot_t forbidden = __pgprot(0);
242
687c4825 243 /*
ed724be6
AV
244 * The BIOS area between 640k and 1Mb needs to be executable for
245 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
687c4825 246 */
c31c7d48 247 if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
ed724be6
AV
248 pgprot_val(forbidden) |= _PAGE_NX;
249
250 /*
251 * The kernel text needs to be executable for obvious reasons
c31c7d48
TG
252 * Does not cover __inittext since that is gone later on. On
253 * 64bit we do not enforce !NX on the low mapping
ed724be6
AV
254 */
255 if (within(address, (unsigned long)_text, (unsigned long)_etext))
256 pgprot_val(forbidden) |= _PAGE_NX;
cc0f21bb 257
cc0f21bb 258 /*
c31c7d48
TG
259 * The .rodata section needs to be read-only. Using the pfn
260 * catches all aliases.
cc0f21bb 261 */
c31c7d48
TG
262 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
263 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
cc0f21bb 264 pgprot_val(forbidden) |= _PAGE_RW;
ed724be6
AV
265
266 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
687c4825
IM
267
268 return prot;
269}
270
9a14aefc
TG
271/*
272 * Lookup the page table entry for a virtual address. Return a pointer
273 * to the entry and the level of the mapping.
274 *
275 * Note: We return pud and pmd either when the entry is marked large
276 * or when the present bit is not set. Otherwise we would return a
277 * pointer to a nonexisting mapping.
278 */
da7bfc50 279pte_t *lookup_address(unsigned long address, unsigned int *level)
9f4c815c 280{
1da177e4
LT
281 pgd_t *pgd = pgd_offset_k(address);
282 pud_t *pud;
283 pmd_t *pmd;
9f4c815c 284
30551bb3
TG
285 *level = PG_LEVEL_NONE;
286
1da177e4
LT
287 if (pgd_none(*pgd))
288 return NULL;
9df84993 289
1da177e4
LT
290 pud = pud_offset(pgd, address);
291 if (pud_none(*pud))
292 return NULL;
c2f71ee2
AK
293
294 *level = PG_LEVEL_1G;
295 if (pud_large(*pud) || !pud_present(*pud))
296 return (pte_t *)pud;
297
1da177e4
LT
298 pmd = pmd_offset(pud, address);
299 if (pmd_none(*pmd))
300 return NULL;
30551bb3
TG
301
302 *level = PG_LEVEL_2M;
9a14aefc 303 if (pmd_large(*pmd) || !pmd_present(*pmd))
1da177e4 304 return (pte_t *)pmd;
1da177e4 305
30551bb3 306 *level = PG_LEVEL_4K;
9df84993 307
9f4c815c
IM
308 return pte_offset_kernel(pmd, address);
309}
75bb8835 310EXPORT_SYMBOL_GPL(lookup_address);
9f4c815c 311
9df84993
IM
312/*
313 * Set the new pmd in all the pgds we know about:
314 */
9a3dc780 315static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
9f4c815c 316{
9f4c815c
IM
317 /* change init_mm */
318 set_pte_atomic(kpte, pte);
44af6c41 319#ifdef CONFIG_X86_32
e4b71dcf 320 if (!SHARED_KERNEL_PMD) {
44af6c41
IM
321 struct page *page;
322
e3ed910d 323 list_for_each_entry(page, &pgd_list, lru) {
44af6c41
IM
324 pgd_t *pgd;
325 pud_t *pud;
326 pmd_t *pmd;
327
328 pgd = (pgd_t *)page_address(page) + pgd_index(address);
329 pud = pud_offset(pgd, address);
330 pmd = pmd_offset(pud, address);
331 set_pte_atomic((pte_t *)pmd, pte);
332 }
1da177e4 333 }
44af6c41 334#endif
1da177e4
LT
335}
336
9df84993
IM
337static int
338try_preserve_large_page(pte_t *kpte, unsigned long address,
339 struct cpa_data *cpa)
65e074df 340{
c31c7d48 341 unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
65e074df
TG
342 pte_t new_pte, old_pte, *tmp;
343 pgprot_t old_prot, new_prot;
fac84939 344 int i, do_split = 1;
da7bfc50 345 unsigned int level;
65e074df 346
c9caa02c
AK
347 if (cpa->force_split)
348 return 1;
349
65e074df
TG
350 spin_lock_irqsave(&pgd_lock, flags);
351 /*
352 * Check for races, another CPU might have split this page
353 * up already:
354 */
355 tmp = lookup_address(address, &level);
356 if (tmp != kpte)
357 goto out_unlock;
358
359 switch (level) {
360 case PG_LEVEL_2M:
31422c51
AK
361 psize = PMD_PAGE_SIZE;
362 pmask = PMD_PAGE_MASK;
65e074df 363 break;
f07333fd 364#ifdef CONFIG_X86_64
65e074df 365 case PG_LEVEL_1G:
5d3c8b21
AK
366 psize = PUD_PAGE_SIZE;
367 pmask = PUD_PAGE_MASK;
f07333fd
AK
368 break;
369#endif
65e074df 370 default:
beaff633 371 do_split = -EINVAL;
65e074df
TG
372 goto out_unlock;
373 }
374
375 /*
376 * Calculate the number of pages, which fit into this large
377 * page starting at address:
378 */
379 nextpage_addr = (address + psize) & pmask;
380 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
9b5cf48b
RW
381 if (numpages < cpa->numpages)
382 cpa->numpages = numpages;
65e074df
TG
383
384 /*
385 * We are safe now. Check whether the new pgprot is the same:
386 */
387 old_pte = *kpte;
388 old_prot = new_prot = pte_pgprot(old_pte);
389
390 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
391 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
c31c7d48
TG
392
393 /*
394 * old_pte points to the large page base address. So we need
395 * to add the offset of the virtual address:
396 */
397 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
398 cpa->pfn = pfn;
399
400 new_prot = static_protections(new_prot, address, pfn);
65e074df 401
fac84939
TG
402 /*
403 * We need to check the full range, whether
404 * static_protection() requires a different pgprot for one of
405 * the pages in the range we try to preserve:
406 */
407 addr = address + PAGE_SIZE;
c31c7d48 408 pfn++;
9b5cf48b 409 for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
c31c7d48 410 pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
fac84939
TG
411
412 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
413 goto out_unlock;
414 }
415
65e074df
TG
416 /*
417 * If there are no changes, return. maxpages has been updated
418 * above:
419 */
420 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
beaff633 421 do_split = 0;
65e074df
TG
422 goto out_unlock;
423 }
424
425 /*
426 * We need to change the attributes. Check, whether we can
427 * change the large page in one go. We request a split, when
428 * the address is not aligned and the number of pages is
429 * smaller than the number of pages in the large page. Note
430 * that we limited the number of possible pages already to
431 * the number of pages in the large page.
432 */
9b5cf48b 433 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
65e074df
TG
434 /*
435 * The address is aligned and the number of pages
436 * covers the full page.
437 */
438 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
439 __set_pmd_pte(kpte, address, new_pte);
d75586ad 440 cpa->flags |= CPA_FLUSHTLB;
beaff633 441 do_split = 0;
65e074df
TG
442 }
443
444out_unlock:
445 spin_unlock_irqrestore(&pgd_lock, flags);
9df84993 446
beaff633 447 return do_split;
65e074df
TG
448}
449
76ebd054
TG
450static LIST_HEAD(page_pool);
451static unsigned long pool_size, pool_pages, pool_low;
92cb54a3 452static unsigned long pool_used, pool_failed;
76ebd054 453
92cb54a3 454static void cpa_fill_pool(struct page **ret)
76ebd054 455{
76ebd054 456 gfp_t gfp = GFP_KERNEL;
92cb54a3
IM
457 unsigned long flags;
458 struct page *p;
76ebd054 459
76ebd054 460 /*
92cb54a3
IM
461 * Avoid recursion (on debug-pagealloc) and also signal
462 * our priority to get to these pagetables:
76ebd054 463 */
92cb54a3 464 if (current->flags & PF_MEMALLOC)
76ebd054 465 return;
92cb54a3 466 current->flags |= PF_MEMALLOC;
76ebd054 467
76ebd054 468 /*
92cb54a3 469 * Allocate atomically from atomic contexts:
76ebd054 470 */
92cb54a3
IM
471 if (in_atomic() || irqs_disabled() || debug_pagealloc)
472 gfp = GFP_ATOMIC | __GFP_NORETRY | __GFP_NOWARN;
76ebd054 473
92cb54a3 474 while (pool_pages < pool_size || (ret && !*ret)) {
76ebd054
TG
475 p = alloc_pages(gfp, 0);
476 if (!p) {
477 pool_failed++;
478 break;
479 }
92cb54a3
IM
480 /*
481 * If the call site needs a page right now, provide it:
482 */
483 if (ret && !*ret) {
484 *ret = p;
485 continue;
486 }
487 spin_lock_irqsave(&pgd_lock, flags);
76ebd054
TG
488 list_add(&p->lru, &page_pool);
489 pool_pages++;
92cb54a3 490 spin_unlock_irqrestore(&pgd_lock, flags);
76ebd054 491 }
92cb54a3
IM
492
493 current->flags &= ~PF_MEMALLOC;
76ebd054
TG
494}
495
496#define SHIFT_MB (20 - PAGE_SHIFT)
497#define ROUND_MB_GB ((1 << 10) - 1)
498#define SHIFT_MB_GB 10
499#define POOL_PAGES_PER_GB 16
500
501void __init cpa_init(void)
502{
503 struct sysinfo si;
504 unsigned long gb;
505
506 si_meminfo(&si);
507 /*
508 * Calculate the number of pool pages:
509 *
510 * Convert totalram (nr of pages) to MiB and round to the next
511 * GiB. Shift MiB to Gib and multiply the result by
512 * POOL_PAGES_PER_GB:
513 */
92cb54a3
IM
514 if (debug_pagealloc) {
515 gb = ((si.totalram >> SHIFT_MB) + ROUND_MB_GB) >> SHIFT_MB_GB;
516 pool_size = POOL_PAGES_PER_GB * gb;
517 } else {
518 pool_size = 1;
519 }
76ebd054
TG
520 pool_low = pool_size;
521
92cb54a3 522 cpa_fill_pool(NULL);
76ebd054
TG
523 printk(KERN_DEBUG
524 "CPA: page pool initialized %lu of %lu pages preallocated\n",
525 pool_pages, pool_size);
526}
527
7afe15b9 528static int split_large_page(pte_t *kpte, unsigned long address)
bb5c2dbd 529{
7b610eec 530 unsigned long flags, pfn, pfninc = 1;
9df84993 531 unsigned int i, level;
bb5c2dbd 532 pte_t *pbase, *tmp;
9df84993 533 pgprot_t ref_prot;
bb5c2dbd
IM
534 struct page *base;
535
eb5b5f02
TG
536 /*
537 * Get a page from the pool. The pool list is protected by the
538 * pgd_lock, which we have to take anyway for the split
539 * operation:
540 */
541 spin_lock_irqsave(&pgd_lock, flags);
542 if (list_empty(&page_pool)) {
543 spin_unlock_irqrestore(&pgd_lock, flags);
92cb54a3
IM
544 base = NULL;
545 cpa_fill_pool(&base);
546 if (!base)
547 return -ENOMEM;
548 spin_lock_irqsave(&pgd_lock, flags);
549 } else {
550 base = list_first_entry(&page_pool, struct page, lru);
551 list_del(&base->lru);
552 pool_pages--;
553
554 if (pool_pages < pool_low)
555 pool_low = pool_pages;
eb5b5f02
TG
556 }
557
bb5c2dbd
IM
558 /*
559 * Check for races, another CPU might have split this page
560 * up for us already:
561 */
562 tmp = lookup_address(address, &level);
6ce9fc17 563 if (tmp != kpte)
bb5c2dbd
IM
564 goto out_unlock;
565
bb5c2dbd 566 pbase = (pte_t *)page_address(base);
6944a9c8 567 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
07cf89c0 568 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
bb5c2dbd 569
f07333fd
AK
570#ifdef CONFIG_X86_64
571 if (level == PG_LEVEL_1G) {
572 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
573 pgprot_val(ref_prot) |= _PAGE_PSE;
f07333fd
AK
574 }
575#endif
576
63c1dcf4
TG
577 /*
578 * Get the target pfn from the original entry:
579 */
580 pfn = pte_pfn(*kpte);
f07333fd 581 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
63c1dcf4 582 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
bb5c2dbd 583
ce0c0e50 584 if (address >= (unsigned long)__va(0) &&
f361a450
YL
585 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
586 split_page_count(level);
587
588#ifdef CONFIG_X86_64
589 if (address >= (unsigned long)__va(1UL<<32) &&
65280e61
TG
590 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
591 split_page_count(level);
f361a450 592#endif
ce0c0e50 593
bb5c2dbd 594 /*
07cf89c0 595 * Install the new, split up pagetable. Important details here:
4c881ca1
HY
596 *
597 * On Intel the NX bit of all levels must be cleared to make a
598 * page executable. See section 4.13.2 of Intel 64 and IA-32
599 * Architectures Software Developer's Manual).
07cf89c0
TG
600 *
601 * Mark the entry present. The current mapping might be
602 * set to not present, which we preserved above.
bb5c2dbd 603 */
4c881ca1 604 ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
07cf89c0 605 pgprot_val(ref_prot) |= _PAGE_PRESENT;
9a3dc780 606 __set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
bb5c2dbd
IM
607 base = NULL;
608
609out_unlock:
eb5b5f02
TG
610 /*
611 * If we dropped out via the lookup_address check under
612 * pgd_lock then stick the page back into the pool:
613 */
614 if (base) {
615 list_add(&base->lru, &page_pool);
616 pool_pages++;
617 } else
618 pool_used++;
9a3dc780 619 spin_unlock_irqrestore(&pgd_lock, flags);
bb5c2dbd 620
bb5c2dbd
IM
621 return 0;
622}
623
c31c7d48 624static int __change_page_attr(struct cpa_data *cpa, int primary)
9f4c815c 625{
d75586ad 626 unsigned long address;
da7bfc50
HH
627 int do_split, err;
628 unsigned int level;
c31c7d48 629 pte_t *kpte, old_pte;
1da177e4 630
d75586ad
SL
631 if (cpa->flags & CPA_ARRAY)
632 address = cpa->vaddr[cpa->curpage];
633 else
634 address = *cpa->vaddr;
635
97f99fed 636repeat:
f0646e43 637 kpte = lookup_address(address, &level);
1da177e4 638 if (!kpte)
d1a4be63 639 return 0;
c31c7d48
TG
640
641 old_pte = *kpte;
642 if (!pte_val(old_pte)) {
643 if (!primary)
644 return 0;
875e40b9 645 WARN(1, KERN_WARNING "CPA: called for zero pte. "
c31c7d48 646 "vaddr = %lx cpa->vaddr = %lx\n", address,
d75586ad 647 *cpa->vaddr);
1da177e4 648 return -EINVAL;
c31c7d48 649 }
9f4c815c 650
30551bb3 651 if (level == PG_LEVEL_4K) {
c31c7d48 652 pte_t new_pte;
626c2c9d 653 pgprot_t new_prot = pte_pgprot(old_pte);
c31c7d48 654 unsigned long pfn = pte_pfn(old_pte);
86f03989 655
72e458df
TG
656 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
657 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
86f03989 658
c31c7d48 659 new_prot = static_protections(new_prot, address, pfn);
86f03989 660
626c2c9d
AV
661 /*
662 * We need to keep the pfn from the existing PTE,
663 * after all we're only going to change it's attributes
664 * not the memory it points to
665 */
c31c7d48
TG
666 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
667 cpa->pfn = pfn;
f4ae5da0
TG
668 /*
669 * Do we really change anything ?
670 */
671 if (pte_val(old_pte) != pte_val(new_pte)) {
672 set_pte_atomic(kpte, new_pte);
d75586ad 673 cpa->flags |= CPA_FLUSHTLB;
f4ae5da0 674 }
9b5cf48b 675 cpa->numpages = 1;
65e074df 676 return 0;
1da177e4 677 }
65e074df
TG
678
679 /*
680 * Check, whether we can keep the large page intact
681 * and just change the pte:
682 */
beaff633 683 do_split = try_preserve_large_page(kpte, address, cpa);
65e074df
TG
684 /*
685 * When the range fits into the existing large page,
9b5cf48b 686 * return. cp->numpages and cpa->tlbflush have been updated in
65e074df
TG
687 * try_large_page:
688 */
87f7f8fe
IM
689 if (do_split <= 0)
690 return do_split;
65e074df
TG
691
692 /*
693 * We have to split the large page:
694 */
87f7f8fe
IM
695 err = split_large_page(kpte, address);
696 if (!err) {
d75586ad 697 cpa->flags |= CPA_FLUSHTLB;
87f7f8fe
IM
698 goto repeat;
699 }
beaff633 700
87f7f8fe 701 return err;
9f4c815c 702}
1da177e4 703
c31c7d48
TG
704static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
705
706static int cpa_process_alias(struct cpa_data *cpa)
1da177e4 707{
c31c7d48 708 struct cpa_data alias_cpa;
f34b439f 709 int ret = 0;
d75586ad 710 unsigned long temp_cpa_vaddr, vaddr;
44af6c41 711
965194c1 712 if (cpa->pfn >= max_pfn_mapped)
c31c7d48 713 return 0;
626c2c9d 714
f361a450 715#ifdef CONFIG_X86_64
965194c1 716 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
f361a450
YL
717 return 0;
718#endif
f34b439f
TG
719 /*
720 * No need to redo, when the primary call touched the direct
721 * mapping already:
722 */
d75586ad
SL
723 if (cpa->flags & CPA_ARRAY)
724 vaddr = cpa->vaddr[cpa->curpage];
725 else
726 vaddr = *cpa->vaddr;
727
728 if (!(within(vaddr, PAGE_OFFSET,
f361a450
YL
729 PAGE_OFFSET + (max_low_pfn_mapped << PAGE_SHIFT))
730#ifdef CONFIG_X86_64
d75586ad 731 || within(vaddr, PAGE_OFFSET + (1UL<<32),
f361a450
YL
732 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))
733#endif
734 )) {
44af6c41 735
f34b439f 736 alias_cpa = *cpa;
d75586ad
SL
737 temp_cpa_vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT);
738 alias_cpa.vaddr = &temp_cpa_vaddr;
739 alias_cpa.flags &= ~CPA_ARRAY;
740
f34b439f
TG
741
742 ret = __change_page_attr_set_clr(&alias_cpa, 0);
743 }
44af6c41 744
44af6c41 745#ifdef CONFIG_X86_64
c31c7d48
TG
746 if (ret)
747 return ret;
f34b439f
TG
748 /*
749 * No need to redo, when the primary call touched the high
750 * mapping already:
751 */
d75586ad 752 if (within(vaddr, (unsigned long) _text, (unsigned long) _end))
f34b439f
TG
753 return 0;
754
488fd995 755 /*
0879750f
TG
756 * If the physical address is inside the kernel map, we need
757 * to touch the high mapped kernel as well:
488fd995 758 */
c31c7d48
TG
759 if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn()))
760 return 0;
0879750f 761
c31c7d48 762 alias_cpa = *cpa;
d75586ad
SL
763 temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base;
764 alias_cpa.vaddr = &temp_cpa_vaddr;
765 alias_cpa.flags &= ~CPA_ARRAY;
c31c7d48
TG
766
767 /*
768 * The high mapping range is imprecise, so ignore the return value.
769 */
770 __change_page_attr_set_clr(&alias_cpa, 0);
488fd995 771#endif
c31c7d48 772 return ret;
1da177e4
LT
773}
774
c31c7d48 775static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
ff31452b 776{
65e074df 777 int ret, numpages = cpa->numpages;
ff31452b 778
65e074df
TG
779 while (numpages) {
780 /*
781 * Store the remaining nr of pages for the large page
782 * preservation check.
783 */
9b5cf48b 784 cpa->numpages = numpages;
d75586ad
SL
785 /* for array changes, we can't use large page */
786 if (cpa->flags & CPA_ARRAY)
787 cpa->numpages = 1;
c31c7d48
TG
788
789 ret = __change_page_attr(cpa, checkalias);
ff31452b
TG
790 if (ret)
791 return ret;
ff31452b 792
c31c7d48
TG
793 if (checkalias) {
794 ret = cpa_process_alias(cpa);
795 if (ret)
796 return ret;
797 }
798
65e074df
TG
799 /*
800 * Adjust the number of pages with the result of the
801 * CPA operation. Either a large page has been
802 * preserved or a single page update happened.
803 */
9b5cf48b
RW
804 BUG_ON(cpa->numpages > numpages);
805 numpages -= cpa->numpages;
d75586ad
SL
806 if (cpa->flags & CPA_ARRAY)
807 cpa->curpage++;
808 else
809 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
810
65e074df 811 }
ff31452b
TG
812 return 0;
813}
814
6bb8383b
AK
815static inline int cache_attr(pgprot_t attr)
816{
817 return pgprot_val(attr) &
818 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
819}
820
d75586ad 821static int change_page_attr_set_clr(unsigned long *addr, int numpages,
c9caa02c 822 pgprot_t mask_set, pgprot_t mask_clr,
d75586ad 823 int force_split, int array)
ff31452b 824{
72e458df 825 struct cpa_data cpa;
cacf8906 826 int ret, cache, checkalias;
331e4065
TG
827
828 /*
829 * Check, if we are requested to change a not supported
830 * feature:
831 */
832 mask_set = canon_pgprot(mask_set);
833 mask_clr = canon_pgprot(mask_clr);
c9caa02c 834 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
331e4065
TG
835 return 0;
836
69b1415e 837 /* Ensure we are PAGE_SIZE aligned */
d75586ad
SL
838 if (!array) {
839 if (*addr & ~PAGE_MASK) {
840 *addr &= PAGE_MASK;
841 /*
842 * People should not be passing in unaligned addresses:
843 */
844 WARN_ON_ONCE(1);
845 }
846 } else {
847 int i;
848 for (i = 0; i < numpages; i++) {
849 if (addr[i] & ~PAGE_MASK) {
850 addr[i] &= PAGE_MASK;
851 WARN_ON_ONCE(1);
852 }
853 }
69b1415e
TG
854 }
855
5843d9a4
NP
856 /* Must avoid aliasing mappings in the highmem code */
857 kmap_flush_unused();
858
72e458df
TG
859 cpa.vaddr = addr;
860 cpa.numpages = numpages;
861 cpa.mask_set = mask_set;
862 cpa.mask_clr = mask_clr;
d75586ad
SL
863 cpa.flags = 0;
864 cpa.curpage = 0;
c9caa02c 865 cpa.force_split = force_split;
72e458df 866
d75586ad
SL
867 if (array)
868 cpa.flags |= CPA_ARRAY;
869
af96e443
TG
870 /* No alias checking for _NX bit modifications */
871 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
872
873 ret = __change_page_attr_set_clr(&cpa, checkalias);
ff31452b 874
f4ae5da0
TG
875 /*
876 * Check whether we really changed something:
877 */
d75586ad 878 if (!(cpa.flags & CPA_FLUSHTLB))
1ac2f7d5 879 goto out;
cacf8906 880
6bb8383b
AK
881 /*
882 * No need to flush, when we did not set any of the caching
883 * attributes:
884 */
885 cache = cache_attr(mask_set);
886
57a6a46a
TG
887 /*
888 * On success we use clflush, when the CPU supports it to
889 * avoid the wbindv. If the CPU does not support it and in the
af1e6844 890 * error case we fall back to cpa_flush_all (which uses
57a6a46a
TG
891 * wbindv):
892 */
d75586ad
SL
893 if (!ret && cpu_has_clflush) {
894 if (cpa.flags & CPA_ARRAY)
895 cpa_flush_array(addr, numpages, cache);
896 else
897 cpa_flush_range(*addr, numpages, cache);
898 } else
6bb8383b 899 cpa_flush_all(cache);
cacf8906 900
76ebd054 901out:
cacf8906
IM
902 cpa_fill_pool(NULL);
903
ff31452b
TG
904 return ret;
905}
906
d75586ad
SL
907static inline int change_page_attr_set(unsigned long *addr, int numpages,
908 pgprot_t mask, int array)
75cbade8 909{
d75586ad
SL
910 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
911 array);
75cbade8
AV
912}
913
d75586ad
SL
914static inline int change_page_attr_clear(unsigned long *addr, int numpages,
915 pgprot_t mask, int array)
72932c7a 916{
d75586ad
SL
917 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
918 array);
72932c7a
TG
919}
920
1219333d 921int _set_memory_uc(unsigned long addr, int numpages)
72932c7a 922{
de33c442
SS
923 /*
924 * for now UC MINUS. see comments in ioremap_nocache()
925 */
d75586ad
SL
926 return change_page_attr_set(&addr, numpages,
927 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
75cbade8 928}
1219333d 929
930int set_memory_uc(unsigned long addr, int numpages)
931{
de33c442
SS
932 /*
933 * for now UC MINUS. see comments in ioremap_nocache()
934 */
c15238df 935 if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
de33c442 936 _PAGE_CACHE_UC_MINUS, NULL))
1219333d 937 return -EINVAL;
938
939 return _set_memory_uc(addr, numpages);
940}
75cbade8
AV
941EXPORT_SYMBOL(set_memory_uc);
942
d75586ad
SL
943int set_memory_array_uc(unsigned long *addr, int addrinarray)
944{
c5e147cf
RH
945 unsigned long start;
946 unsigned long end;
d75586ad
SL
947 int i;
948 /*
949 * for now UC MINUS. see comments in ioremap_nocache()
950 */
951 for (i = 0; i < addrinarray; i++) {
c5e147cf
RH
952 start = __pa(addr[i]);
953 for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) {
954 if (end != __pa(addr[i + 1]))
955 break;
956 i++;
957 }
958 if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL))
d75586ad
SL
959 goto out;
960 }
961
962 return change_page_attr_set(addr, addrinarray,
963 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
964out:
c5e147cf
RH
965 for (i = 0; i < addrinarray; i++) {
966 unsigned long tmp = __pa(addr[i]);
967
968 if (tmp == start)
969 break;
970 for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) {
971 if (end != __pa(addr[i + 1]))
972 break;
973 i++;
974 }
975 free_memtype(tmp, end);
976 }
d75586ad
SL
977 return -EINVAL;
978}
979EXPORT_SYMBOL(set_memory_array_uc);
980
ef354af4 981int _set_memory_wc(unsigned long addr, int numpages)
982{
d75586ad
SL
983 return change_page_attr_set(&addr, numpages,
984 __pgprot(_PAGE_CACHE_WC), 0);
ef354af4 985}
986
987int set_memory_wc(unsigned long addr, int numpages)
988{
499f8f84 989 if (!pat_enabled)
ef354af4 990 return set_memory_uc(addr, numpages);
991
c15238df 992 if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
ef354af4 993 _PAGE_CACHE_WC, NULL))
994 return -EINVAL;
995
996 return _set_memory_wc(addr, numpages);
997}
998EXPORT_SYMBOL(set_memory_wc);
999
1219333d 1000int _set_memory_wb(unsigned long addr, int numpages)
75cbade8 1001{
d75586ad
SL
1002 return change_page_attr_clear(&addr, numpages,
1003 __pgprot(_PAGE_CACHE_MASK), 0);
75cbade8 1004}
1219333d 1005
1006int set_memory_wb(unsigned long addr, int numpages)
1007{
c15238df 1008 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1219333d 1009
1010 return _set_memory_wb(addr, numpages);
1011}
75cbade8
AV
1012EXPORT_SYMBOL(set_memory_wb);
1013
d75586ad
SL
1014int set_memory_array_wb(unsigned long *addr, int addrinarray)
1015{
1016 int i;
d75586ad 1017
c5e147cf
RH
1018 for (i = 0; i < addrinarray; i++) {
1019 unsigned long start = __pa(addr[i]);
1020 unsigned long end;
1021
1022 for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) {
1023 if (end != __pa(addr[i + 1]))
1024 break;
1025 i++;
1026 }
1027 free_memtype(start, end);
1028 }
d75586ad
SL
1029 return change_page_attr_clear(addr, addrinarray,
1030 __pgprot(_PAGE_CACHE_MASK), 1);
1031}
1032EXPORT_SYMBOL(set_memory_array_wb);
1033
75cbade8
AV
1034int set_memory_x(unsigned long addr, int numpages)
1035{
d75586ad 1036 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
75cbade8
AV
1037}
1038EXPORT_SYMBOL(set_memory_x);
1039
1040int set_memory_nx(unsigned long addr, int numpages)
1041{
d75586ad 1042 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
75cbade8
AV
1043}
1044EXPORT_SYMBOL(set_memory_nx);
1045
1046int set_memory_ro(unsigned long addr, int numpages)
1047{
d75586ad 1048 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
75cbade8 1049}
75cbade8
AV
1050
1051int set_memory_rw(unsigned long addr, int numpages)
1052{
d75586ad 1053 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
75cbade8 1054}
f62d0f00
IM
1055
1056int set_memory_np(unsigned long addr, int numpages)
1057{
d75586ad 1058 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
f62d0f00 1059}
75cbade8 1060
c9caa02c
AK
1061int set_memory_4k(unsigned long addr, int numpages)
1062{
d75586ad
SL
1063 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1064 __pgprot(0), 1, 0);
c9caa02c
AK
1065}
1066
75cbade8
AV
1067int set_pages_uc(struct page *page, int numpages)
1068{
1069 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1070
d7c8f21a 1071 return set_memory_uc(addr, numpages);
75cbade8
AV
1072}
1073EXPORT_SYMBOL(set_pages_uc);
1074
1075int set_pages_wb(struct page *page, int numpages)
1076{
1077 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1078
d7c8f21a 1079 return set_memory_wb(addr, numpages);
75cbade8
AV
1080}
1081EXPORT_SYMBOL(set_pages_wb);
1082
1083int set_pages_x(struct page *page, int numpages)
1084{
1085 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1086
d7c8f21a 1087 return set_memory_x(addr, numpages);
75cbade8
AV
1088}
1089EXPORT_SYMBOL(set_pages_x);
1090
1091int set_pages_nx(struct page *page, int numpages)
1092{
1093 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1094
d7c8f21a 1095 return set_memory_nx(addr, numpages);
75cbade8
AV
1096}
1097EXPORT_SYMBOL(set_pages_nx);
1098
1099int set_pages_ro(struct page *page, int numpages)
1100{
1101 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1102
d7c8f21a 1103 return set_memory_ro(addr, numpages);
75cbade8 1104}
75cbade8
AV
1105
1106int set_pages_rw(struct page *page, int numpages)
1107{
1108 unsigned long addr = (unsigned long)page_address(page);
e81d5dc4 1109
d7c8f21a 1110 return set_memory_rw(addr, numpages);
78c94aba
IM
1111}
1112
1da177e4 1113#ifdef CONFIG_DEBUG_PAGEALLOC
f62d0f00
IM
1114
1115static int __set_pages_p(struct page *page, int numpages)
1116{
d75586ad
SL
1117 unsigned long tempaddr = (unsigned long) page_address(page);
1118 struct cpa_data cpa = { .vaddr = &tempaddr,
72e458df
TG
1119 .numpages = numpages,
1120 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
d75586ad
SL
1121 .mask_clr = __pgprot(0),
1122 .flags = 0};
72932c7a 1123
c31c7d48 1124 return __change_page_attr_set_clr(&cpa, 1);
f62d0f00
IM
1125}
1126
1127static int __set_pages_np(struct page *page, int numpages)
1128{
d75586ad
SL
1129 unsigned long tempaddr = (unsigned long) page_address(page);
1130 struct cpa_data cpa = { .vaddr = &tempaddr,
72e458df
TG
1131 .numpages = numpages,
1132 .mask_set = __pgprot(0),
d75586ad
SL
1133 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1134 .flags = 0};
72932c7a 1135
c31c7d48 1136 return __change_page_attr_set_clr(&cpa, 1);
f62d0f00
IM
1137}
1138
1da177e4
LT
1139void kernel_map_pages(struct page *page, int numpages, int enable)
1140{
1141 if (PageHighMem(page))
1142 return;
9f4c815c 1143 if (!enable) {
f9b8404c
IM
1144 debug_check_no_locks_freed(page_address(page),
1145 numpages * PAGE_SIZE);
9f4c815c 1146 }
de5097c2 1147
12d6f21e
IM
1148 /*
1149 * If page allocator is not up yet then do not call c_p_a():
1150 */
1151 if (!debug_pagealloc_enabled)
1152 return;
1153
9f4c815c 1154 /*
f8d8406b
IM
1155 * The return value is ignored as the calls cannot fail.
1156 * Large pages are kept enabled at boot time, and are
1157 * split up quickly with DEBUG_PAGEALLOC. If a splitup
1158 * fails here (due to temporary memory shortage) no damage
1159 * is done because we just keep the largepage intact up
1160 * to the next attempt when it will likely be split up:
1da177e4 1161 */
f62d0f00
IM
1162 if (enable)
1163 __set_pages_p(page, numpages);
1164 else
1165 __set_pages_np(page, numpages);
9f4c815c
IM
1166
1167 /*
e4b71dcf
IM
1168 * We should perform an IPI and flush all tlbs,
1169 * but that can deadlock->flush only current cpu:
1da177e4
LT
1170 */
1171 __flush_tlb_all();
76ebd054
TG
1172
1173 /*
1174 * Try to refill the page pool here. We can do this only after
1175 * the tlb flush.
1176 */
92cb54a3 1177 cpa_fill_pool(NULL);
1da177e4 1178}
8a235efa 1179
ee7ae7a1
TG
1180#ifdef CONFIG_DEBUG_FS
1181static int dpa_show(struct seq_file *m, void *v)
1182{
1183 seq_puts(m, "DEBUG_PAGEALLOC\n");
1184 seq_printf(m, "pool_size : %lu\n", pool_size);
1185 seq_printf(m, "pool_pages : %lu\n", pool_pages);
1186 seq_printf(m, "pool_low : %lu\n", pool_low);
1187 seq_printf(m, "pool_used : %lu\n", pool_used);
1188 seq_printf(m, "pool_failed : %lu\n", pool_failed);
1189
1190 return 0;
1191}
1192
1193static int dpa_open(struct inode *inode, struct file *filp)
1194{
1195 return single_open(filp, dpa_show, NULL);
1196}
1197
1198static const struct file_operations dpa_fops = {
1199 .open = dpa_open,
1200 .read = seq_read,
1201 .llseek = seq_lseek,
1202 .release = single_release,
1203};
1204
a4928cff 1205static int __init debug_pagealloc_proc_init(void)
ee7ae7a1
TG
1206{
1207 struct dentry *de;
1208
1209 de = debugfs_create_file("debug_pagealloc", 0600, NULL, NULL,
1210 &dpa_fops);
1211 if (!de)
1212 return -ENOMEM;
1213
1214 return 0;
1215}
1216__initcall(debug_pagealloc_proc_init);
1217#endif
1218
8a235efa
RW
1219#ifdef CONFIG_HIBERNATION
1220
1221bool kernel_page_present(struct page *page)
1222{
1223 unsigned int level;
1224 pte_t *pte;
1225
1226 if (PageHighMem(page))
1227 return false;
1228
1229 pte = lookup_address((unsigned long)page_address(page), &level);
1230 return (pte_val(*pte) & _PAGE_PRESENT);
1231}
1232
1233#endif /* CONFIG_HIBERNATION */
1234
1235#endif /* CONFIG_DEBUG_PAGEALLOC */
d1028a15
AV
1236
1237/*
1238 * The testcases use internal knowledge of the implementation that shouldn't
1239 * be exposed to the rest of the kernel. Include these directly here.
1240 */
1241#ifdef CONFIG_CPA_DEBUG
1242#include "pageattr-test.c"
1243#endif