x86, crash: Unify ifdef
[linux-2.6-block.git] / arch / x86 / mm / pageattr.c
CommitLineData
9f4c815c
IM
1/*
2 * Copyright 2002 Andi Kleen, SuSE Labs.
1da177e4 3 * Thanks to Ben LaHaise for precious feedback.
9f4c815c 4 */
1da177e4 5#include <linux/highmem.h>
8192206d 6#include <linux/bootmem.h>
1da177e4 7#include <linux/module.h>
9f4c815c 8#include <linux/sched.h>
9f4c815c 9#include <linux/mm.h>
76ebd054 10#include <linux/interrupt.h>
ee7ae7a1
TG
11#include <linux/seq_file.h>
12#include <linux/debugfs.h>
e59a1bb2 13#include <linux/pfn.h>
8c4bfc6e 14#include <linux/percpu.h>
5a0e3ad6 15#include <linux/gfp.h>
5bd5a452 16#include <linux/pci.h>
9f4c815c 17
950f9d95 18#include <asm/e820.h>
1da177e4
LT
19#include <asm/processor.h>
20#include <asm/tlbflush.h>
f8af095d 21#include <asm/sections.h>
93dbda7c 22#include <asm/setup.h>
9f4c815c
IM
23#include <asm/uaccess.h>
24#include <asm/pgalloc.h>
c31c7d48 25#include <asm/proto.h>
1219333d 26#include <asm/pat.h>
1da177e4 27
9df84993
IM
28/*
29 * The current flushing context - we pass it instead of 5 arguments:
30 */
72e458df 31struct cpa_data {
d75586ad 32 unsigned long *vaddr;
0fd64c23 33 pgd_t *pgd;
72e458df
TG
34 pgprot_t mask_set;
35 pgprot_t mask_clr;
65e074df 36 int numpages;
d75586ad 37 int flags;
c31c7d48 38 unsigned long pfn;
c9caa02c 39 unsigned force_split : 1;
d75586ad 40 int curpage;
9ae28475 41 struct page **pages;
72e458df
TG
42};
43
ad5ca55f
SS
44/*
45 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
46 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
47 * entries change the page attribute in parallel to some other cpu
48 * splitting a large page entry along with changing the attribute.
49 */
50static DEFINE_SPINLOCK(cpa_lock);
51
d75586ad
SL
52#define CPA_FLUSHTLB 1
53#define CPA_ARRAY 2
9ae28475 54#define CPA_PAGES_ARRAY 4
d75586ad 55
65280e61 56#ifdef CONFIG_PROC_FS
ce0c0e50
AK
57static unsigned long direct_pages_count[PG_LEVEL_NUM];
58
65280e61 59void update_page_count(int level, unsigned long pages)
ce0c0e50 60{
ce0c0e50 61 /* Protect against CPA */
a79e53d8 62 spin_lock(&pgd_lock);
ce0c0e50 63 direct_pages_count[level] += pages;
a79e53d8 64 spin_unlock(&pgd_lock);
65280e61
TG
65}
66
67static void split_page_count(int level)
68{
69 direct_pages_count[level]--;
70 direct_pages_count[level - 1] += PTRS_PER_PTE;
71}
72
e1759c21 73void arch_report_meminfo(struct seq_file *m)
65280e61 74{
b9c3bfc2 75 seq_printf(m, "DirectMap4k: %8lu kB\n",
a06de630
HD
76 direct_pages_count[PG_LEVEL_4K] << 2);
77#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
b9c3bfc2 78 seq_printf(m, "DirectMap2M: %8lu kB\n",
a06de630
HD
79 direct_pages_count[PG_LEVEL_2M] << 11);
80#else
b9c3bfc2 81 seq_printf(m, "DirectMap4M: %8lu kB\n",
a06de630
HD
82 direct_pages_count[PG_LEVEL_2M] << 12);
83#endif
65280e61 84#ifdef CONFIG_X86_64
a06de630 85 if (direct_gbpages)
b9c3bfc2 86 seq_printf(m, "DirectMap1G: %8lu kB\n",
a06de630 87 direct_pages_count[PG_LEVEL_1G] << 20);
ce0c0e50
AK
88#endif
89}
65280e61
TG
90#else
91static inline void split_page_count(int level) { }
92#endif
ce0c0e50 93
c31c7d48
TG
94#ifdef CONFIG_X86_64
95
96static inline unsigned long highmap_start_pfn(void)
97{
fc8d7826 98 return __pa_symbol(_text) >> PAGE_SHIFT;
c31c7d48
TG
99}
100
101static inline unsigned long highmap_end_pfn(void)
102{
fc8d7826 103 return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
c31c7d48
TG
104}
105
106#endif
107
92cb54a3
IM
108#ifdef CONFIG_DEBUG_PAGEALLOC
109# define debug_pagealloc 1
110#else
111# define debug_pagealloc 0
112#endif
113
ed724be6
AV
114static inline int
115within(unsigned long addr, unsigned long start, unsigned long end)
687c4825 116{
ed724be6
AV
117 return addr >= start && addr < end;
118}
119
d7c8f21a
TG
120/*
121 * Flushing functions
122 */
cd8ddf1a 123
cd8ddf1a
TG
124/**
125 * clflush_cache_range - flush a cache range with clflush
9efc31b8 126 * @vaddr: virtual start address
cd8ddf1a
TG
127 * @size: number of bytes to flush
128 *
129 * clflush is an unordered instruction which needs fencing with mfence
130 * to avoid ordering issues.
131 */
4c61afcd 132void clflush_cache_range(void *vaddr, unsigned int size)
d7c8f21a 133{
4c61afcd 134 void *vend = vaddr + size - 1;
d7c8f21a 135
cd8ddf1a 136 mb();
4c61afcd
IM
137
138 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
139 clflush(vaddr);
140 /*
141 * Flush any possible final partial cacheline:
142 */
143 clflush(vend);
144
cd8ddf1a 145 mb();
d7c8f21a 146}
e517a5e9 147EXPORT_SYMBOL_GPL(clflush_cache_range);
d7c8f21a 148
af1e6844 149static void __cpa_flush_all(void *arg)
d7c8f21a 150{
6bb8383b
AK
151 unsigned long cache = (unsigned long)arg;
152
d7c8f21a
TG
153 /*
154 * Flush all to work around Errata in early athlons regarding
155 * large page flushing.
156 */
157 __flush_tlb_all();
158
0b827537 159 if (cache && boot_cpu_data.x86 >= 4)
d7c8f21a
TG
160 wbinvd();
161}
162
6bb8383b 163static void cpa_flush_all(unsigned long cache)
d7c8f21a
TG
164{
165 BUG_ON(irqs_disabled());
166
15c8b6c1 167 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
d7c8f21a
TG
168}
169
57a6a46a
TG
170static void __cpa_flush_range(void *arg)
171{
57a6a46a
TG
172 /*
173 * We could optimize that further and do individual per page
174 * tlb invalidates for a low number of pages. Caveat: we must
175 * flush the high aliases on 64bit as well.
176 */
177 __flush_tlb_all();
57a6a46a
TG
178}
179
6bb8383b 180static void cpa_flush_range(unsigned long start, int numpages, int cache)
57a6a46a 181{
4c61afcd
IM
182 unsigned int i, level;
183 unsigned long addr;
184
57a6a46a 185 BUG_ON(irqs_disabled());
4c61afcd 186 WARN_ON(PAGE_ALIGN(start) != start);
57a6a46a 187
15c8b6c1 188 on_each_cpu(__cpa_flush_range, NULL, 1);
57a6a46a 189
6bb8383b
AK
190 if (!cache)
191 return;
192
3b233e52
TG
193 /*
194 * We only need to flush on one CPU,
195 * clflush is a MESI-coherent instruction that
196 * will cause all other CPUs to flush the same
197 * cachelines:
198 */
4c61afcd
IM
199 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
200 pte_t *pte = lookup_address(addr, &level);
201
202 /*
203 * Only flush present addresses:
204 */
7bfb72e8 205 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
4c61afcd
IM
206 clflush_cache_range((void *) addr, PAGE_SIZE);
207 }
57a6a46a
TG
208}
209
9ae28475 210static void cpa_flush_array(unsigned long *start, int numpages, int cache,
211 int in_flags, struct page **pages)
d75586ad
SL
212{
213 unsigned int i, level;
2171787b 214 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
d75586ad
SL
215
216 BUG_ON(irqs_disabled());
217
2171787b 218 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
d75586ad 219
2171787b 220 if (!cache || do_wbinvd)
d75586ad
SL
221 return;
222
d75586ad
SL
223 /*
224 * We only need to flush on one CPU,
225 * clflush is a MESI-coherent instruction that
226 * will cause all other CPUs to flush the same
227 * cachelines:
228 */
9ae28475 229 for (i = 0; i < numpages; i++) {
230 unsigned long addr;
231 pte_t *pte;
232
233 if (in_flags & CPA_PAGES_ARRAY)
234 addr = (unsigned long)page_address(pages[i]);
235 else
236 addr = start[i];
237
238 pte = lookup_address(addr, &level);
d75586ad
SL
239
240 /*
241 * Only flush present addresses:
242 */
243 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
9ae28475 244 clflush_cache_range((void *)addr, PAGE_SIZE);
d75586ad
SL
245 }
246}
247
ed724be6
AV
248/*
249 * Certain areas of memory on x86 require very specific protection flags,
250 * for example the BIOS area or kernel text. Callers don't always get this
251 * right (again, ioremap() on BIOS memory is not uncommon) so this function
252 * checks and fixes these known static required protection bits.
253 */
c31c7d48
TG
254static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
255 unsigned long pfn)
ed724be6
AV
256{
257 pgprot_t forbidden = __pgprot(0);
258
687c4825 259 /*
ed724be6
AV
260 * The BIOS area between 640k and 1Mb needs to be executable for
261 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
687c4825 262 */
5bd5a452
MC
263#ifdef CONFIG_PCI_BIOS
264 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
ed724be6 265 pgprot_val(forbidden) |= _PAGE_NX;
5bd5a452 266#endif
ed724be6
AV
267
268 /*
269 * The kernel text needs to be executable for obvious reasons
c31c7d48
TG
270 * Does not cover __inittext since that is gone later on. On
271 * 64bit we do not enforce !NX on the low mapping
ed724be6
AV
272 */
273 if (within(address, (unsigned long)_text, (unsigned long)_etext))
274 pgprot_val(forbidden) |= _PAGE_NX;
cc0f21bb 275
cc0f21bb 276 /*
c31c7d48
TG
277 * The .rodata section needs to be read-only. Using the pfn
278 * catches all aliases.
cc0f21bb 279 */
fc8d7826
AD
280 if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
281 __pa_symbol(__end_rodata) >> PAGE_SHIFT))
cc0f21bb 282 pgprot_val(forbidden) |= _PAGE_RW;
ed724be6 283
55ca3cc1 284#if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
74e08179 285 /*
502f6604
SS
286 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
287 * kernel text mappings for the large page aligned text, rodata sections
288 * will be always read-only. For the kernel identity mappings covering
289 * the holes caused by this alignment can be anything that user asks.
74e08179
SS
290 *
291 * This will preserve the large page mappings for kernel text/data
292 * at no extra cost.
293 */
502f6604
SS
294 if (kernel_set_to_readonly &&
295 within(address, (unsigned long)_text,
281ff33b
SS
296 (unsigned long)__end_rodata_hpage_align)) {
297 unsigned int level;
298
299 /*
300 * Don't enforce the !RW mapping for the kernel text mapping,
301 * if the current mapping is already using small page mapping.
302 * No need to work hard to preserve large page mappings in this
303 * case.
304 *
305 * This also fixes the Linux Xen paravirt guest boot failure
306 * (because of unexpected read-only mappings for kernel identity
307 * mappings). In this paravirt guest case, the kernel text
308 * mapping and the kernel identity mapping share the same
309 * page-table pages. Thus we can't really use different
310 * protections for the kernel text and identity mappings. Also,
311 * these shared mappings are made of small page mappings.
312 * Thus this don't enforce !RW mapping for small page kernel
313 * text mapping logic will help Linux Xen parvirt guest boot
0d2eb44f 314 * as well.
281ff33b
SS
315 */
316 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
317 pgprot_val(forbidden) |= _PAGE_RW;
318 }
74e08179
SS
319#endif
320
ed724be6 321 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
687c4825
IM
322
323 return prot;
324}
325
0fd64c23
BP
326static pte_t *__lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
327 unsigned int *level)
9f4c815c 328{
1da177e4
LT
329 pud_t *pud;
330 pmd_t *pmd;
9f4c815c 331
30551bb3
TG
332 *level = PG_LEVEL_NONE;
333
1da177e4
LT
334 if (pgd_none(*pgd))
335 return NULL;
9df84993 336
1da177e4
LT
337 pud = pud_offset(pgd, address);
338 if (pud_none(*pud))
339 return NULL;
c2f71ee2
AK
340
341 *level = PG_LEVEL_1G;
342 if (pud_large(*pud) || !pud_present(*pud))
343 return (pte_t *)pud;
344
1da177e4
LT
345 pmd = pmd_offset(pud, address);
346 if (pmd_none(*pmd))
347 return NULL;
30551bb3
TG
348
349 *level = PG_LEVEL_2M;
9a14aefc 350 if (pmd_large(*pmd) || !pmd_present(*pmd))
1da177e4 351 return (pte_t *)pmd;
1da177e4 352
30551bb3 353 *level = PG_LEVEL_4K;
9df84993 354
9f4c815c
IM
355 return pte_offset_kernel(pmd, address);
356}
0fd64c23
BP
357
358/*
359 * Lookup the page table entry for a virtual address. Return a pointer
360 * to the entry and the level of the mapping.
361 *
362 * Note: We return pud and pmd either when the entry is marked large
363 * or when the present bit is not set. Otherwise we would return a
364 * pointer to a nonexisting mapping.
365 */
366pte_t *lookup_address(unsigned long address, unsigned int *level)
367{
368 return __lookup_address_in_pgd(pgd_offset_k(address), address, level);
369}
75bb8835 370EXPORT_SYMBOL_GPL(lookup_address);
9f4c815c 371
0fd64c23
BP
372static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address,
373 unsigned int *level)
374{
375 if (cpa->pgd)
376 return __lookup_address_in_pgd(cpa->pgd + pgd_index(address),
377 address, level);
378
379 return lookup_address(address, level);
380}
381
d7656534
DH
382/*
383 * This is necessary because __pa() does not work on some
384 * kinds of memory, like vmalloc() or the alloc_remap()
385 * areas on 32-bit NUMA systems. The percpu areas can
386 * end up in this kind of memory, for instance.
387 *
388 * This could be optimized, but it is only intended to be
389 * used at inititalization time, and keeping it
390 * unoptimized should increase the testing coverage for
391 * the more obscure platforms.
392 */
393phys_addr_t slow_virt_to_phys(void *__virt_addr)
394{
395 unsigned long virt_addr = (unsigned long)__virt_addr;
396 phys_addr_t phys_addr;
397 unsigned long offset;
398 enum pg_level level;
399 unsigned long psize;
400 unsigned long pmask;
401 pte_t *pte;
402
403 pte = lookup_address(virt_addr, &level);
404 BUG_ON(!pte);
405 psize = page_level_size(level);
406 pmask = page_level_mask(level);
407 offset = virt_addr & ~pmask;
408 phys_addr = pte_pfn(*pte) << PAGE_SHIFT;
409 return (phys_addr | offset);
410}
411EXPORT_SYMBOL_GPL(slow_virt_to_phys);
412
9df84993
IM
413/*
414 * Set the new pmd in all the pgds we know about:
415 */
9a3dc780 416static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
9f4c815c 417{
9f4c815c
IM
418 /* change init_mm */
419 set_pte_atomic(kpte, pte);
44af6c41 420#ifdef CONFIG_X86_32
e4b71dcf 421 if (!SHARED_KERNEL_PMD) {
44af6c41
IM
422 struct page *page;
423
e3ed910d 424 list_for_each_entry(page, &pgd_list, lru) {
44af6c41
IM
425 pgd_t *pgd;
426 pud_t *pud;
427 pmd_t *pmd;
428
429 pgd = (pgd_t *)page_address(page) + pgd_index(address);
430 pud = pud_offset(pgd, address);
431 pmd = pmd_offset(pud, address);
432 set_pte_atomic((pte_t *)pmd, pte);
433 }
1da177e4 434 }
44af6c41 435#endif
1da177e4
LT
436}
437
9df84993
IM
438static int
439try_preserve_large_page(pte_t *kpte, unsigned long address,
440 struct cpa_data *cpa)
65e074df 441{
a79e53d8 442 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn;
65e074df 443 pte_t new_pte, old_pte, *tmp;
64edc8ed 444 pgprot_t old_prot, new_prot, req_prot;
fac84939 445 int i, do_split = 1;
f3c4fbb6 446 enum pg_level level;
65e074df 447
c9caa02c
AK
448 if (cpa->force_split)
449 return 1;
450
a79e53d8 451 spin_lock(&pgd_lock);
65e074df
TG
452 /*
453 * Check for races, another CPU might have split this page
454 * up already:
455 */
82f0712c 456 tmp = _lookup_address_cpa(cpa, address, &level);
65e074df
TG
457 if (tmp != kpte)
458 goto out_unlock;
459
460 switch (level) {
461 case PG_LEVEL_2M:
f07333fd 462#ifdef CONFIG_X86_64
65e074df 463 case PG_LEVEL_1G:
f07333fd 464#endif
f3c4fbb6
DH
465 psize = page_level_size(level);
466 pmask = page_level_mask(level);
467 break;
65e074df 468 default:
beaff633 469 do_split = -EINVAL;
65e074df
TG
470 goto out_unlock;
471 }
472
473 /*
474 * Calculate the number of pages, which fit into this large
475 * page starting at address:
476 */
477 nextpage_addr = (address + psize) & pmask;
478 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
9b5cf48b
RW
479 if (numpages < cpa->numpages)
480 cpa->numpages = numpages;
65e074df
TG
481
482 /*
483 * We are safe now. Check whether the new pgprot is the same:
484 */
485 old_pte = *kpte;
f76cfa3c 486 old_prot = req_prot = pte_pgprot(old_pte);
65e074df 487
64edc8ed 488 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
489 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
c31c7d48 490
a8aed3e0
AA
491 /*
492 * Set the PSE and GLOBAL flags only if the PRESENT flag is
493 * set otherwise pmd_present/pmd_huge will return true even on
494 * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL
495 * for the ancient hardware that doesn't support it.
496 */
f76cfa3c
AA
497 if (pgprot_val(req_prot) & _PAGE_PRESENT)
498 pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL;
a8aed3e0 499 else
f76cfa3c 500 pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL);
a8aed3e0 501
f76cfa3c 502 req_prot = canon_pgprot(req_prot);
a8aed3e0 503
c31c7d48
TG
504 /*
505 * old_pte points to the large page base address. So we need
506 * to add the offset of the virtual address:
507 */
508 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
509 cpa->pfn = pfn;
510
64edc8ed 511 new_prot = static_protections(req_prot, address, pfn);
65e074df 512
fac84939
TG
513 /*
514 * We need to check the full range, whether
515 * static_protection() requires a different pgprot for one of
516 * the pages in the range we try to preserve:
517 */
64edc8ed 518 addr = address & pmask;
519 pfn = pte_pfn(old_pte);
520 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
521 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
fac84939
TG
522
523 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
524 goto out_unlock;
525 }
526
65e074df
TG
527 /*
528 * If there are no changes, return. maxpages has been updated
529 * above:
530 */
531 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
beaff633 532 do_split = 0;
65e074df
TG
533 goto out_unlock;
534 }
535
536 /*
537 * We need to change the attributes. Check, whether we can
538 * change the large page in one go. We request a split, when
539 * the address is not aligned and the number of pages is
540 * smaller than the number of pages in the large page. Note
541 * that we limited the number of possible pages already to
542 * the number of pages in the large page.
543 */
64edc8ed 544 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
65e074df
TG
545 /*
546 * The address is aligned and the number of pages
547 * covers the full page.
548 */
a8aed3e0 549 new_pte = pfn_pte(pte_pfn(old_pte), new_prot);
65e074df 550 __set_pmd_pte(kpte, address, new_pte);
d75586ad 551 cpa->flags |= CPA_FLUSHTLB;
beaff633 552 do_split = 0;
65e074df
TG
553 }
554
555out_unlock:
a79e53d8 556 spin_unlock(&pgd_lock);
9df84993 557
beaff633 558 return do_split;
65e074df
TG
559}
560
5952886b 561static int
82f0712c
BP
562__split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,
563 struct page *base)
bb5c2dbd 564{
5952886b 565 pte_t *pbase = (pte_t *)page_address(base);
a79e53d8 566 unsigned long pfn, pfninc = 1;
9df84993 567 unsigned int i, level;
ae9aae9e 568 pte_t *tmp;
9df84993 569 pgprot_t ref_prot;
bb5c2dbd 570
a79e53d8 571 spin_lock(&pgd_lock);
bb5c2dbd
IM
572 /*
573 * Check for races, another CPU might have split this page
574 * up for us already:
575 */
82f0712c 576 tmp = _lookup_address_cpa(cpa, address, &level);
ae9aae9e
WC
577 if (tmp != kpte) {
578 spin_unlock(&pgd_lock);
579 return 1;
580 }
bb5c2dbd 581
6944a9c8 582 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
07cf89c0 583 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
7a5714e0
IM
584 /*
585 * If we ever want to utilize the PAT bit, we need to
586 * update this function to make sure it's converted from
587 * bit 12 to bit 7 when we cross from the 2MB level to
588 * the 4K level:
589 */
590 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
bb5c2dbd 591
f07333fd
AK
592#ifdef CONFIG_X86_64
593 if (level == PG_LEVEL_1G) {
594 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
a8aed3e0
AA
595 /*
596 * Set the PSE flags only if the PRESENT flag is set
597 * otherwise pmd_present/pmd_huge will return true
598 * even on a non present pmd.
599 */
600 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
601 pgprot_val(ref_prot) |= _PAGE_PSE;
602 else
603 pgprot_val(ref_prot) &= ~_PAGE_PSE;
f07333fd
AK
604 }
605#endif
606
a8aed3e0
AA
607 /*
608 * Set the GLOBAL flags only if the PRESENT flag is set
609 * otherwise pmd/pte_present will return true even on a non
610 * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL
611 * for the ancient hardware that doesn't support it.
612 */
613 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
614 pgprot_val(ref_prot) |= _PAGE_GLOBAL;
615 else
616 pgprot_val(ref_prot) &= ~_PAGE_GLOBAL;
617
63c1dcf4
TG
618 /*
619 * Get the target pfn from the original entry:
620 */
621 pfn = pte_pfn(*kpte);
f07333fd 622 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
a8aed3e0 623 set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot)));
bb5c2dbd 624
8eb5779f
YL
625 if (pfn_range_is_mapped(PFN_DOWN(__pa(address)),
626 PFN_DOWN(__pa(address)) + 1))
f361a450
YL
627 split_page_count(level);
628
bb5c2dbd 629 /*
07a66d7c 630 * Install the new, split up pagetable.
4c881ca1 631 *
07a66d7c
IM
632 * We use the standard kernel pagetable protections for the new
633 * pagetable protections, the actual ptes set above control the
634 * primary protection behavior:
bb5c2dbd 635 */
07a66d7c 636 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
211b3d03
IM
637
638 /*
639 * Intel Atom errata AAH41 workaround.
640 *
641 * The real fix should be in hw or in a microcode update, but
642 * we also probabilistically try to reduce the window of having
643 * a large TLB mixed with 4K TLBs while instruction fetches are
644 * going on.
645 */
646 __flush_tlb_all();
ae9aae9e 647 spin_unlock(&pgd_lock);
211b3d03 648
ae9aae9e
WC
649 return 0;
650}
bb5c2dbd 651
82f0712c
BP
652static int split_large_page(struct cpa_data *cpa, pte_t *kpte,
653 unsigned long address)
ae9aae9e 654{
ae9aae9e
WC
655 struct page *base;
656
657 if (!debug_pagealloc)
658 spin_unlock(&cpa_lock);
659 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
660 if (!debug_pagealloc)
661 spin_lock(&cpa_lock);
662 if (!base)
663 return -ENOMEM;
664
82f0712c 665 if (__split_large_page(cpa, kpte, address, base))
8311eb84 666 __free_page(base);
bb5c2dbd 667
bb5c2dbd
IM
668 return 0;
669}
670
52a628fb
BP
671static bool try_to_free_pte_page(pte_t *pte)
672{
673 int i;
674
675 for (i = 0; i < PTRS_PER_PTE; i++)
676 if (!pte_none(pte[i]))
677 return false;
678
679 free_page((unsigned long)pte);
680 return true;
681}
682
683static bool try_to_free_pmd_page(pmd_t *pmd)
684{
685 int i;
686
687 for (i = 0; i < PTRS_PER_PMD; i++)
688 if (!pmd_none(pmd[i]))
689 return false;
690
691 free_page((unsigned long)pmd);
692 return true;
693}
694
695static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end)
696{
697 pte_t *pte = pte_offset_kernel(pmd, start);
698
699 while (start < end) {
700 set_pte(pte, __pte(0));
701
702 start += PAGE_SIZE;
703 pte++;
704 }
705
706 if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) {
707 pmd_clear(pmd);
708 return true;
709 }
710 return false;
711}
712
713static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd,
714 unsigned long start, unsigned long end)
715{
716 if (unmap_pte_range(pmd, start, end))
717 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
718 pud_clear(pud);
719}
720
721static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end)
722{
723 pmd_t *pmd = pmd_offset(pud, start);
724
725 /*
726 * Not on a 2MB page boundary?
727 */
728 if (start & (PMD_SIZE - 1)) {
729 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
730 unsigned long pre_end = min_t(unsigned long, end, next_page);
731
732 __unmap_pmd_range(pud, pmd, start, pre_end);
733
734 start = pre_end;
735 pmd++;
736 }
737
738 /*
739 * Try to unmap in 2M chunks.
740 */
741 while (end - start >= PMD_SIZE) {
742 if (pmd_large(*pmd))
743 pmd_clear(pmd);
744 else
745 __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE);
746
747 start += PMD_SIZE;
748 pmd++;
749 }
750
751 /*
752 * 4K leftovers?
753 */
754 if (start < end)
755 return __unmap_pmd_range(pud, pmd, start, end);
756
757 /*
758 * Try again to free the PMD page if haven't succeeded above.
759 */
760 if (!pud_none(*pud))
761 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
762 pud_clear(pud);
763}
0bb8aeee
BP
764
765static void unmap_pud_range(pgd_t *pgd, unsigned long start, unsigned long end)
766{
767 pud_t *pud = pud_offset(pgd, start);
768
769 /*
770 * Not on a GB page boundary?
771 */
772 if (start & (PUD_SIZE - 1)) {
773 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
774 unsigned long pre_end = min_t(unsigned long, end, next_page);
775
776 unmap_pmd_range(pud, start, pre_end);
777
778 start = pre_end;
779 pud++;
780 }
781
782 /*
783 * Try to unmap in 1G chunks?
784 */
785 while (end - start >= PUD_SIZE) {
786
787 if (pud_large(*pud))
788 pud_clear(pud);
789 else
790 unmap_pmd_range(pud, start, start + PUD_SIZE);
791
792 start += PUD_SIZE;
793 pud++;
794 }
795
796 /*
797 * 2M leftovers?
798 */
799 if (start < end)
800 unmap_pmd_range(pud, start, end);
801
802 /*
803 * No need to try to free the PUD page because we'll free it in
804 * populate_pgd's error path
805 */
806}
807
f900a4b8
BP
808static int alloc_pte_page(pmd_t *pmd)
809{
810 pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK);
811 if (!pte)
812 return -1;
813
814 set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE));
815 return 0;
816}
817
4b23538d
BP
818static int alloc_pmd_page(pud_t *pud)
819{
820 pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK);
821 if (!pmd)
822 return -1;
823
824 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
825 return 0;
826}
827
c6b6f363
BP
828static void populate_pte(struct cpa_data *cpa,
829 unsigned long start, unsigned long end,
830 unsigned num_pages, pmd_t *pmd, pgprot_t pgprot)
831{
832 pte_t *pte;
833
834 pte = pte_offset_kernel(pmd, start);
835
836 while (num_pages-- && start < end) {
837
838 /* deal with the NX bit */
839 if (!(pgprot_val(pgprot) & _PAGE_NX))
840 cpa->pfn &= ~_PAGE_NX;
841
842 set_pte(pte, pfn_pte(cpa->pfn >> PAGE_SHIFT, pgprot));
843
844 start += PAGE_SIZE;
845 cpa->pfn += PAGE_SIZE;
846 pte++;
847 }
848}
f900a4b8
BP
849
850static int populate_pmd(struct cpa_data *cpa,
851 unsigned long start, unsigned long end,
852 unsigned num_pages, pud_t *pud, pgprot_t pgprot)
853{
854 unsigned int cur_pages = 0;
855 pmd_t *pmd;
856
857 /*
858 * Not on a 2M boundary?
859 */
860 if (start & (PMD_SIZE - 1)) {
861 unsigned long pre_end = start + (num_pages << PAGE_SHIFT);
862 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
863
864 pre_end = min_t(unsigned long, pre_end, next_page);
865 cur_pages = (pre_end - start) >> PAGE_SHIFT;
866 cur_pages = min_t(unsigned int, num_pages, cur_pages);
867
868 /*
869 * Need a PTE page?
870 */
871 pmd = pmd_offset(pud, start);
872 if (pmd_none(*pmd))
873 if (alloc_pte_page(pmd))
874 return -1;
875
876 populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot);
877
878 start = pre_end;
879 }
880
881 /*
882 * We mapped them all?
883 */
884 if (num_pages == cur_pages)
885 return cur_pages;
886
887 while (end - start >= PMD_SIZE) {
888
889 /*
890 * We cannot use a 1G page so allocate a PMD page if needed.
891 */
892 if (pud_none(*pud))
893 if (alloc_pmd_page(pud))
894 return -1;
895
896 pmd = pmd_offset(pud, start);
897
898 set_pmd(pmd, __pmd(cpa->pfn | _PAGE_PSE | massage_pgprot(pgprot)));
899
900 start += PMD_SIZE;
901 cpa->pfn += PMD_SIZE;
902 cur_pages += PMD_SIZE >> PAGE_SHIFT;
903 }
904
905 /*
906 * Map trailing 4K pages.
907 */
908 if (start < end) {
909 pmd = pmd_offset(pud, start);
910 if (pmd_none(*pmd))
911 if (alloc_pte_page(pmd))
912 return -1;
913
914 populate_pte(cpa, start, end, num_pages - cur_pages,
915 pmd, pgprot);
916 }
917 return num_pages;
918}
4b23538d
BP
919
920static int populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd,
921 pgprot_t pgprot)
922{
923 pud_t *pud;
924 unsigned long end;
925 int cur_pages = 0;
926
927 end = start + (cpa->numpages << PAGE_SHIFT);
928
929 /*
930 * Not on a Gb page boundary? => map everything up to it with
931 * smaller pages.
932 */
933 if (start & (PUD_SIZE - 1)) {
934 unsigned long pre_end;
935 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
936
937 pre_end = min_t(unsigned long, end, next_page);
938 cur_pages = (pre_end - start) >> PAGE_SHIFT;
939 cur_pages = min_t(int, (int)cpa->numpages, cur_pages);
940
941 pud = pud_offset(pgd, start);
942
943 /*
944 * Need a PMD page?
945 */
946 if (pud_none(*pud))
947 if (alloc_pmd_page(pud))
948 return -1;
949
950 cur_pages = populate_pmd(cpa, start, pre_end, cur_pages,
951 pud, pgprot);
952 if (cur_pages < 0)
953 return cur_pages;
954
955 start = pre_end;
956 }
957
958 /* We mapped them all? */
959 if (cpa->numpages == cur_pages)
960 return cur_pages;
961
962 pud = pud_offset(pgd, start);
963
964 /*
965 * Map everything starting from the Gb boundary, possibly with 1G pages
966 */
967 while (end - start >= PUD_SIZE) {
968 set_pud(pud, __pud(cpa->pfn | _PAGE_PSE | massage_pgprot(pgprot)));
969
970 start += PUD_SIZE;
971 cpa->pfn += PUD_SIZE;
972 cur_pages += PUD_SIZE >> PAGE_SHIFT;
973 pud++;
974 }
975
976 /* Map trailing leftover */
977 if (start < end) {
978 int tmp;
979
980 pud = pud_offset(pgd, start);
981 if (pud_none(*pud))
982 if (alloc_pmd_page(pud))
983 return -1;
984
985 tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages,
986 pud, pgprot);
987 if (tmp < 0)
988 return cur_pages;
989
990 cur_pages += tmp;
991 }
992 return cur_pages;
993}
f3f72966
BP
994
995/*
996 * Restrictions for kernel page table do not necessarily apply when mapping in
997 * an alternate PGD.
998 */
999static int populate_pgd(struct cpa_data *cpa, unsigned long addr)
1000{
1001 pgprot_t pgprot = __pgprot(_KERNPG_TABLE);
1002 bool allocd_pgd = false;
1003 pgd_t *pgd_entry;
1004 pud_t *pud = NULL; /* shut up gcc */
1005 int ret;
1006
1007 pgd_entry = cpa->pgd + pgd_index(addr);
1008
1009 /*
1010 * Allocate a PUD page and hand it down for mapping.
1011 */
1012 if (pgd_none(*pgd_entry)) {
1013 pud = (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK);
1014 if (!pud)
1015 return -1;
1016
1017 set_pgd(pgd_entry, __pgd(__pa(pud) | _KERNPG_TABLE));
1018 allocd_pgd = true;
1019 }
1020
1021 pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr);
1022 pgprot_val(pgprot) |= pgprot_val(cpa->mask_set);
1023
1024 ret = populate_pud(cpa, addr, pgd_entry, pgprot);
0bb8aeee
BP
1025 if (ret < 0) {
1026 unmap_pud_range(pgd_entry, addr,
1027 addr + (cpa->numpages << PAGE_SHIFT));
1028
1029 if (allocd_pgd) {
1030 /*
1031 * If I allocated this PUD page, I can just as well
1032 * free it in this error path.
1033 */
1034 pgd_clear(pgd_entry);
1035 free_page((unsigned long)pud);
1036 }
f3f72966 1037 return ret;
0bb8aeee 1038 }
f3f72966
BP
1039 cpa->numpages = ret;
1040 return 0;
1041}
1042
a1e46212
SS
1043static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
1044 int primary)
1045{
82f0712c
BP
1046 if (cpa->pgd)
1047 return populate_pgd(cpa, vaddr);
1048
a1e46212
SS
1049 /*
1050 * Ignore all non primary paths.
1051 */
1052 if (!primary)
1053 return 0;
1054
1055 /*
1056 * Ignore the NULL PTE for kernel identity mapping, as it is expected
1057 * to have holes.
1058 * Also set numpages to '1' indicating that we processed cpa req for
1059 * one virtual address page and its pfn. TBD: numpages can be set based
1060 * on the initial value and the level returned by lookup_address().
1061 */
1062 if (within(vaddr, PAGE_OFFSET,
1063 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
1064 cpa->numpages = 1;
1065 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
1066 return 0;
1067 } else {
1068 WARN(1, KERN_WARNING "CPA: called for zero pte. "
1069 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
1070 *cpa->vaddr);
1071
1072 return -EFAULT;
1073 }
1074}
1075
c31c7d48 1076static int __change_page_attr(struct cpa_data *cpa, int primary)
9f4c815c 1077{
d75586ad 1078 unsigned long address;
da7bfc50
HH
1079 int do_split, err;
1080 unsigned int level;
c31c7d48 1081 pte_t *kpte, old_pte;
1da177e4 1082
8523acfe
TH
1083 if (cpa->flags & CPA_PAGES_ARRAY) {
1084 struct page *page = cpa->pages[cpa->curpage];
1085 if (unlikely(PageHighMem(page)))
1086 return 0;
1087 address = (unsigned long)page_address(page);
1088 } else if (cpa->flags & CPA_ARRAY)
d75586ad
SL
1089 address = cpa->vaddr[cpa->curpage];
1090 else
1091 address = *cpa->vaddr;
97f99fed 1092repeat:
82f0712c 1093 kpte = _lookup_address_cpa(cpa, address, &level);
1da177e4 1094 if (!kpte)
a1e46212 1095 return __cpa_process_fault(cpa, address, primary);
c31c7d48
TG
1096
1097 old_pte = *kpte;
a1e46212
SS
1098 if (!pte_val(old_pte))
1099 return __cpa_process_fault(cpa, address, primary);
9f4c815c 1100
30551bb3 1101 if (level == PG_LEVEL_4K) {
c31c7d48 1102 pte_t new_pte;
626c2c9d 1103 pgprot_t new_prot = pte_pgprot(old_pte);
c31c7d48 1104 unsigned long pfn = pte_pfn(old_pte);
86f03989 1105
72e458df
TG
1106 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
1107 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
86f03989 1108
c31c7d48 1109 new_prot = static_protections(new_prot, address, pfn);
86f03989 1110
a8aed3e0
AA
1111 /*
1112 * Set the GLOBAL flags only if the PRESENT flag is
1113 * set otherwise pte_present will return true even on
1114 * a non present pte. The canon_pgprot will clear
1115 * _PAGE_GLOBAL for the ancient hardware that doesn't
1116 * support it.
1117 */
1118 if (pgprot_val(new_prot) & _PAGE_PRESENT)
1119 pgprot_val(new_prot) |= _PAGE_GLOBAL;
1120 else
1121 pgprot_val(new_prot) &= ~_PAGE_GLOBAL;
1122
626c2c9d
AV
1123 /*
1124 * We need to keep the pfn from the existing PTE,
1125 * after all we're only going to change it's attributes
1126 * not the memory it points to
1127 */
c31c7d48
TG
1128 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
1129 cpa->pfn = pfn;
f4ae5da0
TG
1130 /*
1131 * Do we really change anything ?
1132 */
1133 if (pte_val(old_pte) != pte_val(new_pte)) {
1134 set_pte_atomic(kpte, new_pte);
d75586ad 1135 cpa->flags |= CPA_FLUSHTLB;
f4ae5da0 1136 }
9b5cf48b 1137 cpa->numpages = 1;
65e074df 1138 return 0;
1da177e4 1139 }
65e074df
TG
1140
1141 /*
1142 * Check, whether we can keep the large page intact
1143 * and just change the pte:
1144 */
beaff633 1145 do_split = try_preserve_large_page(kpte, address, cpa);
65e074df
TG
1146 /*
1147 * When the range fits into the existing large page,
9b5cf48b 1148 * return. cp->numpages and cpa->tlbflush have been updated in
65e074df
TG
1149 * try_large_page:
1150 */
87f7f8fe
IM
1151 if (do_split <= 0)
1152 return do_split;
65e074df
TG
1153
1154 /*
1155 * We have to split the large page:
1156 */
82f0712c 1157 err = split_large_page(cpa, kpte, address);
87f7f8fe 1158 if (!err) {
ad5ca55f
SS
1159 /*
1160 * Do a global flush tlb after splitting the large page
1161 * and before we do the actual change page attribute in the PTE.
1162 *
1163 * With out this, we violate the TLB application note, that says
1164 * "The TLBs may contain both ordinary and large-page
1165 * translations for a 4-KByte range of linear addresses. This
1166 * may occur if software modifies the paging structures so that
1167 * the page size used for the address range changes. If the two
1168 * translations differ with respect to page frame or attributes
1169 * (e.g., permissions), processor behavior is undefined and may
1170 * be implementation-specific."
1171 *
1172 * We do this global tlb flush inside the cpa_lock, so that we
1173 * don't allow any other cpu, with stale tlb entries change the
1174 * page attribute in parallel, that also falls into the
1175 * just split large page entry.
1176 */
1177 flush_tlb_all();
87f7f8fe
IM
1178 goto repeat;
1179 }
beaff633 1180
87f7f8fe 1181 return err;
9f4c815c 1182}
1da177e4 1183
c31c7d48
TG
1184static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
1185
1186static int cpa_process_alias(struct cpa_data *cpa)
1da177e4 1187{
c31c7d48 1188 struct cpa_data alias_cpa;
992f4c1c 1189 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
e933a73f 1190 unsigned long vaddr;
992f4c1c 1191 int ret;
44af6c41 1192
8eb5779f 1193 if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1))
c31c7d48 1194 return 0;
626c2c9d 1195
f34b439f
TG
1196 /*
1197 * No need to redo, when the primary call touched the direct
1198 * mapping already:
1199 */
8523acfe
TH
1200 if (cpa->flags & CPA_PAGES_ARRAY) {
1201 struct page *page = cpa->pages[cpa->curpage];
1202 if (unlikely(PageHighMem(page)))
1203 return 0;
1204 vaddr = (unsigned long)page_address(page);
1205 } else if (cpa->flags & CPA_ARRAY)
d75586ad
SL
1206 vaddr = cpa->vaddr[cpa->curpage];
1207 else
1208 vaddr = *cpa->vaddr;
1209
1210 if (!(within(vaddr, PAGE_OFFSET,
a1e46212 1211 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
44af6c41 1212
f34b439f 1213 alias_cpa = *cpa;
992f4c1c 1214 alias_cpa.vaddr = &laddr;
9ae28475 1215 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
d75586ad 1216
f34b439f 1217 ret = __change_page_attr_set_clr(&alias_cpa, 0);
992f4c1c
TH
1218 if (ret)
1219 return ret;
f34b439f 1220 }
44af6c41 1221
44af6c41 1222#ifdef CONFIG_X86_64
488fd995 1223 /*
992f4c1c
TH
1224 * If the primary call didn't touch the high mapping already
1225 * and the physical address is inside the kernel map, we need
0879750f 1226 * to touch the high mapped kernel as well:
488fd995 1227 */
992f4c1c
TH
1228 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
1229 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
1230 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
1231 __START_KERNEL_map - phys_base;
1232 alias_cpa = *cpa;
1233 alias_cpa.vaddr = &temp_cpa_vaddr;
1234 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
c31c7d48 1235
992f4c1c
TH
1236 /*
1237 * The high mapping range is imprecise, so ignore the
1238 * return value.
1239 */
1240 __change_page_attr_set_clr(&alias_cpa, 0);
1241 }
488fd995 1242#endif
992f4c1c
TH
1243
1244 return 0;
1da177e4
LT
1245}
1246
c31c7d48 1247static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
ff31452b 1248{
65e074df 1249 int ret, numpages = cpa->numpages;
ff31452b 1250
65e074df
TG
1251 while (numpages) {
1252 /*
1253 * Store the remaining nr of pages for the large page
1254 * preservation check.
1255 */
9b5cf48b 1256 cpa->numpages = numpages;
d75586ad 1257 /* for array changes, we can't use large page */
9ae28475 1258 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
d75586ad 1259 cpa->numpages = 1;
c31c7d48 1260
ad5ca55f
SS
1261 if (!debug_pagealloc)
1262 spin_lock(&cpa_lock);
c31c7d48 1263 ret = __change_page_attr(cpa, checkalias);
ad5ca55f
SS
1264 if (!debug_pagealloc)
1265 spin_unlock(&cpa_lock);
ff31452b
TG
1266 if (ret)
1267 return ret;
ff31452b 1268
c31c7d48
TG
1269 if (checkalias) {
1270 ret = cpa_process_alias(cpa);
1271 if (ret)
1272 return ret;
1273 }
1274
65e074df
TG
1275 /*
1276 * Adjust the number of pages with the result of the
1277 * CPA operation. Either a large page has been
1278 * preserved or a single page update happened.
1279 */
9b5cf48b
RW
1280 BUG_ON(cpa->numpages > numpages);
1281 numpages -= cpa->numpages;
9ae28475 1282 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
d75586ad
SL
1283 cpa->curpage++;
1284 else
1285 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
1286
65e074df 1287 }
ff31452b
TG
1288 return 0;
1289}
1290
6bb8383b
AK
1291static inline int cache_attr(pgprot_t attr)
1292{
1293 return pgprot_val(attr) &
1294 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
1295}
1296
d75586ad 1297static int change_page_attr_set_clr(unsigned long *addr, int numpages,
c9caa02c 1298 pgprot_t mask_set, pgprot_t mask_clr,
9ae28475 1299 int force_split, int in_flag,
1300 struct page **pages)
ff31452b 1301{
72e458df 1302 struct cpa_data cpa;
cacf8906 1303 int ret, cache, checkalias;
fa526d0d 1304 unsigned long baddr = 0;
331e4065 1305
82f0712c
BP
1306 memset(&cpa, 0, sizeof(cpa));
1307
331e4065
TG
1308 /*
1309 * Check, if we are requested to change a not supported
1310 * feature:
1311 */
1312 mask_set = canon_pgprot(mask_set);
1313 mask_clr = canon_pgprot(mask_clr);
c9caa02c 1314 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
331e4065
TG
1315 return 0;
1316
69b1415e 1317 /* Ensure we are PAGE_SIZE aligned */
9ae28475 1318 if (in_flag & CPA_ARRAY) {
d75586ad
SL
1319 int i;
1320 for (i = 0; i < numpages; i++) {
1321 if (addr[i] & ~PAGE_MASK) {
1322 addr[i] &= PAGE_MASK;
1323 WARN_ON_ONCE(1);
1324 }
1325 }
9ae28475 1326 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
1327 /*
1328 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
1329 * No need to cehck in that case
1330 */
1331 if (*addr & ~PAGE_MASK) {
1332 *addr &= PAGE_MASK;
1333 /*
1334 * People should not be passing in unaligned addresses:
1335 */
1336 WARN_ON_ONCE(1);
1337 }
fa526d0d
JS
1338 /*
1339 * Save address for cache flush. *addr is modified in the call
1340 * to __change_page_attr_set_clr() below.
1341 */
1342 baddr = *addr;
69b1415e
TG
1343 }
1344
5843d9a4
NP
1345 /* Must avoid aliasing mappings in the highmem code */
1346 kmap_flush_unused();
1347
db64fe02
NP
1348 vm_unmap_aliases();
1349
72e458df 1350 cpa.vaddr = addr;
9ae28475 1351 cpa.pages = pages;
72e458df
TG
1352 cpa.numpages = numpages;
1353 cpa.mask_set = mask_set;
1354 cpa.mask_clr = mask_clr;
d75586ad
SL
1355 cpa.flags = 0;
1356 cpa.curpage = 0;
c9caa02c 1357 cpa.force_split = force_split;
72e458df 1358
9ae28475 1359 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
1360 cpa.flags |= in_flag;
d75586ad 1361
af96e443
TG
1362 /* No alias checking for _NX bit modifications */
1363 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
1364
1365 ret = __change_page_attr_set_clr(&cpa, checkalias);
ff31452b 1366
f4ae5da0
TG
1367 /*
1368 * Check whether we really changed something:
1369 */
d75586ad 1370 if (!(cpa.flags & CPA_FLUSHTLB))
1ac2f7d5 1371 goto out;
cacf8906 1372
6bb8383b
AK
1373 /*
1374 * No need to flush, when we did not set any of the caching
1375 * attributes:
1376 */
1377 cache = cache_attr(mask_set);
1378
57a6a46a
TG
1379 /*
1380 * On success we use clflush, when the CPU supports it to
f026cfa8
PA
1381 * avoid the wbindv. If the CPU does not support it and in the
1382 * error case we fall back to cpa_flush_all (which uses
1383 * wbindv):
57a6a46a 1384 */
f026cfa8 1385 if (!ret && cpu_has_clflush) {
9ae28475 1386 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
1387 cpa_flush_array(addr, numpages, cache,
1388 cpa.flags, pages);
1389 } else
fa526d0d 1390 cpa_flush_range(baddr, numpages, cache);
d75586ad 1391 } else
6bb8383b 1392 cpa_flush_all(cache);
cacf8906 1393
76ebd054 1394out:
ff31452b
TG
1395 return ret;
1396}
1397
d75586ad
SL
1398static inline int change_page_attr_set(unsigned long *addr, int numpages,
1399 pgprot_t mask, int array)
75cbade8 1400{
d75586ad 1401 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
9ae28475 1402 (array ? CPA_ARRAY : 0), NULL);
75cbade8
AV
1403}
1404
d75586ad
SL
1405static inline int change_page_attr_clear(unsigned long *addr, int numpages,
1406 pgprot_t mask, int array)
72932c7a 1407{
d75586ad 1408 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
9ae28475 1409 (array ? CPA_ARRAY : 0), NULL);
72932c7a
TG
1410}
1411
0f350755 1412static inline int cpa_set_pages_array(struct page **pages, int numpages,
1413 pgprot_t mask)
1414{
1415 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
1416 CPA_PAGES_ARRAY, pages);
1417}
1418
1419static inline int cpa_clear_pages_array(struct page **pages, int numpages,
1420 pgprot_t mask)
1421{
1422 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
1423 CPA_PAGES_ARRAY, pages);
1424}
1425
1219333d 1426int _set_memory_uc(unsigned long addr, int numpages)
72932c7a 1427{
de33c442
SS
1428 /*
1429 * for now UC MINUS. see comments in ioremap_nocache()
1430 */
d75586ad
SL
1431 return change_page_attr_set(&addr, numpages,
1432 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
75cbade8 1433}
1219333d 1434
1435int set_memory_uc(unsigned long addr, int numpages)
1436{
9fa3ab39 1437 int ret;
1438
de33c442
SS
1439 /*
1440 * for now UC MINUS. see comments in ioremap_nocache()
1441 */
9fa3ab39 1442 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1443 _PAGE_CACHE_UC_MINUS, NULL);
1444 if (ret)
1445 goto out_err;
1446
1447 ret = _set_memory_uc(addr, numpages);
1448 if (ret)
1449 goto out_free;
1450
1451 return 0;
1219333d 1452
9fa3ab39 1453out_free:
1454 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1455out_err:
1456 return ret;
1219333d 1457}
75cbade8
AV
1458EXPORT_SYMBOL(set_memory_uc);
1459
2d070eff 1460static int _set_memory_array(unsigned long *addr, int addrinarray,
4f646254 1461 unsigned long new_type)
d75586ad 1462{
9fa3ab39 1463 int i, j;
1464 int ret;
1465
d75586ad
SL
1466 /*
1467 * for now UC MINUS. see comments in ioremap_nocache()
1468 */
1469 for (i = 0; i < addrinarray; i++) {
9fa3ab39 1470 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
4f646254 1471 new_type, NULL);
9fa3ab39 1472 if (ret)
1473 goto out_free;
d75586ad
SL
1474 }
1475
9fa3ab39 1476 ret = change_page_attr_set(addr, addrinarray,
d75586ad 1477 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
4f646254
PN
1478
1479 if (!ret && new_type == _PAGE_CACHE_WC)
1480 ret = change_page_attr_set_clr(addr, addrinarray,
1481 __pgprot(_PAGE_CACHE_WC),
1482 __pgprot(_PAGE_CACHE_MASK),
1483 0, CPA_ARRAY, NULL);
9fa3ab39 1484 if (ret)
1485 goto out_free;
1486
1487 return 0;
1488
1489out_free:
1490 for (j = 0; j < i; j++)
1491 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1492
1493 return ret;
d75586ad 1494}
4f646254
PN
1495
1496int set_memory_array_uc(unsigned long *addr, int addrinarray)
1497{
1498 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
1499}
d75586ad
SL
1500EXPORT_SYMBOL(set_memory_array_uc);
1501
4f646254
PN
1502int set_memory_array_wc(unsigned long *addr, int addrinarray)
1503{
1504 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
1505}
1506EXPORT_SYMBOL(set_memory_array_wc);
1507
ef354af4 1508int _set_memory_wc(unsigned long addr, int numpages)
1509{
3869c4aa 1510 int ret;
bdc6340f
PV
1511 unsigned long addr_copy = addr;
1512
3869c4aa 1513 ret = change_page_attr_set(&addr, numpages,
1514 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
3869c4aa 1515 if (!ret) {
bdc6340f
PV
1516 ret = change_page_attr_set_clr(&addr_copy, numpages,
1517 __pgprot(_PAGE_CACHE_WC),
1518 __pgprot(_PAGE_CACHE_MASK),
1519 0, 0, NULL);
3869c4aa 1520 }
1521 return ret;
ef354af4 1522}
1523
1524int set_memory_wc(unsigned long addr, int numpages)
1525{
9fa3ab39 1526 int ret;
1527
499f8f84 1528 if (!pat_enabled)
ef354af4 1529 return set_memory_uc(addr, numpages);
1530
9fa3ab39 1531 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1532 _PAGE_CACHE_WC, NULL);
1533 if (ret)
1534 goto out_err;
ef354af4 1535
9fa3ab39 1536 ret = _set_memory_wc(addr, numpages);
1537 if (ret)
1538 goto out_free;
1539
1540 return 0;
1541
1542out_free:
1543 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1544out_err:
1545 return ret;
ef354af4 1546}
1547EXPORT_SYMBOL(set_memory_wc);
1548
1219333d 1549int _set_memory_wb(unsigned long addr, int numpages)
75cbade8 1550{
d75586ad
SL
1551 return change_page_attr_clear(&addr, numpages,
1552 __pgprot(_PAGE_CACHE_MASK), 0);
75cbade8 1553}
1219333d 1554
1555int set_memory_wb(unsigned long addr, int numpages)
1556{
9fa3ab39 1557 int ret;
1558
1559 ret = _set_memory_wb(addr, numpages);
1560 if (ret)
1561 return ret;
1562
c15238df 1563 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
9fa3ab39 1564 return 0;
1219333d 1565}
75cbade8
AV
1566EXPORT_SYMBOL(set_memory_wb);
1567
d75586ad
SL
1568int set_memory_array_wb(unsigned long *addr, int addrinarray)
1569{
1570 int i;
a5593e0b 1571 int ret;
1572
1573 ret = change_page_attr_clear(addr, addrinarray,
1574 __pgprot(_PAGE_CACHE_MASK), 1);
9fa3ab39 1575 if (ret)
1576 return ret;
d75586ad 1577
9fa3ab39 1578 for (i = 0; i < addrinarray; i++)
1579 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
c5e147cf 1580
9fa3ab39 1581 return 0;
d75586ad
SL
1582}
1583EXPORT_SYMBOL(set_memory_array_wb);
1584
75cbade8
AV
1585int set_memory_x(unsigned long addr, int numpages)
1586{
583140af
PA
1587 if (!(__supported_pte_mask & _PAGE_NX))
1588 return 0;
1589
d75586ad 1590 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
75cbade8
AV
1591}
1592EXPORT_SYMBOL(set_memory_x);
1593
1594int set_memory_nx(unsigned long addr, int numpages)
1595{
583140af
PA
1596 if (!(__supported_pte_mask & _PAGE_NX))
1597 return 0;
1598
d75586ad 1599 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
75cbade8
AV
1600}
1601EXPORT_SYMBOL(set_memory_nx);
1602
1603int set_memory_ro(unsigned long addr, int numpages)
1604{
d75586ad 1605 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
75cbade8 1606}
a03352d2 1607EXPORT_SYMBOL_GPL(set_memory_ro);
75cbade8
AV
1608
1609int set_memory_rw(unsigned long addr, int numpages)
1610{
d75586ad 1611 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
75cbade8 1612}
a03352d2 1613EXPORT_SYMBOL_GPL(set_memory_rw);
f62d0f00
IM
1614
1615int set_memory_np(unsigned long addr, int numpages)
1616{
d75586ad 1617 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
f62d0f00 1618}
75cbade8 1619
c9caa02c
AK
1620int set_memory_4k(unsigned long addr, int numpages)
1621{
d75586ad 1622 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
9ae28475 1623 __pgprot(0), 1, 0, NULL);
c9caa02c
AK
1624}
1625
75cbade8
AV
1626int set_pages_uc(struct page *page, int numpages)
1627{
1628 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1629
d7c8f21a 1630 return set_memory_uc(addr, numpages);
75cbade8
AV
1631}
1632EXPORT_SYMBOL(set_pages_uc);
1633
4f646254
PN
1634static int _set_pages_array(struct page **pages, int addrinarray,
1635 unsigned long new_type)
0f350755 1636{
1637 unsigned long start;
1638 unsigned long end;
1639 int i;
1640 int free_idx;
4f646254 1641 int ret;
0f350755 1642
1643 for (i = 0; i < addrinarray; i++) {
8523acfe
TH
1644 if (PageHighMem(pages[i]))
1645 continue;
1646 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
0f350755 1647 end = start + PAGE_SIZE;
4f646254 1648 if (reserve_memtype(start, end, new_type, NULL))
0f350755 1649 goto err_out;
1650 }
1651
4f646254
PN
1652 ret = cpa_set_pages_array(pages, addrinarray,
1653 __pgprot(_PAGE_CACHE_UC_MINUS));
1654 if (!ret && new_type == _PAGE_CACHE_WC)
1655 ret = change_page_attr_set_clr(NULL, addrinarray,
1656 __pgprot(_PAGE_CACHE_WC),
1657 __pgprot(_PAGE_CACHE_MASK),
1658 0, CPA_PAGES_ARRAY, pages);
1659 if (ret)
1660 goto err_out;
1661 return 0; /* Success */
0f350755 1662err_out:
1663 free_idx = i;
1664 for (i = 0; i < free_idx; i++) {
8523acfe
TH
1665 if (PageHighMem(pages[i]))
1666 continue;
1667 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
0f350755 1668 end = start + PAGE_SIZE;
1669 free_memtype(start, end);
1670 }
1671 return -EINVAL;
1672}
4f646254
PN
1673
1674int set_pages_array_uc(struct page **pages, int addrinarray)
1675{
1676 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
1677}
0f350755 1678EXPORT_SYMBOL(set_pages_array_uc);
1679
4f646254
PN
1680int set_pages_array_wc(struct page **pages, int addrinarray)
1681{
1682 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
1683}
1684EXPORT_SYMBOL(set_pages_array_wc);
1685
75cbade8
AV
1686int set_pages_wb(struct page *page, int numpages)
1687{
1688 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1689
d7c8f21a 1690 return set_memory_wb(addr, numpages);
75cbade8
AV
1691}
1692EXPORT_SYMBOL(set_pages_wb);
1693
0f350755 1694int set_pages_array_wb(struct page **pages, int addrinarray)
1695{
1696 int retval;
1697 unsigned long start;
1698 unsigned long end;
1699 int i;
1700
1701 retval = cpa_clear_pages_array(pages, addrinarray,
1702 __pgprot(_PAGE_CACHE_MASK));
9fa3ab39 1703 if (retval)
1704 return retval;
0f350755 1705
1706 for (i = 0; i < addrinarray; i++) {
8523acfe
TH
1707 if (PageHighMem(pages[i]))
1708 continue;
1709 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
0f350755 1710 end = start + PAGE_SIZE;
1711 free_memtype(start, end);
1712 }
1713
9fa3ab39 1714 return 0;
0f350755 1715}
1716EXPORT_SYMBOL(set_pages_array_wb);
1717
75cbade8
AV
1718int set_pages_x(struct page *page, int numpages)
1719{
1720 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1721
d7c8f21a 1722 return set_memory_x(addr, numpages);
75cbade8
AV
1723}
1724EXPORT_SYMBOL(set_pages_x);
1725
1726int set_pages_nx(struct page *page, int numpages)
1727{
1728 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1729
d7c8f21a 1730 return set_memory_nx(addr, numpages);
75cbade8
AV
1731}
1732EXPORT_SYMBOL(set_pages_nx);
1733
1734int set_pages_ro(struct page *page, int numpages)
1735{
1736 unsigned long addr = (unsigned long)page_address(page);
75cbade8 1737
d7c8f21a 1738 return set_memory_ro(addr, numpages);
75cbade8 1739}
75cbade8
AV
1740
1741int set_pages_rw(struct page *page, int numpages)
1742{
1743 unsigned long addr = (unsigned long)page_address(page);
e81d5dc4 1744
d7c8f21a 1745 return set_memory_rw(addr, numpages);
78c94aba
IM
1746}
1747
1da177e4 1748#ifdef CONFIG_DEBUG_PAGEALLOC
f62d0f00
IM
1749
1750static int __set_pages_p(struct page *page, int numpages)
1751{
d75586ad
SL
1752 unsigned long tempaddr = (unsigned long) page_address(page);
1753 struct cpa_data cpa = { .vaddr = &tempaddr,
82f0712c 1754 .pgd = NULL,
72e458df
TG
1755 .numpages = numpages,
1756 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
d75586ad
SL
1757 .mask_clr = __pgprot(0),
1758 .flags = 0};
72932c7a 1759
55121b43
SS
1760 /*
1761 * No alias checking needed for setting present flag. otherwise,
1762 * we may need to break large pages for 64-bit kernel text
1763 * mappings (this adds to complexity if we want to do this from
1764 * atomic context especially). Let's keep it simple!
1765 */
1766 return __change_page_attr_set_clr(&cpa, 0);
f62d0f00
IM
1767}
1768
1769static int __set_pages_np(struct page *page, int numpages)
1770{
d75586ad
SL
1771 unsigned long tempaddr = (unsigned long) page_address(page);
1772 struct cpa_data cpa = { .vaddr = &tempaddr,
82f0712c 1773 .pgd = NULL,
72e458df
TG
1774 .numpages = numpages,
1775 .mask_set = __pgprot(0),
d75586ad
SL
1776 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1777 .flags = 0};
72932c7a 1778
55121b43
SS
1779 /*
1780 * No alias checking needed for setting not present flag. otherwise,
1781 * we may need to break large pages for 64-bit kernel text
1782 * mappings (this adds to complexity if we want to do this from
1783 * atomic context especially). Let's keep it simple!
1784 */
1785 return __change_page_attr_set_clr(&cpa, 0);
f62d0f00
IM
1786}
1787
1da177e4
LT
1788void kernel_map_pages(struct page *page, int numpages, int enable)
1789{
1790 if (PageHighMem(page))
1791 return;
9f4c815c 1792 if (!enable) {
f9b8404c
IM
1793 debug_check_no_locks_freed(page_address(page),
1794 numpages * PAGE_SIZE);
9f4c815c 1795 }
de5097c2 1796
9f4c815c 1797 /*
f8d8406b 1798 * The return value is ignored as the calls cannot fail.
55121b43
SS
1799 * Large pages for identity mappings are not used at boot time
1800 * and hence no memory allocations during large page split.
1da177e4 1801 */
f62d0f00
IM
1802 if (enable)
1803 __set_pages_p(page, numpages);
1804 else
1805 __set_pages_np(page, numpages);
9f4c815c
IM
1806
1807 /*
e4b71dcf
IM
1808 * We should perform an IPI and flush all tlbs,
1809 * but that can deadlock->flush only current cpu:
1da177e4
LT
1810 */
1811 __flush_tlb_all();
26564600
BO
1812
1813 arch_flush_lazy_mmu_mode();
ee7ae7a1
TG
1814}
1815
8a235efa
RW
1816#ifdef CONFIG_HIBERNATION
1817
1818bool kernel_page_present(struct page *page)
1819{
1820 unsigned int level;
1821 pte_t *pte;
1822
1823 if (PageHighMem(page))
1824 return false;
1825
1826 pte = lookup_address((unsigned long)page_address(page), &level);
1827 return (pte_val(*pte) & _PAGE_PRESENT);
1828}
1829
1830#endif /* CONFIG_HIBERNATION */
1831
1832#endif /* CONFIG_DEBUG_PAGEALLOC */
d1028a15 1833
82f0712c
BP
1834int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
1835 unsigned numpages, unsigned long page_flags)
1836{
1837 int retval = -EINVAL;
1838
1839 struct cpa_data cpa = {
1840 .vaddr = &address,
1841 .pfn = pfn,
1842 .pgd = pgd,
1843 .numpages = numpages,
1844 .mask_set = __pgprot(0),
1845 .mask_clr = __pgprot(0),
1846 .flags = 0,
1847 };
1848
1849 if (!(__supported_pte_mask & _PAGE_NX))
1850 goto out;
1851
1852 if (!(page_flags & _PAGE_NX))
1853 cpa.mask_clr = __pgprot(_PAGE_NX);
1854
1855 cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags);
1856
1857 retval = __change_page_attr_set_clr(&cpa, 0);
1858 __flush_tlb_all();
1859
1860out:
1861 return retval;
1862}
1863
d1028a15
AV
1864/*
1865 * The testcases use internal knowledge of the implementation that shouldn't
1866 * be exposed to the rest of the kernel. Include these directly here.
1867 */
1868#ifdef CONFIG_CPA_DEBUG
1869#include "pageattr-test.c"
1870#endif