x86: compile pat debugfs interface only if CONFIG_X86_PAT is set
[linux-2.6-block.git] / arch / x86 / mm / pageattr.c
CommitLineData
9f4c815c
IM
1/*
2 * Copyright 2002 Andi Kleen, SuSE Labs.
1da177e4 3 * Thanks to Ben LaHaise for precious feedback.
9f4c815c 4 */
1da177e4 5#include <linux/highmem.h>
8192206d 6#include <linux/bootmem.h>
1da177e4 7#include <linux/module.h>
9f4c815c 8#include <linux/sched.h>
1da177e4 9#include <linux/slab.h>
9f4c815c 10#include <linux/mm.h>
76ebd054 11#include <linux/interrupt.h>
ee7ae7a1
TG
12#include <linux/seq_file.h>
13#include <linux/debugfs.h>
9f4c815c 14
950f9d95 15#include <asm/e820.h>
1da177e4
LT
16#include <asm/processor.h>
17#include <asm/tlbflush.h>
f8af095d 18#include <asm/sections.h>
9f4c815c
IM
19#include <asm/uaccess.h>
20#include <asm/pgalloc.h>
c31c7d48 21#include <asm/proto.h>
1219333d 22#include <asm/pat.h>
1da177e4 23
9df84993
IM
24/*
25 * The current flushing context - we pass it instead of 5 arguments:
26 */
72e458df
TG
27struct cpa_data {
28 unsigned long vaddr;
72e458df
TG
29 pgprot_t mask_set;
30 pgprot_t mask_clr;
65e074df 31 int numpages;
f4ae5da0 32 int flushtlb;
c31c7d48 33 unsigned long pfn;
c9caa02c 34 unsigned force_split : 1;
72e458df
TG
35};
36
65280e61 37#ifdef CONFIG_PROC_FS
ce0c0e50
AK
38static unsigned long direct_pages_count[PG_LEVEL_NUM];
39
65280e61 40void update_page_count(int level, unsigned long pages)
ce0c0e50 41{
ce0c0e50 42 unsigned long flags;
65280e61 43
ce0c0e50
AK
44 /* Protect against CPA */
45 spin_lock_irqsave(&pgd_lock, flags);
46 direct_pages_count[level] += pages;
47 spin_unlock_irqrestore(&pgd_lock, flags);
65280e61
TG
48}
49
50static void split_page_count(int level)
51{
52 direct_pages_count[level]--;
53 direct_pages_count[level - 1] += PTRS_PER_PTE;
54}
55
56int arch_report_meminfo(char *page)
57{
58 int n = sprintf(page, "DirectMap4k: %8lu\n"
59 "DirectMap2M: %8lu\n",
60 direct_pages_count[PG_LEVEL_4K],
61 direct_pages_count[PG_LEVEL_2M]);
62#ifdef CONFIG_X86_64
63 n += sprintf(page + n, "DirectMap1G: %8lu\n",
64 direct_pages_count[PG_LEVEL_1G]);
ce0c0e50 65#endif
65280e61 66 return n;
ce0c0e50 67}
65280e61
TG
68#else
69static inline void split_page_count(int level) { }
70#endif
ce0c0e50 71
c31c7d48
TG
72#ifdef CONFIG_X86_64
73
74static inline unsigned long highmap_start_pfn(void)
75{
76 return __pa(_text) >> PAGE_SHIFT;
77}
78
79static inline unsigned long highmap_end_pfn(void)
80{
81 return __pa(round_up((unsigned long)_end, PMD_SIZE)) >> PAGE_SHIFT;
82}
83
84#endif
85
92cb54a3
IM
86#ifdef CONFIG_DEBUG_PAGEALLOC
87# define debug_pagealloc 1
88#else
89# define debug_pagealloc 0
90#endif
91
ed724be6
AV
92static inline int
93within(unsigned long addr, unsigned long start, unsigned long end)
687c4825 94{
ed724be6
AV
95 return addr >= start && addr < end;
96}
97
d7c8f21a
TG
98/*
99 * Flushing functions
100 */
cd8ddf1a 101
cd8ddf1a
TG
102/**
103 * clflush_cache_range - flush a cache range with clflush
104 * @addr: virtual start address
105 * @size: number of bytes to flush
106 *
107 * clflush is an unordered instruction which needs fencing with mfence
108 * to avoid ordering issues.
109 */
4c61afcd 110void clflush_cache_range(void *vaddr, unsigned int size)
d7c8f21a 111{
4c61afcd 112 void *vend = vaddr + size - 1;
d7c8f21a 113
cd8ddf1a 114 mb();
4c61afcd
IM
115
116 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
117 clflush(vaddr);
118 /*
119 * Flush any possible final partial cacheline:
120 */
121 clflush(vend);
122
cd8ddf1a 123 mb();
d7c8f21a
TG
124}
125
af1e6844 126static void __cpa_flush_all(void *arg)
d7c8f21a 127{
6bb8383b
AK
128 unsigned long cache = (unsigned long)arg;
129
d7c8f21a
TG
130 /*
131 * Flush all to work around Errata in early athlons regarding
132 * large page flushing.
133 */
134 __flush_tlb_all();
135
6bb8383b 136 if (cache && boot_cpu_data.x86_model >= 4)
d7c8f21a
TG
137 wbinvd();
138}
139
6bb8383b 140static void cpa_flush_all(unsigned long cache)
d7c8f21a
TG
141{
142 BUG_ON(irqs_disabled());
143
15c8b6c1 144 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
d7c8f21a
TG
145}
146
57a6a46a
TG
147static void __cpa_flush_range(void *arg)
148{
57a6a46a
TG
149 /*
150 * We could optimize that further and do individual per page
151 * tlb invalidates for a low number of pages. Caveat: we must
152 * flush the high aliases on 64bit as well.
153 */
154 __flush_tlb_all();
57a6a46a
TG
155}
156
6bb8383b 157static void cpa_flush_range(unsigned long start, int numpages, int cache)
57a6a46a 158{
4c61afcd
IM
159 unsigned int i, level;
160 unsigned long addr;
161
57a6a46a 162 BUG_ON(irqs_disabled());
4c61afcd 163 WARN_ON(PAGE_ALIGN(start) != start);
57a6a46a 164
15c8b6c1 165 on_each_cpu(__cpa_flush_range, NULL, 1);
57a6a46a 166
6bb8383b
AK
167 if (!cache)
168 return;
169
3b233e52
TG
170 /*
171 * We only need to flush on one CPU,
172 * clflush is a MESI-coherent instruction that
173 * will cause all other CPUs to flush the same
174 * cachelines:
175 */
4c61afcd
IM
176 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
177 pte_t *pte = lookup_address(addr, &level);
178
179 /*
180 * Only flush present addresses:
181 */
7bfb72e8 182 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
4c61afcd
IM
183 clflush_cache_range((void *) addr, PAGE_SIZE);
184 }
57a6a46a
TG
185}
186
ed724be6
AV
187/*
188 * Certain areas of memory on x86 require very specific protection flags,
189 * for example the BIOS area or kernel text. Callers don't always get this
190 * right (again, ioremap() on BIOS memory is not uncommon) so this function
191 * checks and fixes these known static required protection bits.
192 */
c31c7d48
TG
193static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
194 unsigned long pfn)
ed724be6
AV
195{
196 pgprot_t forbidden = __pgprot(0);
197
687c4825 198 /*
ed724be6
AV
199 * The BIOS area between 640k and 1Mb needs to be executable for
200 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
687c4825 201 */
c31c7d48 202 if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
ed724be6
AV
203 pgprot_val(forbidden) |= _PAGE_NX;
204
205 /*
206 * The kernel text needs to be executable for obvious reasons
c31c7d48
TG
207 * Does not cover __inittext since that is gone later on. On
208 * 64bit we do not enforce !NX on the low mapping
ed724be6
AV
209 */
210 if (within(address, (unsigned long)_text, (unsigned long)_etext))
211 pgprot_val(forbidden) |= _PAGE_NX;
cc0f21bb 212
cc0f21bb 213 /*
c31c7d48
TG
214 * The .rodata section needs to be read-only. Using the pfn
215 * catches all aliases.
cc0f21bb 216 */
c31c7d48
TG
217 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
218 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
cc0f21bb 219 pgprot_val(forbidden) |= _PAGE_RW;
ed724be6
AV
220
221 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
687c4825
IM
222
223 return prot;
224}
225
9a14aefc
TG
226/*
227 * Lookup the page table entry for a virtual address. Return a pointer
228 * to the entry and the level of the mapping.
229 *
230 * Note: We return pud and pmd either when the entry is marked large
231 * or when the present bit is not set. Otherwise we would return a
232 * pointer to a nonexisting mapping.
233 */
da7bfc50 234pte_t *lookup_address(unsigned long address, unsigned int *level)
9f4c815c 235{
1da177e4
LT
236 pgd_t *pgd = pgd_offset_k(address);
237 pud_t *pud;
238 pmd_t *pmd;
9f4c815c 239
30551bb3
TG
240 *level = PG_LEVEL_NONE;
241
1da177e4
LT
242 if (pgd_none(*pgd))
243 return NULL;
9df84993 244
1da177e4
LT
245 pud = pud_offset(pgd, address);
246 if (pud_none(*pud))
247 return NULL;
c2f71ee2
AK
248
249 *level = PG_LEVEL_1G;
250 if (pud_large(*pud) || !pud_present(*pud))
251 return (pte_t *)pud;
252
1da177e4
LT
253 pmd = pmd_offset(pud, address);
254 if (pmd_none(*pmd))
255 return NULL;
30551bb3
TG
256
257 *level = PG_LEVEL_2M;
9a14aefc 258 if (pmd_large(*pmd) || !pmd_present(*pmd))
1da177e4 259 return (pte_t *)pmd;
1da177e4 260
30551bb3 261 *level = PG_LEVEL_4K;
9df84993 262
9f4c815c
IM
263 return pte_offset_kernel(pmd, address);
264}
75bb8835 265EXPORT_SYMBOL_GPL(lookup_address);
9f4c815c 266
9df84993
IM
267/*
268 * Set the new pmd in all the pgds we know about:
269 */
9a3dc780 270static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
9f4c815c 271{
9f4c815c
IM
272 /* change init_mm */
273 set_pte_atomic(kpte, pte);
44af6c41 274#ifdef CONFIG_X86_32
e4b71dcf 275 if (!SHARED_KERNEL_PMD) {
44af6c41
IM
276 struct page *page;
277
e3ed910d 278 list_for_each_entry(page, &pgd_list, lru) {
44af6c41
IM
279 pgd_t *pgd;
280 pud_t *pud;
281 pmd_t *pmd;
282
283 pgd = (pgd_t *)page_address(page) + pgd_index(address);
284 pud = pud_offset(pgd, address);
285 pmd = pmd_offset(pud, address);
286 set_pte_atomic((pte_t *)pmd, pte);
287 }
1da177e4 288 }
44af6c41 289#endif
1da177e4
LT
290}
291
9df84993
IM
292static int
293try_preserve_large_page(pte_t *kpte, unsigned long address,
294 struct cpa_data *cpa)
65e074df 295{
c31c7d48 296 unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
65e074df
TG
297 pte_t new_pte, old_pte, *tmp;
298 pgprot_t old_prot, new_prot;
fac84939 299 int i, do_split = 1;
da7bfc50 300 unsigned int level;
65e074df 301
c9caa02c
AK
302 if (cpa->force_split)
303 return 1;
304
65e074df
TG
305 spin_lock_irqsave(&pgd_lock, flags);
306 /*
307 * Check for races, another CPU might have split this page
308 * up already:
309 */
310 tmp = lookup_address(address, &level);
311 if (tmp != kpte)
312 goto out_unlock;
313
314 switch (level) {
315 case PG_LEVEL_2M:
31422c51
AK
316 psize = PMD_PAGE_SIZE;
317 pmask = PMD_PAGE_MASK;
65e074df 318 break;
f07333fd 319#ifdef CONFIG_X86_64
65e074df 320 case PG_LEVEL_1G:
5d3c8b21
AK
321 psize = PUD_PAGE_SIZE;
322 pmask = PUD_PAGE_MASK;
f07333fd
AK
323 break;
324#endif
65e074df 325 default:
beaff633 326 do_split = -EINVAL;
65e074df
TG
327 goto out_unlock;
328 }
329
330 /*
331 * Calculate the number of pages, which fit into this large
332 * page starting at address:
333 */
334 nextpage_addr = (address + psize) & pmask;
335 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
9b5cf48b
RW
336 if (numpages < cpa->numpages)
337 cpa->numpages = numpages;
65e074df
TG
338
339 /*
340 * We are safe now. Check whether the new pgprot is the same:
341 */
342 old_pte = *kpte;
343 old_prot = new_prot = pte_pgprot(old_pte);
344
345 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
346 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
c31c7d48
TG
347
348 /*
349 * old_pte points to the large page base address. So we need
350 * to add the offset of the virtual address:
351 */
352 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
353 cpa->pfn = pfn;
354
355 new_prot = static_protections(new_prot, address, pfn);
65e074df 356
fac84939
TG
357 /*
358 * We need to check the full range, whether
359 * static_protection() requires a different pgprot for one of
360 * the pages in the range we try to preserve:
361 */
362 addr = address + PAGE_SIZE;
c31c7d48 363 pfn++;
9b5cf48b 364 for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
c31c7d48 365 pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
fac84939
TG
366
367 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
368 goto out_unlock;
369 }
370
65e074df
TG
371 /*
372 * If there are no changes, return. maxpages has been updated
373 * above:
374 */
375 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
beaff633 376 do_split = 0;
65e074df
TG
377 goto out_unlock;
378 }
379
380 /*
381 * We need to change the attributes. Check, whether we can
382 * change the large page in one go. We request a split, when
383 * the address is not aligned and the number of pages is
384 * smaller than the number of pages in the large page. Note
385 * that we limited the number of possible pages already to
386 * the number of pages in the large page.
387 */
9b5cf48b 388 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
65e074df
TG
389 /*
390 * The address is aligned and the number of pages
391 * covers the full page.
392 */
393 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
394 __set_pmd_pte(kpte, address, new_pte);
395 cpa->flushtlb = 1;
beaff633 396 do_split = 0;
65e074df
TG
397 }
398
399out_unlock:
400 spin_unlock_irqrestore(&pgd_lock, flags);
9df84993 401
beaff633 402 return do_split;
65e074df
TG
403}
404
76ebd054
TG
405static LIST_HEAD(page_pool);
406static unsigned long pool_size, pool_pages, pool_low;
92cb54a3 407static unsigned long pool_used, pool_failed;
76ebd054 408
92cb54a3 409static void cpa_fill_pool(struct page **ret)
76ebd054 410{
76ebd054 411 gfp_t gfp = GFP_KERNEL;
92cb54a3
IM
412 unsigned long flags;
413 struct page *p;
76ebd054 414
76ebd054 415 /*
92cb54a3
IM
416 * Avoid recursion (on debug-pagealloc) and also signal
417 * our priority to get to these pagetables:
76ebd054 418 */
92cb54a3 419 if (current->flags & PF_MEMALLOC)
76ebd054 420 return;
92cb54a3 421 current->flags |= PF_MEMALLOC;
76ebd054 422
76ebd054 423 /*
92cb54a3 424 * Allocate atomically from atomic contexts:
76ebd054 425 */
92cb54a3
IM
426 if (in_atomic() || irqs_disabled() || debug_pagealloc)
427 gfp = GFP_ATOMIC | __GFP_NORETRY | __GFP_NOWARN;
76ebd054 428
92cb54a3 429 while (pool_pages < pool_size || (ret && !*ret)) {
76ebd054
TG
430 p = alloc_pages(gfp, 0);
431 if (!p) {
432 pool_failed++;
433 break;
434 }
92cb54a3
IM
435 /*
436 * If the call site needs a page right now, provide it:
437 */
438 if (ret && !*ret) {
439 *ret = p;
440 continue;
441 }
442 spin_lock_irqsave(&pgd_lock, flags);
76ebd054
TG
443 list_add(&p->lru, &page_pool);
444 pool_pages++;
92cb54a3 445 spin_unlock_irqrestore(&pgd_lock, flags);
76ebd054 446 }
92cb54a3
IM
447
448 current->flags &= ~PF_MEMALLOC;
76ebd054
TG
449}
450
451#define SHIFT_MB (20 - PAGE_SHIFT)
452#define ROUND_MB_GB ((1 << 10) - 1)
453#define SHIFT_MB_GB 10
454#define POOL_PAGES_PER_GB 16
455
456void __init cpa_init(void)
457{
458 struct sysinfo si;
459 unsigned long gb;
460
461 si_meminfo(&si);
462 /*
463 * Calculate the number of pool pages:
464 *
465 * Convert totalram (nr of pages) to MiB and round to the next
466 * GiB. Shift MiB to Gib and multiply the result by
467 * POOL_PAGES_PER_GB:
468 */
92cb54a3
IM
469 if (debug_pagealloc) {
470 gb = ((si.totalram >> SHIFT_MB) + ROUND_MB_GB) >> SHIFT_MB_GB;
471 pool_size = POOL_PAGES_PER_GB * gb;
472 } else {
473 pool_size = 1;
474 }
76ebd054
TG
475 pool_low = pool_size;
476
92cb54a3 477 cpa_fill_pool(NULL);
76ebd054
TG
478 printk(KERN_DEBUG
479 "CPA: page pool initialized %lu of %lu pages preallocated\n",
480 pool_pages, pool_size);
481}
482
7afe15b9 483static int split_large_page(pte_t *kpte, unsigned long address)
bb5c2dbd 484{
7b610eec 485 unsigned long flags, pfn, pfninc = 1;
9df84993 486 unsigned int i, level;
bb5c2dbd 487 pte_t *pbase, *tmp;
9df84993 488 pgprot_t ref_prot;
bb5c2dbd
IM
489 struct page *base;
490
eb5b5f02
TG
491 /*
492 * Get a page from the pool. The pool list is protected by the
493 * pgd_lock, which we have to take anyway for the split
494 * operation:
495 */
496 spin_lock_irqsave(&pgd_lock, flags);
497 if (list_empty(&page_pool)) {
498 spin_unlock_irqrestore(&pgd_lock, flags);
92cb54a3
IM
499 base = NULL;
500 cpa_fill_pool(&base);
501 if (!base)
502 return -ENOMEM;
503 spin_lock_irqsave(&pgd_lock, flags);
504 } else {
505 base = list_first_entry(&page_pool, struct page, lru);
506 list_del(&base->lru);
507 pool_pages--;
508
509 if (pool_pages < pool_low)
510 pool_low = pool_pages;
eb5b5f02
TG
511 }
512
bb5c2dbd
IM
513 /*
514 * Check for races, another CPU might have split this page
515 * up for us already:
516 */
517 tmp = lookup_address(address, &level);
6ce9fc17 518 if (tmp != kpte)
bb5c2dbd
IM
519 goto out_unlock;
520
bb5c2dbd 521 pbase = (pte_t *)page_address(base);
6944a9c8 522 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
07cf89c0 523 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
bb5c2dbd 524
f07333fd
AK
525#ifdef CONFIG_X86_64
526 if (level == PG_LEVEL_1G) {
527 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
528 pgprot_val(ref_prot) |= _PAGE_PSE;
f07333fd
AK
529 }
530#endif
531
63c1dcf4
TG
532 /*
533 * Get the target pfn from the original entry:
534 */
535 pfn = pte_pfn(*kpte);
f07333fd 536 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
63c1dcf4 537 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
bb5c2dbd 538
ce0c0e50 539 if (address >= (unsigned long)__va(0) &&
f361a450
YL
540 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
541 split_page_count(level);
542
543#ifdef CONFIG_X86_64
544 if (address >= (unsigned long)__va(1UL<<32) &&
65280e61
TG
545 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
546 split_page_count(level);
f361a450 547#endif
ce0c0e50 548
bb5c2dbd 549 /*
07cf89c0 550 * Install the new, split up pagetable. Important details here:
4c881ca1
HY
551 *
552 * On Intel the NX bit of all levels must be cleared to make a
553 * page executable. See section 4.13.2 of Intel 64 and IA-32
554 * Architectures Software Developer's Manual).
07cf89c0
TG
555 *
556 * Mark the entry present. The current mapping might be
557 * set to not present, which we preserved above.
bb5c2dbd 558 */
4c881ca1 559 ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
07cf89c0 560 pgprot_val(ref_prot) |= _PAGE_PRESENT;
9a3dc780 561 __set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
bb5c2dbd
IM
562 base = NULL;
563
564out_unlock:
eb5b5f02
TG
565 /*
566 * If we dropped out via the lookup_address check under
567 * pgd_lock then stick the page back into the pool:
568 */
569 if (base) {
570 list_add(&base->lru, &page_pool);
571 pool_pages++;
572 } else
573 pool_used++;
9a3dc780 574 spin_unlock_irqrestore(&pgd_lock, flags);
bb5c2dbd 575
bb5c2dbd
IM
576 return 0;
577}
578
c31c7d48 579static int __change_page_attr(struct cpa_data *cpa, int primary)
9f4c815c 580{
c31c7d48 581 unsigned long address = cpa->vaddr;
da7bfc50
HH
582 int do_split, err;
583 unsigned int level;
c31c7d48 584 pte_t *kpte, old_pte;
1da177e4 585
97f99fed 586repeat:
f0646e43 587 kpte = lookup_address(address, &level);
1da177e4 588 if (!kpte)
d1a4be63 589 return 0;
c31c7d48
TG
590
591 old_pte = *kpte;
592 if (!pte_val(old_pte)) {
593 if (!primary)
594 return 0;
595 printk(KERN_WARNING "CPA: called for zero pte. "
596 "vaddr = %lx cpa->vaddr = %lx\n", address,
597 cpa->vaddr);
598 WARN_ON(1);
1da177e4 599 return -EINVAL;
c31c7d48 600 }
9f4c815c 601
30551bb3 602 if (level == PG_LEVEL_4K) {
c31c7d48 603 pte_t new_pte;
626c2c9d 604 pgprot_t new_prot = pte_pgprot(old_pte);
c31c7d48 605 unsigned long pfn = pte_pfn(old_pte);
86f03989 606
72e458df
TG
607 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
608 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
86f03989 609
c31c7d48 610 new_prot = static_protections(new_prot, address, pfn);
86f03989 611
626c2c9d
AV
612 /*
613 * We need to keep the pfn from the existing PTE,
614 * after all we're only going to change it's attributes
615 * not the memory it points to
616 */
c31c7d48
TG
617 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
618 cpa->pfn = pfn;
f4ae5da0
TG
619 /*
620 * Do we really change anything ?
621 */
622 if (pte_val(old_pte) != pte_val(new_pte)) {
623 set_pte_atomic(kpte, new_pte);
624 cpa->flushtlb = 1;
625 }
9b5cf48b 626 cpa->numpages = 1;
65e074df 627 return 0;
1da177e4 628 }
65e074df
TG
629
630 /*
631 * Check, whether we can keep the large page intact
632 * and just change the pte:
633 */
beaff633 634 do_split = try_preserve_large_page(kpte, address, cpa);
65e074df
TG
635 /*
636 * When the range fits into the existing large page,
9b5cf48b 637 * return. cp->numpages and cpa->tlbflush have been updated in
65e074df
TG
638 * try_large_page:
639 */
87f7f8fe
IM
640 if (do_split <= 0)
641 return do_split;
65e074df
TG
642
643 /*
644 * We have to split the large page:
645 */
87f7f8fe
IM
646 err = split_large_page(kpte, address);
647 if (!err) {
648 cpa->flushtlb = 1;
649 goto repeat;
650 }
beaff633 651
87f7f8fe 652 return err;
9f4c815c 653}
1da177e4 654
c31c7d48
TG
655static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
656
657static int cpa_process_alias(struct cpa_data *cpa)
1da177e4 658{
c31c7d48 659 struct cpa_data alias_cpa;
f34b439f 660 int ret = 0;
44af6c41 661
965194c1 662 if (cpa->pfn >= max_pfn_mapped)
c31c7d48 663 return 0;
626c2c9d 664
f361a450 665#ifdef CONFIG_X86_64
965194c1 666 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
f361a450
YL
667 return 0;
668#endif
f34b439f
TG
669 /*
670 * No need to redo, when the primary call touched the direct
671 * mapping already:
672 */
f361a450
YL
673 if (!(within(cpa->vaddr, PAGE_OFFSET,
674 PAGE_OFFSET + (max_low_pfn_mapped << PAGE_SHIFT))
675#ifdef CONFIG_X86_64
676 || within(cpa->vaddr, PAGE_OFFSET + (1UL<<32),
677 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))
678#endif
679 )) {
44af6c41 680
f34b439f
TG
681 alias_cpa = *cpa;
682 alias_cpa.vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT);
683
684 ret = __change_page_attr_set_clr(&alias_cpa, 0);
685 }
44af6c41 686
44af6c41 687#ifdef CONFIG_X86_64
c31c7d48
TG
688 if (ret)
689 return ret;
f34b439f
TG
690 /*
691 * No need to redo, when the primary call touched the high
692 * mapping already:
693 */
694 if (within(cpa->vaddr, (unsigned long) _text, (unsigned long) _end))
695 return 0;
696
488fd995 697 /*
0879750f
TG
698 * If the physical address is inside the kernel map, we need
699 * to touch the high mapped kernel as well:
488fd995 700 */
c31c7d48
TG
701 if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn()))
702 return 0;
0879750f 703
c31c7d48
TG
704 alias_cpa = *cpa;
705 alias_cpa.vaddr =
706 (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base;
707
708 /*
709 * The high mapping range is imprecise, so ignore the return value.
710 */
711 __change_page_attr_set_clr(&alias_cpa, 0);
488fd995 712#endif
c31c7d48 713 return ret;
1da177e4
LT
714}
715
c31c7d48 716static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
ff31452b 717{
65e074df 718 int ret, numpages = cpa->numpages;
ff31452b 719
65e074df
TG
720 while (numpages) {
721 /*
722 * Store the remaining nr of pages for the large page
723 * preservation check.
724 */
9b5cf48b 725 cpa->numpages = numpages;
c31c7d48
TG
726
727 ret = __change_page_attr(cpa, checkalias);
ff31452b
TG
728 if (ret)
729 return ret;
ff31452b 730
c31c7d48
TG
731 if (checkalias) {
732 ret = cpa_process_alias(cpa);
733 if (ret)
734 return ret;
735 }
736
65e074df
TG
737 /*
738 * Adjust the number of pages with the result of the
739 * CPA operation. Either a large page has been
740 * preserved or a single page update happened.
741 */
9b5cf48b
RW
742 BUG_ON(cpa->numpages > numpages);
743 numpages -= cpa->numpages;
744 cpa->vaddr += cpa->numpages * PAGE_SIZE;
65e074df 745 }
ff31452b
TG
746 return 0;
747}
748
6bb8383b
AK
749static inline int cache_attr(pgprot_t attr)
750{
751 return pgprot_val(attr) &
752 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
753}
754
ff31452b 755static int change_page_attr_set_clr(unsigned long addr, int numpages,
c9caa02c
AK
756 pgprot_t mask_set, pgprot_t mask_clr,
757 int force_split)
ff31452b 758{
72e458df 759 struct cpa_data cpa;
af96e443 760 int ret, cache, checkalias;
331e4065
TG
761
762 /*
763 * Check, if we are requested to change a not supported
764 * feature:
765 */
766 mask_set = canon_pgprot(mask_set);
767 mask_clr = canon_pgprot(mask_clr);
c9caa02c 768 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
331e4065
TG
769 return 0;
770
69b1415e
TG
771 /* Ensure we are PAGE_SIZE aligned */
772 if (addr & ~PAGE_MASK) {
773 addr &= PAGE_MASK;
774 /*
775 * People should not be passing in unaligned addresses:
776 */
777 WARN_ON_ONCE(1);
778 }
779
72e458df
TG
780 cpa.vaddr = addr;
781 cpa.numpages = numpages;
782 cpa.mask_set = mask_set;
783 cpa.mask_clr = mask_clr;
f4ae5da0 784 cpa.flushtlb = 0;
c9caa02c 785 cpa.force_split = force_split;
72e458df 786
af96e443
TG
787 /* No alias checking for _NX bit modifications */
788 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
789
790 ret = __change_page_attr_set_clr(&cpa, checkalias);
ff31452b 791
f4ae5da0
TG
792 /*
793 * Check whether we really changed something:
794 */
795 if (!cpa.flushtlb)
76ebd054 796 goto out;
f4ae5da0 797
6bb8383b
AK
798 /*
799 * No need to flush, when we did not set any of the caching
800 * attributes:
801 */
802 cache = cache_attr(mask_set);
803
57a6a46a
TG
804 /*
805 * On success we use clflush, when the CPU supports it to
806 * avoid the wbindv. If the CPU does not support it and in the
af1e6844 807 * error case we fall back to cpa_flush_all (which uses
57a6a46a
TG
808 * wbindv):
809 */
810 if (!ret && cpu_has_clflush)
6bb8383b 811 cpa_flush_range(addr, numpages, cache);
57a6a46a 812 else
6bb8383b 813 cpa_flush_all(cache);
ff31452b 814
76ebd054 815out:
92cb54a3
IM
816 cpa_fill_pool(NULL);
817
ff31452b
TG
818 return ret;
819}
820
56744546
TG
821static inline int change_page_attr_set(unsigned long addr, int numpages,
822 pgprot_t mask)
75cbade8 823{
c9caa02c 824 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0);
75cbade8
AV
825}
826
56744546
TG
827static inline int change_page_attr_clear(unsigned long addr, int numpages,
828 pgprot_t mask)
72932c7a 829{
c9caa02c 830 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0);
72932c7a
TG
831}
832
1219333d 833int _set_memory_uc(unsigned long addr, int numpages)
72932c7a 834{
de33c442
SS
835 /*
836 * for now UC MINUS. see comments in ioremap_nocache()
837 */
72932c7a 838 return change_page_attr_set(addr, numpages,
de33c442 839 __pgprot(_PAGE_CACHE_UC_MINUS));
75cbade8 840}
1219333d 841
842int set_memory_uc(unsigned long addr, int numpages)
843{
de33c442
SS
844 /*
845 * for now UC MINUS. see comments in ioremap_nocache()
846 */
1219333d 847 if (reserve_memtype(addr, addr + numpages * PAGE_SIZE,
de33c442 848 _PAGE_CACHE_UC_MINUS, NULL))
1219333d 849 return -EINVAL;
850
851 return _set_memory_uc(addr, numpages);
852}
75cbade8
AV
853EXPORT_SYMBOL(set_memory_uc);
854
ef354af4 855int _set_memory_wc(unsigned long addr, int numpages)
856{
857 return change_page_attr_set(addr, numpages,
858 __pgprot(_PAGE_CACHE_WC));
859}
860
861int set_memory_wc(unsigned long addr, int numpages)
862{
499f8f84 863 if (!pat_enabled)
ef354af4 864 return set_memory_uc(addr, numpages);
865
866 if (reserve_memtype(addr, addr + numpages * PAGE_SIZE,
867 _PAGE_CACHE_WC, NULL))
868 return -EINVAL;
869
870 return _set_memory_wc(addr, numpages);
871}
872EXPORT_SYMBOL(set_memory_wc);
873
1219333d 874int _set_memory_wb(unsigned long addr, int numpages)
75cbade8 875{
72932c7a 876 return change_page_attr_clear(addr, numpages,
2e5d9c85 877 __pgprot(_PAGE_CACHE_MASK));
75cbade8 878}
1219333d 879
880int set_memory_wb(unsigned long addr, int numpages)
881{
882 free_memtype(addr, addr + numpages * PAGE_SIZE);
883
884 return _set_memory_wb(addr, numpages);
885}
75cbade8
AV
886EXPORT_SYMBOL(set_memory_wb);
887
888int set_memory_x(unsigned long addr, int numpages)
889{
72932c7a 890 return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX));
75cbade8
AV
891}
892EXPORT_SYMBOL(set_memory_x);
893
894int set_memory_nx(unsigned long addr, int numpages)
895{
72932c7a 896 return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX));
75cbade8
AV
897}
898EXPORT_SYMBOL(set_memory_nx);
899
900int set_memory_ro(unsigned long addr, int numpages)
901{
72932c7a 902 return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW));
75cbade8 903}
75cbade8
AV
904
905int set_memory_rw(unsigned long addr, int numpages)
906{
72932c7a 907 return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW));
75cbade8 908}
f62d0f00
IM
909
910int set_memory_np(unsigned long addr, int numpages)
911{
72932c7a 912 return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT));
f62d0f00 913}
75cbade8 914
c9caa02c
AK
915int set_memory_4k(unsigned long addr, int numpages)
916{
917 return change_page_attr_set_clr(addr, numpages, __pgprot(0),
918 __pgprot(0), 1);
919}
920
75cbade8
AV
921int set_pages_uc(struct page *page, int numpages)
922{
923 unsigned long addr = (unsigned long)page_address(page);
75cbade8 924
d7c8f21a 925 return set_memory_uc(addr, numpages);
75cbade8
AV
926}
927EXPORT_SYMBOL(set_pages_uc);
928
929int set_pages_wb(struct page *page, int numpages)
930{
931 unsigned long addr = (unsigned long)page_address(page);
75cbade8 932
d7c8f21a 933 return set_memory_wb(addr, numpages);
75cbade8
AV
934}
935EXPORT_SYMBOL(set_pages_wb);
936
937int set_pages_x(struct page *page, int numpages)
938{
939 unsigned long addr = (unsigned long)page_address(page);
75cbade8 940
d7c8f21a 941 return set_memory_x(addr, numpages);
75cbade8
AV
942}
943EXPORT_SYMBOL(set_pages_x);
944
945int set_pages_nx(struct page *page, int numpages)
946{
947 unsigned long addr = (unsigned long)page_address(page);
75cbade8 948
d7c8f21a 949 return set_memory_nx(addr, numpages);
75cbade8
AV
950}
951EXPORT_SYMBOL(set_pages_nx);
952
953int set_pages_ro(struct page *page, int numpages)
954{
955 unsigned long addr = (unsigned long)page_address(page);
75cbade8 956
d7c8f21a 957 return set_memory_ro(addr, numpages);
75cbade8 958}
75cbade8
AV
959
960int set_pages_rw(struct page *page, int numpages)
961{
962 unsigned long addr = (unsigned long)page_address(page);
e81d5dc4 963
d7c8f21a 964 return set_memory_rw(addr, numpages);
78c94aba
IM
965}
966
1da177e4 967#ifdef CONFIG_DEBUG_PAGEALLOC
f62d0f00
IM
968
969static int __set_pages_p(struct page *page, int numpages)
970{
72e458df
TG
971 struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page),
972 .numpages = numpages,
973 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
974 .mask_clr = __pgprot(0)};
72932c7a 975
c31c7d48 976 return __change_page_attr_set_clr(&cpa, 1);
f62d0f00
IM
977}
978
979static int __set_pages_np(struct page *page, int numpages)
980{
72e458df
TG
981 struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page),
982 .numpages = numpages,
983 .mask_set = __pgprot(0),
984 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW)};
72932c7a 985
c31c7d48 986 return __change_page_attr_set_clr(&cpa, 1);
f62d0f00
IM
987}
988
1da177e4
LT
989void kernel_map_pages(struct page *page, int numpages, int enable)
990{
991 if (PageHighMem(page))
992 return;
9f4c815c 993 if (!enable) {
f9b8404c
IM
994 debug_check_no_locks_freed(page_address(page),
995 numpages * PAGE_SIZE);
9f4c815c 996 }
de5097c2 997
12d6f21e
IM
998 /*
999 * If page allocator is not up yet then do not call c_p_a():
1000 */
1001 if (!debug_pagealloc_enabled)
1002 return;
1003
9f4c815c 1004 /*
f8d8406b
IM
1005 * The return value is ignored as the calls cannot fail.
1006 * Large pages are kept enabled at boot time, and are
1007 * split up quickly with DEBUG_PAGEALLOC. If a splitup
1008 * fails here (due to temporary memory shortage) no damage
1009 * is done because we just keep the largepage intact up
1010 * to the next attempt when it will likely be split up:
1da177e4 1011 */
f62d0f00
IM
1012 if (enable)
1013 __set_pages_p(page, numpages);
1014 else
1015 __set_pages_np(page, numpages);
9f4c815c
IM
1016
1017 /*
e4b71dcf
IM
1018 * We should perform an IPI and flush all tlbs,
1019 * but that can deadlock->flush only current cpu:
1da177e4
LT
1020 */
1021 __flush_tlb_all();
76ebd054
TG
1022
1023 /*
1024 * Try to refill the page pool here. We can do this only after
1025 * the tlb flush.
1026 */
92cb54a3 1027 cpa_fill_pool(NULL);
1da177e4 1028}
8a235efa 1029
ee7ae7a1
TG
1030#ifdef CONFIG_DEBUG_FS
1031static int dpa_show(struct seq_file *m, void *v)
1032{
1033 seq_puts(m, "DEBUG_PAGEALLOC\n");
1034 seq_printf(m, "pool_size : %lu\n", pool_size);
1035 seq_printf(m, "pool_pages : %lu\n", pool_pages);
1036 seq_printf(m, "pool_low : %lu\n", pool_low);
1037 seq_printf(m, "pool_used : %lu\n", pool_used);
1038 seq_printf(m, "pool_failed : %lu\n", pool_failed);
1039
1040 return 0;
1041}
1042
1043static int dpa_open(struct inode *inode, struct file *filp)
1044{
1045 return single_open(filp, dpa_show, NULL);
1046}
1047
1048static const struct file_operations dpa_fops = {
1049 .open = dpa_open,
1050 .read = seq_read,
1051 .llseek = seq_lseek,
1052 .release = single_release,
1053};
1054
a4928cff 1055static int __init debug_pagealloc_proc_init(void)
ee7ae7a1
TG
1056{
1057 struct dentry *de;
1058
1059 de = debugfs_create_file("debug_pagealloc", 0600, NULL, NULL,
1060 &dpa_fops);
1061 if (!de)
1062 return -ENOMEM;
1063
1064 return 0;
1065}
1066__initcall(debug_pagealloc_proc_init);
1067#endif
1068
8a235efa
RW
1069#ifdef CONFIG_HIBERNATION
1070
1071bool kernel_page_present(struct page *page)
1072{
1073 unsigned int level;
1074 pte_t *pte;
1075
1076 if (PageHighMem(page))
1077 return false;
1078
1079 pte = lookup_address((unsigned long)page_address(page), &level);
1080 return (pte_val(*pte) & _PAGE_PRESENT);
1081}
1082
1083#endif /* CONFIG_HIBERNATION */
1084
1085#endif /* CONFIG_DEBUG_PAGEALLOC */
d1028a15
AV
1086
1087/*
1088 * The testcases use internal knowledge of the implementation that shouldn't
1089 * be exposed to the rest of the kernel. Include these directly here.
1090 */
1091#ifdef CONFIG_CPA_DEBUG
1092#include "pageattr-test.c"
1093#endif