Commit | Line | Data |
---|---|---|
457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
9f4c815c IM |
2 | /* |
3 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 4 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 5 | */ |
1da177e4 | 6 | #include <linux/highmem.h> |
57c8a661 | 7 | #include <linux/memblock.h> |
9f4c815c | 8 | #include <linux/sched.h> |
9f4c815c | 9 | #include <linux/mm.h> |
76ebd054 | 10 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
11 | #include <linux/seq_file.h> |
12 | #include <linux/debugfs.h> | |
e59a1bb2 | 13 | #include <linux/pfn.h> |
8c4bfc6e | 14 | #include <linux/percpu.h> |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
5bd5a452 | 16 | #include <linux/pci.h> |
d6472302 | 17 | #include <linux/vmalloc.h> |
9f4c815c | 18 | |
66441bd3 | 19 | #include <asm/e820/api.h> |
1da177e4 LT |
20 | #include <asm/processor.h> |
21 | #include <asm/tlbflush.h> | |
f8af095d | 22 | #include <asm/sections.h> |
93dbda7c | 23 | #include <asm/setup.h> |
7c0f6ba6 | 24 | #include <linux/uaccess.h> |
9f4c815c | 25 | #include <asm/pgalloc.h> |
c31c7d48 | 26 | #include <asm/proto.h> |
1219333d | 27 | #include <asm/pat.h> |
d1163651 | 28 | #include <asm/set_memory.h> |
1da177e4 | 29 | |
935f5839 PZ |
30 | #include "mm_internal.h" |
31 | ||
9df84993 IM |
32 | /* |
33 | * The current flushing context - we pass it instead of 5 arguments: | |
34 | */ | |
72e458df | 35 | struct cpa_data { |
d75586ad | 36 | unsigned long *vaddr; |
0fd64c23 | 37 | pgd_t *pgd; |
72e458df TG |
38 | pgprot_t mask_set; |
39 | pgprot_t mask_clr; | |
74256377 | 40 | unsigned long numpages; |
98bfc9b0 | 41 | unsigned long curpage; |
c31c7d48 | 42 | unsigned long pfn; |
98bfc9b0 PZ |
43 | unsigned int flags; |
44 | unsigned int force_split : 1, | |
f61c5ba2 | 45 | force_static_prot : 1; |
9ae28475 | 46 | struct page **pages; |
72e458df TG |
47 | }; |
48 | ||
4046460b | 49 | enum cpa_warn { |
f61c5ba2 | 50 | CPA_CONFLICT, |
4046460b TG |
51 | CPA_PROTECT, |
52 | CPA_DETECT, | |
53 | }; | |
54 | ||
55 | static const int cpa_warn_level = CPA_PROTECT; | |
56 | ||
ad5ca55f SS |
57 | /* |
58 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
59 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
60 | * entries change the page attribute in parallel to some other cpu | |
61 | * splitting a large page entry along with changing the attribute. | |
62 | */ | |
63 | static DEFINE_SPINLOCK(cpa_lock); | |
64 | ||
d75586ad SL |
65 | #define CPA_FLUSHTLB 1 |
66 | #define CPA_ARRAY 2 | |
9ae28475 | 67 | #define CPA_PAGES_ARRAY 4 |
c40a56a7 | 68 | #define CPA_NO_CHECK_ALIAS 8 /* Do not search for aliases */ |
d75586ad | 69 | |
65280e61 | 70 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
71 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
72 | ||
65280e61 | 73 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 74 | { |
ce0c0e50 | 75 | /* Protect against CPA */ |
a79e53d8 | 76 | spin_lock(&pgd_lock); |
ce0c0e50 | 77 | direct_pages_count[level] += pages; |
a79e53d8 | 78 | spin_unlock(&pgd_lock); |
65280e61 TG |
79 | } |
80 | ||
81 | static void split_page_count(int level) | |
82 | { | |
c9e0d391 DJ |
83 | if (direct_pages_count[level] == 0) |
84 | return; | |
85 | ||
65280e61 TG |
86 | direct_pages_count[level]--; |
87 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
88 | } | |
89 | ||
e1759c21 | 90 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 91 | { |
b9c3bfc2 | 92 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
93 | direct_pages_count[PG_LEVEL_4K] << 2); |
94 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 95 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
96 | direct_pages_count[PG_LEVEL_2M] << 11); |
97 | #else | |
b9c3bfc2 | 98 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
99 | direct_pages_count[PG_LEVEL_2M] << 12); |
100 | #endif | |
a06de630 | 101 | if (direct_gbpages) |
b9c3bfc2 | 102 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 103 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 | 104 | } |
65280e61 TG |
105 | #else |
106 | static inline void split_page_count(int level) { } | |
107 | #endif | |
ce0c0e50 | 108 | |
5c280cf6 TG |
109 | #ifdef CONFIG_X86_CPA_STATISTICS |
110 | ||
111 | static unsigned long cpa_1g_checked; | |
112 | static unsigned long cpa_1g_sameprot; | |
113 | static unsigned long cpa_1g_preserved; | |
114 | static unsigned long cpa_2m_checked; | |
115 | static unsigned long cpa_2m_sameprot; | |
116 | static unsigned long cpa_2m_preserved; | |
5c280cf6 TG |
117 | static unsigned long cpa_4k_install; |
118 | ||
119 | static inline void cpa_inc_1g_checked(void) | |
120 | { | |
121 | cpa_1g_checked++; | |
122 | } | |
123 | ||
124 | static inline void cpa_inc_2m_checked(void) | |
125 | { | |
126 | cpa_2m_checked++; | |
127 | } | |
128 | ||
5c280cf6 TG |
129 | static inline void cpa_inc_4k_install(void) |
130 | { | |
131 | cpa_4k_install++; | |
132 | } | |
133 | ||
134 | static inline void cpa_inc_lp_sameprot(int level) | |
135 | { | |
136 | if (level == PG_LEVEL_1G) | |
137 | cpa_1g_sameprot++; | |
138 | else | |
139 | cpa_2m_sameprot++; | |
140 | } | |
141 | ||
142 | static inline void cpa_inc_lp_preserved(int level) | |
143 | { | |
144 | if (level == PG_LEVEL_1G) | |
145 | cpa_1g_preserved++; | |
146 | else | |
147 | cpa_2m_preserved++; | |
148 | } | |
149 | ||
150 | static int cpastats_show(struct seq_file *m, void *p) | |
151 | { | |
152 | seq_printf(m, "1G pages checked: %16lu\n", cpa_1g_checked); | |
153 | seq_printf(m, "1G pages sameprot: %16lu\n", cpa_1g_sameprot); | |
154 | seq_printf(m, "1G pages preserved: %16lu\n", cpa_1g_preserved); | |
155 | seq_printf(m, "2M pages checked: %16lu\n", cpa_2m_checked); | |
156 | seq_printf(m, "2M pages sameprot: %16lu\n", cpa_2m_sameprot); | |
157 | seq_printf(m, "2M pages preserved: %16lu\n", cpa_2m_preserved); | |
5c280cf6 TG |
158 | seq_printf(m, "4K pages set-checked: %16lu\n", cpa_4k_install); |
159 | return 0; | |
160 | } | |
161 | ||
162 | static int cpastats_open(struct inode *inode, struct file *file) | |
163 | { | |
164 | return single_open(file, cpastats_show, NULL); | |
165 | } | |
166 | ||
167 | static const struct file_operations cpastats_fops = { | |
168 | .open = cpastats_open, | |
169 | .read = seq_read, | |
170 | .llseek = seq_lseek, | |
171 | .release = single_release, | |
172 | }; | |
173 | ||
174 | static int __init cpa_stats_init(void) | |
175 | { | |
176 | debugfs_create_file("cpa_stats", S_IRUSR, arch_debugfs_dir, NULL, | |
177 | &cpastats_fops); | |
178 | return 0; | |
179 | } | |
180 | late_initcall(cpa_stats_init); | |
181 | #else | |
182 | static inline void cpa_inc_1g_checked(void) { } | |
183 | static inline void cpa_inc_2m_checked(void) { } | |
5c280cf6 TG |
184 | static inline void cpa_inc_4k_install(void) { } |
185 | static inline void cpa_inc_lp_sameprot(int level) { } | |
186 | static inline void cpa_inc_lp_preserved(int level) { } | |
187 | #endif | |
188 | ||
189 | ||
58e65b51 DH |
190 | static inline int |
191 | within(unsigned long addr, unsigned long start, unsigned long end) | |
192 | { | |
193 | return addr >= start && addr < end; | |
194 | } | |
195 | ||
196 | static inline int | |
197 | within_inclusive(unsigned long addr, unsigned long start, unsigned long end) | |
198 | { | |
199 | return addr >= start && addr <= end; | |
200 | } | |
201 | ||
c31c7d48 TG |
202 | #ifdef CONFIG_X86_64 |
203 | ||
204 | static inline unsigned long highmap_start_pfn(void) | |
205 | { | |
fc8d7826 | 206 | return __pa_symbol(_text) >> PAGE_SHIFT; |
c31c7d48 TG |
207 | } |
208 | ||
209 | static inline unsigned long highmap_end_pfn(void) | |
210 | { | |
4ff53087 TG |
211 | /* Do not reference physical address outside the kernel. */ |
212 | return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT; | |
c31c7d48 TG |
213 | } |
214 | ||
58e65b51 | 215 | static bool __cpa_pfn_in_highmap(unsigned long pfn) |
687c4825 | 216 | { |
58e65b51 DH |
217 | /* |
218 | * Kernel text has an alias mapping at a high address, known | |
219 | * here as "highmap". | |
220 | */ | |
221 | return within_inclusive(pfn, highmap_start_pfn(), highmap_end_pfn()); | |
ed724be6 AV |
222 | } |
223 | ||
58e65b51 DH |
224 | #else |
225 | ||
226 | static bool __cpa_pfn_in_highmap(unsigned long pfn) | |
4ff53087 | 227 | { |
58e65b51 DH |
228 | /* There is no highmap on 32-bit */ |
229 | return false; | |
4ff53087 TG |
230 | } |
231 | ||
58e65b51 DH |
232 | #endif |
233 | ||
0521e8be PZ |
234 | /* |
235 | * See set_mce_nospec(). | |
236 | * | |
237 | * Machine check recovery code needs to change cache mode of poisoned pages to | |
238 | * UC to avoid speculative access logging another error. But passing the | |
239 | * address of the 1:1 mapping to set_memory_uc() is a fine way to encourage a | |
240 | * speculative access. So we cheat and flip the top bit of the address. This | |
241 | * works fine for the code that updates the page tables. But at the end of the | |
242 | * process we need to flush the TLB and cache and the non-canonical address | |
243 | * causes a #GP fault when used by the INVLPG and CLFLUSH instructions. | |
244 | * | |
245 | * But in the common case we already have a canonical address. This code | |
246 | * will fix the top bit if needed and is a no-op otherwise. | |
247 | */ | |
248 | static inline unsigned long fix_addr(unsigned long addr) | |
249 | { | |
250 | #ifdef CONFIG_X86_64 | |
251 | return (long)(addr << 1) >> 1; | |
252 | #else | |
253 | return addr; | |
254 | #endif | |
255 | } | |
256 | ||
98bfc9b0 | 257 | static unsigned long __cpa_addr(struct cpa_data *cpa, unsigned long idx) |
16ebf031 PZ |
258 | { |
259 | if (cpa->flags & CPA_PAGES_ARRAY) { | |
260 | struct page *page = cpa->pages[idx]; | |
261 | ||
262 | if (unlikely(PageHighMem(page))) | |
263 | return 0; | |
264 | ||
265 | return (unsigned long)page_address(page); | |
266 | } | |
267 | ||
268 | if (cpa->flags & CPA_ARRAY) | |
269 | return cpa->vaddr[idx]; | |
270 | ||
98bfc9b0 | 271 | return *cpa->vaddr + idx * PAGE_SIZE; |
16ebf031 PZ |
272 | } |
273 | ||
d7c8f21a TG |
274 | /* |
275 | * Flushing functions | |
276 | */ | |
cd8ddf1a | 277 | |
c38116bb | 278 | static void clflush_cache_range_opt(void *vaddr, unsigned int size) |
d7c8f21a | 279 | { |
1f1a89ac CW |
280 | const unsigned long clflush_size = boot_cpu_data.x86_clflush_size; |
281 | void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1)); | |
6c434d61 | 282 | void *vend = vaddr + size; |
1f1a89ac CW |
283 | |
284 | if (p >= vend) | |
285 | return; | |
d7c8f21a | 286 | |
1f1a89ac | 287 | for (; p < vend; p += clflush_size) |
6c434d61 | 288 | clflushopt(p); |
c38116bb | 289 | } |
4c61afcd | 290 | |
c38116bb PZ |
291 | /** |
292 | * clflush_cache_range - flush a cache range with clflush | |
293 | * @vaddr: virtual start address | |
294 | * @size: number of bytes to flush | |
295 | * | |
296 | * CLFLUSHOPT is an unordered instruction which needs fencing with MFENCE or | |
297 | * SFENCE to avoid ordering issues. | |
298 | */ | |
299 | void clflush_cache_range(void *vaddr, unsigned int size) | |
300 | { | |
301 | mb(); | |
302 | clflush_cache_range_opt(vaddr, size); | |
cd8ddf1a | 303 | mb(); |
d7c8f21a | 304 | } |
e517a5e9 | 305 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 306 | |
f2b61257 DW |
307 | void arch_invalidate_pmem(void *addr, size_t size) |
308 | { | |
309 | clflush_cache_range(addr, size); | |
310 | } | |
311 | EXPORT_SYMBOL_GPL(arch_invalidate_pmem); | |
312 | ||
af1e6844 | 313 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 314 | { |
6bb8383b AK |
315 | unsigned long cache = (unsigned long)arg; |
316 | ||
d7c8f21a TG |
317 | /* |
318 | * Flush all to work around Errata in early athlons regarding | |
319 | * large page flushing. | |
320 | */ | |
321 | __flush_tlb_all(); | |
322 | ||
0b827537 | 323 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
324 | wbinvd(); |
325 | } | |
326 | ||
6bb8383b | 327 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a | 328 | { |
d2479a30 | 329 | BUG_ON(irqs_disabled() && !early_boot_irqs_disabled); |
d7c8f21a | 330 | |
15c8b6c1 | 331 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
332 | } |
333 | ||
fe0937b2 | 334 | void __cpa_flush_tlb(void *data) |
57a6a46a | 335 | { |
935f5839 PZ |
336 | struct cpa_data *cpa = data; |
337 | unsigned int i; | |
47e262ac | 338 | |
935f5839 | 339 | for (i = 0; i < cpa->numpages; i++) |
0521e8be | 340 | __flush_tlb_one_kernel(fix_addr(__cpa_addr(cpa, i))); |
47e262ac PZ |
341 | } |
342 | ||
fe0937b2 | 343 | static void cpa_flush(struct cpa_data *data, int cache) |
47e262ac | 344 | { |
fe0937b2 | 345 | struct cpa_data *cpa = data; |
935f5839 | 346 | unsigned int i; |
47e262ac | 347 | |
fe0937b2 | 348 | BUG_ON(irqs_disabled() && !early_boot_irqs_disabled); |
721066df | 349 | |
fe0937b2 PZ |
350 | if (cache && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
351 | cpa_flush_all(cache); | |
6bb8383b | 352 | return; |
4c61afcd | 353 | } |
57a6a46a | 354 | |
935f5839 | 355 | if (cpa->numpages <= tlb_single_page_flush_ceiling) |
fe0937b2 | 356 | on_each_cpu(__cpa_flush_tlb, cpa, 1); |
935f5839 PZ |
357 | else |
358 | flush_tlb_all(); | |
721066df PZ |
359 | |
360 | if (!cache) | |
d75586ad SL |
361 | return; |
362 | ||
c38116bb | 363 | mb(); |
935f5839 PZ |
364 | for (i = 0; i < cpa->numpages; i++) { |
365 | unsigned long addr = __cpa_addr(cpa, i); | |
366 | unsigned int level; | |
9ae28475 | 367 | |
fe0937b2 | 368 | pte_t *pte = lookup_address(addr, &level); |
d75586ad SL |
369 | |
370 | /* | |
371 | * Only flush present addresses: | |
372 | */ | |
373 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
0521e8be | 374 | clflush_cache_range_opt((void *)fix_addr(addr), PAGE_SIZE); |
d75586ad | 375 | } |
c38116bb | 376 | mb(); |
d75586ad SL |
377 | } |
378 | ||
91ee8f5c TG |
379 | static bool overlaps(unsigned long r1_start, unsigned long r1_end, |
380 | unsigned long r2_start, unsigned long r2_end) | |
381 | { | |
382 | return (r1_start <= r2_end && r1_end >= r2_start) || | |
383 | (r2_start <= r1_end && r2_end >= r1_start); | |
384 | } | |
385 | ||
afd7969a | 386 | #ifdef CONFIG_PCI_BIOS |
ed724be6 | 387 | /* |
afd7969a TG |
388 | * The BIOS area between 640k and 1Mb needs to be executable for PCI BIOS |
389 | * based config access (CONFIG_PCI_GOBIOS) support. | |
ed724be6 | 390 | */ |
afd7969a | 391 | #define BIOS_PFN PFN_DOWN(BIOS_BEGIN) |
91ee8f5c | 392 | #define BIOS_PFN_END PFN_DOWN(BIOS_END - 1) |
ed724be6 | 393 | |
91ee8f5c | 394 | static pgprotval_t protect_pci_bios(unsigned long spfn, unsigned long epfn) |
afd7969a | 395 | { |
91ee8f5c | 396 | if (pcibios_enabled && overlaps(spfn, epfn, BIOS_PFN, BIOS_PFN_END)) |
afd7969a TG |
397 | return _PAGE_NX; |
398 | return 0; | |
399 | } | |
400 | #else | |
91ee8f5c | 401 | static pgprotval_t protect_pci_bios(unsigned long spfn, unsigned long epfn) |
afd7969a TG |
402 | { |
403 | return 0; | |
404 | } | |
5bd5a452 | 405 | #endif |
ed724be6 | 406 | |
afd7969a TG |
407 | /* |
408 | * The .rodata section needs to be read-only. Using the pfn catches all | |
409 | * aliases. This also includes __ro_after_init, so do not enforce until | |
410 | * kernel_set_to_readonly is true. | |
411 | */ | |
91ee8f5c | 412 | static pgprotval_t protect_rodata(unsigned long spfn, unsigned long epfn) |
afd7969a | 413 | { |
91ee8f5c TG |
414 | unsigned long epfn_ro, spfn_ro = PFN_DOWN(__pa_symbol(__start_rodata)); |
415 | ||
416 | /* | |
417 | * Note: __end_rodata is at page aligned and not inclusive, so | |
418 | * subtract 1 to get the last enforced PFN in the rodata area. | |
419 | */ | |
420 | epfn_ro = PFN_DOWN(__pa_symbol(__end_rodata)) - 1; | |
cc0f21bb | 421 | |
91ee8f5c | 422 | if (kernel_set_to_readonly && overlaps(spfn, epfn, spfn_ro, epfn_ro)) |
afd7969a TG |
423 | return _PAGE_RW; |
424 | return 0; | |
425 | } | |
426 | ||
427 | /* | |
428 | * Protect kernel text against becoming non executable by forbidding | |
429 | * _PAGE_NX. This protects only the high kernel mapping (_text -> _etext) | |
430 | * out of which the kernel actually executes. Do not protect the low | |
431 | * mapping. | |
432 | * | |
433 | * This does not cover __inittext since that is gone after boot. | |
434 | */ | |
91ee8f5c | 435 | static pgprotval_t protect_kernel_text(unsigned long start, unsigned long end) |
afd7969a | 436 | { |
91ee8f5c TG |
437 | unsigned long t_end = (unsigned long)_etext - 1; |
438 | unsigned long t_start = (unsigned long)_text; | |
439 | ||
440 | if (overlaps(start, end, t_start, t_end)) | |
afd7969a TG |
441 | return _PAGE_NX; |
442 | return 0; | |
443 | } | |
ed724be6 | 444 | |
9ccaf77c | 445 | #if defined(CONFIG_X86_64) |
afd7969a TG |
446 | /* |
447 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), | |
448 | * kernel text mappings for the large page aligned text, rodata sections | |
449 | * will be always read-only. For the kernel identity mappings covering the | |
450 | * holes caused by this alignment can be anything that user asks. | |
451 | * | |
452 | * This will preserve the large page mappings for kernel text/data at no | |
453 | * extra cost. | |
454 | */ | |
91ee8f5c TG |
455 | static pgprotval_t protect_kernel_text_ro(unsigned long start, |
456 | unsigned long end) | |
afd7969a | 457 | { |
91ee8f5c TG |
458 | unsigned long t_end = (unsigned long)__end_rodata_hpage_align - 1; |
459 | unsigned long t_start = (unsigned long)_text; | |
afd7969a TG |
460 | unsigned int level; |
461 | ||
91ee8f5c | 462 | if (!kernel_set_to_readonly || !overlaps(start, end, t_start, t_end)) |
afd7969a | 463 | return 0; |
74e08179 | 464 | /* |
afd7969a TG |
465 | * Don't enforce the !RW mapping for the kernel text mapping, if |
466 | * the current mapping is already using small page mapping. No | |
467 | * need to work hard to preserve large page mappings in this case. | |
74e08179 | 468 | * |
afd7969a TG |
469 | * This also fixes the Linux Xen paravirt guest boot failure caused |
470 | * by unexpected read-only mappings for kernel identity | |
471 | * mappings. In this paravirt guest case, the kernel text mapping | |
472 | * and the kernel identity mapping share the same page-table pages, | |
473 | * so the protections for kernel text and identity mappings have to | |
474 | * be the same. | |
74e08179 | 475 | */ |
91ee8f5c | 476 | if (lookup_address(start, &level) && (level != PG_LEVEL_4K)) |
afd7969a TG |
477 | return _PAGE_RW; |
478 | return 0; | |
479 | } | |
480 | #else | |
91ee8f5c TG |
481 | static pgprotval_t protect_kernel_text_ro(unsigned long start, |
482 | unsigned long end) | |
afd7969a TG |
483 | { |
484 | return 0; | |
485 | } | |
74e08179 SS |
486 | #endif |
487 | ||
4046460b TG |
488 | static inline bool conflicts(pgprot_t prot, pgprotval_t val) |
489 | { | |
490 | return (pgprot_val(prot) & ~val) != pgprot_val(prot); | |
491 | } | |
492 | ||
493 | static inline void check_conflict(int warnlvl, pgprot_t prot, pgprotval_t val, | |
494 | unsigned long start, unsigned long end, | |
495 | unsigned long pfn, const char *txt) | |
496 | { | |
497 | static const char *lvltxt[] = { | |
f61c5ba2 | 498 | [CPA_CONFLICT] = "conflict", |
4046460b TG |
499 | [CPA_PROTECT] = "protect", |
500 | [CPA_DETECT] = "detect", | |
501 | }; | |
502 | ||
503 | if (warnlvl > cpa_warn_level || !conflicts(prot, val)) | |
504 | return; | |
505 | ||
506 | pr_warn("CPA %8s %10s: 0x%016lx - 0x%016lx PFN %lx req %016llx prevent %016llx\n", | |
507 | lvltxt[warnlvl], txt, start, end, pfn, (unsigned long long)pgprot_val(prot), | |
508 | (unsigned long long)val); | |
509 | } | |
510 | ||
afd7969a TG |
511 | /* |
512 | * Certain areas of memory on x86 require very specific protection flags, | |
513 | * for example the BIOS area or kernel text. Callers don't always get this | |
514 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
515 | * checks and fixes these known static required protection bits. | |
516 | */ | |
91ee8f5c | 517 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long start, |
4046460b | 518 | unsigned long pfn, unsigned long npg, |
7af01450 | 519 | unsigned long lpsize, int warnlvl) |
afd7969a | 520 | { |
4046460b | 521 | pgprotval_t forbidden, res; |
91ee8f5c | 522 | unsigned long end; |
afd7969a | 523 | |
69c31e69 TG |
524 | /* |
525 | * There is no point in checking RW/NX conflicts when the requested | |
526 | * mapping is setting the page !PRESENT. | |
527 | */ | |
528 | if (!(pgprot_val(prot) & _PAGE_PRESENT)) | |
529 | return prot; | |
530 | ||
afd7969a | 531 | /* Operate on the virtual address */ |
91ee8f5c | 532 | end = start + npg * PAGE_SIZE - 1; |
4046460b TG |
533 | |
534 | res = protect_kernel_text(start, end); | |
535 | check_conflict(warnlvl, prot, res, start, end, pfn, "Text NX"); | |
536 | forbidden = res; | |
537 | ||
7af01450 TG |
538 | /* |
539 | * Special case to preserve a large page. If the change spawns the | |
540 | * full large page mapping then there is no point to split it | |
541 | * up. Happens with ftrace and is going to be removed once ftrace | |
542 | * switched to text_poke(). | |
543 | */ | |
544 | if (lpsize != (npg * PAGE_SIZE) || (start & (lpsize - 1))) { | |
545 | res = protect_kernel_text_ro(start, end); | |
546 | check_conflict(warnlvl, prot, res, start, end, pfn, "Text RO"); | |
547 | forbidden |= res; | |
548 | } | |
afd7969a TG |
549 | |
550 | /* Check the PFN directly */ | |
4046460b TG |
551 | res = protect_pci_bios(pfn, pfn + npg - 1); |
552 | check_conflict(warnlvl, prot, res, start, end, pfn, "PCIBIOS NX"); | |
553 | forbidden |= res; | |
554 | ||
555 | res = protect_rodata(pfn, pfn + npg - 1); | |
556 | check_conflict(warnlvl, prot, res, start, end, pfn, "Rodata RO"); | |
557 | forbidden |= res; | |
687c4825 | 558 | |
afd7969a | 559 | return __pgprot(pgprot_val(prot) & ~forbidden); |
687c4825 IM |
560 | } |
561 | ||
426e34cc MF |
562 | /* |
563 | * Lookup the page table entry for a virtual address in a specific pgd. | |
564 | * Return a pointer to the entry and the level of the mapping. | |
565 | */ | |
566 | pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, | |
567 | unsigned int *level) | |
9f4c815c | 568 | { |
45478336 | 569 | p4d_t *p4d; |
1da177e4 LT |
570 | pud_t *pud; |
571 | pmd_t *pmd; | |
9f4c815c | 572 | |
30551bb3 TG |
573 | *level = PG_LEVEL_NONE; |
574 | ||
1da177e4 LT |
575 | if (pgd_none(*pgd)) |
576 | return NULL; | |
9df84993 | 577 | |
45478336 KS |
578 | p4d = p4d_offset(pgd, address); |
579 | if (p4d_none(*p4d)) | |
580 | return NULL; | |
581 | ||
582 | *level = PG_LEVEL_512G; | |
583 | if (p4d_large(*p4d) || !p4d_present(*p4d)) | |
584 | return (pte_t *)p4d; | |
585 | ||
586 | pud = pud_offset(p4d, address); | |
1da177e4 LT |
587 | if (pud_none(*pud)) |
588 | return NULL; | |
c2f71ee2 AK |
589 | |
590 | *level = PG_LEVEL_1G; | |
591 | if (pud_large(*pud) || !pud_present(*pud)) | |
592 | return (pte_t *)pud; | |
593 | ||
1da177e4 LT |
594 | pmd = pmd_offset(pud, address); |
595 | if (pmd_none(*pmd)) | |
596 | return NULL; | |
30551bb3 TG |
597 | |
598 | *level = PG_LEVEL_2M; | |
9a14aefc | 599 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 600 | return (pte_t *)pmd; |
1da177e4 | 601 | |
30551bb3 | 602 | *level = PG_LEVEL_4K; |
9df84993 | 603 | |
9f4c815c IM |
604 | return pte_offset_kernel(pmd, address); |
605 | } | |
0fd64c23 BP |
606 | |
607 | /* | |
608 | * Lookup the page table entry for a virtual address. Return a pointer | |
609 | * to the entry and the level of the mapping. | |
610 | * | |
611 | * Note: We return pud and pmd either when the entry is marked large | |
612 | * or when the present bit is not set. Otherwise we would return a | |
613 | * pointer to a nonexisting mapping. | |
614 | */ | |
615 | pte_t *lookup_address(unsigned long address, unsigned int *level) | |
616 | { | |
8679de09 | 617 | return lookup_address_in_pgd(pgd_offset_k(address), address, level); |
0fd64c23 | 618 | } |
75bb8835 | 619 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 620 | |
0fd64c23 BP |
621 | static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address, |
622 | unsigned int *level) | |
623 | { | |
8679de09 | 624 | if (cpa->pgd) |
426e34cc | 625 | return lookup_address_in_pgd(cpa->pgd + pgd_index(address), |
0fd64c23 BP |
626 | address, level); |
627 | ||
8679de09 | 628 | return lookup_address(address, level); |
0fd64c23 BP |
629 | } |
630 | ||
792230c3 JG |
631 | /* |
632 | * Lookup the PMD entry for a virtual address. Return a pointer to the entry | |
633 | * or NULL if not present. | |
634 | */ | |
635 | pmd_t *lookup_pmd_address(unsigned long address) | |
636 | { | |
637 | pgd_t *pgd; | |
45478336 | 638 | p4d_t *p4d; |
792230c3 JG |
639 | pud_t *pud; |
640 | ||
641 | pgd = pgd_offset_k(address); | |
642 | if (pgd_none(*pgd)) | |
643 | return NULL; | |
644 | ||
45478336 KS |
645 | p4d = p4d_offset(pgd, address); |
646 | if (p4d_none(*p4d) || p4d_large(*p4d) || !p4d_present(*p4d)) | |
647 | return NULL; | |
648 | ||
649 | pud = pud_offset(p4d, address); | |
792230c3 JG |
650 | if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud)) |
651 | return NULL; | |
652 | ||
653 | return pmd_offset(pud, address); | |
654 | } | |
655 | ||
d7656534 DH |
656 | /* |
657 | * This is necessary because __pa() does not work on some | |
658 | * kinds of memory, like vmalloc() or the alloc_remap() | |
659 | * areas on 32-bit NUMA systems. The percpu areas can | |
660 | * end up in this kind of memory, for instance. | |
661 | * | |
662 | * This could be optimized, but it is only intended to be | |
663 | * used at inititalization time, and keeping it | |
664 | * unoptimized should increase the testing coverage for | |
665 | * the more obscure platforms. | |
666 | */ | |
667 | phys_addr_t slow_virt_to_phys(void *__virt_addr) | |
668 | { | |
669 | unsigned long virt_addr = (unsigned long)__virt_addr; | |
bf70e551 DC |
670 | phys_addr_t phys_addr; |
671 | unsigned long offset; | |
d7656534 | 672 | enum pg_level level; |
d7656534 DH |
673 | pte_t *pte; |
674 | ||
675 | pte = lookup_address(virt_addr, &level); | |
676 | BUG_ON(!pte); | |
34437e67 | 677 | |
bf70e551 DC |
678 | /* |
679 | * pXX_pfn() returns unsigned long, which must be cast to phys_addr_t | |
680 | * before being left-shifted PAGE_SHIFT bits -- this trick is to | |
681 | * make 32-PAE kernel work correctly. | |
682 | */ | |
34437e67 TK |
683 | switch (level) { |
684 | case PG_LEVEL_1G: | |
bf70e551 | 685 | phys_addr = (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
686 | offset = virt_addr & ~PUD_PAGE_MASK; |
687 | break; | |
688 | case PG_LEVEL_2M: | |
bf70e551 | 689 | phys_addr = (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
690 | offset = virt_addr & ~PMD_PAGE_MASK; |
691 | break; | |
692 | default: | |
bf70e551 | 693 | phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT; |
34437e67 TK |
694 | offset = virt_addr & ~PAGE_MASK; |
695 | } | |
696 | ||
697 | return (phys_addr_t)(phys_addr | offset); | |
d7656534 DH |
698 | } |
699 | EXPORT_SYMBOL_GPL(slow_virt_to_phys); | |
700 | ||
9df84993 IM |
701 | /* |
702 | * Set the new pmd in all the pgds we know about: | |
703 | */ | |
9a3dc780 | 704 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 705 | { |
9f4c815c IM |
706 | /* change init_mm */ |
707 | set_pte_atomic(kpte, pte); | |
44af6c41 | 708 | #ifdef CONFIG_X86_32 |
e4b71dcf | 709 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
710 | struct page *page; |
711 | ||
e3ed910d | 712 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 | 713 | pgd_t *pgd; |
45478336 | 714 | p4d_t *p4d; |
44af6c41 IM |
715 | pud_t *pud; |
716 | pmd_t *pmd; | |
717 | ||
718 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
45478336 KS |
719 | p4d = p4d_offset(pgd, address); |
720 | pud = pud_offset(p4d, address); | |
44af6c41 IM |
721 | pmd = pmd_offset(pud, address); |
722 | set_pte_atomic((pte_t *)pmd, pte); | |
723 | } | |
1da177e4 | 724 | } |
44af6c41 | 725 | #endif |
1da177e4 LT |
726 | } |
727 | ||
d1440b23 DH |
728 | static pgprot_t pgprot_clear_protnone_bits(pgprot_t prot) |
729 | { | |
730 | /* | |
731 | * _PAGE_GLOBAL means "global page" for present PTEs. | |
732 | * But, it is also used to indicate _PAGE_PROTNONE | |
733 | * for non-present PTEs. | |
734 | * | |
735 | * This ensures that a _PAGE_GLOBAL PTE going from | |
736 | * present to non-present is not confused as | |
737 | * _PAGE_PROTNONE. | |
738 | */ | |
739 | if (!(pgprot_val(prot) & _PAGE_PRESENT)) | |
740 | pgprot_val(prot) &= ~_PAGE_GLOBAL; | |
741 | ||
742 | return prot; | |
743 | } | |
744 | ||
8679de09 TG |
745 | static int __should_split_large_page(pte_t *kpte, unsigned long address, |
746 | struct cpa_data *cpa) | |
65e074df | 747 | { |
585948f4 | 748 | unsigned long numpages, pmask, psize, lpaddr, pfn, old_pfn; |
f61c5ba2 | 749 | pgprot_t old_prot, new_prot, req_prot, chk_prot; |
24c41220 | 750 | pte_t new_pte, *tmp; |
f3c4fbb6 | 751 | enum pg_level level; |
65e074df | 752 | |
65e074df TG |
753 | /* |
754 | * Check for races, another CPU might have split this page | |
755 | * up already: | |
756 | */ | |
82f0712c | 757 | tmp = _lookup_address_cpa(cpa, address, &level); |
65e074df | 758 | if (tmp != kpte) |
8679de09 | 759 | return 1; |
65e074df TG |
760 | |
761 | switch (level) { | |
762 | case PG_LEVEL_2M: | |
3a19109e TK |
763 | old_prot = pmd_pgprot(*(pmd_t *)kpte); |
764 | old_pfn = pmd_pfn(*(pmd_t *)kpte); | |
5c280cf6 | 765 | cpa_inc_2m_checked(); |
3a19109e | 766 | break; |
65e074df | 767 | case PG_LEVEL_1G: |
3a19109e TK |
768 | old_prot = pud_pgprot(*(pud_t *)kpte); |
769 | old_pfn = pud_pfn(*(pud_t *)kpte); | |
5c280cf6 | 770 | cpa_inc_1g_checked(); |
f3c4fbb6 | 771 | break; |
65e074df | 772 | default: |
8679de09 | 773 | return -EINVAL; |
65e074df TG |
774 | } |
775 | ||
3a19109e TK |
776 | psize = page_level_size(level); |
777 | pmask = page_level_mask(level); | |
778 | ||
65e074df TG |
779 | /* |
780 | * Calculate the number of pages, which fit into this large | |
781 | * page starting at address: | |
782 | */ | |
8679de09 TG |
783 | lpaddr = (address + psize) & pmask; |
784 | numpages = (lpaddr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
785 | if (numpages < cpa->numpages) |
786 | cpa->numpages = numpages; | |
65e074df TG |
787 | |
788 | /* | |
789 | * We are safe now. Check whether the new pgprot is the same: | |
f5b2831d JG |
790 | * Convert protection attributes to 4k-format, as cpa->mask* are set |
791 | * up accordingly. | |
65e074df | 792 | */ |
24c41220 | 793 | |
606c7193 | 794 | /* Clear PSE (aka _PAGE_PAT) and move PAT bit to correct position */ |
55696b1f | 795 | req_prot = pgprot_large_2_4k(old_prot); |
65e074df | 796 | |
64edc8ed | 797 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
798 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 | 799 | |
f5b2831d JG |
800 | /* |
801 | * req_prot is in format of 4k pages. It must be converted to large | |
802 | * page format: the caching mode includes the PAT bit located at | |
803 | * different bit positions in the two formats. | |
804 | */ | |
805 | req_prot = pgprot_4k_2_large(req_prot); | |
d1440b23 | 806 | req_prot = pgprot_clear_protnone_bits(req_prot); |
f76cfa3c | 807 | if (pgprot_val(req_prot) & _PAGE_PRESENT) |
d1440b23 | 808 | pgprot_val(req_prot) |= _PAGE_PSE; |
a8aed3e0 | 809 | |
c31c7d48 | 810 | /* |
8679de09 TG |
811 | * old_pfn points to the large page base pfn. So we need to add the |
812 | * offset of the virtual address: | |
c31c7d48 | 813 | */ |
3a19109e | 814 | pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT); |
c31c7d48 TG |
815 | cpa->pfn = pfn; |
816 | ||
8679de09 TG |
817 | /* |
818 | * Calculate the large page base address and the number of 4K pages | |
819 | * in the large page | |
820 | */ | |
821 | lpaddr = address & pmask; | |
822 | numpages = psize >> PAGE_SHIFT; | |
65e074df | 823 | |
f61c5ba2 TG |
824 | /* |
825 | * Sanity check that the existing mapping is correct versus the static | |
826 | * protections. static_protections() guards against !PRESENT, so no | |
827 | * extra conditional required here. | |
828 | */ | |
829 | chk_prot = static_protections(old_prot, lpaddr, old_pfn, numpages, | |
7af01450 | 830 | psize, CPA_CONFLICT); |
f61c5ba2 TG |
831 | |
832 | if (WARN_ON_ONCE(pgprot_val(chk_prot) != pgprot_val(old_prot))) { | |
833 | /* | |
834 | * Split the large page and tell the split code to | |
835 | * enforce static protections. | |
836 | */ | |
837 | cpa->force_static_prot = 1; | |
838 | return 1; | |
839 | } | |
840 | ||
1c4b406e TG |
841 | /* |
842 | * Optimization: If the requested pgprot is the same as the current | |
843 | * pgprot, then the large page can be preserved and no updates are | |
844 | * required independent of alignment and length of the requested | |
845 | * range. The above already established that the current pgprot is | |
846 | * correct, which in consequence makes the requested pgprot correct | |
847 | * as well if it is the same. The static protection scan below will | |
848 | * not come to a different conclusion. | |
849 | */ | |
850 | if (pgprot_val(req_prot) == pgprot_val(old_prot)) { | |
851 | cpa_inc_lp_sameprot(level); | |
852 | return 0; | |
853 | } | |
854 | ||
fac84939 | 855 | /* |
585948f4 | 856 | * If the requested range does not cover the full page, split it up |
9cc9f17a | 857 | */ |
585948f4 TG |
858 | if (address != lpaddr || cpa->numpages != numpages) |
859 | return 1; | |
9cc9f17a TG |
860 | |
861 | /* | |
585948f4 TG |
862 | * Check whether the requested pgprot is conflicting with a static |
863 | * protection requirement in the large page. | |
fac84939 | 864 | */ |
585948f4 | 865 | new_prot = static_protections(req_prot, lpaddr, old_pfn, numpages, |
7af01450 | 866 | psize, CPA_DETECT); |
65e074df TG |
867 | |
868 | /* | |
585948f4 TG |
869 | * If there is a conflict, split the large page. |
870 | * | |
871 | * There used to be a 4k wise evaluation trying really hard to | |
872 | * preserve the large pages, but experimentation has shown, that this | |
873 | * does not help at all. There might be corner cases which would | |
874 | * preserve one large page occasionally, but it's really not worth the | |
875 | * extra code and cycles for the common case. | |
65e074df | 876 | */ |
585948f4 | 877 | if (pgprot_val(req_prot) != pgprot_val(new_prot)) |
8679de09 TG |
878 | return 1; |
879 | ||
880 | /* All checks passed. Update the large page mapping. */ | |
881 | new_pte = pfn_pte(old_pfn, new_prot); | |
882 | __set_pmd_pte(kpte, address, new_pte); | |
883 | cpa->flags |= CPA_FLUSHTLB; | |
5c280cf6 | 884 | cpa_inc_lp_preserved(level); |
8679de09 TG |
885 | return 0; |
886 | } | |
887 | ||
888 | static int should_split_large_page(pte_t *kpte, unsigned long address, | |
889 | struct cpa_data *cpa) | |
890 | { | |
891 | int do_split; | |
892 | ||
893 | if (cpa->force_split) | |
894 | return 1; | |
65e074df | 895 | |
8679de09 TG |
896 | spin_lock(&pgd_lock); |
897 | do_split = __should_split_large_page(kpte, address, cpa); | |
a79e53d8 | 898 | spin_unlock(&pgd_lock); |
9df84993 | 899 | |
beaff633 | 900 | return do_split; |
65e074df TG |
901 | } |
902 | ||
f61c5ba2 TG |
903 | static void split_set_pte(struct cpa_data *cpa, pte_t *pte, unsigned long pfn, |
904 | pgprot_t ref_prot, unsigned long address, | |
905 | unsigned long size) | |
906 | { | |
907 | unsigned int npg = PFN_DOWN(size); | |
908 | pgprot_t prot; | |
909 | ||
910 | /* | |
911 | * If should_split_large_page() discovered an inconsistent mapping, | |
912 | * remove the invalid protection in the split mapping. | |
913 | */ | |
914 | if (!cpa->force_static_prot) | |
915 | goto set; | |
916 | ||
7af01450 TG |
917 | /* Hand in lpsize = 0 to enforce the protection mechanism */ |
918 | prot = static_protections(ref_prot, address, pfn, npg, 0, CPA_PROTECT); | |
f61c5ba2 TG |
919 | |
920 | if (pgprot_val(prot) == pgprot_val(ref_prot)) | |
921 | goto set; | |
922 | ||
923 | /* | |
924 | * If this is splitting a PMD, fix it up. PUD splits cannot be | |
925 | * fixed trivially as that would require to rescan the newly | |
926 | * installed PMD mappings after returning from split_large_page() | |
927 | * so an eventual further split can allocate the necessary PTE | |
928 | * pages. Warn for now and revisit it in case this actually | |
929 | * happens. | |
930 | */ | |
931 | if (size == PAGE_SIZE) | |
932 | ref_prot = prot; | |
933 | else | |
934 | pr_warn_once("CPA: Cannot fixup static protections for PUD split\n"); | |
935 | set: | |
936 | set_pte(pte, pfn_pte(pfn, ref_prot)); | |
937 | } | |
938 | ||
5952886b | 939 | static int |
82f0712c BP |
940 | __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address, |
941 | struct page *base) | |
bb5c2dbd | 942 | { |
f61c5ba2 | 943 | unsigned long lpaddr, lpinc, ref_pfn, pfn, pfninc = 1; |
5952886b | 944 | pte_t *pbase = (pte_t *)page_address(base); |
9df84993 | 945 | unsigned int i, level; |
9df84993 | 946 | pgprot_t ref_prot; |
f61c5ba2 | 947 | pte_t *tmp; |
bb5c2dbd | 948 | |
a79e53d8 | 949 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
950 | /* |
951 | * Check for races, another CPU might have split this page | |
952 | * up for us already: | |
953 | */ | |
82f0712c | 954 | tmp = _lookup_address_cpa(cpa, address, &level); |
ae9aae9e WC |
955 | if (tmp != kpte) { |
956 | spin_unlock(&pgd_lock); | |
957 | return 1; | |
958 | } | |
bb5c2dbd | 959 | |
6944a9c8 | 960 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
f5b2831d | 961 | |
d551aaa2 TK |
962 | switch (level) { |
963 | case PG_LEVEL_2M: | |
964 | ref_prot = pmd_pgprot(*(pmd_t *)kpte); | |
606c7193 DH |
965 | /* |
966 | * Clear PSE (aka _PAGE_PAT) and move | |
967 | * PAT bit to correct position. | |
968 | */ | |
f5b2831d | 969 | ref_prot = pgprot_large_2_4k(ref_prot); |
d551aaa2 | 970 | ref_pfn = pmd_pfn(*(pmd_t *)kpte); |
f61c5ba2 TG |
971 | lpaddr = address & PMD_MASK; |
972 | lpinc = PAGE_SIZE; | |
d551aaa2 | 973 | break; |
bb5c2dbd | 974 | |
d551aaa2 TK |
975 | case PG_LEVEL_1G: |
976 | ref_prot = pud_pgprot(*(pud_t *)kpte); | |
977 | ref_pfn = pud_pfn(*(pud_t *)kpte); | |
f07333fd | 978 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; |
f61c5ba2 TG |
979 | lpaddr = address & PUD_MASK; |
980 | lpinc = PMD_SIZE; | |
a8aed3e0 | 981 | /* |
d551aaa2 | 982 | * Clear the PSE flags if the PRESENT flag is not set |
a8aed3e0 AA |
983 | * otherwise pmd_present/pmd_huge will return true |
984 | * even on a non present pmd. | |
985 | */ | |
d551aaa2 | 986 | if (!(pgprot_val(ref_prot) & _PAGE_PRESENT)) |
a8aed3e0 | 987 | pgprot_val(ref_prot) &= ~_PAGE_PSE; |
d551aaa2 TK |
988 | break; |
989 | ||
990 | default: | |
991 | spin_unlock(&pgd_lock); | |
992 | return 1; | |
f07333fd | 993 | } |
f07333fd | 994 | |
d1440b23 | 995 | ref_prot = pgprot_clear_protnone_bits(ref_prot); |
a8aed3e0 | 996 | |
63c1dcf4 TG |
997 | /* |
998 | * Get the target pfn from the original entry: | |
999 | */ | |
d551aaa2 | 1000 | pfn = ref_pfn; |
f61c5ba2 TG |
1001 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc, lpaddr += lpinc) |
1002 | split_set_pte(cpa, pbase + i, pfn, ref_prot, lpaddr, lpinc); | |
bb5c2dbd | 1003 | |
2c66e24d SP |
1004 | if (virt_addr_valid(address)) { |
1005 | unsigned long pfn = PFN_DOWN(__pa(address)); | |
1006 | ||
1007 | if (pfn_range_is_mapped(pfn, pfn + 1)) | |
1008 | split_page_count(level); | |
1009 | } | |
f361a450 | 1010 | |
bb5c2dbd | 1011 | /* |
07a66d7c | 1012 | * Install the new, split up pagetable. |
4c881ca1 | 1013 | * |
07a66d7c IM |
1014 | * We use the standard kernel pagetable protections for the new |
1015 | * pagetable protections, the actual ptes set above control the | |
1016 | * primary protection behavior: | |
bb5c2dbd | 1017 | */ |
07a66d7c | 1018 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
1019 | |
1020 | /* | |
c0a759ab PZ |
1021 | * Do a global flush tlb after splitting the large page |
1022 | * and before we do the actual change page attribute in the PTE. | |
211b3d03 | 1023 | * |
c0a759ab PZ |
1024 | * Without this, we violate the TLB application note, that says: |
1025 | * "The TLBs may contain both ordinary and large-page | |
1026 | * translations for a 4-KByte range of linear addresses. This | |
1027 | * may occur if software modifies the paging structures so that | |
1028 | * the page size used for the address range changes. If the two | |
1029 | * translations differ with respect to page frame or attributes | |
1030 | * (e.g., permissions), processor behavior is undefined and may | |
1031 | * be implementation-specific." | |
1032 | * | |
1033 | * We do this global tlb flush inside the cpa_lock, so that we | |
1034 | * don't allow any other cpu, with stale tlb entries change the | |
1035 | * page attribute in parallel, that also falls into the | |
1036 | * just split large page entry. | |
211b3d03 | 1037 | */ |
c0a759ab | 1038 | flush_tlb_all(); |
ae9aae9e | 1039 | spin_unlock(&pgd_lock); |
211b3d03 | 1040 | |
ae9aae9e WC |
1041 | return 0; |
1042 | } | |
bb5c2dbd | 1043 | |
82f0712c BP |
1044 | static int split_large_page(struct cpa_data *cpa, pte_t *kpte, |
1045 | unsigned long address) | |
ae9aae9e | 1046 | { |
ae9aae9e WC |
1047 | struct page *base; |
1048 | ||
288cf3c6 | 1049 | if (!debug_pagealloc_enabled()) |
ae9aae9e | 1050 | spin_unlock(&cpa_lock); |
75f296d9 | 1051 | base = alloc_pages(GFP_KERNEL, 0); |
288cf3c6 | 1052 | if (!debug_pagealloc_enabled()) |
ae9aae9e WC |
1053 | spin_lock(&cpa_lock); |
1054 | if (!base) | |
1055 | return -ENOMEM; | |
1056 | ||
82f0712c | 1057 | if (__split_large_page(cpa, kpte, address, base)) |
8311eb84 | 1058 | __free_page(base); |
bb5c2dbd | 1059 | |
bb5c2dbd IM |
1060 | return 0; |
1061 | } | |
1062 | ||
52a628fb BP |
1063 | static bool try_to_free_pte_page(pte_t *pte) |
1064 | { | |
1065 | int i; | |
1066 | ||
1067 | for (i = 0; i < PTRS_PER_PTE; i++) | |
1068 | if (!pte_none(pte[i])) | |
1069 | return false; | |
1070 | ||
1071 | free_page((unsigned long)pte); | |
1072 | return true; | |
1073 | } | |
1074 | ||
1075 | static bool try_to_free_pmd_page(pmd_t *pmd) | |
1076 | { | |
1077 | int i; | |
1078 | ||
1079 | for (i = 0; i < PTRS_PER_PMD; i++) | |
1080 | if (!pmd_none(pmd[i])) | |
1081 | return false; | |
1082 | ||
1083 | free_page((unsigned long)pmd); | |
1084 | return true; | |
1085 | } | |
1086 | ||
1087 | static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end) | |
1088 | { | |
1089 | pte_t *pte = pte_offset_kernel(pmd, start); | |
1090 | ||
1091 | while (start < end) { | |
1092 | set_pte(pte, __pte(0)); | |
1093 | ||
1094 | start += PAGE_SIZE; | |
1095 | pte++; | |
1096 | } | |
1097 | ||
1098 | if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) { | |
1099 | pmd_clear(pmd); | |
1100 | return true; | |
1101 | } | |
1102 | return false; | |
1103 | } | |
1104 | ||
1105 | static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd, | |
1106 | unsigned long start, unsigned long end) | |
1107 | { | |
1108 | if (unmap_pte_range(pmd, start, end)) | |
1109 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
1110 | pud_clear(pud); | |
1111 | } | |
1112 | ||
1113 | static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end) | |
1114 | { | |
1115 | pmd_t *pmd = pmd_offset(pud, start); | |
1116 | ||
1117 | /* | |
1118 | * Not on a 2MB page boundary? | |
1119 | */ | |
1120 | if (start & (PMD_SIZE - 1)) { | |
1121 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
1122 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
1123 | ||
1124 | __unmap_pmd_range(pud, pmd, start, pre_end); | |
1125 | ||
1126 | start = pre_end; | |
1127 | pmd++; | |
1128 | } | |
1129 | ||
1130 | /* | |
1131 | * Try to unmap in 2M chunks. | |
1132 | */ | |
1133 | while (end - start >= PMD_SIZE) { | |
1134 | if (pmd_large(*pmd)) | |
1135 | pmd_clear(pmd); | |
1136 | else | |
1137 | __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE); | |
1138 | ||
1139 | start += PMD_SIZE; | |
1140 | pmd++; | |
1141 | } | |
1142 | ||
1143 | /* | |
1144 | * 4K leftovers? | |
1145 | */ | |
1146 | if (start < end) | |
1147 | return __unmap_pmd_range(pud, pmd, start, end); | |
1148 | ||
1149 | /* | |
1150 | * Try again to free the PMD page if haven't succeeded above. | |
1151 | */ | |
1152 | if (!pud_none(*pud)) | |
1153 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
1154 | pud_clear(pud); | |
1155 | } | |
0bb8aeee | 1156 | |
45478336 | 1157 | static void unmap_pud_range(p4d_t *p4d, unsigned long start, unsigned long end) |
0bb8aeee | 1158 | { |
45478336 | 1159 | pud_t *pud = pud_offset(p4d, start); |
0bb8aeee BP |
1160 | |
1161 | /* | |
1162 | * Not on a GB page boundary? | |
1163 | */ | |
1164 | if (start & (PUD_SIZE - 1)) { | |
1165 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
1166 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
1167 | ||
1168 | unmap_pmd_range(pud, start, pre_end); | |
1169 | ||
1170 | start = pre_end; | |
1171 | pud++; | |
1172 | } | |
1173 | ||
1174 | /* | |
1175 | * Try to unmap in 1G chunks? | |
1176 | */ | |
1177 | while (end - start >= PUD_SIZE) { | |
1178 | ||
1179 | if (pud_large(*pud)) | |
1180 | pud_clear(pud); | |
1181 | else | |
1182 | unmap_pmd_range(pud, start, start + PUD_SIZE); | |
1183 | ||
1184 | start += PUD_SIZE; | |
1185 | pud++; | |
1186 | } | |
1187 | ||
1188 | /* | |
1189 | * 2M leftovers? | |
1190 | */ | |
1191 | if (start < end) | |
1192 | unmap_pmd_range(pud, start, end); | |
1193 | ||
1194 | /* | |
1195 | * No need to try to free the PUD page because we'll free it in | |
1196 | * populate_pgd's error path | |
1197 | */ | |
1198 | } | |
1199 | ||
f900a4b8 BP |
1200 | static int alloc_pte_page(pmd_t *pmd) |
1201 | { | |
75f296d9 | 1202 | pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL); |
f900a4b8 BP |
1203 | if (!pte) |
1204 | return -1; | |
1205 | ||
1206 | set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE)); | |
1207 | return 0; | |
1208 | } | |
1209 | ||
4b23538d BP |
1210 | static int alloc_pmd_page(pud_t *pud) |
1211 | { | |
75f296d9 | 1212 | pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL); |
4b23538d BP |
1213 | if (!pmd) |
1214 | return -1; | |
1215 | ||
1216 | set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); | |
1217 | return 0; | |
1218 | } | |
1219 | ||
c6b6f363 BP |
1220 | static void populate_pte(struct cpa_data *cpa, |
1221 | unsigned long start, unsigned long end, | |
1222 | unsigned num_pages, pmd_t *pmd, pgprot_t pgprot) | |
1223 | { | |
1224 | pte_t *pte; | |
1225 | ||
1226 | pte = pte_offset_kernel(pmd, start); | |
1227 | ||
d1440b23 | 1228 | pgprot = pgprot_clear_protnone_bits(pgprot); |
c6b6f363 | 1229 | |
c6b6f363 | 1230 | while (num_pages-- && start < end) { |
edc3b912 | 1231 | set_pte(pte, pfn_pte(cpa->pfn, pgprot)); |
c6b6f363 BP |
1232 | |
1233 | start += PAGE_SIZE; | |
edc3b912 | 1234 | cpa->pfn++; |
c6b6f363 BP |
1235 | pte++; |
1236 | } | |
1237 | } | |
f900a4b8 | 1238 | |
e535ec08 MF |
1239 | static long populate_pmd(struct cpa_data *cpa, |
1240 | unsigned long start, unsigned long end, | |
1241 | unsigned num_pages, pud_t *pud, pgprot_t pgprot) | |
f900a4b8 | 1242 | { |
e535ec08 | 1243 | long cur_pages = 0; |
f900a4b8 | 1244 | pmd_t *pmd; |
f5b2831d | 1245 | pgprot_t pmd_pgprot; |
f900a4b8 BP |
1246 | |
1247 | /* | |
1248 | * Not on a 2M boundary? | |
1249 | */ | |
1250 | if (start & (PMD_SIZE - 1)) { | |
1251 | unsigned long pre_end = start + (num_pages << PAGE_SHIFT); | |
1252 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
1253 | ||
1254 | pre_end = min_t(unsigned long, pre_end, next_page); | |
1255 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
1256 | cur_pages = min_t(unsigned int, num_pages, cur_pages); | |
1257 | ||
1258 | /* | |
1259 | * Need a PTE page? | |
1260 | */ | |
1261 | pmd = pmd_offset(pud, start); | |
1262 | if (pmd_none(*pmd)) | |
1263 | if (alloc_pte_page(pmd)) | |
1264 | return -1; | |
1265 | ||
1266 | populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot); | |
1267 | ||
1268 | start = pre_end; | |
1269 | } | |
1270 | ||
1271 | /* | |
1272 | * We mapped them all? | |
1273 | */ | |
1274 | if (num_pages == cur_pages) | |
1275 | return cur_pages; | |
1276 | ||
f5b2831d JG |
1277 | pmd_pgprot = pgprot_4k_2_large(pgprot); |
1278 | ||
f900a4b8 BP |
1279 | while (end - start >= PMD_SIZE) { |
1280 | ||
1281 | /* | |
1282 | * We cannot use a 1G page so allocate a PMD page if needed. | |
1283 | */ | |
1284 | if (pud_none(*pud)) | |
1285 | if (alloc_pmd_page(pud)) | |
1286 | return -1; | |
1287 | ||
1288 | pmd = pmd_offset(pud, start); | |
1289 | ||
958f79b9 AK |
1290 | set_pmd(pmd, pmd_mkhuge(pfn_pmd(cpa->pfn, |
1291 | canon_pgprot(pmd_pgprot)))); | |
f900a4b8 BP |
1292 | |
1293 | start += PMD_SIZE; | |
edc3b912 | 1294 | cpa->pfn += PMD_SIZE >> PAGE_SHIFT; |
f900a4b8 BP |
1295 | cur_pages += PMD_SIZE >> PAGE_SHIFT; |
1296 | } | |
1297 | ||
1298 | /* | |
1299 | * Map trailing 4K pages. | |
1300 | */ | |
1301 | if (start < end) { | |
1302 | pmd = pmd_offset(pud, start); | |
1303 | if (pmd_none(*pmd)) | |
1304 | if (alloc_pte_page(pmd)) | |
1305 | return -1; | |
1306 | ||
1307 | populate_pte(cpa, start, end, num_pages - cur_pages, | |
1308 | pmd, pgprot); | |
1309 | } | |
1310 | return num_pages; | |
1311 | } | |
4b23538d | 1312 | |
45478336 KS |
1313 | static int populate_pud(struct cpa_data *cpa, unsigned long start, p4d_t *p4d, |
1314 | pgprot_t pgprot) | |
4b23538d BP |
1315 | { |
1316 | pud_t *pud; | |
1317 | unsigned long end; | |
e535ec08 | 1318 | long cur_pages = 0; |
f5b2831d | 1319 | pgprot_t pud_pgprot; |
4b23538d BP |
1320 | |
1321 | end = start + (cpa->numpages << PAGE_SHIFT); | |
1322 | ||
1323 | /* | |
1324 | * Not on a Gb page boundary? => map everything up to it with | |
1325 | * smaller pages. | |
1326 | */ | |
1327 | if (start & (PUD_SIZE - 1)) { | |
1328 | unsigned long pre_end; | |
1329 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
1330 | ||
1331 | pre_end = min_t(unsigned long, end, next_page); | |
1332 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
1333 | cur_pages = min_t(int, (int)cpa->numpages, cur_pages); | |
1334 | ||
45478336 | 1335 | pud = pud_offset(p4d, start); |
4b23538d BP |
1336 | |
1337 | /* | |
1338 | * Need a PMD page? | |
1339 | */ | |
1340 | if (pud_none(*pud)) | |
1341 | if (alloc_pmd_page(pud)) | |
1342 | return -1; | |
1343 | ||
1344 | cur_pages = populate_pmd(cpa, start, pre_end, cur_pages, | |
1345 | pud, pgprot); | |
1346 | if (cur_pages < 0) | |
1347 | return cur_pages; | |
1348 | ||
1349 | start = pre_end; | |
1350 | } | |
1351 | ||
1352 | /* We mapped them all? */ | |
1353 | if (cpa->numpages == cur_pages) | |
1354 | return cur_pages; | |
1355 | ||
45478336 | 1356 | pud = pud_offset(p4d, start); |
f5b2831d | 1357 | pud_pgprot = pgprot_4k_2_large(pgprot); |
4b23538d BP |
1358 | |
1359 | /* | |
1360 | * Map everything starting from the Gb boundary, possibly with 1G pages | |
1361 | */ | |
b8291adc | 1362 | while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) { |
958f79b9 AK |
1363 | set_pud(pud, pud_mkhuge(pfn_pud(cpa->pfn, |
1364 | canon_pgprot(pud_pgprot)))); | |
4b23538d BP |
1365 | |
1366 | start += PUD_SIZE; | |
edc3b912 | 1367 | cpa->pfn += PUD_SIZE >> PAGE_SHIFT; |
4b23538d BP |
1368 | cur_pages += PUD_SIZE >> PAGE_SHIFT; |
1369 | pud++; | |
1370 | } | |
1371 | ||
1372 | /* Map trailing leftover */ | |
1373 | if (start < end) { | |
e535ec08 | 1374 | long tmp; |
4b23538d | 1375 | |
45478336 | 1376 | pud = pud_offset(p4d, start); |
4b23538d BP |
1377 | if (pud_none(*pud)) |
1378 | if (alloc_pmd_page(pud)) | |
1379 | return -1; | |
1380 | ||
1381 | tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages, | |
1382 | pud, pgprot); | |
1383 | if (tmp < 0) | |
1384 | return cur_pages; | |
1385 | ||
1386 | cur_pages += tmp; | |
1387 | } | |
1388 | return cur_pages; | |
1389 | } | |
f3f72966 BP |
1390 | |
1391 | /* | |
1392 | * Restrictions for kernel page table do not necessarily apply when mapping in | |
1393 | * an alternate PGD. | |
1394 | */ | |
1395 | static int populate_pgd(struct cpa_data *cpa, unsigned long addr) | |
1396 | { | |
1397 | pgprot_t pgprot = __pgprot(_KERNPG_TABLE); | |
f3f72966 | 1398 | pud_t *pud = NULL; /* shut up gcc */ |
45478336 | 1399 | p4d_t *p4d; |
42a54772 | 1400 | pgd_t *pgd_entry; |
e535ec08 | 1401 | long ret; |
f3f72966 BP |
1402 | |
1403 | pgd_entry = cpa->pgd + pgd_index(addr); | |
1404 | ||
45478336 | 1405 | if (pgd_none(*pgd_entry)) { |
75f296d9 | 1406 | p4d = (p4d_t *)get_zeroed_page(GFP_KERNEL); |
45478336 KS |
1407 | if (!p4d) |
1408 | return -1; | |
1409 | ||
1410 | set_pgd(pgd_entry, __pgd(__pa(p4d) | _KERNPG_TABLE)); | |
1411 | } | |
1412 | ||
f3f72966 BP |
1413 | /* |
1414 | * Allocate a PUD page and hand it down for mapping. | |
1415 | */ | |
45478336 KS |
1416 | p4d = p4d_offset(pgd_entry, addr); |
1417 | if (p4d_none(*p4d)) { | |
75f296d9 | 1418 | pud = (pud_t *)get_zeroed_page(GFP_KERNEL); |
f3f72966 BP |
1419 | if (!pud) |
1420 | return -1; | |
530dd8d4 | 1421 | |
45478336 | 1422 | set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE)); |
f3f72966 BP |
1423 | } |
1424 | ||
1425 | pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr); | |
1426 | pgprot_val(pgprot) |= pgprot_val(cpa->mask_set); | |
1427 | ||
45478336 | 1428 | ret = populate_pud(cpa, addr, p4d, pgprot); |
0bb8aeee | 1429 | if (ret < 0) { |
55920d31 AL |
1430 | /* |
1431 | * Leave the PUD page in place in case some other CPU or thread | |
1432 | * already found it, but remove any useless entries we just | |
1433 | * added to it. | |
1434 | */ | |
45478336 | 1435 | unmap_pud_range(p4d, addr, |
0bb8aeee | 1436 | addr + (cpa->numpages << PAGE_SHIFT)); |
f3f72966 | 1437 | return ret; |
0bb8aeee | 1438 | } |
42a54772 | 1439 | |
f3f72966 BP |
1440 | cpa->numpages = ret; |
1441 | return 0; | |
1442 | } | |
1443 | ||
a1e46212 SS |
1444 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
1445 | int primary) | |
1446 | { | |
7fc8442f MF |
1447 | if (cpa->pgd) { |
1448 | /* | |
1449 | * Right now, we only execute this code path when mapping | |
1450 | * the EFI virtual memory map regions, no other users | |
1451 | * provide a ->pgd value. This may change in the future. | |
1452 | */ | |
82f0712c | 1453 | return populate_pgd(cpa, vaddr); |
7fc8442f | 1454 | } |
82f0712c | 1455 | |
a1e46212 SS |
1456 | /* |
1457 | * Ignore all non primary paths. | |
1458 | */ | |
405e1133 JB |
1459 | if (!primary) { |
1460 | cpa->numpages = 1; | |
a1e46212 | 1461 | return 0; |
405e1133 | 1462 | } |
a1e46212 SS |
1463 | |
1464 | /* | |
1465 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
1466 | * to have holes. | |
1467 | * Also set numpages to '1' indicating that we processed cpa req for | |
1468 | * one virtual address page and its pfn. TBD: numpages can be set based | |
1469 | * on the initial value and the level returned by lookup_address(). | |
1470 | */ | |
1471 | if (within(vaddr, PAGE_OFFSET, | |
1472 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
1473 | cpa->numpages = 1; | |
1474 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
1475 | return 0; | |
58e65b51 DH |
1476 | |
1477 | } else if (__cpa_pfn_in_highmap(cpa->pfn)) { | |
1478 | /* Faults in the highmap are OK, so do not warn: */ | |
1479 | return -EFAULT; | |
a1e46212 SS |
1480 | } else { |
1481 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
1482 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
1483 | *cpa->vaddr); | |
1484 | ||
1485 | return -EFAULT; | |
1486 | } | |
1487 | } | |
1488 | ||
c31c7d48 | 1489 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 1490 | { |
d75586ad | 1491 | unsigned long address; |
da7bfc50 HH |
1492 | int do_split, err; |
1493 | unsigned int level; | |
c31c7d48 | 1494 | pte_t *kpte, old_pte; |
1da177e4 | 1495 | |
16ebf031 | 1496 | address = __cpa_addr(cpa, cpa->curpage); |
97f99fed | 1497 | repeat: |
82f0712c | 1498 | kpte = _lookup_address_cpa(cpa, address, &level); |
1da177e4 | 1499 | if (!kpte) |
a1e46212 | 1500 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
1501 | |
1502 | old_pte = *kpte; | |
dcb32d99 | 1503 | if (pte_none(old_pte)) |
a1e46212 | 1504 | return __cpa_process_fault(cpa, address, primary); |
9f4c815c | 1505 | |
30551bb3 | 1506 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 1507 | pte_t new_pte; |
626c2c9d | 1508 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 1509 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 1510 | |
72e458df TG |
1511 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
1512 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 1513 | |
5c280cf6 | 1514 | cpa_inc_4k_install(); |
7af01450 TG |
1515 | /* Hand in lpsize = 0 to enforce the protection mechanism */ |
1516 | new_prot = static_protections(new_prot, address, pfn, 1, 0, | |
4046460b | 1517 | CPA_PROTECT); |
86f03989 | 1518 | |
d1440b23 | 1519 | new_prot = pgprot_clear_protnone_bits(new_prot); |
a8aed3e0 | 1520 | |
626c2c9d AV |
1521 | /* |
1522 | * We need to keep the pfn from the existing PTE, | |
1523 | * after all we're only going to change it's attributes | |
1524 | * not the memory it points to | |
1525 | */ | |
1a54420a | 1526 | new_pte = pfn_pte(pfn, new_prot); |
c31c7d48 | 1527 | cpa->pfn = pfn; |
f4ae5da0 TG |
1528 | /* |
1529 | * Do we really change anything ? | |
1530 | */ | |
1531 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
1532 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 1533 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 1534 | } |
9b5cf48b | 1535 | cpa->numpages = 1; |
65e074df | 1536 | return 0; |
1da177e4 | 1537 | } |
65e074df TG |
1538 | |
1539 | /* | |
1540 | * Check, whether we can keep the large page intact | |
1541 | * and just change the pte: | |
1542 | */ | |
8679de09 | 1543 | do_split = should_split_large_page(kpte, address, cpa); |
65e074df TG |
1544 | /* |
1545 | * When the range fits into the existing large page, | |
9b5cf48b | 1546 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
1547 | * try_large_page: |
1548 | */ | |
87f7f8fe IM |
1549 | if (do_split <= 0) |
1550 | return do_split; | |
65e074df TG |
1551 | |
1552 | /* | |
1553 | * We have to split the large page: | |
1554 | */ | |
82f0712c | 1555 | err = split_large_page(cpa, kpte, address); |
c0a759ab | 1556 | if (!err) |
87f7f8fe | 1557 | goto repeat; |
beaff633 | 1558 | |
87f7f8fe | 1559 | return err; |
9f4c815c | 1560 | } |
1da177e4 | 1561 | |
c31c7d48 TG |
1562 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
1563 | ||
1564 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 1565 | { |
c31c7d48 | 1566 | struct cpa_data alias_cpa; |
992f4c1c | 1567 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 1568 | unsigned long vaddr; |
992f4c1c | 1569 | int ret; |
44af6c41 | 1570 | |
8eb5779f | 1571 | if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1)) |
c31c7d48 | 1572 | return 0; |
626c2c9d | 1573 | |
f34b439f TG |
1574 | /* |
1575 | * No need to redo, when the primary call touched the direct | |
1576 | * mapping already: | |
1577 | */ | |
16ebf031 | 1578 | vaddr = __cpa_addr(cpa, cpa->curpage); |
d75586ad | 1579 | if (!(within(vaddr, PAGE_OFFSET, |
a1e46212 | 1580 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 1581 | |
f34b439f | 1582 | alias_cpa = *cpa; |
992f4c1c | 1583 | alias_cpa.vaddr = &laddr; |
9ae28475 | 1584 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
98bfc9b0 | 1585 | alias_cpa.curpage = 0; |
d75586ad | 1586 | |
f34b439f | 1587 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
1588 | if (ret) |
1589 | return ret; | |
f34b439f | 1590 | } |
44af6c41 | 1591 | |
44af6c41 | 1592 | #ifdef CONFIG_X86_64 |
488fd995 | 1593 | /* |
992f4c1c TH |
1594 | * If the primary call didn't touch the high mapping already |
1595 | * and the physical address is inside the kernel map, we need | |
0879750f | 1596 | * to touch the high mapped kernel as well: |
488fd995 | 1597 | */ |
992f4c1c | 1598 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
58e65b51 | 1599 | __cpa_pfn_in_highmap(cpa->pfn)) { |
992f4c1c TH |
1600 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + |
1601 | __START_KERNEL_map - phys_base; | |
1602 | alias_cpa = *cpa; | |
1603 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
1604 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
98bfc9b0 | 1605 | alias_cpa.curpage = 0; |
c31c7d48 | 1606 | |
992f4c1c TH |
1607 | /* |
1608 | * The high mapping range is imprecise, so ignore the | |
1609 | * return value. | |
1610 | */ | |
1611 | __change_page_attr_set_clr(&alias_cpa, 0); | |
1612 | } | |
488fd995 | 1613 | #endif |
992f4c1c TH |
1614 | |
1615 | return 0; | |
1da177e4 LT |
1616 | } |
1617 | ||
c31c7d48 | 1618 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 1619 | { |
e535ec08 | 1620 | unsigned long numpages = cpa->numpages; |
83b4e391 PZ |
1621 | unsigned long rempages = numpages; |
1622 | int ret = 0; | |
ff31452b | 1623 | |
83b4e391 | 1624 | while (rempages) { |
65e074df TG |
1625 | /* |
1626 | * Store the remaining nr of pages for the large page | |
1627 | * preservation check. | |
1628 | */ | |
83b4e391 | 1629 | cpa->numpages = rempages; |
d75586ad | 1630 | /* for array changes, we can't use large page */ |
9ae28475 | 1631 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 1632 | cpa->numpages = 1; |
c31c7d48 | 1633 | |
288cf3c6 | 1634 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1635 | spin_lock(&cpa_lock); |
c31c7d48 | 1636 | ret = __change_page_attr(cpa, checkalias); |
288cf3c6 | 1637 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1638 | spin_unlock(&cpa_lock); |
ff31452b | 1639 | if (ret) |
83b4e391 | 1640 | goto out; |
ff31452b | 1641 | |
c31c7d48 TG |
1642 | if (checkalias) { |
1643 | ret = cpa_process_alias(cpa); | |
1644 | if (ret) | |
83b4e391 | 1645 | goto out; |
c31c7d48 TG |
1646 | } |
1647 | ||
65e074df TG |
1648 | /* |
1649 | * Adjust the number of pages with the result of the | |
1650 | * CPA operation. Either a large page has been | |
1651 | * preserved or a single page update happened. | |
1652 | */ | |
83b4e391 PZ |
1653 | BUG_ON(cpa->numpages > rempages || !cpa->numpages); |
1654 | rempages -= cpa->numpages; | |
98bfc9b0 | 1655 | cpa->curpage += cpa->numpages; |
65e074df | 1656 | } |
83b4e391 PZ |
1657 | |
1658 | out: | |
1659 | /* Restore the original numpages */ | |
1660 | cpa->numpages = numpages; | |
1661 | return ret; | |
ff31452b TG |
1662 | } |
1663 | ||
d75586ad | 1664 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 1665 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 1666 | int force_split, int in_flag, |
1667 | struct page **pages) | |
ff31452b | 1668 | { |
72e458df | 1669 | struct cpa_data cpa; |
cacf8906 | 1670 | int ret, cache, checkalias; |
331e4065 | 1671 | |
82f0712c BP |
1672 | memset(&cpa, 0, sizeof(cpa)); |
1673 | ||
331e4065 | 1674 | /* |
39114b7a DH |
1675 | * Check, if we are requested to set a not supported |
1676 | * feature. Clearing non-supported features is OK. | |
331e4065 TG |
1677 | */ |
1678 | mask_set = canon_pgprot(mask_set); | |
39114b7a | 1679 | |
c9caa02c | 1680 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
1681 | return 0; |
1682 | ||
69b1415e | 1683 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 1684 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
1685 | int i; |
1686 | for (i = 0; i < numpages; i++) { | |
1687 | if (addr[i] & ~PAGE_MASK) { | |
1688 | addr[i] &= PAGE_MASK; | |
1689 | WARN_ON_ONCE(1); | |
1690 | } | |
1691 | } | |
9ae28475 | 1692 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
1693 | /* | |
1694 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
a97673a1 | 1695 | * No need to check in that case |
9ae28475 | 1696 | */ |
1697 | if (*addr & ~PAGE_MASK) { | |
1698 | *addr &= PAGE_MASK; | |
1699 | /* | |
1700 | * People should not be passing in unaligned addresses: | |
1701 | */ | |
1702 | WARN_ON_ONCE(1); | |
1703 | } | |
69b1415e TG |
1704 | } |
1705 | ||
5843d9a4 NP |
1706 | /* Must avoid aliasing mappings in the highmem code */ |
1707 | kmap_flush_unused(); | |
1708 | ||
db64fe02 NP |
1709 | vm_unmap_aliases(); |
1710 | ||
72e458df | 1711 | cpa.vaddr = addr; |
9ae28475 | 1712 | cpa.pages = pages; |
72e458df TG |
1713 | cpa.numpages = numpages; |
1714 | cpa.mask_set = mask_set; | |
1715 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
1716 | cpa.flags = 0; |
1717 | cpa.curpage = 0; | |
c9caa02c | 1718 | cpa.force_split = force_split; |
72e458df | 1719 | |
9ae28475 | 1720 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
1721 | cpa.flags |= in_flag; | |
d75586ad | 1722 | |
af96e443 TG |
1723 | /* No alias checking for _NX bit modifications */ |
1724 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
c40a56a7 DH |
1725 | /* Has caller explicitly disabled alias checking? */ |
1726 | if (in_flag & CPA_NO_CHECK_ALIAS) | |
1727 | checkalias = 0; | |
af96e443 TG |
1728 | |
1729 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 1730 | |
f4ae5da0 TG |
1731 | /* |
1732 | * Check whether we really changed something: | |
1733 | */ | |
d75586ad | 1734 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 1735 | goto out; |
cacf8906 | 1736 | |
6bb8383b AK |
1737 | /* |
1738 | * No need to flush, when we did not set any of the caching | |
1739 | * attributes: | |
1740 | */ | |
c06814d8 | 1741 | cache = !!pgprot2cachemode(mask_set); |
6bb8383b | 1742 | |
57a6a46a | 1743 | /* |
fce2ce95 | 1744 | * On error; flush everything to be sure. |
57a6a46a | 1745 | */ |
fce2ce95 | 1746 | if (ret) { |
6bb8383b | 1747 | cpa_flush_all(cache); |
fce2ce95 PZ |
1748 | goto out; |
1749 | } | |
1750 | ||
fe0937b2 | 1751 | cpa_flush(&cpa, cache); |
76ebd054 | 1752 | out: |
ff31452b TG |
1753 | return ret; |
1754 | } | |
1755 | ||
d75586ad SL |
1756 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
1757 | pgprot_t mask, int array) | |
75cbade8 | 1758 | { |
d75586ad | 1759 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 1760 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
1761 | } |
1762 | ||
d75586ad SL |
1763 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
1764 | pgprot_t mask, int array) | |
72932c7a | 1765 | { |
d75586ad | 1766 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 1767 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
1768 | } |
1769 | ||
0f350755 | 1770 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
1771 | pgprot_t mask) | |
1772 | { | |
1773 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
1774 | CPA_PAGES_ARRAY, pages); | |
1775 | } | |
1776 | ||
1777 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
1778 | pgprot_t mask) | |
1779 | { | |
1780 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
1781 | CPA_PAGES_ARRAY, pages); | |
1782 | } | |
1783 | ||
1219333d | 1784 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 1785 | { |
de33c442 SS |
1786 | /* |
1787 | * for now UC MINUS. see comments in ioremap_nocache() | |
e4b6be33 LR |
1788 | * If you really need strong UC use ioremap_uc(), but note |
1789 | * that you cannot override IO areas with set_memory_*() as | |
1790 | * these helpers cannot work with IO memory. | |
de33c442 | 1791 | */ |
d75586ad | 1792 | return change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1793 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1794 | 0); | |
75cbade8 | 1795 | } |
1219333d | 1796 | |
1797 | int set_memory_uc(unsigned long addr, int numpages) | |
1798 | { | |
9fa3ab39 | 1799 | int ret; |
1800 | ||
de33c442 SS |
1801 | /* |
1802 | * for now UC MINUS. see comments in ioremap_nocache() | |
1803 | */ | |
9fa3ab39 | 1804 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1805 | _PAGE_CACHE_MODE_UC_MINUS, NULL); |
9fa3ab39 | 1806 | if (ret) |
1807 | goto out_err; | |
1808 | ||
1809 | ret = _set_memory_uc(addr, numpages); | |
1810 | if (ret) | |
1811 | goto out_free; | |
1812 | ||
1813 | return 0; | |
1219333d | 1814 | |
9fa3ab39 | 1815 | out_free: |
1816 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1817 | out_err: | |
1818 | return ret; | |
1219333d | 1819 | } |
75cbade8 AV |
1820 | EXPORT_SYMBOL(set_memory_uc); |
1821 | ||
ef354af4 | 1822 | int _set_memory_wc(unsigned long addr, int numpages) |
1823 | { | |
3869c4aa | 1824 | int ret; |
bdc6340f | 1825 | |
3869c4aa | 1826 | ret = change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1827 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1828 | 0); | |
3869c4aa | 1829 | if (!ret) { |
5fe26b7a PZ |
1830 | ret = change_page_attr_set_clr(&addr, numpages, |
1831 | cachemode2pgprot(_PAGE_CACHE_MODE_WC), | |
bdc6340f PV |
1832 | __pgprot(_PAGE_CACHE_MASK), |
1833 | 0, 0, NULL); | |
3869c4aa | 1834 | } |
1835 | return ret; | |
ef354af4 | 1836 | } |
1837 | ||
1838 | int set_memory_wc(unsigned long addr, int numpages) | |
1839 | { | |
9fa3ab39 | 1840 | int ret; |
1841 | ||
9fa3ab39 | 1842 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1843 | _PAGE_CACHE_MODE_WC, NULL); |
9fa3ab39 | 1844 | if (ret) |
623dffb2 | 1845 | return ret; |
ef354af4 | 1846 | |
9fa3ab39 | 1847 | ret = _set_memory_wc(addr, numpages); |
1848 | if (ret) | |
623dffb2 | 1849 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1850 | |
9fa3ab39 | 1851 | return ret; |
ef354af4 | 1852 | } |
1853 | EXPORT_SYMBOL(set_memory_wc); | |
1854 | ||
623dffb2 TK |
1855 | int _set_memory_wt(unsigned long addr, int numpages) |
1856 | { | |
1857 | return change_page_attr_set(&addr, numpages, | |
1858 | cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0); | |
1859 | } | |
1860 | ||
1219333d | 1861 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1862 | { |
c06814d8 | 1863 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
d75586ad SL |
1864 | return change_page_attr_clear(&addr, numpages, |
1865 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1866 | } |
1219333d | 1867 | |
1868 | int set_memory_wb(unsigned long addr, int numpages) | |
1869 | { | |
9fa3ab39 | 1870 | int ret; |
1871 | ||
1872 | ret = _set_memory_wb(addr, numpages); | |
1873 | if (ret) | |
1874 | return ret; | |
1875 | ||
c15238df | 1876 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1877 | return 0; |
1219333d | 1878 | } |
75cbade8 AV |
1879 | EXPORT_SYMBOL(set_memory_wb); |
1880 | ||
1881 | int set_memory_x(unsigned long addr, int numpages) | |
1882 | { | |
583140af PA |
1883 | if (!(__supported_pte_mask & _PAGE_NX)) |
1884 | return 0; | |
1885 | ||
d75586ad | 1886 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 | 1887 | } |
75cbade8 AV |
1888 | |
1889 | int set_memory_nx(unsigned long addr, int numpages) | |
1890 | { | |
583140af PA |
1891 | if (!(__supported_pte_mask & _PAGE_NX)) |
1892 | return 0; | |
1893 | ||
d75586ad | 1894 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 | 1895 | } |
75cbade8 AV |
1896 | |
1897 | int set_memory_ro(unsigned long addr, int numpages) | |
1898 | { | |
d75586ad | 1899 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1900 | } |
75cbade8 AV |
1901 | |
1902 | int set_memory_rw(unsigned long addr, int numpages) | |
1903 | { | |
d75586ad | 1904 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1905 | } |
f62d0f00 IM |
1906 | |
1907 | int set_memory_np(unsigned long addr, int numpages) | |
1908 | { | |
d75586ad | 1909 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1910 | } |
75cbade8 | 1911 | |
c40a56a7 DH |
1912 | int set_memory_np_noalias(unsigned long addr, int numpages) |
1913 | { | |
1914 | int cpa_flags = CPA_NO_CHECK_ALIAS; | |
1915 | ||
1916 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), | |
1917 | __pgprot(_PAGE_PRESENT), 0, | |
1918 | cpa_flags, NULL); | |
1919 | } | |
1920 | ||
c9caa02c AK |
1921 | int set_memory_4k(unsigned long addr, int numpages) |
1922 | { | |
d75586ad | 1923 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1924 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1925 | } |
1926 | ||
39114b7a DH |
1927 | int set_memory_nonglobal(unsigned long addr, int numpages) |
1928 | { | |
1929 | return change_page_attr_clear(&addr, numpages, | |
1930 | __pgprot(_PAGE_GLOBAL), 0); | |
1931 | } | |
1932 | ||
eac7073a DH |
1933 | int set_memory_global(unsigned long addr, int numpages) |
1934 | { | |
1935 | return change_page_attr_set(&addr, numpages, | |
1936 | __pgprot(_PAGE_GLOBAL), 0); | |
1937 | } | |
1938 | ||
77bd2342 TL |
1939 | static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) |
1940 | { | |
1941 | struct cpa_data cpa; | |
77bd2342 TL |
1942 | int ret; |
1943 | ||
a72ec5a3 TL |
1944 | /* Nothing to do if memory encryption is not active */ |
1945 | if (!mem_encrypt_active()) | |
77bd2342 TL |
1946 | return 0; |
1947 | ||
1948 | /* Should not be working on unaligned addresses */ | |
1949 | if (WARN_ONCE(addr & ~PAGE_MASK, "misaligned address: %#lx\n", addr)) | |
1950 | addr &= PAGE_MASK; | |
1951 | ||
77bd2342 TL |
1952 | memset(&cpa, 0, sizeof(cpa)); |
1953 | cpa.vaddr = &addr; | |
1954 | cpa.numpages = numpages; | |
1955 | cpa.mask_set = enc ? __pgprot(_PAGE_ENC) : __pgprot(0); | |
1956 | cpa.mask_clr = enc ? __pgprot(0) : __pgprot(_PAGE_ENC); | |
1957 | cpa.pgd = init_mm.pgd; | |
1958 | ||
1959 | /* Must avoid aliasing mappings in the highmem code */ | |
1960 | kmap_flush_unused(); | |
1961 | vm_unmap_aliases(); | |
1962 | ||
1963 | /* | |
1964 | * Before changing the encryption attribute, we need to flush caches. | |
1965 | */ | |
fe0937b2 | 1966 | cpa_flush(&cpa, 1); |
77bd2342 TL |
1967 | |
1968 | ret = __change_page_attr_set_clr(&cpa, 1); | |
1969 | ||
1970 | /* | |
fe0937b2 PZ |
1971 | * After changing the encryption attribute, we need to flush TLBs again |
1972 | * in case any speculative TLB caching occurred (but no need to flush | |
1973 | * caches again). We could just use cpa_flush_all(), but in case TLB | |
1974 | * flushing gets optimized in the cpa_flush() path use the same logic | |
1975 | * as above. | |
77bd2342 | 1976 | */ |
fe0937b2 | 1977 | cpa_flush(&cpa, 0); |
77bd2342 TL |
1978 | |
1979 | return ret; | |
1980 | } | |
1981 | ||
1982 | int set_memory_encrypted(unsigned long addr, int numpages) | |
1983 | { | |
1984 | return __set_memory_enc_dec(addr, numpages, true); | |
1985 | } | |
95cf9264 | 1986 | EXPORT_SYMBOL_GPL(set_memory_encrypted); |
77bd2342 TL |
1987 | |
1988 | int set_memory_decrypted(unsigned long addr, int numpages) | |
1989 | { | |
1990 | return __set_memory_enc_dec(addr, numpages, false); | |
1991 | } | |
95cf9264 | 1992 | EXPORT_SYMBOL_GPL(set_memory_decrypted); |
77bd2342 | 1993 | |
75cbade8 AV |
1994 | int set_pages_uc(struct page *page, int numpages) |
1995 | { | |
1996 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1997 | |
d7c8f21a | 1998 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1999 | } |
2000 | EXPORT_SYMBOL(set_pages_uc); | |
2001 | ||
3c567356 | 2002 | static int _set_pages_array(struct page **pages, int numpages, |
c06814d8 | 2003 | enum page_cache_mode new_type) |
0f350755 | 2004 | { |
2005 | unsigned long start; | |
2006 | unsigned long end; | |
623dffb2 | 2007 | enum page_cache_mode set_type; |
0f350755 | 2008 | int i; |
2009 | int free_idx; | |
4f646254 | 2010 | int ret; |
0f350755 | 2011 | |
3c567356 | 2012 | for (i = 0; i < numpages; i++) { |
8523acfe TH |
2013 | if (PageHighMem(pages[i])) |
2014 | continue; | |
2015 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 2016 | end = start + PAGE_SIZE; |
4f646254 | 2017 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 2018 | goto err_out; |
2019 | } | |
2020 | ||
623dffb2 TK |
2021 | /* If WC, set to UC- first and then WC */ |
2022 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
2023 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
2024 | ||
3c567356 | 2025 | ret = cpa_set_pages_array(pages, numpages, |
623dffb2 | 2026 | cachemode2pgprot(set_type)); |
c06814d8 | 2027 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
3c567356 | 2028 | ret = change_page_attr_set_clr(NULL, numpages, |
c06814d8 JG |
2029 | cachemode2pgprot( |
2030 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
2031 | __pgprot(_PAGE_CACHE_MASK), |
2032 | 0, CPA_PAGES_ARRAY, pages); | |
2033 | if (ret) | |
2034 | goto err_out; | |
2035 | return 0; /* Success */ | |
0f350755 | 2036 | err_out: |
2037 | free_idx = i; | |
2038 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
2039 | if (PageHighMem(pages[i])) |
2040 | continue; | |
2041 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 2042 | end = start + PAGE_SIZE; |
2043 | free_memtype(start, end); | |
2044 | } | |
2045 | return -EINVAL; | |
2046 | } | |
4f646254 | 2047 | |
3c567356 | 2048 | int set_pages_array_uc(struct page **pages, int numpages) |
4f646254 | 2049 | { |
3c567356 | 2050 | return _set_pages_array(pages, numpages, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 2051 | } |
0f350755 | 2052 | EXPORT_SYMBOL(set_pages_array_uc); |
2053 | ||
3c567356 | 2054 | int set_pages_array_wc(struct page **pages, int numpages) |
4f646254 | 2055 | { |
3c567356 | 2056 | return _set_pages_array(pages, numpages, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
2057 | } |
2058 | EXPORT_SYMBOL(set_pages_array_wc); | |
2059 | ||
3c567356 | 2060 | int set_pages_array_wt(struct page **pages, int numpages) |
623dffb2 | 2061 | { |
3c567356 | 2062 | return _set_pages_array(pages, numpages, _PAGE_CACHE_MODE_WT); |
623dffb2 TK |
2063 | } |
2064 | EXPORT_SYMBOL_GPL(set_pages_array_wt); | |
2065 | ||
75cbade8 AV |
2066 | int set_pages_wb(struct page *page, int numpages) |
2067 | { | |
2068 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 2069 | |
d7c8f21a | 2070 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
2071 | } |
2072 | EXPORT_SYMBOL(set_pages_wb); | |
2073 | ||
3c567356 | 2074 | int set_pages_array_wb(struct page **pages, int numpages) |
0f350755 | 2075 | { |
2076 | int retval; | |
2077 | unsigned long start; | |
2078 | unsigned long end; | |
2079 | int i; | |
2080 | ||
c06814d8 | 2081 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
3c567356 | 2082 | retval = cpa_clear_pages_array(pages, numpages, |
0f350755 | 2083 | __pgprot(_PAGE_CACHE_MASK)); |
9fa3ab39 | 2084 | if (retval) |
2085 | return retval; | |
0f350755 | 2086 | |
3c567356 | 2087 | for (i = 0; i < numpages; i++) { |
8523acfe TH |
2088 | if (PageHighMem(pages[i])) |
2089 | continue; | |
2090 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 2091 | end = start + PAGE_SIZE; |
2092 | free_memtype(start, end); | |
2093 | } | |
2094 | ||
9fa3ab39 | 2095 | return 0; |
0f350755 | 2096 | } |
2097 | EXPORT_SYMBOL(set_pages_array_wb); | |
2098 | ||
75cbade8 AV |
2099 | int set_pages_ro(struct page *page, int numpages) |
2100 | { | |
2101 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 2102 | |
d7c8f21a | 2103 | return set_memory_ro(addr, numpages); |
75cbade8 | 2104 | } |
75cbade8 AV |
2105 | |
2106 | int set_pages_rw(struct page *page, int numpages) | |
2107 | { | |
2108 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 2109 | |
d7c8f21a | 2110 | return set_memory_rw(addr, numpages); |
78c94aba IM |
2111 | } |
2112 | ||
f62d0f00 IM |
2113 | static int __set_pages_p(struct page *page, int numpages) |
2114 | { | |
d75586ad SL |
2115 | unsigned long tempaddr = (unsigned long) page_address(page); |
2116 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 2117 | .pgd = NULL, |
72e458df TG |
2118 | .numpages = numpages, |
2119 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
2120 | .mask_clr = __pgprot(0), |
2121 | .flags = 0}; | |
72932c7a | 2122 | |
55121b43 SS |
2123 | /* |
2124 | * No alias checking needed for setting present flag. otherwise, | |
2125 | * we may need to break large pages for 64-bit kernel text | |
2126 | * mappings (this adds to complexity if we want to do this from | |
2127 | * atomic context especially). Let's keep it simple! | |
2128 | */ | |
2129 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
2130 | } |
2131 | ||
2132 | static int __set_pages_np(struct page *page, int numpages) | |
2133 | { | |
d75586ad SL |
2134 | unsigned long tempaddr = (unsigned long) page_address(page); |
2135 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 2136 | .pgd = NULL, |
72e458df TG |
2137 | .numpages = numpages, |
2138 | .mask_set = __pgprot(0), | |
d75586ad SL |
2139 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
2140 | .flags = 0}; | |
72932c7a | 2141 | |
55121b43 SS |
2142 | /* |
2143 | * No alias checking needed for setting not present flag. otherwise, | |
2144 | * we may need to break large pages for 64-bit kernel text | |
2145 | * mappings (this adds to complexity if we want to do this from | |
2146 | * atomic context especially). Let's keep it simple! | |
2147 | */ | |
2148 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
2149 | } |
2150 | ||
d253ca0c RE |
2151 | int set_direct_map_invalid_noflush(struct page *page) |
2152 | { | |
2153 | return __set_pages_np(page, 1); | |
2154 | } | |
2155 | ||
2156 | int set_direct_map_default_noflush(struct page *page) | |
2157 | { | |
2158 | return __set_pages_p(page, 1); | |
2159 | } | |
2160 | ||
031bc574 | 2161 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
1da177e4 LT |
2162 | { |
2163 | if (PageHighMem(page)) | |
2164 | return; | |
9f4c815c | 2165 | if (!enable) { |
f9b8404c IM |
2166 | debug_check_no_locks_freed(page_address(page), |
2167 | numpages * PAGE_SIZE); | |
9f4c815c | 2168 | } |
de5097c2 | 2169 | |
9f4c815c | 2170 | /* |
f8d8406b | 2171 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
2172 | * Large pages for identity mappings are not used at boot time |
2173 | * and hence no memory allocations during large page split. | |
1da177e4 | 2174 | */ |
f62d0f00 IM |
2175 | if (enable) |
2176 | __set_pages_p(page, numpages); | |
2177 | else | |
2178 | __set_pages_np(page, numpages); | |
9f4c815c IM |
2179 | |
2180 | /* | |
e4b71dcf | 2181 | * We should perform an IPI and flush all tlbs, |
f77084d9 SAS |
2182 | * but that can deadlock->flush only current cpu. |
2183 | * Preemption needs to be disabled around __flush_tlb_all() due to | |
2184 | * CR3 reload in __native_flush_tlb(). | |
1da177e4 | 2185 | */ |
f77084d9 | 2186 | preempt_disable(); |
1da177e4 | 2187 | __flush_tlb_all(); |
f77084d9 | 2188 | preempt_enable(); |
26564600 BO |
2189 | |
2190 | arch_flush_lazy_mmu_mode(); | |
ee7ae7a1 TG |
2191 | } |
2192 | ||
8a235efa | 2193 | #ifdef CONFIG_HIBERNATION |
8a235efa RW |
2194 | bool kernel_page_present(struct page *page) |
2195 | { | |
2196 | unsigned int level; | |
2197 | pte_t *pte; | |
2198 | ||
2199 | if (PageHighMem(page)) | |
2200 | return false; | |
2201 | ||
2202 | pte = lookup_address((unsigned long)page_address(page), &level); | |
2203 | return (pte_val(*pte) & _PAGE_PRESENT); | |
2204 | } | |
8a235efa RW |
2205 | #endif /* CONFIG_HIBERNATION */ |
2206 | ||
7e0dabd3 SPP |
2207 | int __init kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address, |
2208 | unsigned numpages, unsigned long page_flags) | |
82f0712c BP |
2209 | { |
2210 | int retval = -EINVAL; | |
2211 | ||
2212 | struct cpa_data cpa = { | |
2213 | .vaddr = &address, | |
2214 | .pfn = pfn, | |
2215 | .pgd = pgd, | |
2216 | .numpages = numpages, | |
2217 | .mask_set = __pgprot(0), | |
2218 | .mask_clr = __pgprot(0), | |
2219 | .flags = 0, | |
2220 | }; | |
2221 | ||
7e0dabd3 SPP |
2222 | WARN_ONCE(num_online_cpus() > 1, "Don't call after initializing SMP"); |
2223 | ||
82f0712c BP |
2224 | if (!(__supported_pte_mask & _PAGE_NX)) |
2225 | goto out; | |
2226 | ||
2227 | if (!(page_flags & _PAGE_NX)) | |
2228 | cpa.mask_clr = __pgprot(_PAGE_NX); | |
2229 | ||
15f003d2 SP |
2230 | if (!(page_flags & _PAGE_RW)) |
2231 | cpa.mask_clr = __pgprot(_PAGE_RW); | |
2232 | ||
21729f81 TL |
2233 | if (!(page_flags & _PAGE_ENC)) |
2234 | cpa.mask_clr = pgprot_encrypted(cpa.mask_clr); | |
2235 | ||
82f0712c BP |
2236 | cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags); |
2237 | ||
2238 | retval = __change_page_attr_set_clr(&cpa, 0); | |
2239 | __flush_tlb_all(); | |
2240 | ||
2241 | out: | |
2242 | return retval; | |
2243 | } | |
2244 | ||
7e0dabd3 SPP |
2245 | /* |
2246 | * __flush_tlb_all() flushes mappings only on current CPU and hence this | |
2247 | * function shouldn't be used in an SMP environment. Presently, it's used only | |
2248 | * during boot (way before smp_init()) by EFI subsystem and hence is ok. | |
2249 | */ | |
2250 | int __init kernel_unmap_pages_in_pgd(pgd_t *pgd, unsigned long address, | |
2251 | unsigned long numpages) | |
2252 | { | |
2253 | int retval; | |
2254 | ||
2255 | /* | |
2256 | * The typical sequence for unmapping is to find a pte through | |
2257 | * lookup_address_in_pgd() (ideally, it should never return NULL because | |
2258 | * the address is already mapped) and change it's protections. As pfn is | |
2259 | * the *target* of a mapping, it's not useful while unmapping. | |
2260 | */ | |
2261 | struct cpa_data cpa = { | |
2262 | .vaddr = &address, | |
2263 | .pfn = 0, | |
2264 | .pgd = pgd, | |
2265 | .numpages = numpages, | |
2266 | .mask_set = __pgprot(0), | |
2267 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
2268 | .flags = 0, | |
2269 | }; | |
2270 | ||
2271 | WARN_ONCE(num_online_cpus() > 1, "Don't call after initializing SMP"); | |
2272 | ||
2273 | retval = __change_page_attr_set_clr(&cpa, 0); | |
2274 | __flush_tlb_all(); | |
2275 | ||
2276 | return retval; | |
2277 | } | |
2278 | ||
d1028a15 AV |
2279 | /* |
2280 | * The testcases use internal knowledge of the implementation that shouldn't | |
2281 | * be exposed to the rest of the kernel. Include these directly here. | |
2282 | */ | |
2283 | #ifdef CONFIG_CPA_DEBUG | |
2284 | #include "pageattr-test.c" | |
2285 | #endif |