mm: pass the vmem_altmap to memmap_init_zone
[linux-block.git] / arch / x86 / mm / init_64.c
CommitLineData
1da177e4
LT
1/*
2 * linux/arch/x86_64/mm/init.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
a2531293 5 * Copyright (C) 2000 Pavel Machek <pavel@ucw.cz>
1da177e4
LT
6 * Copyright (C) 2002,2003 Andi Kleen <ak@suse.de>
7 */
8
1da177e4
LT
9#include <linux/signal.h>
10#include <linux/sched.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/string.h>
14#include <linux/types.h>
15#include <linux/ptrace.h>
16#include <linux/mman.h>
17#include <linux/mm.h>
18#include <linux/swap.h>
19#include <linux/smp.h>
20#include <linux/init.h>
11034d55 21#include <linux/initrd.h>
1da177e4
LT
22#include <linux/pagemap.h>
23#include <linux/bootmem.h>
a9ce6bc1 24#include <linux/memblock.h>
1da177e4 25#include <linux/proc_fs.h>
59170891 26#include <linux/pci.h>
6fb14755 27#include <linux/pfn.h>
c9cf5528 28#include <linux/poison.h>
17a941d8 29#include <linux/dma-mapping.h>
a63fdc51 30#include <linux/memory.h>
44df75e6 31#include <linux/memory_hotplug.h>
4b94ffdc 32#include <linux/memremap.h>
ae32b129 33#include <linux/nmi.h>
5a0e3ad6 34#include <linux/gfp.h>
2f96b8c1 35#include <linux/kcore.h>
1da177e4
LT
36
37#include <asm/processor.h>
46eaa670 38#include <asm/bios_ebda.h>
7c0f6ba6 39#include <linux/uaccess.h>
1da177e4
LT
40#include <asm/pgtable.h>
41#include <asm/pgalloc.h>
42#include <asm/dma.h>
43#include <asm/fixmap.h>
66441bd3 44#include <asm/e820/api.h>
1da177e4
LT
45#include <asm/apic.h>
46#include <asm/tlb.h>
47#include <asm/mmu_context.h>
48#include <asm/proto.h>
49#include <asm/smp.h>
2bc0414e 50#include <asm/sections.h>
718fc13b 51#include <asm/kdebug.h>
aaa64e04 52#include <asm/numa.h>
d1163651 53#include <asm/set_memory.h>
4fcb2083 54#include <asm/init.h>
43c75f93 55#include <asm/uv/uv.h>
e5f15b45 56#include <asm/setup.h>
1da177e4 57
5c51bdbe
YL
58#include "mm_internal.h"
59
cf4fb15b 60#include "ident_map.c"
aece2785 61
1da177e4
LT
62/*
63 * NOTE: pagetable_init alloc all the fixmap pagetables contiguous on the
64 * physical space so we can cache the place of the first one and move
65 * around without checking the pgd every time.
66 */
67
f955371c 68pteval_t __supported_pte_mask __read_mostly = ~0;
bd220a24
YL
69EXPORT_SYMBOL_GPL(__supported_pte_mask);
70
bd220a24
YL
71int force_personality32;
72
deed05b7
IM
73/*
74 * noexec32=on|off
75 * Control non executable heap for 32bit processes.
76 * To control the stack too use noexec=off
77 *
78 * on PROT_READ does not imply PROT_EXEC for 32-bit processes (default)
79 * off PROT_READ implies PROT_EXEC
80 */
bd220a24
YL
81static int __init nonx32_setup(char *str)
82{
83 if (!strcmp(str, "on"))
84 force_personality32 &= ~READ_IMPLIES_EXEC;
85 else if (!strcmp(str, "off"))
86 force_personality32 |= READ_IMPLIES_EXEC;
87 return 1;
88}
89__setup("noexec32=", nonx32_setup);
90
6afb5157 91/*
5372e155 92 * When memory was added make sure all the processes MM have
6afb5157
HL
93 * suitable PGD entries in the local PGD level page.
94 */
141efad7
KS
95#ifdef CONFIG_X86_5LEVEL
96void sync_global_pgds(unsigned long start, unsigned long end)
97{
98 unsigned long addr;
99
100 for (addr = start; addr <= end; addr = ALIGN(addr + 1, PGDIR_SIZE)) {
101 const pgd_t *pgd_ref = pgd_offset_k(addr);
102 struct page *page;
103
104 /* Check for overflow */
105 if (addr < start)
106 break;
107
108 if (pgd_none(*pgd_ref))
109 continue;
110
111 spin_lock(&pgd_lock);
112 list_for_each_entry(page, &pgd_list, lru) {
113 pgd_t *pgd;
114 spinlock_t *pgt_lock;
115
116 pgd = (pgd_t *)page_address(page) + pgd_index(addr);
117 /* the pgt_lock only for Xen */
118 pgt_lock = &pgd_page_get_mm(page)->page_table_lock;
119 spin_lock(pgt_lock);
120
121 if (!pgd_none(*pgd_ref) && !pgd_none(*pgd))
122 BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_ref));
123
124 if (pgd_none(*pgd))
125 set_pgd(pgd, *pgd_ref);
126
127 spin_unlock(pgt_lock);
128 }
129 spin_unlock(&pgd_lock);
130 }
131}
132#else
5372e155 133void sync_global_pgds(unsigned long start, unsigned long end)
6afb5157 134{
fc5f9d5f 135 unsigned long addr;
44235dcd 136
fc5f9d5f
BH
137 for (addr = start; addr <= end; addr = ALIGN(addr + 1, PGDIR_SIZE)) {
138 pgd_t *pgd_ref = pgd_offset_k(addr);
f2a6a705 139 const p4d_t *p4d_ref;
44235dcd
JF
140 struct page *page;
141
f2a6a705
KS
142 /*
143 * With folded p4d, pgd_none() is always false, we need to
144 * handle synchonization on p4d level.
145 */
146 BUILD_BUG_ON(pgd_none(*pgd_ref));
fc5f9d5f 147 p4d_ref = p4d_offset(pgd_ref, addr);
f2a6a705
KS
148
149 if (p4d_none(*p4d_ref))
44235dcd
JF
150 continue;
151
a79e53d8 152 spin_lock(&pgd_lock);
44235dcd 153 list_for_each_entry(page, &pgd_list, lru) {
be354f40 154 pgd_t *pgd;
f2a6a705 155 p4d_t *p4d;
617d34d9
JF
156 spinlock_t *pgt_lock;
157
fc5f9d5f
BH
158 pgd = (pgd_t *)page_address(page) + pgd_index(addr);
159 p4d = p4d_offset(pgd, addr);
a79e53d8 160 /* the pgt_lock only for Xen */
617d34d9
JF
161 pgt_lock = &pgd_page_get_mm(page)->page_table_lock;
162 spin_lock(pgt_lock);
163
f2a6a705
KS
164 if (!p4d_none(*p4d_ref) && !p4d_none(*p4d))
165 BUG_ON(p4d_page_vaddr(*p4d)
166 != p4d_page_vaddr(*p4d_ref));
617d34d9 167
f2a6a705
KS
168 if (p4d_none(*p4d))
169 set_p4d(p4d, *p4d_ref);
9661d5bc 170
617d34d9 171 spin_unlock(pgt_lock);
44235dcd 172 }
a79e53d8 173 spin_unlock(&pgd_lock);
44235dcd 174 }
6afb5157 175}
141efad7 176#endif
6afb5157 177
8d6ea967
MS
178/*
179 * NOTE: This function is marked __ref because it calls __init function
180 * (alloc_bootmem_pages). It's safe to do it ONLY when after_bootmem == 0.
181 */
182static __ref void *spp_getpage(void)
14a62c34 183{
1da177e4 184 void *ptr;
14a62c34 185
1da177e4 186 if (after_bootmem)
75f296d9 187 ptr = (void *) get_zeroed_page(GFP_ATOMIC);
1da177e4
LT
188 else
189 ptr = alloc_bootmem_pages(PAGE_SIZE);
14a62c34
TG
190
191 if (!ptr || ((unsigned long)ptr & ~PAGE_MASK)) {
192 panic("set_pte_phys: cannot allocate page data %s\n",
193 after_bootmem ? "after bootmem" : "");
194 }
1da177e4 195
10f22dde 196 pr_debug("spp_getpage %p\n", ptr);
14a62c34 197
1da177e4 198 return ptr;
14a62c34 199}
1da177e4 200
f2a6a705 201static p4d_t *fill_p4d(pgd_t *pgd, unsigned long vaddr)
1da177e4 202{
458a3e64 203 if (pgd_none(*pgd)) {
f2a6a705
KS
204 p4d_t *p4d = (p4d_t *)spp_getpage();
205 pgd_populate(&init_mm, pgd, p4d);
206 if (p4d != p4d_offset(pgd, 0))
458a3e64 207 printk(KERN_ERR "PAGETABLE BUG #00! %p <-> %p\n",
f2a6a705
KS
208 p4d, p4d_offset(pgd, 0));
209 }
210 return p4d_offset(pgd, vaddr);
211}
212
213static pud_t *fill_pud(p4d_t *p4d, unsigned long vaddr)
214{
215 if (p4d_none(*p4d)) {
216 pud_t *pud = (pud_t *)spp_getpage();
217 p4d_populate(&init_mm, p4d, pud);
218 if (pud != pud_offset(p4d, 0))
219 printk(KERN_ERR "PAGETABLE BUG #01! %p <-> %p\n",
220 pud, pud_offset(p4d, 0));
458a3e64 221 }
f2a6a705 222 return pud_offset(p4d, vaddr);
458a3e64 223}
1da177e4 224
f254f390 225static pmd_t *fill_pmd(pud_t *pud, unsigned long vaddr)
458a3e64 226{
1da177e4 227 if (pud_none(*pud)) {
458a3e64 228 pmd_t *pmd = (pmd_t *) spp_getpage();
bb23e403 229 pud_populate(&init_mm, pud, pmd);
458a3e64 230 if (pmd != pmd_offset(pud, 0))
f2a6a705 231 printk(KERN_ERR "PAGETABLE BUG #02! %p <-> %p\n",
458a3e64 232 pmd, pmd_offset(pud, 0));
1da177e4 233 }
458a3e64
TH
234 return pmd_offset(pud, vaddr);
235}
236
f254f390 237static pte_t *fill_pte(pmd_t *pmd, unsigned long vaddr)
458a3e64 238{
1da177e4 239 if (pmd_none(*pmd)) {
458a3e64 240 pte_t *pte = (pte_t *) spp_getpage();
bb23e403 241 pmd_populate_kernel(&init_mm, pmd, pte);
458a3e64 242 if (pte != pte_offset_kernel(pmd, 0))
f2a6a705 243 printk(KERN_ERR "PAGETABLE BUG #03!\n");
1da177e4 244 }
458a3e64
TH
245 return pte_offset_kernel(pmd, vaddr);
246}
247
f2a6a705 248static void __set_pte_vaddr(pud_t *pud, unsigned long vaddr, pte_t new_pte)
458a3e64 249{
f2a6a705
KS
250 pmd_t *pmd = fill_pmd(pud, vaddr);
251 pte_t *pte = fill_pte(pmd, vaddr);
1da177e4 252
1da177e4
LT
253 set_pte(pte, new_pte);
254
255 /*
256 * It's enough to flush this one mapping.
257 * (PGE mappings get flushed as well)
258 */
259 __flush_tlb_one(vaddr);
260}
261
f2a6a705
KS
262void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte)
263{
264 p4d_t *p4d = p4d_page + p4d_index(vaddr);
265 pud_t *pud = fill_pud(p4d, vaddr);
266
267 __set_pte_vaddr(pud, vaddr, new_pte);
268}
269
270void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte)
271{
272 pud_t *pud = pud_page + pud_index(vaddr);
273
274 __set_pte_vaddr(pud, vaddr, new_pte);
275}
276
458a3e64 277void set_pte_vaddr(unsigned long vaddr, pte_t pteval)
0814e0ba
EH
278{
279 pgd_t *pgd;
f2a6a705 280 p4d_t *p4d_page;
0814e0ba
EH
281
282 pr_debug("set_pte_vaddr %lx to %lx\n", vaddr, native_pte_val(pteval));
283
284 pgd = pgd_offset_k(vaddr);
285 if (pgd_none(*pgd)) {
286 printk(KERN_ERR
287 "PGD FIXMAP MISSING, it should be setup in head.S!\n");
288 return;
289 }
f2a6a705
KS
290
291 p4d_page = p4d_offset(pgd, 0);
292 set_pte_vaddr_p4d(p4d_page, vaddr, pteval);
0814e0ba
EH
293}
294
458a3e64 295pmd_t * __init populate_extra_pmd(unsigned long vaddr)
11124411
TH
296{
297 pgd_t *pgd;
f2a6a705 298 p4d_t *p4d;
11124411
TH
299 pud_t *pud;
300
301 pgd = pgd_offset_k(vaddr);
f2a6a705
KS
302 p4d = fill_p4d(pgd, vaddr);
303 pud = fill_pud(p4d, vaddr);
458a3e64
TH
304 return fill_pmd(pud, vaddr);
305}
306
307pte_t * __init populate_extra_pte(unsigned long vaddr)
308{
309 pmd_t *pmd;
11124411 310
458a3e64
TH
311 pmd = populate_extra_pmd(vaddr);
312 return fill_pte(pmd, vaddr);
11124411
TH
313}
314
3a9e189d
JS
315/*
316 * Create large page table mappings for a range of physical addresses.
317 */
318static void __init __init_extra_mapping(unsigned long phys, unsigned long size,
2df58b6d 319 enum page_cache_mode cache)
3a9e189d
JS
320{
321 pgd_t *pgd;
f2a6a705 322 p4d_t *p4d;
3a9e189d
JS
323 pud_t *pud;
324 pmd_t *pmd;
2df58b6d 325 pgprot_t prot;
3a9e189d 326
2df58b6d
JG
327 pgprot_val(prot) = pgprot_val(PAGE_KERNEL_LARGE) |
328 pgprot_val(pgprot_4k_2_large(cachemode2pgprot(cache)));
3a9e189d
JS
329 BUG_ON((phys & ~PMD_MASK) || (size & ~PMD_MASK));
330 for (; size; phys += PMD_SIZE, size -= PMD_SIZE) {
331 pgd = pgd_offset_k((unsigned long)__va(phys));
332 if (pgd_none(*pgd)) {
f2a6a705
KS
333 p4d = (p4d_t *) spp_getpage();
334 set_pgd(pgd, __pgd(__pa(p4d) | _KERNPG_TABLE |
335 _PAGE_USER));
336 }
337 p4d = p4d_offset(pgd, (unsigned long)__va(phys));
338 if (p4d_none(*p4d)) {
3a9e189d 339 pud = (pud_t *) spp_getpage();
f2a6a705 340 set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE |
3a9e189d
JS
341 _PAGE_USER));
342 }
f2a6a705 343 pud = pud_offset(p4d, (unsigned long)__va(phys));
3a9e189d
JS
344 if (pud_none(*pud)) {
345 pmd = (pmd_t *) spp_getpage();
346 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE |
347 _PAGE_USER));
348 }
349 pmd = pmd_offset(pud, phys);
350 BUG_ON(!pmd_none(*pmd));
351 set_pmd(pmd, __pmd(phys | pgprot_val(prot)));
352 }
353}
354
355void __init init_extra_mapping_wb(unsigned long phys, unsigned long size)
356{
2df58b6d 357 __init_extra_mapping(phys, size, _PAGE_CACHE_MODE_WB);
3a9e189d
JS
358}
359
360void __init init_extra_mapping_uc(unsigned long phys, unsigned long size)
361{
2df58b6d 362 __init_extra_mapping(phys, size, _PAGE_CACHE_MODE_UC);
3a9e189d
JS
363}
364
31eedd82 365/*
88f3aec7
IM
366 * The head.S code sets up the kernel high mapping:
367 *
368 * from __START_KERNEL_map to __START_KERNEL_map + size (== _end-_text)
31eedd82 369 *
1e3b3081 370 * phys_base holds the negative offset to the kernel, which is added
31eedd82
TG
371 * to the compile time generated pmds. This results in invalid pmds up
372 * to the point where we hit the physaddr 0 mapping.
373 *
e5f15b45
YL
374 * We limit the mappings to the region from _text to _brk_end. _brk_end
375 * is rounded up to the 2MB boundary. This catches the invalid pmds as
31eedd82
TG
376 * well, as they are located before _text:
377 */
378void __init cleanup_highmap(void)
379{
380 unsigned long vaddr = __START_KERNEL_map;
10054230 381 unsigned long vaddr_end = __START_KERNEL_map + KERNEL_IMAGE_SIZE;
e5f15b45 382 unsigned long end = roundup((unsigned long)_brk_end, PMD_SIZE) - 1;
31eedd82 383 pmd_t *pmd = level2_kernel_pgt;
31eedd82 384
10054230
YL
385 /*
386 * Native path, max_pfn_mapped is not set yet.
387 * Xen has valid max_pfn_mapped set in
388 * arch/x86/xen/mmu.c:xen_setup_kernel_pagetable().
389 */
390 if (max_pfn_mapped)
391 vaddr_end = __START_KERNEL_map + (max_pfn_mapped << PAGE_SHIFT);
392
e5f15b45 393 for (; vaddr + PMD_SIZE - 1 < vaddr_end; pmd++, vaddr += PMD_SIZE) {
2884f110 394 if (pmd_none(*pmd))
31eedd82
TG
395 continue;
396 if (vaddr < (unsigned long) _text || vaddr > end)
397 set_pmd(pmd, __pmd(0));
398 }
399}
400
59b3d020
TG
401/*
402 * Create PTE level page table mapping for physical addresses.
403 * It returns the last physical address mapped.
404 */
7b16eb89 405static unsigned long __meminit
59b3d020 406phys_pte_init(pte_t *pte_page, unsigned long paddr, unsigned long paddr_end,
b27a43c1 407 pgprot_t prot)
4f9c11dd 408{
59b3d020
TG
409 unsigned long pages = 0, paddr_next;
410 unsigned long paddr_last = paddr_end;
411 pte_t *pte;
4f9c11dd 412 int i;
7b16eb89 413
59b3d020
TG
414 pte = pte_page + pte_index(paddr);
415 i = pte_index(paddr);
4f9c11dd 416
59b3d020
TG
417 for (; i < PTRS_PER_PTE; i++, paddr = paddr_next, pte++) {
418 paddr_next = (paddr & PAGE_MASK) + PAGE_SIZE;
419 if (paddr >= paddr_end) {
eceb3632 420 if (!after_bootmem &&
3bce64f0 421 !e820__mapped_any(paddr & PAGE_MASK, paddr_next,
09821ff1 422 E820_TYPE_RAM) &&
3bce64f0 423 !e820__mapped_any(paddr & PAGE_MASK, paddr_next,
09821ff1 424 E820_TYPE_RESERVED_KERN))
eceb3632
YL
425 set_pte(pte, __pte(0));
426 continue;
4f9c11dd
JF
427 }
428
b27a43c1
SS
429 /*
430 * We will re-use the existing mapping.
431 * Xen for example has some special requirements, like mapping
432 * pagetable pages as RO. So assume someone who pre-setup
433 * these mappings are more intelligent.
434 */
dcb32d99 435 if (!pte_none(*pte)) {
876ee61a
JB
436 if (!after_bootmem)
437 pages++;
4f9c11dd 438 continue;
3afa3949 439 }
4f9c11dd
JF
440
441 if (0)
59b3d020
TG
442 pr_info(" pte=%p addr=%lx pte=%016lx\n", pte, paddr,
443 pfn_pte(paddr >> PAGE_SHIFT, PAGE_KERNEL).pte);
4f9c11dd 444 pages++;
59b3d020
TG
445 set_pte(pte, pfn_pte(paddr >> PAGE_SHIFT, prot));
446 paddr_last = (paddr & PAGE_MASK) + PAGE_SIZE;
4f9c11dd 447 }
a2699e47 448
4f9c11dd 449 update_page_count(PG_LEVEL_4K, pages);
7b16eb89 450
59b3d020 451 return paddr_last;
4f9c11dd
JF
452}
453
59b3d020
TG
454/*
455 * Create PMD level page table mapping for physical addresses. The virtual
456 * and physical address have to be aligned at this level.
457 * It returns the last physical address mapped.
458 */
cc615032 459static unsigned long __meminit
59b3d020 460phys_pmd_init(pmd_t *pmd_page, unsigned long paddr, unsigned long paddr_end,
b27a43c1 461 unsigned long page_size_mask, pgprot_t prot)
44df75e6 462{
59b3d020
TG
463 unsigned long pages = 0, paddr_next;
464 unsigned long paddr_last = paddr_end;
ce0c0e50 465
59b3d020 466 int i = pmd_index(paddr);
44df75e6 467
59b3d020
TG
468 for (; i < PTRS_PER_PMD; i++, paddr = paddr_next) {
469 pmd_t *pmd = pmd_page + pmd_index(paddr);
4f9c11dd 470 pte_t *pte;
b27a43c1 471 pgprot_t new_prot = prot;
44df75e6 472
59b3d020
TG
473 paddr_next = (paddr & PMD_MASK) + PMD_SIZE;
474 if (paddr >= paddr_end) {
eceb3632 475 if (!after_bootmem &&
3bce64f0 476 !e820__mapped_any(paddr & PMD_MASK, paddr_next,
09821ff1 477 E820_TYPE_RAM) &&
3bce64f0 478 !e820__mapped_any(paddr & PMD_MASK, paddr_next,
09821ff1 479 E820_TYPE_RESERVED_KERN))
eceb3632
YL
480 set_pmd(pmd, __pmd(0));
481 continue;
44df75e6 482 }
6ad91658 483
dcb32d99 484 if (!pmd_none(*pmd)) {
8ae3a5a8
JB
485 if (!pmd_large(*pmd)) {
486 spin_lock(&init_mm.page_table_lock);
973dc4f3 487 pte = (pte_t *)pmd_page_vaddr(*pmd);
59b3d020
TG
488 paddr_last = phys_pte_init(pte, paddr,
489 paddr_end, prot);
8ae3a5a8 490 spin_unlock(&init_mm.page_table_lock);
a2699e47 491 continue;
8ae3a5a8 492 }
b27a43c1
SS
493 /*
494 * If we are ok with PG_LEVEL_2M mapping, then we will
495 * use the existing mapping,
496 *
497 * Otherwise, we will split the large page mapping but
498 * use the same existing protection bits except for
499 * large page, so that we don't violate Intel's TLB
500 * Application note (317080) which says, while changing
501 * the page sizes, new and old translations should
502 * not differ with respect to page frame and
503 * attributes.
504 */
3afa3949 505 if (page_size_mask & (1 << PG_LEVEL_2M)) {
876ee61a
JB
506 if (!after_bootmem)
507 pages++;
59b3d020 508 paddr_last = paddr_next;
b27a43c1 509 continue;
3afa3949 510 }
b27a43c1 511 new_prot = pte_pgprot(pte_clrhuge(*(pte_t *)pmd));
4f9c11dd
JF
512 }
513
b50efd2a 514 if (page_size_mask & (1<<PG_LEVEL_2M)) {
4f9c11dd 515 pages++;
8ae3a5a8 516 spin_lock(&init_mm.page_table_lock);
4f9c11dd 517 set_pte((pte_t *)pmd,
59b3d020 518 pfn_pte((paddr & PMD_MASK) >> PAGE_SHIFT,
b27a43c1 519 __pgprot(pgprot_val(prot) | _PAGE_PSE)));
8ae3a5a8 520 spin_unlock(&init_mm.page_table_lock);
59b3d020 521 paddr_last = paddr_next;
6ad91658 522 continue;
4f9c11dd 523 }
6ad91658 524
868bf4d6 525 pte = alloc_low_page();
59b3d020 526 paddr_last = phys_pte_init(pte, paddr, paddr_end, new_prot);
4f9c11dd 527
8ae3a5a8 528 spin_lock(&init_mm.page_table_lock);
868bf4d6 529 pmd_populate_kernel(&init_mm, pmd, pte);
8ae3a5a8 530 spin_unlock(&init_mm.page_table_lock);
44df75e6 531 }
ce0c0e50 532 update_page_count(PG_LEVEL_2M, pages);
59b3d020 533 return paddr_last;
44df75e6
MT
534}
535
59b3d020
TG
536/*
537 * Create PUD level page table mapping for physical addresses. The virtual
faa37933
TG
538 * and physical address do not have to be aligned at this level. KASLR can
539 * randomize virtual addresses up to this level.
59b3d020
TG
540 * It returns the last physical address mapped.
541 */
cc615032 542static unsigned long __meminit
59b3d020
TG
543phys_pud_init(pud_t *pud_page, unsigned long paddr, unsigned long paddr_end,
544 unsigned long page_size_mask)
14a62c34 545{
59b3d020
TG
546 unsigned long pages = 0, paddr_next;
547 unsigned long paddr_last = paddr_end;
faa37933
TG
548 unsigned long vaddr = (unsigned long)__va(paddr);
549 int i = pud_index(vaddr);
44df75e6 550
59b3d020 551 for (; i < PTRS_PER_PUD; i++, paddr = paddr_next) {
faa37933 552 pud_t *pud;
1da177e4 553 pmd_t *pmd;
b27a43c1 554 pgprot_t prot = PAGE_KERNEL;
1da177e4 555
faa37933
TG
556 vaddr = (unsigned long)__va(paddr);
557 pud = pud_page + pud_index(vaddr);
59b3d020 558 paddr_next = (paddr & PUD_MASK) + PUD_SIZE;
faa37933 559
59b3d020 560 if (paddr >= paddr_end) {
eceb3632 561 if (!after_bootmem &&
3bce64f0 562 !e820__mapped_any(paddr & PUD_MASK, paddr_next,
09821ff1 563 E820_TYPE_RAM) &&
3bce64f0 564 !e820__mapped_any(paddr & PUD_MASK, paddr_next,
09821ff1 565 E820_TYPE_RESERVED_KERN))
eceb3632 566 set_pud(pud, __pud(0));
1da177e4 567 continue;
14a62c34 568 }
1da177e4 569
dcb32d99 570 if (!pud_none(*pud)) {
a2699e47 571 if (!pud_large(*pud)) {
973dc4f3 572 pmd = pmd_offset(pud, 0);
59b3d020
TG
573 paddr_last = phys_pmd_init(pmd, paddr,
574 paddr_end,
575 page_size_mask,
576 prot);
4b239f45 577 __flush_tlb_all();
a2699e47
SS
578 continue;
579 }
b27a43c1
SS
580 /*
581 * If we are ok with PG_LEVEL_1G mapping, then we will
582 * use the existing mapping.
583 *
584 * Otherwise, we will split the gbpage mapping but use
585 * the same existing protection bits except for large
586 * page, so that we don't violate Intel's TLB
587 * Application note (317080) which says, while changing
588 * the page sizes, new and old translations should
589 * not differ with respect to page frame and
590 * attributes.
591 */
3afa3949 592 if (page_size_mask & (1 << PG_LEVEL_1G)) {
876ee61a
JB
593 if (!after_bootmem)
594 pages++;
59b3d020 595 paddr_last = paddr_next;
b27a43c1 596 continue;
3afa3949 597 }
b27a43c1 598 prot = pte_pgprot(pte_clrhuge(*(pte_t *)pud));
ef925766
AK
599 }
600
b50efd2a 601 if (page_size_mask & (1<<PG_LEVEL_1G)) {
ce0c0e50 602 pages++;
8ae3a5a8 603 spin_lock(&init_mm.page_table_lock);
ef925766 604 set_pte((pte_t *)pud,
59b3d020 605 pfn_pte((paddr & PUD_MASK) >> PAGE_SHIFT,
960ddb4f 606 PAGE_KERNEL_LARGE));
8ae3a5a8 607 spin_unlock(&init_mm.page_table_lock);
59b3d020 608 paddr_last = paddr_next;
6ad91658
KM
609 continue;
610 }
611
868bf4d6 612 pmd = alloc_low_page();
59b3d020
TG
613 paddr_last = phys_pmd_init(pmd, paddr, paddr_end,
614 page_size_mask, prot);
8ae3a5a8
JB
615
616 spin_lock(&init_mm.page_table_lock);
868bf4d6 617 pud_populate(&init_mm, pud, pmd);
44df75e6 618 spin_unlock(&init_mm.page_table_lock);
1da177e4 619 }
1a2b4412 620 __flush_tlb_all();
a2699e47 621
ce0c0e50 622 update_page_count(PG_LEVEL_1G, pages);
cc615032 623
59b3d020 624 return paddr_last;
14a62c34 625}
1da177e4 626
7e82ea94
KS
627static unsigned long __meminit
628phys_p4d_init(p4d_t *p4d_page, unsigned long paddr, unsigned long paddr_end,
629 unsigned long page_size_mask)
630{
631 unsigned long paddr_next, paddr_last = paddr_end;
632 unsigned long vaddr = (unsigned long)__va(paddr);
633 int i = p4d_index(vaddr);
634
635 if (!IS_ENABLED(CONFIG_X86_5LEVEL))
636 return phys_pud_init((pud_t *) p4d_page, paddr, paddr_end, page_size_mask);
637
638 for (; i < PTRS_PER_P4D; i++, paddr = paddr_next) {
639 p4d_t *p4d;
640 pud_t *pud;
641
642 vaddr = (unsigned long)__va(paddr);
643 p4d = p4d_page + p4d_index(vaddr);
644 paddr_next = (paddr & P4D_MASK) + P4D_SIZE;
645
646 if (paddr >= paddr_end) {
647 if (!after_bootmem &&
648 !e820__mapped_any(paddr & P4D_MASK, paddr_next,
649 E820_TYPE_RAM) &&
650 !e820__mapped_any(paddr & P4D_MASK, paddr_next,
651 E820_TYPE_RESERVED_KERN))
652 set_p4d(p4d, __p4d(0));
653 continue;
654 }
655
656 if (!p4d_none(*p4d)) {
657 pud = pud_offset(p4d, 0);
658 paddr_last = phys_pud_init(pud, paddr,
659 paddr_end,
660 page_size_mask);
661 __flush_tlb_all();
662 continue;
663 }
664
665 pud = alloc_low_page();
666 paddr_last = phys_pud_init(pud, paddr, paddr_end,
667 page_size_mask);
668
669 spin_lock(&init_mm.page_table_lock);
670 p4d_populate(&init_mm, p4d, pud);
671 spin_unlock(&init_mm.page_table_lock);
672 }
673 __flush_tlb_all();
674
675 return paddr_last;
676}
677
59b3d020
TG
678/*
679 * Create page table mapping for the physical memory for specific physical
faa37933 680 * addresses. The virtual and physical addresses have to be aligned on PMD level
59b3d020
TG
681 * down. It returns the last physical address mapped.
682 */
41d840e2 683unsigned long __meminit
59b3d020
TG
684kernel_physical_mapping_init(unsigned long paddr_start,
685 unsigned long paddr_end,
f765090a 686 unsigned long page_size_mask)
14a62c34 687{
9b861528 688 bool pgd_changed = false;
59b3d020 689 unsigned long vaddr, vaddr_start, vaddr_end, vaddr_next, paddr_last;
1da177e4 690
59b3d020
TG
691 paddr_last = paddr_end;
692 vaddr = (unsigned long)__va(paddr_start);
693 vaddr_end = (unsigned long)__va(paddr_end);
694 vaddr_start = vaddr;
1da177e4 695
59b3d020
TG
696 for (; vaddr < vaddr_end; vaddr = vaddr_next) {
697 pgd_t *pgd = pgd_offset_k(vaddr);
f2a6a705 698 p4d_t *p4d;
44df75e6 699
59b3d020 700 vaddr_next = (vaddr & PGDIR_MASK) + PGDIR_SIZE;
4f9c11dd 701
7e82ea94
KS
702 if (pgd_val(*pgd)) {
703 p4d = (p4d_t *)pgd_page_vaddr(*pgd);
704 paddr_last = phys_p4d_init(p4d, __pa(vaddr),
59b3d020
TG
705 __pa(vaddr_end),
706 page_size_mask);
4f9c11dd
JF
707 continue;
708 }
709
7e82ea94
KS
710 p4d = alloc_low_page();
711 paddr_last = phys_p4d_init(p4d, __pa(vaddr), __pa(vaddr_end),
59b3d020 712 page_size_mask);
8ae3a5a8
JB
713
714 spin_lock(&init_mm.page_table_lock);
7e82ea94
KS
715 if (IS_ENABLED(CONFIG_X86_5LEVEL))
716 pgd_populate(&init_mm, pgd, p4d);
717 else
718 p4d_populate(&init_mm, p4d_offset(pgd, vaddr), (pud_t *) p4d);
8ae3a5a8 719 spin_unlock(&init_mm.page_table_lock);
9b861528 720 pgd_changed = true;
14a62c34 721 }
9b861528
HL
722
723 if (pgd_changed)
5372e155 724 sync_global_pgds(vaddr_start, vaddr_end - 1);
9b861528 725
a2699e47 726 __flush_tlb_all();
1da177e4 727
59b3d020 728 return paddr_last;
b50efd2a 729}
7b16eb89 730
2b97690f 731#ifndef CONFIG_NUMA
d8fc3afc 732void __init initmem_init(void)
1f75d7e3 733{
e7e8de59 734 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1f75d7e3 735}
3551f88f 736#endif
1f75d7e3 737
1da177e4
LT
738void __init paging_init(void)
739{
3551f88f 740 sparse_memory_present_with_active_regions(MAX_NUMNODES);
44df75e6 741 sparse_init();
44b57280
YL
742
743 /*
744 * clear the default setting with node 0
745 * note: don't use nodes_clear here, that is really clearing when
746 * numa support is not compiled in, and later node_set_state
747 * will not set it back.
748 */
4b0ef1fe
LJ
749 node_clear_state(0, N_MEMORY);
750 if (N_MEMORY != N_NORMAL_MEMORY)
751 node_clear_state(0, N_NORMAL_MEMORY);
44b57280 752
4c0b2e5f 753 zone_sizes_init();
1da177e4 754}
1da177e4 755
44df75e6
MT
756/*
757 * Memory hotplug specific functions
44df75e6 758 */
bc02af93 759#ifdef CONFIG_MEMORY_HOTPLUG
ea085417
SZ
760/*
761 * After memory hotplug the variables max_pfn, max_low_pfn and high_memory need
762 * updating.
763 */
3072e413 764static void update_end_of_memory_vars(u64 start, u64 size)
ea085417
SZ
765{
766 unsigned long end_pfn = PFN_UP(start + size);
767
768 if (end_pfn > max_pfn) {
769 max_pfn = end_pfn;
770 max_low_pfn = end_pfn;
771 high_memory = (void *)__va(max_pfn * PAGE_SIZE - 1) + 1;
772 }
773}
774
24e6d5a5
CH
775int add_pages(int nid, unsigned long start_pfn, unsigned long nr_pages,
776 struct vmem_altmap *altmap, bool want_memblock)
44df75e6 777{
44df75e6
MT
778 int ret;
779
24e6d5a5 780 ret = __add_pages(nid, start_pfn, nr_pages, altmap, want_memblock);
fe8b868e 781 WARN_ON_ONCE(ret);
44df75e6 782
ea085417 783 /* update max_pfn, max_low_pfn and high_memory */
3072e413
MH
784 update_end_of_memory_vars(start_pfn << PAGE_SHIFT,
785 nr_pages << PAGE_SHIFT);
ea085417 786
44df75e6 787 return ret;
44df75e6 788}
3072e413 789
24e6d5a5
CH
790int arch_add_memory(int nid, u64 start, u64 size, struct vmem_altmap *altmap,
791 bool want_memblock)
3072e413
MH
792{
793 unsigned long start_pfn = start >> PAGE_SHIFT;
794 unsigned long nr_pages = size >> PAGE_SHIFT;
795
796 init_memory_mapping(start, start + size);
797
24e6d5a5 798 return add_pages(nid, start_pfn, nr_pages, altmap, want_memblock);
3072e413 799}
44df75e6 800
ae9aae9e
WC
801#define PAGE_INUSE 0xFD
802
24b6d416
CH
803static void __meminit free_pagetable(struct page *page, int order,
804 struct vmem_altmap *altmap)
ae9aae9e 805{
ae9aae9e
WC
806 unsigned long magic;
807 unsigned int nr_pages = 1 << order;
4b94ffdc
DW
808
809 if (altmap) {
810 vmem_altmap_free(altmap, nr_pages);
811 return;
812 }
ae9aae9e
WC
813
814 /* bootmem page has reserved flag */
815 if (PageReserved(page)) {
816 __ClearPageReserved(page);
ae9aae9e 817
ddffe98d 818 magic = (unsigned long)page->freelist;
ae9aae9e
WC
819 if (magic == SECTION_INFO || magic == MIX_SECTION_INFO) {
820 while (nr_pages--)
821 put_page_bootmem(page++);
822 } else
170a5a7e
JL
823 while (nr_pages--)
824 free_reserved_page(page++);
ae9aae9e
WC
825 } else
826 free_pages((unsigned long)page_address(page), order);
ae9aae9e
WC
827}
828
24b6d416
CH
829static void __meminit free_pte_table(pte_t *pte_start, pmd_t *pmd,
830 struct vmem_altmap *altmap)
ae9aae9e
WC
831{
832 pte_t *pte;
833 int i;
834
835 for (i = 0; i < PTRS_PER_PTE; i++) {
836 pte = pte_start + i;
dcb32d99 837 if (!pte_none(*pte))
ae9aae9e
WC
838 return;
839 }
840
841 /* free a pte talbe */
24b6d416 842 free_pagetable(pmd_page(*pmd), 0, altmap);
ae9aae9e
WC
843 spin_lock(&init_mm.page_table_lock);
844 pmd_clear(pmd);
845 spin_unlock(&init_mm.page_table_lock);
846}
847
24b6d416
CH
848static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud,
849 struct vmem_altmap *altmap)
ae9aae9e
WC
850{
851 pmd_t *pmd;
852 int i;
853
854 for (i = 0; i < PTRS_PER_PMD; i++) {
855 pmd = pmd_start + i;
dcb32d99 856 if (!pmd_none(*pmd))
ae9aae9e
WC
857 return;
858 }
859
860 /* free a pmd talbe */
24b6d416 861 free_pagetable(pud_page(*pud), 0, altmap);
ae9aae9e
WC
862 spin_lock(&init_mm.page_table_lock);
863 pud_clear(pud);
864 spin_unlock(&init_mm.page_table_lock);
865}
866
24b6d416
CH
867static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d,
868 struct vmem_altmap *altmap)
f2a6a705
KS
869{
870 pud_t *pud;
871 int i;
872
873 for (i = 0; i < PTRS_PER_PUD; i++) {
874 pud = pud_start + i;
875 if (!pud_none(*pud))
876 return;
877 }
878
879 /* free a pud talbe */
24b6d416 880 free_pagetable(p4d_page(*p4d), 0, altmap);
f2a6a705
KS
881 spin_lock(&init_mm.page_table_lock);
882 p4d_clear(p4d);
883 spin_unlock(&init_mm.page_table_lock);
884}
885
ae9aae9e
WC
886static void __meminit
887remove_pte_table(pte_t *pte_start, unsigned long addr, unsigned long end,
24b6d416 888 struct vmem_altmap *altmap, bool direct)
ae9aae9e
WC
889{
890 unsigned long next, pages = 0;
891 pte_t *pte;
892 void *page_addr;
893 phys_addr_t phys_addr;
894
895 pte = pte_start + pte_index(addr);
896 for (; addr < end; addr = next, pte++) {
897 next = (addr + PAGE_SIZE) & PAGE_MASK;
898 if (next > end)
899 next = end;
900
901 if (!pte_present(*pte))
902 continue;
903
904 /*
905 * We mapped [0,1G) memory as identity mapping when
906 * initializing, in arch/x86/kernel/head_64.S. These
907 * pagetables cannot be removed.
908 */
909 phys_addr = pte_val(*pte) + (addr & PAGE_MASK);
910 if (phys_addr < (phys_addr_t)0x40000000)
911 return;
912
b500f77b 913 if (PAGE_ALIGNED(addr) && PAGE_ALIGNED(next)) {
ae9aae9e
WC
914 /*
915 * Do not free direct mapping pages since they were
916 * freed when offlining, or simplely not in use.
917 */
918 if (!direct)
24b6d416 919 free_pagetable(pte_page(*pte), 0, altmap);
ae9aae9e
WC
920
921 spin_lock(&init_mm.page_table_lock);
922 pte_clear(&init_mm, addr, pte);
923 spin_unlock(&init_mm.page_table_lock);
924
925 /* For non-direct mapping, pages means nothing. */
926 pages++;
927 } else {
928 /*
929 * If we are here, we are freeing vmemmap pages since
930 * direct mapped memory ranges to be freed are aligned.
931 *
932 * If we are not removing the whole page, it means
933 * other page structs in this page are being used and
934 * we canot remove them. So fill the unused page_structs
935 * with 0xFD, and remove the page when it is wholly
936 * filled with 0xFD.
937 */
938 memset((void *)addr, PAGE_INUSE, next - addr);
939
940 page_addr = page_address(pte_page(*pte));
941 if (!memchr_inv(page_addr, PAGE_INUSE, PAGE_SIZE)) {
24b6d416 942 free_pagetable(pte_page(*pte), 0, altmap);
ae9aae9e
WC
943
944 spin_lock(&init_mm.page_table_lock);
945 pte_clear(&init_mm, addr, pte);
946 spin_unlock(&init_mm.page_table_lock);
947 }
948 }
949 }
950
951 /* Call free_pte_table() in remove_pmd_table(). */
952 flush_tlb_all();
953 if (direct)
954 update_page_count(PG_LEVEL_4K, -pages);
955}
956
957static void __meminit
958remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
24b6d416 959 bool direct, struct vmem_altmap *altmap)
ae9aae9e
WC
960{
961 unsigned long next, pages = 0;
962 pte_t *pte_base;
963 pmd_t *pmd;
964 void *page_addr;
965
966 pmd = pmd_start + pmd_index(addr);
967 for (; addr < end; addr = next, pmd++) {
968 next = pmd_addr_end(addr, end);
969
970 if (!pmd_present(*pmd))
971 continue;
972
973 if (pmd_large(*pmd)) {
974 if (IS_ALIGNED(addr, PMD_SIZE) &&
975 IS_ALIGNED(next, PMD_SIZE)) {
976 if (!direct)
977 free_pagetable(pmd_page(*pmd),
24b6d416
CH
978 get_order(PMD_SIZE),
979 altmap);
ae9aae9e
WC
980
981 spin_lock(&init_mm.page_table_lock);
982 pmd_clear(pmd);
983 spin_unlock(&init_mm.page_table_lock);
984 pages++;
985 } else {
986 /* If here, we are freeing vmemmap pages. */
987 memset((void *)addr, PAGE_INUSE, next - addr);
988
989 page_addr = page_address(pmd_page(*pmd));
990 if (!memchr_inv(page_addr, PAGE_INUSE,
991 PMD_SIZE)) {
992 free_pagetable(pmd_page(*pmd),
24b6d416
CH
993 get_order(PMD_SIZE),
994 altmap);
ae9aae9e
WC
995
996 spin_lock(&init_mm.page_table_lock);
997 pmd_clear(pmd);
998 spin_unlock(&init_mm.page_table_lock);
999 }
1000 }
1001
1002 continue;
1003 }
1004
1005 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
24b6d416
CH
1006 remove_pte_table(pte_base, addr, next, altmap, direct);
1007 free_pte_table(pte_base, pmd, altmap);
ae9aae9e
WC
1008 }
1009
1010 /* Call free_pmd_table() in remove_pud_table(). */
1011 if (direct)
1012 update_page_count(PG_LEVEL_2M, -pages);
1013}
1014
1015static void __meminit
1016remove_pud_table(pud_t *pud_start, unsigned long addr, unsigned long end,
24b6d416 1017 struct vmem_altmap *altmap, bool direct)
ae9aae9e
WC
1018{
1019 unsigned long next, pages = 0;
1020 pmd_t *pmd_base;
1021 pud_t *pud;
1022 void *page_addr;
1023
1024 pud = pud_start + pud_index(addr);
1025 for (; addr < end; addr = next, pud++) {
1026 next = pud_addr_end(addr, end);
1027
1028 if (!pud_present(*pud))
1029 continue;
1030
1031 if (pud_large(*pud)) {
1032 if (IS_ALIGNED(addr, PUD_SIZE) &&
1033 IS_ALIGNED(next, PUD_SIZE)) {
1034 if (!direct)
1035 free_pagetable(pud_page(*pud),
24b6d416
CH
1036 get_order(PUD_SIZE),
1037 altmap);
ae9aae9e
WC
1038
1039 spin_lock(&init_mm.page_table_lock);
1040 pud_clear(pud);
1041 spin_unlock(&init_mm.page_table_lock);
1042 pages++;
1043 } else {
1044 /* If here, we are freeing vmemmap pages. */
1045 memset((void *)addr, PAGE_INUSE, next - addr);
1046
1047 page_addr = page_address(pud_page(*pud));
1048 if (!memchr_inv(page_addr, PAGE_INUSE,
1049 PUD_SIZE)) {
1050 free_pagetable(pud_page(*pud),
24b6d416
CH
1051 get_order(PUD_SIZE),
1052 altmap);
ae9aae9e
WC
1053
1054 spin_lock(&init_mm.page_table_lock);
1055 pud_clear(pud);
1056 spin_unlock(&init_mm.page_table_lock);
1057 }
1058 }
1059
1060 continue;
1061 }
1062
e6ab9c4d 1063 pmd_base = pmd_offset(pud, 0);
24b6d416
CH
1064 remove_pmd_table(pmd_base, addr, next, direct, altmap);
1065 free_pmd_table(pmd_base, pud, altmap);
ae9aae9e
WC
1066 }
1067
1068 if (direct)
1069 update_page_count(PG_LEVEL_1G, -pages);
1070}
1071
f2a6a705
KS
1072static void __meminit
1073remove_p4d_table(p4d_t *p4d_start, unsigned long addr, unsigned long end,
24b6d416 1074 struct vmem_altmap *altmap, bool direct)
f2a6a705
KS
1075{
1076 unsigned long next, pages = 0;
1077 pud_t *pud_base;
1078 p4d_t *p4d;
1079
1080 p4d = p4d_start + p4d_index(addr);
1081 for (; addr < end; addr = next, p4d++) {
1082 next = p4d_addr_end(addr, end);
1083
1084 if (!p4d_present(*p4d))
1085 continue;
1086
1087 BUILD_BUG_ON(p4d_large(*p4d));
1088
e6ab9c4d 1089 pud_base = pud_offset(p4d, 0);
24b6d416 1090 remove_pud_table(pud_base, addr, next, altmap, direct);
98fe3633
JG
1091 /*
1092 * For 4-level page tables we do not want to free PUDs, but in the
1093 * 5-level case we should free them. This code will have to change
1094 * to adapt for boot-time switching between 4 and 5 level page tables.
1095 */
1096 if (CONFIG_PGTABLE_LEVELS == 5)
24b6d416 1097 free_pud_table(pud_base, p4d, altmap);
f2a6a705
KS
1098 }
1099
1100 if (direct)
1101 update_page_count(PG_LEVEL_512G, -pages);
1102}
1103
ae9aae9e
WC
1104/* start and end are both virtual address. */
1105static void __meminit
24b6d416
CH
1106remove_pagetable(unsigned long start, unsigned long end, bool direct,
1107 struct vmem_altmap *altmap)
ae9aae9e
WC
1108{
1109 unsigned long next;
5255e0a7 1110 unsigned long addr;
ae9aae9e 1111 pgd_t *pgd;
f2a6a705 1112 p4d_t *p4d;
ae9aae9e 1113
5255e0a7
YI
1114 for (addr = start; addr < end; addr = next) {
1115 next = pgd_addr_end(addr, end);
ae9aae9e 1116
5255e0a7 1117 pgd = pgd_offset_k(addr);
ae9aae9e
WC
1118 if (!pgd_present(*pgd))
1119 continue;
1120
e6ab9c4d 1121 p4d = p4d_offset(pgd, 0);
24b6d416 1122 remove_p4d_table(p4d, addr, next, altmap, direct);
ae9aae9e
WC
1123 }
1124
ae9aae9e
WC
1125 flush_tlb_all();
1126}
1127
24b6d416
CH
1128void __ref vmemmap_free(unsigned long start, unsigned long end,
1129 struct vmem_altmap *altmap)
0197518c 1130{
24b6d416 1131 remove_pagetable(start, end, false, altmap);
0197518c
TC
1132}
1133
587ff8c4 1134#ifdef CONFIG_MEMORY_HOTREMOVE
bbcab878
TC
1135static void __meminit
1136kernel_physical_mapping_remove(unsigned long start, unsigned long end)
1137{
1138 start = (unsigned long)__va(start);
1139 end = (unsigned long)__va(end);
1140
24b6d416 1141 remove_pagetable(start, end, true, NULL);
bbcab878
TC
1142}
1143
da024512 1144int __ref arch_remove_memory(u64 start, u64 size, struct vmem_altmap *altmap)
24d335ca
WC
1145{
1146 unsigned long start_pfn = start >> PAGE_SHIFT;
1147 unsigned long nr_pages = size >> PAGE_SHIFT;
4b94ffdc 1148 struct page *page = pfn_to_page(start_pfn);
24d335ca
WC
1149 struct zone *zone;
1150 int ret;
1151
4b94ffdc 1152 /* With altmap the first mapped page is offset from @start */
4b94ffdc
DW
1153 if (altmap)
1154 page += vmem_altmap_offset(altmap);
1155 zone = page_zone(page);
da024512 1156 ret = __remove_pages(zone, start_pfn, nr_pages, altmap);
24d335ca 1157 WARN_ON_ONCE(ret);
4b94ffdc 1158 kernel_physical_mapping_remove(start, start + size);
24d335ca
WC
1159
1160 return ret;
1161}
1162#endif
45e0b78b
KM
1163#endif /* CONFIG_MEMORY_HOTPLUG */
1164
81ac3ad9 1165static struct kcore_list kcore_vsyscall;
1da177e4 1166
94b43c3d
YL
1167static void __init register_page_bootmem_info(void)
1168{
1169#ifdef CONFIG_NUMA
1170 int i;
1171
1172 for_each_online_node(i)
1173 register_page_bootmem_info_node(NODE_DATA(i));
1174#endif
1175}
1176
1da177e4
LT
1177void __init mem_init(void)
1178{
0dc243ae 1179 pci_iommu_alloc();
1da177e4 1180
48ddb154 1181 /* clear_bss() already clear the empty_zero_page */
1da177e4 1182
bced0e32 1183 /* this will put all memory onto the freelists */
0c988534 1184 free_all_bootmem();
1da177e4
LT
1185 after_bootmem = 1;
1186
353b1e7b
PT
1187 /*
1188 * Must be done after boot memory is put on freelist, because here we
1189 * might set fields in deferred struct pages that have not yet been
1190 * initialized, and free_all_bootmem() initializes all the reserved
1191 * deferred pages for us.
1192 */
1193 register_page_bootmem_info();
1194
1da177e4 1195 /* Register memory areas for /proc/kcore */
f40c3300
AL
1196 kclist_add(&kcore_vsyscall, (void *)VSYSCALL_ADDR,
1197 PAGE_SIZE, KCORE_OTHER);
1da177e4 1198
46a84132 1199 mem_init_print_info(NULL);
1da177e4
LT
1200}
1201
502f6604 1202int kernel_set_to_readonly;
16239630
SR
1203
1204void set_kernel_text_rw(void)
1205{
b9af7c0d 1206 unsigned long start = PFN_ALIGN(_text);
e7d23dde 1207 unsigned long end = PFN_ALIGN(__stop___ex_table);
16239630
SR
1208
1209 if (!kernel_set_to_readonly)
1210 return;
1211
1212 pr_debug("Set kernel text: %lx - %lx for read write\n",
1213 start, end);
1214
e7d23dde
SS
1215 /*
1216 * Make the kernel identity mapping for text RW. Kernel text
1217 * mapping will always be RO. Refer to the comment in
1218 * static_protections() in pageattr.c
1219 */
16239630
SR
1220 set_memory_rw(start, (end - start) >> PAGE_SHIFT);
1221}
1222
1223void set_kernel_text_ro(void)
1224{
b9af7c0d 1225 unsigned long start = PFN_ALIGN(_text);
e7d23dde 1226 unsigned long end = PFN_ALIGN(__stop___ex_table);
16239630
SR
1227
1228 if (!kernel_set_to_readonly)
1229 return;
1230
1231 pr_debug("Set kernel text: %lx - %lx for read only\n",
1232 start, end);
1233
e7d23dde
SS
1234 /*
1235 * Set the kernel identity mapping for text RO.
1236 */
16239630
SR
1237 set_memory_ro(start, (end - start) >> PAGE_SHIFT);
1238}
1239
67df197b
AV
1240void mark_rodata_ro(void)
1241{
74e08179 1242 unsigned long start = PFN_ALIGN(_text);
fc8d7826 1243 unsigned long rodata_start = PFN_ALIGN(__start_rodata);
74e08179 1244 unsigned long end = (unsigned long) &__end_rodata_hpage_align;
fc8d7826
AD
1245 unsigned long text_end = PFN_ALIGN(&__stop___ex_table);
1246 unsigned long rodata_end = PFN_ALIGN(&__end_rodata);
45e2a9d4 1247 unsigned long all_end;
8f0f996e 1248
6fb14755 1249 printk(KERN_INFO "Write protecting the kernel read-only data: %luk\n",
e3ebadd9 1250 (end - start) >> 10);
984bb80d
AV
1251 set_memory_ro(start, (end - start) >> PAGE_SHIFT);
1252
16239630
SR
1253 kernel_set_to_readonly = 1;
1254
984bb80d 1255 /*
72212675
YL
1256 * The rodata/data/bss/brk section (but not the kernel text!)
1257 * should also be not-executable.
45e2a9d4
KC
1258 *
1259 * We align all_end to PMD_SIZE because the existing mapping
1260 * is a full PMD. If we would align _brk_end to PAGE_SIZE we
1261 * split the PMD and the reminder between _brk_end and the end
1262 * of the PMD will remain mapped executable.
1263 *
1264 * Any PMD which was setup after the one which covers _brk_end
1265 * has been zapped already via cleanup_highmem().
984bb80d 1266 */
45e2a9d4 1267 all_end = roundup((unsigned long)_brk_end, PMD_SIZE);
ab76f7b4 1268 set_memory_nx(text_end, (all_end - text_end) >> PAGE_SHIFT);
67df197b 1269
0c42f392 1270#ifdef CONFIG_CPA_DEBUG
10f22dde 1271 printk(KERN_INFO "Testing CPA: undo %lx-%lx\n", start, end);
6d238cc4 1272 set_memory_rw(start, (end-start) >> PAGE_SHIFT);
0c42f392 1273
10f22dde 1274 printk(KERN_INFO "Testing CPA: again\n");
6d238cc4 1275 set_memory_ro(start, (end-start) >> PAGE_SHIFT);
0c42f392 1276#endif
74e08179 1277
c88442ec 1278 free_init_pages("unused kernel",
fc8d7826
AD
1279 (unsigned long) __va(__pa_symbol(text_end)),
1280 (unsigned long) __va(__pa_symbol(rodata_start)));
c88442ec 1281 free_init_pages("unused kernel",
fc8d7826
AD
1282 (unsigned long) __va(__pa_symbol(rodata_end)),
1283 (unsigned long) __va(__pa_symbol(_sdata)));
e1a58320
SS
1284
1285 debug_checkwx();
67df197b 1286}
4e4eee0e 1287
14a62c34
TG
1288int kern_addr_valid(unsigned long addr)
1289{
1da177e4 1290 unsigned long above = ((long)addr) >> __VIRTUAL_MASK_SHIFT;
14a62c34 1291 pgd_t *pgd;
f2a6a705 1292 p4d_t *p4d;
14a62c34
TG
1293 pud_t *pud;
1294 pmd_t *pmd;
1295 pte_t *pte;
1da177e4
LT
1296
1297 if (above != 0 && above != -1UL)
14a62c34
TG
1298 return 0;
1299
1da177e4
LT
1300 pgd = pgd_offset_k(addr);
1301 if (pgd_none(*pgd))
1302 return 0;
1303
f2a6a705
KS
1304 p4d = p4d_offset(pgd, addr);
1305 if (p4d_none(*p4d))
1306 return 0;
1307
1308 pud = pud_offset(p4d, addr);
1da177e4 1309 if (pud_none(*pud))
14a62c34 1310 return 0;
1da177e4 1311
0ee364eb
MG
1312 if (pud_large(*pud))
1313 return pfn_valid(pud_pfn(*pud));
1314
1da177e4
LT
1315 pmd = pmd_offset(pud, addr);
1316 if (pmd_none(*pmd))
1317 return 0;
14a62c34 1318
1da177e4
LT
1319 if (pmd_large(*pmd))
1320 return pfn_valid(pmd_pfn(*pmd));
1321
1322 pte = pte_offset_kernel(pmd, addr);
1323 if (pte_none(*pte))
1324 return 0;
14a62c34 1325
1da177e4
LT
1326 return pfn_valid(pte_pfn(*pte));
1327}
1328
982792c7 1329static unsigned long probe_memory_block_size(void)
1dc41aa6 1330{
43c75f93 1331 unsigned long bz = MIN_MEMORY_BLOCK_SIZE;
982792c7 1332
43c75f93
SJ
1333 /* if system is UV or has 64GB of RAM or more, use large blocks */
1334 if (is_uv_system() || ((max_pfn << PAGE_SHIFT) >= (64UL << 30)))
1335 bz = 2UL << 30; /* 2GB */
982792c7 1336
43c75f93 1337 pr_info("x86/mm: Memory block size: %ldMB\n", bz >> 20);
982792c7
YL
1338
1339 return bz;
1340}
1341
1342static unsigned long memory_block_size_probed;
1343unsigned long memory_block_size_bytes(void)
1344{
1345 if (!memory_block_size_probed)
1346 memory_block_size_probed = probe_memory_block_size();
1347
1348 return memory_block_size_probed;
1349}
1350
0889eba5
CL
1351#ifdef CONFIG_SPARSEMEM_VMEMMAP
1352/*
1353 * Initialise the sparsemem vmemmap using huge-pages at the PMD level.
1354 */
c2b91e2e
YL
1355static long __meminitdata addr_start, addr_end;
1356static void __meminitdata *p_start, *p_end;
1357static int __meminitdata node_start;
1358
e8216da5 1359static int __meminit vmemmap_populate_hugepages(unsigned long start,
4b94ffdc 1360 unsigned long end, int node, struct vmem_altmap *altmap)
0889eba5 1361{
0aad818b 1362 unsigned long addr;
0889eba5
CL
1363 unsigned long next;
1364 pgd_t *pgd;
f2a6a705 1365 p4d_t *p4d;
0889eba5
CL
1366 pud_t *pud;
1367 pmd_t *pmd;
1368
0aad818b 1369 for (addr = start; addr < end; addr = next) {
e8216da5 1370 next = pmd_addr_end(addr, end);
0889eba5
CL
1371
1372 pgd = vmemmap_pgd_populate(addr, node);
1373 if (!pgd)
1374 return -ENOMEM;
14a62c34 1375
f2a6a705
KS
1376 p4d = vmemmap_p4d_populate(pgd, addr, node);
1377 if (!p4d)
1378 return -ENOMEM;
1379
1380 pud = vmemmap_pud_populate(p4d, addr, node);
0889eba5
CL
1381 if (!pud)
1382 return -ENOMEM;
1383
e8216da5
JW
1384 pmd = pmd_offset(pud, addr);
1385 if (pmd_none(*pmd)) {
e8216da5 1386 void *p;
14a62c34 1387
4b94ffdc 1388 p = __vmemmap_alloc_block_buf(PMD_SIZE, node, altmap);
8e2cdbcb
JW
1389 if (p) {
1390 pte_t entry;
1391
1392 entry = pfn_pte(__pa(p) >> PAGE_SHIFT,
1393 PAGE_KERNEL_LARGE);
1394 set_pmd(pmd, __pmd(pte_val(entry)));
1395
1396 /* check to see if we have contiguous blocks */
1397 if (p_end != p || node_start != node) {
1398 if (p_start)
c9cdaeb2 1399 pr_debug(" [%lx-%lx] PMD -> [%p-%p] on node %d\n",
8e2cdbcb
JW
1400 addr_start, addr_end-1, p_start, p_end-1, node_start);
1401 addr_start = addr;
1402 node_start = node;
1403 p_start = p;
1404 }
7c934d39 1405
8e2cdbcb
JW
1406 addr_end = addr + PMD_SIZE;
1407 p_end = p + PMD_SIZE;
1408 continue;
4b94ffdc
DW
1409 } else if (altmap)
1410 return -ENOMEM; /* no fallback */
8e2cdbcb 1411 } else if (pmd_large(*pmd)) {
e8216da5 1412 vmemmap_verify((pte_t *)pmd, node, addr, next);
8e2cdbcb
JW
1413 continue;
1414 }
8e2cdbcb
JW
1415 if (vmemmap_populate_basepages(addr, next, node))
1416 return -ENOMEM;
0889eba5 1417 }
0889eba5
CL
1418 return 0;
1419}
c2b91e2e 1420
7b73d978
CH
1421int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node,
1422 struct vmem_altmap *altmap)
e8216da5
JW
1423{
1424 int err;
1425
16bf9226 1426 if (boot_cpu_has(X86_FEATURE_PSE))
4b94ffdc
DW
1427 err = vmemmap_populate_hugepages(start, end, node, altmap);
1428 else if (altmap) {
1429 pr_err_once("%s: no cpu support for altmap allocations\n",
1430 __func__);
1431 err = -ENOMEM;
1432 } else
e8216da5
JW
1433 err = vmemmap_populate_basepages(start, end, node);
1434 if (!err)
5372e155 1435 sync_global_pgds(start, end - 1);
e8216da5
JW
1436 return err;
1437}
1438
46723bfa
YI
1439#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE) && defined(CONFIG_HAVE_BOOTMEM_INFO_NODE)
1440void register_page_bootmem_memmap(unsigned long section_nr,
15670bfe 1441 struct page *start_page, unsigned long nr_pages)
46723bfa
YI
1442{
1443 unsigned long addr = (unsigned long)start_page;
15670bfe 1444 unsigned long end = (unsigned long)(start_page + nr_pages);
46723bfa
YI
1445 unsigned long next;
1446 pgd_t *pgd;
f2a6a705 1447 p4d_t *p4d;
46723bfa
YI
1448 pud_t *pud;
1449 pmd_t *pmd;
15670bfe 1450 unsigned int nr_pmd_pages;
46723bfa
YI
1451 struct page *page;
1452
1453 for (; addr < end; addr = next) {
1454 pte_t *pte = NULL;
1455
1456 pgd = pgd_offset_k(addr);
1457 if (pgd_none(*pgd)) {
1458 next = (addr + PAGE_SIZE) & PAGE_MASK;
1459 continue;
1460 }
1461 get_page_bootmem(section_nr, pgd_page(*pgd), MIX_SECTION_INFO);
1462
f2a6a705
KS
1463 p4d = p4d_offset(pgd, addr);
1464 if (p4d_none(*p4d)) {
1465 next = (addr + PAGE_SIZE) & PAGE_MASK;
1466 continue;
1467 }
1468 get_page_bootmem(section_nr, p4d_page(*p4d), MIX_SECTION_INFO);
1469
1470 pud = pud_offset(p4d, addr);
46723bfa
YI
1471 if (pud_none(*pud)) {
1472 next = (addr + PAGE_SIZE) & PAGE_MASK;
1473 continue;
1474 }
1475 get_page_bootmem(section_nr, pud_page(*pud), MIX_SECTION_INFO);
1476
16bf9226 1477 if (!boot_cpu_has(X86_FEATURE_PSE)) {
46723bfa
YI
1478 next = (addr + PAGE_SIZE) & PAGE_MASK;
1479 pmd = pmd_offset(pud, addr);
1480 if (pmd_none(*pmd))
1481 continue;
1482 get_page_bootmem(section_nr, pmd_page(*pmd),
1483 MIX_SECTION_INFO);
1484
1485 pte = pte_offset_kernel(pmd, addr);
1486 if (pte_none(*pte))
1487 continue;
1488 get_page_bootmem(section_nr, pte_page(*pte),
1489 SECTION_INFO);
1490 } else {
1491 next = pmd_addr_end(addr, end);
1492
1493 pmd = pmd_offset(pud, addr);
1494 if (pmd_none(*pmd))
1495 continue;
1496
15670bfe 1497 nr_pmd_pages = 1 << get_order(PMD_SIZE);
46723bfa 1498 page = pmd_page(*pmd);
15670bfe 1499 while (nr_pmd_pages--)
46723bfa
YI
1500 get_page_bootmem(section_nr, page++,
1501 SECTION_INFO);
1502 }
1503 }
1504}
1505#endif
1506
c2b91e2e
YL
1507void __meminit vmemmap_populate_print_last(void)
1508{
1509 if (p_start) {
c9cdaeb2 1510 pr_debug(" [%lx-%lx] PMD -> [%p-%p] on node %d\n",
c2b91e2e
YL
1511 addr_start, addr_end-1, p_start, p_end-1, node_start);
1512 p_start = NULL;
1513 p_end = NULL;
1514 node_start = 0;
1515 }
1516}
0889eba5 1517#endif