Commit | Line | Data |
---|---|---|
f938d2c8 RR |
1 | /*P:010 |
2 | * A hypervisor allows multiple Operating Systems to run on a single machine. | |
3 | * To quote David Wheeler: "Any problem in computer science can be solved with | |
4 | * another layer of indirection." | |
5 | * | |
6 | * We keep things simple in two ways. First, we start with a normal Linux | |
7 | * kernel and insert a module (lg.ko) which allows us to run other Linux | |
8 | * kernels the same way we'd run processes. We call the first kernel the Host, | |
9 | * and the others the Guests. The program which sets up and configures Guests | |
b21e332d | 10 | * (such as the example in tools/lguest/lguest.c) is called the Launcher. |
f938d2c8 | 11 | * |
a6bd8e13 RR |
12 | * Secondly, we only run specially modified Guests, not normal kernels: setting |
13 | * CONFIG_LGUEST_GUEST to "y" compiles this file into the kernel so it knows | |
14 | * how to be a Guest at boot time. This means that you can use the same kernel | |
15 | * you boot normally (ie. as a Host) as a Guest. | |
07ad157f | 16 | * |
f938d2c8 RR |
17 | * These Guests know that they cannot do privileged operations, such as disable |
18 | * interrupts, and that they have to ask the Host to do such things explicitly. | |
19 | * This file consists of all the replacements for such low-level native | |
20 | * hardware operations: these special Guest versions call the Host. | |
21 | * | |
a6bd8e13 RR |
22 | * So how does the kernel know it's a Guest? We'll see that later, but let's |
23 | * just say that we end up here where we replace the native functions various | |
2e04ef76 RR |
24 | * "paravirt" structures with our Guest versions, then boot like normal. |
25 | :*/ | |
f938d2c8 RR |
26 | |
27 | /* | |
07ad157f RR |
28 | * Copyright (C) 2006, Rusty Russell <rusty@rustcorp.com.au> IBM Corporation. |
29 | * | |
30 | * This program is free software; you can redistribute it and/or modify | |
31 | * it under the terms of the GNU General Public License as published by | |
32 | * the Free Software Foundation; either version 2 of the License, or | |
33 | * (at your option) any later version. | |
34 | * | |
35 | * This program is distributed in the hope that it will be useful, but | |
36 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
37 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
38 | * NON INFRINGEMENT. See the GNU General Public License for more | |
39 | * details. | |
40 | * | |
41 | * You should have received a copy of the GNU General Public License | |
42 | * along with this program; if not, write to the Free Software | |
43 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
44 | */ | |
45 | #include <linux/kernel.h> | |
46 | #include <linux/start_kernel.h> | |
47 | #include <linux/string.h> | |
48 | #include <linux/console.h> | |
49 | #include <linux/screen_info.h> | |
50 | #include <linux/irq.h> | |
51 | #include <linux/interrupt.h> | |
d7e28ffe RR |
52 | #include <linux/clocksource.h> |
53 | #include <linux/clockchips.h> | |
07ad157f RR |
54 | #include <linux/lguest.h> |
55 | #include <linux/lguest_launcher.h> | |
19f1537b | 56 | #include <linux/virtio_console.h> |
4cfe6c3c | 57 | #include <linux/pm.h> |
39a0e33d | 58 | #include <linux/export.h> |
e1b83e27 | 59 | #include <linux/pci.h> |
a561adfa | 60 | #include <linux/virtio_pci.h> |
ee72576c | 61 | #include <asm/acpi.h> |
7b6aa335 | 62 | #include <asm/apic.h> |
cbc34973 | 63 | #include <asm/lguest.h> |
07ad157f RR |
64 | #include <asm/paravirt.h> |
65 | #include <asm/param.h> | |
66 | #include <asm/page.h> | |
67 | #include <asm/pgtable.h> | |
68 | #include <asm/desc.h> | |
69 | #include <asm/setup.h> | |
70 | #include <asm/e820.h> | |
71 | #include <asm/mce.h> | |
72 | #include <asm/io.h> | |
df6b35f4 | 73 | #include <asm/fpu/api.h> |
2cb7878a | 74 | #include <asm/stackprotector.h> |
ec04b13f | 75 | #include <asm/reboot.h> /* for struct machine_ops */ |
89cfc991 | 76 | #include <asm/kvm_para.h> |
e1b83e27 | 77 | #include <asm/pci_x86.h> |
a561adfa | 78 | #include <asm/pci-direct.h> |
07ad157f | 79 | |
9f54288d RR |
80 | /*G:010 |
81 | * Welcome to the Guest! | |
b2b47c21 RR |
82 | * |
83 | * The Guest in our tale is a simple creature: identical to the Host but | |
84 | * behaving in simplified but equivalent ways. In particular, the Guest is the | |
2e04ef76 RR |
85 | * same kernel as the Host (or at least, built from the same source code). |
86 | :*/ | |
b2b47c21 | 87 | |
07ad157f RR |
88 | struct lguest_data lguest_data = { |
89 | .hcall_status = { [0 ... LHCALL_RING_SIZE-1] = 0xFF }, | |
2f921b5b | 90 | .noirq_iret = (u32)lguest_noirq_iret, |
47436aa4 | 91 | .kernel_address = PAGE_OFFSET, |
07ad157f | 92 | .blocked_interrupts = { 1 }, /* Block timer interrupts */ |
51bb9284 | 93 | .syscall_vec = IA32_SYSCALL_VECTOR, |
07ad157f | 94 | }; |
07ad157f | 95 | |
2e04ef76 RR |
96 | /*G:037 |
97 | * async_hcall() is pretty simple: I'm quite proud of it really. We have a | |
b2b47c21 | 98 | * ring buffer of stored hypercalls which the Host will run though next time we |
cefcad17 | 99 | * do a normal hypercall. Each entry in the ring has 5 slots for the hypercall |
b2b47c21 RR |
100 | * arguments, and a "hcall_status" word which is 0 if the call is ready to go, |
101 | * and 255 once the Host has finished with it. | |
102 | * | |
103 | * If we come around to a slot which hasn't been finished, then the table is | |
104 | * full and we just make the hypercall directly. This has the nice side | |
105 | * effect of causing the Host to run all the stored calls in the ring buffer | |
2e04ef76 RR |
106 | * which empties it for next time! |
107 | */ | |
9b56fdb4 | 108 | static void async_hcall(unsigned long call, unsigned long arg1, |
cefcad17 MZ |
109 | unsigned long arg2, unsigned long arg3, |
110 | unsigned long arg4) | |
07ad157f RR |
111 | { |
112 | /* Note: This code assumes we're uniprocessor. */ | |
113 | static unsigned int next_call; | |
114 | unsigned long flags; | |
115 | ||
2e04ef76 RR |
116 | /* |
117 | * Disable interrupts if not already disabled: we don't want an | |
b2b47c21 | 118 | * interrupt handler making a hypercall while we're already doing |
2e04ef76 RR |
119 | * one! |
120 | */ | |
07ad157f RR |
121 | local_irq_save(flags); |
122 | if (lguest_data.hcall_status[next_call] != 0xFF) { | |
123 | /* Table full, so do normal hcall which will flush table. */ | |
091ebf07 | 124 | hcall(call, arg1, arg2, arg3, arg4); |
07ad157f | 125 | } else { |
b410e7b1 JS |
126 | lguest_data.hcalls[next_call].arg0 = call; |
127 | lguest_data.hcalls[next_call].arg1 = arg1; | |
128 | lguest_data.hcalls[next_call].arg2 = arg2; | |
129 | lguest_data.hcalls[next_call].arg3 = arg3; | |
cefcad17 | 130 | lguest_data.hcalls[next_call].arg4 = arg4; |
b2b47c21 | 131 | /* Arguments must all be written before we mark it to go */ |
07ad157f RR |
132 | wmb(); |
133 | lguest_data.hcall_status[next_call] = 0; | |
134 | if (++next_call == LHCALL_RING_SIZE) | |
135 | next_call = 0; | |
136 | } | |
137 | local_irq_restore(flags); | |
138 | } | |
9b56fdb4 | 139 | |
2e04ef76 RR |
140 | /*G:035 |
141 | * Notice the lazy_hcall() above, rather than hcall(). This is our first real | |
142 | * optimization trick! | |
633872b9 RR |
143 | * |
144 | * When lazy_mode is set, it means we're allowed to defer all hypercalls and do | |
145 | * them as a batch when lazy_mode is eventually turned off. Because hypercalls | |
146 | * are reasonably expensive, batching them up makes sense. For example, a | |
147 | * large munmap might update dozens of page table entries: that code calls | |
148 | * paravirt_enter_lazy_mmu(), does the dozen updates, then calls | |
149 | * lguest_leave_lazy_mode(). | |
150 | * | |
151 | * So, when we're in lazy mode, we call async_hcall() to store the call for | |
2e04ef76 RR |
152 | * future processing: |
153 | */ | |
091ebf07 | 154 | static void lazy_hcall1(unsigned long call, unsigned long arg1) |
4cd8b5e2 MZ |
155 | { |
156 | if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE) | |
091ebf07 | 157 | hcall(call, arg1, 0, 0, 0); |
4cd8b5e2 | 158 | else |
cefcad17 | 159 | async_hcall(call, arg1, 0, 0, 0); |
4cd8b5e2 MZ |
160 | } |
161 | ||
a91d74a3 | 162 | /* You can imagine what lazy_hcall2, 3 and 4 look like. :*/ |
4cd8b5e2 | 163 | static void lazy_hcall2(unsigned long call, |
091ebf07 RR |
164 | unsigned long arg1, |
165 | unsigned long arg2) | |
4cd8b5e2 MZ |
166 | { |
167 | if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE) | |
091ebf07 | 168 | hcall(call, arg1, arg2, 0, 0); |
4cd8b5e2 | 169 | else |
cefcad17 | 170 | async_hcall(call, arg1, arg2, 0, 0); |
4cd8b5e2 MZ |
171 | } |
172 | ||
173 | static void lazy_hcall3(unsigned long call, | |
091ebf07 RR |
174 | unsigned long arg1, |
175 | unsigned long arg2, | |
176 | unsigned long arg3) | |
9b56fdb4 AB |
177 | { |
178 | if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE) | |
091ebf07 | 179 | hcall(call, arg1, arg2, arg3, 0); |
9b56fdb4 | 180 | else |
cefcad17 MZ |
181 | async_hcall(call, arg1, arg2, arg3, 0); |
182 | } | |
183 | ||
acdd0b62 | 184 | #ifdef CONFIG_X86_PAE |
cefcad17 | 185 | static void lazy_hcall4(unsigned long call, |
091ebf07 RR |
186 | unsigned long arg1, |
187 | unsigned long arg2, | |
188 | unsigned long arg3, | |
189 | unsigned long arg4) | |
cefcad17 MZ |
190 | { |
191 | if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE) | |
091ebf07 | 192 | hcall(call, arg1, arg2, arg3, arg4); |
cefcad17 MZ |
193 | else |
194 | async_hcall(call, arg1, arg2, arg3, arg4); | |
9b56fdb4 | 195 | } |
acdd0b62 | 196 | #endif |
633872b9 | 197 | |
a91d74a3 | 198 | /*G:036 |
9f54288d RR |
199 | * When lazy mode is turned off, we issue the do-nothing hypercall to |
200 | * flush any stored calls, and call the generic helper to reset the | |
201 | * per-cpu lazy mode variable. | |
202 | */ | |
b407fc57 | 203 | static void lguest_leave_lazy_mmu_mode(void) |
633872b9 | 204 | { |
091ebf07 | 205 | hcall(LHCALL_FLUSH_ASYNC, 0, 0, 0, 0); |
b407fc57 JF |
206 | paravirt_leave_lazy_mmu(); |
207 | } | |
208 | ||
9f54288d RR |
209 | /* |
210 | * We also catch the end of context switch; we enter lazy mode for much of | |
211 | * that too, so again we need to flush here. | |
212 | * | |
213 | * (Technically, this is lazy CPU mode, and normally we're in lazy MMU | |
214 | * mode, but unlike Xen, lguest doesn't care about the difference). | |
215 | */ | |
224101ed | 216 | static void lguest_end_context_switch(struct task_struct *next) |
b407fc57 | 217 | { |
091ebf07 | 218 | hcall(LHCALL_FLUSH_ASYNC, 0, 0, 0, 0); |
224101ed | 219 | paravirt_end_context_switch(next); |
633872b9 | 220 | } |
07ad157f | 221 | |
61f4bc83 | 222 | /*G:032 |
e1e72965 RR |
223 | * After that diversion we return to our first native-instruction |
224 | * replacements: four functions for interrupt control. | |
b2b47c21 RR |
225 | * |
226 | * The simplest way of implementing these would be to have "turn interrupts | |
227 | * off" and "turn interrupts on" hypercalls. Unfortunately, this is too slow: | |
228 | * these are by far the most commonly called functions of those we override. | |
229 | * | |
230 | * So instead we keep an "irq_enabled" field inside our "struct lguest_data", | |
231 | * which the Guest can update with a single instruction. The Host knows to | |
a6bd8e13 | 232 | * check there before it tries to deliver an interrupt. |
b2b47c21 RR |
233 | */ |
234 | ||
2e04ef76 RR |
235 | /* |
236 | * save_flags() is expected to return the processor state (ie. "flags"). The | |
65ea5b03 | 237 | * flags word contains all kind of stuff, but in practice Linux only cares |
2e04ef76 RR |
238 | * about the interrupt flag. Our "save_flags()" just returns that. |
239 | */ | |
2605fc21 | 240 | asmlinkage __visible unsigned long lguest_save_fl(void) |
07ad157f RR |
241 | { |
242 | return lguest_data.irq_enabled; | |
243 | } | |
07ad157f | 244 | |
b2b47c21 | 245 | /* Interrupts go off... */ |
2605fc21 | 246 | asmlinkage __visible void lguest_irq_disable(void) |
07ad157f RR |
247 | { |
248 | lguest_data.irq_enabled = 0; | |
249 | } | |
250 | ||
2e04ef76 RR |
251 | /* |
252 | * Let's pause a moment. Remember how I said these are called so often? | |
61f4bc83 RR |
253 | * Jeremy Fitzhardinge optimized them so hard early in 2009 that he had to |
254 | * break some rules. In particular, these functions are assumed to save their | |
255 | * own registers if they need to: normal C functions assume they can trash the | |
256 | * eax register. To use normal C functions, we use | |
257 | * PV_CALLEE_SAVE_REGS_THUNK(), which pushes %eax onto the stack, calls the | |
2e04ef76 RR |
258 | * C function, then restores it. |
259 | */ | |
9549b9b3 AK |
260 | PV_CALLEE_SAVE_REGS_THUNK(lguest_save_fl); |
261 | PV_CALLEE_SAVE_REGS_THUNK(lguest_irq_disable); | |
61f4bc83 | 262 | /*:*/ |
a32a8813 | 263 | |
41f055d4 | 264 | /* These are in head_32.S */ |
61f4bc83 RR |
265 | extern void lg_irq_enable(void); |
266 | extern void lg_restore_fl(unsigned long flags); | |
ecb93d1c | 267 | |
2e04ef76 | 268 | /*M:003 |
a91d74a3 RR |
269 | * We could be more efficient in our checking of outstanding interrupts, rather |
270 | * than using a branch. One way would be to put the "irq_enabled" field in a | |
271 | * page by itself, and have the Host write-protect it when an interrupt comes | |
272 | * in when irqs are disabled. There will then be a page fault as soon as | |
273 | * interrupts are re-enabled. | |
a6bd8e13 RR |
274 | * |
275 | * A better method is to implement soft interrupt disable generally for x86: | |
276 | * instead of disabling interrupts, we set a flag. If an interrupt does come | |
277 | * in, we then disable them for real. This is uncommon, so we could simply use | |
2e04ef76 RR |
278 | * a hypercall for interrupt control and not worry about efficiency. |
279 | :*/ | |
07ad157f | 280 | |
b2b47c21 RR |
281 | /*G:034 |
282 | * The Interrupt Descriptor Table (IDT). | |
283 | * | |
284 | * The IDT tells the processor what to do when an interrupt comes in. Each | |
285 | * entry in the table is a 64-bit descriptor: this holds the privilege level, | |
286 | * address of the handler, and... well, who cares? The Guest just asks the | |
287 | * Host to make the change anyway, because the Host controls the real IDT. | |
288 | */ | |
8d947344 GOC |
289 | static void lguest_write_idt_entry(gate_desc *dt, |
290 | int entrynum, const gate_desc *g) | |
07ad157f | 291 | { |
2e04ef76 RR |
292 | /* |
293 | * The gate_desc structure is 8 bytes long: we hand it to the Host in | |
a6bd8e13 RR |
294 | * two 32-bit chunks. The whole 32-bit kernel used to hand descriptors |
295 | * around like this; typesafety wasn't a big concern in Linux's early | |
2e04ef76 RR |
296 | * years. |
297 | */ | |
8d947344 | 298 | u32 *desc = (u32 *)g; |
b2b47c21 | 299 | /* Keep the local copy up to date. */ |
8d947344 | 300 | native_write_idt_entry(dt, entrynum, g); |
b2b47c21 | 301 | /* Tell Host about this new entry. */ |
091ebf07 | 302 | hcall(LHCALL_LOAD_IDT_ENTRY, entrynum, desc[0], desc[1], 0); |
07ad157f RR |
303 | } |
304 | ||
2e04ef76 RR |
305 | /* |
306 | * Changing to a different IDT is very rare: we keep the IDT up-to-date every | |
b2b47c21 | 307 | * time it is written, so we can simply loop through all entries and tell the |
2e04ef76 RR |
308 | * Host about them. |
309 | */ | |
6b68f01b | 310 | static void lguest_load_idt(const struct desc_ptr *desc) |
07ad157f RR |
311 | { |
312 | unsigned int i; | |
313 | struct desc_struct *idt = (void *)desc->address; | |
314 | ||
315 | for (i = 0; i < (desc->size+1)/8; i++) | |
091ebf07 | 316 | hcall(LHCALL_LOAD_IDT_ENTRY, i, idt[i].a, idt[i].b, 0); |
07ad157f RR |
317 | } |
318 | ||
b2b47c21 RR |
319 | /* |
320 | * The Global Descriptor Table. | |
321 | * | |
322 | * The Intel architecture defines another table, called the Global Descriptor | |
323 | * Table (GDT). You tell the CPU where it is (and its size) using the "lgdt" | |
324 | * instruction, and then several other instructions refer to entries in the | |
325 | * table. There are three entries which the Switcher needs, so the Host simply | |
326 | * controls the entire thing and the Guest asks it to make changes using the | |
327 | * LOAD_GDT hypercall. | |
328 | * | |
a489f0b5 | 329 | * This is the exactly like the IDT code. |
b2b47c21 | 330 | */ |
6b68f01b | 331 | static void lguest_load_gdt(const struct desc_ptr *desc) |
07ad157f | 332 | { |
a489f0b5 RR |
333 | unsigned int i; |
334 | struct desc_struct *gdt = (void *)desc->address; | |
335 | ||
336 | for (i = 0; i < (desc->size+1)/8; i++) | |
091ebf07 | 337 | hcall(LHCALL_LOAD_GDT_ENTRY, i, gdt[i].a, gdt[i].b, 0); |
07ad157f RR |
338 | } |
339 | ||
2e04ef76 | 340 | /* |
9b6efcd2 RR |
341 | * For a single GDT entry which changes, we simply change our copy and |
342 | * then tell the host about it. | |
2e04ef76 | 343 | */ |
014b15be GOC |
344 | static void lguest_write_gdt_entry(struct desc_struct *dt, int entrynum, |
345 | const void *desc, int type) | |
07ad157f | 346 | { |
014b15be | 347 | native_write_gdt_entry(dt, entrynum, desc, type); |
a489f0b5 | 348 | /* Tell Host about this new entry. */ |
091ebf07 RR |
349 | hcall(LHCALL_LOAD_GDT_ENTRY, entrynum, |
350 | dt[entrynum].a, dt[entrynum].b, 0); | |
07ad157f RR |
351 | } |
352 | ||
2e04ef76 | 353 | /* |
9b6efcd2 | 354 | * There are three "thread local storage" GDT entries which change |
b2b47c21 | 355 | * on every context switch (these three entries are how glibc implements |
9b6efcd2 RR |
356 | * __thread variables). As an optimization, we have a hypercall |
357 | * specifically for this case. | |
358 | * | |
359 | * Wouldn't it be nicer to have a general LOAD_GDT_ENTRIES hypercall | |
360 | * which took a range of entries? | |
2e04ef76 | 361 | */ |
07ad157f RR |
362 | static void lguest_load_tls(struct thread_struct *t, unsigned int cpu) |
363 | { | |
2e04ef76 RR |
364 | /* |
365 | * There's one problem which normal hardware doesn't have: the Host | |
0d027c01 | 366 | * can't handle us removing entries we're currently using. So we clear |
2e04ef76 RR |
367 | * the GS register here: if it's needed it'll be reloaded anyway. |
368 | */ | |
ccbeed3a | 369 | lazy_load_gs(0); |
4cd8b5e2 | 370 | lazy_hcall2(LHCALL_LOAD_TLS, __pa(&t->tls_array), cpu); |
07ad157f RR |
371 | } |
372 | ||
2e04ef76 RR |
373 | /*G:038 |
374 | * That's enough excitement for now, back to ploughing through each of the | |
375 | * different pv_ops structures (we're about 1/3 of the way through). | |
b2b47c21 RR |
376 | * |
377 | * This is the Local Descriptor Table, another weird Intel thingy. Linux only | |
378 | * uses this for some strange applications like Wine. We don't do anything | |
2e04ef76 RR |
379 | * here, so they'll get an informative and friendly Segmentation Fault. |
380 | */ | |
07ad157f RR |
381 | static void lguest_set_ldt(const void *addr, unsigned entries) |
382 | { | |
383 | } | |
384 | ||
2e04ef76 RR |
385 | /* |
386 | * This loads a GDT entry into the "Task Register": that entry points to a | |
b2b47c21 RR |
387 | * structure called the Task State Segment. Some comments scattered though the |
388 | * kernel code indicate that this used for task switching in ages past, along | |
389 | * with blood sacrifice and astrology. | |
390 | * | |
391 | * Now there's nothing interesting in here that we don't get told elsewhere. | |
392 | * But the native version uses the "ltr" instruction, which makes the Host | |
393 | * complain to the Guest about a Segmentation Fault and it'll oops. So we | |
2e04ef76 RR |
394 | * override the native version with a do-nothing version. |
395 | */ | |
07ad157f RR |
396 | static void lguest_load_tr_desc(void) |
397 | { | |
398 | } | |
399 | ||
2e04ef76 RR |
400 | /* |
401 | * The "cpuid" instruction is a way of querying both the CPU identity | |
b2b47c21 | 402 | * (manufacturer, model, etc) and its features. It was introduced before the |
a6bd8e13 RR |
403 | * Pentium in 1993 and keeps getting extended by both Intel, AMD and others. |
404 | * As you might imagine, after a decade and a half this treatment, it is now a | |
405 | * giant ball of hair. Its entry in the current Intel manual runs to 28 pages. | |
b2b47c21 RR |
406 | * |
407 | * This instruction even it has its own Wikipedia entry. The Wikipedia entry | |
8d431f41 | 408 | * has been translated into 6 languages. I am not making this up! |
b2b47c21 RR |
409 | * |
410 | * We could get funky here and identify ourselves as "GenuineLguest", but | |
411 | * instead we just use the real "cpuid" instruction. Then I pretty much turned | |
412 | * off feature bits until the Guest booted. (Don't say that: you'll damage | |
413 | * lguest sales!) Shut up, inner voice! (Hey, just pointing out that this is | |
0d2eb44f | 414 | * hardly future proof.) No one's listening! They don't like you anyway, |
b2b47c21 RR |
415 | * parenthetic weirdo! |
416 | * | |
417 | * Replacing the cpuid so we can turn features off is great for the kernel, but | |
418 | * anyone (including userspace) can just use the raw "cpuid" instruction and | |
419 | * the Host won't even notice since it isn't privileged. So we try not to get | |
2e04ef76 RR |
420 | * too worked up about it. |
421 | */ | |
65ea5b03 PA |
422 | static void lguest_cpuid(unsigned int *ax, unsigned int *bx, |
423 | unsigned int *cx, unsigned int *dx) | |
07ad157f | 424 | { |
65ea5b03 | 425 | int function = *ax; |
07ad157f | 426 | |
65ea5b03 | 427 | native_cpuid(ax, bx, cx, dx); |
07ad157f | 428 | switch (function) { |
2e04ef76 RR |
429 | /* |
430 | * CPUID 0 gives the highest legal CPUID number (and the ID string). | |
431 | * We futureproof our code a little by sticking to known CPUID values. | |
432 | */ | |
433 | case 0: | |
7a504920 RR |
434 | if (*ax > 5) |
435 | *ax = 5; | |
436 | break; | |
2e04ef76 RR |
437 | |
438 | /* | |
439 | * CPUID 1 is a basic feature request. | |
440 | * | |
441 | * CX: we only allow kernel to see SSE3, CMPXCHG16B and SSSE3 | |
442 | * DX: SSE, SSE2, FXSR, MMX, CMOV, CMPXCHG8B, TSC, FPU and PAE. | |
443 | */ | |
444 | case 1: | |
65ea5b03 | 445 | *cx &= 0x00002201; |
acdd0b62 | 446 | *dx &= 0x07808151; |
2e04ef76 RR |
447 | /* |
448 | * The Host can do a nice optimization if it knows that the | |
b2b47c21 RR |
449 | * kernel mappings (addresses above 0xC0000000 or whatever |
450 | * PAGE_OFFSET is set to) haven't changed. But Linux calls | |
451 | * flush_tlb_user() for both user and kernel mappings unless | |
2e04ef76 RR |
452 | * the Page Global Enable (PGE) feature bit is set. |
453 | */ | |
65ea5b03 | 454 | *dx |= 0x00002000; |
2e04ef76 RR |
455 | /* |
456 | * We also lie, and say we're family id 5. 6 or greater | |
cbd88c8e | 457 | * leads to a rdmsr in early_init_intel which we can't handle. |
2e04ef76 RR |
458 | * Family ID is returned as bits 8-12 in ax. |
459 | */ | |
cbd88c8e RR |
460 | *ax &= 0xFFFFF0FF; |
461 | *ax |= 0x00000500; | |
07ad157f | 462 | break; |
89cfc991 RR |
463 | |
464 | /* | |
465 | * This is used to detect if we're running under KVM. We might be, | |
466 | * but that's a Host matter, not us. So say we're not. | |
467 | */ | |
468 | case KVM_CPUID_SIGNATURE: | |
469 | *bx = *cx = *dx = 0; | |
470 | break; | |
471 | ||
2e04ef76 RR |
472 | /* |
473 | * 0x80000000 returns the highest Extended Function, so we futureproof | |
474 | * like we do above by limiting it to known fields. | |
475 | */ | |
07ad157f | 476 | case 0x80000000: |
65ea5b03 PA |
477 | if (*ax > 0x80000008) |
478 | *ax = 0x80000008; | |
07ad157f | 479 | break; |
2e04ef76 RR |
480 | |
481 | /* | |
482 | * PAE systems can mark pages as non-executable. Linux calls this the | |
483 | * NX bit. Intel calls it XD (eXecute Disable), AMD EVP (Enhanced | |
64be1158 | 484 | * Virus Protection). We just switch it off here, since we don't |
2e04ef76 RR |
485 | * support it. |
486 | */ | |
acdd0b62 | 487 | case 0x80000001: |
acdd0b62 MZ |
488 | *dx &= ~(1 << 20); |
489 | break; | |
07ad157f RR |
490 | } |
491 | } | |
492 | ||
2e04ef76 RR |
493 | /* |
494 | * Intel has four control registers, imaginatively named cr0, cr2, cr3 and cr4. | |
b2b47c21 RR |
495 | * I assume there's a cr1, but it hasn't bothered us yet, so we'll not bother |
496 | * it. The Host needs to know when the Guest wants to change them, so we have | |
497 | * a whole series of functions like read_cr0() and write_cr0(). | |
498 | * | |
e1e72965 | 499 | * We start with cr0. cr0 allows you to turn on and off all kinds of basic |
cd95ea81 AL |
500 | * features, but the only cr0 bit that Linux ever used at runtime was the |
501 | * horrifically-named Task Switched (TS) bit at bit 3 (ie. 8) | |
b2b47c21 RR |
502 | * |
503 | * What does the TS bit do? Well, it causes the CPU to trap (interrupt 7) if | |
504 | * the floating point unit is used. Which allows us to restore FPU state | |
cd95ea81 AL |
505 | * lazily after a task switch if we wanted to, but wouldn't a name like |
506 | * "FPUTRAP bit" be a little less cryptic? | |
b2b47c21 | 507 | * |
cd95ea81 AL |
508 | * Fortunately, Linux keeps it simple and doesn't use TS, so we can ignore |
509 | * cr0. | |
2e04ef76 | 510 | */ |
07ad157f RR |
511 | static void lguest_write_cr0(unsigned long val) |
512 | { | |
07ad157f RR |
513 | } |
514 | ||
515 | static unsigned long lguest_read_cr0(void) | |
516 | { | |
cd95ea81 | 517 | return 0; |
07ad157f RR |
518 | } |
519 | ||
2e04ef76 RR |
520 | /* |
521 | * cr2 is the virtual address of the last page fault, which the Guest only ever | |
b2b47c21 | 522 | * reads. The Host kindly writes this into our "struct lguest_data", so we |
2e04ef76 RR |
523 | * just read it out of there. |
524 | */ | |
07ad157f RR |
525 | static unsigned long lguest_read_cr2(void) |
526 | { | |
527 | return lguest_data.cr2; | |
528 | } | |
529 | ||
ad5173ff RR |
530 | /* See lguest_set_pte() below. */ |
531 | static bool cr3_changed = false; | |
5dea1c88 | 532 | static unsigned long current_cr3; |
ad5173ff | 533 | |
2e04ef76 RR |
534 | /* |
535 | * cr3 is the current toplevel pagetable page: the principle is the same as | |
5dea1c88 | 536 | * cr0. Keep a local copy, and tell the Host when it changes. |
2e04ef76 | 537 | */ |
07ad157f RR |
538 | static void lguest_write_cr3(unsigned long cr3) |
539 | { | |
4cd8b5e2 | 540 | lazy_hcall1(LHCALL_NEW_PGTABLE, cr3); |
5dea1c88 | 541 | current_cr3 = cr3; |
bb4093de RR |
542 | |
543 | /* These two page tables are simple, linear, and used during boot */ | |
6a3956bd AD |
544 | if (cr3 != __pa_symbol(swapper_pg_dir) && |
545 | cr3 != __pa_symbol(initial_page_table)) | |
bb4093de | 546 | cr3_changed = true; |
07ad157f RR |
547 | } |
548 | ||
549 | static unsigned long lguest_read_cr3(void) | |
550 | { | |
5dea1c88 | 551 | return current_cr3; |
07ad157f RR |
552 | } |
553 | ||
e1e72965 | 554 | /* cr4 is used to enable and disable PGE, but we don't care. */ |
07ad157f RR |
555 | static unsigned long lguest_read_cr4(void) |
556 | { | |
557 | return 0; | |
558 | } | |
559 | ||
560 | static void lguest_write_cr4(unsigned long val) | |
561 | { | |
562 | } | |
563 | ||
b2b47c21 RR |
564 | /* |
565 | * Page Table Handling. | |
566 | * | |
567 | * Now would be a good time to take a rest and grab a coffee or similarly | |
568 | * relaxing stimulant. The easy parts are behind us, and the trek gradually | |
569 | * winds uphill from here. | |
570 | * | |
571 | * Quick refresher: memory is divided into "pages" of 4096 bytes each. The CPU | |
572 | * maps virtual addresses to physical addresses using "page tables". We could | |
573 | * use one huge index of 1 million entries: each address is 4 bytes, so that's | |
574 | * 1024 pages just to hold the page tables. But since most virtual addresses | |
e1e72965 | 575 | * are unused, we use a two level index which saves space. The cr3 register |
b2b47c21 RR |
576 | * contains the physical address of the top level "page directory" page, which |
577 | * contains physical addresses of up to 1024 second-level pages. Each of these | |
578 | * second level pages contains up to 1024 physical addresses of actual pages, | |
579 | * or Page Table Entries (PTEs). | |
580 | * | |
581 | * Here's a diagram, where arrows indicate physical addresses: | |
582 | * | |
e1e72965 | 583 | * cr3 ---> +---------+ |
b2b47c21 RR |
584 | * | --------->+---------+ |
585 | * | | | PADDR1 | | |
a91d74a3 | 586 | * Mid-level | | PADDR2 | |
b2b47c21 RR |
587 | * (PMD) page | | | |
588 | * | | Lower-level | | |
589 | * | | (PTE) page | | |
590 | * | | | | | |
591 | * .... .... | |
592 | * | |
593 | * So to convert a virtual address to a physical address, we look up the top | |
594 | * level, which points us to the second level, which gives us the physical | |
595 | * address of that page. If the top level entry was not present, or the second | |
596 | * level entry was not present, then the virtual address is invalid (we | |
597 | * say "the page was not mapped"). | |
598 | * | |
599 | * Put another way, a 32-bit virtual address is divided up like so: | |
600 | * | |
601 | * 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
602 | * |<---- 10 bits ---->|<---- 10 bits ---->|<------ 12 bits ------>| | |
603 | * Index into top Index into second Offset within page | |
604 | * page directory page pagetable page | |
605 | * | |
a91d74a3 RR |
606 | * Now, unfortunately, this isn't the whole story: Intel added Physical Address |
607 | * Extension (PAE) to allow 32 bit systems to use 64GB of memory (ie. 36 bits). | |
608 | * These are held in 64-bit page table entries, so we can now only fit 512 | |
609 | * entries in a page, and the neat three-level tree breaks down. | |
610 | * | |
611 | * The result is a four level page table: | |
612 | * | |
613 | * cr3 --> [ 4 Upper ] | |
614 | * [ Level ] | |
615 | * [ Entries ] | |
616 | * [(PUD Page)]---> +---------+ | |
617 | * | --------->+---------+ | |
618 | * | | | PADDR1 | | |
619 | * Mid-level | | PADDR2 | | |
620 | * (PMD) page | | | | |
621 | * | | Lower-level | | |
622 | * | | (PTE) page | | |
623 | * | | | | | |
624 | * .... .... | |
625 | * | |
626 | * | |
627 | * And the virtual address is decoded as: | |
628 | * | |
629 | * 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
630 | * |<-2->|<--- 9 bits ---->|<---- 9 bits --->|<------ 12 bits ------>| | |
631 | * Index into Index into mid Index into lower Offset within page | |
632 | * top entries directory page pagetable page | |
633 | * | |
634 | * It's too hard to switch between these two formats at runtime, so Linux only | |
635 | * supports one or the other depending on whether CONFIG_X86_PAE is set. Many | |
636 | * distributions turn it on, and not just for people with silly amounts of | |
637 | * memory: the larger PTE entries allow room for the NX bit, which lets the | |
638 | * kernel disable execution of pages and increase security. | |
639 | * | |
640 | * This was a problem for lguest, which couldn't run on these distributions; | |
641 | * then Matias Zabaljauregui figured it all out and implemented it, and only a | |
642 | * handful of puppies were crushed in the process! | |
643 | * | |
644 | * Back to our point: the kernel spends a lot of time changing both the | |
645 | * top-level page directory and lower-level pagetable pages. The Guest doesn't | |
646 | * know physical addresses, so while it maintains these page tables exactly | |
647 | * like normal, it also needs to keep the Host informed whenever it makes a | |
648 | * change: the Host will create the real page tables based on the Guests'. | |
b2b47c21 RR |
649 | */ |
650 | ||
2e04ef76 | 651 | /* |
a91d74a3 | 652 | * The Guest calls this after it has set a second-level entry (pte), ie. to map |
9f54288d | 653 | * a page into a process' address space. We tell the Host the toplevel and |
a91d74a3 RR |
654 | * address this corresponds to. The Guest uses one pagetable per process, so |
655 | * we need to tell the Host which one we're changing (mm->pgd). | |
2e04ef76 | 656 | */ |
b7ff99ea RR |
657 | static void lguest_pte_update(struct mm_struct *mm, unsigned long addr, |
658 | pte_t *ptep) | |
659 | { | |
acdd0b62 | 660 | #ifdef CONFIG_X86_PAE |
a91d74a3 | 661 | /* PAE needs to hand a 64 bit page table entry, so it uses two args. */ |
acdd0b62 MZ |
662 | lazy_hcall4(LHCALL_SET_PTE, __pa(mm->pgd), addr, |
663 | ptep->pte_low, ptep->pte_high); | |
664 | #else | |
4cd8b5e2 | 665 | lazy_hcall3(LHCALL_SET_PTE, __pa(mm->pgd), addr, ptep->pte_low); |
acdd0b62 | 666 | #endif |
b7ff99ea RR |
667 | } |
668 | ||
a91d74a3 | 669 | /* This is the "set and update" combo-meal-deal version. */ |
07ad157f RR |
670 | static void lguest_set_pte_at(struct mm_struct *mm, unsigned long addr, |
671 | pte_t *ptep, pte_t pteval) | |
672 | { | |
90603d15 | 673 | native_set_pte(ptep, pteval); |
b7ff99ea | 674 | lguest_pte_update(mm, addr, ptep); |
07ad157f RR |
675 | } |
676 | ||
2e04ef76 RR |
677 | /* |
678 | * The Guest calls lguest_set_pud to set a top-level entry and lguest_set_pmd | |
acdd0b62 | 679 | * to set a middle-level entry when PAE is activated. |
2e04ef76 | 680 | * |
acdd0b62 | 681 | * Again, we set the entry then tell the Host which page we changed, |
2e04ef76 RR |
682 | * and the index of the entry we changed. |
683 | */ | |
acdd0b62 MZ |
684 | #ifdef CONFIG_X86_PAE |
685 | static void lguest_set_pud(pud_t *pudp, pud_t pudval) | |
686 | { | |
687 | native_set_pud(pudp, pudval); | |
688 | ||
689 | /* 32 bytes aligned pdpt address and the index. */ | |
690 | lazy_hcall2(LHCALL_SET_PGD, __pa(pudp) & 0xFFFFFFE0, | |
691 | (__pa(pudp) & 0x1F) / sizeof(pud_t)); | |
692 | } | |
693 | ||
694 | static void lguest_set_pmd(pmd_t *pmdp, pmd_t pmdval) | |
695 | { | |
696 | native_set_pmd(pmdp, pmdval); | |
697 | lazy_hcall2(LHCALL_SET_PMD, __pa(pmdp) & PAGE_MASK, | |
698 | (__pa(pmdp) & (PAGE_SIZE - 1)) / sizeof(pmd_t)); | |
699 | } | |
700 | #else | |
701 | ||
2e04ef76 | 702 | /* The Guest calls lguest_set_pmd to set a top-level entry when !PAE. */ |
07ad157f RR |
703 | static void lguest_set_pmd(pmd_t *pmdp, pmd_t pmdval) |
704 | { | |
90603d15 | 705 | native_set_pmd(pmdp, pmdval); |
ebe0ba84 | 706 | lazy_hcall2(LHCALL_SET_PGD, __pa(pmdp) & PAGE_MASK, |
90603d15 | 707 | (__pa(pmdp) & (PAGE_SIZE - 1)) / sizeof(pmd_t)); |
07ad157f | 708 | } |
acdd0b62 | 709 | #endif |
07ad157f | 710 | |
2e04ef76 RR |
711 | /* |
712 | * There are a couple of legacy places where the kernel sets a PTE, but we | |
b2b47c21 RR |
713 | * don't know the top level any more. This is useless for us, since we don't |
714 | * know which pagetable is changing or what address, so we just tell the Host | |
715 | * to forget all of them. Fortunately, this is very rare. | |
716 | * | |
717 | * ... except in early boot when the kernel sets up the initial pagetables, | |
bb4093de RR |
718 | * which makes booting astonishingly slow: 48 seconds! So we don't even tell |
719 | * the Host anything changed until we've done the first real page table switch, | |
720 | * which brings boot back to 4.3 seconds. | |
2e04ef76 | 721 | */ |
07ad157f RR |
722 | static void lguest_set_pte(pte_t *ptep, pte_t pteval) |
723 | { | |
90603d15 | 724 | native_set_pte(ptep, pteval); |
ad5173ff | 725 | if (cr3_changed) |
4cd8b5e2 | 726 | lazy_hcall1(LHCALL_FLUSH_TLB, 1); |
07ad157f RR |
727 | } |
728 | ||
acdd0b62 | 729 | #ifdef CONFIG_X86_PAE |
a91d74a3 RR |
730 | /* |
731 | * With 64-bit PTE values, we need to be careful setting them: if we set 32 | |
732 | * bits at a time, the hardware could see a weird half-set entry. These | |
733 | * versions ensure we update all 64 bits at once. | |
734 | */ | |
acdd0b62 MZ |
735 | static void lguest_set_pte_atomic(pte_t *ptep, pte_t pte) |
736 | { | |
737 | native_set_pte_atomic(ptep, pte); | |
738 | if (cr3_changed) | |
739 | lazy_hcall1(LHCALL_FLUSH_TLB, 1); | |
740 | } | |
741 | ||
a91d74a3 RR |
742 | static void lguest_pte_clear(struct mm_struct *mm, unsigned long addr, |
743 | pte_t *ptep) | |
acdd0b62 MZ |
744 | { |
745 | native_pte_clear(mm, addr, ptep); | |
746 | lguest_pte_update(mm, addr, ptep); | |
747 | } | |
748 | ||
a91d74a3 | 749 | static void lguest_pmd_clear(pmd_t *pmdp) |
acdd0b62 MZ |
750 | { |
751 | lguest_set_pmd(pmdp, __pmd(0)); | |
752 | } | |
753 | #endif | |
754 | ||
2e04ef76 RR |
755 | /* |
756 | * Unfortunately for Lguest, the pv_mmu_ops for page tables were based on | |
b2b47c21 RR |
757 | * native page table operations. On native hardware you can set a new page |
758 | * table entry whenever you want, but if you want to remove one you have to do | |
759 | * a TLB flush (a TLB is a little cache of page table entries kept by the CPU). | |
760 | * | |
761 | * So the lguest_set_pte_at() and lguest_set_pmd() functions above are only | |
762 | * called when a valid entry is written, not when it's removed (ie. marked not | |
763 | * present). Instead, this is where we come when the Guest wants to remove a | |
764 | * page table entry: we tell the Host to set that entry to 0 (ie. the present | |
2e04ef76 RR |
765 | * bit is zero). |
766 | */ | |
07ad157f RR |
767 | static void lguest_flush_tlb_single(unsigned long addr) |
768 | { | |
b2b47c21 | 769 | /* Simply set it to zero: if it was not, it will fault back in. */ |
5dea1c88 | 770 | lazy_hcall3(LHCALL_SET_PTE, current_cr3, addr, 0); |
07ad157f RR |
771 | } |
772 | ||
2e04ef76 RR |
773 | /* |
774 | * This is what happens after the Guest has removed a large number of entries. | |
b2b47c21 | 775 | * This tells the Host that any of the page table entries for userspace might |
2e04ef76 RR |
776 | * have changed, ie. virtual addresses below PAGE_OFFSET. |
777 | */ | |
07ad157f RR |
778 | static void lguest_flush_tlb_user(void) |
779 | { | |
4cd8b5e2 | 780 | lazy_hcall1(LHCALL_FLUSH_TLB, 0); |
07ad157f RR |
781 | } |
782 | ||
2e04ef76 RR |
783 | /* |
784 | * This is called when the kernel page tables have changed. That's not very | |
b2b47c21 | 785 | * common (unless the Guest is using highmem, which makes the Guest extremely |
2e04ef76 RR |
786 | * slow), so it's worth separating this from the user flushing above. |
787 | */ | |
07ad157f RR |
788 | static void lguest_flush_tlb_kernel(void) |
789 | { | |
4cd8b5e2 | 790 | lazy_hcall1(LHCALL_FLUSH_TLB, 1); |
07ad157f RR |
791 | } |
792 | ||
b2b47c21 RR |
793 | /* |
794 | * The Unadvanced Programmable Interrupt Controller. | |
795 | * | |
796 | * This is an attempt to implement the simplest possible interrupt controller. | |
797 | * I spent some time looking though routines like set_irq_chip_and_handler, | |
798 | * set_irq_chip_and_handler_name, set_irq_chip_data and set_phasers_to_stun and | |
799 | * I *think* this is as simple as it gets. | |
800 | * | |
801 | * We can tell the Host what interrupts we want blocked ready for using the | |
802 | * lguest_data.interrupts bitmap, so disabling (aka "masking") them is as | |
803 | * simple as setting a bit. We don't actually "ack" interrupts as such, we | |
804 | * just mask and unmask them. I wonder if we should be cleverer? | |
805 | */ | |
fe25c7fc | 806 | static void disable_lguest_irq(struct irq_data *data) |
07ad157f | 807 | { |
fe25c7fc | 808 | set_bit(data->irq, lguest_data.blocked_interrupts); |
07ad157f RR |
809 | } |
810 | ||
fe25c7fc | 811 | static void enable_lguest_irq(struct irq_data *data) |
07ad157f | 812 | { |
fe25c7fc | 813 | clear_bit(data->irq, lguest_data.blocked_interrupts); |
07ad157f RR |
814 | } |
815 | ||
b2b47c21 | 816 | /* This structure describes the lguest IRQ controller. */ |
07ad157f RR |
817 | static struct irq_chip lguest_irq_controller = { |
818 | .name = "lguest", | |
fe25c7fc TG |
819 | .irq_mask = disable_lguest_irq, |
820 | .irq_mask_ack = disable_lguest_irq, | |
821 | .irq_unmask = enable_lguest_irq, | |
07ad157f RR |
822 | }; |
823 | ||
27a6f41c RR |
824 | /* |
825 | * Interrupt descriptors are allocated as-needed, but low-numbered ones are | |
826 | * reserved by the generic x86 code. So we ignore irq_alloc_desc_at if it | |
827 | * tells us the irq is already used: other errors (ie. ENOMEM) we take | |
828 | * seriously. | |
829 | */ | |
830 | static int lguest_setup_irq(unsigned int irq) | |
831 | { | |
a782a7e4 | 832 | struct irq_desc *desc; |
27a6f41c RR |
833 | int err; |
834 | ||
835 | /* Returns -ve error or vector number. */ | |
836 | err = irq_alloc_desc_at(irq, 0); | |
837 | if (err < 0 && err != -EEXIST) | |
838 | return err; | |
839 | ||
ad3f8d5a TG |
840 | /* |
841 | * Tell the Linux infrastructure that the interrupt is | |
842 | * controlled by our level-based lguest interrupt controller. | |
843 | */ | |
27a6f41c RR |
844 | irq_set_chip_and_handler_name(irq, &lguest_irq_controller, |
845 | handle_level_irq, "level"); | |
ad3f8d5a TG |
846 | |
847 | /* Some systems map "vectors" to interrupts weirdly. Not us! */ | |
a782a7e4 TG |
848 | desc = irq_to_desc(irq); |
849 | __this_cpu_write(vector_irq[FIRST_EXTERNAL_VECTOR + irq], desc); | |
27a6f41c RR |
850 | return 0; |
851 | } | |
852 | ||
e1b83e27 RR |
853 | static int lguest_enable_irq(struct pci_dev *dev) |
854 | { | |
ad3f8d5a | 855 | int err; |
e1b83e27 RR |
856 | u8 line = 0; |
857 | ||
858 | /* We literally use the PCI interrupt line as the irq number. */ | |
859 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &line); | |
ad3f8d5a TG |
860 | err = lguest_setup_irq(line); |
861 | if (!err) | |
862 | dev->irq = line; | |
863 | return err; | |
e1b83e27 RR |
864 | } |
865 | ||
866 | /* We don't do hotplug PCI, so this shouldn't be called. */ | |
867 | static void lguest_disable_irq(struct pci_dev *dev) | |
868 | { | |
869 | WARN_ON(1); | |
870 | } | |
871 | ||
2e04ef76 RR |
872 | /* |
873 | * This sets up the Interrupt Descriptor Table (IDT) entry for each hardware | |
ad3f8d5a | 874 | * interrupt (except 128, which is used for system calls). |
2e04ef76 | 875 | */ |
07ad157f RR |
876 | static void __init lguest_init_IRQ(void) |
877 | { | |
878 | unsigned int i; | |
879 | ||
2414e021 | 880 | for (i = FIRST_EXTERNAL_VECTOR; i < FIRST_SYSTEM_VECTOR; i++) { |
51bb9284 | 881 | if (i != IA32_SYSCALL_VECTOR) |
3304c9c3 DV |
882 | set_intr_gate(i, irq_entries_start + |
883 | 8 * (i - FIRST_EXTERNAL_VECTOR)); | |
07ad157f | 884 | } |
2e04ef76 RR |
885 | |
886 | /* | |
887 | * This call is required to set up for 4k stacks, where we have | |
888 | * separate stacks for hard and soft interrupts. | |
889 | */ | |
07ad157f RR |
890 | irq_ctx_init(smp_processor_id()); |
891 | } | |
892 | ||
b2b47c21 RR |
893 | /* |
894 | * Time. | |
895 | * | |
896 | * It would be far better for everyone if the Guest had its own clock, but | |
6c8dca5d | 897 | * until then the Host gives us the time on every interrupt. |
b2b47c21 | 898 | */ |
3565184e | 899 | static void lguest_get_wallclock(struct timespec *now) |
07ad157f | 900 | { |
3565184e | 901 | *now = lguest_data.time; |
07ad157f RR |
902 | } |
903 | ||
2e04ef76 RR |
904 | /* |
905 | * The TSC is an Intel thing called the Time Stamp Counter. The Host tells us | |
a6bd8e13 RR |
906 | * what speed it runs at, or 0 if it's unusable as a reliable clock source. |
907 | * This matches what we want here: if we return 0 from this function, the x86 | |
2e04ef76 RR |
908 | * TSC clock will give up and not register itself. |
909 | */ | |
e93ef949 | 910 | static unsigned long lguest_tsc_khz(void) |
3fabc55f RR |
911 | { |
912 | return lguest_data.tsc_khz; | |
913 | } | |
914 | ||
2e04ef76 RR |
915 | /* |
916 | * If we can't use the TSC, the kernel falls back to our lower-priority | |
917 | * "lguest_clock", where we read the time value given to us by the Host. | |
918 | */ | |
a5a1d1c2 | 919 | static u64 lguest_clock_read(struct clocksource *cs) |
d7e28ffe | 920 | { |
6c8dca5d RR |
921 | unsigned long sec, nsec; |
922 | ||
2e04ef76 RR |
923 | /* |
924 | * Since the time is in two parts (seconds and nanoseconds), we risk | |
3fabc55f RR |
925 | * reading it just as it's changing from 99 & 0.999999999 to 100 and 0, |
926 | * and getting 99 and 0. As Linux tends to come apart under the stress | |
2e04ef76 RR |
927 | * of time travel, we must be careful: |
928 | */ | |
6c8dca5d RR |
929 | do { |
930 | /* First we read the seconds part. */ | |
931 | sec = lguest_data.time.tv_sec; | |
2e04ef76 RR |
932 | /* |
933 | * This read memory barrier tells the compiler and the CPU that | |
6c8dca5d | 934 | * this can't be reordered: we have to complete the above |
2e04ef76 RR |
935 | * before going on. |
936 | */ | |
6c8dca5d RR |
937 | rmb(); |
938 | /* Now we read the nanoseconds part. */ | |
939 | nsec = lguest_data.time.tv_nsec; | |
940 | /* Make sure we've done that. */ | |
941 | rmb(); | |
942 | /* Now if the seconds part has changed, try again. */ | |
943 | } while (unlikely(lguest_data.time.tv_sec != sec)); | |
944 | ||
3fabc55f | 945 | /* Our lguest clock is in real nanoseconds. */ |
6c8dca5d | 946 | return sec*1000000000ULL + nsec; |
d7e28ffe RR |
947 | } |
948 | ||
3fabc55f | 949 | /* This is the fallback clocksource: lower priority than the TSC clocksource. */ |
d7e28ffe RR |
950 | static struct clocksource lguest_clock = { |
951 | .name = "lguest", | |
3fabc55f | 952 | .rating = 200, |
d7e28ffe | 953 | .read = lguest_clock_read, |
6c8dca5d | 954 | .mask = CLOCKSOURCE_MASK(64), |
05aa026a | 955 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
d7e28ffe RR |
956 | }; |
957 | ||
2e04ef76 RR |
958 | /* |
959 | * We also need a "struct clock_event_device": Linux asks us to set it to go | |
d7e28ffe | 960 | * off some time in the future. Actually, James Morris figured all this out, I |
2e04ef76 RR |
961 | * just applied the patch. |
962 | */ | |
d7e28ffe RR |
963 | static int lguest_clockevent_set_next_event(unsigned long delta, |
964 | struct clock_event_device *evt) | |
965 | { | |
a6bd8e13 RR |
966 | /* FIXME: I don't think this can ever happen, but James tells me he had |
967 | * to put this code in. Maybe we should remove it now. Anyone? */ | |
d7e28ffe RR |
968 | if (delta < LG_CLOCK_MIN_DELTA) { |
969 | if (printk_ratelimit()) | |
970 | printk(KERN_DEBUG "%s: small delta %lu ns\n", | |
77bf90ed | 971 | __func__, delta); |
d7e28ffe RR |
972 | return -ETIME; |
973 | } | |
a6bd8e13 RR |
974 | |
975 | /* Please wake us this far in the future. */ | |
091ebf07 | 976 | hcall(LHCALL_SET_CLOCKEVENT, delta, 0, 0, 0); |
d7e28ffe RR |
977 | return 0; |
978 | } | |
979 | ||
c2e13cc2 | 980 | static int lguest_clockevent_shutdown(struct clock_event_device *evt) |
d7e28ffe | 981 | { |
c2e13cc2 VK |
982 | /* A 0 argument shuts the clock down. */ |
983 | hcall(LHCALL_SET_CLOCKEVENT, 0, 0, 0, 0); | |
984 | return 0; | |
d7e28ffe RR |
985 | } |
986 | ||
987 | /* This describes our primitive timer chip. */ | |
988 | static struct clock_event_device lguest_clockevent = { | |
989 | .name = "lguest", | |
990 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
991 | .set_next_event = lguest_clockevent_set_next_event, | |
c2e13cc2 | 992 | .set_state_shutdown = lguest_clockevent_shutdown, |
d7e28ffe RR |
993 | .rating = INT_MAX, |
994 | .mult = 1, | |
995 | .shift = 0, | |
996 | .min_delta_ns = LG_CLOCK_MIN_DELTA, | |
997 | .max_delta_ns = LG_CLOCK_MAX_DELTA, | |
998 | }; | |
999 | ||
2e04ef76 RR |
1000 | /* |
1001 | * This is the Guest timer interrupt handler (hardware interrupt 0). We just | |
1002 | * call the clockevent infrastructure and it does whatever needs doing. | |
1003 | */ | |
bd0b9ac4 | 1004 | static void lguest_time_irq(struct irq_desc *desc) |
07ad157f | 1005 | { |
d7e28ffe RR |
1006 | unsigned long flags; |
1007 | ||
1008 | /* Don't interrupt us while this is running. */ | |
1009 | local_irq_save(flags); | |
1010 | lguest_clockevent.event_handler(&lguest_clockevent); | |
1011 | local_irq_restore(flags); | |
07ad157f RR |
1012 | } |
1013 | ||
2e04ef76 RR |
1014 | /* |
1015 | * At some point in the boot process, we get asked to set up our timing | |
b2b47c21 RR |
1016 | * infrastructure. The kernel doesn't expect timer interrupts before this, but |
1017 | * we cleverly initialized the "blocked_interrupts" field of "struct | |
2e04ef76 RR |
1018 | * lguest_data" so that timer interrupts were blocked until now. |
1019 | */ | |
07ad157f RR |
1020 | static void lguest_time_init(void) |
1021 | { | |
b2b47c21 | 1022 | /* Set up the timer interrupt (0) to go to our simple timer routine */ |
27a6f41c RR |
1023 | if (lguest_setup_irq(0) != 0) |
1024 | panic("Could not set up timer irq"); | |
2c778651 | 1025 | irq_set_handler(0, lguest_time_irq); |
07ad157f | 1026 | |
b01cc1b0 | 1027 | clocksource_register_hz(&lguest_clock, NSEC_PER_SEC); |
d7e28ffe | 1028 | |
b2b47c21 RR |
1029 | /* We can't set cpumask in the initializer: damn C limitations! Set it |
1030 | * here and register our timer device. */ | |
320ab2b0 | 1031 | lguest_clockevent.cpumask = cpumask_of(0); |
d7e28ffe RR |
1032 | clockevents_register_device(&lguest_clockevent); |
1033 | ||
b2b47c21 | 1034 | /* Finally, we unblock the timer interrupt. */ |
bb6f1d9a | 1035 | clear_bit(0, lguest_data.blocked_interrupts); |
07ad157f RR |
1036 | } |
1037 | ||
b2b47c21 RR |
1038 | /* |
1039 | * Miscellaneous bits and pieces. | |
1040 | * | |
1041 | * Here is an oddball collection of functions which the Guest needs for things | |
1042 | * to work. They're pretty simple. | |
1043 | */ | |
1044 | ||
2e04ef76 RR |
1045 | /* |
1046 | * The Guest needs to tell the Host what stack it expects traps to use. For | |
b2b47c21 RR |
1047 | * native hardware, this is part of the Task State Segment mentioned above in |
1048 | * lguest_load_tr_desc(), but to help hypervisors there's this special call. | |
1049 | * | |
1050 | * We tell the Host the segment we want to use (__KERNEL_DS is the kernel data | |
1051 | * segment), the privilege level (we're privilege level 1, the Host is 0 and | |
1052 | * will not tolerate us trying to use that), the stack pointer, and the number | |
2e04ef76 RR |
1053 | * of pages in the stack. |
1054 | */ | |
faca6227 | 1055 | static void lguest_load_sp0(struct tss_struct *tss, |
a6bd8e13 | 1056 | struct thread_struct *thread) |
07ad157f | 1057 | { |
4cd8b5e2 MZ |
1058 | lazy_hcall3(LHCALL_SET_STACK, __KERNEL_DS | 0x1, thread->sp0, |
1059 | THREAD_SIZE / PAGE_SIZE); | |
8ef46a67 | 1060 | tss->x86_tss.sp0 = thread->sp0; |
07ad157f RR |
1061 | } |
1062 | ||
b2b47c21 | 1063 | /* Let's just say, I wouldn't do debugging under a Guest. */ |
aa96a3c6 RR |
1064 | static unsigned long lguest_get_debugreg(int regno) |
1065 | { | |
1066 | /* FIXME: Implement */ | |
1067 | return 0; | |
1068 | } | |
1069 | ||
07ad157f RR |
1070 | static void lguest_set_debugreg(int regno, unsigned long value) |
1071 | { | |
1072 | /* FIXME: Implement */ | |
1073 | } | |
1074 | ||
2e04ef76 RR |
1075 | /* |
1076 | * There are times when the kernel wants to make sure that no memory writes are | |
b2b47c21 RR |
1077 | * caught in the cache (that they've all reached real hardware devices). This |
1078 | * doesn't matter for the Guest which has virtual hardware. | |
1079 | * | |
1080 | * On the Pentium 4 and above, cpuid() indicates that the Cache Line Flush | |
1081 | * (clflush) instruction is available and the kernel uses that. Otherwise, it | |
1082 | * uses the older "Write Back and Invalidate Cache" (wbinvd) instruction. | |
1083 | * Unlike clflush, wbinvd can only be run at privilege level 0. So we can | |
1084 | * ignore clflush, but replace wbinvd. | |
1085 | */ | |
07ad157f RR |
1086 | static void lguest_wbinvd(void) |
1087 | { | |
1088 | } | |
1089 | ||
2e04ef76 RR |
1090 | /* |
1091 | * If the Guest expects to have an Advanced Programmable Interrupt Controller, | |
b2b47c21 RR |
1092 | * we play dumb by ignoring writes and returning 0 for reads. So it's no |
1093 | * longer Programmable nor Controlling anything, and I don't think 8 lines of | |
1094 | * code qualifies for Advanced. It will also never interrupt anything. It | |
2e04ef76 RR |
1095 | * does, however, allow us to get through the Linux boot code. |
1096 | */ | |
07ad157f | 1097 | #ifdef CONFIG_X86_LOCAL_APIC |
ad66dd34 | 1098 | static void lguest_apic_write(u32 reg, u32 v) |
07ad157f RR |
1099 | { |
1100 | } | |
1101 | ||
ad66dd34 | 1102 | static u32 lguest_apic_read(u32 reg) |
07ad157f RR |
1103 | { |
1104 | return 0; | |
1105 | } | |
511d9d34 SS |
1106 | |
1107 | static u64 lguest_apic_icr_read(void) | |
1108 | { | |
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | static void lguest_apic_icr_write(u32 low, u32 id) | |
1113 | { | |
1114 | /* Warn to see if there's any stray references */ | |
1115 | WARN_ON(1); | |
1116 | } | |
1117 | ||
1118 | static void lguest_apic_wait_icr_idle(void) | |
1119 | { | |
1120 | return; | |
1121 | } | |
1122 | ||
1123 | static u32 lguest_apic_safe_wait_icr_idle(void) | |
1124 | { | |
1125 | return 0; | |
1126 | } | |
1127 | ||
c1eeb2de YL |
1128 | static void set_lguest_basic_apic_ops(void) |
1129 | { | |
1130 | apic->read = lguest_apic_read; | |
1131 | apic->write = lguest_apic_write; | |
1132 | apic->icr_read = lguest_apic_icr_read; | |
1133 | apic->icr_write = lguest_apic_icr_write; | |
1134 | apic->wait_icr_idle = lguest_apic_wait_icr_idle; | |
1135 | apic->safe_wait_icr_idle = lguest_apic_safe_wait_icr_idle; | |
511d9d34 | 1136 | }; |
07ad157f RR |
1137 | #endif |
1138 | ||
b2b47c21 | 1139 | /* STOP! Until an interrupt comes in. */ |
07ad157f RR |
1140 | static void lguest_safe_halt(void) |
1141 | { | |
091ebf07 | 1142 | hcall(LHCALL_HALT, 0, 0, 0, 0); |
07ad157f RR |
1143 | } |
1144 | ||
2e04ef76 RR |
1145 | /* |
1146 | * The SHUTDOWN hypercall takes a string to describe what's happening, and | |
a6bd8e13 | 1147 | * an argument which says whether this to restart (reboot) the Guest or not. |
b2b47c21 RR |
1148 | * |
1149 | * Note that the Host always prefers that the Guest speak in physical addresses | |
2e04ef76 RR |
1150 | * rather than virtual addresses, so we use __pa() here. |
1151 | */ | |
07ad157f RR |
1152 | static void lguest_power_off(void) |
1153 | { | |
091ebf07 RR |
1154 | hcall(LHCALL_SHUTDOWN, __pa("Power down"), |
1155 | LGUEST_SHUTDOWN_POWEROFF, 0, 0); | |
07ad157f RR |
1156 | } |
1157 | ||
b2b47c21 RR |
1158 | /* |
1159 | * Panicing. | |
1160 | * | |
1161 | * Don't. But if you did, this is what happens. | |
1162 | */ | |
07ad157f RR |
1163 | static int lguest_panic(struct notifier_block *nb, unsigned long l, void *p) |
1164 | { | |
091ebf07 | 1165 | hcall(LHCALL_SHUTDOWN, __pa(p), LGUEST_SHUTDOWN_POWEROFF, 0, 0); |
b2b47c21 | 1166 | /* The hcall won't return, but to keep gcc happy, we're "done". */ |
07ad157f RR |
1167 | return NOTIFY_DONE; |
1168 | } | |
1169 | ||
1170 | static struct notifier_block paniced = { | |
1171 | .notifier_call = lguest_panic | |
1172 | }; | |
1173 | ||
b2b47c21 | 1174 | /* Setting up memory is fairly easy. */ |
07ad157f RR |
1175 | static __init char *lguest_memory_setup(void) |
1176 | { | |
2e04ef76 | 1177 | /* |
9f54288d | 1178 | * The Linux bootloader header contains an "e820" memory map: the |
2e04ef76 RR |
1179 | * Launcher populated the first entry with our memory limit. |
1180 | */ | |
d0be6bde | 1181 | e820_add_region(boot_params.e820_map[0].addr, |
30c82645 PA |
1182 | boot_params.e820_map[0].size, |
1183 | boot_params.e820_map[0].type); | |
b2b47c21 RR |
1184 | |
1185 | /* This string is for the boot messages. */ | |
07ad157f RR |
1186 | return "LGUEST"; |
1187 | } | |
1188 | ||
a561adfa RR |
1189 | /* Offset within PCI config space of BAR access capability. */ |
1190 | static int console_cfg_offset = 0; | |
1191 | static int console_access_cap; | |
1192 | ||
1193 | /* Set up so that we access off in bar0 (on bus 0, device 1, function 0) */ | |
1194 | static void set_cfg_window(u32 cfg_offset, u32 off) | |
1195 | { | |
1196 | write_pci_config_byte(0, 1, 0, | |
1197 | cfg_offset + offsetof(struct virtio_pci_cap, bar), | |
1198 | 0); | |
1199 | write_pci_config(0, 1, 0, | |
1200 | cfg_offset + offsetof(struct virtio_pci_cap, length), | |
1201 | 4); | |
1202 | write_pci_config(0, 1, 0, | |
1203 | cfg_offset + offsetof(struct virtio_pci_cap, offset), | |
1204 | off); | |
1205 | } | |
1206 | ||
a561adfa RR |
1207 | static void write_bar_via_cfg(u32 cfg_offset, u32 off, u32 val) |
1208 | { | |
55c2d788 RR |
1209 | /* |
1210 | * We could set this up once, then leave it; nothing else in the * | |
1211 | * kernel should touch these registers. But if it went wrong, that | |
1212 | * would be a horrible bug to find. | |
1213 | */ | |
a561adfa RR |
1214 | set_cfg_window(cfg_offset, off); |
1215 | write_pci_config(0, 1, 0, | |
1216 | cfg_offset + sizeof(struct virtio_pci_cap), val); | |
1217 | } | |
1218 | ||
1219 | static void probe_pci_console(void) | |
1220 | { | |
1221 | u8 cap, common_cap = 0, device_cap = 0; | |
55c2d788 | 1222 | u32 device_len; |
a561adfa RR |
1223 | |
1224 | /* Avoid recursive printk into here. */ | |
1225 | console_cfg_offset = -1; | |
1226 | ||
1227 | if (!early_pci_allowed()) { | |
1228 | printk(KERN_ERR "lguest: early PCI access not allowed!\n"); | |
1229 | return; | |
1230 | } | |
1231 | ||
1232 | /* We expect a console PCI device at BUS0, slot 1. */ | |
1233 | if (read_pci_config(0, 1, 0, 0) != 0x10431AF4) { | |
1234 | printk(KERN_ERR "lguest: PCI device is %#x!\n", | |
1235 | read_pci_config(0, 1, 0, 0)); | |
1236 | return; | |
1237 | } | |
1238 | ||
1239 | /* Find the capabilities we need (must be in bar0) */ | |
1240 | cap = read_pci_config_byte(0, 1, 0, PCI_CAPABILITY_LIST); | |
1241 | while (cap) { | |
1242 | u8 vndr = read_pci_config_byte(0, 1, 0, cap); | |
1243 | if (vndr == PCI_CAP_ID_VNDR) { | |
1244 | u8 type, bar; | |
a561adfa RR |
1245 | |
1246 | type = read_pci_config_byte(0, 1, 0, | |
1247 | cap + offsetof(struct virtio_pci_cap, cfg_type)); | |
1248 | bar = read_pci_config_byte(0, 1, 0, | |
1249 | cap + offsetof(struct virtio_pci_cap, bar)); | |
a561adfa RR |
1250 | |
1251 | switch (type) { | |
a561adfa | 1252 | case VIRTIO_PCI_CAP_DEVICE_CFG: |
cf2cf0f5 | 1253 | if (bar == 0) |
a561adfa | 1254 | device_cap = cap; |
a561adfa RR |
1255 | break; |
1256 | case VIRTIO_PCI_CAP_PCI_CFG: | |
1257 | console_access_cap = cap; | |
1258 | break; | |
1259 | } | |
1260 | } | |
1261 | cap = read_pci_config_byte(0, 1, 0, cap + PCI_CAP_LIST_NEXT); | |
1262 | } | |
55c2d788 | 1263 | if (!device_cap || !console_access_cap) { |
a561adfa RR |
1264 | printk(KERN_ERR "lguest: No caps (%u/%u/%u) in console!\n", |
1265 | common_cap, device_cap, console_access_cap); | |
1266 | return; | |
1267 | } | |
1268 | ||
55c2d788 RR |
1269 | /* |
1270 | * Note that we can't check features, until we've set the DRIVER | |
1271 | * status bit. We don't want to do that until we have a real driver, | |
1272 | * so we just check that the device-specific config has room for | |
1273 | * emerg_wr. If it doesn't support VIRTIO_CONSOLE_F_EMERG_WRITE | |
1274 | * it should ignore the access. | |
1275 | */ | |
7faf90ef PB |
1276 | device_len = read_pci_config(0, 1, 0, |
1277 | device_cap + offsetof(struct virtio_pci_cap, length)); | |
55c2d788 RR |
1278 | if (device_len < (offsetof(struct virtio_console_config, emerg_wr) |
1279 | + sizeof(u32))) { | |
1280 | printk(KERN_ERR "lguest: console missing emerg_wr field\n"); | |
a561adfa RR |
1281 | return; |
1282 | } | |
1283 | ||
cf2cf0f5 PB |
1284 | console_cfg_offset = read_pci_config(0, 1, 0, |
1285 | device_cap + offsetof(struct virtio_pci_cap, offset)); | |
55c2d788 | 1286 | printk(KERN_INFO "lguest: Console via virtio-pci emerg_wr\n"); |
a561adfa RR |
1287 | } |
1288 | ||
2e04ef76 RR |
1289 | /* |
1290 | * We will eventually use the virtio console device to produce console output, | |
a561adfa RR |
1291 | * but before that is set up we use the virtio PCI console's backdoor mmio |
1292 | * access and the "emergency" write facility (which is legal even before the | |
1293 | * device is configured). | |
2e04ef76 | 1294 | */ |
19f1537b RR |
1295 | static __init int early_put_chars(u32 vtermno, const char *buf, int count) |
1296 | { | |
a561adfa RR |
1297 | /* If we couldn't find PCI console, forget it. */ |
1298 | if (console_cfg_offset < 0) | |
1299 | return count; | |
19f1537b | 1300 | |
a561adfa RR |
1301 | if (unlikely(!console_cfg_offset)) { |
1302 | probe_pci_console(); | |
1303 | if (console_cfg_offset < 0) | |
1304 | return count; | |
1305 | } | |
19f1537b | 1306 | |
a561adfa RR |
1307 | write_bar_via_cfg(console_access_cap, |
1308 | console_cfg_offset | |
1309 | + offsetof(struct virtio_console_config, emerg_wr), | |
1310 | buf[0]); | |
1311 | return 1; | |
19f1537b RR |
1312 | } |
1313 | ||
2e04ef76 RR |
1314 | /* |
1315 | * Rebooting also tells the Host we're finished, but the RESTART flag tells the | |
1316 | * Launcher to reboot us. | |
1317 | */ | |
a6bd8e13 RR |
1318 | static void lguest_restart(char *reason) |
1319 | { | |
091ebf07 | 1320 | hcall(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART, 0, 0); |
a6bd8e13 RR |
1321 | } |
1322 | ||
b2b47c21 RR |
1323 | /*G:050 |
1324 | * Patching (Powerfully Placating Performance Pedants) | |
1325 | * | |
a6bd8e13 RR |
1326 | * We have already seen that pv_ops structures let us replace simple native |
1327 | * instructions with calls to the appropriate back end all throughout the | |
1328 | * kernel. This allows the same kernel to run as a Guest and as a native | |
b2b47c21 RR |
1329 | * kernel, but it's slow because of all the indirect branches. |
1330 | * | |
1331 | * Remember that David Wheeler quote about "Any problem in computer science can | |
1332 | * be solved with another layer of indirection"? The rest of that quote is | |
1333 | * "... But that usually will create another problem." This is the first of | |
1334 | * those problems. | |
1335 | * | |
1336 | * Our current solution is to allow the paravirt back end to optionally patch | |
1337 | * over the indirect calls to replace them with something more efficient. We | |
a32a8813 RR |
1338 | * patch two of the simplest of the most commonly called functions: disable |
1339 | * interrupts and save interrupts. We usually have 6 or 10 bytes to patch | |
1340 | * into: the Guest versions of these operations are small enough that we can | |
1341 | * fit comfortably. | |
b2b47c21 RR |
1342 | * |
1343 | * First we need assembly templates of each of the patchable Guest operations, | |
41f055d4 | 1344 | * and these are in head_32.S. |
2e04ef76 | 1345 | */ |
b2b47c21 RR |
1346 | |
1347 | /*G:060 We construct a table from the assembler templates: */ | |
07ad157f RR |
1348 | static const struct lguest_insns |
1349 | { | |
1350 | const char *start, *end; | |
1351 | } lguest_insns[] = { | |
93b1eab3 | 1352 | [PARAVIRT_PATCH(pv_irq_ops.irq_disable)] = { lgstart_cli, lgend_cli }, |
93b1eab3 | 1353 | [PARAVIRT_PATCH(pv_irq_ops.save_fl)] = { lgstart_pushf, lgend_pushf }, |
07ad157f | 1354 | }; |
b2b47c21 | 1355 | |
2e04ef76 RR |
1356 | /* |
1357 | * Now our patch routine is fairly simple (based on the native one in | |
b2b47c21 | 1358 | * paravirt.c). If we have a replacement, we copy it in and return how much of |
2e04ef76 RR |
1359 | * the available space we used. |
1360 | */ | |
ab144f5e AK |
1361 | static unsigned lguest_patch(u8 type, u16 clobber, void *ibuf, |
1362 | unsigned long addr, unsigned len) | |
07ad157f RR |
1363 | { |
1364 | unsigned int insn_len; | |
1365 | ||
b2b47c21 | 1366 | /* Don't do anything special if we don't have a replacement */ |
07ad157f | 1367 | if (type >= ARRAY_SIZE(lguest_insns) || !lguest_insns[type].start) |
ab144f5e | 1368 | return paravirt_patch_default(type, clobber, ibuf, addr, len); |
07ad157f RR |
1369 | |
1370 | insn_len = lguest_insns[type].end - lguest_insns[type].start; | |
1371 | ||
2e04ef76 | 1372 | /* Similarly if it can't fit (doesn't happen, but let's be thorough). */ |
07ad157f | 1373 | if (len < insn_len) |
ab144f5e | 1374 | return paravirt_patch_default(type, clobber, ibuf, addr, len); |
07ad157f | 1375 | |
b2b47c21 | 1376 | /* Copy in our instructions. */ |
ab144f5e | 1377 | memcpy(ibuf, lguest_insns[type].start, insn_len); |
07ad157f RR |
1378 | return insn_len; |
1379 | } | |
1380 | ||
2e04ef76 RR |
1381 | /*G:029 |
1382 | * Once we get to lguest_init(), we know we're a Guest. The various | |
a6bd8e13 | 1383 | * pv_ops structures in the kernel provide points for (almost) every routine we |
2e04ef76 RR |
1384 | * have to override to avoid privileged instructions. |
1385 | */ | |
814a0e5c | 1386 | __init void lguest_init(void) |
07ad157f | 1387 | { |
2e04ef76 | 1388 | /* We're under lguest. */ |
93b1eab3 | 1389 | pv_info.name = "lguest"; |
2e04ef76 | 1390 | /* We're running at privilege level 1, not 0 as normal. */ |
93b1eab3 | 1391 | pv_info.kernel_rpl = 1; |
2e04ef76 | 1392 | /* Everyone except Xen runs with this set. */ |
acdd0b62 | 1393 | pv_info.shared_kernel_pmd = 1; |
07ad157f | 1394 | |
2e04ef76 RR |
1395 | /* |
1396 | * We set up all the lguest overrides for sensitive operations. These | |
1397 | * are detailed with the operations themselves. | |
1398 | */ | |
93b1eab3 | 1399 | |
2e04ef76 | 1400 | /* Interrupt-related operations */ |
9549b9b3 | 1401 | pv_irq_ops.save_fl = PV_CALLEE_SAVE(lguest_save_fl); |
61f4bc83 | 1402 | pv_irq_ops.restore_fl = __PV_IS_CALLEE_SAVE(lg_restore_fl); |
9549b9b3 | 1403 | pv_irq_ops.irq_disable = PV_CALLEE_SAVE(lguest_irq_disable); |
61f4bc83 | 1404 | pv_irq_ops.irq_enable = __PV_IS_CALLEE_SAVE(lg_irq_enable); |
93b1eab3 JF |
1405 | pv_irq_ops.safe_halt = lguest_safe_halt; |
1406 | ||
2e04ef76 | 1407 | /* Setup operations */ |
93b1eab3 JF |
1408 | pv_init_ops.patch = lguest_patch; |
1409 | ||
2e04ef76 | 1410 | /* Intercepts of various CPU instructions */ |
93b1eab3 JF |
1411 | pv_cpu_ops.load_gdt = lguest_load_gdt; |
1412 | pv_cpu_ops.cpuid = lguest_cpuid; | |
1413 | pv_cpu_ops.load_idt = lguest_load_idt; | |
1414 | pv_cpu_ops.iret = lguest_iret; | |
faca6227 | 1415 | pv_cpu_ops.load_sp0 = lguest_load_sp0; |
93b1eab3 JF |
1416 | pv_cpu_ops.load_tr_desc = lguest_load_tr_desc; |
1417 | pv_cpu_ops.set_ldt = lguest_set_ldt; | |
1418 | pv_cpu_ops.load_tls = lguest_load_tls; | |
aa96a3c6 | 1419 | pv_cpu_ops.get_debugreg = lguest_get_debugreg; |
93b1eab3 | 1420 | pv_cpu_ops.set_debugreg = lguest_set_debugreg; |
93b1eab3 JF |
1421 | pv_cpu_ops.read_cr0 = lguest_read_cr0; |
1422 | pv_cpu_ops.write_cr0 = lguest_write_cr0; | |
1423 | pv_cpu_ops.read_cr4 = lguest_read_cr4; | |
1424 | pv_cpu_ops.write_cr4 = lguest_write_cr4; | |
1425 | pv_cpu_ops.write_gdt_entry = lguest_write_gdt_entry; | |
1426 | pv_cpu_ops.write_idt_entry = lguest_write_idt_entry; | |
1427 | pv_cpu_ops.wbinvd = lguest_wbinvd; | |
224101ed JF |
1428 | pv_cpu_ops.start_context_switch = paravirt_start_context_switch; |
1429 | pv_cpu_ops.end_context_switch = lguest_end_context_switch; | |
93b1eab3 | 1430 | |
2e04ef76 | 1431 | /* Pagetable management */ |
93b1eab3 JF |
1432 | pv_mmu_ops.write_cr3 = lguest_write_cr3; |
1433 | pv_mmu_ops.flush_tlb_user = lguest_flush_tlb_user; | |
1434 | pv_mmu_ops.flush_tlb_single = lguest_flush_tlb_single; | |
1435 | pv_mmu_ops.flush_tlb_kernel = lguest_flush_tlb_kernel; | |
1436 | pv_mmu_ops.set_pte = lguest_set_pte; | |
1437 | pv_mmu_ops.set_pte_at = lguest_set_pte_at; | |
1438 | pv_mmu_ops.set_pmd = lguest_set_pmd; | |
acdd0b62 MZ |
1439 | #ifdef CONFIG_X86_PAE |
1440 | pv_mmu_ops.set_pte_atomic = lguest_set_pte_atomic; | |
1441 | pv_mmu_ops.pte_clear = lguest_pte_clear; | |
1442 | pv_mmu_ops.pmd_clear = lguest_pmd_clear; | |
1443 | pv_mmu_ops.set_pud = lguest_set_pud; | |
1444 | #endif | |
93b1eab3 JF |
1445 | pv_mmu_ops.read_cr2 = lguest_read_cr2; |
1446 | pv_mmu_ops.read_cr3 = lguest_read_cr3; | |
8965c1c0 | 1447 | pv_mmu_ops.lazy_mode.enter = paravirt_enter_lazy_mmu; |
b407fc57 | 1448 | pv_mmu_ops.lazy_mode.leave = lguest_leave_lazy_mmu_mode; |
511ba86e | 1449 | pv_mmu_ops.lazy_mode.flush = paravirt_flush_lazy_mmu; |
b7ff99ea | 1450 | pv_mmu_ops.pte_update = lguest_pte_update; |
93b1eab3 | 1451 | |
07ad157f | 1452 | #ifdef CONFIG_X86_LOCAL_APIC |
2e04ef76 | 1453 | /* APIC read/write intercepts */ |
c1eeb2de | 1454 | set_lguest_basic_apic_ops(); |
07ad157f | 1455 | #endif |
93b1eab3 | 1456 | |
6b18ae3e | 1457 | x86_init.resources.memory_setup = lguest_memory_setup; |
66bcaf0b | 1458 | x86_init.irqs.intr_init = lguest_init_IRQ; |
845b3944 | 1459 | x86_init.timers.timer_init = lguest_time_init; |
2d826404 | 1460 | x86_platform.calibrate_tsc = lguest_tsc_khz; |
7bd867df | 1461 | x86_platform.get_wallclock = lguest_get_wallclock; |
6b18ae3e | 1462 | |
2e04ef76 RR |
1463 | /* |
1464 | * Now is a good time to look at the implementations of these functions | |
1465 | * before returning to the rest of lguest_init(). | |
1466 | */ | |
b2b47c21 | 1467 | |
2e04ef76 RR |
1468 | /*G:070 |
1469 | * Now we've seen all the paravirt_ops, we return to | |
b2b47c21 | 1470 | * lguest_init() where the rest of the fairly chaotic boot setup |
2e04ef76 RR |
1471 | * occurs. |
1472 | */ | |
07ad157f | 1473 | |
2e04ef76 RR |
1474 | /* |
1475 | * The stack protector is a weird thing where gcc places a canary | |
2cb7878a RR |
1476 | * value on the stack and then checks it on return. This file is |
1477 | * compiled with -fno-stack-protector it, so we got this far without | |
1478 | * problems. The value of the canary is kept at offset 20 from the | |
1479 | * %gs register, so we need to set that up before calling C functions | |
2e04ef76 RR |
1480 | * in other files. |
1481 | */ | |
2cb7878a | 1482 | setup_stack_canary_segment(0); |
2e04ef76 RR |
1483 | |
1484 | /* | |
1485 | * We could just call load_stack_canary_segment(), but we might as well | |
1486 | * call switch_to_new_gdt() which loads the whole table and sets up the | |
1487 | * per-cpu segment descriptor register %fs as well. | |
1488 | */ | |
2cb7878a RR |
1489 | switch_to_new_gdt(0); |
1490 | ||
2e04ef76 RR |
1491 | /* |
1492 | * The Host<->Guest Switcher lives at the top of our address space, and | |
a6bd8e13 | 1493 | * the Host told us how big it is when we made LGUEST_INIT hypercall: |
2e04ef76 RR |
1494 | * it put the answer in lguest_data.reserve_mem |
1495 | */ | |
07ad157f RR |
1496 | reserve_top_address(lguest_data.reserve_mem); |
1497 | ||
cdae0ad5 RR |
1498 | /* Hook in our special panic hypercall code. */ |
1499 | atomic_notifier_chain_register(&panic_notifier_list, &paniced); | |
1500 | ||
2e04ef76 RR |
1501 | /* |
1502 | * This is messy CPU setup stuff which the native boot code does before | |
1503 | * start_kernel, so we have to do, too: | |
1504 | */ | |
07ad157f RR |
1505 | cpu_detect(&new_cpu_data); |
1506 | /* head.S usually sets up the first capability word, so do it here. */ | |
16aaa537 | 1507 | new_cpu_data.x86_capability[CPUID_1_EDX] = cpuid_edx(1); |
07ad157f RR |
1508 | |
1509 | /* Math is always hard! */ | |
60e019eb | 1510 | set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU); |
07ad157f | 1511 | |
a6bd8e13 | 1512 | /* We don't have features. We have puppies! Puppies! */ |
07ad157f | 1513 | #ifdef CONFIG_X86_MCE |
1462594b | 1514 | mca_cfg.disabled = true; |
07ad157f | 1515 | #endif |
07ad157f RR |
1516 | #ifdef CONFIG_ACPI |
1517 | acpi_disabled = 1; | |
07ad157f RR |
1518 | #endif |
1519 | ||
2e04ef76 RR |
1520 | /* |
1521 | * We set the preferred console to "hvc". This is the "hypervisor | |
b2b47c21 | 1522 | * virtual console" driver written by the PowerPC people, which we also |
2e04ef76 RR |
1523 | * adapted for lguest's use. |
1524 | */ | |
07ad157f RR |
1525 | add_preferred_console("hvc", 0, NULL); |
1526 | ||
19f1537b RR |
1527 | /* Register our very early console. */ |
1528 | virtio_cons_early_init(early_put_chars); | |
1529 | ||
ee72576c RR |
1530 | /* Don't let ACPI try to control our PCI interrupts. */ |
1531 | disable_acpi(); | |
1532 | ||
e1b83e27 RR |
1533 | /* We control them ourselves, by overriding these two hooks. */ |
1534 | pcibios_enable_irq = lguest_enable_irq; | |
1535 | pcibios_disable_irq = lguest_disable_irq; | |
1536 | ||
2e04ef76 RR |
1537 | /* |
1538 | * Last of all, we set the power management poweroff hook to point to | |
a6bd8e13 | 1539 | * the Guest routine to power off, and the reboot hook to our restart |
2e04ef76 RR |
1540 | * routine. |
1541 | */ | |
07ad157f | 1542 | pm_power_off = lguest_power_off; |
ec04b13f | 1543 | machine_ops.restart = lguest_restart; |
a6bd8e13 | 1544 | |
2e04ef76 RR |
1545 | /* |
1546 | * Now we're set up, call i386_start_kernel() in head32.c and we proceed | |
1547 | * to boot as normal. It never returns. | |
1548 | */ | |
f0d43100 | 1549 | i386_start_kernel(); |
07ad157f | 1550 | } |
b2b47c21 RR |
1551 | /* |
1552 | * This marks the end of stage II of our journey, The Guest. | |
1553 | * | |
e1e72965 RR |
1554 | * It is now time for us to explore the layer of virtual drivers and complete |
1555 | * our understanding of the Guest in "make Drivers". | |
b2b47c21 | 1556 | */ |