projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Only x86 has pio
[linux-2.6-block.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
6aa8b732
AK		 29#define DPRINTF(x...) do {} while (0)
30#endif
6aa8b732 31#include <linux/module.h>
edf88417 32#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
c7e75a3d 65#define MemAbs (1<<9) /* Memory operand is absolute displacement */
b9fa9d6b 66#define String (1<<10) /* String instruction (rep capable) */
6e3d5dfb 67#define Stack (1<<11) /* Stack instruction (push/pop) */
e09d082c
AK		 68#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
69#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
70#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 71
43bb19cd 72enum {
d95058a1 73 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 74};
75
c7e75a3d 76static u16 opcode_table[256] = {
6aa8b732
AK		 77 /* 0x00 - 0x07 */
78 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
79 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
80 0, 0, 0, 0,
81 /* 0x08 - 0x0F */
82 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
83 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
84 0, 0, 0, 0,
85 /* 0x10 - 0x17 */
86 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
87 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
88 0, 0, 0, 0,
89 /* 0x18 - 0x1F */
90 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
91 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
92 0, 0, 0, 0,
93 /* 0x20 - 0x27 */
94 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
95 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 96 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 97 /* 0x28 - 0x2F */
98 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
99 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
100 0, 0, 0, 0,
101 /* 0x30 - 0x37 */
102 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
103 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
104 0, 0, 0, 0,
105 /* 0x38 - 0x3F */
106 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
107 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
108 0, 0, 0, 0,
d77a2507 109 /* 0x40 - 0x47 */
33615aa9 110 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 111 /* 0x48 - 0x4F */
33615aa9 112 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 113 /* 0x50 - 0x57 */
6e3d5dfb
AK		 114 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
115 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 116 /* 0x58 - 0x5F */
6e3d5dfb
AK		 117 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
118 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 119 /* 0x60 - 0x67 */
6aa8b732 120 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 121 0, 0, 0, 0,
122 /* 0x68 - 0x6F */
6e3d5dfb 123 0, 0, ImplicitOps | Mov | Stack, 0,
e70669ab
LV		 124 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
125 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 126 /* 0x70 - 0x77 */
127 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
128 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
129 /* 0x78 - 0x7F */
130 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 132 /* 0x80 - 0x87 */
133 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
134 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
135 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 /* 0x88 - 0x8F */
138 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
139 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
43bb19cd 140 0, ModRM | DstReg, 0, Group | Group1A,
6aa8b732 141 /* 0x90 - 0x9F */
6e3d5dfb
AK		 142 0, 0, 0, 0, 0, 0, 0, 0,
143 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 144 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 145 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
146 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 147 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
148 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 149 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 150 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
151 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
152 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732
AK		 153 /* 0xB0 - 0xBF */
154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
155 /* 0xC0 - 0xC7 */
d9413cd7 156 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 157 0, ImplicitOps | Stack, 0, 0,
d9413cd7 158 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 159 /* 0xC8 - 0xCF */
160 0, 0, 0, 0, 0, 0, 0, 0,
161 /* 0xD0 - 0xD7 */
162 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
163 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
164 0, 0, 0, 0,
165 /* 0xD8 - 0xDF */
166 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 167 /* 0xE0 - 0xE7 */
168 0, 0, 0, 0, 0, 0, 0, 0,
169 /* 0xE8 - 0xEF */
6e3d5dfb
AK		 170 ImplicitOps | Stack, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps,
171 0, 0, 0, 0,
6aa8b732
AK		 172 /* 0xF0 - 0xF7 */
173 0, 0, 0, 0,
7d858a19 174 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 175 /* 0xF8 - 0xFF */
b284be57 176 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fd60754e 177 0, 0, Group | Group4, Group | Group5,
6aa8b732
AK		 178};
179
038e51de 180static u16 twobyte_table[256] = {
6aa8b732 181 /* 0x00 - 0x0F */
d95058a1 182 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 183 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 184 /* 0x10 - 0x1F */
185 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
186 /* 0x20 - 0x2F */
187 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
188 0, 0, 0, 0, 0, 0, 0, 0,
189 /* 0x30 - 0x3F */
35f3f286 190 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 191 /* 0x40 - 0x47 */
192 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
193 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
194 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
195 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
196 /* 0x48 - 0x4F */
197 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
198 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
199 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
200 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
201 /* 0x50 - 0x5F */
202 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
203 /* 0x60 - 0x6F */
204 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
205 /* 0x70 - 0x7F */
206 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
207 /* 0x80 - 0x8F */
bbe9abbd
NK		 208 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
209 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
210 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
211 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 212 /* 0x90 - 0x9F */
213 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
214 /* 0xA0 - 0xA7 */
038e51de 215 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 216 /* 0xA8 - 0xAF */
038e51de 217 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 218 /* 0xB0 - 0xB7 */
219 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 220 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 221 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
222 DstReg | SrcMem16 | ModRM | Mov,
223 /* 0xB8 - 0xBF */
038e51de 224 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 225 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
226 DstReg | SrcMem16 | ModRM | Mov,
227 /* 0xC0 - 0xCF */
a012e65a
SY		 228 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
229 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 230 /* 0xD0 - 0xDF */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0xE0 - 0xEF */
233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
234 /* 0xF0 - 0xFF */
235 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
236};
237
e09d082c 238static u16 group_table[] = {
43bb19cd
AK		 239 [Group1A*8] =
240 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 241 [Group3_Byte*8] =
242 ByteOp | SrcImm | DstMem | ModRM, 0,
243 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
244 0, 0, 0, 0,
245 [Group3*8] =
246 DstMem | SrcImm | ModRM | SrcImm, 0,
247 DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
248 0, 0, 0, 0,
fd60754e
AK		 249 [Group4*8] =
250 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
251 0, 0, 0, 0, 0, 0,
252 [Group5*8] =
253 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
254 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 255 [Group7*8] =
256 0, 0, ModRM | SrcMem, ModRM | SrcMem,
257 SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, SrcMem | ModRM | ByteOp,
e09d082c
AK		 258};
259
260static u16 group2_table[] = {
d95058a1
AK		 261 [Group7*8] =
262 SrcNone | ModRM, 0, 0, 0, SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, 0,
e09d082c
AK		 263};
264
6aa8b732
AK		 265/* EFLAGS bit definitions. */
266#define EFLG_OF (1<<11)
267#define EFLG_DF (1<<10)
268#define EFLG_SF (1<<7)
269#define EFLG_ZF (1<<6)
270#define EFLG_AF (1<<4)
271#define EFLG_PF (1<<2)
272#define EFLG_CF (1<<0)
273
274/*
275 * Instruction emulation:
276 * Most instructions are emulated directly via a fragment of inline assembly
277 * code. This allows us to save/restore EFLAGS and thus very easily pick up
278 * any modified flags.
279 */
280
05b3e0c2 281#if defined(CONFIG_X86_64)
6aa8b732
AK		 282#define _LO32 "k" /* force 32-bit operand */
283#define _STK "%%rsp" /* stack pointer */
284#elif defined(__i386__)
285#define _LO32 "" /* force 32-bit operand */
286#define _STK "%%esp" /* stack pointer */
287#endif
288
289/*
290 * These EFLAGS bits are restored from saved value during emulation, and
291 * any changes are written back to the saved value after emulation.
292 */
293#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
294
295/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 296#define _PRE_EFLAGS(_sav, _msk, _tmp) \
297 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
298 "movl %"_sav",%"_LO32 _tmp"; " \
299 "push %"_tmp"; " \
300 "push %"_tmp"; " \
301 "movl %"_msk",%"_LO32 _tmp"; " \
302 "andl %"_LO32 _tmp",("_STK"); " \
303 "pushf; " \
304 "notl %"_LO32 _tmp"; " \
305 "andl %"_LO32 _tmp",("_STK"); " \
306 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
307 "pop %"_tmp"; " \
308 "orl %"_LO32 _tmp",("_STK"); " \
309 "popf; " \
310 "pop %"_sav"; "
6aa8b732
AK		 311
312/* After executing instruction: write-back necessary bits in EFLAGS. */
313#define _POST_EFLAGS(_sav, _msk, _tmp) \
314 /* _sav |= EFLAGS & _msk; */ \
315 "pushf; " \
316 "pop %"_tmp"; " \
317 "andl %"_msk",%"_LO32 _tmp"; " \
318 "orl %"_LO32 _tmp",%"_sav"; "
319
320/* Raw emulation: instruction has two explicit operands. */
321#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
322 do { \
323 unsigned long _tmp; \
324 \
325 switch ((_dst).bytes) { \
326 case 2: \
327 __asm__ __volatile__ ( \
d77c26fc 328 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 329 _op"w %"_wx"3,%1; " \
d77c26fc 330 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 331 : "=m" (_eflags), "=m" ((_dst).val), \
332 "=&r" (_tmp) \
d77c26fc 333 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 334 break; \
335 case 4: \
336 __asm__ __volatile__ ( \
d77c26fc 337 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 338 _op"l %"_lx"3,%1; " \
d77c26fc 339 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 340 : "=m" (_eflags), "=m" ((_dst).val), \
341 "=&r" (_tmp) \
d77c26fc 342 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 343 break; \
344 case 8: \
345 __emulate_2op_8byte(_op, _src, _dst, \
346 _eflags, _qx, _qy); \
347 break; \
348 } \
349 } while (0)
350
351#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
352 do { \
353 unsigned long _tmp; \
d77c26fc 354 switch ((_dst).bytes) { \
6aa8b732
AK		 355 case 1: \
356 __asm__ __volatile__ ( \
d77c26fc 357 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 358 _op"b %"_bx"3,%1; " \
d77c26fc 359 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 360 : "=m" (_eflags), "=m" ((_dst).val), \
361 "=&r" (_tmp) \
d77c26fc 362 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 363 break; \
364 default: \
365 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
366 _wx, _wy, _lx, _ly, _qx, _qy); \
367 break; \
368 } \
369 } while (0)
370
371/* Source operand is byte-sized and may be restricted to just %cl. */
372#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
373 __emulate_2op(_op, _src, _dst, _eflags, \
374 "b", "c", "b", "c", "b", "c", "b", "c")
375
376/* Source operand is byte, word, long or quad sized. */
377#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
378 __emulate_2op(_op, _src, _dst, _eflags, \
379 "b", "q", "w", "r", _LO32, "r", "", "r")
380
381/* Source operand is word, long or quad sized. */
382#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
383 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
384 "w", "r", _LO32, "r", "", "r")
385
386/* Instruction has only one explicit operand (no source operand). */
387#define emulate_1op(_op, _dst, _eflags) \
388 do { \
389 unsigned long _tmp; \
390 \
d77c26fc 391 switch ((_dst).bytes) { \
6aa8b732
AK		 392 case 1: \
393 __asm__ __volatile__ ( \
d77c26fc 394 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 395 _op"b %1; " \
d77c26fc 396 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 397 : "=m" (_eflags), "=m" ((_dst).val), \
398 "=&r" (_tmp) \
d77c26fc 399 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 400 break; \
401 case 2: \
402 __asm__ __volatile__ ( \
d77c26fc 403 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 404 _op"w %1; " \
d77c26fc 405 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 406 : "=m" (_eflags), "=m" ((_dst).val), \
407 "=&r" (_tmp) \
d77c26fc 408 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 409 break; \
410 case 4: \
411 __asm__ __volatile__ ( \
d77c26fc 412 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 413 _op"l %1; " \
d77c26fc 414 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 415 : "=m" (_eflags), "=m" ((_dst).val), \
416 "=&r" (_tmp) \
d77c26fc 417 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 418 break; \
419 case 8: \
420 __emulate_1op_8byte(_op, _dst, _eflags); \
421 break; \
422 } \
423 } while (0)
424
425/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 426#if defined(CONFIG_X86_64)
6aa8b732
AK		 427#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
428 do { \
429 __asm__ __volatile__ ( \
d77c26fc 430 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 431 _op"q %"_qx"3,%1; " \
d77c26fc 432 _POST_EFLAGS("0", "4", "2") \
6aa8b732 433 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 434 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 435 } while (0)
436
437#define __emulate_1op_8byte(_op, _dst, _eflags) \
438 do { \
439 __asm__ __volatile__ ( \
d77c26fc 440 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 441 _op"q %1; " \
d77c26fc 442 _POST_EFLAGS("0", "3", "2") \
6aa8b732 443 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 444 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 445 } while (0)
446
447#elif defined(__i386__)
448#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
449#define __emulate_1op_8byte(_op, _dst, _eflags)
450#endif /* __i386__ */
451
452/* Fetch next part of the instruction being emulated. */
453#define insn_fetch(_type, _size, _eip) \
454({ unsigned long _x; \
62266869 455 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 456 if (rc != 0) \
6aa8b732
AK		 457 goto done; \
458 (_eip) += (_size); \
459 (_type)_x; \
460})
461
462/* Access/update address held in a register, based on addressing mode. */
e70669ab 463#define address_mask(reg) \
e4e03ded
LV		 464 ((c->ad_bytes == sizeof(unsigned long)) ? \
465 (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1)))
6aa8b732 466#define register_address(base, reg) \
e70669ab 467 ((base) + address_mask(reg))
6aa8b732
AK		 468#define register_address_increment(reg, inc) \
469 do { \
470 /* signed type ensures sign extension to long */ \
471 int _inc = (inc); \
e4e03ded 472 if (c->ad_bytes == sizeof(unsigned long)) \
6aa8b732
AK		 473 (reg) += _inc; \
474 else \
e4e03ded
LV		 475 (reg) = ((reg) & \
476 ~((1UL << (c->ad_bytes << 3)) - 1)) | \
477 (((reg) + _inc) & \
478 ((1UL << (c->ad_bytes << 3)) - 1)); \
6aa8b732
AK		 479 } while (0)
480
098c937b
NK		 481#define JMP_REL(rel) \
482 do { \
e4e03ded 483 register_address_increment(c->eip, rel); \
098c937b
NK		 484 } while (0)
485
62266869
AK		 486static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
487 struct x86_emulate_ops *ops,
488 unsigned long linear, u8 *dest)
489{
490 struct fetch_cache *fc = &ctxt->decode.fetch;
491 int rc;
492 int size;
493
494 if (linear < fc->start || linear >= fc->end) {
495 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
496 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
497 if (rc)
498 return rc;
499 fc->start = linear;
500 fc->end = linear + size;
501 }
502 *dest = fc->data[linear - fc->start];
503 return 0;
504}
505
506static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
507 struct x86_emulate_ops *ops,
508 unsigned long eip, void *dest, unsigned size)
509{
510 int rc = 0;
511
512 eip += ctxt->cs_base;
513 while (size--) {
514 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
515 if (rc)
516 return rc;
517 }
518 return 0;
519}
520
1e3c5cb0
RR		 521/*
522 * Given the 'reg' portion of a ModRM byte, and a register block, return a
523 * pointer into the block that addresses the relevant register.
524 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
525 */
526static void *decode_register(u8 modrm_reg, unsigned long *regs,
527 int highbyte_regs)
6aa8b732
AK		 528{
529 void *p;
530
531 p = &regs[modrm_reg];
532 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
533 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
534 return p;
535}
536
537static int read_descriptor(struct x86_emulate_ctxt *ctxt,
538 struct x86_emulate_ops *ops,
539 void *ptr,
540 u16 *size, unsigned long *address, int op_bytes)
541{
542 int rc;
543
544 if (op_bytes == 2)
545 op_bytes = 3;
546 *address = 0;
cebff02b
LV		 547 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
548 ctxt->vcpu);
6aa8b732
AK		 549 if (rc)
550 return rc;
cebff02b
LV		 551 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
552 ctxt->vcpu);
6aa8b732
AK		 553 return rc;
554}
555
bbe9abbd
NK		 556static int test_cc(unsigned int condition, unsigned int flags)
557{
558 int rc = 0;
559
560 switch ((condition & 15) >> 1) {
561 case 0: /* o */
562 rc |= (flags & EFLG_OF);
563 break;
564 case 1: /* b/c/nae */
565 rc |= (flags & EFLG_CF);
566 break;
567 case 2: /* z/e */
568 rc |= (flags & EFLG_ZF);
569 break;
570 case 3: /* be/na */
571 rc |= (flags & (EFLG_CF|EFLG_ZF));
572 break;
573 case 4: /* s */
574 rc |= (flags & EFLG_SF);
575 break;
576 case 5: /* p/pe */
577 rc |= (flags & EFLG_PF);
578 break;
579 case 7: /* le/ng */
580 rc |= (flags & EFLG_ZF);
581 /* fall through */
582 case 6: /* l/nge */
583 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
584 break;
585 }
586
587 /* Odd condition identifiers (lsb == 1) have inverted sense. */
588 return (!!rc ^ (condition & 1));
589}
590
3c118e24
AK		 591static void decode_register_operand(struct operand *op,
592 struct decode_cache *c,
3c118e24
AK		 593 int inhibit_bytereg)
594{
33615aa9 595 unsigned reg = c->modrm_reg;
9f1ef3f8 596 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 597
598 if (!(c->d & ModRM))
599 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 600 op->type = OP_REG;
601 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 602 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 603 op->val = *(u8 *)op->ptr;
604 op->bytes = 1;
605 } else {
33615aa9 606 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 607 op->bytes = c->op_bytes;
608 switch (op->bytes) {
609 case 2:
610 op->val = *(u16 *)op->ptr;
611 break;
612 case 4:
613 op->val = *(u32 *)op->ptr;
614 break;
615 case 8:
616 op->val = *(u64 *) op->ptr;
617 break;
618 }
619 }
620 op->orig_val = op->val;
621}
622
1c73ef66
AK		 623static int decode_modrm(struct x86_emulate_ctxt *ctxt,
624 struct x86_emulate_ops *ops)
625{
626 struct decode_cache *c = &ctxt->decode;
627 u8 sib;
628 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
629 int rc = 0;
630
631 if (c->rex_prefix) {
632 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
633 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
634 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
635 }
636
637 c->modrm = insn_fetch(u8, 1, c->eip);
638 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
639 c->modrm_reg |= (c->modrm & 0x38) >> 3;
640 c->modrm_rm |= (c->modrm & 0x07);
641 c->modrm_ea = 0;
642 c->use_modrm_ea = 1;
643
644 if (c->modrm_mod == 3) {
645 c->modrm_val = *(unsigned long *)
646 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
647 return rc;
648 }
649
650 if (c->ad_bytes == 2) {
651 unsigned bx = c->regs[VCPU_REGS_RBX];
652 unsigned bp = c->regs[VCPU_REGS_RBP];
653 unsigned si = c->regs[VCPU_REGS_RSI];
654 unsigned di = c->regs[VCPU_REGS_RDI];
655
656 /* 16-bit ModR/M decode. */
657 switch (c->modrm_mod) {
658 case 0:
659 if (c->modrm_rm == 6)
660 c->modrm_ea += insn_fetch(u16, 2, c->eip);
661 break;
662 case 1:
663 c->modrm_ea += insn_fetch(s8, 1, c->eip);
664 break;
665 case 2:
666 c->modrm_ea += insn_fetch(u16, 2, c->eip);
667 break;
668 }
669 switch (c->modrm_rm) {
670 case 0:
671 c->modrm_ea += bx + si;
672 break;
673 case 1:
674 c->modrm_ea += bx + di;
675 break;
676 case 2:
677 c->modrm_ea += bp + si;
678 break;
679 case 3:
680 c->modrm_ea += bp + di;
681 break;
682 case 4:
683 c->modrm_ea += si;
684 break;
685 case 5:
686 c->modrm_ea += di;
687 break;
688 case 6:
689 if (c->modrm_mod != 0)
690 c->modrm_ea += bp;
691 break;
692 case 7:
693 c->modrm_ea += bx;
694 break;
695 }
696 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
697 (c->modrm_rm == 6 && c->modrm_mod != 0))
698 if (!c->override_base)
699 c->override_base = &ctxt->ss_base;
700 c->modrm_ea = (u16)c->modrm_ea;
701 } else {
702 /* 32/64-bit ModR/M decode. */
703 switch (c->modrm_rm) {
704 case 4:
705 case 12:
706 sib = insn_fetch(u8, 1, c->eip);
707 index_reg |= (sib >> 3) & 7;
708 base_reg |= sib & 7;
709 scale = sib >> 6;
710
711 switch (base_reg) {
712 case 5:
713 if (c->modrm_mod != 0)
714 c->modrm_ea += c->regs[base_reg];
715 else
716 c->modrm_ea +=
717 insn_fetch(s32, 4, c->eip);
718 break;
719 default:
720 c->modrm_ea += c->regs[base_reg];
721 }
722 switch (index_reg) {
723 case 4:
724 break;
725 default:
726 c->modrm_ea += c->regs[index_reg] << scale;
727 }
728 break;
729 case 5:
730 if (c->modrm_mod != 0)
731 c->modrm_ea += c->regs[c->modrm_rm];
732 else if (ctxt->mode == X86EMUL_MODE_PROT64)
733 rip_relative = 1;
734 break;
735 default:
736 c->modrm_ea += c->regs[c->modrm_rm];
737 break;
738 }
739 switch (c->modrm_mod) {
740 case 0:
741 if (c->modrm_rm == 5)
742 c->modrm_ea += insn_fetch(s32, 4, c->eip);
743 break;
744 case 1:
745 c->modrm_ea += insn_fetch(s8, 1, c->eip);
746 break;
747 case 2:
748 c->modrm_ea += insn_fetch(s32, 4, c->eip);
749 break;
750 }
751 }
752 if (rip_relative) {
753 c->modrm_ea += c->eip;
754 switch (c->d & SrcMask) {
755 case SrcImmByte:
756 c->modrm_ea += 1;
757 break;
758 case SrcImm:
759 if (c->d & ByteOp)
760 c->modrm_ea += 1;
761 else
762 if (c->op_bytes == 8)
763 c->modrm_ea += 4;
764 else
765 c->modrm_ea += c->op_bytes;
766 }
767 }
768done:
769 return rc;
770}
771
772static int decode_abs(struct x86_emulate_ctxt *ctxt,
773 struct x86_emulate_ops *ops)
774{
775 struct decode_cache *c = &ctxt->decode;
776 int rc = 0;
777
778 switch (c->ad_bytes) {
779 case 2:
780 c->modrm_ea = insn_fetch(u16, 2, c->eip);
781 break;
782 case 4:
783 c->modrm_ea = insn_fetch(u32, 4, c->eip);
784 break;
785 case 8:
786 c->modrm_ea = insn_fetch(u64, 8, c->eip);
787 break;
788 }
789done:
790 return rc;
791}
792
6aa8b732 793int
8b4caf66 794x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 795{
e4e03ded 796 struct decode_cache *c = &ctxt->decode;
6aa8b732 797 int rc = 0;
6aa8b732 798 int mode = ctxt->mode;
e09d082c 799 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 800
801 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 802
e4e03ded 803 memset(c, 0, sizeof(struct decode_cache));
ad312c7c
ZX		 804 c->eip = ctxt->vcpu->arch.rip;
805 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 806
807 switch (mode) {
808 case X86EMUL_MODE_REAL:
809 case X86EMUL_MODE_PROT16:
f21b8bf4 810 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 811 break;
812 case X86EMUL_MODE_PROT32:
f21b8bf4 813 def_op_bytes = def_ad_bytes = 4;
6aa8b732 814 break;
05b3e0c2 815#ifdef CONFIG_X86_64
6aa8b732 816 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 817 def_op_bytes = 4;
818 def_ad_bytes = 8;
6aa8b732
AK		 819 break;
820#endif
821 default:
822 return -1;
823 }
824
f21b8bf4
AK		 825 c->op_bytes = def_op_bytes;
826 c->ad_bytes = def_ad_bytes;
827
6aa8b732 828 /* Legacy prefixes. */
b4c6abfe 829 for (;;) {
e4e03ded 830 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 831 case 0x66: /* operand-size override */
f21b8bf4
AK		 832 /* switch between 2/4 bytes */
833 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 834 break;
835 case 0x67: /* address-size override */
836 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 837 /* switch between 4/8 bytes */
f21b8bf4 838 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 839 else
e4e03ded 840 /* switch between 2/4 bytes */
f21b8bf4 841 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732
AK		 842 break;
843 case 0x2e: /* CS override */
e4e03ded 844 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 845 break;
846 case 0x3e: /* DS override */
e4e03ded 847 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 848 break;
849 case 0x26: /* ES override */
e4e03ded 850 c->override_base = &ctxt->es_base;
6aa8b732
AK		 851 break;
852 case 0x64: /* FS override */
e4e03ded 853 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 854 break;
855 case 0x65: /* GS override */
e4e03ded 856 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 857 break;
858 case 0x36: /* SS override */
e4e03ded 859 c->override_base = &ctxt->ss_base;
6aa8b732 860 break;
b4c6abfe
LV		 861 case 0x40 ... 0x4f: /* REX */
862 if (mode != X86EMUL_MODE_PROT64)
863 goto done_prefixes;
33615aa9 864 c->rex_prefix = c->b;
b4c6abfe 865 continue;
6aa8b732 866 case 0xf0: /* LOCK */
e4e03ded 867 c->lock_prefix = 1;
6aa8b732 868 break;
ae6200ba 869 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 870 c->rep_prefix = REPNE_PREFIX;
871 break;
6aa8b732 872 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 873 c->rep_prefix = REPE_PREFIX;
6aa8b732 874 break;
6aa8b732
AK		 875 default:
876 goto done_prefixes;
877 }
b4c6abfe
LV		 878
879 /* Any legacy prefix after a REX prefix nullifies its effect. */
880
33615aa9 881 c->rex_prefix = 0;
6aa8b732
AK		 882 }
883
884done_prefixes:
885
886 /* REX prefix. */
1c73ef66 887 if (c->rex_prefix)
33615aa9 888 if (c->rex_prefix & 8)
e4e03ded 889 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 890
891 /* Opcode byte(s). */
e4e03ded
LV		 892 c->d = opcode_table[c->b];
893 if (c->d == 0) {
6aa8b732 894 /* Two-byte opcode? */
e4e03ded
LV		 895 if (c->b == 0x0f) {
896 c->twobyte = 1;
897 c->b = insn_fetch(u8, 1, c->eip);
898 c->d = twobyte_table[c->b];
6aa8b732 899 }
e09d082c 900 }
6aa8b732 901
e09d082c
AK		 902 if (c->d & Group) {
903 group = c->d & GroupMask;
904 c->modrm = insn_fetch(u8, 1, c->eip);
905 --c->eip;
906
907 group = (group << 3) + ((c->modrm >> 3) & 7);
908 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
909 c->d = group2_table[group];
910 else
911 c->d = group_table[group];
912 }
913
914 /* Unrecognised? */
915 if (c->d == 0) {
916 DPRINTF("Cannot emulate %02x\n", c->b);
917 return -1;
6aa8b732
AK		 918 }
919
6e3d5dfb
AK		 920 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
921 c->op_bytes = 8;
922
6aa8b732 923 /* ModRM and SIB bytes. */
1c73ef66
AK		 924 if (c->d & ModRM)
925 rc = decode_modrm(ctxt, ops);
926 else if (c->d & MemAbs)
927 rc = decode_abs(ctxt, ops);
928 if (rc)
929 goto done;
6aa8b732 930
c7e75a3d
AK		 931 if (!c->override_base)
932 c->override_base = &ctxt->ds_base;
933 if (mode == X86EMUL_MODE_PROT64 &&
934 c->override_base != &ctxt->fs_base &&
935 c->override_base != &ctxt->gs_base)
936 c->override_base = NULL;
937
938 if (c->override_base)
939 c->modrm_ea += *c->override_base;
940
941 if (c->ad_bytes != 8)
942 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 943 /*
944 * Decode and fetch the source operand: register, memory
945 * or immediate.
946 */
e4e03ded 947 switch (c->d & SrcMask) {
6aa8b732
AK		 948 case SrcNone:
949 break;
950 case SrcReg:
9f1ef3f8 951 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 952 break;
953 case SrcMem16:
e4e03ded 954 c->src.bytes = 2;
6aa8b732
AK		 955 goto srcmem_common;
956 case SrcMem32:
e4e03ded 957 c->src.bytes = 4;
6aa8b732
AK		 958 goto srcmem_common;
959 case SrcMem:
e4e03ded
LV		 960 c->src.bytes = (c->d & ByteOp) ? 1 :
961 c->op_bytes;
b85b9ee9 962 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 963 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 964 break;
d77c26fc 965 srcmem_common:
4e62417b
AJ		 966 /*
967 * For instructions with a ModR/M byte, switch to register
968 * access if Mod = 3.
969 */
e4e03ded
LV		 970 if ((c->d & ModRM) && c->modrm_mod == 3) {
971 c->src.type = OP_REG;
4e62417b
AJ		 972 break;
973 }
e4e03ded 974 c->src.type = OP_MEM;
6aa8b732
AK		 975 break;
976 case SrcImm:
e4e03ded
LV		 977 c->src.type = OP_IMM;
978 c->src.ptr = (unsigned long *)c->eip;
979 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
980 if (c->src.bytes == 8)
981 c->src.bytes = 4;
6aa8b732 982 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 983 switch (c->src.bytes) {
6aa8b732 984 case 1:
e4e03ded 985 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 986 break;
987 case 2:
e4e03ded 988 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 989 break;
990 case 4:
e4e03ded 991 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 992 break;
993 }
994 break;
995 case SrcImmByte:
e4e03ded
LV		 996 c->src.type = OP_IMM;
997 c->src.ptr = (unsigned long *)c->eip;
998 c->src.bytes = 1;
999 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1000 break;
1001 }
1002
038e51de 1003 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1004 switch (c->d & DstMask) {
038e51de
AK		 1005 case ImplicitOps:
1006 /* Special instructions do their own operand decoding. */
8b4caf66 1007 return 0;
038e51de 1008 case DstReg:
9f1ef3f8 1009 decode_register_operand(&c->dst, c,
3c118e24 1010 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1011 break;
1012 case DstMem:
e4e03ded
LV		 1013 if ((c->d & ModRM) && c->modrm_mod == 3) {
1014 c->dst.type = OP_REG;
4e62417b
AJ		 1015 break;
1016 }
8b4caf66
LV		 1017 c->dst.type = OP_MEM;
1018 break;
1019 }
1020
1021done:
1022 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1023}
1024
8cdbd2c9
LV		 1025static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1026{
1027 struct decode_cache *c = &ctxt->decode;
1028
1029 c->dst.type = OP_MEM;
1030 c->dst.bytes = c->op_bytes;
1031 c->dst.val = c->src.val;
1032 register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes);
1033 c->dst.ptr = (void *) register_address(ctxt->ss_base,
1034 c->regs[VCPU_REGS_RSP]);
1035}
1036
1037static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1038 struct x86_emulate_ops *ops)
1039{
1040 struct decode_cache *c = &ctxt->decode;
1041 int rc;
1042
8cdbd2c9
LV		 1043 rc = ops->read_std(register_address(ctxt->ss_base,
1044 c->regs[VCPU_REGS_RSP]),
1045 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1046 if (rc != 0)
1047 return rc;
1048
1049 register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes);
1050
1051 return 0;
1052}
1053
05f086f8 1054static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1055{
05f086f8 1056 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1057 switch (c->modrm_reg) {
1058 case 0: /* rol */
05f086f8 1059 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1060 break;
1061 case 1: /* ror */
05f086f8 1062 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1063 break;
1064 case 2: /* rcl */
05f086f8 1065 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1066 break;
1067 case 3: /* rcr */
05f086f8 1068 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1069 break;
1070 case 4: /* sal/shl */
1071 case 6: /* sal/shl */
05f086f8 1072 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1073 break;
1074 case 5: /* shr */
05f086f8 1075 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1076 break;
1077 case 7: /* sar */
05f086f8 1078 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1079 break;
1080 }
1081}
1082
1083static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1084 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1085{
1086 struct decode_cache *c = &ctxt->decode;
1087 int rc = 0;
1088
1089 switch (c->modrm_reg) {
1090 case 0 ... 1: /* test */
05f086f8 1091 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1092 break;
1093 case 2: /* not */
1094 c->dst.val = ~c->dst.val;
1095 break;
1096 case 3: /* neg */
05f086f8 1097 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1098 break;
1099 default:
1100 DPRINTF("Cannot emulate %02x\n", c->b);
1101 rc = X86EMUL_UNHANDLEABLE;
1102 break;
1103 }
8cdbd2c9
LV		 1104 return rc;
1105}
1106
1107static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1108 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1109{
1110 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1111
1112 switch (c->modrm_reg) {
1113 case 0: /* inc */
05f086f8 1114 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1115 break;
1116 case 1: /* dec */
05f086f8 1117 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1118 break;
1119 case 4: /* jmp abs */
fd60754e 1120 c->eip = c->src.val;
8cdbd2c9
LV		 1121 break;
1122 case 6: /* push */
fd60754e 1123 emulate_push(ctxt);
8cdbd2c9 1124 break;
8cdbd2c9
LV		 1125 }
1126 return 0;
1127}
1128
1129static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1130 struct x86_emulate_ops *ops,
e8d8d7fe 1131 unsigned long memop)
8cdbd2c9
LV		 1132{
1133 struct decode_cache *c = &ctxt->decode;
1134 u64 old, new;
1135 int rc;
1136
e8d8d7fe 1137 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1138 if (rc != 0)
1139 return rc;
1140
1141 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1142 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1143
1144 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1145 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1146 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1147
1148 } else {
1149 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1150 (u32) c->regs[VCPU_REGS_RBX];
1151
e8d8d7fe 1152 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1153 if (rc != 0)
1154 return rc;
05f086f8 1155 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1156 }
1157 return 0;
1158}
1159
1160static inline int writeback(struct x86_emulate_ctxt *ctxt,
1161 struct x86_emulate_ops *ops)
1162{
1163 int rc;
1164 struct decode_cache *c = &ctxt->decode;
1165
1166 switch (c->dst.type) {
1167 case OP_REG:
1168 /* The 4-byte case *is* correct:
1169 * in 64-bit mode we zero-extend.
1170 */
1171 switch (c->dst.bytes) {
1172 case 1:
1173 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1174 break;
1175 case 2:
1176 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1177 break;
1178 case 4:
1179 *c->dst.ptr = (u32)c->dst.val;
1180 break; /* 64b: zero-ext */
1181 case 8:
1182 *c->dst.ptr = c->dst.val;
1183 break;
1184 }
1185 break;
1186 case OP_MEM:
1187 if (c->lock_prefix)
1188 rc = ops->cmpxchg_emulated(
1189 (unsigned long)c->dst.ptr,
1190 &c->dst.orig_val,
1191 &c->dst.val,
1192 c->dst.bytes,
1193 ctxt->vcpu);
1194 else
1195 rc = ops->write_emulated(
1196 (unsigned long)c->dst.ptr,
1197 &c->dst.val,
1198 c->dst.bytes,
1199 ctxt->vcpu);
1200 if (rc != 0)
1201 return rc;
a01af5ec
LV		 1202 break;
1203 case OP_NONE:
1204 /* no writeback */
1205 break;
8cdbd2c9
LV		 1206 default:
1207 break;
1208 }
1209 return 0;
1210}
1211
8b4caf66 1212int
1be3aa47 1213x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1214{
e8d8d7fe 1215 unsigned long memop = 0;
8b4caf66 1216 u64 msr_data;
3427318f 1217 unsigned long saved_eip = 0;
8b4caf66 1218 struct decode_cache *c = &ctxt->decode;
1be3aa47 1219 int rc = 0;
8b4caf66 1220
3427318f
LV		 1221 /* Shadow copy of register state. Committed on successful emulation.
1222 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1223 * modify them.
1224 */
1225
ad312c7c 1226 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1227 saved_eip = c->eip;
1228
c7e75a3d 1229 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1230 memop = c->modrm_ea;
8b4caf66 1231
b9fa9d6b
AK		 1232 if (c->rep_prefix && (c->d & String)) {
1233 /* All REP prefixes have the same first termination condition */
1234 if (c->regs[VCPU_REGS_RCX] == 0) {
ad312c7c 1235 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1236 goto done;
1237 }
1238 /* The second termination condition only applies for REPE
1239 * and REPNE. Test if the repeat string operation prefix is
1240 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1241 * corresponding termination condition according to:
1242 * - if REPE/REPZ and ZF = 0 then done
1243 * - if REPNE/REPNZ and ZF = 1 then done
1244 */
1245 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1246 (c->b == 0xae) || (c->b == 0xaf)) {
1247 if ((c->rep_prefix == REPE_PREFIX) &&
1248 ((ctxt->eflags & EFLG_ZF) == 0)) {
ad312c7c 1249 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1250 goto done;
1251 }
1252 if ((c->rep_prefix == REPNE_PREFIX) &&
1253 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
ad312c7c 1254 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1255 goto done;
1256 }
1257 }
1258 c->regs[VCPU_REGS_RCX]--;
ad312c7c 1259 c->eip = ctxt->vcpu->arch.rip;
b9fa9d6b
AK		 1260 }
1261
8b4caf66 1262 if (c->src.type == OP_MEM) {
e8d8d7fe 1263 c->src.ptr = (unsigned long *)memop;
8b4caf66 1264 c->src.val = 0;
d77c26fc
MD		 1265 rc = ops->read_emulated((unsigned long)c->src.ptr,
1266 &c->src.val,
1267 c->src.bytes,
1268 ctxt->vcpu);
1269 if (rc != 0)
8b4caf66
LV		 1270 goto done;
1271 c->src.orig_val = c->src.val;
1272 }
1273
1274 if ((c->d & DstMask) == ImplicitOps)
1275 goto special_insn;
1276
1277
1278 if (c->dst.type == OP_MEM) {
e8d8d7fe 1279 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1280 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1281 c->dst.val = 0;
e4e03ded
LV		 1282 if (c->d & BitOp) {
1283 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1284
e4e03ded
LV		 1285 c->dst.ptr = (void *)c->dst.ptr +
1286 (c->src.val & mask) / 8;
038e51de 1287 }
e4e03ded
LV		 1288 if (!(c->d & Mov) &&
1289 /* optimisation - avoid slow emulated read */
1290 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1291 &c->dst.val,
1292 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1293 goto done;
038e51de 1294 }
e4e03ded 1295 c->dst.orig_val = c->dst.val;
038e51de 1296
018a98db
AK		 1297special_insn:
1298
e4e03ded 1299 if (c->twobyte)
6aa8b732
AK		 1300 goto twobyte_insn;
1301
e4e03ded 1302 switch (c->b) {
6aa8b732
AK		 1303 case 0x00 ... 0x05:
1304 add: /* add */
05f086f8 1305 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1306 break;
1307 case 0x08 ... 0x0d:
1308 or: /* or */
05f086f8 1309 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1310 break;
1311 case 0x10 ... 0x15:
1312 adc: /* adc */
05f086f8 1313 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1314 break;
1315 case 0x18 ... 0x1d:
1316 sbb: /* sbb */
05f086f8 1317 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1318 break;
19eb938e 1319 case 0x20 ... 0x23:
6aa8b732 1320 and: /* and */
05f086f8 1321 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1322 break;
19eb938e 1323 case 0x24: /* and al imm8 */
e4e03ded
LV		 1324 c->dst.type = OP_REG;
1325 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1326 c->dst.val = *(u8 *)c->dst.ptr;
1327 c->dst.bytes = 1;
1328 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1329 goto and;
1330 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1331 c->dst.type = OP_REG;
1332 c->dst.bytes = c->op_bytes;
1333 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1334 if (c->op_bytes == 2)
1335 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1336 else
e4e03ded
LV		 1337 c->dst.val = *(u32 *)c->dst.ptr;
1338 c->dst.orig_val = c->dst.val;
19eb938e 1339 goto and;
6aa8b732
AK		 1340 case 0x28 ... 0x2d:
1341 sub: /* sub */
05f086f8 1342 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1343 break;
1344 case 0x30 ... 0x35:
1345 xor: /* xor */
05f086f8 1346 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1347 break;
1348 case 0x38 ... 0x3d:
1349 cmp: /* cmp */
05f086f8 1350 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1351 break;
33615aa9
AK		 1352 case 0x40 ... 0x47: /* inc r16/r32 */
1353 emulate_1op("inc", c->dst, ctxt->eflags);
1354 break;
1355 case 0x48 ... 0x4f: /* dec r16/r32 */
1356 emulate_1op("dec", c->dst, ctxt->eflags);
1357 break;
1358 case 0x50 ... 0x57: /* push reg */
1359 c->dst.type = OP_MEM;
1360 c->dst.bytes = c->op_bytes;
1361 c->dst.val = c->src.val;
1362 register_address_increment(c->regs[VCPU_REGS_RSP],
1363 -c->op_bytes);
1364 c->dst.ptr = (void *) register_address(
1365 ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
1366 break;
1367 case 0x58 ... 0x5f: /* pop reg */
1368 pop_instruction:
1369 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1370 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1371 c->op_bytes, ctxt->vcpu)) != 0)
1372 goto done;
1373
1374 register_address_increment(c->regs[VCPU_REGS_RSP],
1375 c->op_bytes);
1376 c->dst.type = OP_NONE; /* Disable writeback. */
1377 break;
6aa8b732 1378 case 0x63: /* movsxd */
8b4caf66 1379 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1380 goto cannot_emulate;
e4e03ded 1381 c->dst.val = (s32) c->src.val;
6aa8b732 1382 break;
018a98db
AK		 1383 case 0x6a: /* push imm8 */
1384 c->src.val = 0L;
1385 c->src.val = insn_fetch(s8, 1, c->eip);
1386 emulate_push(ctxt);
1387 break;
1388 case 0x6c: /* insb */
1389 case 0x6d: /* insw/insd */
1390 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1391 1,
1392 (c->d & ByteOp) ? 1 : c->op_bytes,
1393 c->rep_prefix ?
1394 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1395 (ctxt->eflags & EFLG_DF),
1396 register_address(ctxt->es_base,
1397 c->regs[VCPU_REGS_RDI]),
1398 c->rep_prefix,
1399 c->regs[VCPU_REGS_RDX]) == 0) {
1400 c->eip = saved_eip;
1401 return -1;
1402 }
1403 return 0;
1404 case 0x6e: /* outsb */
1405 case 0x6f: /* outsw/outsd */
1406 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1407 0,
1408 (c->d & ByteOp) ? 1 : c->op_bytes,
1409 c->rep_prefix ?
1410 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1411 (ctxt->eflags & EFLG_DF),
1412 register_address(c->override_base ?
1413 *c->override_base :
1414 ctxt->ds_base,
1415 c->regs[VCPU_REGS_RSI]),
1416 c->rep_prefix,
1417 c->regs[VCPU_REGS_RDX]) == 0) {
1418 c->eip = saved_eip;
1419 return -1;
1420 }
1421 return 0;
1422 case 0x70 ... 0x7f: /* jcc (short) */ {
1423 int rel = insn_fetch(s8, 1, c->eip);
1424
1425 if (test_cc(c->b, ctxt->eflags))
1426 JMP_REL(rel);
1427 break;
1428 }
6aa8b732 1429 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1430 switch (c->modrm_reg) {
6aa8b732
AK		 1431 case 0:
1432 goto add;
1433 case 1:
1434 goto or;
1435 case 2:
1436 goto adc;
1437 case 3:
1438 goto sbb;
1439 case 4:
1440 goto and;
1441 case 5:
1442 goto sub;
1443 case 6:
1444 goto xor;
1445 case 7:
1446 goto cmp;
1447 }
1448 break;
1449 case 0x84 ... 0x85:
05f086f8 1450 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1451 break;
1452 case 0x86 ... 0x87: /* xchg */
1453 /* Write back the register source. */
e4e03ded 1454 switch (c->dst.bytes) {
6aa8b732 1455 case 1:
e4e03ded 1456 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1457 break;
1458 case 2:
e4e03ded 1459 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1460 break;
1461 case 4:
e4e03ded 1462 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1463 break; /* 64b reg: zero-extend */
1464 case 8:
e4e03ded 1465 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1466 break;
1467 }
1468 /*
1469 * Write back the memory destination with implicit LOCK
1470 * prefix.
1471 */
e4e03ded
LV		 1472 c->dst.val = c->src.val;
1473 c->lock_prefix = 1;
6aa8b732 1474 break;
6aa8b732 1475 case 0x88 ... 0x8b: /* mov */
7de75248 1476 goto mov;
7e0b54b1 1477 case 0x8d: /* lea r16/r32, m */
e4e03ded 1478 c->dst.val = c->modrm_val;
7e0b54b1 1479 break;
6aa8b732 1480 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1481 rc = emulate_grp1a(ctxt, ops);
1482 if (rc != 0)
6aa8b732 1483 goto done;
6aa8b732 1484 break;
fd2a7608 1485 case 0x9c: /* pushf */
05f086f8 1486 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1487 emulate_push(ctxt);
1488 break;
535eabcf 1489 case 0x9d: /* popf */
05f086f8 1490 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1491 goto pop_instruction;
018a98db
AK		 1492 case 0xa0 ... 0xa1: /* mov */
1493 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1494 c->dst.val = c->src.val;
1495 break;
1496 case 0xa2 ... 0xa3: /* mov */
1497 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1498 break;
6aa8b732 1499 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1500 c->dst.type = OP_MEM;
1501 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1502 c->dst.ptr = (unsigned long *)register_address(
1503 ctxt->es_base,
1504 c->regs[VCPU_REGS_RDI]);
6aa8b732 1505 if ((rc = ops->read_emulated(register_address(
e4e03ded
LV		 1506 c->override_base ? *c->override_base :
1507 ctxt->ds_base,
1508 c->regs[VCPU_REGS_RSI]),
1509 &c->dst.val,
1510 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1511 goto done;
e4e03ded 1512 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1513 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded
LV		 1514 : c->dst.bytes);
1515 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1516 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1517 : c->dst.bytes);
6aa8b732
AK		 1518 break;
1519 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1520 c->src.type = OP_NONE; /* Disable writeback. */
1521 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1522 c->src.ptr = (unsigned long *)register_address(
1523 c->override_base ? *c->override_base :
1524 ctxt->ds_base,
1525 c->regs[VCPU_REGS_RSI]);
1526 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1527 &c->src.val,
1528 c->src.bytes,
1529 ctxt->vcpu)) != 0)
1530 goto done;
1531
1532 c->dst.type = OP_NONE; /* Disable writeback. */
1533 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1534 c->dst.ptr = (unsigned long *)register_address(
1535 ctxt->es_base,
1536 c->regs[VCPU_REGS_RDI]);
1537 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1538 &c->dst.val,
1539 c->dst.bytes,
1540 ctxt->vcpu)) != 0)
1541 goto done;
1542
1543 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1544
1545 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1546
1547 register_address_increment(c->regs[VCPU_REGS_RSI],
1548 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1549 : c->src.bytes);
1550 register_address_increment(c->regs[VCPU_REGS_RDI],
1551 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1552 : c->dst.bytes);
1553
1554 break;
6aa8b732 1555 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1556 c->dst.type = OP_MEM;
1557 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
a7e6c88a
SY		 1558 c->dst.ptr = (unsigned long *)register_address(
1559 ctxt->es_base,
1560 c->regs[VCPU_REGS_RDI]);
e4e03ded
LV		 1561 c->dst.val = c->regs[VCPU_REGS_RAX];
1562 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1563 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1564 : c->dst.bytes);
6aa8b732
AK		 1565 break;
1566 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1567 c->dst.type = OP_REG;
1568 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1569 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
a7e6c88a
SY		 1570 if ((rc = ops->read_emulated(register_address(
1571 c->override_base ? *c->override_base :
1572 ctxt->ds_base,
1573 c->regs[VCPU_REGS_RSI]),
1574 &c->dst.val,
1575 c->dst.bytes,
1576 ctxt->vcpu)) != 0)
6aa8b732 1577 goto done;
e4e03ded 1578 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1579 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1580 : c->dst.bytes);
6aa8b732
AK		 1581 break;
1582 case 0xae ... 0xaf: /* scas */
1583 DPRINTF("Urk! I don't handle SCAS.\n");
1584 goto cannot_emulate;
018a98db
AK		 1585 case 0xc0 ... 0xc1:
1586 emulate_grp2(ctxt);
1587 break;
111de5d6
AK		 1588 case 0xc3: /* ret */
1589 c->dst.ptr = &c->eip;
1590 goto pop_instruction;
018a98db
AK		 1591 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1592 mov:
1593 c->dst.val = c->src.val;
1594 break;
1595 case 0xd0 ... 0xd1: /* Grp2 */
1596 c->src.val = 1;
1597 emulate_grp2(ctxt);
1598 break;
1599 case 0xd2 ... 0xd3: /* Grp2 */
1600 c->src.val = c->regs[VCPU_REGS_RCX];
1601 emulate_grp2(ctxt);
1602 break;
1a52e051
NK		 1603 case 0xe8: /* call (near) */ {
1604 long int rel;
e4e03ded 1605 switch (c->op_bytes) {
1a52e051 1606 case 2:
e4e03ded 1607 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1608 break;
1609 case 4:
e4e03ded 1610 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1611 break;
1a52e051
NK		 1612 default:
1613 DPRINTF("Call: Invalid op_bytes\n");
1614 goto cannot_emulate;
1615 }
e4e03ded 1616 c->src.val = (unsigned long) c->eip;
1a52e051 1617 JMP_REL(rel);
e4e03ded 1618 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1619 emulate_push(ctxt);
1620 break;
1a52e051
NK		 1621 }
1622 case 0xe9: /* jmp rel */
1623 case 0xeb: /* jmp rel short */
e4e03ded 1624 JMP_REL(c->src.val);
a01af5ec 1625 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1626 break;
111de5d6 1627 case 0xf4: /* hlt */
ad312c7c 1628 ctxt->vcpu->arch.halt_request = 1;
111de5d6
AK		 1629 goto done;
1630 case 0xf5: /* cmc */
1631 /* complement carry flag from eflags reg */
1632 ctxt->eflags ^= EFLG_CF;
1633 c->dst.type = OP_NONE; /* Disable writeback. */
1634 break;
018a98db
AK		 1635 case 0xf6 ... 0xf7: /* Grp3 */
1636 rc = emulate_grp3(ctxt, ops);
1637 if (rc != 0)
1638 goto done;
1639 break;
111de5d6
AK		 1640 case 0xf8: /* clc */
1641 ctxt->eflags &= ~EFLG_CF;
1642 c->dst.type = OP_NONE; /* Disable writeback. */
1643 break;
1644 case 0xfa: /* cli */
1645 ctxt->eflags &= ~X86_EFLAGS_IF;
1646 c->dst.type = OP_NONE; /* Disable writeback. */
1647 break;
1648 case 0xfb: /* sti */
1649 ctxt->eflags |= X86_EFLAGS_IF;
1650 c->dst.type = OP_NONE; /* Disable writeback. */
1651 break;
018a98db
AK		 1652 case 0xfe ... 0xff: /* Grp4/Grp5 */
1653 rc = emulate_grp45(ctxt, ops);
1654 if (rc != 0)
1655 goto done;
1656 break;
6aa8b732 1657 }
018a98db
AK		 1658
1659writeback:
1660 rc = writeback(ctxt, ops);
1661 if (rc != 0)
1662 goto done;
1663
1664 /* Commit shadow register state. */
ad312c7c
ZX		 1665 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1666 ctxt->vcpu->arch.rip = c->eip;
018a98db
AK		 1667
1668done:
1669 if (rc == X86EMUL_UNHANDLEABLE) {
1670 c->eip = saved_eip;
1671 return -1;
1672 }
1673 return 0;
6aa8b732
AK		 1674
1675twobyte_insn:
e4e03ded 1676 switch (c->b) {
6aa8b732 1677 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1678 switch (c->modrm_reg) {
6aa8b732
AK		 1679 u16 size;
1680 unsigned long address;
1681
aca7f966 1682 case 0: /* vmcall */
e4e03ded 1683 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1684 goto cannot_emulate;
1685
7aa81cc0
AL		 1686 rc = kvm_fix_hypercall(ctxt->vcpu);
1687 if (rc)
1688 goto done;
1689
1690 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1691 break;
6aa8b732 1692 case 2: /* lgdt */
e4e03ded
LV		 1693 rc = read_descriptor(ctxt, ops, c->src.ptr,
1694 &size, &address, c->op_bytes);
6aa8b732
AK		 1695 if (rc)
1696 goto done;
1697 realmode_lgdt(ctxt->vcpu, size, address);
1698 break;
aca7f966 1699 case 3: /* lidt/vmmcall */
e4e03ded 1700 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1701 rc = kvm_fix_hypercall(ctxt->vcpu);
1702 if (rc)
1703 goto done;
1704 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1705 } else {
e4e03ded 1706 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1707 &size, &address,
e4e03ded 1708 c->op_bytes);
aca7f966
AL		 1709 if (rc)
1710 goto done;
1711 realmode_lidt(ctxt->vcpu, size, address);
1712 }
6aa8b732
AK		 1713 break;
1714 case 4: /* smsw */
e4e03ded 1715 if (c->modrm_mod != 3)
6aa8b732 1716 goto cannot_emulate;
e4e03ded 1717 *(u16 *)&c->regs[c->modrm_rm]
6aa8b732
AK		 1718 = realmode_get_cr(ctxt->vcpu, 0);
1719 break;
1720 case 6: /* lmsw */
e4e03ded 1721 if (c->modrm_mod != 3)
6aa8b732 1722 goto cannot_emulate;
05f086f8
LV		 1723 realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1724 &ctxt->eflags);
6aa8b732
AK		 1725 break;
1726 case 7: /* invlpg*/
e8d8d7fe 1727 emulate_invlpg(ctxt->vcpu, memop);
6aa8b732
AK		 1728 break;
1729 default:
1730 goto cannot_emulate;
1731 }
a01af5ec
LV		 1732 /* Disable writeback. */
1733 c->dst.type = OP_NONE;
6aa8b732 1734 break;
018a98db
AK		 1735 case 0x06:
1736 emulate_clts(ctxt->vcpu);
1737 c->dst.type = OP_NONE;
1738 break;
1739 case 0x08: /* invd */
1740 case 0x09: /* wbinvd */
1741 case 0x0d: /* GrpP (prefetch) */
1742 case 0x18: /* Grp16 (prefetch/nop) */
1743 c->dst.type = OP_NONE;
1744 break;
1745 case 0x20: /* mov cr, reg */
1746 if (c->modrm_mod != 3)
1747 goto cannot_emulate;
1748 c->regs[c->modrm_rm] =
1749 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1750 c->dst.type = OP_NONE; /* no writeback */
1751 break;
6aa8b732 1752 case 0x21: /* mov from dr to reg */
e4e03ded 1753 if (c->modrm_mod != 3)
6aa8b732 1754 goto cannot_emulate;
8cdbd2c9 1755 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1756 if (rc)
1757 goto cannot_emulate;
1758 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1759 break;
018a98db
AK		 1760 case 0x22: /* mov reg, cr */
1761 if (c->modrm_mod != 3)
1762 goto cannot_emulate;
1763 realmode_set_cr(ctxt->vcpu,
1764 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1765 c->dst.type = OP_NONE;
1766 break;
6aa8b732 1767 case 0x23: /* mov from reg to dr */
e4e03ded 1768 if (c->modrm_mod != 3)
6aa8b732 1769 goto cannot_emulate;
e4e03ded
LV		 1770 rc = emulator_set_dr(ctxt, c->modrm_reg,
1771 c->regs[c->modrm_rm]);
a01af5ec
LV		 1772 if (rc)
1773 goto cannot_emulate;
1774 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1775 break;
018a98db
AK		 1776 case 0x30:
1777 /* wrmsr */
1778 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1779 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1780 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1781 if (rc) {
c1a5d4f9 1782 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1783 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1784 }
1785 rc = X86EMUL_CONTINUE;
1786 c->dst.type = OP_NONE;
1787 break;
1788 case 0x32:
1789 /* rdmsr */
1790 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1791 if (rc) {
c1a5d4f9 1792 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1793 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1794 } else {
1795 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1796 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1797 }
1798 rc = X86EMUL_CONTINUE;
1799 c->dst.type = OP_NONE;
1800 break;
6aa8b732 1801 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1802 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1803 if (!test_cc(c->b, ctxt->eflags))
1804 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1805 break;
018a98db
AK		 1806 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1807 long int rel;
1808
1809 switch (c->op_bytes) {
1810 case 2:
1811 rel = insn_fetch(s16, 2, c->eip);
1812 break;
1813 case 4:
1814 rel = insn_fetch(s32, 4, c->eip);
1815 break;
1816 case 8:
1817 rel = insn_fetch(s64, 8, c->eip);
1818 break;
1819 default:
1820 DPRINTF("jnz: Invalid op_bytes\n");
1821 goto cannot_emulate;
1822 }
1823 if (test_cc(c->b, ctxt->eflags))
1824 JMP_REL(rel);
1825 c->dst.type = OP_NONE;
1826 break;
1827 }
7de75248
NK		 1828 case 0xa3:
1829 bt: /* bt */
e4f8e039 1830 c->dst.type = OP_NONE;
e4e03ded
LV		 1831 /* only subword offset */
1832 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1833 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1834 break;
1835 case 0xab:
1836 bts: /* bts */
e4e03ded
LV		 1837 /* only subword offset */
1838 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1839 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1840 break;
6aa8b732
AK		 1841 case 0xb0 ... 0xb1: /* cmpxchg */
1842 /*
1843 * Save real source value, then compare EAX against
1844 * destination.
1845 */
e4e03ded
LV		 1846 c->src.orig_val = c->src.val;
1847 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1848 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1849 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1850 /* Success: write back to memory. */
e4e03ded 1851 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1852 } else {
1853 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1854 c->dst.type = OP_REG;
1855 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1856 }
1857 break;
6aa8b732
AK		 1858 case 0xb3:
1859 btr: /* btr */
e4e03ded
LV		 1860 /* only subword offset */
1861 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1862 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1863 break;
6aa8b732 1864 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1865 c->dst.bytes = c->op_bytes;
1866 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1867 : (u16) c->src.val;
6aa8b732 1868 break;
6aa8b732 1869 case 0xba: /* Grp8 */
e4e03ded 1870 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1871 case 0:
1872 goto bt;
1873 case 1:
1874 goto bts;
1875 case 2:
1876 goto btr;
1877 case 3:
1878 goto btc;
1879 }
1880 break;
7de75248
NK		 1881 case 0xbb:
1882 btc: /* btc */
e4e03ded
LV		 1883 /* only subword offset */
1884 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1885 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 1886 break;
6aa8b732 1887 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 1888 c->dst.bytes = c->op_bytes;
1889 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1890 (s16) c->src.val;
6aa8b732 1891 break;
a012e65a 1892 case 0xc3: /* movnti */
e4e03ded
LV		 1893 c->dst.bytes = c->op_bytes;
1894 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1895 (u64) c->src.val;
a012e65a 1896 break;
6aa8b732 1897 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 1898 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 1899 if (rc != 0)
1900 goto done;
018a98db 1901 c->dst.type = OP_NONE;
8cdbd2c9 1902 break;
6aa8b732
AK		 1903 }
1904 goto writeback;
1905
1906cannot_emulate:
e4e03ded 1907 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 1908 c->eip = saved_eip;
6aa8b732
AK		 1909 return -1;
1910}
Linux 6.x block layer and io_uring tree(s)