Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
313a3dc7 | 30 | |
18068523 | 31 | #include <linux/clocksource.h> |
4d5c5d0f | 32 | #include <linux/interrupt.h> |
313a3dc7 CO |
33 | #include <linux/kvm.h> |
34 | #include <linux/fs.h> | |
35 | #include <linux/vmalloc.h> | |
5fb76f9b | 36 | #include <linux/module.h> |
0de10343 | 37 | #include <linux/mman.h> |
2bacc55c | 38 | #include <linux/highmem.h> |
19de40a8 | 39 | #include <linux/iommu.h> |
62c476c7 | 40 | #include <linux/intel-iommu.h> |
c8076604 | 41 | #include <linux/cpufreq.h> |
18863bdd | 42 | #include <linux/user-return-notifier.h> |
a983fb23 | 43 | #include <linux/srcu.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
ff9d07a0 | 45 | #include <linux/perf_event.h> |
7bee342a | 46 | #include <linux/uaccess.h> |
af585b92 | 47 | #include <linux/hash.h> |
a1b60c1c | 48 | #include <linux/pci.h> |
aec51dc4 | 49 | #include <trace/events/kvm.h> |
2ed152af | 50 | |
229456fc MT |
51 | #define CREATE_TRACE_POINTS |
52 | #include "trace.h" | |
043405e1 | 53 | |
24f1e32c | 54 | #include <asm/debugreg.h> |
d825ed0a | 55 | #include <asm/msr.h> |
a5f61300 | 56 | #include <asm/desc.h> |
0bed3b56 | 57 | #include <asm/mtrr.h> |
890ca9ae | 58 | #include <asm/mce.h> |
7cf30855 | 59 | #include <asm/i387.h> |
1361b83a | 60 | #include <asm/fpu-internal.h> /* Ugh! */ |
98918833 | 61 | #include <asm/xcr.h> |
1d5f066e | 62 | #include <asm/pvclock.h> |
217fc9cf | 63 | #include <asm/div64.h> |
043405e1 | 64 | |
313a3dc7 | 65 | #define MAX_IO_MSRS 256 |
890ca9ae | 66 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 67 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 68 | |
0f65dd70 AK |
69 | #define emul_to_vcpu(ctxt) \ |
70 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
71 | ||
50a37eb4 JR |
72 | /* EFER defaults: |
73 | * - enable syscall per default because its emulated by KVM | |
74 | * - enable LME and LMA per default on 64 bit KVM | |
75 | */ | |
76 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
77 | static |
78 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 79 | #else |
1260edbe | 80 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 81 | #endif |
313a3dc7 | 82 | |
ba1389b7 AK |
83 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
84 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 85 | |
cb142eb7 | 86 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 87 | static void process_nmi(struct kvm_vcpu *vcpu); |
674eea0f | 88 | |
97896d04 | 89 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 90 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 91 | |
476bc001 RR |
92 | static bool ignore_msrs = 0; |
93 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
ed85c068 | 94 | |
92a1f12d JR |
95 | bool kvm_has_tsc_control; |
96 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); | |
97 | u32 kvm_max_guest_tsc_khz; | |
98 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); | |
99 | ||
cc578287 ZA |
100 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
101 | static u32 tsc_tolerance_ppm = 250; | |
102 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); | |
103 | ||
18863bdd AK |
104 | #define KVM_NR_SHARED_MSRS 16 |
105 | ||
106 | struct kvm_shared_msrs_global { | |
107 | int nr; | |
2bf78fa7 | 108 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
109 | }; |
110 | ||
111 | struct kvm_shared_msrs { | |
112 | struct user_return_notifier urn; | |
113 | bool registered; | |
2bf78fa7 SY |
114 | struct kvm_shared_msr_values { |
115 | u64 host; | |
116 | u64 curr; | |
117 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
118 | }; |
119 | ||
120 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
121 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
122 | ||
417bc304 | 123 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
124 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
125 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
126 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
127 | { "invlpg", VCPU_STAT(invlpg) }, | |
128 | { "exits", VCPU_STAT(exits) }, | |
129 | { "io_exits", VCPU_STAT(io_exits) }, | |
130 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
131 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
132 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 133 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
134 | { "halt_exits", VCPU_STAT(halt_exits) }, |
135 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 136 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
137 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
138 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
139 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
140 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
141 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
142 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
143 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 144 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 145 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
146 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
147 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
148 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
149 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
150 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
151 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 152 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 153 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 154 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 155 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
156 | { NULL } |
157 | }; | |
158 | ||
2acf923e DC |
159 | u64 __read_mostly host_xcr0; |
160 | ||
d6aa1000 AK |
161 | int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
162 | ||
af585b92 GN |
163 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
164 | { | |
165 | int i; | |
166 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
167 | vcpu->arch.apf.gfns[i] = ~0; | |
168 | } | |
169 | ||
18863bdd AK |
170 | static void kvm_on_user_return(struct user_return_notifier *urn) |
171 | { | |
172 | unsigned slot; | |
18863bdd AK |
173 | struct kvm_shared_msrs *locals |
174 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 175 | struct kvm_shared_msr_values *values; |
18863bdd AK |
176 | |
177 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
178 | values = &locals->values[slot]; |
179 | if (values->host != values->curr) { | |
180 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
181 | values->curr = values->host; | |
18863bdd AK |
182 | } |
183 | } | |
184 | locals->registered = false; | |
185 | user_return_notifier_unregister(urn); | |
186 | } | |
187 | ||
2bf78fa7 | 188 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 189 | { |
2bf78fa7 | 190 | struct kvm_shared_msrs *smsr; |
18863bdd AK |
191 | u64 value; |
192 | ||
2bf78fa7 SY |
193 | smsr = &__get_cpu_var(shared_msrs); |
194 | /* only read, and nobody should modify it at this time, | |
195 | * so don't need lock */ | |
196 | if (slot >= shared_msrs_global.nr) { | |
197 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
198 | return; | |
199 | } | |
200 | rdmsrl_safe(msr, &value); | |
201 | smsr->values[slot].host = value; | |
202 | smsr->values[slot].curr = value; | |
203 | } | |
204 | ||
205 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
206 | { | |
18863bdd AK |
207 | if (slot >= shared_msrs_global.nr) |
208 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
209 | shared_msrs_global.msrs[slot] = msr; |
210 | /* we need ensured the shared_msr_global have been updated */ | |
211 | smp_wmb(); | |
18863bdd AK |
212 | } |
213 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
214 | ||
215 | static void kvm_shared_msr_cpu_online(void) | |
216 | { | |
217 | unsigned i; | |
18863bdd AK |
218 | |
219 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 220 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
221 | } |
222 | ||
d5696725 | 223 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd AK |
224 | { |
225 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
226 | ||
2bf78fa7 | 227 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 228 | return; |
2bf78fa7 SY |
229 | smsr->values[slot].curr = value; |
230 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
231 | if (!smsr->registered) { |
232 | smsr->urn.on_user_return = kvm_on_user_return; | |
233 | user_return_notifier_register(&smsr->urn); | |
234 | smsr->registered = true; | |
235 | } | |
236 | } | |
237 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
238 | ||
3548bab5 AK |
239 | static void drop_user_return_notifiers(void *ignore) |
240 | { | |
241 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
242 | ||
243 | if (smsr->registered) | |
244 | kvm_on_user_return(&smsr->urn); | |
245 | } | |
246 | ||
6866b83e CO |
247 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
248 | { | |
249 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 250 | return vcpu->arch.apic_base; |
6866b83e | 251 | else |
ad312c7c | 252 | return vcpu->arch.apic_base; |
6866b83e CO |
253 | } |
254 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
255 | ||
256 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
257 | { | |
258 | /* TODO: reserve bits check */ | |
259 | if (irqchip_in_kernel(vcpu->kvm)) | |
260 | kvm_lapic_set_base(vcpu, data); | |
261 | else | |
ad312c7c | 262 | vcpu->arch.apic_base = data; |
6866b83e CO |
263 | } |
264 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
265 | ||
3fd28fce ED |
266 | #define EXCPT_BENIGN 0 |
267 | #define EXCPT_CONTRIBUTORY 1 | |
268 | #define EXCPT_PF 2 | |
269 | ||
270 | static int exception_class(int vector) | |
271 | { | |
272 | switch (vector) { | |
273 | case PF_VECTOR: | |
274 | return EXCPT_PF; | |
275 | case DE_VECTOR: | |
276 | case TS_VECTOR: | |
277 | case NP_VECTOR: | |
278 | case SS_VECTOR: | |
279 | case GP_VECTOR: | |
280 | return EXCPT_CONTRIBUTORY; | |
281 | default: | |
282 | break; | |
283 | } | |
284 | return EXCPT_BENIGN; | |
285 | } | |
286 | ||
287 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
ce7ddec4 JR |
288 | unsigned nr, bool has_error, u32 error_code, |
289 | bool reinject) | |
3fd28fce ED |
290 | { |
291 | u32 prev_nr; | |
292 | int class1, class2; | |
293 | ||
3842d135 AK |
294 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
295 | ||
3fd28fce ED |
296 | if (!vcpu->arch.exception.pending) { |
297 | queue: | |
298 | vcpu->arch.exception.pending = true; | |
299 | vcpu->arch.exception.has_error_code = has_error; | |
300 | vcpu->arch.exception.nr = nr; | |
301 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 302 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
303 | return; |
304 | } | |
305 | ||
306 | /* to check exception */ | |
307 | prev_nr = vcpu->arch.exception.nr; | |
308 | if (prev_nr == DF_VECTOR) { | |
309 | /* triple fault -> shutdown */ | |
a8eeb04a | 310 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
311 | return; |
312 | } | |
313 | class1 = exception_class(prev_nr); | |
314 | class2 = exception_class(nr); | |
315 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
316 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
317 | /* generate double fault per SDM Table 5-5 */ | |
318 | vcpu->arch.exception.pending = true; | |
319 | vcpu->arch.exception.has_error_code = true; | |
320 | vcpu->arch.exception.nr = DF_VECTOR; | |
321 | vcpu->arch.exception.error_code = 0; | |
322 | } else | |
323 | /* replace previous exception with a new one in a hope | |
324 | that instruction re-execution will regenerate lost | |
325 | exception */ | |
326 | goto queue; | |
327 | } | |
328 | ||
298101da AK |
329 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
330 | { | |
ce7ddec4 | 331 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
332 | } |
333 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
334 | ||
ce7ddec4 JR |
335 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
336 | { | |
337 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
338 | } | |
339 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
340 | ||
db8fcefa | 341 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 342 | { |
db8fcefa AP |
343 | if (err) |
344 | kvm_inject_gp(vcpu, 0); | |
345 | else | |
346 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
347 | } | |
348 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 349 | |
6389ee94 | 350 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
351 | { |
352 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
353 | vcpu->arch.cr2 = fault->address; |
354 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 355 | } |
27d6c865 | 356 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 357 | |
6389ee94 | 358 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 359 | { |
6389ee94 AK |
360 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
361 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 362 | else |
6389ee94 | 363 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
d4f8cf66 JR |
364 | } |
365 | ||
3419ffc8 SY |
366 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
367 | { | |
7460fb4a AK |
368 | atomic_inc(&vcpu->arch.nmi_queued); |
369 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
370 | } |
371 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
372 | ||
298101da AK |
373 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
374 | { | |
ce7ddec4 | 375 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
376 | } |
377 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
378 | ||
ce7ddec4 JR |
379 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
380 | { | |
381 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
382 | } | |
383 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
384 | ||
0a79b009 AK |
385 | /* |
386 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
387 | * a #GP and return false. | |
388 | */ | |
389 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 390 | { |
0a79b009 AK |
391 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
392 | return true; | |
393 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
394 | return false; | |
298101da | 395 | } |
0a79b009 | 396 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 397 | |
ec92fe44 JR |
398 | /* |
399 | * This function will be used to read from the physical memory of the currently | |
400 | * running guest. The difference to kvm_read_guest_page is that this function | |
401 | * can read from guest physical or from the guest's guest physical memory. | |
402 | */ | |
403 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
404 | gfn_t ngfn, void *data, int offset, int len, | |
405 | u32 access) | |
406 | { | |
407 | gfn_t real_gfn; | |
408 | gpa_t ngpa; | |
409 | ||
410 | ngpa = gfn_to_gpa(ngfn); | |
411 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access); | |
412 | if (real_gfn == UNMAPPED_GVA) | |
413 | return -EFAULT; | |
414 | ||
415 | real_gfn = gpa_to_gfn(real_gfn); | |
416 | ||
417 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
418 | } | |
419 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
420 | ||
3d06b8bf JR |
421 | int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
422 | void *data, int offset, int len, u32 access) | |
423 | { | |
424 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
425 | data, offset, len, access); | |
426 | } | |
427 | ||
a03490ed CO |
428 | /* |
429 | * Load the pae pdptrs. Return true is they are all valid. | |
430 | */ | |
ff03a073 | 431 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
432 | { |
433 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
434 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
435 | int i; | |
436 | int ret; | |
ff03a073 | 437 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 438 | |
ff03a073 JR |
439 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
440 | offset * sizeof(u64), sizeof(pdpte), | |
441 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
442 | if (ret < 0) { |
443 | ret = 0; | |
444 | goto out; | |
445 | } | |
446 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 447 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 448 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
449 | ret = 0; |
450 | goto out; | |
451 | } | |
452 | } | |
453 | ret = 1; | |
454 | ||
ff03a073 | 455 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
456 | __set_bit(VCPU_EXREG_PDPTR, |
457 | (unsigned long *)&vcpu->arch.regs_avail); | |
458 | __set_bit(VCPU_EXREG_PDPTR, | |
459 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 460 | out: |
a03490ed CO |
461 | |
462 | return ret; | |
463 | } | |
cc4b6871 | 464 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 465 | |
d835dfec AK |
466 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
467 | { | |
ff03a073 | 468 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 469 | bool changed = true; |
3d06b8bf JR |
470 | int offset; |
471 | gfn_t gfn; | |
d835dfec AK |
472 | int r; |
473 | ||
474 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
475 | return false; | |
476 | ||
6de4f3ad AK |
477 | if (!test_bit(VCPU_EXREG_PDPTR, |
478 | (unsigned long *)&vcpu->arch.regs_avail)) | |
479 | return true; | |
480 | ||
9f8fe504 AK |
481 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
482 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
483 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
484 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
485 | if (r < 0) |
486 | goto out; | |
ff03a073 | 487 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 488 | out: |
d835dfec AK |
489 | |
490 | return changed; | |
491 | } | |
492 | ||
49a9b07e | 493 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 494 | { |
aad82703 SY |
495 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
496 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
497 | X86_CR0_CD | X86_CR0_NW; | |
498 | ||
f9a48e6a AK |
499 | cr0 |= X86_CR0_ET; |
500 | ||
ab344828 | 501 | #ifdef CONFIG_X86_64 |
0f12244f GN |
502 | if (cr0 & 0xffffffff00000000UL) |
503 | return 1; | |
ab344828 GN |
504 | #endif |
505 | ||
506 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 507 | |
0f12244f GN |
508 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
509 | return 1; | |
a03490ed | 510 | |
0f12244f GN |
511 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
512 | return 1; | |
a03490ed CO |
513 | |
514 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
515 | #ifdef CONFIG_X86_64 | |
f6801dff | 516 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
517 | int cs_db, cs_l; |
518 | ||
0f12244f GN |
519 | if (!is_pae(vcpu)) |
520 | return 1; | |
a03490ed | 521 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
522 | if (cs_l) |
523 | return 1; | |
a03490ed CO |
524 | } else |
525 | #endif | |
ff03a073 | 526 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 527 | kvm_read_cr3(vcpu))) |
0f12244f | 528 | return 1; |
a03490ed CO |
529 | } |
530 | ||
531 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
a03490ed | 532 | |
d170c419 | 533 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 534 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
535 | kvm_async_pf_hash_reset(vcpu); |
536 | } | |
e5f3f027 | 537 | |
aad82703 SY |
538 | if ((cr0 ^ old_cr0) & update_bits) |
539 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
540 | return 0; |
541 | } | |
2d3ad1f4 | 542 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 543 | |
2d3ad1f4 | 544 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 545 | { |
49a9b07e | 546 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 547 | } |
2d3ad1f4 | 548 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 549 | |
2acf923e DC |
550 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
551 | { | |
552 | u64 xcr0; | |
553 | ||
554 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
555 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
556 | return 1; | |
557 | xcr0 = xcr; | |
558 | if (kvm_x86_ops->get_cpl(vcpu) != 0) | |
559 | return 1; | |
560 | if (!(xcr0 & XSTATE_FP)) | |
561 | return 1; | |
562 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
563 | return 1; | |
564 | if (xcr0 & ~host_xcr0) | |
565 | return 1; | |
566 | vcpu->arch.xcr0 = xcr0; | |
567 | vcpu->guest_xcr0_loaded = 0; | |
568 | return 0; | |
569 | } | |
570 | ||
571 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
572 | { | |
573 | if (__kvm_set_xcr(vcpu, index, xcr)) { | |
574 | kvm_inject_gp(vcpu, 0); | |
575 | return 1; | |
576 | } | |
577 | return 0; | |
578 | } | |
579 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
580 | ||
a83b29c6 | 581 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 582 | { |
fc78f519 | 583 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
c68b734f YW |
584 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | |
585 | X86_CR4_PAE | X86_CR4_SMEP; | |
0f12244f GN |
586 | if (cr4 & CR4_RESERVED_BITS) |
587 | return 1; | |
a03490ed | 588 | |
2acf923e DC |
589 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
590 | return 1; | |
591 | ||
c68b734f YW |
592 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
593 | return 1; | |
594 | ||
74dc2b4f YW |
595 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS)) |
596 | return 1; | |
597 | ||
a03490ed | 598 | if (is_long_mode(vcpu)) { |
0f12244f GN |
599 | if (!(cr4 & X86_CR4_PAE)) |
600 | return 1; | |
a2edf57f AK |
601 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
602 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
603 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
604 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
605 | return 1; |
606 | ||
5e1746d6 | 607 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 608 | return 1; |
a03490ed | 609 | |
aad82703 SY |
610 | if ((cr4 ^ old_cr4) & pdptr_bits) |
611 | kvm_mmu_reset_context(vcpu); | |
0f12244f | 612 | |
2acf923e | 613 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
00b27a3e | 614 | kvm_update_cpuid(vcpu); |
2acf923e | 615 | |
0f12244f GN |
616 | return 0; |
617 | } | |
2d3ad1f4 | 618 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 619 | |
2390218b | 620 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 621 | { |
9f8fe504 | 622 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 623 | kvm_mmu_sync_roots(vcpu); |
d835dfec | 624 | kvm_mmu_flush_tlb(vcpu); |
0f12244f | 625 | return 0; |
d835dfec AK |
626 | } |
627 | ||
a03490ed | 628 | if (is_long_mode(vcpu)) { |
0f12244f GN |
629 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
630 | return 1; | |
a03490ed CO |
631 | } else { |
632 | if (is_pae(vcpu)) { | |
0f12244f GN |
633 | if (cr3 & CR3_PAE_RESERVED_BITS) |
634 | return 1; | |
ff03a073 JR |
635 | if (is_paging(vcpu) && |
636 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
0f12244f | 637 | return 1; |
a03490ed CO |
638 | } |
639 | /* | |
640 | * We don't check reserved bits in nonpae mode, because | |
641 | * this isn't enforced, and VMware depends on this. | |
642 | */ | |
643 | } | |
644 | ||
a03490ed CO |
645 | /* |
646 | * Does the new cr3 value map to physical memory? (Note, we | |
647 | * catch an invalid cr3 even in real-mode, because it would | |
648 | * cause trouble later on when we turn on paging anyway.) | |
649 | * | |
650 | * A real CPU would silently accept an invalid cr3 and would | |
651 | * attempt to use it - with largely undefined (and often hard | |
652 | * to debug) behavior on the guest side. | |
653 | */ | |
654 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
0f12244f GN |
655 | return 1; |
656 | vcpu->arch.cr3 = cr3; | |
aff48baa | 657 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
0f12244f GN |
658 | vcpu->arch.mmu.new_cr3(vcpu); |
659 | return 0; | |
660 | } | |
2d3ad1f4 | 661 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 662 | |
eea1cff9 | 663 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 664 | { |
0f12244f GN |
665 | if (cr8 & CR8_RESERVED_BITS) |
666 | return 1; | |
a03490ed CO |
667 | if (irqchip_in_kernel(vcpu->kvm)) |
668 | kvm_lapic_set_tpr(vcpu, cr8); | |
669 | else | |
ad312c7c | 670 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
671 | return 0; |
672 | } | |
2d3ad1f4 | 673 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 674 | |
2d3ad1f4 | 675 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
676 | { |
677 | if (irqchip_in_kernel(vcpu->kvm)) | |
678 | return kvm_lapic_get_cr8(vcpu); | |
679 | else | |
ad312c7c | 680 | return vcpu->arch.cr8; |
a03490ed | 681 | } |
2d3ad1f4 | 682 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 683 | |
338dbc97 | 684 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
685 | { |
686 | switch (dr) { | |
687 | case 0 ... 3: | |
688 | vcpu->arch.db[dr] = val; | |
689 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
690 | vcpu->arch.eff_db[dr] = val; | |
691 | break; | |
692 | case 4: | |
338dbc97 GN |
693 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
694 | return 1; /* #UD */ | |
020df079 GN |
695 | /* fall through */ |
696 | case 6: | |
338dbc97 GN |
697 | if (val & 0xffffffff00000000ULL) |
698 | return -1; /* #GP */ | |
020df079 GN |
699 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; |
700 | break; | |
701 | case 5: | |
338dbc97 GN |
702 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
703 | return 1; /* #UD */ | |
020df079 GN |
704 | /* fall through */ |
705 | default: /* 7 */ | |
338dbc97 GN |
706 | if (val & 0xffffffff00000000ULL) |
707 | return -1; /* #GP */ | |
020df079 GN |
708 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
709 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
710 | kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7); | |
711 | vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK); | |
712 | } | |
713 | break; | |
714 | } | |
715 | ||
716 | return 0; | |
717 | } | |
338dbc97 GN |
718 | |
719 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
720 | { | |
721 | int res; | |
722 | ||
723 | res = __kvm_set_dr(vcpu, dr, val); | |
724 | if (res > 0) | |
725 | kvm_queue_exception(vcpu, UD_VECTOR); | |
726 | else if (res < 0) | |
727 | kvm_inject_gp(vcpu, 0); | |
728 | ||
729 | return res; | |
730 | } | |
020df079 GN |
731 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
732 | ||
338dbc97 | 733 | static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
734 | { |
735 | switch (dr) { | |
736 | case 0 ... 3: | |
737 | *val = vcpu->arch.db[dr]; | |
738 | break; | |
739 | case 4: | |
338dbc97 | 740 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 741 | return 1; |
020df079 GN |
742 | /* fall through */ |
743 | case 6: | |
744 | *val = vcpu->arch.dr6; | |
745 | break; | |
746 | case 5: | |
338dbc97 | 747 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 748 | return 1; |
020df079 GN |
749 | /* fall through */ |
750 | default: /* 7 */ | |
751 | *val = vcpu->arch.dr7; | |
752 | break; | |
753 | } | |
754 | ||
755 | return 0; | |
756 | } | |
338dbc97 GN |
757 | |
758 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
759 | { | |
760 | if (_kvm_get_dr(vcpu, dr, val)) { | |
761 | kvm_queue_exception(vcpu, UD_VECTOR); | |
762 | return 1; | |
763 | } | |
764 | return 0; | |
765 | } | |
020df079 GN |
766 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
767 | ||
022cd0e8 AK |
768 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
769 | { | |
770 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
771 | u64 data; | |
772 | int err; | |
773 | ||
774 | err = kvm_pmu_read_pmc(vcpu, ecx, &data); | |
775 | if (err) | |
776 | return err; | |
777 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
778 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
779 | return err; | |
780 | } | |
781 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
782 | ||
043405e1 CO |
783 | /* |
784 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
785 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
786 | * | |
787 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
788 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
789 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 790 | */ |
e3267cbb | 791 | |
c9aaa895 | 792 | #define KVM_SAVE_MSRS_BEGIN 9 |
043405e1 | 793 | static u32 msrs_to_save[] = { |
e3267cbb | 794 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 795 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 796 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
c9aaa895 | 797 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, |
ae7a2a3f | 798 | MSR_KVM_PV_EOI_EN, |
043405e1 | 799 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 800 | MSR_STAR, |
043405e1 CO |
801 | #ifdef CONFIG_X86_64 |
802 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
803 | #endif | |
e90aa41e | 804 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
805 | }; |
806 | ||
807 | static unsigned num_msrs_to_save; | |
808 | ||
809 | static u32 emulated_msrs[] = { | |
a3e06bbe | 810 | MSR_IA32_TSCDEADLINE, |
043405e1 | 811 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
812 | MSR_IA32_MCG_STATUS, |
813 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
814 | }; |
815 | ||
b69e8cae | 816 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 817 | { |
aad82703 SY |
818 | u64 old_efer = vcpu->arch.efer; |
819 | ||
b69e8cae RJ |
820 | if (efer & efer_reserved_bits) |
821 | return 1; | |
15c4a640 CO |
822 | |
823 | if (is_paging(vcpu) | |
b69e8cae RJ |
824 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) |
825 | return 1; | |
15c4a640 | 826 | |
1b2fd70c AG |
827 | if (efer & EFER_FFXSR) { |
828 | struct kvm_cpuid_entry2 *feat; | |
829 | ||
830 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
831 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
832 | return 1; | |
1b2fd70c AG |
833 | } |
834 | ||
d8017474 AG |
835 | if (efer & EFER_SVME) { |
836 | struct kvm_cpuid_entry2 *feat; | |
837 | ||
838 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
839 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
840 | return 1; | |
d8017474 AG |
841 | } |
842 | ||
15c4a640 | 843 | efer &= ~EFER_LMA; |
f6801dff | 844 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 845 | |
a3d204e2 SY |
846 | kvm_x86_ops->set_efer(vcpu, efer); |
847 | ||
9645bb56 | 848 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; |
b69e8cae | 849 | |
aad82703 SY |
850 | /* Update reserved bits */ |
851 | if ((efer ^ old_efer) & EFER_NX) | |
852 | kvm_mmu_reset_context(vcpu); | |
853 | ||
b69e8cae | 854 | return 0; |
15c4a640 CO |
855 | } |
856 | ||
f2b4b7dd JR |
857 | void kvm_enable_efer_bits(u64 mask) |
858 | { | |
859 | efer_reserved_bits &= ~mask; | |
860 | } | |
861 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
862 | ||
863 | ||
15c4a640 CO |
864 | /* |
865 | * Writes msr value into into the appropriate "register". | |
866 | * Returns 0 on success, non-0 otherwise. | |
867 | * Assumes vcpu_load() was already called. | |
868 | */ | |
869 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
870 | { | |
871 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
872 | } | |
873 | ||
313a3dc7 CO |
874 | /* |
875 | * Adapt set_msr() to msr_io()'s calling convention | |
876 | */ | |
877 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
878 | { | |
879 | return kvm_set_msr(vcpu, index, *data); | |
880 | } | |
881 | ||
18068523 GOC |
882 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
883 | { | |
9ed3c444 AK |
884 | int version; |
885 | int r; | |
50d0a0f9 | 886 | struct pvclock_wall_clock wc; |
923de3cf | 887 | struct timespec boot; |
18068523 GOC |
888 | |
889 | if (!wall_clock) | |
890 | return; | |
891 | ||
9ed3c444 AK |
892 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
893 | if (r) | |
894 | return; | |
895 | ||
896 | if (version & 1) | |
897 | ++version; /* first time write, random junk */ | |
898 | ||
899 | ++version; | |
18068523 | 900 | |
18068523 GOC |
901 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
902 | ||
50d0a0f9 GH |
903 | /* |
904 | * The guest calculates current wall clock time by adding | |
34c238a1 | 905 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
906 | * wall clock specified here. guest system time equals host |
907 | * system time for us, thus we must fill in host boot time here. | |
908 | */ | |
923de3cf | 909 | getboottime(&boot); |
50d0a0f9 GH |
910 | |
911 | wc.sec = boot.tv_sec; | |
912 | wc.nsec = boot.tv_nsec; | |
913 | wc.version = version; | |
18068523 GOC |
914 | |
915 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
916 | ||
917 | version++; | |
918 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
919 | } |
920 | ||
50d0a0f9 GH |
921 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
922 | { | |
923 | uint32_t quotient, remainder; | |
924 | ||
925 | /* Don't try to replace with do_div(), this one calculates | |
926 | * "(dividend << 32) / divisor" */ | |
927 | __asm__ ( "divl %4" | |
928 | : "=a" (quotient), "=d" (remainder) | |
929 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
930 | return quotient; | |
931 | } | |
932 | ||
5f4e3f88 ZA |
933 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
934 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 935 | { |
5f4e3f88 | 936 | uint64_t scaled64; |
50d0a0f9 GH |
937 | int32_t shift = 0; |
938 | uint64_t tps64; | |
939 | uint32_t tps32; | |
940 | ||
5f4e3f88 ZA |
941 | tps64 = base_khz * 1000LL; |
942 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 943 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
944 | tps64 >>= 1; |
945 | shift--; | |
946 | } | |
947 | ||
948 | tps32 = (uint32_t)tps64; | |
50933623 JK |
949 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
950 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
951 | scaled64 >>= 1; |
952 | else | |
953 | tps32 <<= 1; | |
50d0a0f9 GH |
954 | shift++; |
955 | } | |
956 | ||
5f4e3f88 ZA |
957 | *pshift = shift; |
958 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 959 | |
5f4e3f88 ZA |
960 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
961 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
962 | } |
963 | ||
759379dd ZA |
964 | static inline u64 get_kernel_ns(void) |
965 | { | |
966 | struct timespec ts; | |
967 | ||
968 | WARN_ON(preemptible()); | |
969 | ktime_get_ts(&ts); | |
970 | monotonic_to_bootbased(&ts); | |
971 | return timespec_to_ns(&ts); | |
50d0a0f9 GH |
972 | } |
973 | ||
c8076604 | 974 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
c285545f | 975 | unsigned long max_tsc_khz; |
c8076604 | 976 | |
cc578287 | 977 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 978 | { |
cc578287 ZA |
979 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
980 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
981 | } |
982 | ||
cc578287 | 983 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 984 | { |
cc578287 ZA |
985 | u64 v = (u64)khz * (1000000 + ppm); |
986 | do_div(v, 1000000); | |
987 | return v; | |
1e993611 JR |
988 | } |
989 | ||
cc578287 | 990 | static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) |
759379dd | 991 | { |
cc578287 ZA |
992 | u32 thresh_lo, thresh_hi; |
993 | int use_scaling = 0; | |
217fc9cf | 994 | |
c285545f ZA |
995 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
996 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
cc578287 ZA |
997 | &vcpu->arch.virtual_tsc_shift, |
998 | &vcpu->arch.virtual_tsc_mult); | |
999 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1000 | ||
1001 | /* | |
1002 | * Compute the variation in TSC rate which is acceptable | |
1003 | * within the range of tolerance and decide if the | |
1004 | * rate being applied is within that bounds of the hardware | |
1005 | * rate. If so, no scaling or compensation need be done. | |
1006 | */ | |
1007 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1008 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1009 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1010 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1011 | use_scaling = 1; | |
1012 | } | |
1013 | kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); | |
c285545f ZA |
1014 | } |
1015 | ||
1016 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1017 | { | |
e26101b1 | 1018 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1019 | vcpu->arch.virtual_tsc_mult, |
1020 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1021 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1022 | return tsc; |
1023 | } | |
1024 | ||
99e3e30a ZA |
1025 | void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data) |
1026 | { | |
1027 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1028 | u64 offset, ns, elapsed; |
99e3e30a | 1029 | unsigned long flags; |
02626b6a | 1030 | s64 usdiff; |
99e3e30a | 1031 | |
038f8c11 | 1032 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
857e4099 | 1033 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); |
759379dd | 1034 | ns = get_kernel_ns(); |
f38e098f | 1035 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 ZA |
1036 | |
1037 | /* n.b - signed multiplication and division required */ | |
02626b6a | 1038 | usdiff = data - kvm->arch.last_tsc_write; |
5d3cb0f6 | 1039 | #ifdef CONFIG_X86_64 |
02626b6a | 1040 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 ZA |
1041 | #else |
1042 | /* do_div() only does unsigned */ | |
1043 | asm("idivl %2; xor %%edx, %%edx" | |
02626b6a MT |
1044 | : "=A"(usdiff) |
1045 | : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz)); | |
5d3cb0f6 | 1046 | #endif |
02626b6a MT |
1047 | do_div(elapsed, 1000); |
1048 | usdiff -= elapsed; | |
1049 | if (usdiff < 0) | |
1050 | usdiff = -usdiff; | |
f38e098f ZA |
1051 | |
1052 | /* | |
5d3cb0f6 ZA |
1053 | * Special case: TSC write with a small delta (1 second) of virtual |
1054 | * cycle time against real time is interpreted as an attempt to | |
1055 | * synchronize the CPU. | |
1056 | * | |
1057 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1058 | * TSC, we add elapsed time in this computation. We could let the | |
1059 | * compensation code attempt to catch up if we fall behind, but | |
1060 | * it's better to try to match offsets from the beginning. | |
1061 | */ | |
02626b6a | 1062 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1063 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1064 | if (!check_tsc_unstable()) { |
e26101b1 | 1065 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1066 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1067 | } else { | |
857e4099 | 1068 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 ZA |
1069 | data += delta; |
1070 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
759379dd | 1071 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1072 | } |
e26101b1 ZA |
1073 | } else { |
1074 | /* | |
1075 | * We split periods of matched TSC writes into generations. | |
1076 | * For each generation, we track the original measured | |
1077 | * nanosecond time, offset, and write, so if TSCs are in | |
1078 | * sync, we can match exact offset, and if not, we can match | |
1079 | * exact software computaion in compute_guest_tsc() | |
1080 | * | |
1081 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1082 | */ | |
1083 | kvm->arch.cur_tsc_generation++; | |
1084 | kvm->arch.cur_tsc_nsec = ns; | |
1085 | kvm->arch.cur_tsc_write = data; | |
1086 | kvm->arch.cur_tsc_offset = offset; | |
1087 | pr_debug("kvm: new tsc generation %u, clock %llu\n", | |
1088 | kvm->arch.cur_tsc_generation, data); | |
f38e098f | 1089 | } |
e26101b1 ZA |
1090 | |
1091 | /* | |
1092 | * We also track th most recent recorded KHZ, write and time to | |
1093 | * allow the matching interval to be extended at each write. | |
1094 | */ | |
f38e098f ZA |
1095 | kvm->arch.last_tsc_nsec = ns; |
1096 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1097 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a ZA |
1098 | |
1099 | /* Reset of TSC must disable overshoot protection below */ | |
1100 | vcpu->arch.hv_clock.tsc_timestamp = 0; | |
b183aa58 | 1101 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1102 | |
1103 | /* Keep track of which generation this VCPU has synchronized to */ | |
1104 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1105 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1106 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1107 | ||
1108 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
1109 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
99e3e30a | 1110 | } |
e26101b1 | 1111 | |
99e3e30a ZA |
1112 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1113 | ||
34c238a1 | 1114 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1115 | { |
18068523 GOC |
1116 | unsigned long flags; |
1117 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
1118 | void *shared_kaddr; | |
463656c0 | 1119 | unsigned long this_tsc_khz; |
1d5f066e ZA |
1120 | s64 kernel_ns, max_kernel_ns; |
1121 | u64 tsc_timestamp; | |
18068523 | 1122 | |
18068523 GOC |
1123 | /* Keep irq disabled to prevent changes to the clock */ |
1124 | local_irq_save(flags); | |
d5c1785d | 1125 | tsc_timestamp = kvm_x86_ops->read_l1_tsc(v); |
759379dd | 1126 | kernel_ns = get_kernel_ns(); |
cc578287 | 1127 | this_tsc_khz = __get_cpu_var(cpu_tsc_khz); |
8cfdc000 | 1128 | if (unlikely(this_tsc_khz == 0)) { |
c285545f | 1129 | local_irq_restore(flags); |
34c238a1 | 1130 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
8cfdc000 ZA |
1131 | return 1; |
1132 | } | |
18068523 | 1133 | |
c285545f ZA |
1134 | /* |
1135 | * We may have to catch up the TSC to match elapsed wall clock | |
1136 | * time for two reasons, even if kvmclock is used. | |
1137 | * 1) CPU could have been running below the maximum TSC rate | |
1138 | * 2) Broken TSC compensation resets the base at each VCPU | |
1139 | * entry to avoid unknown leaps of TSC even when running | |
1140 | * again on the same CPU. This may cause apparent elapsed | |
1141 | * time to disappear, and the guest to stand still or run | |
1142 | * very slowly. | |
1143 | */ | |
1144 | if (vcpu->tsc_catchup) { | |
1145 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1146 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1147 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1148 | tsc_timestamp = tsc; |
1149 | } | |
50d0a0f9 GH |
1150 | } |
1151 | ||
18068523 GOC |
1152 | local_irq_restore(flags); |
1153 | ||
c285545f ZA |
1154 | if (!vcpu->time_page) |
1155 | return 0; | |
18068523 | 1156 | |
1d5f066e ZA |
1157 | /* |
1158 | * Time as measured by the TSC may go backwards when resetting the base | |
1159 | * tsc_timestamp. The reason for this is that the TSC resolution is | |
1160 | * higher than the resolution of the other clock scales. Thus, many | |
1161 | * possible measurments of the TSC correspond to one measurement of any | |
1162 | * other clock, and so a spread of values is possible. This is not a | |
1163 | * problem for the computation of the nanosecond clock; with TSC rates | |
1164 | * around 1GHZ, there can only be a few cycles which correspond to one | |
1165 | * nanosecond value, and any path through this code will inevitably | |
1166 | * take longer than that. However, with the kernel_ns value itself, | |
1167 | * the precision may be much lower, down to HZ granularity. If the | |
1168 | * first sampling of TSC against kernel_ns ends in the low part of the | |
1169 | * range, and the second in the high end of the range, we can get: | |
1170 | * | |
1171 | * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new | |
1172 | * | |
1173 | * As the sampling errors potentially range in the thousands of cycles, | |
1174 | * it is possible such a time value has already been observed by the | |
1175 | * guest. To protect against this, we must compute the system time as | |
1176 | * observed by the guest and ensure the new system time is greater. | |
1177 | */ | |
1178 | max_kernel_ns = 0; | |
b183aa58 | 1179 | if (vcpu->hv_clock.tsc_timestamp) { |
1d5f066e ZA |
1180 | max_kernel_ns = vcpu->last_guest_tsc - |
1181 | vcpu->hv_clock.tsc_timestamp; | |
1182 | max_kernel_ns = pvclock_scale_delta(max_kernel_ns, | |
1183 | vcpu->hv_clock.tsc_to_system_mul, | |
1184 | vcpu->hv_clock.tsc_shift); | |
1185 | max_kernel_ns += vcpu->last_kernel_ns; | |
1186 | } | |
afbcf7ab | 1187 | |
e48672fa | 1188 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1189 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1190 | &vcpu->hv_clock.tsc_shift, | |
1191 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1192 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1193 | } |
1194 | ||
1d5f066e ZA |
1195 | if (max_kernel_ns > kernel_ns) |
1196 | kernel_ns = max_kernel_ns; | |
1197 | ||
8cfdc000 | 1198 | /* With all the info we got, fill in the values */ |
1d5f066e | 1199 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1200 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
1d5f066e | 1201 | vcpu->last_kernel_ns = kernel_ns; |
28e4639a | 1202 | vcpu->last_guest_tsc = tsc_timestamp; |
371bcf64 GC |
1203 | vcpu->hv_clock.flags = 0; |
1204 | ||
18068523 GOC |
1205 | /* |
1206 | * The interface expects us to write an even number signaling that the | |
1207 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 1208 | * state, we just increase by 2 at the end. |
18068523 | 1209 | */ |
50d0a0f9 | 1210 | vcpu->hv_clock.version += 2; |
18068523 | 1211 | |
8fd75e12 | 1212 | shared_kaddr = kmap_atomic(vcpu->time_page); |
18068523 GOC |
1213 | |
1214 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 1215 | sizeof(vcpu->hv_clock)); |
18068523 | 1216 | |
8fd75e12 | 1217 | kunmap_atomic(shared_kaddr); |
18068523 GOC |
1218 | |
1219 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
8cfdc000 | 1220 | return 0; |
c8076604 GH |
1221 | } |
1222 | ||
9ba075a6 AK |
1223 | static bool msr_mtrr_valid(unsigned msr) |
1224 | { | |
1225 | switch (msr) { | |
1226 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1227 | case MSR_MTRRfix64K_00000: | |
1228 | case MSR_MTRRfix16K_80000: | |
1229 | case MSR_MTRRfix16K_A0000: | |
1230 | case MSR_MTRRfix4K_C0000: | |
1231 | case MSR_MTRRfix4K_C8000: | |
1232 | case MSR_MTRRfix4K_D0000: | |
1233 | case MSR_MTRRfix4K_D8000: | |
1234 | case MSR_MTRRfix4K_E0000: | |
1235 | case MSR_MTRRfix4K_E8000: | |
1236 | case MSR_MTRRfix4K_F0000: | |
1237 | case MSR_MTRRfix4K_F8000: | |
1238 | case MSR_MTRRdefType: | |
1239 | case MSR_IA32_CR_PAT: | |
1240 | return true; | |
1241 | case 0x2f8: | |
1242 | return true; | |
1243 | } | |
1244 | return false; | |
1245 | } | |
1246 | ||
d6289b93 MT |
1247 | static bool valid_pat_type(unsigned t) |
1248 | { | |
1249 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1250 | } | |
1251 | ||
1252 | static bool valid_mtrr_type(unsigned t) | |
1253 | { | |
1254 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1255 | } | |
1256 | ||
1257 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1258 | { | |
1259 | int i; | |
1260 | ||
1261 | if (!msr_mtrr_valid(msr)) | |
1262 | return false; | |
1263 | ||
1264 | if (msr == MSR_IA32_CR_PAT) { | |
1265 | for (i = 0; i < 8; i++) | |
1266 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1267 | return false; | |
1268 | return true; | |
1269 | } else if (msr == MSR_MTRRdefType) { | |
1270 | if (data & ~0xcff) | |
1271 | return false; | |
1272 | return valid_mtrr_type(data & 0xff); | |
1273 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1274 | for (i = 0; i < 8 ; i++) | |
1275 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1276 | return false; | |
1277 | return true; | |
1278 | } | |
1279 | ||
1280 | /* variable MTRRs */ | |
1281 | return valid_mtrr_type(data & 0xff); | |
1282 | } | |
1283 | ||
9ba075a6 AK |
1284 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1285 | { | |
0bed3b56 SY |
1286 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1287 | ||
d6289b93 | 1288 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1289 | return 1; |
1290 | ||
0bed3b56 SY |
1291 | if (msr == MSR_MTRRdefType) { |
1292 | vcpu->arch.mtrr_state.def_type = data; | |
1293 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1294 | } else if (msr == MSR_MTRRfix64K_00000) | |
1295 | p[0] = data; | |
1296 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1297 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1298 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1299 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1300 | else if (msr == MSR_IA32_CR_PAT) | |
1301 | vcpu->arch.pat = data; | |
1302 | else { /* Variable MTRRs */ | |
1303 | int idx, is_mtrr_mask; | |
1304 | u64 *pt; | |
1305 | ||
1306 | idx = (msr - 0x200) / 2; | |
1307 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1308 | if (!is_mtrr_mask) | |
1309 | pt = | |
1310 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1311 | else | |
1312 | pt = | |
1313 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1314 | *pt = data; | |
1315 | } | |
1316 | ||
1317 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1318 | return 0; |
1319 | } | |
15c4a640 | 1320 | |
890ca9ae | 1321 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1322 | { |
890ca9ae HY |
1323 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1324 | unsigned bank_num = mcg_cap & 0xff; | |
1325 | ||
15c4a640 | 1326 | switch (msr) { |
15c4a640 | 1327 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1328 | vcpu->arch.mcg_status = data; |
15c4a640 | 1329 | break; |
c7ac679c | 1330 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1331 | if (!(mcg_cap & MCG_CTL_P)) |
1332 | return 1; | |
1333 | if (data != 0 && data != ~(u64)0) | |
1334 | return -1; | |
1335 | vcpu->arch.mcg_ctl = data; | |
1336 | break; | |
1337 | default: | |
1338 | if (msr >= MSR_IA32_MC0_CTL && | |
1339 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1340 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
114be429 AP |
1341 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1342 | * some Linux kernels though clear bit 10 in bank 4 to | |
1343 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1344 | * this to avoid an uncatched #GP in the guest | |
1345 | */ | |
890ca9ae | 1346 | if ((offset & 0x3) == 0 && |
114be429 | 1347 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1348 | return -1; |
1349 | vcpu->arch.mce_banks[offset] = data; | |
1350 | break; | |
1351 | } | |
1352 | return 1; | |
1353 | } | |
1354 | return 0; | |
1355 | } | |
1356 | ||
ffde22ac ES |
1357 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1358 | { | |
1359 | struct kvm *kvm = vcpu->kvm; | |
1360 | int lm = is_long_mode(vcpu); | |
1361 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1362 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1363 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1364 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1365 | u32 page_num = data & ~PAGE_MASK; | |
1366 | u64 page_addr = data & PAGE_MASK; | |
1367 | u8 *page; | |
1368 | int r; | |
1369 | ||
1370 | r = -E2BIG; | |
1371 | if (page_num >= blob_size) | |
1372 | goto out; | |
1373 | r = -ENOMEM; | |
ff5c2c03 SL |
1374 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
1375 | if (IS_ERR(page)) { | |
1376 | r = PTR_ERR(page); | |
ffde22ac | 1377 | goto out; |
ff5c2c03 | 1378 | } |
ffde22ac ES |
1379 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) |
1380 | goto out_free; | |
1381 | r = 0; | |
1382 | out_free: | |
1383 | kfree(page); | |
1384 | out: | |
1385 | return r; | |
1386 | } | |
1387 | ||
55cd8e5a GN |
1388 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1389 | { | |
1390 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1391 | } | |
1392 | ||
1393 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1394 | { | |
1395 | bool r = false; | |
1396 | switch (msr) { | |
1397 | case HV_X64_MSR_GUEST_OS_ID: | |
1398 | case HV_X64_MSR_HYPERCALL: | |
1399 | r = true; | |
1400 | break; | |
1401 | } | |
1402 | ||
1403 | return r; | |
1404 | } | |
1405 | ||
1406 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1407 | { | |
1408 | struct kvm *kvm = vcpu->kvm; | |
1409 | ||
1410 | switch (msr) { | |
1411 | case HV_X64_MSR_GUEST_OS_ID: | |
1412 | kvm->arch.hv_guest_os_id = data; | |
1413 | /* setting guest os id to zero disables hypercall page */ | |
1414 | if (!kvm->arch.hv_guest_os_id) | |
1415 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1416 | break; | |
1417 | case HV_X64_MSR_HYPERCALL: { | |
1418 | u64 gfn; | |
1419 | unsigned long addr; | |
1420 | u8 instructions[4]; | |
1421 | ||
1422 | /* if guest os id is not set hypercall should remain disabled */ | |
1423 | if (!kvm->arch.hv_guest_os_id) | |
1424 | break; | |
1425 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1426 | kvm->arch.hv_hypercall = data; | |
1427 | break; | |
1428 | } | |
1429 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1430 | addr = gfn_to_hva(kvm, gfn); | |
1431 | if (kvm_is_error_hva(addr)) | |
1432 | return 1; | |
1433 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1434 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
8b0cedff | 1435 | if (__copy_to_user((void __user *)addr, instructions, 4)) |
55cd8e5a GN |
1436 | return 1; |
1437 | kvm->arch.hv_hypercall = data; | |
1438 | break; | |
1439 | } | |
1440 | default: | |
a737f256 CD |
1441 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1442 | "data 0x%llx\n", msr, data); | |
55cd8e5a GN |
1443 | return 1; |
1444 | } | |
1445 | return 0; | |
1446 | } | |
1447 | ||
1448 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1449 | { | |
10388a07 GN |
1450 | switch (msr) { |
1451 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1452 | unsigned long addr; | |
55cd8e5a | 1453 | |
10388a07 GN |
1454 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1455 | vcpu->arch.hv_vapic = data; | |
1456 | break; | |
1457 | } | |
1458 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1459 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1460 | if (kvm_is_error_hva(addr)) | |
1461 | return 1; | |
8b0cedff | 1462 | if (__clear_user((void __user *)addr, PAGE_SIZE)) |
10388a07 GN |
1463 | return 1; |
1464 | vcpu->arch.hv_vapic = data; | |
1465 | break; | |
1466 | } | |
1467 | case HV_X64_MSR_EOI: | |
1468 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1469 | case HV_X64_MSR_ICR: | |
1470 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1471 | case HV_X64_MSR_TPR: | |
1472 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1473 | default: | |
a737f256 CD |
1474 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1475 | "data 0x%llx\n", msr, data); | |
10388a07 GN |
1476 | return 1; |
1477 | } | |
1478 | ||
1479 | return 0; | |
55cd8e5a GN |
1480 | } |
1481 | ||
344d9588 GN |
1482 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
1483 | { | |
1484 | gpa_t gpa = data & ~0x3f; | |
1485 | ||
6adba527 GN |
1486 | /* Bits 2:5 are resrved, Should be zero */ |
1487 | if (data & 0x3c) | |
344d9588 GN |
1488 | return 1; |
1489 | ||
1490 | vcpu->arch.apf.msr_val = data; | |
1491 | ||
1492 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
1493 | kvm_clear_async_pf_completion_queue(vcpu); | |
1494 | kvm_async_pf_hash_reset(vcpu); | |
1495 | return 0; | |
1496 | } | |
1497 | ||
1498 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa)) | |
1499 | return 1; | |
1500 | ||
6adba527 | 1501 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
1502 | kvm_async_pf_wakeup_all(vcpu); |
1503 | return 0; | |
1504 | } | |
1505 | ||
12f9a48f GC |
1506 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
1507 | { | |
1508 | if (vcpu->arch.time_page) { | |
1509 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1510 | vcpu->arch.time_page = NULL; | |
1511 | } | |
1512 | } | |
1513 | ||
c9aaa895 GC |
1514 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) |
1515 | { | |
1516 | u64 delta; | |
1517 | ||
1518 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
1519 | return; | |
1520 | ||
1521 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
1522 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
1523 | vcpu->arch.st.accum_steal = delta; | |
1524 | } | |
1525 | ||
1526 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
1527 | { | |
1528 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
1529 | return; | |
1530 | ||
1531 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
1532 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
1533 | return; | |
1534 | ||
1535 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
1536 | vcpu->arch.st.steal.version += 2; | |
1537 | vcpu->arch.st.accum_steal = 0; | |
1538 | ||
1539 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
1540 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
1541 | } | |
1542 | ||
15c4a640 CO |
1543 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1544 | { | |
5753785f GN |
1545 | bool pr = false; |
1546 | ||
15c4a640 | 1547 | switch (msr) { |
15c4a640 | 1548 | case MSR_EFER: |
b69e8cae | 1549 | return set_efer(vcpu, data); |
8f1589d9 AP |
1550 | case MSR_K7_HWCR: |
1551 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 1552 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 1553 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
8f1589d9 | 1554 | if (data != 0) { |
a737f256 CD |
1555 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
1556 | data); | |
8f1589d9 AP |
1557 | return 1; |
1558 | } | |
15c4a640 | 1559 | break; |
f7c6d140 AP |
1560 | case MSR_FAM10H_MMIO_CONF_BASE: |
1561 | if (data != 0) { | |
a737f256 CD |
1562 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
1563 | "0x%llx\n", data); | |
f7c6d140 AP |
1564 | return 1; |
1565 | } | |
15c4a640 | 1566 | break; |
c323c0e5 | 1567 | case MSR_AMD64_NB_CFG: |
c7ac679c | 1568 | break; |
b5e2fec0 AG |
1569 | case MSR_IA32_DEBUGCTLMSR: |
1570 | if (!data) { | |
1571 | /* We support the non-activated case already */ | |
1572 | break; | |
1573 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1574 | /* Values other than LBR and BTF are vendor-specific, | |
1575 | thus reserved and should throw a #GP */ | |
1576 | return 1; | |
1577 | } | |
a737f256 CD |
1578 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
1579 | __func__, data); | |
b5e2fec0 | 1580 | break; |
15c4a640 CO |
1581 | case MSR_IA32_UCODE_REV: |
1582 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 1583 | case MSR_VM_HSAVE_PA: |
6098ca93 | 1584 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 1585 | break; |
9ba075a6 AK |
1586 | case 0x200 ... 0x2ff: |
1587 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1588 | case MSR_IA32_APICBASE: |
1589 | kvm_set_apic_base(vcpu, data); | |
1590 | break; | |
0105d1a5 GN |
1591 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1592 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
1593 | case MSR_IA32_TSCDEADLINE: |
1594 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1595 | break; | |
15c4a640 | 1596 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1597 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1598 | break; |
11c6bffa | 1599 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1600 | case MSR_KVM_WALL_CLOCK: |
1601 | vcpu->kvm->arch.wall_clock = data; | |
1602 | kvm_write_wall_clock(vcpu->kvm, data); | |
1603 | break; | |
11c6bffa | 1604 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 1605 | case MSR_KVM_SYSTEM_TIME: { |
12f9a48f | 1606 | kvmclock_reset(vcpu); |
18068523 GOC |
1607 | |
1608 | vcpu->arch.time = data; | |
c285545f | 1609 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
18068523 GOC |
1610 | |
1611 | /* we verify if the enable bit is set... */ | |
1612 | if (!(data & 1)) | |
1613 | break; | |
1614 | ||
1615 | /* ...but clean it before doing the actual write */ | |
1616 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1617 | ||
18068523 GOC |
1618 | vcpu->arch.time_page = |
1619 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
1620 | |
1621 | if (is_error_page(vcpu->arch.time_page)) { | |
1622 | kvm_release_page_clean(vcpu->arch.time_page); | |
1623 | vcpu->arch.time_page = NULL; | |
1624 | } | |
18068523 GOC |
1625 | break; |
1626 | } | |
344d9588 GN |
1627 | case MSR_KVM_ASYNC_PF_EN: |
1628 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
1629 | return 1; | |
1630 | break; | |
c9aaa895 GC |
1631 | case MSR_KVM_STEAL_TIME: |
1632 | ||
1633 | if (unlikely(!sched_info_on())) | |
1634 | return 1; | |
1635 | ||
1636 | if (data & KVM_STEAL_RESERVED_MASK) | |
1637 | return 1; | |
1638 | ||
1639 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
1640 | data & KVM_STEAL_VALID_BITS)) | |
1641 | return 1; | |
1642 | ||
1643 | vcpu->arch.st.msr_val = data; | |
1644 | ||
1645 | if (!(data & KVM_MSR_ENABLED)) | |
1646 | break; | |
1647 | ||
1648 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
1649 | ||
1650 | preempt_disable(); | |
1651 | accumulate_steal_time(vcpu); | |
1652 | preempt_enable(); | |
1653 | ||
1654 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
1655 | ||
1656 | break; | |
ae7a2a3f MT |
1657 | case MSR_KVM_PV_EOI_EN: |
1658 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
1659 | return 1; | |
1660 | break; | |
c9aaa895 | 1661 | |
890ca9ae HY |
1662 | case MSR_IA32_MCG_CTL: |
1663 | case MSR_IA32_MCG_STATUS: | |
1664 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1665 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1666 | |
1667 | /* Performance counters are not protected by a CPUID bit, | |
1668 | * so we should check all of them in the generic path for the sake of | |
1669 | * cross vendor migration. | |
1670 | * Writing a zero into the event select MSRs disables them, | |
1671 | * which we perfectly emulate ;-). Any other value should be at least | |
1672 | * reported, some guests depend on them. | |
1673 | */ | |
71db6023 AP |
1674 | case MSR_K7_EVNTSEL0: |
1675 | case MSR_K7_EVNTSEL1: | |
1676 | case MSR_K7_EVNTSEL2: | |
1677 | case MSR_K7_EVNTSEL3: | |
1678 | if (data != 0) | |
a737f256 CD |
1679 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
1680 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 AP |
1681 | break; |
1682 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1683 | * so we ignore writes to make it happy. | |
1684 | */ | |
71db6023 AP |
1685 | case MSR_K7_PERFCTR0: |
1686 | case MSR_K7_PERFCTR1: | |
1687 | case MSR_K7_PERFCTR2: | |
1688 | case MSR_K7_PERFCTR3: | |
a737f256 CD |
1689 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
1690 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 | 1691 | break; |
5753785f GN |
1692 | case MSR_P6_PERFCTR0: |
1693 | case MSR_P6_PERFCTR1: | |
1694 | pr = true; | |
1695 | case MSR_P6_EVNTSEL0: | |
1696 | case MSR_P6_EVNTSEL1: | |
1697 | if (kvm_pmu_msr(vcpu, msr)) | |
1698 | return kvm_pmu_set_msr(vcpu, msr, data); | |
1699 | ||
1700 | if (pr || data != 0) | |
a737f256 CD |
1701 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
1702 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 1703 | break; |
84e0cefa JS |
1704 | case MSR_K7_CLK_CTL: |
1705 | /* | |
1706 | * Ignore all writes to this no longer documented MSR. | |
1707 | * Writes are only relevant for old K7 processors, | |
1708 | * all pre-dating SVM, but a recommended workaround from | |
1709 | * AMD for these chips. It is possible to speicify the | |
1710 | * affected processor models on the command line, hence | |
1711 | * the need to ignore the workaround. | |
1712 | */ | |
1713 | break; | |
55cd8e5a GN |
1714 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1715 | if (kvm_hv_msr_partition_wide(msr)) { | |
1716 | int r; | |
1717 | mutex_lock(&vcpu->kvm->lock); | |
1718 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
1719 | mutex_unlock(&vcpu->kvm->lock); | |
1720 | return r; | |
1721 | } else | |
1722 | return set_msr_hyperv(vcpu, msr, data); | |
1723 | break; | |
91c9c3ed | 1724 | case MSR_IA32_BBL_CR_CTL3: |
1725 | /* Drop writes to this legacy MSR -- see rdmsr | |
1726 | * counterpart for further detail. | |
1727 | */ | |
a737f256 | 1728 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 1729 | break; |
2b036c6b BO |
1730 | case MSR_AMD64_OSVW_ID_LENGTH: |
1731 | if (!guest_cpuid_has_osvw(vcpu)) | |
1732 | return 1; | |
1733 | vcpu->arch.osvw.length = data; | |
1734 | break; | |
1735 | case MSR_AMD64_OSVW_STATUS: | |
1736 | if (!guest_cpuid_has_osvw(vcpu)) | |
1737 | return 1; | |
1738 | vcpu->arch.osvw.status = data; | |
1739 | break; | |
15c4a640 | 1740 | default: |
ffde22ac ES |
1741 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1742 | return xen_hvm_config(vcpu, data); | |
f5132b01 GN |
1743 | if (kvm_pmu_msr(vcpu, msr)) |
1744 | return kvm_pmu_set_msr(vcpu, msr, data); | |
ed85c068 | 1745 | if (!ignore_msrs) { |
a737f256 CD |
1746 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
1747 | msr, data); | |
ed85c068 AP |
1748 | return 1; |
1749 | } else { | |
a737f256 CD |
1750 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
1751 | msr, data); | |
ed85c068 AP |
1752 | break; |
1753 | } | |
15c4a640 CO |
1754 | } |
1755 | return 0; | |
1756 | } | |
1757 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1758 | ||
1759 | ||
1760 | /* | |
1761 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1762 | * Returns 0 on success, non-0 otherwise. | |
1763 | * Assumes vcpu_load() was already called. | |
1764 | */ | |
1765 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1766 | { | |
1767 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1768 | } | |
1769 | ||
9ba075a6 AK |
1770 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1771 | { | |
0bed3b56 SY |
1772 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1773 | ||
9ba075a6 AK |
1774 | if (!msr_mtrr_valid(msr)) |
1775 | return 1; | |
1776 | ||
0bed3b56 SY |
1777 | if (msr == MSR_MTRRdefType) |
1778 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1779 | (vcpu->arch.mtrr_state.enabled << 10); | |
1780 | else if (msr == MSR_MTRRfix64K_00000) | |
1781 | *pdata = p[0]; | |
1782 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1783 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1784 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1785 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1786 | else if (msr == MSR_IA32_CR_PAT) | |
1787 | *pdata = vcpu->arch.pat; | |
1788 | else { /* Variable MTRRs */ | |
1789 | int idx, is_mtrr_mask; | |
1790 | u64 *pt; | |
1791 | ||
1792 | idx = (msr - 0x200) / 2; | |
1793 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1794 | if (!is_mtrr_mask) | |
1795 | pt = | |
1796 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1797 | else | |
1798 | pt = | |
1799 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1800 | *pdata = *pt; | |
1801 | } | |
1802 | ||
9ba075a6 AK |
1803 | return 0; |
1804 | } | |
1805 | ||
890ca9ae | 1806 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1807 | { |
1808 | u64 data; | |
890ca9ae HY |
1809 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1810 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1811 | |
1812 | switch (msr) { | |
15c4a640 CO |
1813 | case MSR_IA32_P5_MC_ADDR: |
1814 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1815 | data = 0; |
1816 | break; | |
15c4a640 | 1817 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1818 | data = vcpu->arch.mcg_cap; |
1819 | break; | |
c7ac679c | 1820 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1821 | if (!(mcg_cap & MCG_CTL_P)) |
1822 | return 1; | |
1823 | data = vcpu->arch.mcg_ctl; | |
1824 | break; | |
1825 | case MSR_IA32_MCG_STATUS: | |
1826 | data = vcpu->arch.mcg_status; | |
1827 | break; | |
1828 | default: | |
1829 | if (msr >= MSR_IA32_MC0_CTL && | |
1830 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1831 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1832 | data = vcpu->arch.mce_banks[offset]; | |
1833 | break; | |
1834 | } | |
1835 | return 1; | |
1836 | } | |
1837 | *pdata = data; | |
1838 | return 0; | |
1839 | } | |
1840 | ||
55cd8e5a GN |
1841 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1842 | { | |
1843 | u64 data = 0; | |
1844 | struct kvm *kvm = vcpu->kvm; | |
1845 | ||
1846 | switch (msr) { | |
1847 | case HV_X64_MSR_GUEST_OS_ID: | |
1848 | data = kvm->arch.hv_guest_os_id; | |
1849 | break; | |
1850 | case HV_X64_MSR_HYPERCALL: | |
1851 | data = kvm->arch.hv_hypercall; | |
1852 | break; | |
1853 | default: | |
a737f256 | 1854 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
1855 | return 1; |
1856 | } | |
1857 | ||
1858 | *pdata = data; | |
1859 | return 0; | |
1860 | } | |
1861 | ||
1862 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1863 | { | |
1864 | u64 data = 0; | |
1865 | ||
1866 | switch (msr) { | |
1867 | case HV_X64_MSR_VP_INDEX: { | |
1868 | int r; | |
1869 | struct kvm_vcpu *v; | |
1870 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
1871 | if (v == vcpu) | |
1872 | data = r; | |
1873 | break; | |
1874 | } | |
10388a07 GN |
1875 | case HV_X64_MSR_EOI: |
1876 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
1877 | case HV_X64_MSR_ICR: | |
1878 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
1879 | case HV_X64_MSR_TPR: | |
1880 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
14fa67ee | 1881 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
d1613ad5 MW |
1882 | data = vcpu->arch.hv_vapic; |
1883 | break; | |
55cd8e5a | 1884 | default: |
a737f256 | 1885 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
1886 | return 1; |
1887 | } | |
1888 | *pdata = data; | |
1889 | return 0; | |
1890 | } | |
1891 | ||
890ca9ae HY |
1892 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1893 | { | |
1894 | u64 data; | |
1895 | ||
1896 | switch (msr) { | |
890ca9ae | 1897 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1898 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1899 | case MSR_IA32_DEBUGCTLMSR: |
1900 | case MSR_IA32_LASTBRANCHFROMIP: | |
1901 | case MSR_IA32_LASTBRANCHTOIP: | |
1902 | case MSR_IA32_LASTINTFROMIP: | |
1903 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1904 | case MSR_K8_SYSCFG: |
1905 | case MSR_K7_HWCR: | |
61a6bd67 | 1906 | case MSR_VM_HSAVE_PA: |
9e699624 | 1907 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1908 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1909 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1910 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1911 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1912 | data = 0; |
1913 | break; | |
5753785f GN |
1914 | case MSR_P6_PERFCTR0: |
1915 | case MSR_P6_PERFCTR1: | |
1916 | case MSR_P6_EVNTSEL0: | |
1917 | case MSR_P6_EVNTSEL1: | |
1918 | if (kvm_pmu_msr(vcpu, msr)) | |
1919 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
1920 | data = 0; | |
1921 | break; | |
742bc670 MT |
1922 | case MSR_IA32_UCODE_REV: |
1923 | data = 0x100000000ULL; | |
1924 | break; | |
9ba075a6 AK |
1925 | case MSR_MTRRcap: |
1926 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1927 | break; | |
1928 | case 0x200 ... 0x2ff: | |
1929 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1930 | case 0xcd: /* fsb frequency */ |
1931 | data = 3; | |
1932 | break; | |
7b914098 JS |
1933 | /* |
1934 | * MSR_EBC_FREQUENCY_ID | |
1935 | * Conservative value valid for even the basic CPU models. | |
1936 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
1937 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
1938 | * and 266MHz for model 3, or 4. Set Core Clock | |
1939 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
1940 | * 31:24) even though these are only valid for CPU | |
1941 | * models > 2, however guests may end up dividing or | |
1942 | * multiplying by zero otherwise. | |
1943 | */ | |
1944 | case MSR_EBC_FREQUENCY_ID: | |
1945 | data = 1 << 24; | |
1946 | break; | |
15c4a640 CO |
1947 | case MSR_IA32_APICBASE: |
1948 | data = kvm_get_apic_base(vcpu); | |
1949 | break; | |
0105d1a5 GN |
1950 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1951 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1952 | break; | |
a3e06bbe LJ |
1953 | case MSR_IA32_TSCDEADLINE: |
1954 | data = kvm_get_lapic_tscdeadline_msr(vcpu); | |
1955 | break; | |
15c4a640 | 1956 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1957 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1958 | break; |
847f0ad8 AG |
1959 | case MSR_IA32_PERF_STATUS: |
1960 | /* TSC increment by tick */ | |
1961 | data = 1000ULL; | |
1962 | /* CPU multiplier */ | |
1963 | data |= (((uint64_t)4ULL) << 40); | |
1964 | break; | |
15c4a640 | 1965 | case MSR_EFER: |
f6801dff | 1966 | data = vcpu->arch.efer; |
15c4a640 | 1967 | break; |
18068523 | 1968 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 1969 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1970 | data = vcpu->kvm->arch.wall_clock; |
1971 | break; | |
1972 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 1973 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
1974 | data = vcpu->arch.time; |
1975 | break; | |
344d9588 GN |
1976 | case MSR_KVM_ASYNC_PF_EN: |
1977 | data = vcpu->arch.apf.msr_val; | |
1978 | break; | |
c9aaa895 GC |
1979 | case MSR_KVM_STEAL_TIME: |
1980 | data = vcpu->arch.st.msr_val; | |
1981 | break; | |
890ca9ae HY |
1982 | case MSR_IA32_P5_MC_ADDR: |
1983 | case MSR_IA32_P5_MC_TYPE: | |
1984 | case MSR_IA32_MCG_CAP: | |
1985 | case MSR_IA32_MCG_CTL: | |
1986 | case MSR_IA32_MCG_STATUS: | |
1987 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1988 | return get_msr_mce(vcpu, msr, pdata); | |
84e0cefa JS |
1989 | case MSR_K7_CLK_CTL: |
1990 | /* | |
1991 | * Provide expected ramp-up count for K7. All other | |
1992 | * are set to zero, indicating minimum divisors for | |
1993 | * every field. | |
1994 | * | |
1995 | * This prevents guest kernels on AMD host with CPU | |
1996 | * type 6, model 8 and higher from exploding due to | |
1997 | * the rdmsr failing. | |
1998 | */ | |
1999 | data = 0x20000000; | |
2000 | break; | |
55cd8e5a GN |
2001 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2002 | if (kvm_hv_msr_partition_wide(msr)) { | |
2003 | int r; | |
2004 | mutex_lock(&vcpu->kvm->lock); | |
2005 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
2006 | mutex_unlock(&vcpu->kvm->lock); | |
2007 | return r; | |
2008 | } else | |
2009 | return get_msr_hyperv(vcpu, msr, pdata); | |
2010 | break; | |
91c9c3ed | 2011 | case MSR_IA32_BBL_CR_CTL3: |
2012 | /* This legacy MSR exists but isn't fully documented in current | |
2013 | * silicon. It is however accessed by winxp in very narrow | |
2014 | * scenarios where it sets bit #19, itself documented as | |
2015 | * a "reserved" bit. Best effort attempt to source coherent | |
2016 | * read data here should the balance of the register be | |
2017 | * interpreted by the guest: | |
2018 | * | |
2019 | * L2 cache control register 3: 64GB range, 256KB size, | |
2020 | * enabled, latency 0x1, configured | |
2021 | */ | |
2022 | data = 0xbe702111; | |
2023 | break; | |
2b036c6b BO |
2024 | case MSR_AMD64_OSVW_ID_LENGTH: |
2025 | if (!guest_cpuid_has_osvw(vcpu)) | |
2026 | return 1; | |
2027 | data = vcpu->arch.osvw.length; | |
2028 | break; | |
2029 | case MSR_AMD64_OSVW_STATUS: | |
2030 | if (!guest_cpuid_has_osvw(vcpu)) | |
2031 | return 1; | |
2032 | data = vcpu->arch.osvw.status; | |
2033 | break; | |
15c4a640 | 2034 | default: |
f5132b01 GN |
2035 | if (kvm_pmu_msr(vcpu, msr)) |
2036 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
ed85c068 | 2037 | if (!ignore_msrs) { |
a737f256 | 2038 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2039 | return 1; |
2040 | } else { | |
a737f256 | 2041 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2042 | data = 0; |
2043 | } | |
2044 | break; | |
15c4a640 CO |
2045 | } |
2046 | *pdata = data; | |
2047 | return 0; | |
2048 | } | |
2049 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2050 | ||
313a3dc7 CO |
2051 | /* |
2052 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2053 | * | |
2054 | * @return number of msrs set successfully. | |
2055 | */ | |
2056 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2057 | struct kvm_msr_entry *entries, | |
2058 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2059 | unsigned index, u64 *data)) | |
2060 | { | |
f656ce01 | 2061 | int i, idx; |
313a3dc7 | 2062 | |
f656ce01 | 2063 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2064 | for (i = 0; i < msrs->nmsrs; ++i) |
2065 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2066 | break; | |
f656ce01 | 2067 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2068 | |
313a3dc7 CO |
2069 | return i; |
2070 | } | |
2071 | ||
2072 | /* | |
2073 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2074 | * | |
2075 | * @return number of msrs set successfully. | |
2076 | */ | |
2077 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2078 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2079 | unsigned index, u64 *data), | |
2080 | int writeback) | |
2081 | { | |
2082 | struct kvm_msrs msrs; | |
2083 | struct kvm_msr_entry *entries; | |
2084 | int r, n; | |
2085 | unsigned size; | |
2086 | ||
2087 | r = -EFAULT; | |
2088 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2089 | goto out; | |
2090 | ||
2091 | r = -E2BIG; | |
2092 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2093 | goto out; | |
2094 | ||
313a3dc7 | 2095 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2096 | entries = memdup_user(user_msrs->entries, size); |
2097 | if (IS_ERR(entries)) { | |
2098 | r = PTR_ERR(entries); | |
313a3dc7 | 2099 | goto out; |
ff5c2c03 | 2100 | } |
313a3dc7 CO |
2101 | |
2102 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2103 | if (r < 0) | |
2104 | goto out_free; | |
2105 | ||
2106 | r = -EFAULT; | |
2107 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2108 | goto out_free; | |
2109 | ||
2110 | r = n; | |
2111 | ||
2112 | out_free: | |
7a73c028 | 2113 | kfree(entries); |
313a3dc7 CO |
2114 | out: |
2115 | return r; | |
2116 | } | |
2117 | ||
018d00d2 ZX |
2118 | int kvm_dev_ioctl_check_extension(long ext) |
2119 | { | |
2120 | int r; | |
2121 | ||
2122 | switch (ext) { | |
2123 | case KVM_CAP_IRQCHIP: | |
2124 | case KVM_CAP_HLT: | |
2125 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2126 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2127 | case KVM_CAP_EXT_CPUID: |
c8076604 | 2128 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2129 | case KVM_CAP_PIT: |
a28e4f5a | 2130 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2131 | case KVM_CAP_MP_STATE: |
ed848624 | 2132 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2133 | case KVM_CAP_USER_NMI: |
52d939a0 | 2134 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2135 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 2136 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 2137 | case KVM_CAP_IRQFD: |
d34e6b17 | 2138 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 2139 | case KVM_CAP_PIT2: |
e9f42757 | 2140 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2141 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2142 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2143 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2144 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2145 | case KVM_CAP_HYPERV: |
10388a07 | 2146 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2147 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 2148 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2149 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2150 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2151 | case KVM_CAP_XSAVE: |
344d9588 | 2152 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2153 | case KVM_CAP_GET_TSC_KHZ: |
07700a94 | 2154 | case KVM_CAP_PCI_2_3: |
1c0b28c2 | 2155 | case KVM_CAP_KVMCLOCK_CTRL: |
018d00d2 ZX |
2156 | r = 1; |
2157 | break; | |
542472b5 LV |
2158 | case KVM_CAP_COALESCED_MMIO: |
2159 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2160 | break; | |
774ead3a AK |
2161 | case KVM_CAP_VAPIC: |
2162 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2163 | break; | |
f725230a | 2164 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2165 | r = KVM_SOFT_MAX_VCPUS; |
2166 | break; | |
2167 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2168 | r = KVM_MAX_VCPUS; |
2169 | break; | |
a988b910 AK |
2170 | case KVM_CAP_NR_MEMSLOTS: |
2171 | r = KVM_MEMORY_SLOTS; | |
2172 | break; | |
a68a6a72 MT |
2173 | case KVM_CAP_PV_MMU: /* obsolete */ |
2174 | r = 0; | |
2f333bcb | 2175 | break; |
62c476c7 | 2176 | case KVM_CAP_IOMMU: |
a1b60c1c | 2177 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2178 | break; |
890ca9ae HY |
2179 | case KVM_CAP_MCE: |
2180 | r = KVM_MAX_MCE_BANKS; | |
2181 | break; | |
2d5b5a66 SY |
2182 | case KVM_CAP_XCRS: |
2183 | r = cpu_has_xsave; | |
2184 | break; | |
92a1f12d JR |
2185 | case KVM_CAP_TSC_CONTROL: |
2186 | r = kvm_has_tsc_control; | |
2187 | break; | |
4d25a066 JK |
2188 | case KVM_CAP_TSC_DEADLINE_TIMER: |
2189 | r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER); | |
2190 | break; | |
018d00d2 ZX |
2191 | default: |
2192 | r = 0; | |
2193 | break; | |
2194 | } | |
2195 | return r; | |
2196 | ||
2197 | } | |
2198 | ||
043405e1 CO |
2199 | long kvm_arch_dev_ioctl(struct file *filp, |
2200 | unsigned int ioctl, unsigned long arg) | |
2201 | { | |
2202 | void __user *argp = (void __user *)arg; | |
2203 | long r; | |
2204 | ||
2205 | switch (ioctl) { | |
2206 | case KVM_GET_MSR_INDEX_LIST: { | |
2207 | struct kvm_msr_list __user *user_msr_list = argp; | |
2208 | struct kvm_msr_list msr_list; | |
2209 | unsigned n; | |
2210 | ||
2211 | r = -EFAULT; | |
2212 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2213 | goto out; | |
2214 | n = msr_list.nmsrs; | |
2215 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2216 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2217 | goto out; | |
2218 | r = -E2BIG; | |
e125e7b6 | 2219 | if (n < msr_list.nmsrs) |
043405e1 CO |
2220 | goto out; |
2221 | r = -EFAULT; | |
2222 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2223 | num_msrs_to_save * sizeof(u32))) | |
2224 | goto out; | |
e125e7b6 | 2225 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
2226 | &emulated_msrs, |
2227 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2228 | goto out; | |
2229 | r = 0; | |
2230 | break; | |
2231 | } | |
674eea0f AK |
2232 | case KVM_GET_SUPPORTED_CPUID: { |
2233 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2234 | struct kvm_cpuid2 cpuid; | |
2235 | ||
2236 | r = -EFAULT; | |
2237 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2238 | goto out; | |
2239 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 2240 | cpuid_arg->entries); |
674eea0f AK |
2241 | if (r) |
2242 | goto out; | |
2243 | ||
2244 | r = -EFAULT; | |
2245 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2246 | goto out; | |
2247 | r = 0; | |
2248 | break; | |
2249 | } | |
890ca9ae HY |
2250 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2251 | u64 mce_cap; | |
2252 | ||
2253 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2254 | r = -EFAULT; | |
2255 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2256 | goto out; | |
2257 | r = 0; | |
2258 | break; | |
2259 | } | |
043405e1 CO |
2260 | default: |
2261 | r = -EINVAL; | |
2262 | } | |
2263 | out: | |
2264 | return r; | |
2265 | } | |
2266 | ||
f5f48ee1 SY |
2267 | static void wbinvd_ipi(void *garbage) |
2268 | { | |
2269 | wbinvd(); | |
2270 | } | |
2271 | ||
2272 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2273 | { | |
2274 | return vcpu->kvm->arch.iommu_domain && | |
2275 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY); | |
2276 | } | |
2277 | ||
313a3dc7 CO |
2278 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2279 | { | |
f5f48ee1 SY |
2280 | /* Address WBINVD may be executed by guest */ |
2281 | if (need_emulate_wbinvd(vcpu)) { | |
2282 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2283 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2284 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2285 | smp_call_function_single(vcpu->cpu, | |
2286 | wbinvd_ipi, NULL, 1); | |
2287 | } | |
2288 | ||
313a3dc7 | 2289 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 2290 | |
0dd6a6ed ZA |
2291 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
2292 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2293 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2294 | vcpu->arch.tsc_offset_adjustment = 0; | |
2295 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
2296 | } | |
8f6055cb | 2297 | |
48434c20 | 2298 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 ZA |
2299 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
2300 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
e48672fa ZA |
2301 | if (tsc_delta < 0) |
2302 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2303 | if (check_tsc_unstable()) { |
b183aa58 ZA |
2304 | u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, |
2305 | vcpu->arch.last_guest_tsc); | |
2306 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 2307 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2308 | } |
1aa8ceef | 2309 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c285545f ZA |
2310 | if (vcpu->cpu != cpu) |
2311 | kvm_migrate_timers(vcpu); | |
e48672fa | 2312 | vcpu->cpu = cpu; |
6b7d7e76 | 2313 | } |
c9aaa895 GC |
2314 | |
2315 | accumulate_steal_time(vcpu); | |
2316 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
313a3dc7 CO |
2317 | } |
2318 | ||
2319 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2320 | { | |
02daab21 | 2321 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2322 | kvm_put_guest_fpu(vcpu); |
6f526ec5 | 2323 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2324 | } |
2325 | ||
313a3dc7 CO |
2326 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2327 | struct kvm_lapic_state *s) | |
2328 | { | |
ad312c7c | 2329 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2330 | |
2331 | return 0; | |
2332 | } | |
2333 | ||
2334 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2335 | struct kvm_lapic_state *s) | |
2336 | { | |
ad312c7c | 2337 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 | 2338 | kvm_apic_post_state_restore(vcpu); |
cb142eb7 | 2339 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2340 | |
2341 | return 0; | |
2342 | } | |
2343 | ||
f77bc6a4 ZX |
2344 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2345 | struct kvm_interrupt *irq) | |
2346 | { | |
2347 | if (irq->irq < 0 || irq->irq >= 256) | |
2348 | return -EINVAL; | |
2349 | if (irqchip_in_kernel(vcpu->kvm)) | |
2350 | return -ENXIO; | |
f77bc6a4 | 2351 | |
66fd3f7f | 2352 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 2353 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 2354 | |
f77bc6a4 ZX |
2355 | return 0; |
2356 | } | |
2357 | ||
c4abb7c9 JK |
2358 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2359 | { | |
c4abb7c9 | 2360 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2361 | |
2362 | return 0; | |
2363 | } | |
2364 | ||
b209749f AK |
2365 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2366 | struct kvm_tpr_access_ctl *tac) | |
2367 | { | |
2368 | if (tac->flags) | |
2369 | return -EINVAL; | |
2370 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2371 | return 0; | |
2372 | } | |
2373 | ||
890ca9ae HY |
2374 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2375 | u64 mcg_cap) | |
2376 | { | |
2377 | int r; | |
2378 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2379 | ||
2380 | r = -EINVAL; | |
a9e38c3e | 2381 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2382 | goto out; |
2383 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2384 | goto out; | |
2385 | r = 0; | |
2386 | vcpu->arch.mcg_cap = mcg_cap; | |
2387 | /* Init IA32_MCG_CTL to all 1s */ | |
2388 | if (mcg_cap & MCG_CTL_P) | |
2389 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2390 | /* Init IA32_MCi_CTL to all 1s */ | |
2391 | for (bank = 0; bank < bank_num; bank++) | |
2392 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2393 | out: | |
2394 | return r; | |
2395 | } | |
2396 | ||
2397 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2398 | struct kvm_x86_mce *mce) | |
2399 | { | |
2400 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2401 | unsigned bank_num = mcg_cap & 0xff; | |
2402 | u64 *banks = vcpu->arch.mce_banks; | |
2403 | ||
2404 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2405 | return -EINVAL; | |
2406 | /* | |
2407 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2408 | * reporting is disabled | |
2409 | */ | |
2410 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2411 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2412 | return 0; | |
2413 | banks += 4 * mce->bank; | |
2414 | /* | |
2415 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2416 | * reporting is disabled for the bank | |
2417 | */ | |
2418 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2419 | return 0; | |
2420 | if (mce->status & MCI_STATUS_UC) { | |
2421 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2422 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 2423 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2424 | return 0; |
2425 | } | |
2426 | if (banks[1] & MCI_STATUS_VAL) | |
2427 | mce->status |= MCI_STATUS_OVER; | |
2428 | banks[2] = mce->addr; | |
2429 | banks[3] = mce->misc; | |
2430 | vcpu->arch.mcg_status = mce->mcg_status; | |
2431 | banks[1] = mce->status; | |
2432 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2433 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2434 | || !(banks[1] & MCI_STATUS_UC)) { | |
2435 | if (banks[1] & MCI_STATUS_VAL) | |
2436 | mce->status |= MCI_STATUS_OVER; | |
2437 | banks[2] = mce->addr; | |
2438 | banks[3] = mce->misc; | |
2439 | banks[1] = mce->status; | |
2440 | } else | |
2441 | banks[1] |= MCI_STATUS_OVER; | |
2442 | return 0; | |
2443 | } | |
2444 | ||
3cfc3092 JK |
2445 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2446 | struct kvm_vcpu_events *events) | |
2447 | { | |
7460fb4a | 2448 | process_nmi(vcpu); |
03b82a30 JK |
2449 | events->exception.injected = |
2450 | vcpu->arch.exception.pending && | |
2451 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2452 | events->exception.nr = vcpu->arch.exception.nr; |
2453 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 2454 | events->exception.pad = 0; |
3cfc3092 JK |
2455 | events->exception.error_code = vcpu->arch.exception.error_code; |
2456 | ||
03b82a30 JK |
2457 | events->interrupt.injected = |
2458 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2459 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2460 | events->interrupt.soft = 0; |
48005f64 JK |
2461 | events->interrupt.shadow = |
2462 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2463 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
3cfc3092 JK |
2464 | |
2465 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 2466 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 2467 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 2468 | events->nmi.pad = 0; |
3cfc3092 JK |
2469 | |
2470 | events->sipi_vector = vcpu->arch.sipi_vector; | |
2471 | ||
dab4b911 | 2472 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2473 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2474 | | KVM_VCPUEVENT_VALID_SHADOW); | |
97e69aa6 | 2475 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
2476 | } |
2477 | ||
2478 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2479 | struct kvm_vcpu_events *events) | |
2480 | { | |
dab4b911 | 2481 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2482 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2483 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
2484 | return -EINVAL; |
2485 | ||
7460fb4a | 2486 | process_nmi(vcpu); |
3cfc3092 JK |
2487 | vcpu->arch.exception.pending = events->exception.injected; |
2488 | vcpu->arch.exception.nr = events->exception.nr; | |
2489 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2490 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2491 | ||
2492 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2493 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2494 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
2495 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2496 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2497 | events->interrupt.shadow); | |
3cfc3092 JK |
2498 | |
2499 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2500 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2501 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2502 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2503 | ||
dab4b911 JK |
2504 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR) |
2505 | vcpu->arch.sipi_vector = events->sipi_vector; | |
3cfc3092 | 2506 | |
3842d135 AK |
2507 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2508 | ||
3cfc3092 JK |
2509 | return 0; |
2510 | } | |
2511 | ||
a1efbe77 JK |
2512 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
2513 | struct kvm_debugregs *dbgregs) | |
2514 | { | |
a1efbe77 JK |
2515 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
2516 | dbgregs->dr6 = vcpu->arch.dr6; | |
2517 | dbgregs->dr7 = vcpu->arch.dr7; | |
2518 | dbgregs->flags = 0; | |
97e69aa6 | 2519 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
2520 | } |
2521 | ||
2522 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2523 | struct kvm_debugregs *dbgregs) | |
2524 | { | |
2525 | if (dbgregs->flags) | |
2526 | return -EINVAL; | |
2527 | ||
a1efbe77 JK |
2528 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
2529 | vcpu->arch.dr6 = dbgregs->dr6; | |
2530 | vcpu->arch.dr7 = dbgregs->dr7; | |
2531 | ||
a1efbe77 JK |
2532 | return 0; |
2533 | } | |
2534 | ||
2d5b5a66 SY |
2535 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
2536 | struct kvm_xsave *guest_xsave) | |
2537 | { | |
2538 | if (cpu_has_xsave) | |
2539 | memcpy(guest_xsave->region, | |
2540 | &vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2541 | xstate_size); |
2d5b5a66 SY |
2542 | else { |
2543 | memcpy(guest_xsave->region, | |
2544 | &vcpu->arch.guest_fpu.state->fxsave, | |
2545 | sizeof(struct i387_fxsave_struct)); | |
2546 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
2547 | XSTATE_FPSSE; | |
2548 | } | |
2549 | } | |
2550 | ||
2551 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
2552 | struct kvm_xsave *guest_xsave) | |
2553 | { | |
2554 | u64 xstate_bv = | |
2555 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
2556 | ||
2557 | if (cpu_has_xsave) | |
2558 | memcpy(&vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2559 | guest_xsave->region, xstate_size); |
2d5b5a66 SY |
2560 | else { |
2561 | if (xstate_bv & ~XSTATE_FPSSE) | |
2562 | return -EINVAL; | |
2563 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
2564 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
2565 | } | |
2566 | return 0; | |
2567 | } | |
2568 | ||
2569 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
2570 | struct kvm_xcrs *guest_xcrs) | |
2571 | { | |
2572 | if (!cpu_has_xsave) { | |
2573 | guest_xcrs->nr_xcrs = 0; | |
2574 | return; | |
2575 | } | |
2576 | ||
2577 | guest_xcrs->nr_xcrs = 1; | |
2578 | guest_xcrs->flags = 0; | |
2579 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
2580 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
2581 | } | |
2582 | ||
2583 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
2584 | struct kvm_xcrs *guest_xcrs) | |
2585 | { | |
2586 | int i, r = 0; | |
2587 | ||
2588 | if (!cpu_has_xsave) | |
2589 | return -EINVAL; | |
2590 | ||
2591 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
2592 | return -EINVAL; | |
2593 | ||
2594 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
2595 | /* Only support XCR0 currently */ | |
2596 | if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) { | |
2597 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, | |
2598 | guest_xcrs->xcrs[0].value); | |
2599 | break; | |
2600 | } | |
2601 | if (r) | |
2602 | r = -EINVAL; | |
2603 | return r; | |
2604 | } | |
2605 | ||
1c0b28c2 EM |
2606 | /* |
2607 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
2608 | * stopped by the hypervisor. This function will be called from the host only. | |
2609 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
2610 | * does not support pv clocks. | |
2611 | */ | |
2612 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
2613 | { | |
2614 | struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock; | |
2615 | if (!vcpu->arch.time_page) | |
2616 | return -EINVAL; | |
2617 | src->flags |= PVCLOCK_GUEST_STOPPED; | |
2618 | mark_page_dirty(vcpu->kvm, vcpu->arch.time >> PAGE_SHIFT); | |
2619 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
2620 | return 0; | |
2621 | } | |
2622 | ||
313a3dc7 CO |
2623 | long kvm_arch_vcpu_ioctl(struct file *filp, |
2624 | unsigned int ioctl, unsigned long arg) | |
2625 | { | |
2626 | struct kvm_vcpu *vcpu = filp->private_data; | |
2627 | void __user *argp = (void __user *)arg; | |
2628 | int r; | |
d1ac91d8 AK |
2629 | union { |
2630 | struct kvm_lapic_state *lapic; | |
2631 | struct kvm_xsave *xsave; | |
2632 | struct kvm_xcrs *xcrs; | |
2633 | void *buffer; | |
2634 | } u; | |
2635 | ||
2636 | u.buffer = NULL; | |
313a3dc7 CO |
2637 | switch (ioctl) { |
2638 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
2639 | r = -EINVAL; |
2640 | if (!vcpu->arch.apic) | |
2641 | goto out; | |
d1ac91d8 | 2642 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 2643 | |
b772ff36 | 2644 | r = -ENOMEM; |
d1ac91d8 | 2645 | if (!u.lapic) |
b772ff36 | 2646 | goto out; |
d1ac91d8 | 2647 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2648 | if (r) |
2649 | goto out; | |
2650 | r = -EFAULT; | |
d1ac91d8 | 2651 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
2652 | goto out; |
2653 | r = 0; | |
2654 | break; | |
2655 | } | |
2656 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
2657 | r = -EINVAL; |
2658 | if (!vcpu->arch.apic) | |
2659 | goto out; | |
ff5c2c03 SL |
2660 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
2661 | if (IS_ERR(u.lapic)) { | |
2662 | r = PTR_ERR(u.lapic); | |
313a3dc7 | 2663 | goto out; |
ff5c2c03 SL |
2664 | } |
2665 | ||
d1ac91d8 | 2666 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2667 | if (r) |
2668 | goto out; | |
2669 | r = 0; | |
2670 | break; | |
2671 | } | |
f77bc6a4 ZX |
2672 | case KVM_INTERRUPT: { |
2673 | struct kvm_interrupt irq; | |
2674 | ||
2675 | r = -EFAULT; | |
2676 | if (copy_from_user(&irq, argp, sizeof irq)) | |
2677 | goto out; | |
2678 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
2679 | if (r) | |
2680 | goto out; | |
2681 | r = 0; | |
2682 | break; | |
2683 | } | |
c4abb7c9 JK |
2684 | case KVM_NMI: { |
2685 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2686 | if (r) | |
2687 | goto out; | |
2688 | r = 0; | |
2689 | break; | |
2690 | } | |
313a3dc7 CO |
2691 | case KVM_SET_CPUID: { |
2692 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2693 | struct kvm_cpuid cpuid; | |
2694 | ||
2695 | r = -EFAULT; | |
2696 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2697 | goto out; | |
2698 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2699 | if (r) | |
2700 | goto out; | |
2701 | break; | |
2702 | } | |
07716717 DK |
2703 | case KVM_SET_CPUID2: { |
2704 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2705 | struct kvm_cpuid2 cpuid; | |
2706 | ||
2707 | r = -EFAULT; | |
2708 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2709 | goto out; | |
2710 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2711 | cpuid_arg->entries); |
07716717 DK |
2712 | if (r) |
2713 | goto out; | |
2714 | break; | |
2715 | } | |
2716 | case KVM_GET_CPUID2: { | |
2717 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2718 | struct kvm_cpuid2 cpuid; | |
2719 | ||
2720 | r = -EFAULT; | |
2721 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2722 | goto out; | |
2723 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2724 | cpuid_arg->entries); |
07716717 DK |
2725 | if (r) |
2726 | goto out; | |
2727 | r = -EFAULT; | |
2728 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2729 | goto out; | |
2730 | r = 0; | |
2731 | break; | |
2732 | } | |
313a3dc7 CO |
2733 | case KVM_GET_MSRS: |
2734 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2735 | break; | |
2736 | case KVM_SET_MSRS: | |
2737 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2738 | break; | |
b209749f AK |
2739 | case KVM_TPR_ACCESS_REPORTING: { |
2740 | struct kvm_tpr_access_ctl tac; | |
2741 | ||
2742 | r = -EFAULT; | |
2743 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2744 | goto out; | |
2745 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2746 | if (r) | |
2747 | goto out; | |
2748 | r = -EFAULT; | |
2749 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2750 | goto out; | |
2751 | r = 0; | |
2752 | break; | |
2753 | }; | |
b93463aa AK |
2754 | case KVM_SET_VAPIC_ADDR: { |
2755 | struct kvm_vapic_addr va; | |
2756 | ||
2757 | r = -EINVAL; | |
2758 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2759 | goto out; | |
2760 | r = -EFAULT; | |
2761 | if (copy_from_user(&va, argp, sizeof va)) | |
2762 | goto out; | |
2763 | r = 0; | |
2764 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2765 | break; | |
2766 | } | |
890ca9ae HY |
2767 | case KVM_X86_SETUP_MCE: { |
2768 | u64 mcg_cap; | |
2769 | ||
2770 | r = -EFAULT; | |
2771 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2772 | goto out; | |
2773 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2774 | break; | |
2775 | } | |
2776 | case KVM_X86_SET_MCE: { | |
2777 | struct kvm_x86_mce mce; | |
2778 | ||
2779 | r = -EFAULT; | |
2780 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2781 | goto out; | |
2782 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2783 | break; | |
2784 | } | |
3cfc3092 JK |
2785 | case KVM_GET_VCPU_EVENTS: { |
2786 | struct kvm_vcpu_events events; | |
2787 | ||
2788 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2789 | ||
2790 | r = -EFAULT; | |
2791 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2792 | break; | |
2793 | r = 0; | |
2794 | break; | |
2795 | } | |
2796 | case KVM_SET_VCPU_EVENTS: { | |
2797 | struct kvm_vcpu_events events; | |
2798 | ||
2799 | r = -EFAULT; | |
2800 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2801 | break; | |
2802 | ||
2803 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2804 | break; | |
2805 | } | |
a1efbe77 JK |
2806 | case KVM_GET_DEBUGREGS: { |
2807 | struct kvm_debugregs dbgregs; | |
2808 | ||
2809 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
2810 | ||
2811 | r = -EFAULT; | |
2812 | if (copy_to_user(argp, &dbgregs, | |
2813 | sizeof(struct kvm_debugregs))) | |
2814 | break; | |
2815 | r = 0; | |
2816 | break; | |
2817 | } | |
2818 | case KVM_SET_DEBUGREGS: { | |
2819 | struct kvm_debugregs dbgregs; | |
2820 | ||
2821 | r = -EFAULT; | |
2822 | if (copy_from_user(&dbgregs, argp, | |
2823 | sizeof(struct kvm_debugregs))) | |
2824 | break; | |
2825 | ||
2826 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
2827 | break; | |
2828 | } | |
2d5b5a66 | 2829 | case KVM_GET_XSAVE: { |
d1ac91d8 | 2830 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2831 | r = -ENOMEM; |
d1ac91d8 | 2832 | if (!u.xsave) |
2d5b5a66 SY |
2833 | break; |
2834 | ||
d1ac91d8 | 2835 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2836 | |
2837 | r = -EFAULT; | |
d1ac91d8 | 2838 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
2839 | break; |
2840 | r = 0; | |
2841 | break; | |
2842 | } | |
2843 | case KVM_SET_XSAVE: { | |
ff5c2c03 SL |
2844 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
2845 | if (IS_ERR(u.xsave)) { | |
2846 | r = PTR_ERR(u.xsave); | |
2847 | goto out; | |
2848 | } | |
2d5b5a66 | 2849 | |
d1ac91d8 | 2850 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2851 | break; |
2852 | } | |
2853 | case KVM_GET_XCRS: { | |
d1ac91d8 | 2854 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 2855 | r = -ENOMEM; |
d1ac91d8 | 2856 | if (!u.xcrs) |
2d5b5a66 SY |
2857 | break; |
2858 | ||
d1ac91d8 | 2859 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
2860 | |
2861 | r = -EFAULT; | |
d1ac91d8 | 2862 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
2863 | sizeof(struct kvm_xcrs))) |
2864 | break; | |
2865 | r = 0; | |
2866 | break; | |
2867 | } | |
2868 | case KVM_SET_XCRS: { | |
ff5c2c03 SL |
2869 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
2870 | if (IS_ERR(u.xcrs)) { | |
2871 | r = PTR_ERR(u.xcrs); | |
2872 | goto out; | |
2873 | } | |
2d5b5a66 | 2874 | |
d1ac91d8 | 2875 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
2876 | break; |
2877 | } | |
92a1f12d JR |
2878 | case KVM_SET_TSC_KHZ: { |
2879 | u32 user_tsc_khz; | |
2880 | ||
2881 | r = -EINVAL; | |
92a1f12d JR |
2882 | user_tsc_khz = (u32)arg; |
2883 | ||
2884 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
2885 | goto out; | |
2886 | ||
cc578287 ZA |
2887 | if (user_tsc_khz == 0) |
2888 | user_tsc_khz = tsc_khz; | |
2889 | ||
2890 | kvm_set_tsc_khz(vcpu, user_tsc_khz); | |
92a1f12d JR |
2891 | |
2892 | r = 0; | |
2893 | goto out; | |
2894 | } | |
2895 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 2896 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
2897 | goto out; |
2898 | } | |
1c0b28c2 EM |
2899 | case KVM_KVMCLOCK_CTRL: { |
2900 | r = kvm_set_guest_paused(vcpu); | |
2901 | goto out; | |
2902 | } | |
313a3dc7 CO |
2903 | default: |
2904 | r = -EINVAL; | |
2905 | } | |
2906 | out: | |
d1ac91d8 | 2907 | kfree(u.buffer); |
313a3dc7 CO |
2908 | return r; |
2909 | } | |
2910 | ||
5b1c1493 CO |
2911 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
2912 | { | |
2913 | return VM_FAULT_SIGBUS; | |
2914 | } | |
2915 | ||
1fe779f8 CO |
2916 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
2917 | { | |
2918 | int ret; | |
2919 | ||
2920 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
2921 | return -1; | |
2922 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
2923 | return ret; | |
2924 | } | |
2925 | ||
b927a3ce SY |
2926 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
2927 | u64 ident_addr) | |
2928 | { | |
2929 | kvm->arch.ept_identity_map_addr = ident_addr; | |
2930 | return 0; | |
2931 | } | |
2932 | ||
1fe779f8 CO |
2933 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
2934 | u32 kvm_nr_mmu_pages) | |
2935 | { | |
2936 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
2937 | return -EINVAL; | |
2938 | ||
79fac95e | 2939 | mutex_lock(&kvm->slots_lock); |
7c8a83b7 | 2940 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
2941 | |
2942 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 2943 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 2944 | |
7c8a83b7 | 2945 | spin_unlock(&kvm->mmu_lock); |
79fac95e | 2946 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
2947 | return 0; |
2948 | } | |
2949 | ||
2950 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
2951 | { | |
39de71ec | 2952 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
2953 | } |
2954 | ||
1fe779f8 CO |
2955 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
2956 | { | |
2957 | int r; | |
2958 | ||
2959 | r = 0; | |
2960 | switch (chip->chip_id) { | |
2961 | case KVM_IRQCHIP_PIC_MASTER: | |
2962 | memcpy(&chip->chip.pic, | |
2963 | &pic_irqchip(kvm)->pics[0], | |
2964 | sizeof(struct kvm_pic_state)); | |
2965 | break; | |
2966 | case KVM_IRQCHIP_PIC_SLAVE: | |
2967 | memcpy(&chip->chip.pic, | |
2968 | &pic_irqchip(kvm)->pics[1], | |
2969 | sizeof(struct kvm_pic_state)); | |
2970 | break; | |
2971 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2972 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2973 | break; |
2974 | default: | |
2975 | r = -EINVAL; | |
2976 | break; | |
2977 | } | |
2978 | return r; | |
2979 | } | |
2980 | ||
2981 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
2982 | { | |
2983 | int r; | |
2984 | ||
2985 | r = 0; | |
2986 | switch (chip->chip_id) { | |
2987 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 2988 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2989 | memcpy(&pic_irqchip(kvm)->pics[0], |
2990 | &chip->chip.pic, | |
2991 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 2992 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2993 | break; |
2994 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 2995 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2996 | memcpy(&pic_irqchip(kvm)->pics[1], |
2997 | &chip->chip.pic, | |
2998 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 2999 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3000 | break; |
3001 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3002 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3003 | break; |
3004 | default: | |
3005 | r = -EINVAL; | |
3006 | break; | |
3007 | } | |
3008 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3009 | return r; | |
3010 | } | |
3011 | ||
e0f63cb9 SY |
3012 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3013 | { | |
3014 | int r = 0; | |
3015 | ||
894a9c55 | 3016 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3017 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3018 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3019 | return r; |
3020 | } | |
3021 | ||
3022 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3023 | { | |
3024 | int r = 0; | |
3025 | ||
894a9c55 | 3026 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3027 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3028 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3029 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3030 | return r; | |
3031 | } | |
3032 | ||
3033 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3034 | { | |
3035 | int r = 0; | |
3036 | ||
3037 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3038 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3039 | sizeof(ps->channels)); | |
3040 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3041 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3042 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3043 | return r; |
3044 | } | |
3045 | ||
3046 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3047 | { | |
3048 | int r = 0, start = 0; | |
3049 | u32 prev_legacy, cur_legacy; | |
3050 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3051 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3052 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3053 | if (!prev_legacy && cur_legacy) | |
3054 | start = 1; | |
3055 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3056 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3057 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3058 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3059 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3060 | return r; |
3061 | } | |
3062 | ||
52d939a0 MT |
3063 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3064 | struct kvm_reinject_control *control) | |
3065 | { | |
3066 | if (!kvm->arch.vpit) | |
3067 | return -ENXIO; | |
894a9c55 | 3068 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 | 3069 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; |
894a9c55 | 3070 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3071 | return 0; |
3072 | } | |
3073 | ||
95d4c16c | 3074 | /** |
60c34612 TY |
3075 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3076 | * @kvm: kvm instance | |
3077 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3078 | * |
60c34612 TY |
3079 | * We need to keep it in mind that VCPU threads can write to the bitmap |
3080 | * concurrently. So, to avoid losing data, we keep the following order for | |
3081 | * each bit: | |
95d4c16c | 3082 | * |
60c34612 TY |
3083 | * 1. Take a snapshot of the bit and clear it if needed. |
3084 | * 2. Write protect the corresponding page. | |
3085 | * 3. Flush TLB's if needed. | |
3086 | * 4. Copy the snapshot to the userspace. | |
95d4c16c | 3087 | * |
60c34612 TY |
3088 | * Between 2 and 3, the guest may write to the page using the remaining TLB |
3089 | * entry. This is not a problem because the page will be reported dirty at | |
3090 | * step 4 using the snapshot taken before and step 3 ensures that successive | |
3091 | * writes will be logged for the next call. | |
5bb064dc | 3092 | */ |
60c34612 | 3093 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3094 | { |
7850ac54 | 3095 | int r; |
5bb064dc | 3096 | struct kvm_memory_slot *memslot; |
60c34612 TY |
3097 | unsigned long n, i; |
3098 | unsigned long *dirty_bitmap; | |
3099 | unsigned long *dirty_bitmap_buffer; | |
3100 | bool is_dirty = false; | |
5bb064dc | 3101 | |
79fac95e | 3102 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3103 | |
b050b015 MT |
3104 | r = -EINVAL; |
3105 | if (log->slot >= KVM_MEMORY_SLOTS) | |
3106 | goto out; | |
3107 | ||
28a37544 | 3108 | memslot = id_to_memslot(kvm->memslots, log->slot); |
60c34612 TY |
3109 | |
3110 | dirty_bitmap = memslot->dirty_bitmap; | |
b050b015 | 3111 | r = -ENOENT; |
60c34612 | 3112 | if (!dirty_bitmap) |
b050b015 MT |
3113 | goto out; |
3114 | ||
87bf6e7d | 3115 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 | 3116 | |
60c34612 TY |
3117 | dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long); |
3118 | memset(dirty_bitmap_buffer, 0, n); | |
b050b015 | 3119 | |
60c34612 | 3120 | spin_lock(&kvm->mmu_lock); |
b050b015 | 3121 | |
60c34612 TY |
3122 | for (i = 0; i < n / sizeof(long); i++) { |
3123 | unsigned long mask; | |
3124 | gfn_t offset; | |
cdfca7b3 | 3125 | |
60c34612 TY |
3126 | if (!dirty_bitmap[i]) |
3127 | continue; | |
b050b015 | 3128 | |
60c34612 | 3129 | is_dirty = true; |
914ebccd | 3130 | |
60c34612 TY |
3131 | mask = xchg(&dirty_bitmap[i], 0); |
3132 | dirty_bitmap_buffer[i] = mask; | |
edde99ce | 3133 | |
60c34612 TY |
3134 | offset = i * BITS_PER_LONG; |
3135 | kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask); | |
5bb064dc | 3136 | } |
60c34612 TY |
3137 | if (is_dirty) |
3138 | kvm_flush_remote_tlbs(kvm); | |
3139 | ||
3140 | spin_unlock(&kvm->mmu_lock); | |
3141 | ||
3142 | r = -EFAULT; | |
3143 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n)) | |
3144 | goto out; | |
b050b015 | 3145 | |
5bb064dc ZX |
3146 | r = 0; |
3147 | out: | |
79fac95e | 3148 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3149 | return r; |
3150 | } | |
3151 | ||
1fe779f8 CO |
3152 | long kvm_arch_vm_ioctl(struct file *filp, |
3153 | unsigned int ioctl, unsigned long arg) | |
3154 | { | |
3155 | struct kvm *kvm = filp->private_data; | |
3156 | void __user *argp = (void __user *)arg; | |
367e1319 | 3157 | int r = -ENOTTY; |
f0d66275 DH |
3158 | /* |
3159 | * This union makes it completely explicit to gcc-3.x | |
3160 | * that these two variables' stack usage should be | |
3161 | * combined, not added together. | |
3162 | */ | |
3163 | union { | |
3164 | struct kvm_pit_state ps; | |
e9f42757 | 3165 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3166 | struct kvm_pit_config pit_config; |
f0d66275 | 3167 | } u; |
1fe779f8 CO |
3168 | |
3169 | switch (ioctl) { | |
3170 | case KVM_SET_TSS_ADDR: | |
3171 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
3172 | if (r < 0) | |
3173 | goto out; | |
3174 | break; | |
b927a3ce SY |
3175 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3176 | u64 ident_addr; | |
3177 | ||
3178 | r = -EFAULT; | |
3179 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3180 | goto out; | |
3181 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
3182 | if (r < 0) | |
3183 | goto out; | |
3184 | break; | |
3185 | } | |
1fe779f8 CO |
3186 | case KVM_SET_NR_MMU_PAGES: |
3187 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
3188 | if (r) | |
3189 | goto out; | |
3190 | break; | |
3191 | case KVM_GET_NR_MMU_PAGES: | |
3192 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3193 | break; | |
3ddea128 MT |
3194 | case KVM_CREATE_IRQCHIP: { |
3195 | struct kvm_pic *vpic; | |
3196 | ||
3197 | mutex_lock(&kvm->lock); | |
3198 | r = -EEXIST; | |
3199 | if (kvm->arch.vpic) | |
3200 | goto create_irqchip_unlock; | |
3e515705 AK |
3201 | r = -EINVAL; |
3202 | if (atomic_read(&kvm->online_vcpus)) | |
3203 | goto create_irqchip_unlock; | |
1fe779f8 | 3204 | r = -ENOMEM; |
3ddea128 MT |
3205 | vpic = kvm_create_pic(kvm); |
3206 | if (vpic) { | |
1fe779f8 CO |
3207 | r = kvm_ioapic_init(kvm); |
3208 | if (r) { | |
175504cd | 3209 | mutex_lock(&kvm->slots_lock); |
72bb2fcd | 3210 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
743eeb0b SL |
3211 | &vpic->dev_master); |
3212 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3213 | &vpic->dev_slave); | |
3214 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3215 | &vpic->dev_eclr); | |
175504cd | 3216 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
3217 | kfree(vpic); |
3218 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3219 | } |
3220 | } else | |
3ddea128 MT |
3221 | goto create_irqchip_unlock; |
3222 | smp_wmb(); | |
3223 | kvm->arch.vpic = vpic; | |
3224 | smp_wmb(); | |
399ec807 AK |
3225 | r = kvm_setup_default_irq_routing(kvm); |
3226 | if (r) { | |
175504cd | 3227 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3228 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3229 | kvm_ioapic_destroy(kvm); |
3230 | kvm_destroy_pic(kvm); | |
3ddea128 | 3231 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3232 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 3233 | } |
3ddea128 MT |
3234 | create_irqchip_unlock: |
3235 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3236 | break; |
3ddea128 | 3237 | } |
7837699f | 3238 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3239 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3240 | goto create_pit; | |
3241 | case KVM_CREATE_PIT2: | |
3242 | r = -EFAULT; | |
3243 | if (copy_from_user(&u.pit_config, argp, | |
3244 | sizeof(struct kvm_pit_config))) | |
3245 | goto out; | |
3246 | create_pit: | |
79fac95e | 3247 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3248 | r = -EEXIST; |
3249 | if (kvm->arch.vpit) | |
3250 | goto create_pit_unlock; | |
7837699f | 3251 | r = -ENOMEM; |
c5ff41ce | 3252 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3253 | if (kvm->arch.vpit) |
3254 | r = 0; | |
269e05e4 | 3255 | create_pit_unlock: |
79fac95e | 3256 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3257 | break; |
4925663a | 3258 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
3259 | case KVM_IRQ_LINE: { |
3260 | struct kvm_irq_level irq_event; | |
3261 | ||
3262 | r = -EFAULT; | |
3263 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
3264 | goto out; | |
160d2f6c | 3265 | r = -ENXIO; |
1fe779f8 | 3266 | if (irqchip_in_kernel(kvm)) { |
4925663a | 3267 | __s32 status; |
4925663a GN |
3268 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
3269 | irq_event.irq, irq_event.level); | |
4925663a | 3270 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
160d2f6c | 3271 | r = -EFAULT; |
4925663a GN |
3272 | irq_event.status = status; |
3273 | if (copy_to_user(argp, &irq_event, | |
3274 | sizeof irq_event)) | |
3275 | goto out; | |
3276 | } | |
1fe779f8 CO |
3277 | r = 0; |
3278 | } | |
3279 | break; | |
3280 | } | |
3281 | case KVM_GET_IRQCHIP: { | |
3282 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3283 | struct kvm_irqchip *chip; |
1fe779f8 | 3284 | |
ff5c2c03 SL |
3285 | chip = memdup_user(argp, sizeof(*chip)); |
3286 | if (IS_ERR(chip)) { | |
3287 | r = PTR_ERR(chip); | |
1fe779f8 | 3288 | goto out; |
ff5c2c03 SL |
3289 | } |
3290 | ||
1fe779f8 CO |
3291 | r = -ENXIO; |
3292 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3293 | goto get_irqchip_out; |
3294 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3295 | if (r) |
f0d66275 | 3296 | goto get_irqchip_out; |
1fe779f8 | 3297 | r = -EFAULT; |
f0d66275 DH |
3298 | if (copy_to_user(argp, chip, sizeof *chip)) |
3299 | goto get_irqchip_out; | |
1fe779f8 | 3300 | r = 0; |
f0d66275 DH |
3301 | get_irqchip_out: |
3302 | kfree(chip); | |
3303 | if (r) | |
3304 | goto out; | |
1fe779f8 CO |
3305 | break; |
3306 | } | |
3307 | case KVM_SET_IRQCHIP: { | |
3308 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3309 | struct kvm_irqchip *chip; |
1fe779f8 | 3310 | |
ff5c2c03 SL |
3311 | chip = memdup_user(argp, sizeof(*chip)); |
3312 | if (IS_ERR(chip)) { | |
3313 | r = PTR_ERR(chip); | |
1fe779f8 | 3314 | goto out; |
ff5c2c03 SL |
3315 | } |
3316 | ||
1fe779f8 CO |
3317 | r = -ENXIO; |
3318 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3319 | goto set_irqchip_out; |
3320 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3321 | if (r) |
f0d66275 | 3322 | goto set_irqchip_out; |
1fe779f8 | 3323 | r = 0; |
f0d66275 DH |
3324 | set_irqchip_out: |
3325 | kfree(chip); | |
3326 | if (r) | |
3327 | goto out; | |
1fe779f8 CO |
3328 | break; |
3329 | } | |
e0f63cb9 | 3330 | case KVM_GET_PIT: { |
e0f63cb9 | 3331 | r = -EFAULT; |
f0d66275 | 3332 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3333 | goto out; |
3334 | r = -ENXIO; | |
3335 | if (!kvm->arch.vpit) | |
3336 | goto out; | |
f0d66275 | 3337 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3338 | if (r) |
3339 | goto out; | |
3340 | r = -EFAULT; | |
f0d66275 | 3341 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3342 | goto out; |
3343 | r = 0; | |
3344 | break; | |
3345 | } | |
3346 | case KVM_SET_PIT: { | |
e0f63cb9 | 3347 | r = -EFAULT; |
f0d66275 | 3348 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3349 | goto out; |
3350 | r = -ENXIO; | |
3351 | if (!kvm->arch.vpit) | |
3352 | goto out; | |
f0d66275 | 3353 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3354 | if (r) |
3355 | goto out; | |
3356 | r = 0; | |
3357 | break; | |
3358 | } | |
e9f42757 BK |
3359 | case KVM_GET_PIT2: { |
3360 | r = -ENXIO; | |
3361 | if (!kvm->arch.vpit) | |
3362 | goto out; | |
3363 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3364 | if (r) | |
3365 | goto out; | |
3366 | r = -EFAULT; | |
3367 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3368 | goto out; | |
3369 | r = 0; | |
3370 | break; | |
3371 | } | |
3372 | case KVM_SET_PIT2: { | |
3373 | r = -EFAULT; | |
3374 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3375 | goto out; | |
3376 | r = -ENXIO; | |
3377 | if (!kvm->arch.vpit) | |
3378 | goto out; | |
3379 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
3380 | if (r) | |
3381 | goto out; | |
3382 | r = 0; | |
3383 | break; | |
3384 | } | |
52d939a0 MT |
3385 | case KVM_REINJECT_CONTROL: { |
3386 | struct kvm_reinject_control control; | |
3387 | r = -EFAULT; | |
3388 | if (copy_from_user(&control, argp, sizeof(control))) | |
3389 | goto out; | |
3390 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
3391 | if (r) | |
3392 | goto out; | |
3393 | r = 0; | |
3394 | break; | |
3395 | } | |
ffde22ac ES |
3396 | case KVM_XEN_HVM_CONFIG: { |
3397 | r = -EFAULT; | |
3398 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3399 | sizeof(struct kvm_xen_hvm_config))) | |
3400 | goto out; | |
3401 | r = -EINVAL; | |
3402 | if (kvm->arch.xen_hvm_config.flags) | |
3403 | goto out; | |
3404 | r = 0; | |
3405 | break; | |
3406 | } | |
afbcf7ab | 3407 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
3408 | struct kvm_clock_data user_ns; |
3409 | u64 now_ns; | |
3410 | s64 delta; | |
3411 | ||
3412 | r = -EFAULT; | |
3413 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3414 | goto out; | |
3415 | ||
3416 | r = -EINVAL; | |
3417 | if (user_ns.flags) | |
3418 | goto out; | |
3419 | ||
3420 | r = 0; | |
395c6b0a | 3421 | local_irq_disable(); |
759379dd | 3422 | now_ns = get_kernel_ns(); |
afbcf7ab | 3423 | delta = user_ns.clock - now_ns; |
395c6b0a | 3424 | local_irq_enable(); |
afbcf7ab GC |
3425 | kvm->arch.kvmclock_offset = delta; |
3426 | break; | |
3427 | } | |
3428 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
3429 | struct kvm_clock_data user_ns; |
3430 | u64 now_ns; | |
3431 | ||
395c6b0a | 3432 | local_irq_disable(); |
759379dd | 3433 | now_ns = get_kernel_ns(); |
afbcf7ab | 3434 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 3435 | local_irq_enable(); |
afbcf7ab | 3436 | user_ns.flags = 0; |
97e69aa6 | 3437 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
3438 | |
3439 | r = -EFAULT; | |
3440 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3441 | goto out; | |
3442 | r = 0; | |
3443 | break; | |
3444 | } | |
3445 | ||
1fe779f8 CO |
3446 | default: |
3447 | ; | |
3448 | } | |
3449 | out: | |
3450 | return r; | |
3451 | } | |
3452 | ||
a16b043c | 3453 | static void kvm_init_msr_list(void) |
043405e1 CO |
3454 | { |
3455 | u32 dummy[2]; | |
3456 | unsigned i, j; | |
3457 | ||
e3267cbb GC |
3458 | /* skip the first msrs in the list. KVM-specific */ |
3459 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3460 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3461 | continue; | |
3462 | if (j < i) | |
3463 | msrs_to_save[j] = msrs_to_save[i]; | |
3464 | j++; | |
3465 | } | |
3466 | num_msrs_to_save = j; | |
3467 | } | |
3468 | ||
bda9020e MT |
3469 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3470 | const void *v) | |
bbd9b64e | 3471 | { |
70252a10 AK |
3472 | int handled = 0; |
3473 | int n; | |
3474 | ||
3475 | do { | |
3476 | n = min(len, 8); | |
3477 | if (!(vcpu->arch.apic && | |
3478 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v)) | |
3479 | && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3480 | break; | |
3481 | handled += n; | |
3482 | addr += n; | |
3483 | len -= n; | |
3484 | v += n; | |
3485 | } while (len); | |
bbd9b64e | 3486 | |
70252a10 | 3487 | return handled; |
bbd9b64e CO |
3488 | } |
3489 | ||
bda9020e | 3490 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3491 | { |
70252a10 AK |
3492 | int handled = 0; |
3493 | int n; | |
3494 | ||
3495 | do { | |
3496 | n = min(len, 8); | |
3497 | if (!(vcpu->arch.apic && | |
3498 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v)) | |
3499 | && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3500 | break; | |
3501 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
3502 | handled += n; | |
3503 | addr += n; | |
3504 | len -= n; | |
3505 | v += n; | |
3506 | } while (len); | |
bbd9b64e | 3507 | |
70252a10 | 3508 | return handled; |
bbd9b64e CO |
3509 | } |
3510 | ||
2dafc6c2 GN |
3511 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
3512 | struct kvm_segment *var, int seg) | |
3513 | { | |
3514 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
3515 | } | |
3516 | ||
3517 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
3518 | struct kvm_segment *var, int seg) | |
3519 | { | |
3520 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
3521 | } | |
3522 | ||
e459e322 | 3523 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
02f59dc9 JR |
3524 | { |
3525 | gpa_t t_gpa; | |
ab9ae313 | 3526 | struct x86_exception exception; |
02f59dc9 JR |
3527 | |
3528 | BUG_ON(!mmu_is_nested(vcpu)); | |
3529 | ||
3530 | /* NPT walks are always user-walks */ | |
3531 | access |= PFERR_USER_MASK; | |
ab9ae313 | 3532 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception); |
02f59dc9 JR |
3533 | |
3534 | return t_gpa; | |
3535 | } | |
3536 | ||
ab9ae313 AK |
3537 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
3538 | struct x86_exception *exception) | |
1871c602 GN |
3539 | { |
3540 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 3541 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3542 | } |
3543 | ||
ab9ae313 AK |
3544 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
3545 | struct x86_exception *exception) | |
1871c602 GN |
3546 | { |
3547 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3548 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 3549 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3550 | } |
3551 | ||
ab9ae313 AK |
3552 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
3553 | struct x86_exception *exception) | |
1871c602 GN |
3554 | { |
3555 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3556 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 3557 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3558 | } |
3559 | ||
3560 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
3561 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
3562 | struct x86_exception *exception) | |
1871c602 | 3563 | { |
ab9ae313 | 3564 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
3565 | } |
3566 | ||
3567 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3568 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 3569 | struct x86_exception *exception) |
bbd9b64e CO |
3570 | { |
3571 | void *data = val; | |
10589a46 | 3572 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3573 | |
3574 | while (bytes) { | |
14dfe855 | 3575 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 3576 | exception); |
bbd9b64e | 3577 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3578 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3579 | int ret; |
3580 | ||
bcc55cba | 3581 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3582 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e | 3583 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 | 3584 | if (ret < 0) { |
c3cd7ffa | 3585 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
3586 | goto out; |
3587 | } | |
bbd9b64e | 3588 | |
77c2002e IE |
3589 | bytes -= toread; |
3590 | data += toread; | |
3591 | addr += toread; | |
bbd9b64e | 3592 | } |
10589a46 | 3593 | out: |
10589a46 | 3594 | return r; |
bbd9b64e | 3595 | } |
77c2002e | 3596 | |
1871c602 | 3597 | /* used for instruction fetching */ |
0f65dd70 AK |
3598 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
3599 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 3600 | struct x86_exception *exception) |
1871c602 | 3601 | { |
0f65dd70 | 3602 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 3603 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 3604 | |
1871c602 | 3605 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, |
bcc55cba AK |
3606 | access | PFERR_FETCH_MASK, |
3607 | exception); | |
1871c602 GN |
3608 | } |
3609 | ||
064aea77 | 3610 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 3611 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 3612 | struct x86_exception *exception) |
1871c602 | 3613 | { |
0f65dd70 | 3614 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 3615 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 3616 | |
1871c602 | 3617 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 3618 | exception); |
1871c602 | 3619 | } |
064aea77 | 3620 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 3621 | |
0f65dd70 AK |
3622 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
3623 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 3624 | struct x86_exception *exception) |
1871c602 | 3625 | { |
0f65dd70 | 3626 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 3627 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
3628 | } |
3629 | ||
6a4d7550 | 3630 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 3631 | gva_t addr, void *val, |
2dafc6c2 | 3632 | unsigned int bytes, |
bcc55cba | 3633 | struct x86_exception *exception) |
77c2002e | 3634 | { |
0f65dd70 | 3635 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
3636 | void *data = val; |
3637 | int r = X86EMUL_CONTINUE; | |
3638 | ||
3639 | while (bytes) { | |
14dfe855 JR |
3640 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
3641 | PFERR_WRITE_MASK, | |
ab9ae313 | 3642 | exception); |
77c2002e IE |
3643 | unsigned offset = addr & (PAGE_SIZE-1); |
3644 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3645 | int ret; | |
3646 | ||
bcc55cba | 3647 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3648 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e IE |
3649 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); |
3650 | if (ret < 0) { | |
c3cd7ffa | 3651 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
3652 | goto out; |
3653 | } | |
3654 | ||
3655 | bytes -= towrite; | |
3656 | data += towrite; | |
3657 | addr += towrite; | |
3658 | } | |
3659 | out: | |
3660 | return r; | |
3661 | } | |
6a4d7550 | 3662 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 3663 | |
af7cc7d1 XG |
3664 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
3665 | gpa_t *gpa, struct x86_exception *exception, | |
3666 | bool write) | |
3667 | { | |
3668 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3669 | ||
bebb106a XG |
3670 | if (vcpu_match_mmio_gva(vcpu, gva) && |
3671 | check_write_user_access(vcpu, write, access, | |
3672 | vcpu->arch.access)) { | |
3673 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | | |
3674 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 3675 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
3676 | return 1; |
3677 | } | |
3678 | ||
af7cc7d1 XG |
3679 | if (write) |
3680 | access |= PFERR_WRITE_MASK; | |
3681 | ||
3682 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); | |
3683 | ||
3684 | if (*gpa == UNMAPPED_GVA) | |
3685 | return -1; | |
3686 | ||
3687 | /* For APIC access vmexit */ | |
3688 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3689 | return 1; | |
3690 | ||
4f022648 XG |
3691 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
3692 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 3693 | return 1; |
4f022648 | 3694 | } |
bebb106a | 3695 | |
af7cc7d1 XG |
3696 | return 0; |
3697 | } | |
3698 | ||
3200f405 | 3699 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 3700 | const void *val, int bytes) |
bbd9b64e CO |
3701 | { |
3702 | int ret; | |
3703 | ||
3704 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 3705 | if (ret < 0) |
bbd9b64e | 3706 | return 0; |
f57f2ef5 | 3707 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
3708 | return 1; |
3709 | } | |
3710 | ||
77d197b2 XG |
3711 | struct read_write_emulator_ops { |
3712 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
3713 | int bytes); | |
3714 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3715 | void *val, int bytes); | |
3716 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3717 | int bytes, void *val); | |
3718 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3719 | void *val, int bytes); | |
3720 | bool write; | |
3721 | }; | |
3722 | ||
3723 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
3724 | { | |
3725 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 3726 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 3727 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
3728 | vcpu->mmio_read_completed = 0; |
3729 | return 1; | |
3730 | } | |
3731 | ||
3732 | return 0; | |
3733 | } | |
3734 | ||
3735 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3736 | void *val, int bytes) | |
3737 | { | |
3738 | return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); | |
3739 | } | |
3740 | ||
3741 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3742 | void *val, int bytes) | |
3743 | { | |
3744 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
3745 | } | |
3746 | ||
3747 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
3748 | { | |
3749 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
3750 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
3751 | } | |
3752 | ||
3753 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3754 | void *val, int bytes) | |
3755 | { | |
3756 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
3757 | return X86EMUL_IO_NEEDED; | |
3758 | } | |
3759 | ||
3760 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3761 | void *val, int bytes) | |
3762 | { | |
f78146b0 AK |
3763 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
3764 | ||
3765 | memcpy(vcpu->run->mmio.data, frag->data, frag->len); | |
77d197b2 XG |
3766 | return X86EMUL_CONTINUE; |
3767 | } | |
3768 | ||
3769 | static struct read_write_emulator_ops read_emultor = { | |
3770 | .read_write_prepare = read_prepare, | |
3771 | .read_write_emulate = read_emulate, | |
3772 | .read_write_mmio = vcpu_mmio_read, | |
3773 | .read_write_exit_mmio = read_exit_mmio, | |
3774 | }; | |
3775 | ||
3776 | static struct read_write_emulator_ops write_emultor = { | |
3777 | .read_write_emulate = write_emulate, | |
3778 | .read_write_mmio = write_mmio, | |
3779 | .read_write_exit_mmio = write_exit_mmio, | |
3780 | .write = true, | |
3781 | }; | |
3782 | ||
22388a3c XG |
3783 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
3784 | unsigned int bytes, | |
3785 | struct x86_exception *exception, | |
3786 | struct kvm_vcpu *vcpu, | |
3787 | struct read_write_emulator_ops *ops) | |
bbd9b64e | 3788 | { |
af7cc7d1 XG |
3789 | gpa_t gpa; |
3790 | int handled, ret; | |
22388a3c | 3791 | bool write = ops->write; |
f78146b0 | 3792 | struct kvm_mmio_fragment *frag; |
10589a46 | 3793 | |
22388a3c | 3794 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 3795 | |
af7cc7d1 | 3796 | if (ret < 0) |
bbd9b64e | 3797 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3798 | |
3799 | /* For APIC access vmexit */ | |
af7cc7d1 | 3800 | if (ret) |
bbd9b64e CO |
3801 | goto mmio; |
3802 | ||
22388a3c | 3803 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
3804 | return X86EMUL_CONTINUE; |
3805 | ||
3806 | mmio: | |
3807 | /* | |
3808 | * Is this MMIO handled locally? | |
3809 | */ | |
22388a3c | 3810 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 3811 | if (handled == bytes) |
bbd9b64e | 3812 | return X86EMUL_CONTINUE; |
bbd9b64e | 3813 | |
70252a10 AK |
3814 | gpa += handled; |
3815 | bytes -= handled; | |
3816 | val += handled; | |
3817 | ||
f78146b0 AK |
3818 | while (bytes) { |
3819 | unsigned now = min(bytes, 8U); | |
bbd9b64e | 3820 | |
f78146b0 AK |
3821 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; |
3822 | frag->gpa = gpa; | |
3823 | frag->data = val; | |
3824 | frag->len = now; | |
3825 | ||
3826 | gpa += now; | |
3827 | val += now; | |
3828 | bytes -= now; | |
3829 | } | |
3830 | return X86EMUL_CONTINUE; | |
bbd9b64e CO |
3831 | } |
3832 | ||
22388a3c XG |
3833 | int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr, |
3834 | void *val, unsigned int bytes, | |
3835 | struct x86_exception *exception, | |
3836 | struct read_write_emulator_ops *ops) | |
bbd9b64e | 3837 | { |
0f65dd70 | 3838 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
3839 | gpa_t gpa; |
3840 | int rc; | |
3841 | ||
3842 | if (ops->read_write_prepare && | |
3843 | ops->read_write_prepare(vcpu, val, bytes)) | |
3844 | return X86EMUL_CONTINUE; | |
3845 | ||
3846 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 3847 | |
bbd9b64e CO |
3848 | /* Crossing a page boundary? */ |
3849 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 3850 | int now; |
bbd9b64e CO |
3851 | |
3852 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
3853 | rc = emulator_read_write_onepage(addr, val, now, exception, |
3854 | vcpu, ops); | |
3855 | ||
bbd9b64e CO |
3856 | if (rc != X86EMUL_CONTINUE) |
3857 | return rc; | |
3858 | addr += now; | |
3859 | val += now; | |
3860 | bytes -= now; | |
3861 | } | |
22388a3c | 3862 | |
f78146b0 AK |
3863 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
3864 | vcpu, ops); | |
3865 | if (rc != X86EMUL_CONTINUE) | |
3866 | return rc; | |
3867 | ||
3868 | if (!vcpu->mmio_nr_fragments) | |
3869 | return rc; | |
3870 | ||
3871 | gpa = vcpu->mmio_fragments[0].gpa; | |
3872 | ||
3873 | vcpu->mmio_needed = 1; | |
3874 | vcpu->mmio_cur_fragment = 0; | |
3875 | ||
3876 | vcpu->run->mmio.len = vcpu->mmio_fragments[0].len; | |
3877 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; | |
3878 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
3879 | vcpu->run->mmio.phys_addr = gpa; | |
3880 | ||
3881 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
3882 | } |
3883 | ||
3884 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
3885 | unsigned long addr, | |
3886 | void *val, | |
3887 | unsigned int bytes, | |
3888 | struct x86_exception *exception) | |
3889 | { | |
3890 | return emulator_read_write(ctxt, addr, val, bytes, | |
3891 | exception, &read_emultor); | |
3892 | } | |
3893 | ||
3894 | int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, | |
3895 | unsigned long addr, | |
3896 | const void *val, | |
3897 | unsigned int bytes, | |
3898 | struct x86_exception *exception) | |
3899 | { | |
3900 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
3901 | exception, &write_emultor); | |
bbd9b64e | 3902 | } |
bbd9b64e | 3903 | |
daea3e73 AK |
3904 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
3905 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
3906 | ||
3907 | #ifdef CONFIG_X86_64 | |
3908 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
3909 | #else | |
3910 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 3911 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
3912 | #endif |
3913 | ||
0f65dd70 AK |
3914 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
3915 | unsigned long addr, | |
bbd9b64e CO |
3916 | const void *old, |
3917 | const void *new, | |
3918 | unsigned int bytes, | |
0f65dd70 | 3919 | struct x86_exception *exception) |
bbd9b64e | 3920 | { |
0f65dd70 | 3921 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
3922 | gpa_t gpa; |
3923 | struct page *page; | |
3924 | char *kaddr; | |
3925 | bool exchanged; | |
2bacc55c | 3926 | |
daea3e73 AK |
3927 | /* guests cmpxchg8b have to be emulated atomically */ |
3928 | if (bytes > 8 || (bytes & (bytes - 1))) | |
3929 | goto emul_write; | |
10589a46 | 3930 | |
daea3e73 | 3931 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 3932 | |
daea3e73 AK |
3933 | if (gpa == UNMAPPED_GVA || |
3934 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3935 | goto emul_write; | |
2bacc55c | 3936 | |
daea3e73 AK |
3937 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
3938 | goto emul_write; | |
72dc67a6 | 3939 | |
daea3e73 | 3940 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
c19b8bd6 WY |
3941 | if (is_error_page(page)) { |
3942 | kvm_release_page_clean(page); | |
3943 | goto emul_write; | |
3944 | } | |
72dc67a6 | 3945 | |
8fd75e12 | 3946 | kaddr = kmap_atomic(page); |
daea3e73 AK |
3947 | kaddr += offset_in_page(gpa); |
3948 | switch (bytes) { | |
3949 | case 1: | |
3950 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
3951 | break; | |
3952 | case 2: | |
3953 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
3954 | break; | |
3955 | case 4: | |
3956 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
3957 | break; | |
3958 | case 8: | |
3959 | exchanged = CMPXCHG64(kaddr, old, new); | |
3960 | break; | |
3961 | default: | |
3962 | BUG(); | |
2bacc55c | 3963 | } |
8fd75e12 | 3964 | kunmap_atomic(kaddr); |
daea3e73 AK |
3965 | kvm_release_page_dirty(page); |
3966 | ||
3967 | if (!exchanged) | |
3968 | return X86EMUL_CMPXCHG_FAILED; | |
3969 | ||
f57f2ef5 | 3970 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
3971 | |
3972 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 3973 | |
3200f405 | 3974 | emul_write: |
daea3e73 | 3975 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 3976 | |
0f65dd70 | 3977 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
3978 | } |
3979 | ||
cf8f70bf GN |
3980 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
3981 | { | |
3982 | /* TODO: String I/O for in kernel device */ | |
3983 | int r; | |
3984 | ||
3985 | if (vcpu->arch.pio.in) | |
3986 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
3987 | vcpu->arch.pio.size, pd); | |
3988 | else | |
3989 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
3990 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
3991 | pd); | |
3992 | return r; | |
3993 | } | |
3994 | ||
6f6fbe98 XG |
3995 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
3996 | unsigned short port, void *val, | |
3997 | unsigned int count, bool in) | |
cf8f70bf | 3998 | { |
6f6fbe98 | 3999 | trace_kvm_pio(!in, port, size, count); |
cf8f70bf GN |
4000 | |
4001 | vcpu->arch.pio.port = port; | |
6f6fbe98 | 4002 | vcpu->arch.pio.in = in; |
7972995b | 4003 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4004 | vcpu->arch.pio.size = size; |
4005 | ||
4006 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4007 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4008 | return 1; |
4009 | } | |
4010 | ||
4011 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4012 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4013 | vcpu->run->io.size = size; |
4014 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4015 | vcpu->run->io.count = count; | |
4016 | vcpu->run->io.port = port; | |
4017 | ||
4018 | return 0; | |
4019 | } | |
4020 | ||
6f6fbe98 XG |
4021 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4022 | int size, unsigned short port, void *val, | |
4023 | unsigned int count) | |
cf8f70bf | 4024 | { |
ca1d4a9e | 4025 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4026 | int ret; |
ca1d4a9e | 4027 | |
6f6fbe98 XG |
4028 | if (vcpu->arch.pio.count) |
4029 | goto data_avail; | |
cf8f70bf | 4030 | |
6f6fbe98 XG |
4031 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4032 | if (ret) { | |
4033 | data_avail: | |
4034 | memcpy(val, vcpu->arch.pio_data, size * count); | |
7972995b | 4035 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4036 | return 1; |
4037 | } | |
4038 | ||
cf8f70bf GN |
4039 | return 0; |
4040 | } | |
4041 | ||
6f6fbe98 XG |
4042 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4043 | int size, unsigned short port, | |
4044 | const void *val, unsigned int count) | |
4045 | { | |
4046 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4047 | ||
4048 | memcpy(vcpu->arch.pio_data, val, size * count); | |
4049 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); | |
4050 | } | |
4051 | ||
bbd9b64e CO |
4052 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4053 | { | |
4054 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4055 | } | |
4056 | ||
3cb16fe7 | 4057 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4058 | { |
3cb16fe7 | 4059 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4060 | } |
4061 | ||
f5f48ee1 SY |
4062 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) |
4063 | { | |
4064 | if (!need_emulate_wbinvd(vcpu)) | |
4065 | return X86EMUL_CONTINUE; | |
4066 | ||
4067 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4068 | int cpu = get_cpu(); |
4069 | ||
4070 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4071 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4072 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4073 | put_cpu(); |
f5f48ee1 | 4074 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4075 | } else |
4076 | wbinvd(); | |
f5f48ee1 SY |
4077 | return X86EMUL_CONTINUE; |
4078 | } | |
4079 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
4080 | ||
bcaf5cc5 AK |
4081 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4082 | { | |
4083 | kvm_emulate_wbinvd(emul_to_vcpu(ctxt)); | |
4084 | } | |
4085 | ||
717746e3 | 4086 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) |
bbd9b64e | 4087 | { |
717746e3 | 4088 | return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4089 | } |
4090 | ||
717746e3 | 4091 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) |
bbd9b64e | 4092 | { |
338dbc97 | 4093 | |
717746e3 | 4094 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4095 | } |
4096 | ||
52a46617 | 4097 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4098 | { |
52a46617 | 4099 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4100 | } |
4101 | ||
717746e3 | 4102 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4103 | { |
717746e3 | 4104 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4105 | unsigned long value; |
4106 | ||
4107 | switch (cr) { | |
4108 | case 0: | |
4109 | value = kvm_read_cr0(vcpu); | |
4110 | break; | |
4111 | case 2: | |
4112 | value = vcpu->arch.cr2; | |
4113 | break; | |
4114 | case 3: | |
9f8fe504 | 4115 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4116 | break; |
4117 | case 4: | |
4118 | value = kvm_read_cr4(vcpu); | |
4119 | break; | |
4120 | case 8: | |
4121 | value = kvm_get_cr8(vcpu); | |
4122 | break; | |
4123 | default: | |
a737f256 | 4124 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4125 | return 0; |
4126 | } | |
4127 | ||
4128 | return value; | |
4129 | } | |
4130 | ||
717746e3 | 4131 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4132 | { |
717746e3 | 4133 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4134 | int res = 0; |
4135 | ||
52a46617 GN |
4136 | switch (cr) { |
4137 | case 0: | |
49a9b07e | 4138 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4139 | break; |
4140 | case 2: | |
4141 | vcpu->arch.cr2 = val; | |
4142 | break; | |
4143 | case 3: | |
2390218b | 4144 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4145 | break; |
4146 | case 4: | |
a83b29c6 | 4147 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4148 | break; |
4149 | case 8: | |
eea1cff9 | 4150 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4151 | break; |
4152 | default: | |
a737f256 | 4153 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 4154 | res = -1; |
52a46617 | 4155 | } |
0f12244f GN |
4156 | |
4157 | return res; | |
52a46617 GN |
4158 | } |
4159 | ||
4cee4798 KW |
4160 | static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val) |
4161 | { | |
4162 | kvm_set_rflags(emul_to_vcpu(ctxt), val); | |
4163 | } | |
4164 | ||
717746e3 | 4165 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 4166 | { |
717746e3 | 4167 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
4168 | } |
4169 | ||
4bff1e86 | 4170 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 4171 | { |
4bff1e86 | 4172 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
4173 | } |
4174 | ||
4bff1e86 | 4175 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 4176 | { |
4bff1e86 | 4177 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
4178 | } |
4179 | ||
1ac9d0cf AK |
4180 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
4181 | { | |
4182 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4183 | } | |
4184 | ||
4185 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4186 | { | |
4187 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4188 | } | |
4189 | ||
4bff1e86 AK |
4190 | static unsigned long emulator_get_cached_segment_base( |
4191 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 4192 | { |
4bff1e86 | 4193 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
4194 | } |
4195 | ||
1aa36616 AK |
4196 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
4197 | struct desc_struct *desc, u32 *base3, | |
4198 | int seg) | |
2dafc6c2 GN |
4199 | { |
4200 | struct kvm_segment var; | |
4201 | ||
4bff1e86 | 4202 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 4203 | *selector = var.selector; |
2dafc6c2 GN |
4204 | |
4205 | if (var.unusable) | |
4206 | return false; | |
4207 | ||
4208 | if (var.g) | |
4209 | var.limit >>= 12; | |
4210 | set_desc_limit(desc, var.limit); | |
4211 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4212 | #ifdef CONFIG_X86_64 |
4213 | if (base3) | |
4214 | *base3 = var.base >> 32; | |
4215 | #endif | |
2dafc6c2 GN |
4216 | desc->type = var.type; |
4217 | desc->s = var.s; | |
4218 | desc->dpl = var.dpl; | |
4219 | desc->p = var.present; | |
4220 | desc->avl = var.avl; | |
4221 | desc->l = var.l; | |
4222 | desc->d = var.db; | |
4223 | desc->g = var.g; | |
4224 | ||
4225 | return true; | |
4226 | } | |
4227 | ||
1aa36616 AK |
4228 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
4229 | struct desc_struct *desc, u32 base3, | |
4230 | int seg) | |
2dafc6c2 | 4231 | { |
4bff1e86 | 4232 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
4233 | struct kvm_segment var; |
4234 | ||
1aa36616 | 4235 | var.selector = selector; |
2dafc6c2 | 4236 | var.base = get_desc_base(desc); |
5601d05b GN |
4237 | #ifdef CONFIG_X86_64 |
4238 | var.base |= ((u64)base3) << 32; | |
4239 | #endif | |
2dafc6c2 GN |
4240 | var.limit = get_desc_limit(desc); |
4241 | if (desc->g) | |
4242 | var.limit = (var.limit << 12) | 0xfff; | |
4243 | var.type = desc->type; | |
4244 | var.present = desc->p; | |
4245 | var.dpl = desc->dpl; | |
4246 | var.db = desc->d; | |
4247 | var.s = desc->s; | |
4248 | var.l = desc->l; | |
4249 | var.g = desc->g; | |
4250 | var.avl = desc->avl; | |
4251 | var.present = desc->p; | |
4252 | var.unusable = !var.present; | |
4253 | var.padding = 0; | |
4254 | ||
4255 | kvm_set_segment(vcpu, &var, seg); | |
4256 | return; | |
4257 | } | |
4258 | ||
717746e3 AK |
4259 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
4260 | u32 msr_index, u64 *pdata) | |
4261 | { | |
4262 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
4263 | } | |
4264 | ||
4265 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4266 | u32 msr_index, u64 data) | |
4267 | { | |
4268 | return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); | |
4269 | } | |
4270 | ||
222d21aa AK |
4271 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
4272 | u32 pmc, u64 *pdata) | |
4273 | { | |
4274 | return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); | |
4275 | } | |
4276 | ||
6c3287f7 AK |
4277 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
4278 | { | |
4279 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
4280 | } | |
4281 | ||
5037f6f3 AK |
4282 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
4283 | { | |
4284 | preempt_disable(); | |
5197b808 | 4285 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
4286 | /* |
4287 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
4288 | * so it may be clear at this point. | |
4289 | */ | |
4290 | clts(); | |
4291 | } | |
4292 | ||
4293 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
4294 | { | |
4295 | preempt_enable(); | |
4296 | } | |
4297 | ||
2953538e | 4298 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 4299 | struct x86_instruction_info *info, |
c4f035c6 AK |
4300 | enum x86_intercept_stage stage) |
4301 | { | |
2953538e | 4302 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
4303 | } |
4304 | ||
0017f93a | 4305 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
4306 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
4307 | { | |
0017f93a | 4308 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
4309 | } |
4310 | ||
14af3f3c | 4311 | static struct x86_emulate_ops emulate_ops = { |
1871c602 | 4312 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4313 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 4314 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4315 | .read_emulated = emulator_read_emulated, |
4316 | .write_emulated = emulator_write_emulated, | |
4317 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 4318 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
4319 | .pio_in_emulated = emulator_pio_in_emulated, |
4320 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
4321 | .get_segment = emulator_get_segment, |
4322 | .set_segment = emulator_set_segment, | |
5951c442 | 4323 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 4324 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 4325 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
4326 | .set_gdt = emulator_set_gdt, |
4327 | .set_idt = emulator_set_idt, | |
52a46617 GN |
4328 | .get_cr = emulator_get_cr, |
4329 | .set_cr = emulator_set_cr, | |
4cee4798 | 4330 | .set_rflags = emulator_set_rflags, |
9c537244 | 4331 | .cpl = emulator_get_cpl, |
35aa5375 GN |
4332 | .get_dr = emulator_get_dr, |
4333 | .set_dr = emulator_set_dr, | |
717746e3 AK |
4334 | .set_msr = emulator_set_msr, |
4335 | .get_msr = emulator_get_msr, | |
222d21aa | 4336 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 4337 | .halt = emulator_halt, |
bcaf5cc5 | 4338 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 4339 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
4340 | .get_fpu = emulator_get_fpu, |
4341 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 4342 | .intercept = emulator_intercept, |
bdb42f5a | 4343 | .get_cpuid = emulator_get_cpuid, |
bbd9b64e CO |
4344 | }; |
4345 | ||
5fdbf976 MT |
4346 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
4347 | { | |
4348 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4349 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4350 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
4351 | vcpu->arch.regs_dirty = ~0; | |
4352 | } | |
4353 | ||
95cb2295 GN |
4354 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
4355 | { | |
4356 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); | |
4357 | /* | |
4358 | * an sti; sti; sequence only disable interrupts for the first | |
4359 | * instruction. So, if the last instruction, be it emulated or | |
4360 | * not, left the system with the INT_STI flag enabled, it | |
4361 | * means that the last instruction is an sti. We should not | |
4362 | * leave the flag on in this case. The same goes for mov ss | |
4363 | */ | |
4364 | if (!(int_shadow & mask)) | |
4365 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); | |
4366 | } | |
4367 | ||
54b8486f GN |
4368 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
4369 | { | |
4370 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 4371 | if (ctxt->exception.vector == PF_VECTOR) |
6389ee94 | 4372 | kvm_propagate_fault(vcpu, &ctxt->exception); |
da9cb575 AK |
4373 | else if (ctxt->exception.error_code_valid) |
4374 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, | |
4375 | ctxt->exception.error_code); | |
54b8486f | 4376 | else |
da9cb575 | 4377 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
54b8486f GN |
4378 | } |
4379 | ||
9dac77fa | 4380 | static void init_decode_cache(struct x86_emulate_ctxt *ctxt, |
b5c9ff73 TY |
4381 | const unsigned long *regs) |
4382 | { | |
9dac77fa AK |
4383 | memset(&ctxt->twobyte, 0, |
4384 | (void *)&ctxt->regs - (void *)&ctxt->twobyte); | |
4385 | memcpy(ctxt->regs, regs, sizeof(ctxt->regs)); | |
b5c9ff73 | 4386 | |
9dac77fa AK |
4387 | ctxt->fetch.start = 0; |
4388 | ctxt->fetch.end = 0; | |
4389 | ctxt->io_read.pos = 0; | |
4390 | ctxt->io_read.end = 0; | |
4391 | ctxt->mem_read.pos = 0; | |
4392 | ctxt->mem_read.end = 0; | |
b5c9ff73 TY |
4393 | } |
4394 | ||
8ec4722d MG |
4395 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
4396 | { | |
adf52235 | 4397 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
4398 | int cs_db, cs_l; |
4399 | ||
2aab2c5b GN |
4400 | /* |
4401 | * TODO: fix emulate.c to use guest_read/write_register | |
4402 | * instead of direct ->regs accesses, can save hundred cycles | |
4403 | * on Intel for instructions that don't read/change RSP, for | |
4404 | * for example. | |
4405 | */ | |
8ec4722d MG |
4406 | cache_all_regs(vcpu); |
4407 | ||
4408 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4409 | ||
adf52235 TY |
4410 | ctxt->eflags = kvm_get_rflags(vcpu); |
4411 | ctxt->eip = kvm_rip_read(vcpu); | |
4412 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
4413 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
4414 | cs_l ? X86EMUL_MODE_PROT64 : | |
4415 | cs_db ? X86EMUL_MODE_PROT32 : | |
4416 | X86EMUL_MODE_PROT16; | |
4417 | ctxt->guest_mode = is_guest_mode(vcpu); | |
4418 | ||
9dac77fa | 4419 | init_decode_cache(ctxt, vcpu->arch.regs); |
7ae441ea | 4420 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
4421 | } |
4422 | ||
71f9833b | 4423 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 4424 | { |
9d74191a | 4425 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
4426 | int ret; |
4427 | ||
4428 | init_emulate_ctxt(vcpu); | |
4429 | ||
9dac77fa AK |
4430 | ctxt->op_bytes = 2; |
4431 | ctxt->ad_bytes = 2; | |
4432 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 4433 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
4434 | |
4435 | if (ret != X86EMUL_CONTINUE) | |
4436 | return EMULATE_FAIL; | |
4437 | ||
9dac77fa AK |
4438 | ctxt->eip = ctxt->_eip; |
4439 | memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs); | |
9d74191a TY |
4440 | kvm_rip_write(vcpu, ctxt->eip); |
4441 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
4442 | |
4443 | if (irq == NMI_VECTOR) | |
7460fb4a | 4444 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
4445 | else |
4446 | vcpu->arch.interrupt.pending = false; | |
4447 | ||
4448 | return EMULATE_DONE; | |
4449 | } | |
4450 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
4451 | ||
6d77dbfc GN |
4452 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
4453 | { | |
fc3a9157 JR |
4454 | int r = EMULATE_DONE; |
4455 | ||
6d77dbfc GN |
4456 | ++vcpu->stat.insn_emulation_fail; |
4457 | trace_kvm_emulate_insn_failed(vcpu); | |
fc3a9157 JR |
4458 | if (!is_guest_mode(vcpu)) { |
4459 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4460 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4461 | vcpu->run->internal.ndata = 0; | |
4462 | r = EMULATE_FAIL; | |
4463 | } | |
6d77dbfc | 4464 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
4465 | |
4466 | return r; | |
6d77dbfc GN |
4467 | } |
4468 | ||
a6f177ef GN |
4469 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva) |
4470 | { | |
4471 | gpa_t gpa; | |
4472 | ||
68be0803 GN |
4473 | if (tdp_enabled) |
4474 | return false; | |
4475 | ||
a6f177ef GN |
4476 | /* |
4477 | * if emulation was due to access to shadowed page table | |
4478 | * and it failed try to unshadow page and re-entetr the | |
4479 | * guest to let CPU execute the instruction. | |
4480 | */ | |
4481 | if (kvm_mmu_unprotect_page_virt(vcpu, gva)) | |
4482 | return true; | |
4483 | ||
4484 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL); | |
4485 | ||
4486 | if (gpa == UNMAPPED_GVA) | |
4487 | return true; /* let cpu generate fault */ | |
4488 | ||
4489 | if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT))) | |
4490 | return true; | |
4491 | ||
4492 | return false; | |
4493 | } | |
4494 | ||
1cb3f3ae XG |
4495 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
4496 | unsigned long cr2, int emulation_type) | |
4497 | { | |
4498 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4499 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
4500 | ||
4501 | last_retry_eip = vcpu->arch.last_retry_eip; | |
4502 | last_retry_addr = vcpu->arch.last_retry_addr; | |
4503 | ||
4504 | /* | |
4505 | * If the emulation is caused by #PF and it is non-page_table | |
4506 | * writing instruction, it means the VM-EXIT is caused by shadow | |
4507 | * page protected, we can zap the shadow page and retry this | |
4508 | * instruction directly. | |
4509 | * | |
4510 | * Note: if the guest uses a non-page-table modifying instruction | |
4511 | * on the PDE that points to the instruction, then we will unmap | |
4512 | * the instruction and go to an infinite loop. So, we cache the | |
4513 | * last retried eip and the last fault address, if we meet the eip | |
4514 | * and the address again, we can break out of the potential infinite | |
4515 | * loop. | |
4516 | */ | |
4517 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
4518 | ||
4519 | if (!(emulation_type & EMULTYPE_RETRY)) | |
4520 | return false; | |
4521 | ||
4522 | if (x86_page_table_writing_insn(ctxt)) | |
4523 | return false; | |
4524 | ||
4525 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
4526 | return false; | |
4527 | ||
4528 | vcpu->arch.last_retry_eip = ctxt->eip; | |
4529 | vcpu->arch.last_retry_addr = cr2; | |
4530 | ||
4531 | if (!vcpu->arch.mmu.direct_map) | |
4532 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
4533 | ||
4534 | kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); | |
4535 | ||
4536 | return true; | |
4537 | } | |
4538 | ||
51d8b661 AP |
4539 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
4540 | unsigned long cr2, | |
dc25e89e AP |
4541 | int emulation_type, |
4542 | void *insn, | |
4543 | int insn_len) | |
bbd9b64e | 4544 | { |
95cb2295 | 4545 | int r; |
9d74191a | 4546 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 4547 | bool writeback = true; |
bbd9b64e | 4548 | |
26eef70c | 4549 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 4550 | |
571008da | 4551 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 4552 | init_emulate_ctxt(vcpu); |
9d74191a TY |
4553 | ctxt->interruptibility = 0; |
4554 | ctxt->have_exception = false; | |
4555 | ctxt->perm_ok = false; | |
bbd9b64e | 4556 | |
9d74191a | 4557 | ctxt->only_vendor_specific_insn |
4005996e AK |
4558 | = emulation_type & EMULTYPE_TRAP_UD; |
4559 | ||
9d74191a | 4560 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 4561 | |
e46479f8 | 4562 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 4563 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 4564 | if (r != EMULATION_OK) { |
4005996e AK |
4565 | if (emulation_type & EMULTYPE_TRAP_UD) |
4566 | return EMULATE_FAIL; | |
a6f177ef | 4567 | if (reexecute_instruction(vcpu, cr2)) |
bbd9b64e | 4568 | return EMULATE_DONE; |
6d77dbfc GN |
4569 | if (emulation_type & EMULTYPE_SKIP) |
4570 | return EMULATE_FAIL; | |
4571 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
4572 | } |
4573 | } | |
4574 | ||
ba8afb6b | 4575 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 4576 | kvm_rip_write(vcpu, ctxt->_eip); |
ba8afb6b GN |
4577 | return EMULATE_DONE; |
4578 | } | |
4579 | ||
1cb3f3ae XG |
4580 | if (retry_instruction(ctxt, cr2, emulation_type)) |
4581 | return EMULATE_DONE; | |
4582 | ||
7ae441ea | 4583 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 4584 | changes registers values during IO operation */ |
7ae441ea GN |
4585 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
4586 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
9dac77fa | 4587 | memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs); |
7ae441ea | 4588 | } |
4d2179e1 | 4589 | |
5cd21917 | 4590 | restart: |
9d74191a | 4591 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 4592 | |
775fde86 JR |
4593 | if (r == EMULATION_INTERCEPTED) |
4594 | return EMULATE_DONE; | |
4595 | ||
d2ddd1c4 | 4596 | if (r == EMULATION_FAILED) { |
a6f177ef | 4597 | if (reexecute_instruction(vcpu, cr2)) |
c3cd7ffa GN |
4598 | return EMULATE_DONE; |
4599 | ||
6d77dbfc | 4600 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
4601 | } |
4602 | ||
9d74191a | 4603 | if (ctxt->have_exception) { |
54b8486f | 4604 | inject_emulated_exception(vcpu); |
d2ddd1c4 GN |
4605 | r = EMULATE_DONE; |
4606 | } else if (vcpu->arch.pio.count) { | |
3457e419 GN |
4607 | if (!vcpu->arch.pio.in) |
4608 | vcpu->arch.pio.count = 0; | |
7ae441ea GN |
4609 | else |
4610 | writeback = false; | |
e85d28f8 | 4611 | r = EMULATE_DO_MMIO; |
7ae441ea GN |
4612 | } else if (vcpu->mmio_needed) { |
4613 | if (!vcpu->mmio_is_write) | |
4614 | writeback = false; | |
e85d28f8 | 4615 | r = EMULATE_DO_MMIO; |
7ae441ea | 4616 | } else if (r == EMULATION_RESTART) |
5cd21917 | 4617 | goto restart; |
d2ddd1c4 GN |
4618 | else |
4619 | r = EMULATE_DONE; | |
f850e2e6 | 4620 | |
7ae441ea | 4621 | if (writeback) { |
9d74191a TY |
4622 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
4623 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7ae441ea | 4624 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
9dac77fa | 4625 | memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs); |
7ae441ea | 4626 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9d74191a | 4627 | kvm_rip_write(vcpu, ctxt->eip); |
7ae441ea GN |
4628 | } else |
4629 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
4630 | |
4631 | return r; | |
de7d789a | 4632 | } |
51d8b661 | 4633 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 4634 | |
cf8f70bf | 4635 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 4636 | { |
cf8f70bf | 4637 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
4638 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
4639 | size, port, &val, 1); | |
cf8f70bf | 4640 | /* do not return to emulator after return from userspace */ |
7972995b | 4641 | vcpu->arch.pio.count = 0; |
de7d789a CO |
4642 | return ret; |
4643 | } | |
cf8f70bf | 4644 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 4645 | |
8cfdc000 ZA |
4646 | static void tsc_bad(void *info) |
4647 | { | |
0a3aee0d | 4648 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
4649 | } |
4650 | ||
4651 | static void tsc_khz_changed(void *data) | |
c8076604 | 4652 | { |
8cfdc000 ZA |
4653 | struct cpufreq_freqs *freq = data; |
4654 | unsigned long khz = 0; | |
4655 | ||
4656 | if (data) | |
4657 | khz = freq->new; | |
4658 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
4659 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
4660 | if (!khz) | |
4661 | khz = tsc_khz; | |
0a3aee0d | 4662 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
4663 | } |
4664 | ||
c8076604 GH |
4665 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
4666 | void *data) | |
4667 | { | |
4668 | struct cpufreq_freqs *freq = data; | |
4669 | struct kvm *kvm; | |
4670 | struct kvm_vcpu *vcpu; | |
4671 | int i, send_ipi = 0; | |
4672 | ||
8cfdc000 ZA |
4673 | /* |
4674 | * We allow guests to temporarily run on slowing clocks, | |
4675 | * provided we notify them after, or to run on accelerating | |
4676 | * clocks, provided we notify them before. Thus time never | |
4677 | * goes backwards. | |
4678 | * | |
4679 | * However, we have a problem. We can't atomically update | |
4680 | * the frequency of a given CPU from this function; it is | |
4681 | * merely a notifier, which can be called from any CPU. | |
4682 | * Changing the TSC frequency at arbitrary points in time | |
4683 | * requires a recomputation of local variables related to | |
4684 | * the TSC for each VCPU. We must flag these local variables | |
4685 | * to be updated and be sure the update takes place with the | |
4686 | * new frequency before any guests proceed. | |
4687 | * | |
4688 | * Unfortunately, the combination of hotplug CPU and frequency | |
4689 | * change creates an intractable locking scenario; the order | |
4690 | * of when these callouts happen is undefined with respect to | |
4691 | * CPU hotplug, and they can race with each other. As such, | |
4692 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
4693 | * undefined; you can actually have a CPU frequency change take | |
4694 | * place in between the computation of X and the setting of the | |
4695 | * variable. To protect against this problem, all updates of | |
4696 | * the per_cpu tsc_khz variable are done in an interrupt | |
4697 | * protected IPI, and all callers wishing to update the value | |
4698 | * must wait for a synchronous IPI to complete (which is trivial | |
4699 | * if the caller is on the CPU already). This establishes the | |
4700 | * necessary total order on variable updates. | |
4701 | * | |
4702 | * Note that because a guest time update may take place | |
4703 | * anytime after the setting of the VCPU's request bit, the | |
4704 | * correct TSC value must be set before the request. However, | |
4705 | * to ensure the update actually makes it to any guest which | |
4706 | * starts running in hardware virtualization between the set | |
4707 | * and the acquisition of the spinlock, we must also ping the | |
4708 | * CPU after setting the request bit. | |
4709 | * | |
4710 | */ | |
4711 | ||
c8076604 GH |
4712 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
4713 | return 0; | |
4714 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
4715 | return 0; | |
8cfdc000 ZA |
4716 | |
4717 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 4718 | |
e935b837 | 4719 | raw_spin_lock(&kvm_lock); |
c8076604 | 4720 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 4721 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
4722 | if (vcpu->cpu != freq->cpu) |
4723 | continue; | |
c285545f | 4724 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 4725 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 4726 | send_ipi = 1; |
c8076604 GH |
4727 | } |
4728 | } | |
e935b837 | 4729 | raw_spin_unlock(&kvm_lock); |
c8076604 GH |
4730 | |
4731 | if (freq->old < freq->new && send_ipi) { | |
4732 | /* | |
4733 | * We upscale the frequency. Must make the guest | |
4734 | * doesn't see old kvmclock values while running with | |
4735 | * the new frequency, otherwise we risk the guest sees | |
4736 | * time go backwards. | |
4737 | * | |
4738 | * In case we update the frequency for another cpu | |
4739 | * (which might be in guest context) send an interrupt | |
4740 | * to kick the cpu out of guest context. Next time | |
4741 | * guest context is entered kvmclock will be updated, | |
4742 | * so the guest will not see stale values. | |
4743 | */ | |
8cfdc000 | 4744 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
4745 | } |
4746 | return 0; | |
4747 | } | |
4748 | ||
4749 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
4750 | .notifier_call = kvmclock_cpufreq_notifier |
4751 | }; | |
4752 | ||
4753 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
4754 | unsigned long action, void *hcpu) | |
4755 | { | |
4756 | unsigned int cpu = (unsigned long)hcpu; | |
4757 | ||
4758 | switch (action) { | |
4759 | case CPU_ONLINE: | |
4760 | case CPU_DOWN_FAILED: | |
4761 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
4762 | break; | |
4763 | case CPU_DOWN_PREPARE: | |
4764 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
4765 | break; | |
4766 | } | |
4767 | return NOTIFY_OK; | |
4768 | } | |
4769 | ||
4770 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
4771 | .notifier_call = kvmclock_cpu_notifier, | |
4772 | .priority = -INT_MAX | |
c8076604 GH |
4773 | }; |
4774 | ||
b820cc0c ZA |
4775 | static void kvm_timer_init(void) |
4776 | { | |
4777 | int cpu; | |
4778 | ||
c285545f | 4779 | max_tsc_khz = tsc_khz; |
8cfdc000 | 4780 | register_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
b820cc0c | 4781 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
4782 | #ifdef CONFIG_CPU_FREQ |
4783 | struct cpufreq_policy policy; | |
4784 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
4785 | cpu = get_cpu(); |
4786 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
4787 | if (policy.cpuinfo.max_freq) |
4788 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 4789 | put_cpu(); |
c285545f | 4790 | #endif |
b820cc0c ZA |
4791 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
4792 | CPUFREQ_TRANSITION_NOTIFIER); | |
4793 | } | |
c285545f | 4794 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
4795 | for_each_online_cpu(cpu) |
4796 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
b820cc0c ZA |
4797 | } |
4798 | ||
ff9d07a0 ZY |
4799 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
4800 | ||
f5132b01 | 4801 | int kvm_is_in_guest(void) |
ff9d07a0 | 4802 | { |
086c9855 | 4803 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
4804 | } |
4805 | ||
4806 | static int kvm_is_user_mode(void) | |
4807 | { | |
4808 | int user_mode = 3; | |
dcf46b94 | 4809 | |
086c9855 AS |
4810 | if (__this_cpu_read(current_vcpu)) |
4811 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 4812 | |
ff9d07a0 ZY |
4813 | return user_mode != 0; |
4814 | } | |
4815 | ||
4816 | static unsigned long kvm_get_guest_ip(void) | |
4817 | { | |
4818 | unsigned long ip = 0; | |
dcf46b94 | 4819 | |
086c9855 AS |
4820 | if (__this_cpu_read(current_vcpu)) |
4821 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 4822 | |
ff9d07a0 ZY |
4823 | return ip; |
4824 | } | |
4825 | ||
4826 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
4827 | .is_in_guest = kvm_is_in_guest, | |
4828 | .is_user_mode = kvm_is_user_mode, | |
4829 | .get_guest_ip = kvm_get_guest_ip, | |
4830 | }; | |
4831 | ||
4832 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
4833 | { | |
086c9855 | 4834 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
4835 | } |
4836 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
4837 | ||
4838 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
4839 | { | |
086c9855 | 4840 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
4841 | } |
4842 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
4843 | ||
ce88decf XG |
4844 | static void kvm_set_mmio_spte_mask(void) |
4845 | { | |
4846 | u64 mask; | |
4847 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
4848 | ||
4849 | /* | |
4850 | * Set the reserved bits and the present bit of an paging-structure | |
4851 | * entry to generate page fault with PFER.RSV = 1. | |
4852 | */ | |
4853 | mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr; | |
4854 | mask |= 1ull; | |
4855 | ||
4856 | #ifdef CONFIG_X86_64 | |
4857 | /* | |
4858 | * If reserved bit is not supported, clear the present bit to disable | |
4859 | * mmio page fault. | |
4860 | */ | |
4861 | if (maxphyaddr == 52) | |
4862 | mask &= ~1ull; | |
4863 | #endif | |
4864 | ||
4865 | kvm_mmu_set_mmio_spte_mask(mask); | |
4866 | } | |
4867 | ||
f8c16bba | 4868 | int kvm_arch_init(void *opaque) |
043405e1 | 4869 | { |
b820cc0c | 4870 | int r; |
f8c16bba ZX |
4871 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
4872 | ||
f8c16bba ZX |
4873 | if (kvm_x86_ops) { |
4874 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
4875 | r = -EEXIST; |
4876 | goto out; | |
f8c16bba ZX |
4877 | } |
4878 | ||
4879 | if (!ops->cpu_has_kvm_support()) { | |
4880 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
4881 | r = -EOPNOTSUPP; |
4882 | goto out; | |
f8c16bba ZX |
4883 | } |
4884 | if (ops->disabled_by_bios()) { | |
4885 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
4886 | r = -EOPNOTSUPP; |
4887 | goto out; | |
f8c16bba ZX |
4888 | } |
4889 | ||
97db56ce AK |
4890 | r = kvm_mmu_module_init(); |
4891 | if (r) | |
4892 | goto out; | |
4893 | ||
ce88decf | 4894 | kvm_set_mmio_spte_mask(); |
97db56ce AK |
4895 | kvm_init_msr_list(); |
4896 | ||
f8c16bba | 4897 | kvm_x86_ops = ops; |
7b52345e | 4898 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 4899 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 4900 | |
b820cc0c | 4901 | kvm_timer_init(); |
c8076604 | 4902 | |
ff9d07a0 ZY |
4903 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
4904 | ||
2acf923e DC |
4905 | if (cpu_has_xsave) |
4906 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
4907 | ||
f8c16bba | 4908 | return 0; |
56c6d28a ZX |
4909 | |
4910 | out: | |
56c6d28a | 4911 | return r; |
043405e1 | 4912 | } |
8776e519 | 4913 | |
f8c16bba ZX |
4914 | void kvm_arch_exit(void) |
4915 | { | |
ff9d07a0 ZY |
4916 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
4917 | ||
888d256e JK |
4918 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
4919 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
4920 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 4921 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
f8c16bba | 4922 | kvm_x86_ops = NULL; |
56c6d28a ZX |
4923 | kvm_mmu_module_exit(); |
4924 | } | |
f8c16bba | 4925 | |
8776e519 HB |
4926 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
4927 | { | |
4928 | ++vcpu->stat.halt_exits; | |
4929 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 4930 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
4931 | return 1; |
4932 | } else { | |
4933 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
4934 | return 0; | |
4935 | } | |
4936 | } | |
4937 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
4938 | ||
55cd8e5a GN |
4939 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
4940 | { | |
4941 | u64 param, ingpa, outgpa, ret; | |
4942 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
4943 | bool fast, longmode; | |
4944 | int cs_db, cs_l; | |
4945 | ||
4946 | /* | |
4947 | * hypercall generates UD from non zero cpl and real mode | |
4948 | * per HYPER-V spec | |
4949 | */ | |
3eeb3288 | 4950 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
4951 | kvm_queue_exception(vcpu, UD_VECTOR); |
4952 | return 0; | |
4953 | } | |
4954 | ||
4955 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4956 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
4957 | ||
4958 | if (!longmode) { | |
ccd46936 GN |
4959 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
4960 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
4961 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
4962 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
4963 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
4964 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
4965 | } |
4966 | #ifdef CONFIG_X86_64 | |
4967 | else { | |
4968 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4969 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4970 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
4971 | } | |
4972 | #endif | |
4973 | ||
4974 | code = param & 0xffff; | |
4975 | fast = (param >> 16) & 0x1; | |
4976 | rep_cnt = (param >> 32) & 0xfff; | |
4977 | rep_idx = (param >> 48) & 0xfff; | |
4978 | ||
4979 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
4980 | ||
c25bc163 GN |
4981 | switch (code) { |
4982 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
4983 | kvm_vcpu_on_spin(vcpu); | |
4984 | break; | |
4985 | default: | |
4986 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
4987 | break; | |
4988 | } | |
55cd8e5a GN |
4989 | |
4990 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
4991 | if (longmode) { | |
4992 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
4993 | } else { | |
4994 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
4995 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
4996 | } | |
4997 | ||
4998 | return 1; | |
4999 | } | |
5000 | ||
8776e519 HB |
5001 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
5002 | { | |
5003 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 5004 | int r = 1; |
8776e519 | 5005 | |
55cd8e5a GN |
5006 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
5007 | return kvm_hv_hypercall(vcpu); | |
5008 | ||
5fdbf976 MT |
5009 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5010 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5011 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5012 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5013 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 5014 | |
229456fc | 5015 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 5016 | |
8776e519 HB |
5017 | if (!is_long_mode(vcpu)) { |
5018 | nr &= 0xFFFFFFFF; | |
5019 | a0 &= 0xFFFFFFFF; | |
5020 | a1 &= 0xFFFFFFFF; | |
5021 | a2 &= 0xFFFFFFFF; | |
5022 | a3 &= 0xFFFFFFFF; | |
5023 | } | |
5024 | ||
07708c4a JK |
5025 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
5026 | ret = -KVM_EPERM; | |
5027 | goto out; | |
5028 | } | |
5029 | ||
8776e519 | 5030 | switch (nr) { |
b93463aa AK |
5031 | case KVM_HC_VAPIC_POLL_IRQ: |
5032 | ret = 0; | |
5033 | break; | |
8776e519 HB |
5034 | default: |
5035 | ret = -KVM_ENOSYS; | |
5036 | break; | |
5037 | } | |
07708c4a | 5038 | out: |
5fdbf976 | 5039 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 5040 | ++vcpu->stat.hypercalls; |
2f333bcb | 5041 | return r; |
8776e519 HB |
5042 | } |
5043 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
5044 | ||
d6aa1000 | 5045 | int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 5046 | { |
d6aa1000 | 5047 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 5048 | char instruction[3]; |
5fdbf976 | 5049 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 5050 | |
8776e519 HB |
5051 | /* |
5052 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
5053 | * to ensure that the updated hypercall appears atomically across all | |
5054 | * VCPUs. | |
5055 | */ | |
5056 | kvm_mmu_zap_all(vcpu->kvm); | |
5057 | ||
8776e519 | 5058 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 5059 | |
9d74191a | 5060 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
5061 | } |
5062 | ||
b6c7a5dc HB |
5063 | /* |
5064 | * Check if userspace requested an interrupt window, and that the | |
5065 | * interrupt window is open. | |
5066 | * | |
5067 | * No need to exit to userspace if we already have an interrupt queued. | |
5068 | */ | |
851ba692 | 5069 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5070 | { |
8061823a | 5071 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 5072 | vcpu->run->request_interrupt_window && |
5df56646 | 5073 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
5074 | } |
5075 | ||
851ba692 | 5076 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5077 | { |
851ba692 AK |
5078 | struct kvm_run *kvm_run = vcpu->run; |
5079 | ||
91586a3b | 5080 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 5081 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 5082 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 5083 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 5084 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 5085 | else |
b6c7a5dc | 5086 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
5087 | kvm_arch_interrupt_allowed(vcpu) && |
5088 | !kvm_cpu_has_interrupt(vcpu) && | |
5089 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
5090 | } |
5091 | ||
b93463aa AK |
5092 | static void vapic_enter(struct kvm_vcpu *vcpu) |
5093 | { | |
5094 | struct kvm_lapic *apic = vcpu->arch.apic; | |
5095 | struct page *page; | |
5096 | ||
5097 | if (!apic || !apic->vapic_addr) | |
5098 | return; | |
5099 | ||
5100 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
5101 | |
5102 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
5103 | } |
5104 | ||
5105 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
5106 | { | |
5107 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 5108 | int idx; |
b93463aa AK |
5109 | |
5110 | if (!apic || !apic->vapic_addr) | |
5111 | return; | |
5112 | ||
f656ce01 | 5113 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
5114 | kvm_release_page_dirty(apic->vapic_page); |
5115 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 5116 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5117 | } |
5118 | ||
95ba8273 GN |
5119 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
5120 | { | |
5121 | int max_irr, tpr; | |
5122 | ||
5123 | if (!kvm_x86_ops->update_cr8_intercept) | |
5124 | return; | |
5125 | ||
88c808fd AK |
5126 | if (!vcpu->arch.apic) |
5127 | return; | |
5128 | ||
8db3baa2 GN |
5129 | if (!vcpu->arch.apic->vapic_addr) |
5130 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
5131 | else | |
5132 | max_irr = -1; | |
95ba8273 GN |
5133 | |
5134 | if (max_irr != -1) | |
5135 | max_irr >>= 4; | |
5136 | ||
5137 | tpr = kvm_lapic_get_cr8(vcpu); | |
5138 | ||
5139 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
5140 | } | |
5141 | ||
851ba692 | 5142 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
5143 | { |
5144 | /* try to reinject previous events if any */ | |
b59bb7bd | 5145 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
5146 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
5147 | vcpu->arch.exception.has_error_code, | |
5148 | vcpu->arch.exception.error_code); | |
b59bb7bd GN |
5149 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
5150 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
5151 | vcpu->arch.exception.error_code, |
5152 | vcpu->arch.exception.reinject); | |
b59bb7bd GN |
5153 | return; |
5154 | } | |
5155 | ||
95ba8273 GN |
5156 | if (vcpu->arch.nmi_injected) { |
5157 | kvm_x86_ops->set_nmi(vcpu); | |
5158 | return; | |
5159 | } | |
5160 | ||
5161 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 5162 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
5163 | return; |
5164 | } | |
5165 | ||
5166 | /* try to inject new event if pending */ | |
5167 | if (vcpu->arch.nmi_pending) { | |
5168 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
7460fb4a | 5169 | --vcpu->arch.nmi_pending; |
95ba8273 GN |
5170 | vcpu->arch.nmi_injected = true; |
5171 | kvm_x86_ops->set_nmi(vcpu); | |
5172 | } | |
5173 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
5174 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
5175 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
5176 | false); | |
5177 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
5178 | } |
5179 | } | |
5180 | } | |
5181 | ||
2acf923e DC |
5182 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
5183 | { | |
5184 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
5185 | !vcpu->guest_xcr0_loaded) { | |
5186 | /* kvm_set_xcr() also depends on this */ | |
5187 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
5188 | vcpu->guest_xcr0_loaded = 1; | |
5189 | } | |
5190 | } | |
5191 | ||
5192 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
5193 | { | |
5194 | if (vcpu->guest_xcr0_loaded) { | |
5195 | if (vcpu->arch.xcr0 != host_xcr0) | |
5196 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
5197 | vcpu->guest_xcr0_loaded = 0; | |
5198 | } | |
5199 | } | |
5200 | ||
7460fb4a AK |
5201 | static void process_nmi(struct kvm_vcpu *vcpu) |
5202 | { | |
5203 | unsigned limit = 2; | |
5204 | ||
5205 | /* | |
5206 | * x86 is limited to one NMI running, and one NMI pending after it. | |
5207 | * If an NMI is already in progress, limit further NMIs to just one. | |
5208 | * Otherwise, allow two (and we'll inject the first one immediately). | |
5209 | */ | |
5210 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
5211 | limit = 1; | |
5212 | ||
5213 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
5214 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
5215 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5216 | } | |
5217 | ||
851ba692 | 5218 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
5219 | { |
5220 | int r; | |
6a8b1d13 | 5221 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 5222 | vcpu->run->request_interrupt_window; |
d6185f20 | 5223 | bool req_immediate_exit = 0; |
b6c7a5dc | 5224 | |
3e007509 | 5225 | if (vcpu->requests) { |
a8eeb04a | 5226 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 5227 | kvm_mmu_unload(vcpu); |
a8eeb04a | 5228 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 5229 | __kvm_migrate_timers(vcpu); |
34c238a1 ZA |
5230 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
5231 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
5232 | if (unlikely(r)) |
5233 | goto out; | |
5234 | } | |
a8eeb04a | 5235 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 5236 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 5237 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
d4acf7e7 | 5238 | kvm_x86_ops->tlb_flush(vcpu); |
a8eeb04a | 5239 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 5240 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
5241 | r = 0; |
5242 | goto out; | |
5243 | } | |
a8eeb04a | 5244 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 5245 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
5246 | r = 0; |
5247 | goto out; | |
5248 | } | |
a8eeb04a | 5249 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
5250 | vcpu->fpu_active = 0; |
5251 | kvm_x86_ops->fpu_deactivate(vcpu); | |
5252 | } | |
af585b92 GN |
5253 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
5254 | /* Page is swapped out. Do synthetic halt */ | |
5255 | vcpu->arch.apf.halted = true; | |
5256 | r = 1; | |
5257 | goto out; | |
5258 | } | |
c9aaa895 GC |
5259 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
5260 | record_steal_time(vcpu); | |
7460fb4a AK |
5261 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
5262 | process_nmi(vcpu); | |
d6185f20 NHE |
5263 | req_immediate_exit = |
5264 | kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu); | |
f5132b01 GN |
5265 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
5266 | kvm_handle_pmu_event(vcpu); | |
5267 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
5268 | kvm_deliver_pmi(vcpu); | |
2f52d58c | 5269 | } |
b93463aa | 5270 | |
b463a6f7 AK |
5271 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
5272 | inject_pending_event(vcpu); | |
5273 | ||
5274 | /* enable NMI/IRQ window open exits if needed */ | |
7460fb4a | 5275 | if (vcpu->arch.nmi_pending) |
b463a6f7 AK |
5276 | kvm_x86_ops->enable_nmi_window(vcpu); |
5277 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
5278 | kvm_x86_ops->enable_irq_window(vcpu); | |
5279 | ||
5280 | if (kvm_lapic_enabled(vcpu)) { | |
5281 | update_cr8_intercept(vcpu); | |
5282 | kvm_lapic_sync_to_vapic(vcpu); | |
5283 | } | |
5284 | } | |
5285 | ||
d8368af8 AK |
5286 | r = kvm_mmu_reload(vcpu); |
5287 | if (unlikely(r)) { | |
d905c069 | 5288 | goto cancel_injection; |
d8368af8 AK |
5289 | } |
5290 | ||
b6c7a5dc HB |
5291 | preempt_disable(); |
5292 | ||
5293 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
5294 | if (vcpu->fpu_active) |
5295 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 5296 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 5297 | |
6b7e2d09 XG |
5298 | vcpu->mode = IN_GUEST_MODE; |
5299 | ||
5300 | /* We should set ->mode before check ->requests, | |
5301 | * see the comment in make_all_cpus_request. | |
5302 | */ | |
5303 | smp_mb(); | |
b6c7a5dc | 5304 | |
d94e1dc9 | 5305 | local_irq_disable(); |
32f88400 | 5306 | |
6b7e2d09 | 5307 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 5308 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 5309 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5310 | smp_wmb(); |
6c142801 AK |
5311 | local_irq_enable(); |
5312 | preempt_enable(); | |
5313 | r = 1; | |
d905c069 | 5314 | goto cancel_injection; |
6c142801 AK |
5315 | } |
5316 | ||
f656ce01 | 5317 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 5318 | |
d6185f20 NHE |
5319 | if (req_immediate_exit) |
5320 | smp_send_reschedule(vcpu->cpu); | |
5321 | ||
b6c7a5dc HB |
5322 | kvm_guest_enter(); |
5323 | ||
42dbaa5a | 5324 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
5325 | set_debugreg(0, 7); |
5326 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
5327 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
5328 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
5329 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
5330 | } | |
b6c7a5dc | 5331 | |
229456fc | 5332 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 5333 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 5334 | |
24f1e32c FW |
5335 | /* |
5336 | * If the guest has used debug registers, at least dr7 | |
5337 | * will be disabled while returning to the host. | |
5338 | * If we don't have active breakpoints in the host, we don't | |
5339 | * care about the messed up debug address registers. But if | |
5340 | * we have some of them active, restore the old state. | |
5341 | */ | |
59d8eb53 | 5342 | if (hw_breakpoint_active()) |
24f1e32c | 5343 | hw_breakpoint_restore(); |
42dbaa5a | 5344 | |
d5c1785d | 5345 | vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu); |
1d5f066e | 5346 | |
6b7e2d09 | 5347 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5348 | smp_wmb(); |
b6c7a5dc HB |
5349 | local_irq_enable(); |
5350 | ||
5351 | ++vcpu->stat.exits; | |
5352 | ||
5353 | /* | |
5354 | * We must have an instruction between local_irq_enable() and | |
5355 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
5356 | * the interrupt shadow. The stat.exits increment will do nicely. | |
5357 | * But we need to prevent reordering, hence this barrier(): | |
5358 | */ | |
5359 | barrier(); | |
5360 | ||
5361 | kvm_guest_exit(); | |
5362 | ||
5363 | preempt_enable(); | |
5364 | ||
f656ce01 | 5365 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 5366 | |
b6c7a5dc HB |
5367 | /* |
5368 | * Profile KVM exit RIPs: | |
5369 | */ | |
5370 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
5371 | unsigned long rip = kvm_rip_read(vcpu); |
5372 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
5373 | } |
5374 | ||
cc578287 ZA |
5375 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
5376 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 5377 | |
5cfb1d5a MT |
5378 | if (vcpu->arch.apic_attention) |
5379 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 5380 | |
851ba692 | 5381 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
5382 | return r; |
5383 | ||
5384 | cancel_injection: | |
5385 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
5386 | if (unlikely(vcpu->arch.apic_attention)) |
5387 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
5388 | out: |
5389 | return r; | |
5390 | } | |
b6c7a5dc | 5391 | |
09cec754 | 5392 | |
851ba692 | 5393 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
5394 | { |
5395 | int r; | |
f656ce01 | 5396 | struct kvm *kvm = vcpu->kvm; |
d7690175 MT |
5397 | |
5398 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
5399 | pr_debug("vcpu %d received sipi with vector # %x\n", |
5400 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 5401 | kvm_lapic_reset(vcpu); |
5f179287 | 5402 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
5403 | if (r) |
5404 | return r; | |
5405 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
5406 | } |
5407 | ||
f656ce01 | 5408 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
5409 | vapic_enter(vcpu); |
5410 | ||
5411 | r = 1; | |
5412 | while (r > 0) { | |
af585b92 GN |
5413 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
5414 | !vcpu->arch.apf.halted) | |
851ba692 | 5415 | r = vcpu_enter_guest(vcpu); |
d7690175 | 5416 | else { |
f656ce01 | 5417 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 5418 | kvm_vcpu_block(vcpu); |
f656ce01 | 5419 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
a8eeb04a | 5420 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
09cec754 GN |
5421 | { |
5422 | switch(vcpu->arch.mp_state) { | |
5423 | case KVM_MP_STATE_HALTED: | |
d7690175 | 5424 | vcpu->arch.mp_state = |
09cec754 GN |
5425 | KVM_MP_STATE_RUNNABLE; |
5426 | case KVM_MP_STATE_RUNNABLE: | |
af585b92 | 5427 | vcpu->arch.apf.halted = false; |
09cec754 GN |
5428 | break; |
5429 | case KVM_MP_STATE_SIPI_RECEIVED: | |
5430 | default: | |
5431 | r = -EINTR; | |
5432 | break; | |
5433 | } | |
5434 | } | |
d7690175 MT |
5435 | } |
5436 | ||
09cec754 GN |
5437 | if (r <= 0) |
5438 | break; | |
5439 | ||
5440 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
5441 | if (kvm_cpu_has_pending_timer(vcpu)) | |
5442 | kvm_inject_pending_timer_irqs(vcpu); | |
5443 | ||
851ba692 | 5444 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 5445 | r = -EINTR; |
851ba692 | 5446 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5447 | ++vcpu->stat.request_irq_exits; |
5448 | } | |
af585b92 GN |
5449 | |
5450 | kvm_check_async_pf_completion(vcpu); | |
5451 | ||
09cec754 GN |
5452 | if (signal_pending(current)) { |
5453 | r = -EINTR; | |
851ba692 | 5454 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5455 | ++vcpu->stat.signal_exits; |
5456 | } | |
5457 | if (need_resched()) { | |
f656ce01 | 5458 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 5459 | kvm_resched(vcpu); |
f656ce01 | 5460 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 5461 | } |
b6c7a5dc HB |
5462 | } |
5463 | ||
f656ce01 | 5464 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc | 5465 | |
b93463aa AK |
5466 | vapic_exit(vcpu); |
5467 | ||
b6c7a5dc HB |
5468 | return r; |
5469 | } | |
5470 | ||
f78146b0 AK |
5471 | /* |
5472 | * Implements the following, as a state machine: | |
5473 | * | |
5474 | * read: | |
5475 | * for each fragment | |
5476 | * write gpa, len | |
5477 | * exit | |
5478 | * copy data | |
5479 | * execute insn | |
5480 | * | |
5481 | * write: | |
5482 | * for each fragment | |
5483 | * write gpa, len | |
5484 | * copy data | |
5485 | * exit | |
5486 | */ | |
5287f194 AK |
5487 | static int complete_mmio(struct kvm_vcpu *vcpu) |
5488 | { | |
5489 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 5490 | struct kvm_mmio_fragment *frag; |
5287f194 AK |
5491 | int r; |
5492 | ||
5493 | if (!(vcpu->arch.pio.count || vcpu->mmio_needed)) | |
5494 | return 1; | |
5495 | ||
5496 | if (vcpu->mmio_needed) { | |
f78146b0 AK |
5497 | /* Complete previous fragment */ |
5498 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++]; | |
cef4dea0 | 5499 | if (!vcpu->mmio_is_write) |
f78146b0 AK |
5500 | memcpy(frag->data, run->mmio.data, frag->len); |
5501 | if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) { | |
5502 | vcpu->mmio_needed = 0; | |
5503 | if (vcpu->mmio_is_write) | |
5504 | return 1; | |
5505 | vcpu->mmio_read_completed = 1; | |
5506 | goto done; | |
cef4dea0 | 5507 | } |
f78146b0 AK |
5508 | /* Initiate next fragment */ |
5509 | ++frag; | |
5510 | run->exit_reason = KVM_EXIT_MMIO; | |
5511 | run->mmio.phys_addr = frag->gpa; | |
cef4dea0 | 5512 | if (vcpu->mmio_is_write) |
f78146b0 AK |
5513 | memcpy(run->mmio.data, frag->data, frag->len); |
5514 | run->mmio.len = frag->len; | |
5515 | run->mmio.is_write = vcpu->mmio_is_write; | |
5516 | return 0; | |
5517 | ||
5287f194 | 5518 | } |
f78146b0 | 5519 | done: |
5287f194 AK |
5520 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
5521 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
5522 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
5523 | if (r != EMULATE_DONE) | |
5524 | return 0; | |
5525 | return 1; | |
5526 | } | |
5527 | ||
b6c7a5dc HB |
5528 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
5529 | { | |
5530 | int r; | |
5531 | sigset_t sigsaved; | |
5532 | ||
e5c30142 AK |
5533 | if (!tsk_used_math(current) && init_fpu(current)) |
5534 | return -ENOMEM; | |
5535 | ||
ac9f6dc0 AK |
5536 | if (vcpu->sigset_active) |
5537 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
5538 | ||
a4535290 | 5539 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 5540 | kvm_vcpu_block(vcpu); |
d7690175 | 5541 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
5542 | r = -EAGAIN; |
5543 | goto out; | |
b6c7a5dc HB |
5544 | } |
5545 | ||
b6c7a5dc | 5546 | /* re-sync apic's tpr */ |
eea1cff9 AP |
5547 | if (!irqchip_in_kernel(vcpu->kvm)) { |
5548 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
5549 | r = -EINVAL; | |
5550 | goto out; | |
5551 | } | |
5552 | } | |
b6c7a5dc | 5553 | |
5287f194 AK |
5554 | r = complete_mmio(vcpu); |
5555 | if (r <= 0) | |
5556 | goto out; | |
5557 | ||
851ba692 | 5558 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
5559 | |
5560 | out: | |
f1d86e46 | 5561 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
5562 | if (vcpu->sigset_active) |
5563 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
5564 | ||
b6c7a5dc HB |
5565 | return r; |
5566 | } | |
5567 | ||
5568 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5569 | { | |
7ae441ea GN |
5570 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
5571 | /* | |
5572 | * We are here if userspace calls get_regs() in the middle of | |
5573 | * instruction emulation. Registers state needs to be copied | |
5574 | * back from emulation context to vcpu. Usrapace shouldn't do | |
5575 | * that usually, but some bad designed PV devices (vmware | |
5576 | * backdoor interface) need this to work | |
5577 | */ | |
9dac77fa AK |
5578 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
5579 | memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs); | |
7ae441ea GN |
5580 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
5581 | } | |
5fdbf976 MT |
5582 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5583 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5584 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5585 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5586 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
5587 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
5588 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
5589 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 5590 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5591 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
5592 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
5593 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
5594 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
5595 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
5596 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
5597 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
5598 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
5599 | #endif |
5600 | ||
5fdbf976 | 5601 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 5602 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 5603 | |
b6c7a5dc HB |
5604 | return 0; |
5605 | } | |
5606 | ||
5607 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5608 | { | |
7ae441ea GN |
5609 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
5610 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
5611 | ||
5fdbf976 MT |
5612 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
5613 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
5614 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
5615 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
5616 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
5617 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
5618 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
5619 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 5620 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5621 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
5622 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
5623 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
5624 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
5625 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
5626 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
5627 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
5628 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
5629 | #endif |
5630 | ||
5fdbf976 | 5631 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 5632 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 5633 | |
b4f14abd JK |
5634 | vcpu->arch.exception.pending = false; |
5635 | ||
3842d135 AK |
5636 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5637 | ||
b6c7a5dc HB |
5638 | return 0; |
5639 | } | |
5640 | ||
b6c7a5dc HB |
5641 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
5642 | { | |
5643 | struct kvm_segment cs; | |
5644 | ||
3e6e0aab | 5645 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
5646 | *db = cs.db; |
5647 | *l = cs.l; | |
5648 | } | |
5649 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
5650 | ||
5651 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
5652 | struct kvm_sregs *sregs) | |
5653 | { | |
89a27f4d | 5654 | struct desc_ptr dt; |
b6c7a5dc | 5655 | |
3e6e0aab GT |
5656 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5657 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5658 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5659 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5660 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5661 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5662 | |
3e6e0aab GT |
5663 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5664 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
5665 | |
5666 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
5667 | sregs->idt.limit = dt.size; |
5668 | sregs->idt.base = dt.address; | |
b6c7a5dc | 5669 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
5670 | sregs->gdt.limit = dt.size; |
5671 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 5672 | |
4d4ec087 | 5673 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 5674 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 5675 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 5676 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 5677 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 5678 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
5679 | sregs->apic_base = kvm_get_apic_base(vcpu); |
5680 | ||
923c61bb | 5681 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 5682 | |
36752c9b | 5683 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
5684 | set_bit(vcpu->arch.interrupt.nr, |
5685 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 5686 | |
b6c7a5dc HB |
5687 | return 0; |
5688 | } | |
5689 | ||
62d9f0db MT |
5690 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
5691 | struct kvm_mp_state *mp_state) | |
5692 | { | |
62d9f0db | 5693 | mp_state->mp_state = vcpu->arch.mp_state; |
62d9f0db MT |
5694 | return 0; |
5695 | } | |
5696 | ||
5697 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
5698 | struct kvm_mp_state *mp_state) | |
5699 | { | |
62d9f0db | 5700 | vcpu->arch.mp_state = mp_state->mp_state; |
3842d135 | 5701 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
5702 | return 0; |
5703 | } | |
5704 | ||
7f3d35fd KW |
5705 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
5706 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 5707 | { |
9d74191a | 5708 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 5709 | int ret; |
e01c2426 | 5710 | |
8ec4722d | 5711 | init_emulate_ctxt(vcpu); |
c697518a | 5712 | |
7f3d35fd | 5713 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 5714 | has_error_code, error_code); |
c697518a | 5715 | |
c697518a | 5716 | if (ret) |
19d04437 | 5717 | return EMULATE_FAIL; |
37817f29 | 5718 | |
9dac77fa | 5719 | memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs); |
9d74191a TY |
5720 | kvm_rip_write(vcpu, ctxt->eip); |
5721 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 5722 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 5723 | return EMULATE_DONE; |
37817f29 IE |
5724 | } |
5725 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
5726 | ||
b6c7a5dc HB |
5727 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
5728 | struct kvm_sregs *sregs) | |
5729 | { | |
5730 | int mmu_reset_needed = 0; | |
63f42e02 | 5731 | int pending_vec, max_bits, idx; |
89a27f4d | 5732 | struct desc_ptr dt; |
b6c7a5dc | 5733 | |
89a27f4d GN |
5734 | dt.size = sregs->idt.limit; |
5735 | dt.address = sregs->idt.base; | |
b6c7a5dc | 5736 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
5737 | dt.size = sregs->gdt.limit; |
5738 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
5739 | kvm_x86_ops->set_gdt(vcpu, &dt); |
5740 | ||
ad312c7c | 5741 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 5742 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 5743 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 5744 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 5745 | |
2d3ad1f4 | 5746 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 5747 | |
f6801dff | 5748 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 5749 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
5750 | kvm_set_apic_base(vcpu, sregs->apic_base); |
5751 | ||
4d4ec087 | 5752 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 5753 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 5754 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 5755 | |
fc78f519 | 5756 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 5757 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c | 5758 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
00b27a3e | 5759 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
5760 | |
5761 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 5762 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 5763 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
5764 | mmu_reset_needed = 1; |
5765 | } | |
63f42e02 | 5766 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
5767 | |
5768 | if (mmu_reset_needed) | |
5769 | kvm_mmu_reset_context(vcpu); | |
5770 | ||
923c61bb GN |
5771 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
5772 | pending_vec = find_first_bit( | |
5773 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
5774 | if (pending_vec < max_bits) { | |
66fd3f7f | 5775 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 5776 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
5777 | } |
5778 | ||
3e6e0aab GT |
5779 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5780 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5781 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5782 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5783 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5784 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5785 | |
3e6e0aab GT |
5786 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5787 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 5788 | |
5f0269f5 ME |
5789 | update_cr8_intercept(vcpu); |
5790 | ||
9c3e4aab | 5791 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 5792 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 5793 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 5794 | !is_protmode(vcpu)) |
9c3e4aab MT |
5795 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
5796 | ||
3842d135 AK |
5797 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5798 | ||
b6c7a5dc HB |
5799 | return 0; |
5800 | } | |
5801 | ||
d0bfb940 JK |
5802 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
5803 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 5804 | { |
355be0b9 | 5805 | unsigned long rflags; |
ae675ef0 | 5806 | int i, r; |
b6c7a5dc | 5807 | |
4f926bf2 JK |
5808 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
5809 | r = -EBUSY; | |
5810 | if (vcpu->arch.exception.pending) | |
2122ff5e | 5811 | goto out; |
4f926bf2 JK |
5812 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
5813 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5814 | else | |
5815 | kvm_queue_exception(vcpu, BP_VECTOR); | |
5816 | } | |
5817 | ||
91586a3b JK |
5818 | /* |
5819 | * Read rflags as long as potentially injected trace flags are still | |
5820 | * filtered out. | |
5821 | */ | |
5822 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
5823 | |
5824 | vcpu->guest_debug = dbg->control; | |
5825 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
5826 | vcpu->guest_debug = 0; | |
5827 | ||
5828 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
5829 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
5830 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
5831 | vcpu->arch.switch_db_regs = | |
5832 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
5833 | } else { | |
5834 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
5835 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
5836 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
5837 | } | |
5838 | ||
f92653ee JK |
5839 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
5840 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
5841 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 5842 | |
91586a3b JK |
5843 | /* |
5844 | * Trigger an rflags update that will inject or remove the trace | |
5845 | * flags. | |
5846 | */ | |
5847 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 5848 | |
355be0b9 | 5849 | kvm_x86_ops->set_guest_debug(vcpu, dbg); |
b6c7a5dc | 5850 | |
4f926bf2 | 5851 | r = 0; |
d0bfb940 | 5852 | |
2122ff5e | 5853 | out: |
b6c7a5dc HB |
5854 | |
5855 | return r; | |
5856 | } | |
5857 | ||
8b006791 ZX |
5858 | /* |
5859 | * Translate a guest virtual address to a guest physical address. | |
5860 | */ | |
5861 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
5862 | struct kvm_translation *tr) | |
5863 | { | |
5864 | unsigned long vaddr = tr->linear_address; | |
5865 | gpa_t gpa; | |
f656ce01 | 5866 | int idx; |
8b006791 | 5867 | |
f656ce01 | 5868 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 5869 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 5870 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
5871 | tr->physical_address = gpa; |
5872 | tr->valid = gpa != UNMAPPED_GVA; | |
5873 | tr->writeable = 1; | |
5874 | tr->usermode = 0; | |
8b006791 ZX |
5875 | |
5876 | return 0; | |
5877 | } | |
5878 | ||
d0752060 HB |
5879 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
5880 | { | |
98918833 SY |
5881 | struct i387_fxsave_struct *fxsave = |
5882 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5883 | |
d0752060 HB |
5884 | memcpy(fpu->fpr, fxsave->st_space, 128); |
5885 | fpu->fcw = fxsave->cwd; | |
5886 | fpu->fsw = fxsave->swd; | |
5887 | fpu->ftwx = fxsave->twd; | |
5888 | fpu->last_opcode = fxsave->fop; | |
5889 | fpu->last_ip = fxsave->rip; | |
5890 | fpu->last_dp = fxsave->rdp; | |
5891 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
5892 | ||
d0752060 HB |
5893 | return 0; |
5894 | } | |
5895 | ||
5896 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
5897 | { | |
98918833 SY |
5898 | struct i387_fxsave_struct *fxsave = |
5899 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5900 | |
d0752060 HB |
5901 | memcpy(fxsave->st_space, fpu->fpr, 128); |
5902 | fxsave->cwd = fpu->fcw; | |
5903 | fxsave->swd = fpu->fsw; | |
5904 | fxsave->twd = fpu->ftwx; | |
5905 | fxsave->fop = fpu->last_opcode; | |
5906 | fxsave->rip = fpu->last_ip; | |
5907 | fxsave->rdp = fpu->last_dp; | |
5908 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
5909 | ||
d0752060 HB |
5910 | return 0; |
5911 | } | |
5912 | ||
10ab25cd | 5913 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 5914 | { |
10ab25cd JK |
5915 | int err; |
5916 | ||
5917 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
5918 | if (err) | |
5919 | return err; | |
5920 | ||
98918833 | 5921 | fpu_finit(&vcpu->arch.guest_fpu); |
d0752060 | 5922 | |
2acf923e DC |
5923 | /* |
5924 | * Ensure guest xcr0 is valid for loading | |
5925 | */ | |
5926 | vcpu->arch.xcr0 = XSTATE_FP; | |
5927 | ||
ad312c7c | 5928 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
5929 | |
5930 | return 0; | |
d0752060 HB |
5931 | } |
5932 | EXPORT_SYMBOL_GPL(fx_init); | |
5933 | ||
98918833 SY |
5934 | static void fx_free(struct kvm_vcpu *vcpu) |
5935 | { | |
5936 | fpu_free(&vcpu->arch.guest_fpu); | |
5937 | } | |
5938 | ||
d0752060 HB |
5939 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
5940 | { | |
2608d7a1 | 5941 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
5942 | return; |
5943 | ||
2acf923e DC |
5944 | /* |
5945 | * Restore all possible states in the guest, | |
5946 | * and assume host would use all available bits. | |
5947 | * Guest xcr0 would be loaded later. | |
5948 | */ | |
5949 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 5950 | vcpu->guest_fpu_loaded = 1; |
7cf30855 | 5951 | unlazy_fpu(current); |
98918833 | 5952 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 5953 | trace_kvm_fpu(1); |
d0752060 | 5954 | } |
d0752060 HB |
5955 | |
5956 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
5957 | { | |
2acf923e DC |
5958 | kvm_put_guest_xcr0(vcpu); |
5959 | ||
d0752060 HB |
5960 | if (!vcpu->guest_fpu_loaded) |
5961 | return; | |
5962 | ||
5963 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 5964 | fpu_save_init(&vcpu->arch.guest_fpu); |
f096ed85 | 5965 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 5966 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 5967 | trace_kvm_fpu(0); |
d0752060 | 5968 | } |
e9b11c17 ZX |
5969 | |
5970 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
5971 | { | |
12f9a48f | 5972 | kvmclock_reset(vcpu); |
7f1ea208 | 5973 | |
f5f48ee1 | 5974 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 5975 | fx_free(vcpu); |
e9b11c17 ZX |
5976 | kvm_x86_ops->vcpu_free(vcpu); |
5977 | } | |
5978 | ||
5979 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
5980 | unsigned int id) | |
5981 | { | |
6755bae8 ZA |
5982 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
5983 | printk_once(KERN_WARNING | |
5984 | "kvm: SMP vm created on host with unstable TSC; " | |
5985 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
5986 | return kvm_x86_ops->vcpu_create(kvm, id); |
5987 | } | |
e9b11c17 | 5988 | |
26e5215f AK |
5989 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
5990 | { | |
5991 | int r; | |
e9b11c17 | 5992 | |
0bed3b56 | 5993 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
5994 | vcpu_load(vcpu); |
5995 | r = kvm_arch_vcpu_reset(vcpu); | |
5996 | if (r == 0) | |
5997 | r = kvm_mmu_setup(vcpu); | |
5998 | vcpu_put(vcpu); | |
e9b11c17 | 5999 | |
26e5215f | 6000 | return r; |
e9b11c17 ZX |
6001 | } |
6002 | ||
d40ccc62 | 6003 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 6004 | { |
344d9588 GN |
6005 | vcpu->arch.apf.msr_val = 0; |
6006 | ||
e9b11c17 ZX |
6007 | vcpu_load(vcpu); |
6008 | kvm_mmu_unload(vcpu); | |
6009 | vcpu_put(vcpu); | |
6010 | ||
98918833 | 6011 | fx_free(vcpu); |
e9b11c17 ZX |
6012 | kvm_x86_ops->vcpu_free(vcpu); |
6013 | } | |
6014 | ||
6015 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
6016 | { | |
7460fb4a AK |
6017 | atomic_set(&vcpu->arch.nmi_queued, 0); |
6018 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 JK |
6019 | vcpu->arch.nmi_injected = false; |
6020 | ||
42dbaa5a JK |
6021 | vcpu->arch.switch_db_regs = 0; |
6022 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
6023 | vcpu->arch.dr6 = DR6_FIXED_1; | |
6024 | vcpu->arch.dr7 = DR7_FIXED_1; | |
6025 | ||
3842d135 | 6026 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 6027 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 6028 | vcpu->arch.st.msr_val = 0; |
3842d135 | 6029 | |
12f9a48f GC |
6030 | kvmclock_reset(vcpu); |
6031 | ||
af585b92 GN |
6032 | kvm_clear_async_pf_completion_queue(vcpu); |
6033 | kvm_async_pf_hash_reset(vcpu); | |
6034 | vcpu->arch.apf.halted = false; | |
3842d135 | 6035 | |
f5132b01 GN |
6036 | kvm_pmu_reset(vcpu); |
6037 | ||
e9b11c17 ZX |
6038 | return kvm_x86_ops->vcpu_reset(vcpu); |
6039 | } | |
6040 | ||
10474ae8 | 6041 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 6042 | { |
ca84d1a2 ZA |
6043 | struct kvm *kvm; |
6044 | struct kvm_vcpu *vcpu; | |
6045 | int i; | |
0dd6a6ed ZA |
6046 | int ret; |
6047 | u64 local_tsc; | |
6048 | u64 max_tsc = 0; | |
6049 | bool stable, backwards_tsc = false; | |
18863bdd AK |
6050 | |
6051 | kvm_shared_msr_cpu_online(); | |
0dd6a6ed ZA |
6052 | ret = kvm_x86_ops->hardware_enable(garbage); |
6053 | if (ret != 0) | |
6054 | return ret; | |
6055 | ||
6056 | local_tsc = native_read_tsc(); | |
6057 | stable = !check_tsc_unstable(); | |
6058 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6059 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6060 | if (!stable && vcpu->cpu == smp_processor_id()) | |
6061 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
6062 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { | |
6063 | backwards_tsc = true; | |
6064 | if (vcpu->arch.last_host_tsc > max_tsc) | |
6065 | max_tsc = vcpu->arch.last_host_tsc; | |
6066 | } | |
6067 | } | |
6068 | } | |
6069 | ||
6070 | /* | |
6071 | * Sometimes, even reliable TSCs go backwards. This happens on | |
6072 | * platforms that reset TSC during suspend or hibernate actions, but | |
6073 | * maintain synchronization. We must compensate. Fortunately, we can | |
6074 | * detect that condition here, which happens early in CPU bringup, | |
6075 | * before any KVM threads can be running. Unfortunately, we can't | |
6076 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
6077 | * enough into CPU bringup that we know how much real time has actually | |
6078 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
6079 | * variables that haven't been updated yet. | |
6080 | * | |
6081 | * So we simply find the maximum observed TSC above, then record the | |
6082 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
6083 | * the adjustment will be applied. Note that we accumulate | |
6084 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
6085 | * gets a chance to run again. In the event that no KVM threads get a | |
6086 | * chance to run, we will miss the entire elapsed period, as we'll have | |
6087 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
6088 | * loose cycle time. This isn't too big a deal, since the loss will be | |
6089 | * uniform across all VCPUs (not to mention the scenario is extremely | |
6090 | * unlikely). It is possible that a second hibernate recovery happens | |
6091 | * much faster than a first, causing the observed TSC here to be | |
6092 | * smaller; this would require additional padding adjustment, which is | |
6093 | * why we set last_host_tsc to the local tsc observed here. | |
6094 | * | |
6095 | * N.B. - this code below runs only on platforms with reliable TSC, | |
6096 | * as that is the only way backwards_tsc is set above. Also note | |
6097 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
6098 | * have the same delta_cyc adjustment applied if backwards_tsc | |
6099 | * is detected. Note further, this adjustment is only done once, | |
6100 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
6101 | * called multiple times (one for each physical CPU bringup). | |
6102 | * | |
6103 | * Platforms with unnreliable TSCs don't have to deal with this, they | |
6104 | * will be compensated by the logic in vcpu_load, which sets the TSC to | |
6105 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
6106 | * guarantee that they stay in perfect synchronization. | |
6107 | */ | |
6108 | if (backwards_tsc) { | |
6109 | u64 delta_cyc = max_tsc - local_tsc; | |
6110 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6111 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6112 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
6113 | vcpu->arch.last_host_tsc = local_tsc; | |
6114 | } | |
6115 | ||
6116 | /* | |
6117 | * We have to disable TSC offset matching.. if you were | |
6118 | * booting a VM while issuing an S4 host suspend.... | |
6119 | * you may have some problem. Solving this issue is | |
6120 | * left as an exercise to the reader. | |
6121 | */ | |
6122 | kvm->arch.last_tsc_nsec = 0; | |
6123 | kvm->arch.last_tsc_write = 0; | |
6124 | } | |
6125 | ||
6126 | } | |
6127 | return 0; | |
e9b11c17 ZX |
6128 | } |
6129 | ||
6130 | void kvm_arch_hardware_disable(void *garbage) | |
6131 | { | |
6132 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 6133 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
6134 | } |
6135 | ||
6136 | int kvm_arch_hardware_setup(void) | |
6137 | { | |
6138 | return kvm_x86_ops->hardware_setup(); | |
6139 | } | |
6140 | ||
6141 | void kvm_arch_hardware_unsetup(void) | |
6142 | { | |
6143 | kvm_x86_ops->hardware_unsetup(); | |
6144 | } | |
6145 | ||
6146 | void kvm_arch_check_processor_compat(void *rtn) | |
6147 | { | |
6148 | kvm_x86_ops->check_processor_compatibility(rtn); | |
6149 | } | |
6150 | ||
3e515705 AK |
6151 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) |
6152 | { | |
6153 | return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); | |
6154 | } | |
6155 | ||
e9b11c17 ZX |
6156 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
6157 | { | |
6158 | struct page *page; | |
6159 | struct kvm *kvm; | |
6160 | int r; | |
6161 | ||
6162 | BUG_ON(vcpu->kvm == NULL); | |
6163 | kvm = vcpu->kvm; | |
6164 | ||
9aabc88f | 6165 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
c5af89b6 | 6166 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 6167 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 6168 | else |
a4535290 | 6169 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
6170 | |
6171 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
6172 | if (!page) { | |
6173 | r = -ENOMEM; | |
6174 | goto fail; | |
6175 | } | |
ad312c7c | 6176 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 6177 | |
cc578287 | 6178 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 6179 | |
e9b11c17 ZX |
6180 | r = kvm_mmu_create(vcpu); |
6181 | if (r < 0) | |
6182 | goto fail_free_pio_data; | |
6183 | ||
6184 | if (irqchip_in_kernel(kvm)) { | |
6185 | r = kvm_create_lapic(vcpu); | |
6186 | if (r < 0) | |
6187 | goto fail_mmu_destroy; | |
6188 | } | |
6189 | ||
890ca9ae HY |
6190 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
6191 | GFP_KERNEL); | |
6192 | if (!vcpu->arch.mce_banks) { | |
6193 | r = -ENOMEM; | |
443c39bc | 6194 | goto fail_free_lapic; |
890ca9ae HY |
6195 | } |
6196 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
6197 | ||
f5f48ee1 SY |
6198 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) |
6199 | goto fail_free_mce_banks; | |
6200 | ||
af585b92 | 6201 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 6202 | kvm_pmu_init(vcpu); |
af585b92 | 6203 | |
e9b11c17 | 6204 | return 0; |
f5f48ee1 SY |
6205 | fail_free_mce_banks: |
6206 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
6207 | fail_free_lapic: |
6208 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
6209 | fail_mmu_destroy: |
6210 | kvm_mmu_destroy(vcpu); | |
6211 | fail_free_pio_data: | |
ad312c7c | 6212 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
6213 | fail: |
6214 | return r; | |
6215 | } | |
6216 | ||
6217 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
6218 | { | |
f656ce01 MT |
6219 | int idx; |
6220 | ||
f5132b01 | 6221 | kvm_pmu_destroy(vcpu); |
36cb93fd | 6222 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 6223 | kvm_free_lapic(vcpu); |
f656ce01 | 6224 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 6225 | kvm_mmu_destroy(vcpu); |
f656ce01 | 6226 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 6227 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 6228 | } |
d19a9cd2 | 6229 | |
e08b9637 | 6230 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 6231 | { |
e08b9637 CO |
6232 | if (type) |
6233 | return -EINVAL; | |
6234 | ||
f05e70ac | 6235 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 6236 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 6237 | |
5550af4d SY |
6238 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
6239 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
6240 | ||
038f8c11 | 6241 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
53f658b3 | 6242 | |
d89f5eff | 6243 | return 0; |
d19a9cd2 ZX |
6244 | } |
6245 | ||
6246 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
6247 | { | |
6248 | vcpu_load(vcpu); | |
6249 | kvm_mmu_unload(vcpu); | |
6250 | vcpu_put(vcpu); | |
6251 | } | |
6252 | ||
6253 | static void kvm_free_vcpus(struct kvm *kvm) | |
6254 | { | |
6255 | unsigned int i; | |
988a2cae | 6256 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
6257 | |
6258 | /* | |
6259 | * Unpin any mmu pages first. | |
6260 | */ | |
af585b92 GN |
6261 | kvm_for_each_vcpu(i, vcpu, kvm) { |
6262 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 6263 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 6264 | } |
988a2cae GN |
6265 | kvm_for_each_vcpu(i, vcpu, kvm) |
6266 | kvm_arch_vcpu_free(vcpu); | |
6267 | ||
6268 | mutex_lock(&kvm->lock); | |
6269 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
6270 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 6271 | |
988a2cae GN |
6272 | atomic_set(&kvm->online_vcpus, 0); |
6273 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
6274 | } |
6275 | ||
ad8ba2cd SY |
6276 | void kvm_arch_sync_events(struct kvm *kvm) |
6277 | { | |
ba4cef31 | 6278 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 6279 | kvm_free_pit(kvm); |
ad8ba2cd SY |
6280 | } |
6281 | ||
d19a9cd2 ZX |
6282 | void kvm_arch_destroy_vm(struct kvm *kvm) |
6283 | { | |
6eb55818 | 6284 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
6285 | kfree(kvm->arch.vpic); |
6286 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 6287 | kvm_free_vcpus(kvm); |
3d45830c AK |
6288 | if (kvm->arch.apic_access_page) |
6289 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
6290 | if (kvm->arch.ept_identity_pagetable) |
6291 | put_page(kvm->arch.ept_identity_pagetable); | |
d19a9cd2 | 6292 | } |
0de10343 | 6293 | |
db3fe4eb TY |
6294 | void kvm_arch_free_memslot(struct kvm_memory_slot *free, |
6295 | struct kvm_memory_slot *dont) | |
6296 | { | |
6297 | int i; | |
6298 | ||
6299 | for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) { | |
6300 | if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) { | |
c1a7b32a | 6301 | kvm_kvfree(free->arch.lpage_info[i]); |
db3fe4eb TY |
6302 | free->arch.lpage_info[i] = NULL; |
6303 | } | |
6304 | } | |
6305 | } | |
6306 | ||
6307 | int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages) | |
6308 | { | |
6309 | int i; | |
6310 | ||
6311 | for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) { | |
6312 | unsigned long ugfn; | |
6313 | int lpages; | |
6314 | int level = i + 2; | |
6315 | ||
6316 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
6317 | slot->base_gfn, level) + 1; | |
6318 | ||
6319 | slot->arch.lpage_info[i] = | |
c1a7b32a | 6320 | kvm_kvzalloc(lpages * sizeof(*slot->arch.lpage_info[i])); |
db3fe4eb TY |
6321 | if (!slot->arch.lpage_info[i]) |
6322 | goto out_free; | |
6323 | ||
6324 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
6325 | slot->arch.lpage_info[i][0].write_count = 1; | |
6326 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
6327 | slot->arch.lpage_info[i][lpages - 1].write_count = 1; | |
6328 | ugfn = slot->userspace_addr >> PAGE_SHIFT; | |
6329 | /* | |
6330 | * If the gfn and userspace address are not aligned wrt each | |
6331 | * other, or if explicitly asked to, disable large page | |
6332 | * support for this slot | |
6333 | */ | |
6334 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
6335 | !kvm_largepages_enabled()) { | |
6336 | unsigned long j; | |
6337 | ||
6338 | for (j = 0; j < lpages; ++j) | |
6339 | slot->arch.lpage_info[i][j].write_count = 1; | |
6340 | } | |
6341 | } | |
6342 | ||
6343 | return 0; | |
6344 | ||
6345 | out_free: | |
6346 | for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) { | |
9e40b67b | 6347 | kvm_kvfree(slot->arch.lpage_info[i]); |
db3fe4eb TY |
6348 | slot->arch.lpage_info[i] = NULL; |
6349 | } | |
6350 | return -ENOMEM; | |
6351 | } | |
6352 | ||
f7784b8e MT |
6353 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
6354 | struct kvm_memory_slot *memslot, | |
0de10343 | 6355 | struct kvm_memory_slot old, |
f7784b8e | 6356 | struct kvm_userspace_memory_region *mem, |
0de10343 ZX |
6357 | int user_alloc) |
6358 | { | |
f7784b8e | 6359 | int npages = memslot->npages; |
7ac77099 AK |
6360 | int map_flags = MAP_PRIVATE | MAP_ANONYMOUS; |
6361 | ||
6362 | /* Prevent internal slot pages from being moved by fork()/COW. */ | |
6363 | if (memslot->id >= KVM_MEMORY_SLOTS) | |
6364 | map_flags = MAP_SHARED | MAP_ANONYMOUS; | |
0de10343 ZX |
6365 | |
6366 | /*To keep backward compatibility with older userspace, | |
6367 | *x86 needs to hanlde !user_alloc case. | |
6368 | */ | |
6369 | if (!user_alloc) { | |
6370 | if (npages && !old.rmap) { | |
604b38ac AA |
6371 | unsigned long userspace_addr; |
6372 | ||
6be5ceb0 | 6373 | userspace_addr = vm_mmap(NULL, 0, |
604b38ac AA |
6374 | npages * PAGE_SIZE, |
6375 | PROT_READ | PROT_WRITE, | |
7ac77099 | 6376 | map_flags, |
604b38ac | 6377 | 0); |
0de10343 | 6378 | |
604b38ac AA |
6379 | if (IS_ERR((void *)userspace_addr)) |
6380 | return PTR_ERR((void *)userspace_addr); | |
6381 | ||
604b38ac | 6382 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
6383 | } |
6384 | } | |
6385 | ||
f7784b8e MT |
6386 | |
6387 | return 0; | |
6388 | } | |
6389 | ||
6390 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
6391 | struct kvm_userspace_memory_region *mem, | |
6392 | struct kvm_memory_slot old, | |
6393 | int user_alloc) | |
6394 | { | |
6395 | ||
48c0e4e9 | 6396 | int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT; |
f7784b8e MT |
6397 | |
6398 | if (!user_alloc && !old.user_alloc && old.rmap && !npages) { | |
6399 | int ret; | |
6400 | ||
bfce281c | 6401 | ret = vm_munmap(old.userspace_addr, |
f7784b8e | 6402 | old.npages * PAGE_SIZE); |
f7784b8e MT |
6403 | if (ret < 0) |
6404 | printk(KERN_WARNING | |
6405 | "kvm_vm_ioctl_set_memory_region: " | |
6406 | "failed to munmap memory\n"); | |
6407 | } | |
6408 | ||
48c0e4e9 XG |
6409 | if (!kvm->arch.n_requested_mmu_pages) |
6410 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
6411 | ||
7c8a83b7 | 6412 | spin_lock(&kvm->mmu_lock); |
48c0e4e9 | 6413 | if (nr_mmu_pages) |
0de10343 | 6414 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
0de10343 | 6415 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); |
7c8a83b7 | 6416 | spin_unlock(&kvm->mmu_lock); |
0de10343 | 6417 | } |
1d737c8a | 6418 | |
34d4cb8f MT |
6419 | void kvm_arch_flush_shadow(struct kvm *kvm) |
6420 | { | |
6421 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 6422 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
6423 | } |
6424 | ||
1d737c8a ZX |
6425 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
6426 | { | |
af585b92 GN |
6427 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6428 | !vcpu->arch.apf.halted) | |
6429 | || !list_empty_careful(&vcpu->async_pf.done) | |
a1b37100 | 6430 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
7460fb4a | 6431 | || atomic_read(&vcpu->arch.nmi_queued) || |
a1b37100 GN |
6432 | (kvm_arch_interrupt_allowed(vcpu) && |
6433 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 6434 | } |
5736199a | 6435 | |
b6d33834 | 6436 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 6437 | { |
b6d33834 | 6438 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 6439 | } |
78646121 GN |
6440 | |
6441 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
6442 | { | |
6443 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
6444 | } | |
229456fc | 6445 | |
f92653ee JK |
6446 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
6447 | { | |
6448 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
6449 | get_segment_base(vcpu, VCPU_SREG_CS); | |
6450 | ||
6451 | return current_rip == linear_rip; | |
6452 | } | |
6453 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
6454 | ||
94fe45da JK |
6455 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
6456 | { | |
6457 | unsigned long rflags; | |
6458 | ||
6459 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
6460 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 6461 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
6462 | return rflags; |
6463 | } | |
6464 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
6465 | ||
6466 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
6467 | { | |
6468 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 6469 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 6470 | rflags |= X86_EFLAGS_TF; |
94fe45da | 6471 | kvm_x86_ops->set_rflags(vcpu, rflags); |
3842d135 | 6472 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
6473 | } |
6474 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
6475 | ||
56028d08 GN |
6476 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
6477 | { | |
6478 | int r; | |
6479 | ||
fb67e14f | 6480 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
c4806acd | 6481 | is_error_page(work->page)) |
56028d08 GN |
6482 | return; |
6483 | ||
6484 | r = kvm_mmu_reload(vcpu); | |
6485 | if (unlikely(r)) | |
6486 | return; | |
6487 | ||
fb67e14f XG |
6488 | if (!vcpu->arch.mmu.direct_map && |
6489 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
6490 | return; | |
6491 | ||
56028d08 GN |
6492 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
6493 | } | |
6494 | ||
af585b92 GN |
6495 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
6496 | { | |
6497 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
6498 | } | |
6499 | ||
6500 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
6501 | { | |
6502 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
6503 | } | |
6504 | ||
6505 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6506 | { | |
6507 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6508 | ||
6509 | while (vcpu->arch.apf.gfns[key] != ~0) | |
6510 | key = kvm_async_pf_next_probe(key); | |
6511 | ||
6512 | vcpu->arch.apf.gfns[key] = gfn; | |
6513 | } | |
6514 | ||
6515 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6516 | { | |
6517 | int i; | |
6518 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6519 | ||
6520 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
6521 | (vcpu->arch.apf.gfns[key] != gfn && |
6522 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
6523 | key = kvm_async_pf_next_probe(key); |
6524 | ||
6525 | return key; | |
6526 | } | |
6527 | ||
6528 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6529 | { | |
6530 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
6531 | } | |
6532 | ||
6533 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6534 | { | |
6535 | u32 i, j, k; | |
6536 | ||
6537 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
6538 | while (true) { | |
6539 | vcpu->arch.apf.gfns[i] = ~0; | |
6540 | do { | |
6541 | j = kvm_async_pf_next_probe(j); | |
6542 | if (vcpu->arch.apf.gfns[j] == ~0) | |
6543 | return; | |
6544 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
6545 | /* | |
6546 | * k lies cyclically in ]i,j] | |
6547 | * | i.k.j | | |
6548 | * |....j i.k.| or |.k..j i...| | |
6549 | */ | |
6550 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
6551 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
6552 | i = j; | |
6553 | } | |
6554 | } | |
6555 | ||
7c90705b GN |
6556 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
6557 | { | |
6558 | ||
6559 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
6560 | sizeof(val)); | |
6561 | } | |
6562 | ||
af585b92 GN |
6563 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
6564 | struct kvm_async_pf *work) | |
6565 | { | |
6389ee94 AK |
6566 | struct x86_exception fault; |
6567 | ||
7c90705b | 6568 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 6569 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
6570 | |
6571 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
6572 | (vcpu->arch.apf.send_user_only && |
6573 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
6574 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
6575 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
6576 | fault.vector = PF_VECTOR; |
6577 | fault.error_code_valid = true; | |
6578 | fault.error_code = 0; | |
6579 | fault.nested_page_fault = false; | |
6580 | fault.address = work->arch.token; | |
6581 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 6582 | } |
af585b92 GN |
6583 | } |
6584 | ||
6585 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
6586 | struct kvm_async_pf *work) | |
6587 | { | |
6389ee94 AK |
6588 | struct x86_exception fault; |
6589 | ||
7c90705b GN |
6590 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
6591 | if (is_error_page(work->page)) | |
6592 | work->arch.token = ~0; /* broadcast wakeup */ | |
6593 | else | |
6594 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
6595 | ||
6596 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
6597 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
6598 | fault.vector = PF_VECTOR; |
6599 | fault.error_code_valid = true; | |
6600 | fault.error_code = 0; | |
6601 | fault.nested_page_fault = false; | |
6602 | fault.address = work->arch.token; | |
6603 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 6604 | } |
e6d53e3b | 6605 | vcpu->arch.apf.halted = false; |
a4fa1635 | 6606 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
6607 | } |
6608 | ||
6609 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
6610 | { | |
6611 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
6612 | return true; | |
6613 | else | |
6614 | return !kvm_event_needs_reinjection(vcpu) && | |
6615 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
6616 | } |
6617 | ||
229456fc MT |
6618 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
6619 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
6620 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
6621 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
6622 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 6623 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 6624 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 6625 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 6626 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 6627 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 6628 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 6629 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |