projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Don't allow lmsw to clear cr0.pe
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
043405e1 55
313a3dc7 56#define MAX_IO_MSRS 256
a03490ed
CO		 57#define CR0_RESERVED_BITS \
58 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
59 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
60 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
61#define CR4_RESERVED_BITS \
62 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
63 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
64 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
65 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
66
67#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 68
69#define KVM_MAX_MCE_BANKS 32
70#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
78#else
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 86static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
87 struct kvm_cpuid_entry2 __user *entries);
88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
18863bdd
AK		 150static void kvm_on_user_return(struct user_return_notifier *urn)
151{
152 unsigned slot;
18863bdd
AK		 153 struct kvm_shared_msrs *locals
154 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 155 struct kvm_shared_msr_values *values;
18863bdd
AK		 156
157 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 158 values = &locals->values[slot];
159 if (values->host != values->curr) {
160 wrmsrl(shared_msrs_global.msrs[slot], values->host);
161 values->curr = values->host;
18863bdd
AK		 162 }
163 }
164 locals->registered = false;
165 user_return_notifier_unregister(urn);
166}
167
2bf78fa7 168static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 169{
2bf78fa7 170 struct kvm_shared_msrs *smsr;
18863bdd
AK		 171 u64 value;
172
2bf78fa7
SY		 173 smsr = &__get_cpu_var(shared_msrs);
174 /* only read, and nobody should modify it at this time,
175 * so don't need lock */
176 if (slot >= shared_msrs_global.nr) {
177 printk(KERN_ERR "kvm: invalid MSR slot!");
178 return;
179 }
180 rdmsrl_safe(msr, &value);
181 smsr->values[slot].host = value;
182 smsr->values[slot].curr = value;
183}
184
185void kvm_define_shared_msr(unsigned slot, u32 msr)
186{
18863bdd
AK		 187 if (slot >= shared_msrs_global.nr)
188 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 189 shared_msrs_global.msrs[slot] = msr;
190 /* we need ensured the shared_msr_global have been updated */
191 smp_wmb();
18863bdd
AK		 192}
193EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
194
195static void kvm_shared_msr_cpu_online(void)
196{
197 unsigned i;
18863bdd
AK		 198
199 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 200 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 201}
202
d5696725 203void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 204{
205 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
206
2bf78fa7 207 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 208 return;
2bf78fa7
SY		 209 smsr->values[slot].curr = value;
210 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 211 if (!smsr->registered) {
212 smsr->urn.on_user_return = kvm_on_user_return;
213 user_return_notifier_register(&smsr->urn);
214 smsr->registered = true;
215 }
216}
217EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
218
3548bab5
AK		 219static void drop_user_return_notifiers(void *ignore)
220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
223 if (smsr->registered)
224 kvm_on_user_return(&smsr->urn);
225}
226
6866b83e
CO		 227u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
228{
229 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 230 return vcpu->arch.apic_base;
6866b83e 231 else
ad312c7c 232 return vcpu->arch.apic_base;
6866b83e
CO		 233}
234EXPORT_SYMBOL_GPL(kvm_get_apic_base);
235
236void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
237{
238 /* TODO: reserve bits check */
239 if (irqchip_in_kernel(vcpu->kvm))
240 kvm_lapic_set_base(vcpu, data);
241 else
ad312c7c 242 vcpu->arch.apic_base = data;
6866b83e
CO		 243}
244EXPORT_SYMBOL_GPL(kvm_set_apic_base);
245
3fd28fce
ED		 246#define EXCPT_BENIGN 0
247#define EXCPT_CONTRIBUTORY 1
248#define EXCPT_PF 2
249
250static int exception_class(int vector)
251{
252 switch (vector) {
253 case PF_VECTOR:
254 return EXCPT_PF;
255 case DE_VECTOR:
256 case TS_VECTOR:
257 case NP_VECTOR:
258 case SS_VECTOR:
259 case GP_VECTOR:
260 return EXCPT_CONTRIBUTORY;
261 default:
262 break;
263 }
264 return EXCPT_BENIGN;
265}
266
267static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 268 unsigned nr, bool has_error, u32 error_code,
269 bool reinject)
3fd28fce
ED		 270{
271 u32 prev_nr;
272 int class1, class2;
273
274 if (!vcpu->arch.exception.pending) {
275 queue:
276 vcpu->arch.exception.pending = true;
277 vcpu->arch.exception.has_error_code = has_error;
278 vcpu->arch.exception.nr = nr;
279 vcpu->arch.exception.error_code = error_code;
3f0fd292 280 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 281 return;
282 }
283
284 /* to check exception */
285 prev_nr = vcpu->arch.exception.nr;
286 if (prev_nr == DF_VECTOR) {
287 /* triple fault -> shutdown */
288 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
289 return;
290 }
291 class1 = exception_class(prev_nr);
292 class2 = exception_class(nr);
293 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
294 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
295 /* generate double fault per SDM Table 5-5 */
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = true;
298 vcpu->arch.exception.nr = DF_VECTOR;
299 vcpu->arch.exception.error_code = 0;
300 } else
301 /* replace previous exception with a new one in a hope
302 that instruction re-execution will regenerate lost
303 exception */
304 goto queue;
305}
306
298101da
AK		 307void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
308{
ce7ddec4 309 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 310}
311EXPORT_SYMBOL_GPL(kvm_queue_exception);
312
ce7ddec4
JR		 313void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
314{
315 kvm_multiple_exception(vcpu, nr, false, 0, true);
316}
317EXPORT_SYMBOL_GPL(kvm_requeue_exception);
318
c3c91fee
AK		 319void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
320 u32 error_code)
321{
322 ++vcpu->stat.pf_guest;
ad312c7c 323 vcpu->arch.cr2 = addr;
c3c91fee
AK		 324 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
325}
326
3419ffc8
SY		 327void kvm_inject_nmi(struct kvm_vcpu *vcpu)
328{
329 vcpu->arch.nmi_pending = 1;
330}
331EXPORT_SYMBOL_GPL(kvm_inject_nmi);
332
298101da
AK		 333void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
334{
ce7ddec4 335 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 336}
337EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
338
ce7ddec4
JR		 339void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
340{
341 kvm_multiple_exception(vcpu, nr, true, error_code, true);
342}
343EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
344
0a79b009
AK		 345/*
346 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
347 * a #GP and return false.
348 */
349bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 350{
0a79b009
AK		 351 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
352 return true;
353 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
354 return false;
298101da 355}
0a79b009 356EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 357
a03490ed
CO		 358/*
359 * Load the pae pdptrs. Return true is they are all valid.
360 */
361int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
362{
363 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
364 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
365 int i;
366 int ret;
ad312c7c 367 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 368
a03490ed
CO		 369 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
370 offset * sizeof(u64), sizeof(pdpte));
371 if (ret < 0) {
372 ret = 0;
373 goto out;
374 }
375 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 376 if (is_present_gpte(pdpte[i]) &&
20c466b5 377 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 378 ret = 0;
379 goto out;
380 }
381 }
382 ret = 1;
383
ad312c7c 384 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 385 __set_bit(VCPU_EXREG_PDPTR,
386 (unsigned long *)&vcpu->arch.regs_avail);
387 __set_bit(VCPU_EXREG_PDPTR,
388 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 389out:
a03490ed
CO		 390
391 return ret;
392}
cc4b6871 393EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 394
d835dfec
AK		 395static bool pdptrs_changed(struct kvm_vcpu *vcpu)
396{
ad312c7c 397 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 398 bool changed = true;
399 int r;
400
401 if (is_long_mode(vcpu) || !is_pae(vcpu))
402 return false;
403
6de4f3ad
AK		 404 if (!test_bit(VCPU_EXREG_PDPTR,
405 (unsigned long *)&vcpu->arch.regs_avail))
406 return true;
407
ad312c7c 408 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 409 if (r < 0)
410 goto out;
ad312c7c 411 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 412out:
d835dfec
AK		 413
414 return changed;
415}
416
2d3ad1f4 417void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 418{
f9a48e6a
AK		 419 cr0 |= X86_CR0_ET;
420
ab344828
GN		 421#ifdef CONFIG_X86_64
422 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 423 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 424 return;
425 }
ab344828
GN		 426#endif
427
428 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 429
430 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 431 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 432 return;
433 }
434
435 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
439
440 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
441#ifdef CONFIG_X86_64
f6801dff 442 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 443 int cs_db, cs_l;
444
445 if (!is_pae(vcpu)) {
c1a5d4f9 446 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 447 return;
448 }
449 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
450 if (cs_l) {
c1a5d4f9 451 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 452 return;
453
454 }
455 } else
456#endif
ad312c7c 457 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 458 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 459 return;
460 }
461
462 }
463
464 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 465
a03490ed 466 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 467 return;
468}
2d3ad1f4 469EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 470
2d3ad1f4 471void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 472{
f78e9176 473 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 474}
2d3ad1f4 475EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 476
2d3ad1f4 477void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 478{
fc78f519 479 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 480 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
481
a03490ed 482 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 483 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 484 return;
485 }
486
487 if (is_long_mode(vcpu)) {
488 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 489 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 490 return;
491 }
a2edf57f
AK		 492 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
493 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 494 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 495 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 496 return;
497 }
498
499 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 500 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 501 return;
502 }
503 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 504 vcpu->arch.cr4 = cr4;
a03490ed 505 kvm_mmu_reset_context(vcpu);
a03490ed 506}
2d3ad1f4 507EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 508
2d3ad1f4 509void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 510{
ad312c7c 511 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 512 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 513 kvm_mmu_flush_tlb(vcpu);
514 return;
515 }
516
a03490ed
CO		 517 if (is_long_mode(vcpu)) {
518 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 519 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 520 return;
521 }
522 } else {
523 if (is_pae(vcpu)) {
524 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 525 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 526 return;
527 }
528 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 529 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 530 return;
531 }
532 }
533 /*
534 * We don't check reserved bits in nonpae mode, because
535 * this isn't enforced, and VMware depends on this.
536 */
537 }
538
a03490ed
CO		 539 /*
540 * Does the new cr3 value map to physical memory? (Note, we
541 * catch an invalid cr3 even in real-mode, because it would
542 * cause trouble later on when we turn on paging anyway.)
543 *
544 * A real CPU would silently accept an invalid cr3 and would
545 * attempt to use it - with largely undefined (and often hard
546 * to debug) behavior on the guest side.
547 */
548 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 549 kvm_inject_gp(vcpu, 0);
a03490ed 550 else {
ad312c7c
ZX		 551 vcpu->arch.cr3 = cr3;
552 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 553 }
a03490ed 554}
2d3ad1f4 555EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 556
2d3ad1f4 557void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 558{
559 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 560 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 561 return;
562 }
563 if (irqchip_in_kernel(vcpu->kvm))
564 kvm_lapic_set_tpr(vcpu, cr8);
565 else
ad312c7c 566 vcpu->arch.cr8 = cr8;
a03490ed 567}
2d3ad1f4 568EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 569
2d3ad1f4 570unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 571{
572 if (irqchip_in_kernel(vcpu->kvm))
573 return kvm_lapic_get_cr8(vcpu);
574 else
ad312c7c 575 return vcpu->arch.cr8;
a03490ed 576}
2d3ad1f4 577EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 578
020df079
GN		 579int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
580{
581 switch (dr) {
582 case 0 ... 3:
583 vcpu->arch.db[dr] = val;
584 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
585 vcpu->arch.eff_db[dr] = val;
586 break;
587 case 4:
588 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
589 kvm_queue_exception(vcpu, UD_VECTOR);
590 return 1;
591 }
592 /* fall through */
593 case 6:
594 if (val & 0xffffffff00000000ULL) {
595 kvm_inject_gp(vcpu, 0);
596 return 1;
597 }
598 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
599 break;
600 case 5:
601 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
602 kvm_queue_exception(vcpu, UD_VECTOR);
603 return 1;
604 }
605 /* fall through */
606 default: /* 7 */
607 if (val & 0xffffffff00000000ULL) {
608 kvm_inject_gp(vcpu, 0);
609 return 1;
610 }
611 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
612 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
613 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
614 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
615 }
616 break;
617 }
618
619 return 0;
620}
621EXPORT_SYMBOL_GPL(kvm_set_dr);
622
623int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
624{
625 switch (dr) {
626 case 0 ... 3:
627 *val = vcpu->arch.db[dr];
628 break;
629 case 4:
630 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
631 kvm_queue_exception(vcpu, UD_VECTOR);
632 return 1;
633 }
634 /* fall through */
635 case 6:
636 *val = vcpu->arch.dr6;
637 break;
638 case 5:
639 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
640 kvm_queue_exception(vcpu, UD_VECTOR);
641 return 1;
642 }
643 /* fall through */
644 default: /* 7 */
645 *val = vcpu->arch.dr7;
646 break;
647 }
648
649 return 0;
650}
651EXPORT_SYMBOL_GPL(kvm_get_dr);
652
d8017474
AG		 653static inline u32 bit(int bitno)
654{
655 return 1 << (bitno & 31);
656}
657
043405e1
CO		 658/*
659 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
660 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
661 *
662 * This list is modified at module load time to reflect the
e3267cbb
GC		 663 * capabilities of the host cpu. This capabilities test skips MSRs that are
664 * kvm-specific. Those are put in the beginning of the list.
043405e1 665 */
e3267cbb 666
11c6bffa 667#define KVM_SAVE_MSRS_BEGIN 7
043405e1 668static u32 msrs_to_save[] = {
e3267cbb 669 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 670 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 671 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 672 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 673 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
674 MSR_K6_STAR,
675#ifdef CONFIG_X86_64
676 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
677#endif
e3267cbb 678 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 679};
680
681static unsigned num_msrs_to_save;
682
683static u32 emulated_msrs[] = {
684 MSR_IA32_MISC_ENABLE,
685};
686
b69e8cae 687static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 688{
b69e8cae
RJ		 689 if (efer & efer_reserved_bits)
690 return 1;
15c4a640
CO		 691
692 if (is_paging(vcpu)
b69e8cae
RJ		 693 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
694 return 1;
15c4a640 695
1b2fd70c
AG		 696 if (efer & EFER_FFXSR) {
697 struct kvm_cpuid_entry2 *feat;
698
699 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 700 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
701 return 1;
1b2fd70c
AG		 702 }
703
d8017474
AG		 704 if (efer & EFER_SVME) {
705 struct kvm_cpuid_entry2 *feat;
706
707 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 708 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
709 return 1;
d8017474
AG		 710 }
711
15c4a640
CO		 712 kvm_x86_ops->set_efer(vcpu, efer);
713
714 efer &= ~EFER_LMA;
f6801dff 715 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 716
f6801dff 717 vcpu->arch.efer = efer;
9645bb56
AK		 718
719 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
720 kvm_mmu_reset_context(vcpu);
b69e8cae
RJ		 721
722 return 0;
15c4a640
CO		 723}
724
f2b4b7dd
JR		 725void kvm_enable_efer_bits(u64 mask)
726{
727 efer_reserved_bits &= ~mask;
728}
729EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
730
731
15c4a640
CO		 732/*
733 * Writes msr value into into the appropriate "register".
734 * Returns 0 on success, non-0 otherwise.
735 * Assumes vcpu_load() was already called.
736 */
737int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
738{
739 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
740}
741
313a3dc7
CO		 742/*
743 * Adapt set_msr() to msr_io()'s calling convention
744 */
745static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
746{
747 return kvm_set_msr(vcpu, index, *data);
748}
749
18068523
GOC		 750static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
751{
9ed3c444
AK		 752 int version;
753 int r;
50d0a0f9 754 struct pvclock_wall_clock wc;
923de3cf 755 struct timespec boot;
18068523
GOC		 756
757 if (!wall_clock)
758 return;
759
9ed3c444
AK		 760 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
761 if (r)
762 return;
763
764 if (version & 1)
765 ++version; /* first time write, random junk */
766
767 ++version;
18068523 768
18068523
GOC		 769 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
770
50d0a0f9
GH		 771 /*
772 * The guest calculates current wall clock time by adding
773 * system time (updated by kvm_write_guest_time below) to the
774 * wall clock specified here. guest system time equals host
775 * system time for us, thus we must fill in host boot time here.
776 */
923de3cf 777 getboottime(&boot);
50d0a0f9
GH		 778
779 wc.sec = boot.tv_sec;
780 wc.nsec = boot.tv_nsec;
781 wc.version = version;
18068523
GOC		 782
783 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
784
785 version++;
786 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 787}
788
50d0a0f9
GH		 789static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
790{
791 uint32_t quotient, remainder;
792
793 /* Don't try to replace with do_div(), this one calculates
794 * "(dividend << 32) / divisor" */
795 __asm__ ( "divl %4"
796 : "=a" (quotient), "=d" (remainder)
797 : "0" (0), "1" (dividend), "r" (divisor) );
798 return quotient;
799}
800
801static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
802{
803 uint64_t nsecs = 1000000000LL;
804 int32_t shift = 0;
805 uint64_t tps64;
806 uint32_t tps32;
807
808 tps64 = tsc_khz * 1000LL;
809 while (tps64 > nsecs*2) {
810 tps64 >>= 1;
811 shift--;
812 }
813
814 tps32 = (uint32_t)tps64;
815 while (tps32 <= (uint32_t)nsecs) {
816 tps32 <<= 1;
817 shift++;
818 }
819
820 hv_clock->tsc_shift = shift;
821 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
822
823 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 824 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 825 hv_clock->tsc_to_system_mul);
826}
827
c8076604
GH		 828static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
829
18068523
GOC		 830static void kvm_write_guest_time(struct kvm_vcpu *v)
831{
832 struct timespec ts;
833 unsigned long flags;
834 struct kvm_vcpu_arch *vcpu = &v->arch;
835 void *shared_kaddr;
463656c0 836 unsigned long this_tsc_khz;
18068523
GOC		 837
838 if ((!vcpu->time_page))
839 return;
840
463656c0
AK		 841 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
842 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
843 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
844 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 845 }
463656c0 846 put_cpu_var(cpu_tsc_khz);
50d0a0f9 847
18068523
GOC		 848 /* Keep irq disabled to prevent changes to the clock */
849 local_irq_save(flags);
af24a4e4 850 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 851 ktime_get_ts(&ts);
923de3cf 852 monotonic_to_bootbased(&ts);
18068523
GOC		 853 local_irq_restore(flags);
854
855 /* With all the info we got, fill in the values */
856
857 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 858 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
859
371bcf64
GC		 860 vcpu->hv_clock.flags = 0;
861
18068523
GOC		 862 /*
863 * The interface expects us to write an even number signaling that the
864 * update is finished. Since the guest won't see the intermediate
50d0a0f9 865 * state, we just increase by 2 at the end.
18068523 866 */
50d0a0f9 867 vcpu->hv_clock.version += 2;
18068523
GOC		 868
869 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
870
871 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 872 sizeof(vcpu->hv_clock));
18068523
GOC		 873
874 kunmap_atomic(shared_kaddr, KM_USER0);
875
876 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
877}
878
c8076604
GH		 879static int kvm_request_guest_time_update(struct kvm_vcpu *v)
880{
881 struct kvm_vcpu_arch *vcpu = &v->arch;
882
883 if (!vcpu->time_page)
884 return 0;
885 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
886 return 1;
887}
888
9ba075a6
AK		 889static bool msr_mtrr_valid(unsigned msr)
890{
891 switch (msr) {
892 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
893 case MSR_MTRRfix64K_00000:
894 case MSR_MTRRfix16K_80000:
895 case MSR_MTRRfix16K_A0000:
896 case MSR_MTRRfix4K_C0000:
897 case MSR_MTRRfix4K_C8000:
898 case MSR_MTRRfix4K_D0000:
899 case MSR_MTRRfix4K_D8000:
900 case MSR_MTRRfix4K_E0000:
901 case MSR_MTRRfix4K_E8000:
902 case MSR_MTRRfix4K_F0000:
903 case MSR_MTRRfix4K_F8000:
904 case MSR_MTRRdefType:
905 case MSR_IA32_CR_PAT:
906 return true;
907 case 0x2f8:
908 return true;
909 }
910 return false;
911}
912
d6289b93
MT		 913static bool valid_pat_type(unsigned t)
914{
915 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
916}
917
918static bool valid_mtrr_type(unsigned t)
919{
920 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
921}
922
923static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
924{
925 int i;
926
927 if (!msr_mtrr_valid(msr))
928 return false;
929
930 if (msr == MSR_IA32_CR_PAT) {
931 for (i = 0; i < 8; i++)
932 if (!valid_pat_type((data >> (i * 8)) & 0xff))
933 return false;
934 return true;
935 } else if (msr == MSR_MTRRdefType) {
936 if (data & ~0xcff)
937 return false;
938 return valid_mtrr_type(data & 0xff);
939 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
940 for (i = 0; i < 8 ; i++)
941 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
942 return false;
943 return true;
944 }
945
946 /* variable MTRRs */
947 return valid_mtrr_type(data & 0xff);
948}
949
9ba075a6
AK		 950static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
951{
0bed3b56
SY		 952 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
953
d6289b93 954 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 955 return 1;
956
0bed3b56
SY		 957 if (msr == MSR_MTRRdefType) {
958 vcpu->arch.mtrr_state.def_type = data;
959 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
960 } else if (msr == MSR_MTRRfix64K_00000)
961 p[0] = data;
962 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
963 p[1 + msr - MSR_MTRRfix16K_80000] = data;
964 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
965 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
966 else if (msr == MSR_IA32_CR_PAT)
967 vcpu->arch.pat = data;
968 else { /* Variable MTRRs */
969 int idx, is_mtrr_mask;
970 u64 *pt;
971
972 idx = (msr - 0x200) / 2;
973 is_mtrr_mask = msr - 0x200 - 2 * idx;
974 if (!is_mtrr_mask)
975 pt =
976 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
977 else
978 pt =
979 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
980 *pt = data;
981 }
982
983 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 984 return 0;
985}
15c4a640 986
890ca9ae 987static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 988{
890ca9ae
HY		 989 u64 mcg_cap = vcpu->arch.mcg_cap;
990 unsigned bank_num = mcg_cap & 0xff;
991
15c4a640 992 switch (msr) {
15c4a640 993 case MSR_IA32_MCG_STATUS:
890ca9ae 994 vcpu->arch.mcg_status = data;
15c4a640 995 break;
c7ac679c 996 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 997 if (!(mcg_cap & MCG_CTL_P))
998 return 1;
999 if (data != 0 && data != ~(u64)0)
1000 return -1;
1001 vcpu->arch.mcg_ctl = data;
1002 break;
1003 default:
1004 if (msr >= MSR_IA32_MC0_CTL &&
1005 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1006 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1007 /* only 0 or all 1s can be written to IA32_MCi_CTL
1008 * some Linux kernels though clear bit 10 in bank 4 to
1009 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1010 * this to avoid an uncatched #GP in the guest
1011 */
890ca9ae 1012 if ((offset & 0x3) == 0 &&
114be429 1013 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1014 return -1;
1015 vcpu->arch.mce_banks[offset] = data;
1016 break;
1017 }
1018 return 1;
1019 }
1020 return 0;
1021}
1022
ffde22ac
ES		 1023static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1024{
1025 struct kvm *kvm = vcpu->kvm;
1026 int lm = is_long_mode(vcpu);
1027 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1028 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1029 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1030 : kvm->arch.xen_hvm_config.blob_size_32;
1031 u32 page_num = data & ~PAGE_MASK;
1032 u64 page_addr = data & PAGE_MASK;
1033 u8 *page;
1034 int r;
1035
1036 r = -E2BIG;
1037 if (page_num >= blob_size)
1038 goto out;
1039 r = -ENOMEM;
1040 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1041 if (!page)
1042 goto out;
1043 r = -EFAULT;
1044 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1045 goto out_free;
1046 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1047 goto out_free;
1048 r = 0;
1049out_free:
1050 kfree(page);
1051out:
1052 return r;
1053}
1054
55cd8e5a
GN		 1055static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1056{
1057 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1058}
1059
1060static bool kvm_hv_msr_partition_wide(u32 msr)
1061{
1062 bool r = false;
1063 switch (msr) {
1064 case HV_X64_MSR_GUEST_OS_ID:
1065 case HV_X64_MSR_HYPERCALL:
1066 r = true;
1067 break;
1068 }
1069
1070 return r;
1071}
1072
1073static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1074{
1075 struct kvm *kvm = vcpu->kvm;
1076
1077 switch (msr) {
1078 case HV_X64_MSR_GUEST_OS_ID:
1079 kvm->arch.hv_guest_os_id = data;
1080 /* setting guest os id to zero disables hypercall page */
1081 if (!kvm->arch.hv_guest_os_id)
1082 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1083 break;
1084 case HV_X64_MSR_HYPERCALL: {
1085 u64 gfn;
1086 unsigned long addr;
1087 u8 instructions[4];
1088
1089 /* if guest os id is not set hypercall should remain disabled */
1090 if (!kvm->arch.hv_guest_os_id)
1091 break;
1092 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1093 kvm->arch.hv_hypercall = data;
1094 break;
1095 }
1096 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1097 addr = gfn_to_hva(kvm, gfn);
1098 if (kvm_is_error_hva(addr))
1099 return 1;
1100 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1101 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1102 if (copy_to_user((void __user *)addr, instructions, 4))
1103 return 1;
1104 kvm->arch.hv_hypercall = data;
1105 break;
1106 }
1107 default:
1108 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1109 "data 0x%llx\n", msr, data);
1110 return 1;
1111 }
1112 return 0;
1113}
1114
1115static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1116{
10388a07
GN		 1117 switch (msr) {
1118 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1119 unsigned long addr;
55cd8e5a 1120
10388a07
GN		 1121 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1122 vcpu->arch.hv_vapic = data;
1123 break;
1124 }
1125 addr = gfn_to_hva(vcpu->kvm, data >>
1126 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1127 if (kvm_is_error_hva(addr))
1128 return 1;
1129 if (clear_user((void __user *)addr, PAGE_SIZE))
1130 return 1;
1131 vcpu->arch.hv_vapic = data;
1132 break;
1133 }
1134 case HV_X64_MSR_EOI:
1135 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1136 case HV_X64_MSR_ICR:
1137 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1138 case HV_X64_MSR_TPR:
1139 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1140 default:
1141 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1142 "data 0x%llx\n", msr, data);
1143 return 1;
1144 }
1145
1146 return 0;
55cd8e5a
GN		 1147}
1148
15c4a640
CO		 1149int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1150{
1151 switch (msr) {
15c4a640 1152 case MSR_EFER:
b69e8cae 1153 return set_efer(vcpu, data);
8f1589d9
AP		 1154 case MSR_K7_HWCR:
1155 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1156 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1157 if (data != 0) {
1158 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1159 data);
1160 return 1;
1161 }
15c4a640 1162 break;
f7c6d140
AP		 1163 case MSR_FAM10H_MMIO_CONF_BASE:
1164 if (data != 0) {
1165 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1166 "0x%llx\n", data);
1167 return 1;
1168 }
15c4a640 1169 break;
c323c0e5 1170 case MSR_AMD64_NB_CFG:
c7ac679c 1171 break;
b5e2fec0
AG		 1172 case MSR_IA32_DEBUGCTLMSR:
1173 if (!data) {
1174 /* We support the non-activated case already */
1175 break;
1176 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1177 /* Values other than LBR and BTF are vendor-specific,
1178 thus reserved and should throw a #GP */
1179 return 1;
1180 }
1181 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1182 __func__, data);
1183 break;
15c4a640
CO		 1184 case MSR_IA32_UCODE_REV:
1185 case MSR_IA32_UCODE_WRITE:
61a6bd67 1186 case MSR_VM_HSAVE_PA:
6098ca93 1187 case MSR_AMD64_PATCH_LOADER:
15c4a640 1188 break;
9ba075a6
AK		 1189 case 0x200 ... 0x2ff:
1190 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1191 case MSR_IA32_APICBASE:
1192 kvm_set_apic_base(vcpu, data);
1193 break;
0105d1a5
GN		 1194 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1195 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1196 case MSR_IA32_MISC_ENABLE:
ad312c7c 1197 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1198 break;
11c6bffa 1199 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1200 case MSR_KVM_WALL_CLOCK:
1201 vcpu->kvm->arch.wall_clock = data;
1202 kvm_write_wall_clock(vcpu->kvm, data);
1203 break;
11c6bffa 1204 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1205 case MSR_KVM_SYSTEM_TIME: {
1206 if (vcpu->arch.time_page) {
1207 kvm_release_page_dirty(vcpu->arch.time_page);
1208 vcpu->arch.time_page = NULL;
1209 }
1210
1211 vcpu->arch.time = data;
1212
1213 /* we verify if the enable bit is set... */
1214 if (!(data & 1))
1215 break;
1216
1217 /* ...but clean it before doing the actual write */
1218 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1219
18068523
GOC		 1220 vcpu->arch.time_page =
1221 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1222
1223 if (is_error_page(vcpu->arch.time_page)) {
1224 kvm_release_page_clean(vcpu->arch.time_page);
1225 vcpu->arch.time_page = NULL;
1226 }
1227
c8076604 1228 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1229 break;
1230 }
890ca9ae
HY		 1231 case MSR_IA32_MCG_CTL:
1232 case MSR_IA32_MCG_STATUS:
1233 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1234 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1235
1236 /* Performance counters are not protected by a CPUID bit,
1237 * so we should check all of them in the generic path for the sake of
1238 * cross vendor migration.
1239 * Writing a zero into the event select MSRs disables them,
1240 * which we perfectly emulate ;-). Any other value should be at least
1241 * reported, some guests depend on them.
1242 */
1243 case MSR_P6_EVNTSEL0:
1244 case MSR_P6_EVNTSEL1:
1245 case MSR_K7_EVNTSEL0:
1246 case MSR_K7_EVNTSEL1:
1247 case MSR_K7_EVNTSEL2:
1248 case MSR_K7_EVNTSEL3:
1249 if (data != 0)
1250 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1251 "0x%x data 0x%llx\n", msr, data);
1252 break;
1253 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1254 * so we ignore writes to make it happy.
1255 */
1256 case MSR_P6_PERFCTR0:
1257 case MSR_P6_PERFCTR1:
1258 case MSR_K7_PERFCTR0:
1259 case MSR_K7_PERFCTR1:
1260 case MSR_K7_PERFCTR2:
1261 case MSR_K7_PERFCTR3:
1262 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1263 "0x%x data 0x%llx\n", msr, data);
1264 break;
55cd8e5a
GN		 1265 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1266 if (kvm_hv_msr_partition_wide(msr)) {
1267 int r;
1268 mutex_lock(&vcpu->kvm->lock);
1269 r = set_msr_hyperv_pw(vcpu, msr, data);
1270 mutex_unlock(&vcpu->kvm->lock);
1271 return r;
1272 } else
1273 return set_msr_hyperv(vcpu, msr, data);
1274 break;
15c4a640 1275 default:
ffde22ac
ES		 1276 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1277 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1278 if (!ignore_msrs) {
1279 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1280 msr, data);
1281 return 1;
1282 } else {
1283 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1284 msr, data);
1285 break;
1286 }
15c4a640
CO		 1287 }
1288 return 0;
1289}
1290EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1291
1292
1293/*
1294 * Reads an msr value (of 'msr_index') into 'pdata'.
1295 * Returns 0 on success, non-0 otherwise.
1296 * Assumes vcpu_load() was already called.
1297 */
1298int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1299{
1300 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1301}
1302
9ba075a6
AK		 1303static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1304{
0bed3b56
SY		 1305 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1306
9ba075a6
AK		 1307 if (!msr_mtrr_valid(msr))
1308 return 1;
1309
0bed3b56
SY		 1310 if (msr == MSR_MTRRdefType)
1311 *pdata = vcpu->arch.mtrr_state.def_type +
1312 (vcpu->arch.mtrr_state.enabled << 10);
1313 else if (msr == MSR_MTRRfix64K_00000)
1314 *pdata = p[0];
1315 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1316 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1317 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1318 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1319 else if (msr == MSR_IA32_CR_PAT)
1320 *pdata = vcpu->arch.pat;
1321 else { /* Variable MTRRs */
1322 int idx, is_mtrr_mask;
1323 u64 *pt;
1324
1325 idx = (msr - 0x200) / 2;
1326 is_mtrr_mask = msr - 0x200 - 2 * idx;
1327 if (!is_mtrr_mask)
1328 pt =
1329 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1330 else
1331 pt =
1332 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1333 *pdata = *pt;
1334 }
1335
9ba075a6
AK		 1336 return 0;
1337}
1338
890ca9ae 1339static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1340{
1341 u64 data;
890ca9ae
HY		 1342 u64 mcg_cap = vcpu->arch.mcg_cap;
1343 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1344
1345 switch (msr) {
15c4a640
CO		 1346 case MSR_IA32_P5_MC_ADDR:
1347 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1348 data = 0;
1349 break;
15c4a640 1350 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1351 data = vcpu->arch.mcg_cap;
1352 break;
c7ac679c 1353 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1354 if (!(mcg_cap & MCG_CTL_P))
1355 return 1;
1356 data = vcpu->arch.mcg_ctl;
1357 break;
1358 case MSR_IA32_MCG_STATUS:
1359 data = vcpu->arch.mcg_status;
1360 break;
1361 default:
1362 if (msr >= MSR_IA32_MC0_CTL &&
1363 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1364 u32 offset = msr - MSR_IA32_MC0_CTL;
1365 data = vcpu->arch.mce_banks[offset];
1366 break;
1367 }
1368 return 1;
1369 }
1370 *pdata = data;
1371 return 0;
1372}
1373
55cd8e5a
GN		 1374static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1375{
1376 u64 data = 0;
1377 struct kvm *kvm = vcpu->kvm;
1378
1379 switch (msr) {
1380 case HV_X64_MSR_GUEST_OS_ID:
1381 data = kvm->arch.hv_guest_os_id;
1382 break;
1383 case HV_X64_MSR_HYPERCALL:
1384 data = kvm->arch.hv_hypercall;
1385 break;
1386 default:
1387 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1388 return 1;
1389 }
1390
1391 *pdata = data;
1392 return 0;
1393}
1394
1395static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1396{
1397 u64 data = 0;
1398
1399 switch (msr) {
1400 case HV_X64_MSR_VP_INDEX: {
1401 int r;
1402 struct kvm_vcpu *v;
1403 kvm_for_each_vcpu(r, v, vcpu->kvm)
1404 if (v == vcpu)
1405 data = r;
1406 break;
1407 }
10388a07
GN		 1408 case HV_X64_MSR_EOI:
1409 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1410 case HV_X64_MSR_ICR:
1411 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1412 case HV_X64_MSR_TPR:
1413 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1414 default:
1415 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1416 return 1;
1417 }
1418 *pdata = data;
1419 return 0;
1420}
1421
890ca9ae
HY		 1422int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1423{
1424 u64 data;
1425
1426 switch (msr) {
890ca9ae 1427 case MSR_IA32_PLATFORM_ID:
15c4a640 1428 case MSR_IA32_UCODE_REV:
15c4a640 1429 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1430 case MSR_IA32_DEBUGCTLMSR:
1431 case MSR_IA32_LASTBRANCHFROMIP:
1432 case MSR_IA32_LASTBRANCHTOIP:
1433 case MSR_IA32_LASTINTFROMIP:
1434 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1435 case MSR_K8_SYSCFG:
1436 case MSR_K7_HWCR:
61a6bd67 1437 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1438 case MSR_P6_PERFCTR0:
1439 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1440 case MSR_P6_EVNTSEL0:
1441 case MSR_P6_EVNTSEL1:
9e699624 1442 case MSR_K7_EVNTSEL0:
1f3ee616 1443 case MSR_K7_PERFCTR0:
1fdbd48c 1444 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1445 case MSR_AMD64_NB_CFG:
f7c6d140 1446 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1447 data = 0;
1448 break;
9ba075a6
AK		 1449 case MSR_MTRRcap:
1450 data = 0x500 | KVM_NR_VAR_MTRR;
1451 break;
1452 case 0x200 ... 0x2ff:
1453 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1454 case 0xcd: /* fsb frequency */
1455 data = 3;
1456 break;
1457 case MSR_IA32_APICBASE:
1458 data = kvm_get_apic_base(vcpu);
1459 break;
0105d1a5
GN		 1460 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1461 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1462 break;
15c4a640 1463 case MSR_IA32_MISC_ENABLE:
ad312c7c 1464 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1465 break;
847f0ad8
AG		 1466 case MSR_IA32_PERF_STATUS:
1467 /* TSC increment by tick */
1468 data = 1000ULL;
1469 /* CPU multiplier */
1470 data |= (((uint64_t)4ULL) << 40);
1471 break;
15c4a640 1472 case MSR_EFER:
f6801dff 1473 data = vcpu->arch.efer;
15c4a640 1474 break;
18068523 1475 case MSR_KVM_WALL_CLOCK:
11c6bffa 1476 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1477 data = vcpu->kvm->arch.wall_clock;
1478 break;
1479 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1480 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1481 data = vcpu->arch.time;
1482 break;
890ca9ae
HY		 1483 case MSR_IA32_P5_MC_ADDR:
1484 case MSR_IA32_P5_MC_TYPE:
1485 case MSR_IA32_MCG_CAP:
1486 case MSR_IA32_MCG_CTL:
1487 case MSR_IA32_MCG_STATUS:
1488 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1489 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1490 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1491 if (kvm_hv_msr_partition_wide(msr)) {
1492 int r;
1493 mutex_lock(&vcpu->kvm->lock);
1494 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1495 mutex_unlock(&vcpu->kvm->lock);
1496 return r;
1497 } else
1498 return get_msr_hyperv(vcpu, msr, pdata);
1499 break;
15c4a640 1500 default:
ed85c068
AP		 1501 if (!ignore_msrs) {
1502 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1503 return 1;
1504 } else {
1505 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1506 data = 0;
1507 }
1508 break;
15c4a640
CO		 1509 }
1510 *pdata = data;
1511 return 0;
1512}
1513EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1514
313a3dc7
CO		 1515/*
1516 * Read or write a bunch of msrs. All parameters are kernel addresses.
1517 *
1518 * @return number of msrs set successfully.
1519 */
1520static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1521 struct kvm_msr_entry *entries,
1522 int (*do_msr)(struct kvm_vcpu *vcpu,
1523 unsigned index, u64 *data))
1524{
f656ce01 1525 int i, idx;
313a3dc7
CO		 1526
1527 vcpu_load(vcpu);
1528
f656ce01 1529 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1530 for (i = 0; i < msrs->nmsrs; ++i)
1531 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1532 break;
f656ce01 1533 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1534
1535 vcpu_put(vcpu);
1536
1537 return i;
1538}
1539
1540/*
1541 * Read or write a bunch of msrs. Parameters are user addresses.
1542 *
1543 * @return number of msrs set successfully.
1544 */
1545static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1546 int (*do_msr)(struct kvm_vcpu *vcpu,
1547 unsigned index, u64 *data),
1548 int writeback)
1549{
1550 struct kvm_msrs msrs;
1551 struct kvm_msr_entry *entries;
1552 int r, n;
1553 unsigned size;
1554
1555 r = -EFAULT;
1556 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1557 goto out;
1558
1559 r = -E2BIG;
1560 if (msrs.nmsrs >= MAX_IO_MSRS)
1561 goto out;
1562
1563 r = -ENOMEM;
1564 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1565 entries = vmalloc(size);
1566 if (!entries)
1567 goto out;
1568
1569 r = -EFAULT;
1570 if (copy_from_user(entries, user_msrs->entries, size))
1571 goto out_free;
1572
1573 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1574 if (r < 0)
1575 goto out_free;
1576
1577 r = -EFAULT;
1578 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1579 goto out_free;
1580
1581 r = n;
1582
1583out_free:
1584 vfree(entries);
1585out:
1586 return r;
1587}
1588
018d00d2
ZX		 1589int kvm_dev_ioctl_check_extension(long ext)
1590{
1591 int r;
1592
1593 switch (ext) {
1594 case KVM_CAP_IRQCHIP:
1595 case KVM_CAP_HLT:
1596 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1597 case KVM_CAP_SET_TSS_ADDR:
07716717 1598 case KVM_CAP_EXT_CPUID:
c8076604 1599 case KVM_CAP_CLOCKSOURCE:
7837699f 1600 case KVM_CAP_PIT:
a28e4f5a 1601 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1602 case KVM_CAP_MP_STATE:
ed848624 1603 case KVM_CAP_SYNC_MMU:
52d939a0 1604 case KVM_CAP_REINJECT_CONTROL:
4925663a 1605 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1606 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1607 case KVM_CAP_IRQFD:
d34e6b17 1608 case KVM_CAP_IOEVENTFD:
c5ff41ce 1609 case KVM_CAP_PIT2:
e9f42757 1610 case KVM_CAP_PIT_STATE2:
b927a3ce 1611 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1612 case KVM_CAP_XEN_HVM:
afbcf7ab 1613 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1614 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1615 case KVM_CAP_HYPERV:
10388a07 1616 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1617 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1618 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1619 case KVM_CAP_DEBUGREGS:
d2be1651 1620 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1621 r = 1;
1622 break;
542472b5
LV		 1623 case KVM_CAP_COALESCED_MMIO:
1624 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1625 break;
774ead3a
AK		 1626 case KVM_CAP_VAPIC:
1627 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1628 break;
f725230a
AK		 1629 case KVM_CAP_NR_VCPUS:
1630 r = KVM_MAX_VCPUS;
1631 break;
a988b910
AK		 1632 case KVM_CAP_NR_MEMSLOTS:
1633 r = KVM_MEMORY_SLOTS;
1634 break;
a68a6a72
MT		 1635 case KVM_CAP_PV_MMU: /* obsolete */
1636 r = 0;
2f333bcb 1637 break;
62c476c7 1638 case KVM_CAP_IOMMU:
19de40a8 1639 r = iommu_found();
62c476c7 1640 break;
890ca9ae
HY		 1641 case KVM_CAP_MCE:
1642 r = KVM_MAX_MCE_BANKS;
1643 break;
018d00d2
ZX		 1644 default:
1645 r = 0;
1646 break;
1647 }
1648 return r;
1649
1650}
1651
043405e1
CO		 1652long kvm_arch_dev_ioctl(struct file *filp,
1653 unsigned int ioctl, unsigned long arg)
1654{
1655 void __user *argp = (void __user *)arg;
1656 long r;
1657
1658 switch (ioctl) {
1659 case KVM_GET_MSR_INDEX_LIST: {
1660 struct kvm_msr_list __user *user_msr_list = argp;
1661 struct kvm_msr_list msr_list;
1662 unsigned n;
1663
1664 r = -EFAULT;
1665 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1666 goto out;
1667 n = msr_list.nmsrs;
1668 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1669 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1670 goto out;
1671 r = -E2BIG;
e125e7b6 1672 if (n < msr_list.nmsrs)
043405e1
CO		 1673 goto out;
1674 r = -EFAULT;
1675 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1676 num_msrs_to_save * sizeof(u32)))
1677 goto out;
e125e7b6 1678 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1679 &emulated_msrs,
1680 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1681 goto out;
1682 r = 0;
1683 break;
1684 }
674eea0f
AK		 1685 case KVM_GET_SUPPORTED_CPUID: {
1686 struct kvm_cpuid2 __user *cpuid_arg = argp;
1687 struct kvm_cpuid2 cpuid;
1688
1689 r = -EFAULT;
1690 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1691 goto out;
1692 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1693 cpuid_arg->entries);
674eea0f
AK		 1694 if (r)
1695 goto out;
1696
1697 r = -EFAULT;
1698 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1699 goto out;
1700 r = 0;
1701 break;
1702 }
890ca9ae
HY		 1703 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1704 u64 mce_cap;
1705
1706 mce_cap = KVM_MCE_CAP_SUPPORTED;
1707 r = -EFAULT;
1708 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1709 goto out;
1710 r = 0;
1711 break;
1712 }
043405e1
CO		 1713 default:
1714 r = -EINVAL;
1715 }
1716out:
1717 return r;
1718}
1719
313a3dc7
CO		 1720void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1721{
1722 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1723 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1724 unsigned long khz = cpufreq_quick_get(cpu);
1725 if (!khz)
1726 khz = tsc_khz;
1727 per_cpu(cpu_tsc_khz, cpu) = khz;
1728 }
c8076604 1729 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1730}
1731
1732void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1733{
9327fd11 1734 kvm_put_guest_fpu(vcpu);
02daab21 1735 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1736}
1737
07716717 1738static int is_efer_nx(void)
313a3dc7 1739{
e286e86e 1740 unsigned long long efer = 0;
313a3dc7 1741
e286e86e 1742 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1743 return efer & EFER_NX;
1744}
1745
1746static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1747{
1748 int i;
1749 struct kvm_cpuid_entry2 *e, *entry;
1750
313a3dc7 1751 entry = NULL;
ad312c7c
ZX		 1752 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1753 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1754 if (e->function == 0x80000001) {
1755 entry = e;
1756 break;
1757 }
1758 }
07716717 1759 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1760 entry->edx &= ~(1 << 20);
1761 printk(KERN_INFO "kvm: guest NX capability removed\n");
1762 }
1763}
1764
07716717 1765/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1766static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1767 struct kvm_cpuid *cpuid,
1768 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1769{
1770 int r, i;
1771 struct kvm_cpuid_entry *cpuid_entries;
1772
1773 r = -E2BIG;
1774 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1775 goto out;
1776 r = -ENOMEM;
1777 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1778 if (!cpuid_entries)
1779 goto out;
1780 r = -EFAULT;
1781 if (copy_from_user(cpuid_entries, entries,
1782 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1783 goto out_free;
1784 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1785 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1786 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1787 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1788 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1789 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1790 vcpu->arch.cpuid_entries[i].index = 0;
1791 vcpu->arch.cpuid_entries[i].flags = 0;
1792 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1793 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1794 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1795 }
1796 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1797 cpuid_fix_nx_cap(vcpu);
1798 r = 0;
fc61b800 1799 kvm_apic_set_version(vcpu);
0e851880 1800 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1801
1802out_free:
1803 vfree(cpuid_entries);
1804out:
1805 return r;
1806}
1807
1808static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1809 struct kvm_cpuid2 *cpuid,
1810 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1811{
1812 int r;
1813
1814 r = -E2BIG;
1815 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1816 goto out;
1817 r = -EFAULT;
ad312c7c 1818 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1819 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1820 goto out;
ad312c7c 1821 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1822 kvm_apic_set_version(vcpu);
0e851880 1823 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1824 return 0;
1825
1826out:
1827 return r;
1828}
1829
07716717 1830static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1831 struct kvm_cpuid2 *cpuid,
1832 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1833{
1834 int r;
1835
1836 r = -E2BIG;
ad312c7c 1837 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1838 goto out;
1839 r = -EFAULT;
ad312c7c 1840 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1841 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1842 goto out;
1843 return 0;
1844
1845out:
ad312c7c 1846 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1847 return r;
1848}
1849
07716717 1850static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1851 u32 index)
07716717
DK		 1852{
1853 entry->function = function;
1854 entry->index = index;
1855 cpuid_count(entry->function, entry->index,
19355475 1856 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1857 entry->flags = 0;
1858}
1859
7faa4ee1
AK		 1860#define F(x) bit(X86_FEATURE_##x)
1861
07716717
DK		 1862static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1863 u32 index, int *nent, int maxnent)
1864{
7faa4ee1 1865 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1866#ifdef CONFIG_X86_64
17cc3935
SY		 1867 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1868 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1869 unsigned f_lm = F(LM);
1870#else
17cc3935 1871 unsigned f_gbpages = 0;
7faa4ee1 1872 unsigned f_lm = 0;
07716717 1873#endif
4e47c7a6 1874 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1875
1876 /* cpuid 1.edx */
1877 const u32 kvm_supported_word0_x86_features =
1878 F(FPU) | F(VME) | F(DE) | F(PSE) |
1879 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1880 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1881 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1882 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1883 0 /* Reserved, DS, ACPI */ | F(MMX) |
1884 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1885 0 /* HTT, TM, Reserved, PBE */;
1886 /* cpuid 0x80000001.edx */
1887 const u32 kvm_supported_word1_x86_features =
1888 F(FPU) | F(VME) | F(DE) | F(PSE) |
1889 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1890 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1891 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1892 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1893 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1894 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1895 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1896 /* cpuid 1.ecx */
1897 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1898 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1899 0 /* DS-CPL, VMX, SMX, EST */ |
1900 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1901 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1902 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1903 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1904 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1905 /* cpuid 0x80000001.ecx */
07716717 1906 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1907 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1908 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1909 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1910 0 /* SKINIT */ | 0 /* WDT */;
07716717 1911
19355475 1912 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1913 get_cpu();
1914 do_cpuid_1_ent(entry, function, index);
1915 ++*nent;
1916
1917 switch (function) {
1918 case 0:
1919 entry->eax = min(entry->eax, (u32)0xb);
1920 break;
1921 case 1:
1922 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1923 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1924 /* we support x2apic emulation even if host does not support
1925 * it since we emulate x2apic in software */
1926 entry->ecx |= F(X2APIC);
07716717
DK		 1927 break;
1928 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1929 * may return different values. This forces us to get_cpu() before
1930 * issuing the first command, and also to emulate this annoying behavior
1931 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1932 case 2: {
1933 int t, times = entry->eax & 0xff;
1934
1935 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1936 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1937 for (t = 1; t < times && *nent < maxnent; ++t) {
1938 do_cpuid_1_ent(&entry[t], function, 0);
1939 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1940 ++*nent;
1941 }
1942 break;
1943 }
1944 /* function 4 and 0xb have additional index. */
1945 case 4: {
14af3f3c 1946 int i, cache_type;
07716717
DK		 1947
1948 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1949 /* read more entries until cache_type is zero */
14af3f3c
HH		 1950 for (i = 1; *nent < maxnent; ++i) {
1951 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1952 if (!cache_type)
1953 break;
14af3f3c
HH		 1954 do_cpuid_1_ent(&entry[i], function, i);
1955 entry[i].flags |=
07716717
DK		 1956 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1957 ++*nent;
1958 }
1959 break;
1960 }
1961 case 0xb: {
14af3f3c 1962 int i, level_type;
07716717
DK		 1963
1964 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1965 /* read more entries until level_type is zero */
14af3f3c 1966 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1967 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1968 if (!level_type)
1969 break;
14af3f3c
HH		 1970 do_cpuid_1_ent(&entry[i], function, i);
1971 entry[i].flags |=
07716717
DK		 1972 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1973 ++*nent;
1974 }
1975 break;
1976 }
84478c82
GC		 1977 case KVM_CPUID_SIGNATURE: {
1978 char signature[12] = "KVMKVMKVM\0\0";
1979 u32 *sigptr = (u32 *)signature;
1980 entry->eax = 0;
1981 entry->ebx = sigptr[0];
1982 entry->ecx = sigptr[1];
1983 entry->edx = sigptr[2];
1984 break;
1985 }
1986 case KVM_CPUID_FEATURES:
1987 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1988 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 1989 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1990 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 1991 entry->ebx = 0;
1992 entry->ecx = 0;
1993 entry->edx = 0;
1994 break;
07716717
DK		 1995 case 0x80000000:
1996 entry->eax = min(entry->eax, 0x8000001a);
1997 break;
1998 case 0x80000001:
1999 entry->edx &= kvm_supported_word1_x86_features;
2000 entry->ecx &= kvm_supported_word6_x86_features;
2001 break;
2002 }
d4330ef2
JR		 2003
2004 kvm_x86_ops->set_supported_cpuid(function, entry);
2005
07716717
DK		 2006 put_cpu();
2007}
2008
7faa4ee1
AK		 2009#undef F
2010
674eea0f 2011static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2012 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2013{
2014 struct kvm_cpuid_entry2 *cpuid_entries;
2015 int limit, nent = 0, r = -E2BIG;
2016 u32 func;
2017
2018 if (cpuid->nent < 1)
2019 goto out;
6a544355
AK		 2020 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2021 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2022 r = -ENOMEM;
2023 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2024 if (!cpuid_entries)
2025 goto out;
2026
2027 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2028 limit = cpuid_entries[0].eax;
2029 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2030 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2031 &nent, cpuid->nent);
07716717
DK		 2032 r = -E2BIG;
2033 if (nent >= cpuid->nent)
2034 goto out_free;
2035
2036 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2037 limit = cpuid_entries[nent - 1].eax;
2038 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2039 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2040 &nent, cpuid->nent);
84478c82
GC		 2041
2042
2043
2044 r = -E2BIG;
2045 if (nent >= cpuid->nent)
2046 goto out_free;
2047
2048 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2049 cpuid->nent);
2050
2051 r = -E2BIG;
2052 if (nent >= cpuid->nent)
2053 goto out_free;
2054
2055 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2056 cpuid->nent);
2057
cb007648
MM		 2058 r = -E2BIG;
2059 if (nent >= cpuid->nent)
2060 goto out_free;
2061
07716717
DK		 2062 r = -EFAULT;
2063 if (copy_to_user(entries, cpuid_entries,
19355475 2064 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2065 goto out_free;
2066 cpuid->nent = nent;
2067 r = 0;
2068
2069out_free:
2070 vfree(cpuid_entries);
2071out:
2072 return r;
2073}
2074
313a3dc7
CO		 2075static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2076 struct kvm_lapic_state *s)
2077{
2078 vcpu_load(vcpu);
ad312c7c 2079 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2080 vcpu_put(vcpu);
2081
2082 return 0;
2083}
2084
2085static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2086 struct kvm_lapic_state *s)
2087{
2088 vcpu_load(vcpu);
ad312c7c 2089 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2090 kvm_apic_post_state_restore(vcpu);
cb142eb7 2091 update_cr8_intercept(vcpu);
313a3dc7
CO		 2092 vcpu_put(vcpu);
2093
2094 return 0;
2095}
2096
f77bc6a4
ZX		 2097static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2098 struct kvm_interrupt *irq)
2099{
2100 if (irq->irq < 0 || irq->irq >= 256)
2101 return -EINVAL;
2102 if (irqchip_in_kernel(vcpu->kvm))
2103 return -ENXIO;
2104 vcpu_load(vcpu);
2105
66fd3f7f 2106 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2107
2108 vcpu_put(vcpu);
2109
2110 return 0;
2111}
2112
c4abb7c9
JK		 2113static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2114{
2115 vcpu_load(vcpu);
2116 kvm_inject_nmi(vcpu);
2117 vcpu_put(vcpu);
2118
2119 return 0;
2120}
2121
b209749f
AK		 2122static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2123 struct kvm_tpr_access_ctl *tac)
2124{
2125 if (tac->flags)
2126 return -EINVAL;
2127 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2128 return 0;
2129}
2130
890ca9ae
HY		 2131static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2132 u64 mcg_cap)
2133{
2134 int r;
2135 unsigned bank_num = mcg_cap & 0xff, bank;
2136
2137 r = -EINVAL;
a9e38c3e 2138 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2139 goto out;
2140 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2141 goto out;
2142 r = 0;
2143 vcpu->arch.mcg_cap = mcg_cap;
2144 /* Init IA32_MCG_CTL to all 1s */
2145 if (mcg_cap & MCG_CTL_P)
2146 vcpu->arch.mcg_ctl = ~(u64)0;
2147 /* Init IA32_MCi_CTL to all 1s */
2148 for (bank = 0; bank < bank_num; bank++)
2149 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2150out:
2151 return r;
2152}
2153
2154static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2155 struct kvm_x86_mce *mce)
2156{
2157 u64 mcg_cap = vcpu->arch.mcg_cap;
2158 unsigned bank_num = mcg_cap & 0xff;
2159 u64 *banks = vcpu->arch.mce_banks;
2160
2161 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2162 return -EINVAL;
2163 /*
2164 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2165 * reporting is disabled
2166 */
2167 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2168 vcpu->arch.mcg_ctl != ~(u64)0)
2169 return 0;
2170 banks += 4 * mce->bank;
2171 /*
2172 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2173 * reporting is disabled for the bank
2174 */
2175 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2176 return 0;
2177 if (mce->status & MCI_STATUS_UC) {
2178 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2179 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2180 printk(KERN_DEBUG "kvm: set_mce: "
2181 "injects mce exception while "
2182 "previous one is in progress!\n");
2183 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2184 return 0;
2185 }
2186 if (banks[1] & MCI_STATUS_VAL)
2187 mce->status |= MCI_STATUS_OVER;
2188 banks[2] = mce->addr;
2189 banks[3] = mce->misc;
2190 vcpu->arch.mcg_status = mce->mcg_status;
2191 banks[1] = mce->status;
2192 kvm_queue_exception(vcpu, MC_VECTOR);
2193 } else if (!(banks[1] & MCI_STATUS_VAL)
2194 || !(banks[1] & MCI_STATUS_UC)) {
2195 if (banks[1] & MCI_STATUS_VAL)
2196 mce->status |= MCI_STATUS_OVER;
2197 banks[2] = mce->addr;
2198 banks[3] = mce->misc;
2199 banks[1] = mce->status;
2200 } else
2201 banks[1] |= MCI_STATUS_OVER;
2202 return 0;
2203}
2204
3cfc3092
JK		 2205static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2206 struct kvm_vcpu_events *events)
2207{
2208 vcpu_load(vcpu);
2209
03b82a30
JK		 2210 events->exception.injected =
2211 vcpu->arch.exception.pending &&
2212 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2213 events->exception.nr = vcpu->arch.exception.nr;
2214 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2215 events->exception.error_code = vcpu->arch.exception.error_code;
2216
03b82a30
JK		 2217 events->interrupt.injected =
2218 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2219 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2220 events->interrupt.soft = 0;
48005f64
JK		 2221 events->interrupt.shadow =
2222 kvm_x86_ops->get_interrupt_shadow(vcpu,
2223 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2224
2225 events->nmi.injected = vcpu->arch.nmi_injected;
2226 events->nmi.pending = vcpu->arch.nmi_pending;
2227 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2228
2229 events->sipi_vector = vcpu->arch.sipi_vector;
2230
dab4b911 2231 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2232 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2233 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2234
2235 vcpu_put(vcpu);
2236}
2237
2238static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2239 struct kvm_vcpu_events *events)
2240{
dab4b911 2241 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2242 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2243 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2244 return -EINVAL;
2245
2246 vcpu_load(vcpu);
2247
2248 vcpu->arch.exception.pending = events->exception.injected;
2249 vcpu->arch.exception.nr = events->exception.nr;
2250 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2251 vcpu->arch.exception.error_code = events->exception.error_code;
2252
2253 vcpu->arch.interrupt.pending = events->interrupt.injected;
2254 vcpu->arch.interrupt.nr = events->interrupt.nr;
2255 vcpu->arch.interrupt.soft = events->interrupt.soft;
2256 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2257 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2258 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2259 kvm_x86_ops->set_interrupt_shadow(vcpu,
2260 events->interrupt.shadow);
3cfc3092
JK		 2261
2262 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2263 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2264 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2265 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2266
dab4b911
JK		 2267 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2268 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2269
2270 vcpu_put(vcpu);
2271
2272 return 0;
2273}
2274
a1efbe77
JK		 2275static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2276 struct kvm_debugregs *dbgregs)
2277{
2278 vcpu_load(vcpu);
2279
2280 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2281 dbgregs->dr6 = vcpu->arch.dr6;
2282 dbgregs->dr7 = vcpu->arch.dr7;
2283 dbgregs->flags = 0;
2284
2285 vcpu_put(vcpu);
2286}
2287
2288static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2289 struct kvm_debugregs *dbgregs)
2290{
2291 if (dbgregs->flags)
2292 return -EINVAL;
2293
2294 vcpu_load(vcpu);
2295
2296 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2297 vcpu->arch.dr6 = dbgregs->dr6;
2298 vcpu->arch.dr7 = dbgregs->dr7;
2299
2300 vcpu_put(vcpu);
2301
2302 return 0;
2303}
2304
313a3dc7
CO		 2305long kvm_arch_vcpu_ioctl(struct file *filp,
2306 unsigned int ioctl, unsigned long arg)
2307{
2308 struct kvm_vcpu *vcpu = filp->private_data;
2309 void __user *argp = (void __user *)arg;
2310 int r;
b772ff36 2311 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2312
2313 switch (ioctl) {
2314 case KVM_GET_LAPIC: {
2204ae3c
MT		 2315 r = -EINVAL;
2316 if (!vcpu->arch.apic)
2317 goto out;
b772ff36 2318 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2319
b772ff36
DH		 2320 r = -ENOMEM;
2321 if (!lapic)
2322 goto out;
2323 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2324 if (r)
2325 goto out;
2326 r = -EFAULT;
b772ff36 2327 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2328 goto out;
2329 r = 0;
2330 break;
2331 }
2332 case KVM_SET_LAPIC: {
2204ae3c
MT		 2333 r = -EINVAL;
2334 if (!vcpu->arch.apic)
2335 goto out;
b772ff36
DH		 2336 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2337 r = -ENOMEM;
2338 if (!lapic)
2339 goto out;
313a3dc7 2340 r = -EFAULT;
b772ff36 2341 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2342 goto out;
b772ff36 2343 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2344 if (r)
2345 goto out;
2346 r = 0;
2347 break;
2348 }
f77bc6a4
ZX		 2349 case KVM_INTERRUPT: {
2350 struct kvm_interrupt irq;
2351
2352 r = -EFAULT;
2353 if (copy_from_user(&irq, argp, sizeof irq))
2354 goto out;
2355 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2356 if (r)
2357 goto out;
2358 r = 0;
2359 break;
2360 }
c4abb7c9
JK		 2361 case KVM_NMI: {
2362 r = kvm_vcpu_ioctl_nmi(vcpu);
2363 if (r)
2364 goto out;
2365 r = 0;
2366 break;
2367 }
313a3dc7
CO		 2368 case KVM_SET_CPUID: {
2369 struct kvm_cpuid __user *cpuid_arg = argp;
2370 struct kvm_cpuid cpuid;
2371
2372 r = -EFAULT;
2373 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2374 goto out;
2375 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2376 if (r)
2377 goto out;
2378 break;
2379 }
07716717
DK		 2380 case KVM_SET_CPUID2: {
2381 struct kvm_cpuid2 __user *cpuid_arg = argp;
2382 struct kvm_cpuid2 cpuid;
2383
2384 r = -EFAULT;
2385 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2386 goto out;
2387 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2388 cpuid_arg->entries);
07716717
DK		 2389 if (r)
2390 goto out;
2391 break;
2392 }
2393 case KVM_GET_CPUID2: {
2394 struct kvm_cpuid2 __user *cpuid_arg = argp;
2395 struct kvm_cpuid2 cpuid;
2396
2397 r = -EFAULT;
2398 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2399 goto out;
2400 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2401 cpuid_arg->entries);
07716717
DK		 2402 if (r)
2403 goto out;
2404 r = -EFAULT;
2405 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2406 goto out;
2407 r = 0;
2408 break;
2409 }
313a3dc7
CO		 2410 case KVM_GET_MSRS:
2411 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2412 break;
2413 case KVM_SET_MSRS:
2414 r = msr_io(vcpu, argp, do_set_msr, 0);
2415 break;
b209749f
AK		 2416 case KVM_TPR_ACCESS_REPORTING: {
2417 struct kvm_tpr_access_ctl tac;
2418
2419 r = -EFAULT;
2420 if (copy_from_user(&tac, argp, sizeof tac))
2421 goto out;
2422 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2423 if (r)
2424 goto out;
2425 r = -EFAULT;
2426 if (copy_to_user(argp, &tac, sizeof tac))
2427 goto out;
2428 r = 0;
2429 break;
2430 };
b93463aa
AK		 2431 case KVM_SET_VAPIC_ADDR: {
2432 struct kvm_vapic_addr va;
2433
2434 r = -EINVAL;
2435 if (!irqchip_in_kernel(vcpu->kvm))
2436 goto out;
2437 r = -EFAULT;
2438 if (copy_from_user(&va, argp, sizeof va))
2439 goto out;
2440 r = 0;
2441 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2442 break;
2443 }
890ca9ae
HY		 2444 case KVM_X86_SETUP_MCE: {
2445 u64 mcg_cap;
2446
2447 r = -EFAULT;
2448 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2449 goto out;
2450 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2451 break;
2452 }
2453 case KVM_X86_SET_MCE: {
2454 struct kvm_x86_mce mce;
2455
2456 r = -EFAULT;
2457 if (copy_from_user(&mce, argp, sizeof mce))
2458 goto out;
2459 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2460 break;
2461 }
3cfc3092
JK		 2462 case KVM_GET_VCPU_EVENTS: {
2463 struct kvm_vcpu_events events;
2464
2465 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2466
2467 r = -EFAULT;
2468 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2469 break;
2470 r = 0;
2471 break;
2472 }
2473 case KVM_SET_VCPU_EVENTS: {
2474 struct kvm_vcpu_events events;
2475
2476 r = -EFAULT;
2477 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2478 break;
2479
2480 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2481 break;
2482 }
a1efbe77
JK		 2483 case KVM_GET_DEBUGREGS: {
2484 struct kvm_debugregs dbgregs;
2485
2486 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2487
2488 r = -EFAULT;
2489 if (copy_to_user(argp, &dbgregs,
2490 sizeof(struct kvm_debugregs)))
2491 break;
2492 r = 0;
2493 break;
2494 }
2495 case KVM_SET_DEBUGREGS: {
2496 struct kvm_debugregs dbgregs;
2497
2498 r = -EFAULT;
2499 if (copy_from_user(&dbgregs, argp,
2500 sizeof(struct kvm_debugregs)))
2501 break;
2502
2503 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2504 break;
2505 }
313a3dc7
CO		 2506 default:
2507 r = -EINVAL;
2508 }
2509out:
7a6ce84c 2510 kfree(lapic);
313a3dc7
CO		 2511 return r;
2512}
2513
1fe779f8
CO		 2514static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2515{
2516 int ret;
2517
2518 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2519 return -1;
2520 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2521 return ret;
2522}
2523
b927a3ce
SY		 2524static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2525 u64 ident_addr)
2526{
2527 kvm->arch.ept_identity_map_addr = ident_addr;
2528 return 0;
2529}
2530
1fe779f8
CO		 2531static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2532 u32 kvm_nr_mmu_pages)
2533{
2534 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2535 return -EINVAL;
2536
79fac95e 2537 mutex_lock(&kvm->slots_lock);
7c8a83b7 2538 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2539
2540 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2541 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2542
7c8a83b7 2543 spin_unlock(&kvm->mmu_lock);
79fac95e 2544 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2545 return 0;
2546}
2547
2548static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2549{
f05e70ac 2550 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2551}
2552
a983fb23
MT		 2553gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2554{
2555 int i;
2556 struct kvm_mem_alias *alias;
2557 struct kvm_mem_aliases *aliases;
2558
90d83dc3 2559 aliases = kvm_aliases(kvm);
a983fb23
MT		 2560
2561 for (i = 0; i < aliases->naliases; ++i) {
2562 alias = &aliases->aliases[i];
2563 if (alias->flags & KVM_ALIAS_INVALID)
2564 continue;
2565 if (gfn >= alias->base_gfn
2566 && gfn < alias->base_gfn + alias->npages)
2567 return alias->target_gfn + gfn - alias->base_gfn;
2568 }
2569 return gfn;
2570}
2571
e9f85cde
ZX		 2572gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2573{
2574 int i;
2575 struct kvm_mem_alias *alias;
a983fb23
MT		 2576 struct kvm_mem_aliases *aliases;
2577
90d83dc3 2578 aliases = kvm_aliases(kvm);
e9f85cde 2579
fef9cce0
MT		 2580 for (i = 0; i < aliases->naliases; ++i) {
2581 alias = &aliases->aliases[i];
e9f85cde
ZX		 2582 if (gfn >= alias->base_gfn
2583 && gfn < alias->base_gfn + alias->npages)
2584 return alias->target_gfn + gfn - alias->base_gfn;
2585 }
2586 return gfn;
2587}
2588
1fe779f8
CO		 2589/*
2590 * Set a new alias region. Aliases map a portion of physical memory into
2591 * another portion. This is useful for memory windows, for example the PC
2592 * VGA region.
2593 */
2594static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2595 struct kvm_memory_alias *alias)
2596{
2597 int r, n;
2598 struct kvm_mem_alias *p;
a983fb23 2599 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2600
2601 r = -EINVAL;
2602 /* General sanity checks */
2603 if (alias->memory_size & (PAGE_SIZE - 1))
2604 goto out;
2605 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2606 goto out;
2607 if (alias->slot >= KVM_ALIAS_SLOTS)
2608 goto out;
2609 if (alias->guest_phys_addr + alias->memory_size
2610 < alias->guest_phys_addr)
2611 goto out;
2612 if (alias->target_phys_addr + alias->memory_size
2613 < alias->target_phys_addr)
2614 goto out;
2615
a983fb23
MT		 2616 r = -ENOMEM;
2617 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2618 if (!aliases)
2619 goto out;
2620
79fac95e 2621 mutex_lock(&kvm->slots_lock);
1fe779f8 2622
a983fb23
MT		 2623 /* invalidate any gfn reference in case of deletion/shrinking */
2624 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2625 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2626 old_aliases = kvm->arch.aliases;
2627 rcu_assign_pointer(kvm->arch.aliases, aliases);
2628 synchronize_srcu_expedited(&kvm->srcu);
2629 kvm_mmu_zap_all(kvm);
2630 kfree(old_aliases);
2631
2632 r = -ENOMEM;
2633 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2634 if (!aliases)
2635 goto out_unlock;
2636
2637 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2638
2639 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2640 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2641 p->npages = alias->memory_size >> PAGE_SHIFT;
2642 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2643 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2644
2645 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2646 if (aliases->aliases[n - 1].npages)
1fe779f8 2647 break;
fef9cce0 2648 aliases->naliases = n;
1fe779f8 2649
a983fb23
MT		 2650 old_aliases = kvm->arch.aliases;
2651 rcu_assign_pointer(kvm->arch.aliases, aliases);
2652 synchronize_srcu_expedited(&kvm->srcu);
2653 kfree(old_aliases);
2654 r = 0;
1fe779f8 2655
a983fb23 2656out_unlock:
79fac95e 2657 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2658out:
2659 return r;
2660}
2661
2662static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2663{
2664 int r;
2665
2666 r = 0;
2667 switch (chip->chip_id) {
2668 case KVM_IRQCHIP_PIC_MASTER:
2669 memcpy(&chip->chip.pic,
2670 &pic_irqchip(kvm)->pics[0],
2671 sizeof(struct kvm_pic_state));
2672 break;
2673 case KVM_IRQCHIP_PIC_SLAVE:
2674 memcpy(&chip->chip.pic,
2675 &pic_irqchip(kvm)->pics[1],
2676 sizeof(struct kvm_pic_state));
2677 break;
2678 case KVM_IRQCHIP_IOAPIC:
eba0226b 2679 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2680 break;
2681 default:
2682 r = -EINVAL;
2683 break;
2684 }
2685 return r;
2686}
2687
2688static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2689{
2690 int r;
2691
2692 r = 0;
2693 switch (chip->chip_id) {
2694 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2695 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2696 memcpy(&pic_irqchip(kvm)->pics[0],
2697 &chip->chip.pic,
2698 sizeof(struct kvm_pic_state));
fa8273e9 2699 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2700 break;
2701 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2702 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2703 memcpy(&pic_irqchip(kvm)->pics[1],
2704 &chip->chip.pic,
2705 sizeof(struct kvm_pic_state));
fa8273e9 2706 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2707 break;
2708 case KVM_IRQCHIP_IOAPIC:
eba0226b 2709 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2710 break;
2711 default:
2712 r = -EINVAL;
2713 break;
2714 }
2715 kvm_pic_update_irq(pic_irqchip(kvm));
2716 return r;
2717}
2718
e0f63cb9
SY		 2719static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2720{
2721 int r = 0;
2722
894a9c55 2723 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2724 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2725 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2726 return r;
2727}
2728
2729static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2730{
2731 int r = 0;
2732
894a9c55 2733 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2734 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2735 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2736 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2737 return r;
2738}
2739
2740static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2741{
2742 int r = 0;
2743
2744 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2745 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2746 sizeof(ps->channels));
2747 ps->flags = kvm->arch.vpit->pit_state.flags;
2748 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2749 return r;
2750}
2751
2752static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2753{
2754 int r = 0, start = 0;
2755 u32 prev_legacy, cur_legacy;
2756 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2757 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2758 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2759 if (!prev_legacy && cur_legacy)
2760 start = 1;
2761 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2762 sizeof(kvm->arch.vpit->pit_state.channels));
2763 kvm->arch.vpit->pit_state.flags = ps->flags;
2764 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2765 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2766 return r;
2767}
2768
52d939a0
MT		 2769static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2770 struct kvm_reinject_control *control)
2771{
2772 if (!kvm->arch.vpit)
2773 return -ENXIO;
894a9c55 2774 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2775 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2776 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2777 return 0;
2778}
2779
5bb064dc
ZX		 2780/*
2781 * Get (and clear) the dirty memory log for a memory slot.
2782 */
2783int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2784 struct kvm_dirty_log *log)
2785{
87bf6e7d 2786 int r, i;
5bb064dc 2787 struct kvm_memory_slot *memslot;
87bf6e7d 2788 unsigned long n;
b050b015
MT		 2789 unsigned long is_dirty = 0;
2790 unsigned long *dirty_bitmap = NULL;
5bb064dc 2791
79fac95e 2792 mutex_lock(&kvm->slots_lock);
5bb064dc 2793
b050b015
MT		 2794 r = -EINVAL;
2795 if (log->slot >= KVM_MEMORY_SLOTS)
2796 goto out;
2797
2798 memslot = &kvm->memslots->memslots[log->slot];
2799 r = -ENOENT;
2800 if (!memslot->dirty_bitmap)
2801 goto out;
2802
87bf6e7d 2803 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2804
2805 r = -ENOMEM;
2806 dirty_bitmap = vmalloc(n);
2807 if (!dirty_bitmap)
5bb064dc 2808 goto out;
b050b015
MT		 2809 memset(dirty_bitmap, 0, n);
2810
2811 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2812 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2813
2814 /* If nothing is dirty, don't bother messing with page tables. */
2815 if (is_dirty) {
b050b015
MT		 2816 struct kvm_memslots *slots, *old_slots;
2817
7c8a83b7 2818 spin_lock(&kvm->mmu_lock);
5bb064dc 2819 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2820 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2821
2822 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2823 if (!slots)
2824 goto out_free;
2825
2826 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2827 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2828
2829 old_slots = kvm->memslots;
2830 rcu_assign_pointer(kvm->memslots, slots);
2831 synchronize_srcu_expedited(&kvm->srcu);
2832 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2833 kfree(old_slots);
5bb064dc 2834 }
b050b015 2835
5bb064dc 2836 r = 0;
b050b015
MT		 2837 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2838 r = -EFAULT;
2839out_free:
2840 vfree(dirty_bitmap);
5bb064dc 2841out:
79fac95e 2842 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2843 return r;
2844}
2845
1fe779f8
CO		 2846long kvm_arch_vm_ioctl(struct file *filp,
2847 unsigned int ioctl, unsigned long arg)
2848{
2849 struct kvm *kvm = filp->private_data;
2850 void __user *argp = (void __user *)arg;
367e1319 2851 int r = -ENOTTY;
f0d66275
DH		 2852 /*
2853 * This union makes it completely explicit to gcc-3.x
2854 * that these two variables' stack usage should be
2855 * combined, not added together.
2856 */
2857 union {
2858 struct kvm_pit_state ps;
e9f42757 2859 struct kvm_pit_state2 ps2;
f0d66275 2860 struct kvm_memory_alias alias;
c5ff41ce 2861 struct kvm_pit_config pit_config;
f0d66275 2862 } u;
1fe779f8
CO		 2863
2864 switch (ioctl) {
2865 case KVM_SET_TSS_ADDR:
2866 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2867 if (r < 0)
2868 goto out;
2869 break;
b927a3ce
SY		 2870 case KVM_SET_IDENTITY_MAP_ADDR: {
2871 u64 ident_addr;
2872
2873 r = -EFAULT;
2874 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2875 goto out;
2876 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2877 if (r < 0)
2878 goto out;
2879 break;
2880 }
1fe779f8
CO		 2881 case KVM_SET_MEMORY_REGION: {
2882 struct kvm_memory_region kvm_mem;
2883 struct kvm_userspace_memory_region kvm_userspace_mem;
2884
2885 r = -EFAULT;
2886 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2887 goto out;
2888 kvm_userspace_mem.slot = kvm_mem.slot;
2889 kvm_userspace_mem.flags = kvm_mem.flags;
2890 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2891 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2892 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2893 if (r)
2894 goto out;
2895 break;
2896 }
2897 case KVM_SET_NR_MMU_PAGES:
2898 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2899 if (r)
2900 goto out;
2901 break;
2902 case KVM_GET_NR_MMU_PAGES:
2903 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2904 break;
f0d66275 2905 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2906 r = -EFAULT;
f0d66275 2907 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2908 goto out;
f0d66275 2909 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2910 if (r)
2911 goto out;
2912 break;
3ddea128
MT		 2913 case KVM_CREATE_IRQCHIP: {
2914 struct kvm_pic *vpic;
2915
2916 mutex_lock(&kvm->lock);
2917 r = -EEXIST;
2918 if (kvm->arch.vpic)
2919 goto create_irqchip_unlock;
1fe779f8 2920 r = -ENOMEM;
3ddea128
MT		 2921 vpic = kvm_create_pic(kvm);
2922 if (vpic) {
1fe779f8
CO		 2923 r = kvm_ioapic_init(kvm);
2924 if (r) {
72bb2fcd
WY		 2925 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2926 &vpic->dev);
3ddea128
MT		 2927 kfree(vpic);
2928 goto create_irqchip_unlock;
1fe779f8
CO		 2929 }
2930 } else
3ddea128
MT		 2931 goto create_irqchip_unlock;
2932 smp_wmb();
2933 kvm->arch.vpic = vpic;
2934 smp_wmb();
399ec807
AK		 2935 r = kvm_setup_default_irq_routing(kvm);
2936 if (r) {
3ddea128 2937 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2938 kvm_ioapic_destroy(kvm);
2939 kvm_destroy_pic(kvm);
3ddea128 2940 mutex_unlock(&kvm->irq_lock);
399ec807 2941 }
3ddea128
MT		 2942 create_irqchip_unlock:
2943 mutex_unlock(&kvm->lock);
1fe779f8 2944 break;
3ddea128 2945 }
7837699f 2946 case KVM_CREATE_PIT:
c5ff41ce
JK		 2947 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2948 goto create_pit;
2949 case KVM_CREATE_PIT2:
2950 r = -EFAULT;
2951 if (copy_from_user(&u.pit_config, argp,
2952 sizeof(struct kvm_pit_config)))
2953 goto out;
2954 create_pit:
79fac95e 2955 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2956 r = -EEXIST;
2957 if (kvm->arch.vpit)
2958 goto create_pit_unlock;
7837699f 2959 r = -ENOMEM;
c5ff41ce 2960 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2961 if (kvm->arch.vpit)
2962 r = 0;
269e05e4 2963 create_pit_unlock:
79fac95e 2964 mutex_unlock(&kvm->slots_lock);
7837699f 2965 break;
4925663a 2966 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2967 case KVM_IRQ_LINE: {
2968 struct kvm_irq_level irq_event;
2969
2970 r = -EFAULT;
2971 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2972 goto out;
160d2f6c 2973 r = -ENXIO;
1fe779f8 2974 if (irqchip_in_kernel(kvm)) {
4925663a 2975 __s32 status;
4925663a
GN		 2976 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2977 irq_event.irq, irq_event.level);
4925663a 2978 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2979 r = -EFAULT;
4925663a
GN		 2980 irq_event.status = status;
2981 if (copy_to_user(argp, &irq_event,
2982 sizeof irq_event))
2983 goto out;
2984 }
1fe779f8
CO		 2985 r = 0;
2986 }
2987 break;
2988 }
2989 case KVM_GET_IRQCHIP: {
2990 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2991 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2992
f0d66275
DH		 2993 r = -ENOMEM;
2994 if (!chip)
1fe779f8 2995 goto out;
f0d66275
DH		 2996 r = -EFAULT;
2997 if (copy_from_user(chip, argp, sizeof *chip))
2998 goto get_irqchip_out;
1fe779f8
CO		 2999 r = -ENXIO;
3000 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3001 goto get_irqchip_out;
3002 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3003 if (r)
f0d66275 3004 goto get_irqchip_out;
1fe779f8 3005 r = -EFAULT;
f0d66275
DH		 3006 if (copy_to_user(argp, chip, sizeof *chip))
3007 goto get_irqchip_out;
1fe779f8 3008 r = 0;
f0d66275
DH		 3009 get_irqchip_out:
3010 kfree(chip);
3011 if (r)
3012 goto out;
1fe779f8
CO		 3013 break;
3014 }
3015 case KVM_SET_IRQCHIP: {
3016 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3017 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3018
f0d66275
DH		 3019 r = -ENOMEM;
3020 if (!chip)
1fe779f8 3021 goto out;
f0d66275
DH		 3022 r = -EFAULT;
3023 if (copy_from_user(chip, argp, sizeof *chip))
3024 goto set_irqchip_out;
1fe779f8
CO		 3025 r = -ENXIO;
3026 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3027 goto set_irqchip_out;
3028 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3029 if (r)
f0d66275 3030 goto set_irqchip_out;
1fe779f8 3031 r = 0;
f0d66275
DH		 3032 set_irqchip_out:
3033 kfree(chip);
3034 if (r)
3035 goto out;
1fe779f8
CO		 3036 break;
3037 }
e0f63cb9 3038 case KVM_GET_PIT: {
e0f63cb9 3039 r = -EFAULT;
f0d66275 3040 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3041 goto out;
3042 r = -ENXIO;
3043 if (!kvm->arch.vpit)
3044 goto out;
f0d66275 3045 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3046 if (r)
3047 goto out;
3048 r = -EFAULT;
f0d66275 3049 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3050 goto out;
3051 r = 0;
3052 break;
3053 }
3054 case KVM_SET_PIT: {
e0f63cb9 3055 r = -EFAULT;
f0d66275 3056 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3057 goto out;
3058 r = -ENXIO;
3059 if (!kvm->arch.vpit)
3060 goto out;
f0d66275 3061 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3062 if (r)
3063 goto out;
3064 r = 0;
3065 break;
3066 }
e9f42757
BK		 3067 case KVM_GET_PIT2: {
3068 r = -ENXIO;
3069 if (!kvm->arch.vpit)
3070 goto out;
3071 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3072 if (r)
3073 goto out;
3074 r = -EFAULT;
3075 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3076 goto out;
3077 r = 0;
3078 break;
3079 }
3080 case KVM_SET_PIT2: {
3081 r = -EFAULT;
3082 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3083 goto out;
3084 r = -ENXIO;
3085 if (!kvm->arch.vpit)
3086 goto out;
3087 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3088 if (r)
3089 goto out;
3090 r = 0;
3091 break;
3092 }
52d939a0
MT		 3093 case KVM_REINJECT_CONTROL: {
3094 struct kvm_reinject_control control;
3095 r = -EFAULT;
3096 if (copy_from_user(&control, argp, sizeof(control)))
3097 goto out;
3098 r = kvm_vm_ioctl_reinject(kvm, &control);
3099 if (r)
3100 goto out;
3101 r = 0;
3102 break;
3103 }
ffde22ac
ES		 3104 case KVM_XEN_HVM_CONFIG: {
3105 r = -EFAULT;
3106 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3107 sizeof(struct kvm_xen_hvm_config)))
3108 goto out;
3109 r = -EINVAL;
3110 if (kvm->arch.xen_hvm_config.flags)
3111 goto out;
3112 r = 0;
3113 break;
3114 }
afbcf7ab
GC		 3115 case KVM_SET_CLOCK: {
3116 struct timespec now;
3117 struct kvm_clock_data user_ns;
3118 u64 now_ns;
3119 s64 delta;
3120
3121 r = -EFAULT;
3122 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3123 goto out;
3124
3125 r = -EINVAL;
3126 if (user_ns.flags)
3127 goto out;
3128
3129 r = 0;
3130 ktime_get_ts(&now);
3131 now_ns = timespec_to_ns(&now);
3132 delta = user_ns.clock - now_ns;
3133 kvm->arch.kvmclock_offset = delta;
3134 break;
3135 }
3136 case KVM_GET_CLOCK: {
3137 struct timespec now;
3138 struct kvm_clock_data user_ns;
3139 u64 now_ns;
3140
3141 ktime_get_ts(&now);
3142 now_ns = timespec_to_ns(&now);
3143 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3144 user_ns.flags = 0;
3145
3146 r = -EFAULT;
3147 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3148 goto out;
3149 r = 0;
3150 break;
3151 }
3152
1fe779f8
CO		 3153 default:
3154 ;
3155 }
3156out:
3157 return r;
3158}
3159
a16b043c 3160static void kvm_init_msr_list(void)
043405e1
CO		 3161{
3162 u32 dummy[2];
3163 unsigned i, j;
3164
e3267cbb
GC		 3165 /* skip the first msrs in the list. KVM-specific */
3166 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3167 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3168 continue;
3169 if (j < i)
3170 msrs_to_save[j] = msrs_to_save[i];
3171 j++;
3172 }
3173 num_msrs_to_save = j;
3174}
3175
bda9020e
MT		 3176static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3177 const void *v)
bbd9b64e 3178{
bda9020e
MT		 3179 if (vcpu->arch.apic &&
3180 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3181 return 0;
bbd9b64e 3182
e93f8a0f 3183 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3184}
3185
bda9020e 3186static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3187{
bda9020e
MT		 3188 if (vcpu->arch.apic &&
3189 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3190 return 0;
bbd9b64e 3191
e93f8a0f 3192 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3193}
3194
2dafc6c2
GN		 3195static void kvm_set_segment(struct kvm_vcpu *vcpu,
3196 struct kvm_segment *var, int seg)
3197{
3198 kvm_x86_ops->set_segment(vcpu, var, seg);
3199}
3200
3201void kvm_get_segment(struct kvm_vcpu *vcpu,
3202 struct kvm_segment *var, int seg)
3203{
3204 kvm_x86_ops->get_segment(vcpu, var, seg);
3205}
3206
1871c602
GN		 3207gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3208{
3209 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3210 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3211}
3212
3213 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3214{
3215 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3216 access |= PFERR_FETCH_MASK;
3217 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3218}
3219
3220gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3221{
3222 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3223 access |= PFERR_WRITE_MASK;
3224 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3225}
3226
3227/* uses this to access any guest's mapped memory without checking CPL */
3228gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3229{
3230 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3231}
3232
3233static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3234 struct kvm_vcpu *vcpu, u32 access,
3235 u32 *error)
bbd9b64e
CO		 3236{
3237 void *data = val;
10589a46 3238 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3239
3240 while (bytes) {
1871c602 3241 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3242 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3243 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3244 int ret;
3245
10589a46
MT		 3246 if (gpa == UNMAPPED_GVA) {
3247 r = X86EMUL_PROPAGATE_FAULT;
3248 goto out;
3249 }
77c2002e 3250 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3251 if (ret < 0) {
3252 r = X86EMUL_UNHANDLEABLE;
3253 goto out;
3254 }
bbd9b64e 3255
77c2002e
IE		 3256 bytes -= toread;
3257 data += toread;
3258 addr += toread;
bbd9b64e 3259 }
10589a46 3260out:
10589a46 3261 return r;
bbd9b64e 3262}
77c2002e 3263
1871c602
GN		 3264/* used for instruction fetching */
3265static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3266 struct kvm_vcpu *vcpu, u32 *error)
3267{
3268 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3269 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3270 access | PFERR_FETCH_MASK, error);
3271}
3272
3273static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3274 struct kvm_vcpu *vcpu, u32 *error)
3275{
3276 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3277 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3278 error);
3279}
3280
3281static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3282 struct kvm_vcpu *vcpu, u32 *error)
3283{
3284 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3285}
3286
7972995b 3287static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3288 unsigned int bytes,
7972995b 3289 struct kvm_vcpu *vcpu,
2dafc6c2 3290 u32 *error)
77c2002e
IE		 3291{
3292 void *data = val;
3293 int r = X86EMUL_CONTINUE;
3294
3295 while (bytes) {
7972995b
GN		 3296 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3297 PFERR_WRITE_MASK, error);
77c2002e
IE		 3298 unsigned offset = addr & (PAGE_SIZE-1);
3299 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3300 int ret;
3301
3302 if (gpa == UNMAPPED_GVA) {
3303 r = X86EMUL_PROPAGATE_FAULT;
3304 goto out;
3305 }
3306 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3307 if (ret < 0) {
3308 r = X86EMUL_UNHANDLEABLE;
3309 goto out;
3310 }
3311
3312 bytes -= towrite;
3313 data += towrite;
3314 addr += towrite;
3315 }
3316out:
3317 return r;
3318}
3319
bbd9b64e
CO		 3320static int emulator_read_emulated(unsigned long addr,
3321 void *val,
3322 unsigned int bytes,
3323 struct kvm_vcpu *vcpu)
3324{
bbd9b64e 3325 gpa_t gpa;
1871c602 3326 u32 error_code;
bbd9b64e
CO		 3327
3328 if (vcpu->mmio_read_completed) {
3329 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3330 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3331 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3332 vcpu->mmio_read_completed = 0;
3333 return X86EMUL_CONTINUE;
3334 }
3335
1871c602
GN		 3336 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3337
3338 if (gpa == UNMAPPED_GVA) {
3339 kvm_inject_page_fault(vcpu, addr, error_code);
3340 return X86EMUL_PROPAGATE_FAULT;
3341 }
bbd9b64e
CO		 3342
3343 /* For APIC access vmexit */
3344 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3345 goto mmio;
3346
1871c602 3347 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3348 == X86EMUL_CONTINUE)
bbd9b64e 3349 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3350
3351mmio:
3352 /*
3353 * Is this MMIO handled locally?
3354 */
aec51dc4
AK		 3355 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3356 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3357 return X86EMUL_CONTINUE;
3358 }
aec51dc4
AK		 3359
3360 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3361
3362 vcpu->mmio_needed = 1;
3363 vcpu->mmio_phys_addr = gpa;
3364 vcpu->mmio_size = bytes;
3365 vcpu->mmio_is_write = 0;
3366
3367 return X86EMUL_UNHANDLEABLE;
3368}
3369
3200f405 3370int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3371 const void *val, int bytes)
bbd9b64e
CO		 3372{
3373 int ret;
3374
3375 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3376 if (ret < 0)
bbd9b64e 3377 return 0;
ad218f85 3378 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3379 return 1;
3380}
3381
3382static int emulator_write_emulated_onepage(unsigned long addr,
3383 const void *val,
3384 unsigned int bytes,
8f6abd06 3385 struct kvm_vcpu *vcpu)
bbd9b64e 3386{
10589a46 3387 gpa_t gpa;
1871c602 3388 u32 error_code;
10589a46 3389
1871c602 3390 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3391
3392 if (gpa == UNMAPPED_GVA) {
1871c602 3393 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3394 return X86EMUL_PROPAGATE_FAULT;
3395 }
3396
3397 /* For APIC access vmexit */
3398 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3399 goto mmio;
3400
3401 if (emulator_write_phys(vcpu, gpa, val, bytes))
3402 return X86EMUL_CONTINUE;
3403
3404mmio:
aec51dc4 3405 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3406 /*
3407 * Is this MMIO handled locally?
3408 */
bda9020e 3409 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3410 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3411
3412 vcpu->mmio_needed = 1;
3413 vcpu->mmio_phys_addr = gpa;
3414 vcpu->mmio_size = bytes;
3415 vcpu->mmio_is_write = 1;
3416 memcpy(vcpu->mmio_data, val, bytes);
3417
3418 return X86EMUL_CONTINUE;
3419}
3420
8f6abd06
GN		 3421int emulator_write_emulated(unsigned long addr,
3422 const void *val,
3423 unsigned int bytes,
3424 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3425{
3426 /* Crossing a page boundary? */
3427 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3428 int rc, now;
3429
3430 now = -addr & ~PAGE_MASK;
8f6abd06 3431 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
bbd9b64e
CO		 3432 if (rc != X86EMUL_CONTINUE)
3433 return rc;
3434 addr += now;
3435 val += now;
3436 bytes -= now;
3437 }
8f6abd06 3438 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
bbd9b64e
CO		 3439}
3440EXPORT_SYMBOL_GPL(emulator_write_emulated);
3441
daea3e73
AK		 3442#define CMPXCHG_TYPE(t, ptr, old, new) \
3443 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3444
3445#ifdef CONFIG_X86_64
3446# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3447#else
3448# define CMPXCHG64(ptr, old, new) \
9749a6c0 3449 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3450#endif
3451
bbd9b64e
CO		 3452static int emulator_cmpxchg_emulated(unsigned long addr,
3453 const void *old,
3454 const void *new,
3455 unsigned int bytes,
3456 struct kvm_vcpu *vcpu)
3457{
daea3e73
AK		 3458 gpa_t gpa;
3459 struct page *page;
3460 char *kaddr;
3461 bool exchanged;
2bacc55c 3462
daea3e73
AK		 3463 /* guests cmpxchg8b have to be emulated atomically */
3464 if (bytes > 8 || (bytes & (bytes - 1)))
3465 goto emul_write;
10589a46 3466
daea3e73 3467 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3468
daea3e73
AK		 3469 if (gpa == UNMAPPED_GVA ||
3470 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3471 goto emul_write;
2bacc55c 3472
daea3e73
AK		 3473 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3474 goto emul_write;
72dc67a6 3475
daea3e73 3476 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3477
daea3e73
AK		 3478 kaddr = kmap_atomic(page, KM_USER0);
3479 kaddr += offset_in_page(gpa);
3480 switch (bytes) {
3481 case 1:
3482 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3483 break;
3484 case 2:
3485 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3486 break;
3487 case 4:
3488 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3489 break;
3490 case 8:
3491 exchanged = CMPXCHG64(kaddr, old, new);
3492 break;
3493 default:
3494 BUG();
2bacc55c 3495 }
daea3e73
AK		 3496 kunmap_atomic(kaddr, KM_USER0);
3497 kvm_release_page_dirty(page);
3498
3499 if (!exchanged)
3500 return X86EMUL_CMPXCHG_FAILED;
3501
8f6abd06
GN		 3502 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3503
3504 return X86EMUL_CONTINUE;
4a5f48f6 3505
3200f405 3506emul_write:
daea3e73 3507 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3508
bbd9b64e
CO		 3509 return emulator_write_emulated(addr, new, bytes, vcpu);
3510}
3511
cf8f70bf
GN		 3512static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3513{
3514 /* TODO: String I/O for in kernel device */
3515 int r;
3516
3517 if (vcpu->arch.pio.in)
3518 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3519 vcpu->arch.pio.size, pd);
3520 else
3521 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3522 vcpu->arch.pio.port, vcpu->arch.pio.size,
3523 pd);
3524 return r;
3525}
3526
3527
3528static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3529 unsigned int count, struct kvm_vcpu *vcpu)
3530{
7972995b 3531 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3532 goto data_avail;
3533
3534 trace_kvm_pio(1, port, size, 1);
3535
3536 vcpu->arch.pio.port = port;
3537 vcpu->arch.pio.in = 1;
7972995b 3538 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3539 vcpu->arch.pio.size = size;
3540
3541 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3542 data_avail:
3543 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3544 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3545 return 1;
3546 }
3547
3548 vcpu->run->exit_reason = KVM_EXIT_IO;
3549 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3550 vcpu->run->io.size = size;
3551 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3552 vcpu->run->io.count = count;
3553 vcpu->run->io.port = port;
3554
3555 return 0;
3556}
3557
3558static int emulator_pio_out_emulated(int size, unsigned short port,
3559 const void *val, unsigned int count,
3560 struct kvm_vcpu *vcpu)
3561{
3562 trace_kvm_pio(0, port, size, 1);
3563
3564 vcpu->arch.pio.port = port;
3565 vcpu->arch.pio.in = 0;
7972995b 3566 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3567 vcpu->arch.pio.size = size;
3568
3569 memcpy(vcpu->arch.pio_data, val, size * count);
3570
3571 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3572 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3573 return 1;
3574 }
3575
3576 vcpu->run->exit_reason = KVM_EXIT_IO;
3577 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3578 vcpu->run->io.size = size;
3579 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3580 vcpu->run->io.count = count;
3581 vcpu->run->io.port = port;
3582
3583 return 0;
3584}
3585
bbd9b64e
CO		 3586static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3587{
3588 return kvm_x86_ops->get_segment_base(vcpu, seg);
3589}
3590
3591int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3592{
a7052897 3593 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3594 return X86EMUL_CONTINUE;
3595}
3596
3597int emulate_clts(struct kvm_vcpu *vcpu)
3598{
4d4ec087 3599 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3600 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3601 return X86EMUL_CONTINUE;
3602}
3603
3604int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3605{
020df079 3606 return kvm_get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3607}
3608
3609int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3610{
3611 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3612
020df079 3613 return kvm_set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3614}
3615
3616void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3617{
bbd9b64e 3618 u8 opcodes[4];
5fdbf976 3619 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3620 unsigned long rip_linear;
3621
f76c710d 3622 if (!printk_ratelimit())
bbd9b64e
CO		 3623 return;
3624
25be4608
GC		 3625 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3626
1871c602 3627 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3628
3629 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3630 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3631}
3632EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3633
52a46617
GN		 3634static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3635{
3636 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3637}
3638
3639static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
3640{
3641 unsigned long value;
3642
3643 switch (cr) {
3644 case 0:
3645 value = kvm_read_cr0(vcpu);
3646 break;
3647 case 2:
3648 value = vcpu->arch.cr2;
3649 break;
3650 case 3:
3651 value = vcpu->arch.cr3;
3652 break;
3653 case 4:
3654 value = kvm_read_cr4(vcpu);
3655 break;
3656 case 8:
3657 value = kvm_get_cr8(vcpu);
3658 break;
3659 default:
3660 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3661 return 0;
3662 }
3663
3664 return value;
3665}
3666
3667static void emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
3668{
3669 switch (cr) {
3670 case 0:
3671 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
3672 break;
3673 case 2:
3674 vcpu->arch.cr2 = val;
3675 break;
3676 case 3:
3677 kvm_set_cr3(vcpu, val);
3678 break;
3679 case 4:
3680 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
3681 break;
3682 case 8:
3683 kvm_set_cr8(vcpu, val & 0xfUL);
3684 break;
3685 default:
3686 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3687 }
3688}
3689
9c537244
GN		 3690static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3691{
3692 return kvm_x86_ops->get_cpl(vcpu);
3693}
3694
2dafc6c2
GN		 3695static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3696{
3697 kvm_x86_ops->get_gdt(vcpu, dt);
3698}
3699
3700static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3701 struct kvm_vcpu *vcpu)
3702{
3703 struct kvm_segment var;
3704
3705 kvm_get_segment(vcpu, &var, seg);
3706
3707 if (var.unusable)
3708 return false;
3709
3710 if (var.g)
3711 var.limit >>= 12;
3712 set_desc_limit(desc, var.limit);
3713 set_desc_base(desc, (unsigned long)var.base);
3714 desc->type = var.type;
3715 desc->s = var.s;
3716 desc->dpl = var.dpl;
3717 desc->p = var.present;
3718 desc->avl = var.avl;
3719 desc->l = var.l;
3720 desc->d = var.db;
3721 desc->g = var.g;
3722
3723 return true;
3724}
3725
3726static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3727 struct kvm_vcpu *vcpu)
3728{
3729 struct kvm_segment var;
3730
3731 /* needed to preserve selector */
3732 kvm_get_segment(vcpu, &var, seg);
3733
3734 var.base = get_desc_base(desc);
3735 var.limit = get_desc_limit(desc);
3736 if (desc->g)
3737 var.limit = (var.limit << 12) | 0xfff;
3738 var.type = desc->type;
3739 var.present = desc->p;
3740 var.dpl = desc->dpl;
3741 var.db = desc->d;
3742 var.s = desc->s;
3743 var.l = desc->l;
3744 var.g = desc->g;
3745 var.avl = desc->avl;
3746 var.present = desc->p;
3747 var.unusable = !var.present;
3748 var.padding = 0;
3749
3750 kvm_set_segment(vcpu, &var, seg);
3751 return;
3752}
3753
3754static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3755{
3756 struct kvm_segment kvm_seg;
3757
3758 kvm_get_segment(vcpu, &kvm_seg, seg);
3759 return kvm_seg.selector;
3760}
3761
3762static void emulator_set_segment_selector(u16 sel, int seg,
3763 struct kvm_vcpu *vcpu)
3764{
3765 struct kvm_segment kvm_seg;
3766
3767 kvm_get_segment(vcpu, &kvm_seg, seg);
3768 kvm_seg.selector = sel;
3769 kvm_set_segment(vcpu, &kvm_seg, seg);
3770}
3771
482ac18a
GN		 3772static void emulator_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3773{
3774 kvm_x86_ops->set_rflags(vcpu, rflags);
3775}
3776
14af3f3c 3777static struct x86_emulate_ops emulate_ops = {
1871c602 3778 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3779 .write_std = kvm_write_guest_virt_system,
1871c602 3780 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3781 .read_emulated = emulator_read_emulated,
3782 .write_emulated = emulator_write_emulated,
3783 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3784 .pio_in_emulated = emulator_pio_in_emulated,
3785 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3786 .get_cached_descriptor = emulator_get_cached_descriptor,
3787 .set_cached_descriptor = emulator_set_cached_descriptor,
3788 .get_segment_selector = emulator_get_segment_selector,
3789 .set_segment_selector = emulator_set_segment_selector,
3790 .get_gdt = emulator_get_gdt,
52a46617
GN		 3791 .get_cr = emulator_get_cr,
3792 .set_cr = emulator_set_cr,
9c537244 3793 .cpl = emulator_get_cpl,
482ac18a 3794 .set_rflags = emulator_set_rflags,
bbd9b64e
CO		 3795};
3796
5fdbf976
MT		 3797static void cache_all_regs(struct kvm_vcpu *vcpu)
3798{
3799 kvm_register_read(vcpu, VCPU_REGS_RAX);
3800 kvm_register_read(vcpu, VCPU_REGS_RSP);
3801 kvm_register_read(vcpu, VCPU_REGS_RIP);
3802 vcpu->arch.regs_dirty = ~0;
3803}
3804
bbd9b64e 3805int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3806 unsigned long cr2,
3807 u16 error_code,
571008da 3808 int emulation_type)
bbd9b64e 3809{
310b5d30 3810 int r, shadow_mask;
571008da 3811 struct decode_cache *c;
851ba692 3812 struct kvm_run *run = vcpu->run;
bbd9b64e 3813
26eef70c 3814 kvm_clear_exception_queue(vcpu);
ad312c7c 3815 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3816 /*
56e82318 3817 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3818 * instead of direct ->regs accesses, can save hundred cycles
3819 * on Intel for instructions that don't read/change RSP, for
3820 * for example.
3821 */
3822 cache_all_regs(vcpu);
bbd9b64e
CO		 3823
3824 vcpu->mmio_is_write = 0;
bbd9b64e 3825
571008da 3826 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3827 int cs_db, cs_l;
3828 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3829
ad312c7c 3830 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3831 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3832 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3833 vcpu->arch.emulate_ctxt.mode =
a0044755 3834 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3835 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3836 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3837 ? X86EMUL_MODE_PROT64 : cs_db
3838 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3839
ad312c7c 3840 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3841 trace_kvm_emulate_insn_start(vcpu);
571008da 3842
0cb5762e
AP		 3843 /* Only allow emulation of specific instructions on #UD
3844 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3845 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3846 if (emulation_type & EMULTYPE_TRAP_UD) {
3847 if (!c->twobyte)
3848 return EMULATE_FAIL;
3849 switch (c->b) {
3850 case 0x01: /* VMMCALL */
3851 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3852 return EMULATE_FAIL;
3853 break;
3854 case 0x34: /* sysenter */
3855 case 0x35: /* sysexit */
3856 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3857 return EMULATE_FAIL;
3858 break;
3859 case 0x05: /* syscall */
3860 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3861 return EMULATE_FAIL;
3862 break;
3863 default:
3864 return EMULATE_FAIL;
3865 }
3866
3867 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3868 return EMULATE_FAIL;
3869 }
571008da 3870
f2b5756b 3871 ++vcpu->stat.insn_emulation;
bbd9b64e 3872 if (r) {
f2b5756b 3873 ++vcpu->stat.insn_emulation_fail;
e46479f8 3874 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3875 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3876 return EMULATE_DONE;
3877 return EMULATE_FAIL;
3878 }
3879 }
3880
ba8afb6b
GN		 3881 if (emulation_type & EMULTYPE_SKIP) {
3882 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3883 return EMULATE_DONE;
3884 }
3885
5cd21917 3886restart:
ad312c7c 3887 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3888 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3889
3890 if (r == 0)
3891 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3892
7972995b 3893 if (vcpu->arch.pio.count) {
cf8f70bf 3894 if (!vcpu->arch.pio.in)
7972995b 3895 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3896 return EMULATE_DO_MMIO;
3897 }
3898
112592da 3899 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3900 run->exit_reason = KVM_EXIT_MMIO;
3901 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3902 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3903 run->mmio.len = vcpu->mmio_size;
3904 run->mmio.is_write = vcpu->mmio_is_write;
3905 }
3906
3907 if (r) {
3908 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
5cd21917 3909 goto done;
bbd9b64e 3910 if (!vcpu->mmio_needed) {
e46479f8
AK		 3911 ++vcpu->stat.insn_emulation_fail;
3912 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3913 kvm_report_emulation_failure(vcpu, "mmio");
3914 return EMULATE_FAIL;
3915 }
3916 return EMULATE_DO_MMIO;
3917 }
3918
bbd9b64e
CO		 3919 if (vcpu->mmio_is_write) {
3920 vcpu->mmio_needed = 0;
3921 return EMULATE_DO_MMIO;
3922 }
3923
5cd21917
GN		 3924done:
3925 if (vcpu->arch.exception.pending)
3926 vcpu->arch.emulate_ctxt.restart = false;
3927
3928 if (vcpu->arch.emulate_ctxt.restart)
3929 goto restart;
3930
bbd9b64e
CO		 3931 return EMULATE_DONE;
3932}
3933EXPORT_SYMBOL_GPL(emulate_instruction);
3934
cf8f70bf
GN		 3935int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
3936{
3937 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3938 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3939 /* do not return to emulator after return from userspace */
7972995b 3940 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3941 return ret;
3942}
3943EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
3944
c8076604
GH		 3945static void bounce_off(void *info)
3946{
3947 /* nothing */
3948}
3949
c8076604
GH		 3950static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3951 void *data)
3952{
3953 struct cpufreq_freqs *freq = data;
3954 struct kvm *kvm;
3955 struct kvm_vcpu *vcpu;
3956 int i, send_ipi = 0;
3957
c8076604
GH		 3958 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3959 return 0;
3960 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3961 return 0;
0cca7907 3962 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3963
3964 spin_lock(&kvm_lock);
3965 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3966 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3967 if (vcpu->cpu != freq->cpu)
3968 continue;
3969 if (!kvm_request_guest_time_update(vcpu))
3970 continue;
3971 if (vcpu->cpu != smp_processor_id())
3972 send_ipi++;
3973 }
3974 }
3975 spin_unlock(&kvm_lock);
3976
3977 if (freq->old < freq->new && send_ipi) {
3978 /*
3979 * We upscale the frequency. Must make the guest
3980 * doesn't see old kvmclock values while running with
3981 * the new frequency, otherwise we risk the guest sees
3982 * time go backwards.
3983 *
3984 * In case we update the frequency for another cpu
3985 * (which might be in guest context) send an interrupt
3986 * to kick the cpu out of guest context. Next time
3987 * guest context is entered kvmclock will be updated,
3988 * so the guest will not see stale values.
3989 */
3990 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3991 }
3992 return 0;
3993}
3994
3995static struct notifier_block kvmclock_cpufreq_notifier_block = {
3996 .notifier_call = kvmclock_cpufreq_notifier
3997};
3998
b820cc0c
ZA		 3999static void kvm_timer_init(void)
4000{
4001 int cpu;
4002
b820cc0c 4003 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4004 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4005 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4006 for_each_online_cpu(cpu) {
4007 unsigned long khz = cpufreq_get(cpu);
4008 if (!khz)
4009 khz = tsc_khz;
4010 per_cpu(cpu_tsc_khz, cpu) = khz;
4011 }
0cca7907
ZA		 4012 } else {
4013 for_each_possible_cpu(cpu)
4014 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4015 }
4016}
4017
ff9d07a0
ZY		 4018static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4019
4020static int kvm_is_in_guest(void)
4021{
4022 return percpu_read(current_vcpu) != NULL;
4023}
4024
4025static int kvm_is_user_mode(void)
4026{
4027 int user_mode = 3;
dcf46b94 4028
ff9d07a0
ZY		 4029 if (percpu_read(current_vcpu))
4030 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4031
ff9d07a0
ZY		 4032 return user_mode != 0;
4033}
4034
4035static unsigned long kvm_get_guest_ip(void)
4036{
4037 unsigned long ip = 0;
dcf46b94 4038
ff9d07a0
ZY		 4039 if (percpu_read(current_vcpu))
4040 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4041
ff9d07a0
ZY		 4042 return ip;
4043}
4044
4045static struct perf_guest_info_callbacks kvm_guest_cbs = {
4046 .is_in_guest = kvm_is_in_guest,
4047 .is_user_mode = kvm_is_user_mode,
4048 .get_guest_ip = kvm_get_guest_ip,
4049};
4050
4051void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4052{
4053 percpu_write(current_vcpu, vcpu);
4054}
4055EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4056
4057void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4058{
4059 percpu_write(current_vcpu, NULL);
4060}
4061EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4062
f8c16bba 4063int kvm_arch_init(void *opaque)
043405e1 4064{
b820cc0c 4065 int r;
f8c16bba
ZX		 4066 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4067
f8c16bba
ZX		 4068 if (kvm_x86_ops) {
4069 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4070 r = -EEXIST;
4071 goto out;
f8c16bba
ZX		 4072 }
4073
4074 if (!ops->cpu_has_kvm_support()) {
4075 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4076 r = -EOPNOTSUPP;
4077 goto out;
f8c16bba
ZX		 4078 }
4079 if (ops->disabled_by_bios()) {
4080 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4081 r = -EOPNOTSUPP;
4082 goto out;
f8c16bba
ZX		 4083 }
4084
97db56ce
AK		 4085 r = kvm_mmu_module_init();
4086 if (r)
4087 goto out;
4088
4089 kvm_init_msr_list();
4090
f8c16bba 4091 kvm_x86_ops = ops;
56c6d28a 4092 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4093 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4094 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4095 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4096
b820cc0c 4097 kvm_timer_init();
c8076604 4098
ff9d07a0
ZY		 4099 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4100
f8c16bba 4101 return 0;
56c6d28a
ZX		 4102
4103out:
56c6d28a 4104 return r;
043405e1 4105}
8776e519 4106
f8c16bba
ZX		 4107void kvm_arch_exit(void)
4108{
ff9d07a0
ZY		 4109 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4110
888d256e
JK		 4111 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4112 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4113 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4114 kvm_x86_ops = NULL;
56c6d28a
ZX		 4115 kvm_mmu_module_exit();
4116}
f8c16bba 4117
8776e519
HB		 4118int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4119{
4120 ++vcpu->stat.halt_exits;
4121 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4122 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4123 return 1;
4124 } else {
4125 vcpu->run->exit_reason = KVM_EXIT_HLT;
4126 return 0;
4127 }
4128}
4129EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4130
2f333bcb
MT		 4131static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4132 unsigned long a1)
4133{
4134 if (is_long_mode(vcpu))
4135 return a0;
4136 else
4137 return a0 | ((gpa_t)a1 << 32);
4138}
4139
55cd8e5a
GN		 4140int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4141{
4142 u64 param, ingpa, outgpa, ret;
4143 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4144 bool fast, longmode;
4145 int cs_db, cs_l;
4146
4147 /*
4148 * hypercall generates UD from non zero cpl and real mode
4149 * per HYPER-V spec
4150 */
3eeb3288 4151 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4152 kvm_queue_exception(vcpu, UD_VECTOR);
4153 return 0;
4154 }
4155
4156 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4157 longmode = is_long_mode(vcpu) && cs_l == 1;
4158
4159 if (!longmode) {
ccd46936
GN		 4160 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4161 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4162 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4163 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4164 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4165 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4166 }
4167#ifdef CONFIG_X86_64
4168 else {
4169 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4170 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4171 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4172 }
4173#endif
4174
4175 code = param & 0xffff;
4176 fast = (param >> 16) & 0x1;
4177 rep_cnt = (param >> 32) & 0xfff;
4178 rep_idx = (param >> 48) & 0xfff;
4179
4180 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4181
c25bc163
GN		 4182 switch (code) {
4183 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4184 kvm_vcpu_on_spin(vcpu);
4185 break;
4186 default:
4187 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4188 break;
4189 }
55cd8e5a
GN		 4190
4191 ret = res | (((u64)rep_done & 0xfff) << 32);
4192 if (longmode) {
4193 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4194 } else {
4195 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4196 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4197 }
4198
4199 return 1;
4200}
4201
8776e519
HB		 4202int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4203{
4204 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4205 int r = 1;
8776e519 4206
55cd8e5a
GN		 4207 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4208 return kvm_hv_hypercall(vcpu);
4209
5fdbf976
MT		 4210 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4211 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4212 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4213 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4214 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4215
229456fc 4216 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4217
8776e519
HB		 4218 if (!is_long_mode(vcpu)) {
4219 nr &= 0xFFFFFFFF;
4220 a0 &= 0xFFFFFFFF;
4221 a1 &= 0xFFFFFFFF;
4222 a2 &= 0xFFFFFFFF;
4223 a3 &= 0xFFFFFFFF;
4224 }
4225
07708c4a
JK		 4226 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4227 ret = -KVM_EPERM;
4228 goto out;
4229 }
4230
8776e519 4231 switch (nr) {
b93463aa
AK		 4232 case KVM_HC_VAPIC_POLL_IRQ:
4233 ret = 0;
4234 break;
2f333bcb
MT		 4235 case KVM_HC_MMU_OP:
4236 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4237 break;
8776e519
HB		 4238 default:
4239 ret = -KVM_ENOSYS;
4240 break;
4241 }
07708c4a 4242out:
5fdbf976 4243 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4244 ++vcpu->stat.hypercalls;
2f333bcb 4245 return r;
8776e519
HB		 4246}
4247EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4248
4249int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4250{
4251 char instruction[3];
5fdbf976 4252 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4253
8776e519
HB		 4254 /*
4255 * Blow out the MMU to ensure that no other VCPU has an active mapping
4256 * to ensure that the updated hypercall appears atomically across all
4257 * VCPUs.
4258 */
4259 kvm_mmu_zap_all(vcpu->kvm);
4260
8776e519 4261 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4262
8f6abd06 4263 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 4264}
4265
8776e519
HB		 4266void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4267{
89a27f4d 4268 struct desc_ptr dt = { limit, base };
8776e519
HB		 4269
4270 kvm_x86_ops->set_gdt(vcpu, &dt);
4271}
4272
4273void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4274{
89a27f4d 4275 struct desc_ptr dt = { limit, base };
8776e519
HB		 4276
4277 kvm_x86_ops->set_idt(vcpu, &dt);
4278}
4279
07716717
DK		 4280static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4281{
ad312c7c
ZX		 4282 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4283 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4284
4285 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4286 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4287 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4288 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4289 if (ej->function == e->function) {
4290 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4291 return j;
4292 }
4293 }
4294 return 0; /* silence gcc, even though control never reaches here */
4295}
4296
4297/* find an entry with matching function, matching index (if needed), and that
4298 * should be read next (if it's stateful) */
4299static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4300 u32 function, u32 index)
4301{
4302 if (e->function != function)
4303 return 0;
4304 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4305 return 0;
4306 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4307 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4308 return 0;
4309 return 1;
4310}
4311
d8017474
AG		 4312struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4313 u32 function, u32 index)
8776e519
HB		 4314{
4315 int i;
d8017474 4316 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4317
ad312c7c 4318 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4319 struct kvm_cpuid_entry2 *e;
4320
ad312c7c 4321 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4322 if (is_matching_cpuid_entry(e, function, index)) {
4323 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4324 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4325 best = e;
4326 break;
4327 }
4328 /*
4329 * Both basic or both extended?
4330 */
4331 if (((e->function ^ function) & 0x80000000) == 0)
4332 if (!best || e->function > best->function)
4333 best = e;
4334 }
d8017474
AG		 4335 return best;
4336}
0e851880 4337EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4338
82725b20
DE		 4339int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4340{
4341 struct kvm_cpuid_entry2 *best;
4342
f7a71197
AK		 4343 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4344 if (!best || best->eax < 0x80000008)
4345 goto not_found;
82725b20
DE		 4346 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4347 if (best)
4348 return best->eax & 0xff;
f7a71197 4349not_found:
82725b20
DE		 4350 return 36;
4351}
4352
d8017474
AG		 4353void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4354{
4355 u32 function, index;
4356 struct kvm_cpuid_entry2 *best;
4357
4358 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4359 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4360 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4361 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4362 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4363 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4364 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4365 if (best) {
5fdbf976
MT		 4366 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4367 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4368 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4369 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4370 }
8776e519 4371 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4372 trace_kvm_cpuid(function,
4373 kvm_register_read(vcpu, VCPU_REGS_RAX),
4374 kvm_register_read(vcpu, VCPU_REGS_RBX),
4375 kvm_register_read(vcpu, VCPU_REGS_RCX),
4376 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4377}
4378EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4379
b6c7a5dc
HB		 4380/*
4381 * Check if userspace requested an interrupt window, and that the
4382 * interrupt window is open.
4383 *
4384 * No need to exit to userspace if we already have an interrupt queued.
4385 */
851ba692 4386static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4387{
8061823a 4388 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4389 vcpu->run->request_interrupt_window &&
5df56646 4390 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4391}
4392
851ba692 4393static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4394{
851ba692
AK		 4395 struct kvm_run *kvm_run = vcpu->run;
4396
91586a3b 4397 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4398 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4399 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4400 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4401 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4402 else
b6c7a5dc 4403 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4404 kvm_arch_interrupt_allowed(vcpu) &&
4405 !kvm_cpu_has_interrupt(vcpu) &&
4406 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4407}
4408
b93463aa
AK		 4409static void vapic_enter(struct kvm_vcpu *vcpu)
4410{
4411 struct kvm_lapic *apic = vcpu->arch.apic;
4412 struct page *page;
4413
4414 if (!apic || !apic->vapic_addr)
4415 return;
4416
4417 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4418
4419 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4420}
4421
4422static void vapic_exit(struct kvm_vcpu *vcpu)
4423{
4424 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4425 int idx;
b93463aa
AK		 4426
4427 if (!apic || !apic->vapic_addr)
4428 return;
4429
f656ce01 4430 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4431 kvm_release_page_dirty(apic->vapic_page);
4432 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4433 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4434}
4435
95ba8273
GN		 4436static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4437{
4438 int max_irr, tpr;
4439
4440 if (!kvm_x86_ops->update_cr8_intercept)
4441 return;
4442
88c808fd
AK		 4443 if (!vcpu->arch.apic)
4444 return;
4445
8db3baa2
GN		 4446 if (!vcpu->arch.apic->vapic_addr)
4447 max_irr = kvm_lapic_find_highest_irr(vcpu);
4448 else
4449 max_irr = -1;
95ba8273
GN		 4450
4451 if (max_irr != -1)
4452 max_irr >>= 4;
4453
4454 tpr = kvm_lapic_get_cr8(vcpu);
4455
4456 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4457}
4458
851ba692 4459static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4460{
4461 /* try to reinject previous events if any */
b59bb7bd 4462 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4463 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4464 vcpu->arch.exception.has_error_code,
4465 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4466 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4467 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4468 vcpu->arch.exception.error_code,
4469 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4470 return;
4471 }
4472
95ba8273
GN		 4473 if (vcpu->arch.nmi_injected) {
4474 kvm_x86_ops->set_nmi(vcpu);
4475 return;
4476 }
4477
4478 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4479 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4480 return;
4481 }
4482
4483 /* try to inject new event if pending */
4484 if (vcpu->arch.nmi_pending) {
4485 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4486 vcpu->arch.nmi_pending = false;
4487 vcpu->arch.nmi_injected = true;
4488 kvm_x86_ops->set_nmi(vcpu);
4489 }
4490 } else if (kvm_cpu_has_interrupt(vcpu)) {
4491 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4492 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4493 false);
4494 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4495 }
4496 }
4497}
4498
851ba692 4499static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4500{
4501 int r;
6a8b1d13 4502 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4503 vcpu->run->request_interrupt_window;
b6c7a5dc 4504
2e53d63a
MT		 4505 if (vcpu->requests)
4506 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4507 kvm_mmu_unload(vcpu);
4508
b6c7a5dc
HB		 4509 r = kvm_mmu_reload(vcpu);
4510 if (unlikely(r))
4511 goto out;
4512
2f52d58c
AK		 4513 if (vcpu->requests) {
4514 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4515 __kvm_migrate_timers(vcpu);
c8076604
GH		 4516 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4517 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4518 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4519 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4520 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4521 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4522 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4523 &vcpu->requests)) {
851ba692 4524 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4525 r = 0;
4526 goto out;
4527 }
71c4dfaf 4528 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4529 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4530 r = 0;
4531 goto out;
4532 }
02daab21
AK		 4533 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4534 vcpu->fpu_active = 0;
4535 kvm_x86_ops->fpu_deactivate(vcpu);
4536 }
2f52d58c 4537 }
b93463aa 4538
b6c7a5dc
HB		 4539 preempt_disable();
4540
4541 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4542 if (vcpu->fpu_active)
4543 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4544
4545 local_irq_disable();
4546
32f88400
MT		 4547 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4548 smp_mb__after_clear_bit();
4549
d7690175 4550 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4551 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4552 local_irq_enable();
4553 preempt_enable();
4554 r = 1;
4555 goto out;
4556 }
4557
851ba692 4558 inject_pending_event(vcpu);
b6c7a5dc 4559
6a8b1d13
GN		 4560 /* enable NMI/IRQ window open exits if needed */
4561 if (vcpu->arch.nmi_pending)
4562 kvm_x86_ops->enable_nmi_window(vcpu);
4563 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4564 kvm_x86_ops->enable_irq_window(vcpu);
4565
95ba8273 4566 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4567 update_cr8_intercept(vcpu);
4568 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4569 }
b93463aa 4570
f656ce01 4571 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4572
b6c7a5dc
HB		 4573 kvm_guest_enter();
4574
42dbaa5a 4575 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4576 set_debugreg(0, 7);
4577 set_debugreg(vcpu->arch.eff_db[0], 0);
4578 set_debugreg(vcpu->arch.eff_db[1], 1);
4579 set_debugreg(vcpu->arch.eff_db[2], 2);
4580 set_debugreg(vcpu->arch.eff_db[3], 3);
4581 }
b6c7a5dc 4582
229456fc 4583 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4584 kvm_x86_ops->run(vcpu);
b6c7a5dc 4585
24f1e32c
FW		 4586 /*
4587 * If the guest has used debug registers, at least dr7
4588 * will be disabled while returning to the host.
4589 * If we don't have active breakpoints in the host, we don't
4590 * care about the messed up debug address registers. But if
4591 * we have some of them active, restore the old state.
4592 */
59d8eb53 4593 if (hw_breakpoint_active())
24f1e32c 4594 hw_breakpoint_restore();
42dbaa5a 4595
32f88400 4596 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4597 local_irq_enable();
4598
4599 ++vcpu->stat.exits;
4600
4601 /*
4602 * We must have an instruction between local_irq_enable() and
4603 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4604 * the interrupt shadow. The stat.exits increment will do nicely.
4605 * But we need to prevent reordering, hence this barrier():
4606 */
4607 barrier();
4608
4609 kvm_guest_exit();
4610
4611 preempt_enable();
4612
f656ce01 4613 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4614
b6c7a5dc
HB		 4615 /*
4616 * Profile KVM exit RIPs:
4617 */
4618 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4619 unsigned long rip = kvm_rip_read(vcpu);
4620 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4621 }
4622
298101da 4623
b93463aa
AK		 4624 kvm_lapic_sync_from_vapic(vcpu);
4625
851ba692 4626 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4627out:
4628 return r;
4629}
b6c7a5dc 4630
09cec754 4631
851ba692 4632static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4633{
4634 int r;
f656ce01 4635 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4636
4637 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4638 pr_debug("vcpu %d received sipi with vector # %x\n",
4639 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4640 kvm_lapic_reset(vcpu);
5f179287 4641 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4642 if (r)
4643 return r;
4644 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4645 }
4646
f656ce01 4647 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4648 vapic_enter(vcpu);
4649
4650 r = 1;
4651 while (r > 0) {
af2152f5 4652 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4653 r = vcpu_enter_guest(vcpu);
d7690175 4654 else {
f656ce01 4655 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4656 kvm_vcpu_block(vcpu);
f656ce01 4657 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4658 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4659 {
4660 switch(vcpu->arch.mp_state) {
4661 case KVM_MP_STATE_HALTED:
d7690175 4662 vcpu->arch.mp_state =
09cec754
GN		 4663 KVM_MP_STATE_RUNNABLE;
4664 case KVM_MP_STATE_RUNNABLE:
4665 break;
4666 case KVM_MP_STATE_SIPI_RECEIVED:
4667 default:
4668 r = -EINTR;
4669 break;
4670 }
4671 }
d7690175
MT		 4672 }
4673
09cec754
GN		 4674 if (r <= 0)
4675 break;
4676
4677 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4678 if (kvm_cpu_has_pending_timer(vcpu))
4679 kvm_inject_pending_timer_irqs(vcpu);
4680
851ba692 4681 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4682 r = -EINTR;
851ba692 4683 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4684 ++vcpu->stat.request_irq_exits;
4685 }
4686 if (signal_pending(current)) {
4687 r = -EINTR;
851ba692 4688 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4689 ++vcpu->stat.signal_exits;
4690 }
4691 if (need_resched()) {
f656ce01 4692 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4693 kvm_resched(vcpu);
f656ce01 4694 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4695 }
b6c7a5dc
HB		 4696 }
4697
f656ce01 4698 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4699
b93463aa
AK		 4700 vapic_exit(vcpu);
4701
b6c7a5dc
HB		 4702 return r;
4703}
4704
4705int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4706{
4707 int r;
4708 sigset_t sigsaved;
4709
4710 vcpu_load(vcpu);
4711
ac9f6dc0
AK		 4712 if (vcpu->sigset_active)
4713 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4714
a4535290 4715 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4716 kvm_vcpu_block(vcpu);
d7690175 4717 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4718 r = -EAGAIN;
4719 goto out;
b6c7a5dc
HB		 4720 }
4721
b6c7a5dc
HB		 4722 /* re-sync apic's tpr */
4723 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4724 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4725
92bf9748
GN		 4726 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4727 vcpu->arch.emulate_ctxt.restart) {
4728 if (vcpu->mmio_needed) {
4729 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4730 vcpu->mmio_read_completed = 1;
4731 vcpu->mmio_needed = 0;
b6c7a5dc 4732 }
5cd21917
GN		 4733 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4734 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
4735 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4736 if (r == EMULATE_DO_MMIO) {
4737 r = 0;
4738 goto out;
4739 }
4740 }
5fdbf976
MT		 4741 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4742 kvm_register_write(vcpu, VCPU_REGS_RAX,
4743 kvm_run->hypercall.ret);
b6c7a5dc 4744
851ba692 4745 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4746
4747out:
f1d86e46 4748 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4749 if (vcpu->sigset_active)
4750 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4751
4752 vcpu_put(vcpu);
4753 return r;
4754}
4755
4756int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4757{
4758 vcpu_load(vcpu);
4759
5fdbf976
MT		 4760 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4761 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4762 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4763 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4764 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4765 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4766 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4767 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4768#ifdef CONFIG_X86_64
5fdbf976
MT		 4769 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4770 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4771 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4772 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4773 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4774 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4775 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4776 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4777#endif
4778
5fdbf976 4779 regs->rip = kvm_rip_read(vcpu);
91586a3b 4780 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4781
4782 vcpu_put(vcpu);
4783
4784 return 0;
4785}
4786
4787int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4788{
4789 vcpu_load(vcpu);
4790
5fdbf976
MT		 4791 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4792 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4793 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4794 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4795 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4796 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4797 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4798 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4799#ifdef CONFIG_X86_64
5fdbf976
MT		 4800 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4801 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4802 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4803 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4804 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4805 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4806 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4807 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4808#endif
4809
5fdbf976 4810 kvm_rip_write(vcpu, regs->rip);
91586a3b 4811 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4812
b4f14abd
JK		 4813 vcpu->arch.exception.pending = false;
4814
b6c7a5dc
HB		 4815 vcpu_put(vcpu);
4816
4817 return 0;
4818}
4819
b6c7a5dc
HB		 4820void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4821{
4822 struct kvm_segment cs;
4823
3e6e0aab 4824 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4825 *db = cs.db;
4826 *l = cs.l;
4827}
4828EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4829
4830int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4831 struct kvm_sregs *sregs)
4832{
89a27f4d 4833 struct desc_ptr dt;
b6c7a5dc
HB		 4834
4835 vcpu_load(vcpu);
4836
3e6e0aab
GT		 4837 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4838 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4839 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4840 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4841 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4842 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4843
3e6e0aab
GT		 4844 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4845 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4846
4847 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4848 sregs->idt.limit = dt.size;
4849 sregs->idt.base = dt.address;
b6c7a5dc 4850 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4851 sregs->gdt.limit = dt.size;
4852 sregs->gdt.base = dt.address;
b6c7a5dc 4853
4d4ec087 4854 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4855 sregs->cr2 = vcpu->arch.cr2;
4856 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4857 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4858 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4859 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4860 sregs->apic_base = kvm_get_apic_base(vcpu);
4861
923c61bb 4862 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4863
36752c9b 4864 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4865 set_bit(vcpu->arch.interrupt.nr,
4866 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4867
b6c7a5dc
HB		 4868 vcpu_put(vcpu);
4869
4870 return 0;
4871}
4872
62d9f0db
MT		 4873int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4874 struct kvm_mp_state *mp_state)
4875{
4876 vcpu_load(vcpu);
4877 mp_state->mp_state = vcpu->arch.mp_state;
4878 vcpu_put(vcpu);
4879 return 0;
4880}
4881
4882int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4883 struct kvm_mp_state *mp_state)
4884{
4885 vcpu_load(vcpu);
4886 vcpu->arch.mp_state = mp_state->mp_state;
4887 vcpu_put(vcpu);
4888 return 0;
4889}
4890
e269fb21
JK		 4891int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4892 bool has_error_code, u32 error_code)
37817f29 4893{
ceffb459
GN		 4894 int cs_db, cs_l, ret;
4895 cache_all_regs(vcpu);
37817f29 4896
ceffb459 4897 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
b237ac37 4898
ceffb459
GN		 4899 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4900 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4901 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4902 vcpu->arch.emulate_ctxt.mode =
4903 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4904 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4905 ? X86EMUL_MODE_VM86 : cs_l
4906 ? X86EMUL_MODE_PROT64 : cs_db
4907 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
37817f29 4908
ceffb459 4909 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4910 tss_selector, reason, has_error_code,
4911 error_code);
37817f29 4912
19d04437
GN		 4913 if (ret)
4914 return EMULATE_FAIL;
37817f29 4915
19d04437
GN		 4916 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4917 return EMULATE_DONE;
37817f29
IE		 4918}
4919EXPORT_SYMBOL_GPL(kvm_task_switch);
4920
b6c7a5dc
HB		 4921int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4922 struct kvm_sregs *sregs)
4923{
4924 int mmu_reset_needed = 0;
923c61bb 4925 int pending_vec, max_bits;
89a27f4d 4926 struct desc_ptr dt;
b6c7a5dc
HB		 4927
4928 vcpu_load(vcpu);
4929
89a27f4d
GN		 4930 dt.size = sregs->idt.limit;
4931 dt.address = sregs->idt.base;
b6c7a5dc 4932 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4933 dt.size = sregs->gdt.limit;
4934 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4935 kvm_x86_ops->set_gdt(vcpu, &dt);
4936
ad312c7c
ZX		 4937 vcpu->arch.cr2 = sregs->cr2;
4938 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4939 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4940
2d3ad1f4 4941 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4942
f6801dff 4943 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 4944 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4945 kvm_set_apic_base(vcpu, sregs->apic_base);
4946
4d4ec087 4947 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4948 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4949 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4950
fc78f519 4951 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4952 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4953 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4954 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4955 mmu_reset_needed = 1;
4956 }
b6c7a5dc
HB		 4957
4958 if (mmu_reset_needed)
4959 kvm_mmu_reset_context(vcpu);
4960
923c61bb
GN		 4961 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4962 pending_vec = find_first_bit(
4963 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4964 if (pending_vec < max_bits) {
66fd3f7f 4965 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4966 pr_debug("Set back pending irq %d\n", pending_vec);
4967 if (irqchip_in_kernel(vcpu->kvm))
4968 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4969 }
4970
3e6e0aab
GT		 4971 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4972 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4973 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4974 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4975 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4976 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4977
3e6e0aab
GT		 4978 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4979 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4980
5f0269f5
ME		 4981 update_cr8_intercept(vcpu);
4982
9c3e4aab 4983 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4984 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 4985 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 4986 !is_protmode(vcpu))
9c3e4aab
MT		 4987 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4988
b6c7a5dc
HB		 4989 vcpu_put(vcpu);
4990
4991 return 0;
4992}
4993
d0bfb940
JK		 4994int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4995 struct kvm_guest_debug *dbg)
b6c7a5dc 4996{
355be0b9 4997 unsigned long rflags;
ae675ef0 4998 int i, r;
b6c7a5dc
HB		 4999
5000 vcpu_load(vcpu);
5001
4f926bf2
JK		 5002 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5003 r = -EBUSY;
5004 if (vcpu->arch.exception.pending)
5005 goto unlock_out;
5006 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5007 kvm_queue_exception(vcpu, DB_VECTOR);
5008 else
5009 kvm_queue_exception(vcpu, BP_VECTOR);
5010 }
5011
91586a3b
JK		 5012 /*
5013 * Read rflags as long as potentially injected trace flags are still
5014 * filtered out.
5015 */
5016 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5017
5018 vcpu->guest_debug = dbg->control;
5019 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5020 vcpu->guest_debug = 0;
5021
5022 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5023 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5024 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5025 vcpu->arch.switch_db_regs =
5026 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5027 } else {
5028 for (i = 0; i < KVM_NR_DB_REGS; i++)
5029 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5030 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5031 }
5032
f92653ee
JK		 5033 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5034 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5035 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5036
91586a3b
JK		 5037 /*
5038 * Trigger an rflags update that will inject or remove the trace
5039 * flags.
5040 */
5041 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5042
355be0b9 5043 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5044
4f926bf2 5045 r = 0;
d0bfb940 5046
4f926bf2 5047unlock_out:
b6c7a5dc
HB		 5048 vcpu_put(vcpu);
5049
5050 return r;
5051}
5052
d0752060
HB		 5053/*
5054 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5055 * we have asm/x86/processor.h
5056 */
5057struct fxsave {
5058 u16 cwd;
5059 u16 swd;
5060 u16 twd;
5061 u16 fop;
5062 u64 rip;
5063 u64 rdp;
5064 u32 mxcsr;
5065 u32 mxcsr_mask;
5066 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5067#ifdef CONFIG_X86_64
5068 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5069#else
5070 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5071#endif
5072};
5073
8b006791
ZX		 5074/*
5075 * Translate a guest virtual address to a guest physical address.
5076 */
5077int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5078 struct kvm_translation *tr)
5079{
5080 unsigned long vaddr = tr->linear_address;
5081 gpa_t gpa;
f656ce01 5082 int idx;
8b006791
ZX		 5083
5084 vcpu_load(vcpu);
f656ce01 5085 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5086 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5087 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5088 tr->physical_address = gpa;
5089 tr->valid = gpa != UNMAPPED_GVA;
5090 tr->writeable = 1;
5091 tr->usermode = 0;
8b006791
ZX		 5092 vcpu_put(vcpu);
5093
5094 return 0;
5095}
5096
d0752060
HB		 5097int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5098{
ad312c7c 5099 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5100
5101 vcpu_load(vcpu);
5102
5103 memcpy(fpu->fpr, fxsave->st_space, 128);
5104 fpu->fcw = fxsave->cwd;
5105 fpu->fsw = fxsave->swd;
5106 fpu->ftwx = fxsave->twd;
5107 fpu->last_opcode = fxsave->fop;
5108 fpu->last_ip = fxsave->rip;
5109 fpu->last_dp = fxsave->rdp;
5110 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5111
5112 vcpu_put(vcpu);
5113
5114 return 0;
5115}
5116
5117int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5118{
ad312c7c 5119 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5120
5121 vcpu_load(vcpu);
5122
5123 memcpy(fxsave->st_space, fpu->fpr, 128);
5124 fxsave->cwd = fpu->fcw;
5125 fxsave->swd = fpu->fsw;
5126 fxsave->twd = fpu->ftwx;
5127 fxsave->fop = fpu->last_opcode;
5128 fxsave->rip = fpu->last_ip;
5129 fxsave->rdp = fpu->last_dp;
5130 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5131
5132 vcpu_put(vcpu);
5133
5134 return 0;
5135}
5136
5137void fx_init(struct kvm_vcpu *vcpu)
5138{
5139 unsigned after_mxcsr_mask;
5140
bc1a34f1
AA		 5141 /*
5142 * Touch the fpu the first time in non atomic context as if
5143 * this is the first fpu instruction the exception handler
5144 * will fire before the instruction returns and it'll have to
5145 * allocate ram with GFP_KERNEL.
5146 */
5147 if (!used_math())
d6e88aec 5148 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5149
d0752060
HB		 5150 /* Initialize guest FPU by resetting ours and saving into guest's */
5151 preempt_disable();
d6e88aec
AK		 5152 kvm_fx_save(&vcpu->arch.host_fx_image);
5153 kvm_fx_finit();
5154 kvm_fx_save(&vcpu->arch.guest_fx_image);
5155 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5156 preempt_enable();
5157
ad312c7c 5158 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5159 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5160 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5161 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5162 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5163}
5164EXPORT_SYMBOL_GPL(fx_init);
5165
5166void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5167{
2608d7a1 5168 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5169 return;
5170
5171 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5172 kvm_fx_save(&vcpu->arch.host_fx_image);
5173 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5174 trace_kvm_fpu(1);
d0752060 5175}
d0752060
HB		 5176
5177void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5178{
5179 if (!vcpu->guest_fpu_loaded)
5180 return;
5181
5182 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5183 kvm_fx_save(&vcpu->arch.guest_fx_image);
5184 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5185 ++vcpu->stat.fpu_reload;
02daab21 5186 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5187 trace_kvm_fpu(0);
d0752060 5188}
e9b11c17
ZX		 5189
5190void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5191{
7f1ea208
JR		 5192 if (vcpu->arch.time_page) {
5193 kvm_release_page_dirty(vcpu->arch.time_page);
5194 vcpu->arch.time_page = NULL;
5195 }
5196
e9b11c17
ZX		 5197 kvm_x86_ops->vcpu_free(vcpu);
5198}
5199
5200struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5201 unsigned int id)
5202{
26e5215f
AK		 5203 return kvm_x86_ops->vcpu_create(kvm, id);
5204}
e9b11c17 5205
26e5215f
AK		 5206int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5207{
5208 int r;
e9b11c17
ZX		 5209
5210 /* We do fxsave: this must be aligned. */
ad312c7c 5211 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5212
0bed3b56 5213 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5214 vcpu_load(vcpu);
5215 r = kvm_arch_vcpu_reset(vcpu);
5216 if (r == 0)
5217 r = kvm_mmu_setup(vcpu);
5218 vcpu_put(vcpu);
5219 if (r < 0)
5220 goto free_vcpu;
5221
26e5215f 5222 return 0;
e9b11c17
ZX		 5223free_vcpu:
5224 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5225 return r;
e9b11c17
ZX		 5226}
5227
d40ccc62 5228void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5229{
5230 vcpu_load(vcpu);
5231 kvm_mmu_unload(vcpu);
5232 vcpu_put(vcpu);
5233
5234 kvm_x86_ops->vcpu_free(vcpu);
5235}
5236
5237int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5238{
448fa4a9
JK		 5239 vcpu->arch.nmi_pending = false;
5240 vcpu->arch.nmi_injected = false;
5241
42dbaa5a
JK		 5242 vcpu->arch.switch_db_regs = 0;
5243 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5244 vcpu->arch.dr6 = DR6_FIXED_1;
5245 vcpu->arch.dr7 = DR7_FIXED_1;
5246
e9b11c17
ZX		 5247 return kvm_x86_ops->vcpu_reset(vcpu);
5248}
5249
10474ae8 5250int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5251{
0cca7907
ZA		 5252 /*
5253 * Since this may be called from a hotplug notifcation,
5254 * we can't get the CPU frequency directly.
5255 */
5256 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5257 int cpu = raw_smp_processor_id();
5258 per_cpu(cpu_tsc_khz, cpu) = 0;
5259 }
18863bdd
AK		 5260
5261 kvm_shared_msr_cpu_online();
5262
10474ae8 5263 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5264}
5265
5266void kvm_arch_hardware_disable(void *garbage)
5267{
5268 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5269 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5270}
5271
5272int kvm_arch_hardware_setup(void)
5273{
5274 return kvm_x86_ops->hardware_setup();
5275}
5276
5277void kvm_arch_hardware_unsetup(void)
5278{
5279 kvm_x86_ops->hardware_unsetup();
5280}
5281
5282void kvm_arch_check_processor_compat(void *rtn)
5283{
5284 kvm_x86_ops->check_processor_compatibility(rtn);
5285}
5286
5287int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5288{
5289 struct page *page;
5290 struct kvm *kvm;
5291 int r;
5292
5293 BUG_ON(vcpu->kvm == NULL);
5294 kvm = vcpu->kvm;
5295
ad312c7c 5296 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5297 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5298 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5299 else
a4535290 5300 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5301
5302 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5303 if (!page) {
5304 r = -ENOMEM;
5305 goto fail;
5306 }
ad312c7c 5307 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5308
5309 r = kvm_mmu_create(vcpu);
5310 if (r < 0)
5311 goto fail_free_pio_data;
5312
5313 if (irqchip_in_kernel(kvm)) {
5314 r = kvm_create_lapic(vcpu);
5315 if (r < 0)
5316 goto fail_mmu_destroy;
5317 }
5318
890ca9ae
HY		 5319 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5320 GFP_KERNEL);
5321 if (!vcpu->arch.mce_banks) {
5322 r = -ENOMEM;
443c39bc 5323 goto fail_free_lapic;
890ca9ae
HY		 5324 }
5325 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5326
e9b11c17 5327 return 0;
443c39bc
WY		 5328fail_free_lapic:
5329 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5330fail_mmu_destroy:
5331 kvm_mmu_destroy(vcpu);
5332fail_free_pio_data:
ad312c7c 5333 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5334fail:
5335 return r;
5336}
5337
5338void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5339{
f656ce01
MT		 5340 int idx;
5341
36cb93fd 5342 kfree(vcpu->arch.mce_banks);
e9b11c17 5343 kvm_free_lapic(vcpu);
f656ce01 5344 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5345 kvm_mmu_destroy(vcpu);
f656ce01 5346 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5347 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5348}
d19a9cd2
ZX		 5349
5350struct kvm *kvm_arch_create_vm(void)
5351{
5352 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5353
5354 if (!kvm)
5355 return ERR_PTR(-ENOMEM);
5356
fef9cce0
MT		 5357 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5358 if (!kvm->arch.aliases) {
5359 kfree(kvm);
5360 return ERR_PTR(-ENOMEM);
5361 }
5362
f05e70ac 5363 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5364 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5365
5550af4d
SY		 5366 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5367 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5368
53f658b3
MT		 5369 rdtscll(kvm->arch.vm_init_tsc);
5370
d19a9cd2
ZX		 5371 return kvm;
5372}
5373
5374static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5375{
5376 vcpu_load(vcpu);
5377 kvm_mmu_unload(vcpu);
5378 vcpu_put(vcpu);
5379}
5380
5381static void kvm_free_vcpus(struct kvm *kvm)
5382{
5383 unsigned int i;
988a2cae 5384 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5385
5386 /*
5387 * Unpin any mmu pages first.
5388 */
988a2cae
GN		 5389 kvm_for_each_vcpu(i, vcpu, kvm)
5390 kvm_unload_vcpu_mmu(vcpu);
5391 kvm_for_each_vcpu(i, vcpu, kvm)
5392 kvm_arch_vcpu_free(vcpu);
5393
5394 mutex_lock(&kvm->lock);
5395 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5396 kvm->vcpus[i] = NULL;
d19a9cd2 5397
988a2cae
GN		 5398 atomic_set(&kvm->online_vcpus, 0);
5399 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5400}
5401
ad8ba2cd
SY		 5402void kvm_arch_sync_events(struct kvm *kvm)
5403{
ba4cef31 5404 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5405}
5406
d19a9cd2
ZX		 5407void kvm_arch_destroy_vm(struct kvm *kvm)
5408{
6eb55818 5409 kvm_iommu_unmap_guest(kvm);
7837699f 5410 kvm_free_pit(kvm);
d7deeeb0
ZX		 5411 kfree(kvm->arch.vpic);
5412 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5413 kvm_free_vcpus(kvm);
5414 kvm_free_physmem(kvm);
3d45830c
AK		 5415 if (kvm->arch.apic_access_page)
5416 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5417 if (kvm->arch.ept_identity_pagetable)
5418 put_page(kvm->arch.ept_identity_pagetable);
64749204 5419 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5420 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5421 kfree(kvm);
5422}
0de10343 5423
f7784b8e
MT		 5424int kvm_arch_prepare_memory_region(struct kvm *kvm,
5425 struct kvm_memory_slot *memslot,
0de10343 5426 struct kvm_memory_slot old,
f7784b8e 5427 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5428 int user_alloc)
5429{
f7784b8e 5430 int npages = memslot->npages;
0de10343
ZX		 5431
5432 /*To keep backward compatibility with older userspace,
5433 *x86 needs to hanlde !user_alloc case.
5434 */
5435 if (!user_alloc) {
5436 if (npages && !old.rmap) {
604b38ac
AA		 5437 unsigned long userspace_addr;
5438
72dc67a6 5439 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5440 userspace_addr = do_mmap(NULL, 0,
5441 npages * PAGE_SIZE,
5442 PROT_READ | PROT_WRITE,
acee3c04 5443 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5444 0);
72dc67a6 5445 up_write(&current->mm->mmap_sem);
0de10343 5446
604b38ac
AA		 5447 if (IS_ERR((void *)userspace_addr))
5448 return PTR_ERR((void *)userspace_addr);
5449
604b38ac 5450 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5451 }
5452 }
5453
f7784b8e
MT		 5454
5455 return 0;
5456}
5457
5458void kvm_arch_commit_memory_region(struct kvm *kvm,
5459 struct kvm_userspace_memory_region *mem,
5460 struct kvm_memory_slot old,
5461 int user_alloc)
5462{
5463
5464 int npages = mem->memory_size >> PAGE_SHIFT;
5465
5466 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5467 int ret;
5468
5469 down_write(&current->mm->mmap_sem);
5470 ret = do_munmap(current->mm, old.userspace_addr,
5471 old.npages * PAGE_SIZE);
5472 up_write(&current->mm->mmap_sem);
5473 if (ret < 0)
5474 printk(KERN_WARNING
5475 "kvm_vm_ioctl_set_memory_region: "
5476 "failed to munmap memory\n");
5477 }
5478
7c8a83b7 5479 spin_lock(&kvm->mmu_lock);
f05e70ac 5480 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5481 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5482 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5483 }
5484
5485 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5486 spin_unlock(&kvm->mmu_lock);
0de10343 5487}
1d737c8a 5488
34d4cb8f
MT		 5489void kvm_arch_flush_shadow(struct kvm *kvm)
5490{
5491 kvm_mmu_zap_all(kvm);
8986ecc0 5492 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5493}
5494
1d737c8a
ZX		 5495int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5496{
a4535290 5497 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5498 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5499 || vcpu->arch.nmi_pending ||
5500 (kvm_arch_interrupt_allowed(vcpu) &&
5501 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5502}
5736199a 5503
5736199a
ZX		 5504void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5505{
32f88400
MT		 5506 int me;
5507 int cpu = vcpu->cpu;
5736199a
ZX		 5508
5509 if (waitqueue_active(&vcpu->wq)) {
5510 wake_up_interruptible(&vcpu->wq);
5511 ++vcpu->stat.halt_wakeup;
5512 }
32f88400
MT		 5513
5514 me = get_cpu();
5515 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5516 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5517 smp_send_reschedule(cpu);
e9571ed5 5518 put_cpu();
5736199a 5519}
78646121
GN		 5520
5521int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5522{
5523 return kvm_x86_ops->interrupt_allowed(vcpu);
5524}
229456fc 5525
f92653ee
JK		 5526bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5527{
5528 unsigned long current_rip = kvm_rip_read(vcpu) +
5529 get_segment_base(vcpu, VCPU_SREG_CS);
5530
5531 return current_rip == linear_rip;
5532}
5533EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5534
94fe45da
JK		 5535unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5536{
5537 unsigned long rflags;
5538
5539 rflags = kvm_x86_ops->get_rflags(vcpu);
5540 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5541 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5542 return rflags;
5543}
5544EXPORT_SYMBOL_GPL(kvm_get_rflags);
5545
5546void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5547{
5548 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5549 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5550 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5551 kvm_x86_ops->set_rflags(vcpu, rflags);
5552}
5553EXPORT_SYMBOL_GPL(kvm_set_rflags);
5554
229456fc
MT		 5555EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5556EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5557EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5558EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5559EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5560EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5561EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5562EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5563EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5564EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5565EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5566EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)