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hw-breakpoints: Fix broken hw-breakpoint sample module
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1 44
24f1e32c 45#include <asm/debugreg.h>
043405e1 46#include <asm/uaccess.h>
d825ed0a 47#include <asm/msr.h>
a5f61300 48#include <asm/desc.h>
0bed3b56 49#include <asm/mtrr.h>
890ca9ae 50#include <asm/mce.h>
043405e1 51
313a3dc7 52#define MAX_IO_MSRS 256
a03490ed
CO		 53#define CR0_RESERVED_BITS \
54 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
55 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
56 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
57#define CR4_RESERVED_BITS \
58 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
59 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
60 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
61 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
62
63#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 64
65#define KVM_MAX_MCE_BANKS 32
66#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
67
50a37eb4
JR		 68/* EFER defaults:
69 * - enable syscall per default because its emulated by KVM
70 * - enable LME and LMA per default on 64 bit KVM
71 */
72#ifdef CONFIG_X86_64
73static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
74#else
75static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
76#endif
313a3dc7 77
ba1389b7
AK		 78#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
79#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 80
cb142eb7 81static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 82static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
83 struct kvm_cpuid_entry2 __user *entries);
84
97896d04 85struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 86EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 87
ed85c068
AP		 88int ignore_msrs = 0;
89module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
90
417bc304 91struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 92 { "pf_fixed", VCPU_STAT(pf_fixed) },
93 { "pf_guest", VCPU_STAT(pf_guest) },
94 { "tlb_flush", VCPU_STAT(tlb_flush) },
95 { "invlpg", VCPU_STAT(invlpg) },
96 { "exits", VCPU_STAT(exits) },
97 { "io_exits", VCPU_STAT(io_exits) },
98 { "mmio_exits", VCPU_STAT(mmio_exits) },
99 { "signal_exits", VCPU_STAT(signal_exits) },
100 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 101 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 102 { "halt_exits", VCPU_STAT(halt_exits) },
103 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 104 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 105 { "request_irq", VCPU_STAT(request_irq_exits) },
106 { "irq_exits", VCPU_STAT(irq_exits) },
107 { "host_state_reload", VCPU_STAT(host_state_reload) },
108 { "efer_reload", VCPU_STAT(efer_reload) },
109 { "fpu_reload", VCPU_STAT(fpu_reload) },
110 { "insn_emulation", VCPU_STAT(insn_emulation) },
111 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 112 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 113 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 114 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
115 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
116 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
117 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
118 { "mmu_flooded", VM_STAT(mmu_flooded) },
119 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 120 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 121 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 122 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 123 { "largepages", VM_STAT(lpages) },
417bc304
HB		 124 { NULL }
125};
126
5fb76f9b
CO		 127unsigned long segment_base(u16 selector)
128{
129 struct descriptor_table gdt;
a5f61300 130 struct desc_struct *d;
5fb76f9b
CO		 131 unsigned long table_base;
132 unsigned long v;
133
134 if (selector == 0)
135 return 0;
136
b792c344 137 kvm_get_gdt(&gdt);
5fb76f9b
CO		 138 table_base = gdt.base;
139
140 if (selector & 4) { /* from ldt */
b792c344 141 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 142
5fb76f9b
CO		 143 table_base = segment_base(ldt_selector);
144 }
a5f61300 145 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 146 v = get_desc_base(d);
5fb76f9b 147#ifdef CONFIG_X86_64
a5f61300
AK		 148 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
149 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 150#endif
151 return v;
152}
153EXPORT_SYMBOL_GPL(segment_base);
154
6866b83e
CO		 155u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
156{
157 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 158 return vcpu->arch.apic_base;
6866b83e 159 else
ad312c7c 160 return vcpu->arch.apic_base;
6866b83e
CO		 161}
162EXPORT_SYMBOL_GPL(kvm_get_apic_base);
163
164void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
165{
166 /* TODO: reserve bits check */
167 if (irqchip_in_kernel(vcpu->kvm))
168 kvm_lapic_set_base(vcpu, data);
169 else
ad312c7c 170 vcpu->arch.apic_base = data;
6866b83e
CO		 171}
172EXPORT_SYMBOL_GPL(kvm_set_apic_base);
173
298101da
AK		 174void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
175{
ad312c7c
ZX		 176 WARN_ON(vcpu->arch.exception.pending);
177 vcpu->arch.exception.pending = true;
178 vcpu->arch.exception.has_error_code = false;
179 vcpu->arch.exception.nr = nr;
298101da
AK		 180}
181EXPORT_SYMBOL_GPL(kvm_queue_exception);
182
c3c91fee
AK		 183void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
184 u32 error_code)
185{
186 ++vcpu->stat.pf_guest;
d8017474 187
71c4dfaf 188 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 189 switch(vcpu->arch.exception.nr) {
190 case DF_VECTOR:
71c4dfaf
JR		 191 /* triple fault -> shutdown */
192 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 193 return;
194 case PF_VECTOR:
195 vcpu->arch.exception.nr = DF_VECTOR;
196 vcpu->arch.exception.error_code = 0;
197 return;
198 default:
199 /* replace previous exception with a new one in a hope
200 that instruction re-execution will regenerate lost
201 exception */
202 vcpu->arch.exception.pending = false;
203 break;
71c4dfaf 204 }
c3c91fee 205 }
ad312c7c 206 vcpu->arch.cr2 = addr;
c3c91fee
AK		 207 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
208}
209
3419ffc8
SY		 210void kvm_inject_nmi(struct kvm_vcpu *vcpu)
211{
212 vcpu->arch.nmi_pending = 1;
213}
214EXPORT_SYMBOL_GPL(kvm_inject_nmi);
215
298101da
AK		 216void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
217{
ad312c7c
ZX		 218 WARN_ON(vcpu->arch.exception.pending);
219 vcpu->arch.exception.pending = true;
220 vcpu->arch.exception.has_error_code = true;
221 vcpu->arch.exception.nr = nr;
222 vcpu->arch.exception.error_code = error_code;
298101da
AK		 223}
224EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
225
0a79b009
AK		 226/*
227 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
228 * a #GP and return false.
229 */
230bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 231{
0a79b009
AK		 232 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
233 return true;
234 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
235 return false;
298101da 236}
0a79b009 237EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 238
a03490ed
CO		 239/*
240 * Load the pae pdptrs. Return true is they are all valid.
241 */
242int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
243{
244 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
245 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
246 int i;
247 int ret;
ad312c7c 248 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 249
a03490ed
CO		 250 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
251 offset * sizeof(u64), sizeof(pdpte));
252 if (ret < 0) {
253 ret = 0;
254 goto out;
255 }
256 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 257 if (is_present_gpte(pdpte[i]) &&
20c466b5 258 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 259 ret = 0;
260 goto out;
261 }
262 }
263 ret = 1;
264
ad312c7c 265 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 266 __set_bit(VCPU_EXREG_PDPTR,
267 (unsigned long *)&vcpu->arch.regs_avail);
268 __set_bit(VCPU_EXREG_PDPTR,
269 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 270out:
a03490ed
CO		 271
272 return ret;
273}
cc4b6871 274EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 275
d835dfec
AK		 276static bool pdptrs_changed(struct kvm_vcpu *vcpu)
277{
ad312c7c 278 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 279 bool changed = true;
280 int r;
281
282 if (is_long_mode(vcpu) || !is_pae(vcpu))
283 return false;
284
6de4f3ad
AK		 285 if (!test_bit(VCPU_EXREG_PDPTR,
286 (unsigned long *)&vcpu->arch.regs_avail))
287 return true;
288
ad312c7c 289 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 290 if (r < 0)
291 goto out;
ad312c7c 292 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 293out:
d835dfec
AK		 294
295 return changed;
296}
297
2d3ad1f4 298void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 299{
300 if (cr0 & CR0_RESERVED_BITS) {
301 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 302 cr0, vcpu->arch.cr0);
c1a5d4f9 303 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 304 return;
305 }
306
307 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
308 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 309 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 310 return;
311 }
312
313 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
314 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
315 "and a clear PE flag\n");
c1a5d4f9 316 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 317 return;
318 }
319
320 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
321#ifdef CONFIG_X86_64
ad312c7c 322 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 323 int cs_db, cs_l;
324
325 if (!is_pae(vcpu)) {
326 printk(KERN_DEBUG "set_cr0: #GP, start paging "
327 "in long mode while PAE is disabled\n");
c1a5d4f9 328 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 329 return;
330 }
331 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
332 if (cs_l) {
333 printk(KERN_DEBUG "set_cr0: #GP, start paging "
334 "in long mode while CS.L == 1\n");
c1a5d4f9 335 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 336 return;
337
338 }
339 } else
340#endif
ad312c7c 341 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 342 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
343 "reserved bits\n");
c1a5d4f9 344 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 345 return;
346 }
347
348 }
349
350 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 351 vcpu->arch.cr0 = cr0;
a03490ed 352
a03490ed 353 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 354 return;
355}
2d3ad1f4 356EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 357
2d3ad1f4 358void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 359{
2d3ad1f4 360 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 361}
2d3ad1f4 362EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 363
2d3ad1f4 364void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 365{
a2edf57f
AK		 366 unsigned long old_cr4 = vcpu->arch.cr4;
367 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
368
a03490ed
CO		 369 if (cr4 & CR4_RESERVED_BITS) {
370 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 371 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 372 return;
373 }
374
375 if (is_long_mode(vcpu)) {
376 if (!(cr4 & X86_CR4_PAE)) {
377 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
378 "in long mode\n");
c1a5d4f9 379 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 380 return;
381 }
a2edf57f
AK		 382 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
383 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 384 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 385 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 386 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 387 return;
388 }
389
390 if (cr4 & X86_CR4_VMXE) {
391 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 392 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 393 return;
394 }
395 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 396 vcpu->arch.cr4 = cr4;
5a41accd 397 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 398 kvm_mmu_reset_context(vcpu);
a03490ed 399}
2d3ad1f4 400EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 401
2d3ad1f4 402void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 403{
ad312c7c 404 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 405 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 406 kvm_mmu_flush_tlb(vcpu);
407 return;
408 }
409
a03490ed
CO		 410 if (is_long_mode(vcpu)) {
411 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
412 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 413 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 414 return;
415 }
416 } else {
417 if (is_pae(vcpu)) {
418 if (cr3 & CR3_PAE_RESERVED_BITS) {
419 printk(KERN_DEBUG
420 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 421 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 422 return;
423 }
424 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
425 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
426 "reserved bits\n");
c1a5d4f9 427 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 428 return;
429 }
430 }
431 /*
432 * We don't check reserved bits in nonpae mode, because
433 * this isn't enforced, and VMware depends on this.
434 */
435 }
436
a03490ed
CO		 437 /*
438 * Does the new cr3 value map to physical memory? (Note, we
439 * catch an invalid cr3 even in real-mode, because it would
440 * cause trouble later on when we turn on paging anyway.)
441 *
442 * A real CPU would silently accept an invalid cr3 and would
443 * attempt to use it - with largely undefined (and often hard
444 * to debug) behavior on the guest side.
445 */
446 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 447 kvm_inject_gp(vcpu, 0);
a03490ed 448 else {
ad312c7c
ZX		 449 vcpu->arch.cr3 = cr3;
450 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 451 }
a03490ed 452}
2d3ad1f4 453EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 454
2d3ad1f4 455void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 456{
457 if (cr8 & CR8_RESERVED_BITS) {
458 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 459 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 460 return;
461 }
462 if (irqchip_in_kernel(vcpu->kvm))
463 kvm_lapic_set_tpr(vcpu, cr8);
464 else
ad312c7c 465 vcpu->arch.cr8 = cr8;
a03490ed 466}
2d3ad1f4 467EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 468
2d3ad1f4 469unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 470{
471 if (irqchip_in_kernel(vcpu->kvm))
472 return kvm_lapic_get_cr8(vcpu);
473 else
ad312c7c 474 return vcpu->arch.cr8;
a03490ed 475}
2d3ad1f4 476EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 477
d8017474
AG		 478static inline u32 bit(int bitno)
479{
480 return 1 << (bitno & 31);
481}
482
043405e1
CO		 483/*
484 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
485 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
486 *
487 * This list is modified at module load time to reflect the
488 * capabilities of the host cpu.
489 */
490static u32 msrs_to_save[] = {
491 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
492 MSR_K6_STAR,
493#ifdef CONFIG_X86_64
494 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
495#endif
af24a4e4 496 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 497 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 498};
499
500static unsigned num_msrs_to_save;
501
502static u32 emulated_msrs[] = {
503 MSR_IA32_MISC_ENABLE,
504};
505
15c4a640
CO		 506static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
507{
f2b4b7dd 508 if (efer & efer_reserved_bits) {
15c4a640
CO		 509 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
510 efer);
c1a5d4f9 511 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 512 return;
513 }
514
515 if (is_paging(vcpu)
ad312c7c 516 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 517 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 518 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 519 return;
520 }
521
1b2fd70c
AG		 522 if (efer & EFER_FFXSR) {
523 struct kvm_cpuid_entry2 *feat;
524
525 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
526 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
527 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
528 kvm_inject_gp(vcpu, 0);
529 return;
530 }
531 }
532
d8017474
AG		 533 if (efer & EFER_SVME) {
534 struct kvm_cpuid_entry2 *feat;
535
536 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
537 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
538 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
539 kvm_inject_gp(vcpu, 0);
540 return;
541 }
542 }
543
15c4a640
CO		 544 kvm_x86_ops->set_efer(vcpu, efer);
545
546 efer &= ~EFER_LMA;
ad312c7c 547 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 548
ad312c7c 549 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 550
551 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
552 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 553}
554
f2b4b7dd
JR		 555void kvm_enable_efer_bits(u64 mask)
556{
557 efer_reserved_bits &= ~mask;
558}
559EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
560
561
15c4a640
CO		 562/*
563 * Writes msr value into into the appropriate "register".
564 * Returns 0 on success, non-0 otherwise.
565 * Assumes vcpu_load() was already called.
566 */
567int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
568{
569 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
570}
571
313a3dc7
CO		 572/*
573 * Adapt set_msr() to msr_io()'s calling convention
574 */
575static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
576{
577 return kvm_set_msr(vcpu, index, *data);
578}
579
18068523
GOC		 580static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
581{
582 static int version;
50d0a0f9
GH		 583 struct pvclock_wall_clock wc;
584 struct timespec now, sys, boot;
18068523
GOC		 585
586 if (!wall_clock)
587 return;
588
589 version++;
590
18068523
GOC		 591 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
592
50d0a0f9
GH		 593 /*
594 * The guest calculates current wall clock time by adding
595 * system time (updated by kvm_write_guest_time below) to the
596 * wall clock specified here. guest system time equals host
597 * system time for us, thus we must fill in host boot time here.
598 */
599 now = current_kernel_time();
600 ktime_get_ts(&sys);
601 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
602
603 wc.sec = boot.tv_sec;
604 wc.nsec = boot.tv_nsec;
605 wc.version = version;
18068523
GOC		 606
607 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
608
609 version++;
610 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 611}
612
50d0a0f9
GH		 613static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
614{
615 uint32_t quotient, remainder;
616
617 /* Don't try to replace with do_div(), this one calculates
618 * "(dividend << 32) / divisor" */
619 __asm__ ( "divl %4"
620 : "=a" (quotient), "=d" (remainder)
621 : "0" (0), "1" (dividend), "r" (divisor) );
622 return quotient;
623}
624
625static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
626{
627 uint64_t nsecs = 1000000000LL;
628 int32_t shift = 0;
629 uint64_t tps64;
630 uint32_t tps32;
631
632 tps64 = tsc_khz * 1000LL;
633 while (tps64 > nsecs*2) {
634 tps64 >>= 1;
635 shift--;
636 }
637
638 tps32 = (uint32_t)tps64;
639 while (tps32 <= (uint32_t)nsecs) {
640 tps32 <<= 1;
641 shift++;
642 }
643
644 hv_clock->tsc_shift = shift;
645 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
646
647 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 648 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 649 hv_clock->tsc_to_system_mul);
650}
651
c8076604
GH		 652static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
653
18068523
GOC		 654static void kvm_write_guest_time(struct kvm_vcpu *v)
655{
656 struct timespec ts;
657 unsigned long flags;
658 struct kvm_vcpu_arch *vcpu = &v->arch;
659 void *shared_kaddr;
463656c0 660 unsigned long this_tsc_khz;
18068523
GOC		 661
662 if ((!vcpu->time_page))
663 return;
664
463656c0
AK		 665 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
666 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
667 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
668 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 669 }
463656c0 670 put_cpu_var(cpu_tsc_khz);
50d0a0f9 671
18068523
GOC		 672 /* Keep irq disabled to prevent changes to the clock */
673 local_irq_save(flags);
af24a4e4 674 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 675 ktime_get_ts(&ts);
676 local_irq_restore(flags);
677
678 /* With all the info we got, fill in the values */
679
680 vcpu->hv_clock.system_time = ts.tv_nsec +
681 (NSEC_PER_SEC * (u64)ts.tv_sec);
682 /*
683 * The interface expects us to write an even number signaling that the
684 * update is finished. Since the guest won't see the intermediate
50d0a0f9 685 * state, we just increase by 2 at the end.
18068523 686 */
50d0a0f9 687 vcpu->hv_clock.version += 2;
18068523
GOC		 688
689 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
690
691 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 692 sizeof(vcpu->hv_clock));
18068523
GOC		 693
694 kunmap_atomic(shared_kaddr, KM_USER0);
695
696 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
697}
698
c8076604
GH		 699static int kvm_request_guest_time_update(struct kvm_vcpu *v)
700{
701 struct kvm_vcpu_arch *vcpu = &v->arch;
702
703 if (!vcpu->time_page)
704 return 0;
705 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
706 return 1;
707}
708
9ba075a6
AK		 709static bool msr_mtrr_valid(unsigned msr)
710{
711 switch (msr) {
712 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
713 case MSR_MTRRfix64K_00000:
714 case MSR_MTRRfix16K_80000:
715 case MSR_MTRRfix16K_A0000:
716 case MSR_MTRRfix4K_C0000:
717 case MSR_MTRRfix4K_C8000:
718 case MSR_MTRRfix4K_D0000:
719 case MSR_MTRRfix4K_D8000:
720 case MSR_MTRRfix4K_E0000:
721 case MSR_MTRRfix4K_E8000:
722 case MSR_MTRRfix4K_F0000:
723 case MSR_MTRRfix4K_F8000:
724 case MSR_MTRRdefType:
725 case MSR_IA32_CR_PAT:
726 return true;
727 case 0x2f8:
728 return true;
729 }
730 return false;
731}
732
d6289b93
MT		 733static bool valid_pat_type(unsigned t)
734{
735 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
736}
737
738static bool valid_mtrr_type(unsigned t)
739{
740 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
741}
742
743static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
744{
745 int i;
746
747 if (!msr_mtrr_valid(msr))
748 return false;
749
750 if (msr == MSR_IA32_CR_PAT) {
751 for (i = 0; i < 8; i++)
752 if (!valid_pat_type((data >> (i * 8)) & 0xff))
753 return false;
754 return true;
755 } else if (msr == MSR_MTRRdefType) {
756 if (data & ~0xcff)
757 return false;
758 return valid_mtrr_type(data & 0xff);
759 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
760 for (i = 0; i < 8 ; i++)
761 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
762 return false;
763 return true;
764 }
765
766 /* variable MTRRs */
767 return valid_mtrr_type(data & 0xff);
768}
769
9ba075a6
AK		 770static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
771{
0bed3b56
SY		 772 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
773
d6289b93 774 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 775 return 1;
776
0bed3b56
SY		 777 if (msr == MSR_MTRRdefType) {
778 vcpu->arch.mtrr_state.def_type = data;
779 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
780 } else if (msr == MSR_MTRRfix64K_00000)
781 p[0] = data;
782 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
783 p[1 + msr - MSR_MTRRfix16K_80000] = data;
784 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
785 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
786 else if (msr == MSR_IA32_CR_PAT)
787 vcpu->arch.pat = data;
788 else { /* Variable MTRRs */
789 int idx, is_mtrr_mask;
790 u64 *pt;
791
792 idx = (msr - 0x200) / 2;
793 is_mtrr_mask = msr - 0x200 - 2 * idx;
794 if (!is_mtrr_mask)
795 pt =
796 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
797 else
798 pt =
799 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
800 *pt = data;
801 }
802
803 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 804 return 0;
805}
15c4a640 806
890ca9ae 807static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 808{
890ca9ae
HY		 809 u64 mcg_cap = vcpu->arch.mcg_cap;
810 unsigned bank_num = mcg_cap & 0xff;
811
15c4a640 812 switch (msr) {
15c4a640 813 case MSR_IA32_MCG_STATUS:
890ca9ae 814 vcpu->arch.mcg_status = data;
15c4a640 815 break;
c7ac679c 816 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 817 if (!(mcg_cap & MCG_CTL_P))
818 return 1;
819 if (data != 0 && data != ~(u64)0)
820 return -1;
821 vcpu->arch.mcg_ctl = data;
822 break;
823 default:
824 if (msr >= MSR_IA32_MC0_CTL &&
825 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
826 u32 offset = msr - MSR_IA32_MC0_CTL;
827 /* only 0 or all 1s can be written to IA32_MCi_CTL */
828 if ((offset & 0x3) == 0 &&
829 data != 0 && data != ~(u64)0)
830 return -1;
831 vcpu->arch.mce_banks[offset] = data;
832 break;
833 }
834 return 1;
835 }
836 return 0;
837}
838
15c4a640
CO		 839int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
840{
841 switch (msr) {
15c4a640
CO		 842 case MSR_EFER:
843 set_efer(vcpu, data);
844 break;
8f1589d9
AP		 845 case MSR_K7_HWCR:
846 data &= ~(u64)0x40; /* ignore flush filter disable */
847 if (data != 0) {
848 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
849 data);
850 return 1;
851 }
15c4a640 852 break;
f7c6d140
AP		 853 case MSR_FAM10H_MMIO_CONF_BASE:
854 if (data != 0) {
855 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
856 "0x%llx\n", data);
857 return 1;
858 }
15c4a640 859 break;
c323c0e5 860 case MSR_AMD64_NB_CFG:
c7ac679c 861 break;
b5e2fec0
AG		 862 case MSR_IA32_DEBUGCTLMSR:
863 if (!data) {
864 /* We support the non-activated case already */
865 break;
866 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
867 /* Values other than LBR and BTF are vendor-specific,
868 thus reserved and should throw a #GP */
869 return 1;
870 }
871 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
872 __func__, data);
873 break;
15c4a640
CO		 874 case MSR_IA32_UCODE_REV:
875 case MSR_IA32_UCODE_WRITE:
61a6bd67 876 case MSR_VM_HSAVE_PA:
6098ca93 877 case MSR_AMD64_PATCH_LOADER:
15c4a640 878 break;
9ba075a6
AK		 879 case 0x200 ... 0x2ff:
880 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 881 case MSR_IA32_APICBASE:
882 kvm_set_apic_base(vcpu, data);
883 break;
0105d1a5
GN		 884 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
885 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 886 case MSR_IA32_MISC_ENABLE:
ad312c7c 887 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 888 break;
18068523
GOC		 889 case MSR_KVM_WALL_CLOCK:
890 vcpu->kvm->arch.wall_clock = data;
891 kvm_write_wall_clock(vcpu->kvm, data);
892 break;
893 case MSR_KVM_SYSTEM_TIME: {
894 if (vcpu->arch.time_page) {
895 kvm_release_page_dirty(vcpu->arch.time_page);
896 vcpu->arch.time_page = NULL;
897 }
898
899 vcpu->arch.time = data;
900
901 /* we verify if the enable bit is set... */
902 if (!(data & 1))
903 break;
904
905 /* ...but clean it before doing the actual write */
906 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
907
18068523
GOC		 908 vcpu->arch.time_page =
909 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 910
911 if (is_error_page(vcpu->arch.time_page)) {
912 kvm_release_page_clean(vcpu->arch.time_page);
913 vcpu->arch.time_page = NULL;
914 }
915
c8076604 916 kvm_request_guest_time_update(vcpu);
18068523
GOC		 917 break;
918 }
890ca9ae
HY		 919 case MSR_IA32_MCG_CTL:
920 case MSR_IA32_MCG_STATUS:
921 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
922 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 923
924 /* Performance counters are not protected by a CPUID bit,
925 * so we should check all of them in the generic path for the sake of
926 * cross vendor migration.
927 * Writing a zero into the event select MSRs disables them,
928 * which we perfectly emulate ;-). Any other value should be at least
929 * reported, some guests depend on them.
930 */
931 case MSR_P6_EVNTSEL0:
932 case MSR_P6_EVNTSEL1:
933 case MSR_K7_EVNTSEL0:
934 case MSR_K7_EVNTSEL1:
935 case MSR_K7_EVNTSEL2:
936 case MSR_K7_EVNTSEL3:
937 if (data != 0)
938 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
939 "0x%x data 0x%llx\n", msr, data);
940 break;
941 /* at least RHEL 4 unconditionally writes to the perfctr registers,
942 * so we ignore writes to make it happy.
943 */
944 case MSR_P6_PERFCTR0:
945 case MSR_P6_PERFCTR1:
946 case MSR_K7_PERFCTR0:
947 case MSR_K7_PERFCTR1:
948 case MSR_K7_PERFCTR2:
949 case MSR_K7_PERFCTR3:
950 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
951 "0x%x data 0x%llx\n", msr, data);
952 break;
15c4a640 953 default:
ed85c068
AP		 954 if (!ignore_msrs) {
955 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
956 msr, data);
957 return 1;
958 } else {
959 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
960 msr, data);
961 break;
962 }
15c4a640
CO		 963 }
964 return 0;
965}
966EXPORT_SYMBOL_GPL(kvm_set_msr_common);
967
968
969/*
970 * Reads an msr value (of 'msr_index') into 'pdata'.
971 * Returns 0 on success, non-0 otherwise.
972 * Assumes vcpu_load() was already called.
973 */
974int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
975{
976 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
977}
978
9ba075a6
AK		 979static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
980{
0bed3b56
SY		 981 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
982
9ba075a6
AK		 983 if (!msr_mtrr_valid(msr))
984 return 1;
985
0bed3b56
SY		 986 if (msr == MSR_MTRRdefType)
987 *pdata = vcpu->arch.mtrr_state.def_type +
988 (vcpu->arch.mtrr_state.enabled << 10);
989 else if (msr == MSR_MTRRfix64K_00000)
990 *pdata = p[0];
991 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
992 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
993 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
994 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
995 else if (msr == MSR_IA32_CR_PAT)
996 *pdata = vcpu->arch.pat;
997 else { /* Variable MTRRs */
998 int idx, is_mtrr_mask;
999 u64 *pt;
1000
1001 idx = (msr - 0x200) / 2;
1002 is_mtrr_mask = msr - 0x200 - 2 * idx;
1003 if (!is_mtrr_mask)
1004 pt =
1005 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1006 else
1007 pt =
1008 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1009 *pdata = *pt;
1010 }
1011
9ba075a6
AK		 1012 return 0;
1013}
1014
890ca9ae 1015static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1016{
1017 u64 data;
890ca9ae
HY		 1018 u64 mcg_cap = vcpu->arch.mcg_cap;
1019 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1020
1021 switch (msr) {
15c4a640
CO		 1022 case MSR_IA32_P5_MC_ADDR:
1023 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1024 data = 0;
1025 break;
15c4a640 1026 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1027 data = vcpu->arch.mcg_cap;
1028 break;
c7ac679c 1029 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1030 if (!(mcg_cap & MCG_CTL_P))
1031 return 1;
1032 data = vcpu->arch.mcg_ctl;
1033 break;
1034 case MSR_IA32_MCG_STATUS:
1035 data = vcpu->arch.mcg_status;
1036 break;
1037 default:
1038 if (msr >= MSR_IA32_MC0_CTL &&
1039 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1040 u32 offset = msr - MSR_IA32_MC0_CTL;
1041 data = vcpu->arch.mce_banks[offset];
1042 break;
1043 }
1044 return 1;
1045 }
1046 *pdata = data;
1047 return 0;
1048}
1049
1050int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1051{
1052 u64 data;
1053
1054 switch (msr) {
890ca9ae 1055 case MSR_IA32_PLATFORM_ID:
15c4a640 1056 case MSR_IA32_UCODE_REV:
15c4a640 1057 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1058 case MSR_IA32_DEBUGCTLMSR:
1059 case MSR_IA32_LASTBRANCHFROMIP:
1060 case MSR_IA32_LASTBRANCHTOIP:
1061 case MSR_IA32_LASTINTFROMIP:
1062 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1063 case MSR_K8_SYSCFG:
1064 case MSR_K7_HWCR:
61a6bd67 1065 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1066 case MSR_P6_PERFCTR0:
1067 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1068 case MSR_P6_EVNTSEL0:
1069 case MSR_P6_EVNTSEL1:
9e699624 1070 case MSR_K7_EVNTSEL0:
1f3ee616 1071 case MSR_K7_PERFCTR0:
1fdbd48c 1072 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1073 case MSR_AMD64_NB_CFG:
f7c6d140 1074 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1075 data = 0;
1076 break;
9ba075a6
AK		 1077 case MSR_MTRRcap:
1078 data = 0x500 | KVM_NR_VAR_MTRR;
1079 break;
1080 case 0x200 ... 0x2ff:
1081 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1082 case 0xcd: /* fsb frequency */
1083 data = 3;
1084 break;
1085 case MSR_IA32_APICBASE:
1086 data = kvm_get_apic_base(vcpu);
1087 break;
0105d1a5
GN		 1088 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1089 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1090 break;
15c4a640 1091 case MSR_IA32_MISC_ENABLE:
ad312c7c 1092 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1093 break;
847f0ad8
AG		 1094 case MSR_IA32_PERF_STATUS:
1095 /* TSC increment by tick */
1096 data = 1000ULL;
1097 /* CPU multiplier */
1098 data |= (((uint64_t)4ULL) << 40);
1099 break;
15c4a640 1100 case MSR_EFER:
ad312c7c 1101 data = vcpu->arch.shadow_efer;
15c4a640 1102 break;
18068523
GOC		 1103 case MSR_KVM_WALL_CLOCK:
1104 data = vcpu->kvm->arch.wall_clock;
1105 break;
1106 case MSR_KVM_SYSTEM_TIME:
1107 data = vcpu->arch.time;
1108 break;
890ca9ae
HY		 1109 case MSR_IA32_P5_MC_ADDR:
1110 case MSR_IA32_P5_MC_TYPE:
1111 case MSR_IA32_MCG_CAP:
1112 case MSR_IA32_MCG_CTL:
1113 case MSR_IA32_MCG_STATUS:
1114 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1115 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1116 default:
ed85c068
AP		 1117 if (!ignore_msrs) {
1118 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1119 return 1;
1120 } else {
1121 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1122 data = 0;
1123 }
1124 break;
15c4a640
CO		 1125 }
1126 *pdata = data;
1127 return 0;
1128}
1129EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1130
313a3dc7
CO		 1131/*
1132 * Read or write a bunch of msrs. All parameters are kernel addresses.
1133 *
1134 * @return number of msrs set successfully.
1135 */
1136static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1137 struct kvm_msr_entry *entries,
1138 int (*do_msr)(struct kvm_vcpu *vcpu,
1139 unsigned index, u64 *data))
1140{
1141 int i;
1142
1143 vcpu_load(vcpu);
1144
3200f405 1145 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1146 for (i = 0; i < msrs->nmsrs; ++i)
1147 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1148 break;
3200f405 1149 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1150
1151 vcpu_put(vcpu);
1152
1153 return i;
1154}
1155
1156/*
1157 * Read or write a bunch of msrs. Parameters are user addresses.
1158 *
1159 * @return number of msrs set successfully.
1160 */
1161static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1162 int (*do_msr)(struct kvm_vcpu *vcpu,
1163 unsigned index, u64 *data),
1164 int writeback)
1165{
1166 struct kvm_msrs msrs;
1167 struct kvm_msr_entry *entries;
1168 int r, n;
1169 unsigned size;
1170
1171 r = -EFAULT;
1172 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1173 goto out;
1174
1175 r = -E2BIG;
1176 if (msrs.nmsrs >= MAX_IO_MSRS)
1177 goto out;
1178
1179 r = -ENOMEM;
1180 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1181 entries = vmalloc(size);
1182 if (!entries)
1183 goto out;
1184
1185 r = -EFAULT;
1186 if (copy_from_user(entries, user_msrs->entries, size))
1187 goto out_free;
1188
1189 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1190 if (r < 0)
1191 goto out_free;
1192
1193 r = -EFAULT;
1194 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1195 goto out_free;
1196
1197 r = n;
1198
1199out_free:
1200 vfree(entries);
1201out:
1202 return r;
1203}
1204
018d00d2
ZX		 1205int kvm_dev_ioctl_check_extension(long ext)
1206{
1207 int r;
1208
1209 switch (ext) {
1210 case KVM_CAP_IRQCHIP:
1211 case KVM_CAP_HLT:
1212 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1213 case KVM_CAP_SET_TSS_ADDR:
07716717 1214 case KVM_CAP_EXT_CPUID:
c8076604 1215 case KVM_CAP_CLOCKSOURCE:
7837699f 1216 case KVM_CAP_PIT:
a28e4f5a 1217 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1218 case KVM_CAP_MP_STATE:
ed848624 1219 case KVM_CAP_SYNC_MMU:
52d939a0 1220 case KVM_CAP_REINJECT_CONTROL:
4925663a 1221 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1222 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1223 case KVM_CAP_IRQFD:
d34e6b17 1224 case KVM_CAP_IOEVENTFD:
c5ff41ce 1225 case KVM_CAP_PIT2:
e9f42757 1226 case KVM_CAP_PIT_STATE2:
b927a3ce 1227 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
018d00d2
ZX		 1228 r = 1;
1229 break;
542472b5
LV		 1230 case KVM_CAP_COALESCED_MMIO:
1231 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1232 break;
774ead3a
AK		 1233 case KVM_CAP_VAPIC:
1234 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1235 break;
f725230a
AK		 1236 case KVM_CAP_NR_VCPUS:
1237 r = KVM_MAX_VCPUS;
1238 break;
a988b910
AK		 1239 case KVM_CAP_NR_MEMSLOTS:
1240 r = KVM_MEMORY_SLOTS;
1241 break;
2f333bcb
MT		 1242 case KVM_CAP_PV_MMU:
1243 r = !tdp_enabled;
1244 break;
62c476c7 1245 case KVM_CAP_IOMMU:
19de40a8 1246 r = iommu_found();
62c476c7 1247 break;
890ca9ae
HY		 1248 case KVM_CAP_MCE:
1249 r = KVM_MAX_MCE_BANKS;
1250 break;
018d00d2
ZX		 1251 default:
1252 r = 0;
1253 break;
1254 }
1255 return r;
1256
1257}
1258
043405e1
CO		 1259long kvm_arch_dev_ioctl(struct file *filp,
1260 unsigned int ioctl, unsigned long arg)
1261{
1262 void __user *argp = (void __user *)arg;
1263 long r;
1264
1265 switch (ioctl) {
1266 case KVM_GET_MSR_INDEX_LIST: {
1267 struct kvm_msr_list __user *user_msr_list = argp;
1268 struct kvm_msr_list msr_list;
1269 unsigned n;
1270
1271 r = -EFAULT;
1272 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1273 goto out;
1274 n = msr_list.nmsrs;
1275 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1276 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1277 goto out;
1278 r = -E2BIG;
e125e7b6 1279 if (n < msr_list.nmsrs)
043405e1
CO		 1280 goto out;
1281 r = -EFAULT;
1282 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1283 num_msrs_to_save * sizeof(u32)))
1284 goto out;
e125e7b6 1285 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1286 &emulated_msrs,
1287 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1288 goto out;
1289 r = 0;
1290 break;
1291 }
674eea0f
AK		 1292 case KVM_GET_SUPPORTED_CPUID: {
1293 struct kvm_cpuid2 __user *cpuid_arg = argp;
1294 struct kvm_cpuid2 cpuid;
1295
1296 r = -EFAULT;
1297 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1298 goto out;
1299 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1300 cpuid_arg->entries);
674eea0f
AK		 1301 if (r)
1302 goto out;
1303
1304 r = -EFAULT;
1305 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1306 goto out;
1307 r = 0;
1308 break;
1309 }
890ca9ae
HY		 1310 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1311 u64 mce_cap;
1312
1313 mce_cap = KVM_MCE_CAP_SUPPORTED;
1314 r = -EFAULT;
1315 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1316 goto out;
1317 r = 0;
1318 break;
1319 }
043405e1
CO		 1320 default:
1321 r = -EINVAL;
1322 }
1323out:
1324 return r;
1325}
1326
313a3dc7
CO		 1327void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1328{
1329 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1330 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1331}
1332
1333void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1334{
1335 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1336 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1337}
1338
07716717 1339static int is_efer_nx(void)
313a3dc7 1340{
e286e86e 1341 unsigned long long efer = 0;
313a3dc7 1342
e286e86e 1343 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1344 return efer & EFER_NX;
1345}
1346
1347static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1348{
1349 int i;
1350 struct kvm_cpuid_entry2 *e, *entry;
1351
313a3dc7 1352 entry = NULL;
ad312c7c
ZX		 1353 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1354 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1355 if (e->function == 0x80000001) {
1356 entry = e;
1357 break;
1358 }
1359 }
07716717 1360 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1361 entry->edx &= ~(1 << 20);
1362 printk(KERN_INFO "kvm: guest NX capability removed\n");
1363 }
1364}
1365
07716717 1366/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1367static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1368 struct kvm_cpuid *cpuid,
1369 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1370{
1371 int r, i;
1372 struct kvm_cpuid_entry *cpuid_entries;
1373
1374 r = -E2BIG;
1375 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1376 goto out;
1377 r = -ENOMEM;
1378 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1379 if (!cpuid_entries)
1380 goto out;
1381 r = -EFAULT;
1382 if (copy_from_user(cpuid_entries, entries,
1383 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1384 goto out_free;
1385 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1386 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1387 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1388 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1389 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1390 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1391 vcpu->arch.cpuid_entries[i].index = 0;
1392 vcpu->arch.cpuid_entries[i].flags = 0;
1393 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1394 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1395 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1396 }
1397 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1398 cpuid_fix_nx_cap(vcpu);
1399 r = 0;
fc61b800 1400 kvm_apic_set_version(vcpu);
07716717
DK		 1401
1402out_free:
1403 vfree(cpuid_entries);
1404out:
1405 return r;
1406}
1407
1408static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1409 struct kvm_cpuid2 *cpuid,
1410 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1411{
1412 int r;
1413
1414 r = -E2BIG;
1415 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1416 goto out;
1417 r = -EFAULT;
ad312c7c 1418 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1419 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1420 goto out;
ad312c7c 1421 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1422 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1423 return 0;
1424
1425out:
1426 return r;
1427}
1428
07716717 1429static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1430 struct kvm_cpuid2 *cpuid,
1431 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1432{
1433 int r;
1434
1435 r = -E2BIG;
ad312c7c 1436 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1437 goto out;
1438 r = -EFAULT;
ad312c7c 1439 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1440 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1441 goto out;
1442 return 0;
1443
1444out:
ad312c7c 1445 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1446 return r;
1447}
1448
07716717 1449static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1450 u32 index)
07716717
DK		 1451{
1452 entry->function = function;
1453 entry->index = index;
1454 cpuid_count(entry->function, entry->index,
19355475 1455 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1456 entry->flags = 0;
1457}
1458
7faa4ee1
AK		 1459#define F(x) bit(X86_FEATURE_##x)
1460
07716717
DK		 1461static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1462 u32 index, int *nent, int maxnent)
1463{
7faa4ee1 1464 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
344f414f 1465 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
07716717 1466#ifdef CONFIG_X86_64
7faa4ee1
AK		 1467 unsigned f_lm = F(LM);
1468#else
1469 unsigned f_lm = 0;
07716717 1470#endif
7faa4ee1
AK		 1471
1472 /* cpuid 1.edx */
1473 const u32 kvm_supported_word0_x86_features =
1474 F(FPU) | F(VME) | F(DE) | F(PSE) |
1475 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1476 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1477 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1478 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1479 0 /* Reserved, DS, ACPI */ | F(MMX) |
1480 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1481 0 /* HTT, TM, Reserved, PBE */;
1482 /* cpuid 0x80000001.edx */
1483 const u32 kvm_supported_word1_x86_features =
1484 F(FPU) | F(VME) | F(DE) | F(PSE) |
1485 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1486 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1487 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1488 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1489 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
344f414f 1490 F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ |
7faa4ee1
AK		 1491 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1492 /* cpuid 1.ecx */
1493 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1494 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1495 0 /* DS-CPL, VMX, SMX, EST */ |
1496 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1497 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1498 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1499 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1500 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1501 /* cpuid 0x80000001.ecx */
07716717 1502 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1503 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1504 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1505 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1506 0 /* SKINIT */ | 0 /* WDT */;
07716717 1507
19355475 1508 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1509 get_cpu();
1510 do_cpuid_1_ent(entry, function, index);
1511 ++*nent;
1512
1513 switch (function) {
1514 case 0:
1515 entry->eax = min(entry->eax, (u32)0xb);
1516 break;
1517 case 1:
1518 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1519 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1520 /* we support x2apic emulation even if host does not support
1521 * it since we emulate x2apic in software */
1522 entry->ecx |= F(X2APIC);
07716717
DK		 1523 break;
1524 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1525 * may return different values. This forces us to get_cpu() before
1526 * issuing the first command, and also to emulate this annoying behavior
1527 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1528 case 2: {
1529 int t, times = entry->eax & 0xff;
1530
1531 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1532 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1533 for (t = 1; t < times && *nent < maxnent; ++t) {
1534 do_cpuid_1_ent(&entry[t], function, 0);
1535 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1536 ++*nent;
1537 }
1538 break;
1539 }
1540 /* function 4 and 0xb have additional index. */
1541 case 4: {
14af3f3c 1542 int i, cache_type;
07716717
DK		 1543
1544 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1545 /* read more entries until cache_type is zero */
14af3f3c
HH		 1546 for (i = 1; *nent < maxnent; ++i) {
1547 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1548 if (!cache_type)
1549 break;
14af3f3c
HH		 1550 do_cpuid_1_ent(&entry[i], function, i);
1551 entry[i].flags |=
07716717
DK		 1552 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1553 ++*nent;
1554 }
1555 break;
1556 }
1557 case 0xb: {
14af3f3c 1558 int i, level_type;
07716717
DK		 1559
1560 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1561 /* read more entries until level_type is zero */
14af3f3c 1562 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1563 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1564 if (!level_type)
1565 break;
14af3f3c
HH		 1566 do_cpuid_1_ent(&entry[i], function, i);
1567 entry[i].flags |=
07716717
DK		 1568 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1569 ++*nent;
1570 }
1571 break;
1572 }
1573 case 0x80000000:
1574 entry->eax = min(entry->eax, 0x8000001a);
1575 break;
1576 case 0x80000001:
1577 entry->edx &= kvm_supported_word1_x86_features;
1578 entry->ecx &= kvm_supported_word6_x86_features;
1579 break;
1580 }
1581 put_cpu();
1582}
1583
7faa4ee1
AK		 1584#undef F
1585
674eea0f 1586static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1587 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1588{
1589 struct kvm_cpuid_entry2 *cpuid_entries;
1590 int limit, nent = 0, r = -E2BIG;
1591 u32 func;
1592
1593 if (cpuid->nent < 1)
1594 goto out;
6a544355
AK		 1595 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1596 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1597 r = -ENOMEM;
1598 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1599 if (!cpuid_entries)
1600 goto out;
1601
1602 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1603 limit = cpuid_entries[0].eax;
1604 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1605 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1606 &nent, cpuid->nent);
07716717
DK		 1607 r = -E2BIG;
1608 if (nent >= cpuid->nent)
1609 goto out_free;
1610
1611 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1612 limit = cpuid_entries[nent - 1].eax;
1613 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1614 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1615 &nent, cpuid->nent);
cb007648
MM		 1616 r = -E2BIG;
1617 if (nent >= cpuid->nent)
1618 goto out_free;
1619
07716717
DK		 1620 r = -EFAULT;
1621 if (copy_to_user(entries, cpuid_entries,
19355475 1622 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1623 goto out_free;
1624 cpuid->nent = nent;
1625 r = 0;
1626
1627out_free:
1628 vfree(cpuid_entries);
1629out:
1630 return r;
1631}
1632
313a3dc7
CO		 1633static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1634 struct kvm_lapic_state *s)
1635{
1636 vcpu_load(vcpu);
ad312c7c 1637 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1638 vcpu_put(vcpu);
1639
1640 return 0;
1641}
1642
1643static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1644 struct kvm_lapic_state *s)
1645{
1646 vcpu_load(vcpu);
ad312c7c 1647 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1648 kvm_apic_post_state_restore(vcpu);
cb142eb7 1649 update_cr8_intercept(vcpu);
313a3dc7
CO		 1650 vcpu_put(vcpu);
1651
1652 return 0;
1653}
1654
f77bc6a4
ZX		 1655static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1656 struct kvm_interrupt *irq)
1657{
1658 if (irq->irq < 0 || irq->irq >= 256)
1659 return -EINVAL;
1660 if (irqchip_in_kernel(vcpu->kvm))
1661 return -ENXIO;
1662 vcpu_load(vcpu);
1663
66fd3f7f 1664 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1665
1666 vcpu_put(vcpu);
1667
1668 return 0;
1669}
1670
c4abb7c9
JK		 1671static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1672{
1673 vcpu_load(vcpu);
1674 kvm_inject_nmi(vcpu);
1675 vcpu_put(vcpu);
1676
1677 return 0;
1678}
1679
b209749f
AK		 1680static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1681 struct kvm_tpr_access_ctl *tac)
1682{
1683 if (tac->flags)
1684 return -EINVAL;
1685 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1686 return 0;
1687}
1688
890ca9ae
HY		 1689static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1690 u64 mcg_cap)
1691{
1692 int r;
1693 unsigned bank_num = mcg_cap & 0xff, bank;
1694
1695 r = -EINVAL;
1696 if (!bank_num)
1697 goto out;
1698 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1699 goto out;
1700 r = 0;
1701 vcpu->arch.mcg_cap = mcg_cap;
1702 /* Init IA32_MCG_CTL to all 1s */
1703 if (mcg_cap & MCG_CTL_P)
1704 vcpu->arch.mcg_ctl = ~(u64)0;
1705 /* Init IA32_MCi_CTL to all 1s */
1706 for (bank = 0; bank < bank_num; bank++)
1707 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1708out:
1709 return r;
1710}
1711
1712static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1713 struct kvm_x86_mce *mce)
1714{
1715 u64 mcg_cap = vcpu->arch.mcg_cap;
1716 unsigned bank_num = mcg_cap & 0xff;
1717 u64 *banks = vcpu->arch.mce_banks;
1718
1719 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1720 return -EINVAL;
1721 /*
1722 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1723 * reporting is disabled
1724 */
1725 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1726 vcpu->arch.mcg_ctl != ~(u64)0)
1727 return 0;
1728 banks += 4 * mce->bank;
1729 /*
1730 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1731 * reporting is disabled for the bank
1732 */
1733 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1734 return 0;
1735 if (mce->status & MCI_STATUS_UC) {
1736 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1737 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1738 printk(KERN_DEBUG "kvm: set_mce: "
1739 "injects mce exception while "
1740 "previous one is in progress!\n");
1741 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1742 return 0;
1743 }
1744 if (banks[1] & MCI_STATUS_VAL)
1745 mce->status |= MCI_STATUS_OVER;
1746 banks[2] = mce->addr;
1747 banks[3] = mce->misc;
1748 vcpu->arch.mcg_status = mce->mcg_status;
1749 banks[1] = mce->status;
1750 kvm_queue_exception(vcpu, MC_VECTOR);
1751 } else if (!(banks[1] & MCI_STATUS_VAL)
1752 || !(banks[1] & MCI_STATUS_UC)) {
1753 if (banks[1] & MCI_STATUS_VAL)
1754 mce->status |= MCI_STATUS_OVER;
1755 banks[2] = mce->addr;
1756 banks[3] = mce->misc;
1757 banks[1] = mce->status;
1758 } else
1759 banks[1] |= MCI_STATUS_OVER;
1760 return 0;
1761}
1762
313a3dc7
CO		 1763long kvm_arch_vcpu_ioctl(struct file *filp,
1764 unsigned int ioctl, unsigned long arg)
1765{
1766 struct kvm_vcpu *vcpu = filp->private_data;
1767 void __user *argp = (void __user *)arg;
1768 int r;
b772ff36 1769 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1770
1771 switch (ioctl) {
1772 case KVM_GET_LAPIC: {
b772ff36 1773 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1774
b772ff36
DH		 1775 r = -ENOMEM;
1776 if (!lapic)
1777 goto out;
1778 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1779 if (r)
1780 goto out;
1781 r = -EFAULT;
b772ff36 1782 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1783 goto out;
1784 r = 0;
1785 break;
1786 }
1787 case KVM_SET_LAPIC: {
b772ff36
DH		 1788 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1789 r = -ENOMEM;
1790 if (!lapic)
1791 goto out;
313a3dc7 1792 r = -EFAULT;
b772ff36 1793 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1794 goto out;
b772ff36 1795 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1796 if (r)
1797 goto out;
1798 r = 0;
1799 break;
1800 }
f77bc6a4
ZX		 1801 case KVM_INTERRUPT: {
1802 struct kvm_interrupt irq;
1803
1804 r = -EFAULT;
1805 if (copy_from_user(&irq, argp, sizeof irq))
1806 goto out;
1807 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1808 if (r)
1809 goto out;
1810 r = 0;
1811 break;
1812 }
c4abb7c9
JK		 1813 case KVM_NMI: {
1814 r = kvm_vcpu_ioctl_nmi(vcpu);
1815 if (r)
1816 goto out;
1817 r = 0;
1818 break;
1819 }
313a3dc7
CO		 1820 case KVM_SET_CPUID: {
1821 struct kvm_cpuid __user *cpuid_arg = argp;
1822 struct kvm_cpuid cpuid;
1823
1824 r = -EFAULT;
1825 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1826 goto out;
1827 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1828 if (r)
1829 goto out;
1830 break;
1831 }
07716717
DK		 1832 case KVM_SET_CPUID2: {
1833 struct kvm_cpuid2 __user *cpuid_arg = argp;
1834 struct kvm_cpuid2 cpuid;
1835
1836 r = -EFAULT;
1837 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1838 goto out;
1839 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1840 cpuid_arg->entries);
07716717
DK		 1841 if (r)
1842 goto out;
1843 break;
1844 }
1845 case KVM_GET_CPUID2: {
1846 struct kvm_cpuid2 __user *cpuid_arg = argp;
1847 struct kvm_cpuid2 cpuid;
1848
1849 r = -EFAULT;
1850 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1851 goto out;
1852 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1853 cpuid_arg->entries);
07716717
DK		 1854 if (r)
1855 goto out;
1856 r = -EFAULT;
1857 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1858 goto out;
1859 r = 0;
1860 break;
1861 }
313a3dc7
CO		 1862 case KVM_GET_MSRS:
1863 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1864 break;
1865 case KVM_SET_MSRS:
1866 r = msr_io(vcpu, argp, do_set_msr, 0);
1867 break;
b209749f
AK		 1868 case KVM_TPR_ACCESS_REPORTING: {
1869 struct kvm_tpr_access_ctl tac;
1870
1871 r = -EFAULT;
1872 if (copy_from_user(&tac, argp, sizeof tac))
1873 goto out;
1874 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1875 if (r)
1876 goto out;
1877 r = -EFAULT;
1878 if (copy_to_user(argp, &tac, sizeof tac))
1879 goto out;
1880 r = 0;
1881 break;
1882 };
b93463aa
AK		 1883 case KVM_SET_VAPIC_ADDR: {
1884 struct kvm_vapic_addr va;
1885
1886 r = -EINVAL;
1887 if (!irqchip_in_kernel(vcpu->kvm))
1888 goto out;
1889 r = -EFAULT;
1890 if (copy_from_user(&va, argp, sizeof va))
1891 goto out;
1892 r = 0;
1893 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1894 break;
1895 }
890ca9ae
HY		 1896 case KVM_X86_SETUP_MCE: {
1897 u64 mcg_cap;
1898
1899 r = -EFAULT;
1900 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1901 goto out;
1902 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1903 break;
1904 }
1905 case KVM_X86_SET_MCE: {
1906 struct kvm_x86_mce mce;
1907
1908 r = -EFAULT;
1909 if (copy_from_user(&mce, argp, sizeof mce))
1910 goto out;
1911 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1912 break;
1913 }
313a3dc7
CO		 1914 default:
1915 r = -EINVAL;
1916 }
1917out:
7a6ce84c 1918 kfree(lapic);
313a3dc7
CO		 1919 return r;
1920}
1921
1fe779f8
CO		 1922static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1923{
1924 int ret;
1925
1926 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1927 return -1;
1928 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1929 return ret;
1930}
1931
b927a3ce
SY		 1932static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
1933 u64 ident_addr)
1934{
1935 kvm->arch.ept_identity_map_addr = ident_addr;
1936 return 0;
1937}
1938
1fe779f8
CO		 1939static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1940 u32 kvm_nr_mmu_pages)
1941{
1942 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1943 return -EINVAL;
1944
72dc67a6 1945 down_write(&kvm->slots_lock);
7c8a83b7 1946 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1947
1948 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1949 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1950
7c8a83b7 1951 spin_unlock(&kvm->mmu_lock);
72dc67a6 1952 up_write(&kvm->slots_lock);
1fe779f8
CO		 1953 return 0;
1954}
1955
1956static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1957{
f05e70ac 1958 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1959}
1960
e9f85cde
ZX		 1961gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1962{
1963 int i;
1964 struct kvm_mem_alias *alias;
1965
d69fb81f
ZX		 1966 for (i = 0; i < kvm->arch.naliases; ++i) {
1967 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1968 if (gfn >= alias->base_gfn
1969 && gfn < alias->base_gfn + alias->npages)
1970 return alias->target_gfn + gfn - alias->base_gfn;
1971 }
1972 return gfn;
1973}
1974
1fe779f8
CO		 1975/*
1976 * Set a new alias region. Aliases map a portion of physical memory into
1977 * another portion. This is useful for memory windows, for example the PC
1978 * VGA region.
1979 */
1980static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1981 struct kvm_memory_alias *alias)
1982{
1983 int r, n;
1984 struct kvm_mem_alias *p;
1985
1986 r = -EINVAL;
1987 /* General sanity checks */
1988 if (alias->memory_size & (PAGE_SIZE - 1))
1989 goto out;
1990 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1991 goto out;
1992 if (alias->slot >= KVM_ALIAS_SLOTS)
1993 goto out;
1994 if (alias->guest_phys_addr + alias->memory_size
1995 < alias->guest_phys_addr)
1996 goto out;
1997 if (alias->target_phys_addr + alias->memory_size
1998 < alias->target_phys_addr)
1999 goto out;
2000
72dc67a6 2001 down_write(&kvm->slots_lock);
a1708ce8 2002 spin_lock(&kvm->mmu_lock);
1fe779f8 2003
d69fb81f 2004 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 2005 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2006 p->npages = alias->memory_size >> PAGE_SHIFT;
2007 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
2008
2009 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 2010 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 2011 break;
d69fb81f 2012 kvm->arch.naliases = n;
1fe779f8 2013
a1708ce8 2014 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 2015 kvm_mmu_zap_all(kvm);
2016
72dc67a6 2017 up_write(&kvm->slots_lock);
1fe779f8
CO		 2018
2019 return 0;
2020
2021out:
2022 return r;
2023}
2024
2025static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2026{
2027 int r;
2028
2029 r = 0;
2030 switch (chip->chip_id) {
2031 case KVM_IRQCHIP_PIC_MASTER:
2032 memcpy(&chip->chip.pic,
2033 &pic_irqchip(kvm)->pics[0],
2034 sizeof(struct kvm_pic_state));
2035 break;
2036 case KVM_IRQCHIP_PIC_SLAVE:
2037 memcpy(&chip->chip.pic,
2038 &pic_irqchip(kvm)->pics[1],
2039 sizeof(struct kvm_pic_state));
2040 break;
2041 case KVM_IRQCHIP_IOAPIC:
2042 memcpy(&chip->chip.ioapic,
2043 ioapic_irqchip(kvm),
2044 sizeof(struct kvm_ioapic_state));
2045 break;
2046 default:
2047 r = -EINVAL;
2048 break;
2049 }
2050 return r;
2051}
2052
2053static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2054{
2055 int r;
2056
2057 r = 0;
2058 switch (chip->chip_id) {
2059 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2060 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2061 memcpy(&pic_irqchip(kvm)->pics[0],
2062 &chip->chip.pic,
2063 sizeof(struct kvm_pic_state));
894a9c55 2064 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2065 break;
2066 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2067 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2068 memcpy(&pic_irqchip(kvm)->pics[1],
2069 &chip->chip.pic,
2070 sizeof(struct kvm_pic_state));
894a9c55 2071 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2072 break;
2073 case KVM_IRQCHIP_IOAPIC:
894a9c55 2074 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2075 memcpy(ioapic_irqchip(kvm),
2076 &chip->chip.ioapic,
2077 sizeof(struct kvm_ioapic_state));
894a9c55 2078 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2079 break;
2080 default:
2081 r = -EINVAL;
2082 break;
2083 }
2084 kvm_pic_update_irq(pic_irqchip(kvm));
2085 return r;
2086}
2087
e0f63cb9
SY		 2088static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2089{
2090 int r = 0;
2091
894a9c55 2092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2093 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2094 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2095 return r;
2096}
2097
2098static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2099{
2100 int r = 0;
2101
894a9c55 2102 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2103 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2104 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2105 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2106 return r;
2107}
2108
2109static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2110{
2111 int r = 0;
2112
2113 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2114 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2115 sizeof(ps->channels));
2116 ps->flags = kvm->arch.vpit->pit_state.flags;
2117 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2118 return r;
2119}
2120
2121static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2122{
2123 int r = 0, start = 0;
2124 u32 prev_legacy, cur_legacy;
2125 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2126 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2127 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2128 if (!prev_legacy && cur_legacy)
2129 start = 1;
2130 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2131 sizeof(kvm->arch.vpit->pit_state.channels));
2132 kvm->arch.vpit->pit_state.flags = ps->flags;
2133 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2134 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2135 return r;
2136}
2137
52d939a0
MT		 2138static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2139 struct kvm_reinject_control *control)
2140{
2141 if (!kvm->arch.vpit)
2142 return -ENXIO;
894a9c55 2143 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2144 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2145 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2146 return 0;
2147}
2148
5bb064dc
ZX		 2149/*
2150 * Get (and clear) the dirty memory log for a memory slot.
2151 */
2152int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2153 struct kvm_dirty_log *log)
2154{
2155 int r;
2156 int n;
2157 struct kvm_memory_slot *memslot;
2158 int is_dirty = 0;
2159
72dc67a6 2160 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2161
2162 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2163 if (r)
2164 goto out;
2165
2166 /* If nothing is dirty, don't bother messing with page tables. */
2167 if (is_dirty) {
7c8a83b7 2168 spin_lock(&kvm->mmu_lock);
5bb064dc 2169 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2170 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2171 memslot = &kvm->memslots[log->slot];
2172 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2173 memset(memslot->dirty_bitmap, 0, n);
2174 }
2175 r = 0;
2176out:
72dc67a6 2177 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2178 return r;
2179}
2180
1fe779f8
CO		 2181long kvm_arch_vm_ioctl(struct file *filp,
2182 unsigned int ioctl, unsigned long arg)
2183{
2184 struct kvm *kvm = filp->private_data;
2185 void __user *argp = (void __user *)arg;
2186 int r = -EINVAL;
f0d66275
DH		 2187 /*
2188 * This union makes it completely explicit to gcc-3.x
2189 * that these two variables' stack usage should be
2190 * combined, not added together.
2191 */
2192 union {
2193 struct kvm_pit_state ps;
e9f42757 2194 struct kvm_pit_state2 ps2;
f0d66275 2195 struct kvm_memory_alias alias;
c5ff41ce 2196 struct kvm_pit_config pit_config;
f0d66275 2197 } u;
1fe779f8
CO		 2198
2199 switch (ioctl) {
2200 case KVM_SET_TSS_ADDR:
2201 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2202 if (r < 0)
2203 goto out;
2204 break;
b927a3ce
SY		 2205 case KVM_SET_IDENTITY_MAP_ADDR: {
2206 u64 ident_addr;
2207
2208 r = -EFAULT;
2209 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2210 goto out;
2211 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2212 if (r < 0)
2213 goto out;
2214 break;
2215 }
1fe779f8
CO		 2216 case KVM_SET_MEMORY_REGION: {
2217 struct kvm_memory_region kvm_mem;
2218 struct kvm_userspace_memory_region kvm_userspace_mem;
2219
2220 r = -EFAULT;
2221 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2222 goto out;
2223 kvm_userspace_mem.slot = kvm_mem.slot;
2224 kvm_userspace_mem.flags = kvm_mem.flags;
2225 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2226 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2227 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2228 if (r)
2229 goto out;
2230 break;
2231 }
2232 case KVM_SET_NR_MMU_PAGES:
2233 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2234 if (r)
2235 goto out;
2236 break;
2237 case KVM_GET_NR_MMU_PAGES:
2238 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2239 break;
f0d66275 2240 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2241 r = -EFAULT;
f0d66275 2242 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2243 goto out;
f0d66275 2244 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2245 if (r)
2246 goto out;
2247 break;
1fe779f8
CO		 2248 case KVM_CREATE_IRQCHIP:
2249 r = -ENOMEM;
d7deeeb0
ZX		 2250 kvm->arch.vpic = kvm_create_pic(kvm);
2251 if (kvm->arch.vpic) {
1fe779f8
CO		 2252 r = kvm_ioapic_init(kvm);
2253 if (r) {
d7deeeb0
ZX		 2254 kfree(kvm->arch.vpic);
2255 kvm->arch.vpic = NULL;
1fe779f8
CO		 2256 goto out;
2257 }
2258 } else
2259 goto out;
399ec807
AK		 2260 r = kvm_setup_default_irq_routing(kvm);
2261 if (r) {
2262 kfree(kvm->arch.vpic);
2263 kfree(kvm->arch.vioapic);
2264 goto out;
2265 }
1fe779f8 2266 break;
7837699f 2267 case KVM_CREATE_PIT:
c5ff41ce
JK		 2268 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2269 goto create_pit;
2270 case KVM_CREATE_PIT2:
2271 r = -EFAULT;
2272 if (copy_from_user(&u.pit_config, argp,
2273 sizeof(struct kvm_pit_config)))
2274 goto out;
2275 create_pit:
108b5669 2276 down_write(&kvm->slots_lock);
269e05e4
AK		 2277 r = -EEXIST;
2278 if (kvm->arch.vpit)
2279 goto create_pit_unlock;
7837699f 2280 r = -ENOMEM;
c5ff41ce 2281 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2282 if (kvm->arch.vpit)
2283 r = 0;
269e05e4 2284 create_pit_unlock:
108b5669 2285 up_write(&kvm->slots_lock);
7837699f 2286 break;
4925663a 2287 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2288 case KVM_IRQ_LINE: {
2289 struct kvm_irq_level irq_event;
2290
2291 r = -EFAULT;
2292 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2293 goto out;
2294 if (irqchip_in_kernel(kvm)) {
4925663a 2295 __s32 status;
fa40a821 2296 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2297 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2298 irq_event.irq, irq_event.level);
fa40a821 2299 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2300 if (ioctl == KVM_IRQ_LINE_STATUS) {
2301 irq_event.status = status;
2302 if (copy_to_user(argp, &irq_event,
2303 sizeof irq_event))
2304 goto out;
2305 }
1fe779f8
CO		 2306 r = 0;
2307 }
2308 break;
2309 }
2310 case KVM_GET_IRQCHIP: {
2311 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2312 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2313
f0d66275
DH		 2314 r = -ENOMEM;
2315 if (!chip)
1fe779f8 2316 goto out;
f0d66275
DH		 2317 r = -EFAULT;
2318 if (copy_from_user(chip, argp, sizeof *chip))
2319 goto get_irqchip_out;
1fe779f8
CO		 2320 r = -ENXIO;
2321 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2322 goto get_irqchip_out;
2323 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2324 if (r)
f0d66275 2325 goto get_irqchip_out;
1fe779f8 2326 r = -EFAULT;
f0d66275
DH		 2327 if (copy_to_user(argp, chip, sizeof *chip))
2328 goto get_irqchip_out;
1fe779f8 2329 r = 0;
f0d66275
DH		 2330 get_irqchip_out:
2331 kfree(chip);
2332 if (r)
2333 goto out;
1fe779f8
CO		 2334 break;
2335 }
2336 case KVM_SET_IRQCHIP: {
2337 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2338 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2339
f0d66275
DH		 2340 r = -ENOMEM;
2341 if (!chip)
1fe779f8 2342 goto out;
f0d66275
DH		 2343 r = -EFAULT;
2344 if (copy_from_user(chip, argp, sizeof *chip))
2345 goto set_irqchip_out;
1fe779f8
CO		 2346 r = -ENXIO;
2347 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2348 goto set_irqchip_out;
2349 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2350 if (r)
f0d66275 2351 goto set_irqchip_out;
1fe779f8 2352 r = 0;
f0d66275
DH		 2353 set_irqchip_out:
2354 kfree(chip);
2355 if (r)
2356 goto out;
1fe779f8
CO		 2357 break;
2358 }
e0f63cb9 2359 case KVM_GET_PIT: {
e0f63cb9 2360 r = -EFAULT;
f0d66275 2361 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2362 goto out;
2363 r = -ENXIO;
2364 if (!kvm->arch.vpit)
2365 goto out;
f0d66275 2366 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2367 if (r)
2368 goto out;
2369 r = -EFAULT;
f0d66275 2370 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2371 goto out;
2372 r = 0;
2373 break;
2374 }
2375 case KVM_SET_PIT: {
e0f63cb9 2376 r = -EFAULT;
f0d66275 2377 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2378 goto out;
2379 r = -ENXIO;
2380 if (!kvm->arch.vpit)
2381 goto out;
f0d66275 2382 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2383 if (r)
2384 goto out;
2385 r = 0;
2386 break;
2387 }
e9f42757
BK		 2388 case KVM_GET_PIT2: {
2389 r = -ENXIO;
2390 if (!kvm->arch.vpit)
2391 goto out;
2392 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2393 if (r)
2394 goto out;
2395 r = -EFAULT;
2396 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2397 goto out;
2398 r = 0;
2399 break;
2400 }
2401 case KVM_SET_PIT2: {
2402 r = -EFAULT;
2403 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2404 goto out;
2405 r = -ENXIO;
2406 if (!kvm->arch.vpit)
2407 goto out;
2408 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2409 if (r)
2410 goto out;
2411 r = 0;
2412 break;
2413 }
52d939a0
MT		 2414 case KVM_REINJECT_CONTROL: {
2415 struct kvm_reinject_control control;
2416 r = -EFAULT;
2417 if (copy_from_user(&control, argp, sizeof(control)))
2418 goto out;
2419 r = kvm_vm_ioctl_reinject(kvm, &control);
2420 if (r)
2421 goto out;
2422 r = 0;
2423 break;
2424 }
1fe779f8
CO		 2425 default:
2426 ;
2427 }
2428out:
2429 return r;
2430}
2431
a16b043c 2432static void kvm_init_msr_list(void)
043405e1
CO		 2433{
2434 u32 dummy[2];
2435 unsigned i, j;
2436
2437 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2438 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2439 continue;
2440 if (j < i)
2441 msrs_to_save[j] = msrs_to_save[i];
2442 j++;
2443 }
2444 num_msrs_to_save = j;
2445}
2446
bda9020e
MT		 2447static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2448 const void *v)
bbd9b64e 2449{
bda9020e
MT		 2450 if (vcpu->arch.apic &&
2451 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2452 return 0;
bbd9b64e 2453
bda9020e 2454 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2455}
2456
bda9020e 2457static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2458{
bda9020e
MT		 2459 if (vcpu->arch.apic &&
2460 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2461 return 0;
bbd9b64e 2462
bda9020e 2463 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2464}
2465
cded19f3
HE		 2466static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2467 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2468{
2469 void *data = val;
10589a46 2470 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2471
2472 while (bytes) {
ad312c7c 2473 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2474 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2475 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2476 int ret;
2477
10589a46
MT		 2478 if (gpa == UNMAPPED_GVA) {
2479 r = X86EMUL_PROPAGATE_FAULT;
2480 goto out;
2481 }
77c2002e 2482 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2483 if (ret < 0) {
2484 r = X86EMUL_UNHANDLEABLE;
2485 goto out;
2486 }
bbd9b64e 2487
77c2002e
IE		 2488 bytes -= toread;
2489 data += toread;
2490 addr += toread;
bbd9b64e 2491 }
10589a46 2492out:
10589a46 2493 return r;
bbd9b64e 2494}
77c2002e 2495
cded19f3
HE		 2496static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2497 struct kvm_vcpu *vcpu)
77c2002e
IE		 2498{
2499 void *data = val;
2500 int r = X86EMUL_CONTINUE;
2501
2502 while (bytes) {
2503 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2504 unsigned offset = addr & (PAGE_SIZE-1);
2505 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2506 int ret;
2507
2508 if (gpa == UNMAPPED_GVA) {
2509 r = X86EMUL_PROPAGATE_FAULT;
2510 goto out;
2511 }
2512 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2513 if (ret < 0) {
2514 r = X86EMUL_UNHANDLEABLE;
2515 goto out;
2516 }
2517
2518 bytes -= towrite;
2519 data += towrite;
2520 addr += towrite;
2521 }
2522out:
2523 return r;
2524}
2525
bbd9b64e 2526
bbd9b64e
CO		 2527static int emulator_read_emulated(unsigned long addr,
2528 void *val,
2529 unsigned int bytes,
2530 struct kvm_vcpu *vcpu)
2531{
bbd9b64e
CO		 2532 gpa_t gpa;
2533
2534 if (vcpu->mmio_read_completed) {
2535 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2536 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2537 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2538 vcpu->mmio_read_completed = 0;
2539 return X86EMUL_CONTINUE;
2540 }
2541
ad312c7c 2542 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2543
2544 /* For APIC access vmexit */
2545 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2546 goto mmio;
2547
77c2002e
IE		 2548 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2549 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2550 return X86EMUL_CONTINUE;
2551 if (gpa == UNMAPPED_GVA)
2552 return X86EMUL_PROPAGATE_FAULT;
2553
2554mmio:
2555 /*
2556 * Is this MMIO handled locally?
2557 */
aec51dc4
AK		 2558 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2559 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2560 return X86EMUL_CONTINUE;
2561 }
aec51dc4
AK		 2562
2563 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2564
2565 vcpu->mmio_needed = 1;
2566 vcpu->mmio_phys_addr = gpa;
2567 vcpu->mmio_size = bytes;
2568 vcpu->mmio_is_write = 0;
2569
2570 return X86EMUL_UNHANDLEABLE;
2571}
2572
3200f405 2573int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2574 const void *val, int bytes)
bbd9b64e
CO		 2575{
2576 int ret;
2577
2578 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2579 if (ret < 0)
bbd9b64e 2580 return 0;
ad218f85 2581 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2582 return 1;
2583}
2584
2585static int emulator_write_emulated_onepage(unsigned long addr,
2586 const void *val,
2587 unsigned int bytes,
2588 struct kvm_vcpu *vcpu)
2589{
10589a46
MT		 2590 gpa_t gpa;
2591
10589a46 2592 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2593
2594 if (gpa == UNMAPPED_GVA) {
c3c91fee 2595 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2596 return X86EMUL_PROPAGATE_FAULT;
2597 }
2598
2599 /* For APIC access vmexit */
2600 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2601 goto mmio;
2602
2603 if (emulator_write_phys(vcpu, gpa, val, bytes))
2604 return X86EMUL_CONTINUE;
2605
2606mmio:
aec51dc4 2607 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2608 /*
2609 * Is this MMIO handled locally?
2610 */
bda9020e 2611 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2612 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2613
2614 vcpu->mmio_needed = 1;
2615 vcpu->mmio_phys_addr = gpa;
2616 vcpu->mmio_size = bytes;
2617 vcpu->mmio_is_write = 1;
2618 memcpy(vcpu->mmio_data, val, bytes);
2619
2620 return X86EMUL_CONTINUE;
2621}
2622
2623int emulator_write_emulated(unsigned long addr,
2624 const void *val,
2625 unsigned int bytes,
2626 struct kvm_vcpu *vcpu)
2627{
2628 /* Crossing a page boundary? */
2629 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2630 int rc, now;
2631
2632 now = -addr & ~PAGE_MASK;
2633 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2634 if (rc != X86EMUL_CONTINUE)
2635 return rc;
2636 addr += now;
2637 val += now;
2638 bytes -= now;
2639 }
2640 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2641}
2642EXPORT_SYMBOL_GPL(emulator_write_emulated);
2643
2644static int emulator_cmpxchg_emulated(unsigned long addr,
2645 const void *old,
2646 const void *new,
2647 unsigned int bytes,
2648 struct kvm_vcpu *vcpu)
2649{
9f51e24e 2650 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 2651#ifndef CONFIG_X86_64
2652 /* guests cmpxchg8b have to be emulated atomically */
2653 if (bytes == 8) {
10589a46 2654 gpa_t gpa;
2bacc55c 2655 struct page *page;
c0b49b0d 2656 char *kaddr;
2bacc55c
MT		 2657 u64 val;
2658
10589a46
MT		 2659 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2660
2bacc55c
MT		 2661 if (gpa == UNMAPPED_GVA ||
2662 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2663 goto emul_write;
2664
2665 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2666 goto emul_write;
2667
2668 val = *(u64 *)new;
72dc67a6 2669
2bacc55c 2670 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2671
c0b49b0d
AM		 2672 kaddr = kmap_atomic(page, KM_USER0);
2673 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2674 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2675 kvm_release_page_dirty(page);
2676 }
3200f405 2677emul_write:
2bacc55c
MT		 2678#endif
2679
bbd9b64e
CO		 2680 return emulator_write_emulated(addr, new, bytes, vcpu);
2681}
2682
2683static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2684{
2685 return kvm_x86_ops->get_segment_base(vcpu, seg);
2686}
2687
2688int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2689{
a7052897 2690 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2691 return X86EMUL_CONTINUE;
2692}
2693
2694int emulate_clts(struct kvm_vcpu *vcpu)
2695{
ad312c7c 2696 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2697 return X86EMUL_CONTINUE;
2698}
2699
2700int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2701{
2702 struct kvm_vcpu *vcpu = ctxt->vcpu;
2703
2704 switch (dr) {
2705 case 0 ... 3:
2706 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2707 return X86EMUL_CONTINUE;
2708 default:
b8688d51 2709 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2710 return X86EMUL_UNHANDLEABLE;
2711 }
2712}
2713
2714int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2715{
2716 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2717 int exception;
2718
2719 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2720 if (exception) {
2721 /* FIXME: better handling */
2722 return X86EMUL_UNHANDLEABLE;
2723 }
2724 return X86EMUL_CONTINUE;
2725}
2726
2727void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2728{
bbd9b64e 2729 u8 opcodes[4];
5fdbf976 2730 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2731 unsigned long rip_linear;
2732
f76c710d 2733 if (!printk_ratelimit())
bbd9b64e
CO		 2734 return;
2735
25be4608
GC		 2736 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2737
77c2002e 2738 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2739
2740 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2741 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2742}
2743EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2744
14af3f3c 2745static struct x86_emulate_ops emulate_ops = {
77c2002e 2746 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2747 .read_emulated = emulator_read_emulated,
2748 .write_emulated = emulator_write_emulated,
2749 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2750};
2751
5fdbf976
MT		 2752static void cache_all_regs(struct kvm_vcpu *vcpu)
2753{
2754 kvm_register_read(vcpu, VCPU_REGS_RAX);
2755 kvm_register_read(vcpu, VCPU_REGS_RSP);
2756 kvm_register_read(vcpu, VCPU_REGS_RIP);
2757 vcpu->arch.regs_dirty = ~0;
2758}
2759
bbd9b64e
CO		 2760int emulate_instruction(struct kvm_vcpu *vcpu,
2761 struct kvm_run *run,
2762 unsigned long cr2,
2763 u16 error_code,
571008da 2764 int emulation_type)
bbd9b64e 2765{
310b5d30 2766 int r, shadow_mask;
571008da 2767 struct decode_cache *c;
bbd9b64e 2768
26eef70c 2769 kvm_clear_exception_queue(vcpu);
ad312c7c 2770 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 2771 /*
56e82318 2772 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 2773 * instead of direct ->regs accesses, can save hundred cycles
2774 * on Intel for instructions that don't read/change RSP, for
2775 * for example.
2776 */
2777 cache_all_regs(vcpu);
bbd9b64e
CO		 2778
2779 vcpu->mmio_is_write = 0;
ad312c7c 2780 vcpu->arch.pio.string = 0;
bbd9b64e 2781
571008da 2782 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2783 int cs_db, cs_l;
2784 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2785
ad312c7c
ZX		 2786 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2787 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2788 vcpu->arch.emulate_ctxt.mode =
2789 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2790 ? X86EMUL_MODE_REAL : cs_l
2791 ? X86EMUL_MODE_PROT64 : cs_db
2792 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2793
ad312c7c 2794 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2795
0cb5762e
AP		 2796 /* Only allow emulation of specific instructions on #UD
2797 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2798 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2799 if (emulation_type & EMULTYPE_TRAP_UD) {
2800 if (!c->twobyte)
2801 return EMULATE_FAIL;
2802 switch (c->b) {
2803 case 0x01: /* VMMCALL */
2804 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2805 return EMULATE_FAIL;
2806 break;
2807 case 0x34: /* sysenter */
2808 case 0x35: /* sysexit */
2809 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2810 return EMULATE_FAIL;
2811 break;
2812 case 0x05: /* syscall */
2813 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2814 return EMULATE_FAIL;
2815 break;
2816 default:
2817 return EMULATE_FAIL;
2818 }
2819
2820 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2821 return EMULATE_FAIL;
2822 }
571008da 2823
f2b5756b 2824 ++vcpu->stat.insn_emulation;
bbd9b64e 2825 if (r) {
f2b5756b 2826 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2827 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2828 return EMULATE_DONE;
2829 return EMULATE_FAIL;
2830 }
2831 }
2832
ba8afb6b
GN		 2833 if (emulation_type & EMULTYPE_SKIP) {
2834 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2835 return EMULATE_DONE;
2836 }
2837
ad312c7c 2838 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2839 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2840
2841 if (r == 0)
2842 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2843
ad312c7c 2844 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2845 return EMULATE_DO_MMIO;
2846
2847 if ((r || vcpu->mmio_is_write) && run) {
2848 run->exit_reason = KVM_EXIT_MMIO;
2849 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2850 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2851 run->mmio.len = vcpu->mmio_size;
2852 run->mmio.is_write = vcpu->mmio_is_write;
2853 }
2854
2855 if (r) {
2856 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2857 return EMULATE_DONE;
2858 if (!vcpu->mmio_needed) {
2859 kvm_report_emulation_failure(vcpu, "mmio");
2860 return EMULATE_FAIL;
2861 }
2862 return EMULATE_DO_MMIO;
2863 }
2864
ad312c7c 2865 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2866
2867 if (vcpu->mmio_is_write) {
2868 vcpu->mmio_needed = 0;
2869 return EMULATE_DO_MMIO;
2870 }
2871
2872 return EMULATE_DONE;
2873}
2874EXPORT_SYMBOL_GPL(emulate_instruction);
2875
de7d789a
CO		 2876static int pio_copy_data(struct kvm_vcpu *vcpu)
2877{
ad312c7c 2878 void *p = vcpu->arch.pio_data;
0f346074 2879 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2880 unsigned bytes;
0f346074 2881 int ret;
de7d789a 2882
ad312c7c
ZX		 2883 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2884 if (vcpu->arch.pio.in)
0f346074 2885 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2886 else
0f346074
IE		 2887 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2888 return ret;
de7d789a
CO		 2889}
2890
2891int complete_pio(struct kvm_vcpu *vcpu)
2892{
ad312c7c 2893 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2894 long delta;
2895 int r;
5fdbf976 2896 unsigned long val;
de7d789a
CO		 2897
2898 if (!io->string) {
5fdbf976
MT		 2899 if (io->in) {
2900 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2901 memcpy(&val, vcpu->arch.pio_data, io->size);
2902 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2903 }
de7d789a
CO		 2904 } else {
2905 if (io->in) {
2906 r = pio_copy_data(vcpu);
5fdbf976 2907 if (r)
de7d789a 2908 return r;
de7d789a
CO		 2909 }
2910
2911 delta = 1;
2912 if (io->rep) {
2913 delta *= io->cur_count;
2914 /*
2915 * The size of the register should really depend on
2916 * current address size.
2917 */
5fdbf976
MT		 2918 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2919 val -= delta;
2920 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2921 }
2922 if (io->down)
2923 delta = -delta;
2924 delta *= io->size;
5fdbf976
MT		 2925 if (io->in) {
2926 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2927 val += delta;
2928 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2929 } else {
2930 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2931 val += delta;
2932 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2933 }
de7d789a
CO		 2934 }
2935
de7d789a
CO		 2936 io->count -= io->cur_count;
2937 io->cur_count = 0;
2938
2939 return 0;
2940}
2941
bda9020e 2942static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2943{
2944 /* TODO: String I/O for in kernel device */
bda9020e 2945 int r;
de7d789a 2946
ad312c7c 2947 if (vcpu->arch.pio.in)
bda9020e
MT		 2948 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2949 vcpu->arch.pio.size, pd);
de7d789a 2950 else
bda9020e
MT		 2951 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2952 vcpu->arch.pio.size, pd);
2953 return r;
de7d789a
CO		 2954}
2955
bda9020e 2956static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2957{
ad312c7c
ZX		 2958 struct kvm_pio_request *io = &vcpu->arch.pio;
2959 void *pd = vcpu->arch.pio_data;
bda9020e 2960 int i, r = 0;
de7d789a 2961
de7d789a 2962 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2963 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2964 io->port, io->size, pd)) {
2965 r = -EOPNOTSUPP;
2966 break;
2967 }
de7d789a
CO		 2968 pd += io->size;
2969 }
bda9020e 2970 return r;
de7d789a
CO		 2971}
2972
2973int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2974 int size, unsigned port)
2975{
5fdbf976 2976 unsigned long val;
de7d789a
CO		 2977
2978 vcpu->run->exit_reason = KVM_EXIT_IO;
2979 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2980 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2981 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2982 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2983 vcpu->run->io.port = vcpu->arch.pio.port = port;
2984 vcpu->arch.pio.in = in;
2985 vcpu->arch.pio.string = 0;
2986 vcpu->arch.pio.down = 0;
ad312c7c 2987 vcpu->arch.pio.rep = 0;
de7d789a 2988
229456fc
MT		 2989 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2990 size, 1);
2714d1d3 2991
5fdbf976
MT		 2992 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2993 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2994
bda9020e 2995 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2996 complete_pio(vcpu);
2997 return 1;
2998 }
2999 return 0;
3000}
3001EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3002
3003int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
3004 int size, unsigned long count, int down,
3005 gva_t address, int rep, unsigned port)
3006{
3007 unsigned now, in_page;
0f346074 3008 int ret = 0;
de7d789a
CO		 3009
3010 vcpu->run->exit_reason = KVM_EXIT_IO;
3011 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3012 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3013 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3014 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3015 vcpu->run->io.port = vcpu->arch.pio.port = port;
3016 vcpu->arch.pio.in = in;
3017 vcpu->arch.pio.string = 1;
3018 vcpu->arch.pio.down = down;
ad312c7c 3019 vcpu->arch.pio.rep = rep;
de7d789a 3020
229456fc
MT		 3021 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3022 size, count);
2714d1d3 3023
de7d789a
CO		 3024 if (!count) {
3025 kvm_x86_ops->skip_emulated_instruction(vcpu);
3026 return 1;
3027 }
3028
3029 if (!down)
3030 in_page = PAGE_SIZE - offset_in_page(address);
3031 else
3032 in_page = offset_in_page(address) + size;
3033 now = min(count, (unsigned long)in_page / size);
0f346074 3034 if (!now)
de7d789a 3035 now = 1;
de7d789a
CO		 3036 if (down) {
3037 /*
3038 * String I/O in reverse. Yuck. Kill the guest, fix later.
3039 */
3040 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3041 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3042 return 1;
3043 }
3044 vcpu->run->io.count = now;
ad312c7c 3045 vcpu->arch.pio.cur_count = now;
de7d789a 3046
ad312c7c 3047 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3048 kvm_x86_ops->skip_emulated_instruction(vcpu);
3049
0f346074 3050 vcpu->arch.pio.guest_gva = address;
de7d789a 3051
ad312c7c 3052 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3053 /* string PIO write */
3054 ret = pio_copy_data(vcpu);
0f346074
IE		 3055 if (ret == X86EMUL_PROPAGATE_FAULT) {
3056 kvm_inject_gp(vcpu, 0);
3057 return 1;
3058 }
bda9020e 3059 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3060 complete_pio(vcpu);
ad312c7c 3061 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3062 ret = 1;
3063 }
bda9020e
MT		 3064 }
3065 /* no string PIO read support yet */
de7d789a
CO		 3066
3067 return ret;
3068}
3069EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3070
c8076604
GH		 3071static void bounce_off(void *info)
3072{
3073 /* nothing */
3074}
3075
3076static unsigned int ref_freq;
3077static unsigned long tsc_khz_ref;
3078
3079static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3080 void *data)
3081{
3082 struct cpufreq_freqs *freq = data;
3083 struct kvm *kvm;
3084 struct kvm_vcpu *vcpu;
3085 int i, send_ipi = 0;
3086
3087 if (!ref_freq)
3088 ref_freq = freq->old;
3089
3090 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3091 return 0;
3092 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3093 return 0;
3094 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3095
3096 spin_lock(&kvm_lock);
3097 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3098 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3099 if (vcpu->cpu != freq->cpu)
3100 continue;
3101 if (!kvm_request_guest_time_update(vcpu))
3102 continue;
3103 if (vcpu->cpu != smp_processor_id())
3104 send_ipi++;
3105 }
3106 }
3107 spin_unlock(&kvm_lock);
3108
3109 if (freq->old < freq->new && send_ipi) {
3110 /*
3111 * We upscale the frequency. Must make the guest
3112 * doesn't see old kvmclock values while running with
3113 * the new frequency, otherwise we risk the guest sees
3114 * time go backwards.
3115 *
3116 * In case we update the frequency for another cpu
3117 * (which might be in guest context) send an interrupt
3118 * to kick the cpu out of guest context. Next time
3119 * guest context is entered kvmclock will be updated,
3120 * so the guest will not see stale values.
3121 */
3122 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3123 }
3124 return 0;
3125}
3126
3127static struct notifier_block kvmclock_cpufreq_notifier_block = {
3128 .notifier_call = kvmclock_cpufreq_notifier
3129};
3130
f8c16bba 3131int kvm_arch_init(void *opaque)
043405e1 3132{
c8076604 3133 int r, cpu;
f8c16bba
ZX		 3134 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3135
f8c16bba
ZX		 3136 if (kvm_x86_ops) {
3137 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3138 r = -EEXIST;
3139 goto out;
f8c16bba
ZX		 3140 }
3141
3142 if (!ops->cpu_has_kvm_support()) {
3143 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3144 r = -EOPNOTSUPP;
3145 goto out;
f8c16bba
ZX		 3146 }
3147 if (ops->disabled_by_bios()) {
3148 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3149 r = -EOPNOTSUPP;
3150 goto out;
f8c16bba
ZX		 3151 }
3152
97db56ce
AK		 3153 r = kvm_mmu_module_init();
3154 if (r)
3155 goto out;
3156
3157 kvm_init_msr_list();
3158
f8c16bba 3159 kvm_x86_ops = ops;
56c6d28a 3160 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3161 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3162 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3163 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3164
3165 for_each_possible_cpu(cpu)
3166 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3167 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3168 tsc_khz_ref = tsc_khz;
3169 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3170 CPUFREQ_TRANSITION_NOTIFIER);
3171 }
3172
f8c16bba 3173 return 0;
56c6d28a
ZX		 3174
3175out:
56c6d28a 3176 return r;
043405e1 3177}
8776e519 3178
f8c16bba
ZX		 3179void kvm_arch_exit(void)
3180{
888d256e
JK		 3181 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3182 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3183 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3184 kvm_x86_ops = NULL;
56c6d28a
ZX		 3185 kvm_mmu_module_exit();
3186}
f8c16bba 3187
8776e519
HB		 3188int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3189{
3190 ++vcpu->stat.halt_exits;
3191 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3192 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3193 return 1;
3194 } else {
3195 vcpu->run->exit_reason = KVM_EXIT_HLT;
3196 return 0;
3197 }
3198}
3199EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3200
2f333bcb
MT		 3201static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3202 unsigned long a1)
3203{
3204 if (is_long_mode(vcpu))
3205 return a0;
3206 else
3207 return a0 | ((gpa_t)a1 << 32);
3208}
3209
8776e519
HB		 3210int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3211{
3212 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3213 int r = 1;
8776e519 3214
5fdbf976
MT		 3215 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3216 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3217 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3218 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3219 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3220
229456fc 3221 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3222
8776e519
HB		 3223 if (!is_long_mode(vcpu)) {
3224 nr &= 0xFFFFFFFF;
3225 a0 &= 0xFFFFFFFF;
3226 a1 &= 0xFFFFFFFF;
3227 a2 &= 0xFFFFFFFF;
3228 a3 &= 0xFFFFFFFF;
3229 }
3230
07708c4a
JK		 3231 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3232 ret = -KVM_EPERM;
3233 goto out;
3234 }
3235
8776e519 3236 switch (nr) {
b93463aa
AK		 3237 case KVM_HC_VAPIC_POLL_IRQ:
3238 ret = 0;
3239 break;
2f333bcb
MT		 3240 case KVM_HC_MMU_OP:
3241 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3242 break;
8776e519
HB		 3243 default:
3244 ret = -KVM_ENOSYS;
3245 break;
3246 }
07708c4a 3247out:
5fdbf976 3248 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3249 ++vcpu->stat.hypercalls;
2f333bcb 3250 return r;
8776e519
HB		 3251}
3252EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3253
3254int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3255{
3256 char instruction[3];
3257 int ret = 0;
5fdbf976 3258 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3259
8776e519
HB		 3260
3261 /*
3262 * Blow out the MMU to ensure that no other VCPU has an active mapping
3263 * to ensure that the updated hypercall appears atomically across all
3264 * VCPUs.
3265 */
3266 kvm_mmu_zap_all(vcpu->kvm);
3267
8776e519 3268 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3269 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3270 != X86EMUL_CONTINUE)
3271 ret = -EFAULT;
3272
8776e519
HB		 3273 return ret;
3274}
3275
3276static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3277{
3278 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3279}
3280
3281void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3282{
3283 struct descriptor_table dt = { limit, base };
3284
3285 kvm_x86_ops->set_gdt(vcpu, &dt);
3286}
3287
3288void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3289{
3290 struct descriptor_table dt = { limit, base };
3291
3292 kvm_x86_ops->set_idt(vcpu, &dt);
3293}
3294
3295void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3296 unsigned long *rflags)
3297{
2d3ad1f4 3298 kvm_lmsw(vcpu, msw);
8776e519
HB		 3299 *rflags = kvm_x86_ops->get_rflags(vcpu);
3300}
3301
3302unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3303{
54e445ca
JR		 3304 unsigned long value;
3305
8776e519
HB		 3306 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3307 switch (cr) {
3308 case 0:
54e445ca
JR		 3309 value = vcpu->arch.cr0;
3310 break;
8776e519 3311 case 2:
54e445ca
JR		 3312 value = vcpu->arch.cr2;
3313 break;
8776e519 3314 case 3:
54e445ca
JR		 3315 value = vcpu->arch.cr3;
3316 break;
8776e519 3317 case 4:
54e445ca
JR		 3318 value = vcpu->arch.cr4;
3319 break;
152ff9be 3320 case 8:
54e445ca
JR		 3321 value = kvm_get_cr8(vcpu);
3322 break;
8776e519 3323 default:
b8688d51 3324 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3325 return 0;
3326 }
54e445ca
JR		 3327
3328 return value;
8776e519
HB		 3329}
3330
3331void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3332 unsigned long *rflags)
3333{
3334 switch (cr) {
3335 case 0:
2d3ad1f4 3336 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3337 *rflags = kvm_x86_ops->get_rflags(vcpu);
3338 break;
3339 case 2:
ad312c7c 3340 vcpu->arch.cr2 = val;
8776e519
HB		 3341 break;
3342 case 3:
2d3ad1f4 3343 kvm_set_cr3(vcpu, val);
8776e519
HB		 3344 break;
3345 case 4:
2d3ad1f4 3346 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3347 break;
152ff9be 3348 case 8:
2d3ad1f4 3349 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3350 break;
8776e519 3351 default:
b8688d51 3352 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3353 }
3354}
3355
07716717
DK		 3356static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3357{
ad312c7c
ZX		 3358 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3359 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3360
3361 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3362 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3363 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3364 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3365 if (ej->function == e->function) {
3366 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3367 return j;
3368 }
3369 }
3370 return 0; /* silence gcc, even though control never reaches here */
3371}
3372
3373/* find an entry with matching function, matching index (if needed), and that
3374 * should be read next (if it's stateful) */
3375static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3376 u32 function, u32 index)
3377{
3378 if (e->function != function)
3379 return 0;
3380 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3381 return 0;
3382 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3383 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3384 return 0;
3385 return 1;
3386}
3387
d8017474
AG		 3388struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3389 u32 function, u32 index)
8776e519
HB		 3390{
3391 int i;
d8017474 3392 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3393
ad312c7c 3394 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3395 struct kvm_cpuid_entry2 *e;
3396
ad312c7c 3397 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3398 if (is_matching_cpuid_entry(e, function, index)) {
3399 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3400 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3401 best = e;
3402 break;
3403 }
3404 /*
3405 * Both basic or both extended?
3406 */
3407 if (((e->function ^ function) & 0x80000000) == 0)
3408 if (!best || e->function > best->function)
3409 best = e;
3410 }
d8017474
AG		 3411 return best;
3412}
3413
82725b20
DE		 3414int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3415{
3416 struct kvm_cpuid_entry2 *best;
3417
3418 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3419 if (best)
3420 return best->eax & 0xff;
3421 return 36;
3422}
3423
d8017474
AG		 3424void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3425{
3426 u32 function, index;
3427 struct kvm_cpuid_entry2 *best;
3428
3429 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3430 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3431 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3432 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3433 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3434 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3435 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3436 if (best) {
5fdbf976
MT		 3437 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3438 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3439 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3440 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3441 }
8776e519 3442 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3443 trace_kvm_cpuid(function,
3444 kvm_register_read(vcpu, VCPU_REGS_RAX),
3445 kvm_register_read(vcpu, VCPU_REGS_RBX),
3446 kvm_register_read(vcpu, VCPU_REGS_RCX),
3447 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3448}
3449EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3450
b6c7a5dc
HB		 3451/*
3452 * Check if userspace requested an interrupt window, and that the
3453 * interrupt window is open.
3454 *
3455 * No need to exit to userspace if we already have an interrupt queued.
3456 */
3457static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3458 struct kvm_run *kvm_run)
3459{
8061823a 3460 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3461 kvm_run->request_interrupt_window &&
5df56646 3462 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3463}
3464
3465static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3466 struct kvm_run *kvm_run)
3467{
3468 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3469 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3470 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3471 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3472 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3473 else
b6c7a5dc 3474 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3475 kvm_arch_interrupt_allowed(vcpu) &&
3476 !kvm_cpu_has_interrupt(vcpu) &&
3477 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3478}
3479
b93463aa
AK		 3480static void vapic_enter(struct kvm_vcpu *vcpu)
3481{
3482 struct kvm_lapic *apic = vcpu->arch.apic;
3483 struct page *page;
3484
3485 if (!apic || !apic->vapic_addr)
3486 return;
3487
3488 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3489
3490 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3491}
3492
3493static void vapic_exit(struct kvm_vcpu *vcpu)
3494{
3495 struct kvm_lapic *apic = vcpu->arch.apic;
3496
3497 if (!apic || !apic->vapic_addr)
3498 return;
3499
f8b78fa3 3500 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3501 kvm_release_page_dirty(apic->vapic_page);
3502 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3503 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3504}
3505
95ba8273
GN		 3506static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3507{
3508 int max_irr, tpr;
3509
3510 if (!kvm_x86_ops->update_cr8_intercept)
3511 return;
3512
88c808fd
AK		 3513 if (!vcpu->arch.apic)
3514 return;
3515
8db3baa2
GN		 3516 if (!vcpu->arch.apic->vapic_addr)
3517 max_irr = kvm_lapic_find_highest_irr(vcpu);
3518 else
3519 max_irr = -1;
95ba8273
GN		 3520
3521 if (max_irr != -1)
3522 max_irr >>= 4;
3523
3524 tpr = kvm_lapic_get_cr8(vcpu);
3525
3526 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3527}
3528
b59bb7bd 3529static void inject_pending_event(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3530{
3531 /* try to reinject previous events if any */
b59bb7bd
GN		 3532 if (vcpu->arch.exception.pending) {
3533 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3534 vcpu->arch.exception.has_error_code,
3535 vcpu->arch.exception.error_code);
3536 return;
3537 }
3538
95ba8273
GN		 3539 if (vcpu->arch.nmi_injected) {
3540 kvm_x86_ops->set_nmi(vcpu);
3541 return;
3542 }
3543
3544 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3545 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3546 return;
3547 }
3548
3549 /* try to inject new event if pending */
3550 if (vcpu->arch.nmi_pending) {
3551 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3552 vcpu->arch.nmi_pending = false;
3553 vcpu->arch.nmi_injected = true;
3554 kvm_x86_ops->set_nmi(vcpu);
3555 }
3556 } else if (kvm_cpu_has_interrupt(vcpu)) {
3557 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3558 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3559 false);
3560 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3561 }
3562 }
3563}
3564
d7690175 3565static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3566{
3567 int r;
6a8b1d13
GN		 3568 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3569 kvm_run->request_interrupt_window;
b6c7a5dc 3570
2e53d63a
MT		 3571 if (vcpu->requests)
3572 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3573 kvm_mmu_unload(vcpu);
3574
b6c7a5dc
HB		 3575 r = kvm_mmu_reload(vcpu);
3576 if (unlikely(r))
3577 goto out;
3578
2f52d58c
AK		 3579 if (vcpu->requests) {
3580 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3581 __kvm_migrate_timers(vcpu);
c8076604
GH		 3582 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3583 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3584 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3585 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3586 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3587 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3588 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3589 &vcpu->requests)) {
3590 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3591 r = 0;
3592 goto out;
3593 }
71c4dfaf
JR		 3594 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3595 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3596 r = 0;
3597 goto out;
3598 }
2f52d58c 3599 }
b93463aa 3600
b6c7a5dc
HB		 3601 preempt_disable();
3602
3603 kvm_x86_ops->prepare_guest_switch(vcpu);
3604 kvm_load_guest_fpu(vcpu);
3605
3606 local_irq_disable();
3607
32f88400
MT		 3608 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3609 smp_mb__after_clear_bit();
3610
d7690175 3611 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3612 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3613 local_irq_enable();
3614 preempt_enable();
3615 r = 1;
3616 goto out;
3617 }
3618
b59bb7bd 3619 inject_pending_event(vcpu, kvm_run);
b6c7a5dc 3620
6a8b1d13
GN		 3621 /* enable NMI/IRQ window open exits if needed */
3622 if (vcpu->arch.nmi_pending)
3623 kvm_x86_ops->enable_nmi_window(vcpu);
3624 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3625 kvm_x86_ops->enable_irq_window(vcpu);
3626
95ba8273 3627 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3628 update_cr8_intercept(vcpu);
3629 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3630 }
b93463aa 3631
3200f405
MT		 3632 up_read(&vcpu->kvm->slots_lock);
3633
b6c7a5dc
HB		 3634 kvm_guest_enter();
3635
42dbaa5a 3636 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 3637 set_debugreg(0, 7);
3638 set_debugreg(vcpu->arch.eff_db[0], 0);
3639 set_debugreg(vcpu->arch.eff_db[1], 1);
3640 set_debugreg(vcpu->arch.eff_db[2], 2);
3641 set_debugreg(vcpu->arch.eff_db[3], 3);
3642 }
b6c7a5dc 3643
229456fc 3644 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3645 kvm_x86_ops->run(vcpu, kvm_run);
3646
24f1e32c
FW		 3647 /*
3648 * If the guest has used debug registers, at least dr7
3649 * will be disabled while returning to the host.
3650 * If we don't have active breakpoints in the host, we don't
3651 * care about the messed up debug address registers. But if
3652 * we have some of them active, restore the old state.
3653 */
3654 if (__get_cpu_var(dr7) & DR_GLOBAL_ENABLE_MASK)
3655 hw_breakpoint_restore();
42dbaa5a 3656
32f88400 3657 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3658 local_irq_enable();
3659
3660 ++vcpu->stat.exits;
3661
3662 /*
3663 * We must have an instruction between local_irq_enable() and
3664 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3665 * the interrupt shadow. The stat.exits increment will do nicely.
3666 * But we need to prevent reordering, hence this barrier():
3667 */
3668 barrier();
3669
3670 kvm_guest_exit();
3671
3672 preempt_enable();
3673
3200f405
MT		 3674 down_read(&vcpu->kvm->slots_lock);
3675
b6c7a5dc
HB		 3676 /*
3677 * Profile KVM exit RIPs:
3678 */
3679 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3680 unsigned long rip = kvm_rip_read(vcpu);
3681 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3682 }
3683
298101da 3684
b93463aa
AK		 3685 kvm_lapic_sync_from_vapic(vcpu);
3686
b6c7a5dc 3687 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3688out:
3689 return r;
3690}
b6c7a5dc 3691
09cec754 3692
d7690175
MT		 3693static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3694{
3695 int r;
3696
3697 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3698 pr_debug("vcpu %d received sipi with vector # %x\n",
3699 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3700 kvm_lapic_reset(vcpu);
5f179287 3701 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3702 if (r)
3703 return r;
3704 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3705 }
3706
d7690175
MT		 3707 down_read(&vcpu->kvm->slots_lock);
3708 vapic_enter(vcpu);
3709
3710 r = 1;
3711 while (r > 0) {
af2152f5 3712 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3713 r = vcpu_enter_guest(vcpu, kvm_run);
3714 else {
3715 up_read(&vcpu->kvm->slots_lock);
3716 kvm_vcpu_block(vcpu);
3717 down_read(&vcpu->kvm->slots_lock);
3718 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3719 {
3720 switch(vcpu->arch.mp_state) {
3721 case KVM_MP_STATE_HALTED:
d7690175 3722 vcpu->arch.mp_state =
09cec754
GN		 3723 KVM_MP_STATE_RUNNABLE;
3724 case KVM_MP_STATE_RUNNABLE:
3725 break;
3726 case KVM_MP_STATE_SIPI_RECEIVED:
3727 default:
3728 r = -EINTR;
3729 break;
3730 }
3731 }
d7690175
MT		 3732 }
3733
09cec754
GN		 3734 if (r <= 0)
3735 break;
3736
3737 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3738 if (kvm_cpu_has_pending_timer(vcpu))
3739 kvm_inject_pending_timer_irqs(vcpu);
3740
3741 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3742 r = -EINTR;
3743 kvm_run->exit_reason = KVM_EXIT_INTR;
3744 ++vcpu->stat.request_irq_exits;
3745 }
3746 if (signal_pending(current)) {
3747 r = -EINTR;
3748 kvm_run->exit_reason = KVM_EXIT_INTR;
3749 ++vcpu->stat.signal_exits;
3750 }
3751 if (need_resched()) {
3752 up_read(&vcpu->kvm->slots_lock);
3753 kvm_resched(vcpu);
3754 down_read(&vcpu->kvm->slots_lock);
d7690175 3755 }
b6c7a5dc
HB		 3756 }
3757
d7690175 3758 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3759 post_kvm_run_save(vcpu, kvm_run);
3760
b93463aa
AK		 3761 vapic_exit(vcpu);
3762
b6c7a5dc
HB		 3763 return r;
3764}
3765
3766int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3767{
3768 int r;
3769 sigset_t sigsaved;
3770
3771 vcpu_load(vcpu);
3772
ac9f6dc0
AK		 3773 if (vcpu->sigset_active)
3774 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3775
a4535290 3776 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3777 kvm_vcpu_block(vcpu);
d7690175 3778 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3779 r = -EAGAIN;
3780 goto out;
b6c7a5dc
HB		 3781 }
3782
b6c7a5dc
HB		 3783 /* re-sync apic's tpr */
3784 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3785 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3786
ad312c7c 3787 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3788 r = complete_pio(vcpu);
3789 if (r)
3790 goto out;
3791 }
3792#if CONFIG_HAS_IOMEM
3793 if (vcpu->mmio_needed) {
3794 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3795 vcpu->mmio_read_completed = 1;
3796 vcpu->mmio_needed = 0;
3200f405
MT		 3797
3798 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3799 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3800 vcpu->arch.mmio_fault_cr2, 0,
3801 EMULTYPE_NO_DECODE);
3200f405 3802 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3803 if (r == EMULATE_DO_MMIO) {
3804 /*
3805 * Read-modify-write. Back to userspace.
3806 */
3807 r = 0;
3808 goto out;
3809 }
3810 }
3811#endif
5fdbf976
MT		 3812 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3813 kvm_register_write(vcpu, VCPU_REGS_RAX,
3814 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3815
3816 r = __vcpu_run(vcpu, kvm_run);
3817
3818out:
3819 if (vcpu->sigset_active)
3820 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3821
3822 vcpu_put(vcpu);
3823 return r;
3824}
3825
3826int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3827{
3828 vcpu_load(vcpu);
3829
5fdbf976
MT		 3830 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3831 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3832 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3833 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3834 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3835 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3836 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3837 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3838#ifdef CONFIG_X86_64
5fdbf976
MT		 3839 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3840 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3841 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3842 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3843 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3844 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3845 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3846 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3847#endif
3848
5fdbf976 3849 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3850 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3851
3852 /*
3853 * Don't leak debug flags in case they were set for guest debugging
3854 */
d0bfb940 3855 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3856 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3857
3858 vcpu_put(vcpu);
3859
3860 return 0;
3861}
3862
3863int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3864{
3865 vcpu_load(vcpu);
3866
5fdbf976
MT		 3867 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3868 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3869 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3870 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3871 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3872 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3873 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3874 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3875#ifdef CONFIG_X86_64
5fdbf976
MT		 3876 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3877 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3878 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3879 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3880 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3881 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3882 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3883 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3884
b6c7a5dc
HB		 3885#endif
3886
5fdbf976 3887 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3888 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3889
b6c7a5dc 3890
b4f14abd
JK		 3891 vcpu->arch.exception.pending = false;
3892
b6c7a5dc
HB		 3893 vcpu_put(vcpu);
3894
3895 return 0;
3896}
3897
3e6e0aab
GT		 3898void kvm_get_segment(struct kvm_vcpu *vcpu,
3899 struct kvm_segment *var, int seg)
b6c7a5dc 3900{
14af3f3c 3901 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3902}
3903
3904void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3905{
3906 struct kvm_segment cs;
3907
3e6e0aab 3908 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3909 *db = cs.db;
3910 *l = cs.l;
3911}
3912EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3913
3914int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3915 struct kvm_sregs *sregs)
3916{
3917 struct descriptor_table dt;
b6c7a5dc
HB		 3918
3919 vcpu_load(vcpu);
3920
3e6e0aab
GT		 3921 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3922 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3923 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3924 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3925 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3926 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3927
3e6e0aab
GT		 3928 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3929 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3930
3931 kvm_x86_ops->get_idt(vcpu, &dt);
3932 sregs->idt.limit = dt.limit;
3933 sregs->idt.base = dt.base;
3934 kvm_x86_ops->get_gdt(vcpu, &dt);
3935 sregs->gdt.limit = dt.limit;
3936 sregs->gdt.base = dt.base;
3937
3938 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3939 sregs->cr0 = vcpu->arch.cr0;
3940 sregs->cr2 = vcpu->arch.cr2;
3941 sregs->cr3 = vcpu->arch.cr3;
3942 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3943 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3944 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3945 sregs->apic_base = kvm_get_apic_base(vcpu);
3946
923c61bb 3947 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3948
36752c9b 3949 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3950 set_bit(vcpu->arch.interrupt.nr,
3951 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3952
b6c7a5dc
HB		 3953 vcpu_put(vcpu);
3954
3955 return 0;
3956}
3957
62d9f0db
MT		 3958int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3959 struct kvm_mp_state *mp_state)
3960{
3961 vcpu_load(vcpu);
3962 mp_state->mp_state = vcpu->arch.mp_state;
3963 vcpu_put(vcpu);
3964 return 0;
3965}
3966
3967int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3968 struct kvm_mp_state *mp_state)
3969{
3970 vcpu_load(vcpu);
3971 vcpu->arch.mp_state = mp_state->mp_state;
3972 vcpu_put(vcpu);
3973 return 0;
3974}
3975
3e6e0aab 3976static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3977 struct kvm_segment *var, int seg)
3978{
14af3f3c 3979 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3980}
3981
37817f29
IE		 3982static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3983 struct kvm_segment *kvm_desct)
3984{
46a359e7
AM		 3985 kvm_desct->base = get_desc_base(seg_desc);
3986 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 3987 if (seg_desc->g) {
3988 kvm_desct->limit <<= 12;
3989 kvm_desct->limit |= 0xfff;
3990 }
37817f29
IE		 3991 kvm_desct->selector = selector;
3992 kvm_desct->type = seg_desc->type;
3993 kvm_desct->present = seg_desc->p;
3994 kvm_desct->dpl = seg_desc->dpl;
3995 kvm_desct->db = seg_desc->d;
3996 kvm_desct->s = seg_desc->s;
3997 kvm_desct->l = seg_desc->l;
3998 kvm_desct->g = seg_desc->g;
3999 kvm_desct->avl = seg_desc->avl;
4000 if (!selector)
4001 kvm_desct->unusable = 1;
4002 else
4003 kvm_desct->unusable = 0;
4004 kvm_desct->padding = 0;
4005}
4006
b8222ad2
AS		 4007static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4008 u16 selector,
4009 struct descriptor_table *dtable)
37817f29
IE		 4010{
4011 if (selector & 1 << 2) {
4012 struct kvm_segment kvm_seg;
4013
3e6e0aab 4014 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4015
4016 if (kvm_seg.unusable)
4017 dtable->limit = 0;
4018 else
4019 dtable->limit = kvm_seg.limit;
4020 dtable->base = kvm_seg.base;
4021 }
4022 else
4023 kvm_x86_ops->get_gdt(vcpu, dtable);
4024}
4025
4026/* allowed just for 8 bytes segments */
4027static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4028 struct desc_struct *seg_desc)
4029{
4030 struct descriptor_table dtable;
4031 u16 index = selector >> 3;
4032
b8222ad2 4033 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4034
4035 if (dtable.limit < index * 8 + 7) {
4036 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4037 return 1;
4038 }
d9048d32 4039 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4040}
4041
4042/* allowed just for 8 bytes segments */
4043static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4044 struct desc_struct *seg_desc)
4045{
4046 struct descriptor_table dtable;
4047 u16 index = selector >> 3;
4048
b8222ad2 4049 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4050
4051 if (dtable.limit < index * 8 + 7)
4052 return 1;
d9048d32 4053 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4054}
4055
4056static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
4057 struct desc_struct *seg_desc)
4058{
46a359e7 4059 u32 base_addr = get_desc_base(seg_desc);
37817f29 4060
98899aa0 4061 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4062}
4063
37817f29
IE		 4064static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4065{
4066 struct kvm_segment kvm_seg;
4067
3e6e0aab 4068 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4069 return kvm_seg.selector;
4070}
4071
4072static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4073 u16 selector,
4074 struct kvm_segment *kvm_seg)
4075{
4076 struct desc_struct seg_desc;
4077
4078 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4079 return 1;
4080 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4081 return 0;
4082}
4083
2259e3a7 4084static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4085{
4086 struct kvm_segment segvar = {
4087 .base = selector << 4,
4088 .limit = 0xffff,
4089 .selector = selector,
4090 .type = 3,
4091 .present = 1,
4092 .dpl = 3,
4093 .db = 0,
4094 .s = 1,
4095 .l = 0,
4096 .g = 0,
4097 .avl = 0,
4098 .unusable = 0,
4099 };
4100 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4101 return 0;
4102}
4103
c0c7c04b
AL		 4104static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4105{
4106 return (seg != VCPU_SREG_LDTR) &&
4107 (seg != VCPU_SREG_TR) &&
4108 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_VM);
4109}
4110
3e6e0aab
GT		 4111int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4112 int type_bits, int seg)
37817f29
IE		 4113{
4114 struct kvm_segment kvm_seg;
4115
c0c7c04b 4116 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
f4bbd9aa 4117 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4118 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4119 return 1;
4120 kvm_seg.type |= type_bits;
4121
4122 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4123 seg != VCPU_SREG_LDTR)
4124 if (!kvm_seg.s)
4125 kvm_seg.unusable = 1;
4126
3e6e0aab 4127 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4128 return 0;
4129}
4130
4131static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4132 struct tss_segment_32 *tss)
4133{
4134 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4135 tss->eip = kvm_rip_read(vcpu);
37817f29 4136 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4137 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4138 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4139 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4140 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4141 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4142 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4143 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4144 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4145 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4146 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4147 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4148 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4149 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4150 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4151 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4152}
4153
4154static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4155 struct tss_segment_32 *tss)
4156{
4157 kvm_set_cr3(vcpu, tss->cr3);
4158
5fdbf976 4159 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4160 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4161
5fdbf976
MT		 4162 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4163 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4164 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4165 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4166 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4167 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4168 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4169 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4170
3e6e0aab 4171 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4172 return 1;
4173
3e6e0aab 4174 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4175 return 1;
4176
3e6e0aab 4177 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4178 return 1;
4179
3e6e0aab 4180 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4181 return 1;
4182
3e6e0aab 4183 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4184 return 1;
4185
3e6e0aab 4186 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4187 return 1;
4188
3e6e0aab 4189 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4190 return 1;
4191 return 0;
4192}
4193
4194static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4195 struct tss_segment_16 *tss)
4196{
5fdbf976 4197 tss->ip = kvm_rip_read(vcpu);
37817f29 4198 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4199 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4200 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4201 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4202 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4203 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4204 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4205 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4206 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4207
4208 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4209 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4210 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4211 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4212 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4213 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4214}
4215
4216static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4217 struct tss_segment_16 *tss)
4218{
5fdbf976 4219 kvm_rip_write(vcpu, tss->ip);
37817f29 4220 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4221 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4222 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4223 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4224 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4225 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4226 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4227 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4228 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4229
3e6e0aab 4230 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4231 return 1;
4232
3e6e0aab 4233 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4234 return 1;
4235
3e6e0aab 4236 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4237 return 1;
4238
3e6e0aab 4239 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4240 return 1;
4241
3e6e0aab 4242 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4243 return 1;
4244 return 0;
4245}
4246
8b2cf73c 4247static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4248 u16 old_tss_sel, u32 old_tss_base,
4249 struct desc_struct *nseg_desc)
37817f29
IE		 4250{
4251 struct tss_segment_16 tss_segment_16;
4252 int ret = 0;
4253
34198bf8
MT		 4254 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4255 sizeof tss_segment_16))
37817f29
IE		 4256 goto out;
4257
4258 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4259
34198bf8
MT		 4260 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4261 sizeof tss_segment_16))
37817f29 4262 goto out;
34198bf8
MT		 4263
4264 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4265 &tss_segment_16, sizeof tss_segment_16))
4266 goto out;
4267
b237ac37
GN		 4268 if (old_tss_sel != 0xffff) {
4269 tss_segment_16.prev_task_link = old_tss_sel;
4270
4271 if (kvm_write_guest(vcpu->kvm,
4272 get_tss_base_addr(vcpu, nseg_desc),
4273 &tss_segment_16.prev_task_link,
4274 sizeof tss_segment_16.prev_task_link))
4275 goto out;
4276 }
4277
37817f29
IE		 4278 if (load_state_from_tss16(vcpu, &tss_segment_16))
4279 goto out;
4280
4281 ret = 1;
4282out:
4283 return ret;
4284}
4285
8b2cf73c 4286static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4287 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4288 struct desc_struct *nseg_desc)
4289{
4290 struct tss_segment_32 tss_segment_32;
4291 int ret = 0;
4292
34198bf8
MT		 4293 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4294 sizeof tss_segment_32))
37817f29
IE		 4295 goto out;
4296
4297 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4298
34198bf8
MT		 4299 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4300 sizeof tss_segment_32))
4301 goto out;
4302
4303 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4304 &tss_segment_32, sizeof tss_segment_32))
37817f29 4305 goto out;
34198bf8 4306
b237ac37
GN		 4307 if (old_tss_sel != 0xffff) {
4308 tss_segment_32.prev_task_link = old_tss_sel;
4309
4310 if (kvm_write_guest(vcpu->kvm,
4311 get_tss_base_addr(vcpu, nseg_desc),
4312 &tss_segment_32.prev_task_link,
4313 sizeof tss_segment_32.prev_task_link))
4314 goto out;
4315 }
4316
37817f29
IE		 4317 if (load_state_from_tss32(vcpu, &tss_segment_32))
4318 goto out;
4319
4320 ret = 1;
4321out:
4322 return ret;
4323}
4324
4325int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4326{
4327 struct kvm_segment tr_seg;
4328 struct desc_struct cseg_desc;
4329 struct desc_struct nseg_desc;
4330 int ret = 0;
34198bf8
MT		 4331 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4332 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4333
34198bf8 4334 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4335
34198bf8
MT		 4336 /* FIXME: Handle errors. Failure to read either TSS or their
4337 * descriptors should generate a pagefault.
4338 */
37817f29
IE		 4339 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4340 goto out;
4341
34198bf8 4342 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4343 goto out;
4344
37817f29
IE		 4345 if (reason != TASK_SWITCH_IRET) {
4346 int cpl;
4347
4348 cpl = kvm_x86_ops->get_cpl(vcpu);
4349 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4350 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4351 return 1;
4352 }
4353 }
4354
46a359e7 4355 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4356 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4357 return 1;
4358 }
4359
4360 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4361 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4362 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4363 }
4364
4365 if (reason == TASK_SWITCH_IRET) {
4366 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4367 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4368 }
4369
64a7ec06
GN		 4370 /* set back link to prev task only if NT bit is set in eflags
4371 note that old_tss_sel is not used afetr this point */
4372 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4373 old_tss_sel = 0xffff;
37817f29 4374
b237ac37
GN		 4375 /* set back link to prev task only if NT bit is set in eflags
4376 note that old_tss_sel is not used afetr this point */
4377 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4378 old_tss_sel = 0xffff;
4379
37817f29 4380 if (nseg_desc.type & 8)
b237ac37
GN		 4381 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4382 old_tss_base, &nseg_desc);
37817f29 4383 else
b237ac37
GN		 4384 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4385 old_tss_base, &nseg_desc);
37817f29
IE		 4386
4387 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4388 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4389 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4390 }
4391
4392 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4393 nseg_desc.type |= (1 << 1);
37817f29
IE		 4394 save_guest_segment_descriptor(vcpu, tss_selector,
4395 &nseg_desc);
4396 }
4397
4398 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4399 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4400 tr_seg.type = 11;
3e6e0aab 4401 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4402out:
37817f29
IE		 4403 return ret;
4404}
4405EXPORT_SYMBOL_GPL(kvm_task_switch);
4406
b6c7a5dc
HB		 4407int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4408 struct kvm_sregs *sregs)
4409{
4410 int mmu_reset_needed = 0;
923c61bb 4411 int pending_vec, max_bits;
b6c7a5dc
HB		 4412 struct descriptor_table dt;
4413
4414 vcpu_load(vcpu);
4415
4416 dt.limit = sregs->idt.limit;
4417 dt.base = sregs->idt.base;
4418 kvm_x86_ops->set_idt(vcpu, &dt);
4419 dt.limit = sregs->gdt.limit;
4420 dt.base = sregs->gdt.base;
4421 kvm_x86_ops->set_gdt(vcpu, &dt);
4422
ad312c7c
ZX		 4423 vcpu->arch.cr2 = sregs->cr2;
4424 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4425 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4426
2d3ad1f4 4427 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4428
ad312c7c 4429 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4430 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4431 kvm_set_apic_base(vcpu, sregs->apic_base);
4432
4433 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4434
ad312c7c 4435 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4436 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4437 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4438
ad312c7c 4439 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4440 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4441 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4442 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4443
4444 if (mmu_reset_needed)
4445 kvm_mmu_reset_context(vcpu);
4446
923c61bb
GN		 4447 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4448 pending_vec = find_first_bit(
4449 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4450 if (pending_vec < max_bits) {
66fd3f7f 4451 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4452 pr_debug("Set back pending irq %d\n", pending_vec);
4453 if (irqchip_in_kernel(vcpu->kvm))
4454 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4455 }
4456
3e6e0aab
GT		 4457 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4458 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4459 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4460 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4461 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4462 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4463
3e6e0aab
GT		 4464 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4465 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4466
5f0269f5
ME		 4467 update_cr8_intercept(vcpu);
4468
9c3e4aab 4469 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4470 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4471 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4472 !(vcpu->arch.cr0 & X86_CR0_PE))
4473 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4474
b6c7a5dc
HB		 4475 vcpu_put(vcpu);
4476
4477 return 0;
4478}
4479
d0bfb940
JK		 4480int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4481 struct kvm_guest_debug *dbg)
b6c7a5dc 4482{
ae675ef0 4483 int i, r;
b6c7a5dc
HB		 4484
4485 vcpu_load(vcpu);
4486
ae675ef0
JK		 4487 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4488 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4489 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4490 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4491 vcpu->arch.switch_db_regs =
4492 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4493 } else {
4494 for (i = 0; i < KVM_NR_DB_REGS; i++)
4495 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4496 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4497 }
4498
b6c7a5dc
HB		 4499 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4500
d0bfb940
JK		 4501 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4502 kvm_queue_exception(vcpu, DB_VECTOR);
4503 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4504 kvm_queue_exception(vcpu, BP_VECTOR);
4505
b6c7a5dc
HB		 4506 vcpu_put(vcpu);
4507
4508 return r;
4509}
4510
d0752060
HB		 4511/*
4512 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4513 * we have asm/x86/processor.h
4514 */
4515struct fxsave {
4516 u16 cwd;
4517 u16 swd;
4518 u16 twd;
4519 u16 fop;
4520 u64 rip;
4521 u64 rdp;
4522 u32 mxcsr;
4523 u32 mxcsr_mask;
4524 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4525#ifdef CONFIG_X86_64
4526 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4527#else
4528 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4529#endif
4530};
4531
8b006791
ZX		 4532/*
4533 * Translate a guest virtual address to a guest physical address.
4534 */
4535int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4536 struct kvm_translation *tr)
4537{
4538 unsigned long vaddr = tr->linear_address;
4539 gpa_t gpa;
4540
4541 vcpu_load(vcpu);
72dc67a6 4542 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4543 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4544 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4545 tr->physical_address = gpa;
4546 tr->valid = gpa != UNMAPPED_GVA;
4547 tr->writeable = 1;
4548 tr->usermode = 0;
8b006791
ZX		 4549 vcpu_put(vcpu);
4550
4551 return 0;
4552}
4553
d0752060
HB		 4554int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4555{
ad312c7c 4556 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4557
4558 vcpu_load(vcpu);
4559
4560 memcpy(fpu->fpr, fxsave->st_space, 128);
4561 fpu->fcw = fxsave->cwd;
4562 fpu->fsw = fxsave->swd;
4563 fpu->ftwx = fxsave->twd;
4564 fpu->last_opcode = fxsave->fop;
4565 fpu->last_ip = fxsave->rip;
4566 fpu->last_dp = fxsave->rdp;
4567 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4568
4569 vcpu_put(vcpu);
4570
4571 return 0;
4572}
4573
4574int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4575{
ad312c7c 4576 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4577
4578 vcpu_load(vcpu);
4579
4580 memcpy(fxsave->st_space, fpu->fpr, 128);
4581 fxsave->cwd = fpu->fcw;
4582 fxsave->swd = fpu->fsw;
4583 fxsave->twd = fpu->ftwx;
4584 fxsave->fop = fpu->last_opcode;
4585 fxsave->rip = fpu->last_ip;
4586 fxsave->rdp = fpu->last_dp;
4587 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4588
4589 vcpu_put(vcpu);
4590
4591 return 0;
4592}
4593
4594void fx_init(struct kvm_vcpu *vcpu)
4595{
4596 unsigned after_mxcsr_mask;
4597
bc1a34f1
AA		 4598 /*
4599 * Touch the fpu the first time in non atomic context as if
4600 * this is the first fpu instruction the exception handler
4601 * will fire before the instruction returns and it'll have to
4602 * allocate ram with GFP_KERNEL.
4603 */
4604 if (!used_math())
d6e88aec 4605 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4606
d0752060
HB		 4607 /* Initialize guest FPU by resetting ours and saving into guest's */
4608 preempt_disable();
d6e88aec
AK		 4609 kvm_fx_save(&vcpu->arch.host_fx_image);
4610 kvm_fx_finit();
4611 kvm_fx_save(&vcpu->arch.guest_fx_image);
4612 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4613 preempt_enable();
4614
ad312c7c 4615 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4616 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4617 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4618 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4619 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4620}
4621EXPORT_SYMBOL_GPL(fx_init);
4622
4623void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4624{
4625 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4626 return;
4627
4628 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4629 kvm_fx_save(&vcpu->arch.host_fx_image);
4630 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4631}
4632EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4633
4634void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4635{
4636 if (!vcpu->guest_fpu_loaded)
4637 return;
4638
4639 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4640 kvm_fx_save(&vcpu->arch.guest_fx_image);
4641 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4642 ++vcpu->stat.fpu_reload;
d0752060
HB		 4643}
4644EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4645
4646void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4647{
7f1ea208
JR		 4648 if (vcpu->arch.time_page) {
4649 kvm_release_page_dirty(vcpu->arch.time_page);
4650 vcpu->arch.time_page = NULL;
4651 }
4652
e9b11c17
ZX		 4653 kvm_x86_ops->vcpu_free(vcpu);
4654}
4655
4656struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4657 unsigned int id)
4658{
26e5215f
AK		 4659 return kvm_x86_ops->vcpu_create(kvm, id);
4660}
e9b11c17 4661
26e5215f
AK		 4662int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4663{
4664 int r;
e9b11c17
ZX		 4665
4666 /* We do fxsave: this must be aligned. */
ad312c7c 4667 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4668
0bed3b56 4669 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4670 vcpu_load(vcpu);
4671 r = kvm_arch_vcpu_reset(vcpu);
4672 if (r == 0)
4673 r = kvm_mmu_setup(vcpu);
4674 vcpu_put(vcpu);
4675 if (r < 0)
4676 goto free_vcpu;
4677
26e5215f 4678 return 0;
e9b11c17
ZX		 4679free_vcpu:
4680 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4681 return r;
e9b11c17
ZX		 4682}
4683
d40ccc62 4684void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4685{
4686 vcpu_load(vcpu);
4687 kvm_mmu_unload(vcpu);
4688 vcpu_put(vcpu);
4689
4690 kvm_x86_ops->vcpu_free(vcpu);
4691}
4692
4693int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4694{
448fa4a9
JK		 4695 vcpu->arch.nmi_pending = false;
4696 vcpu->arch.nmi_injected = false;
4697
42dbaa5a
JK		 4698 vcpu->arch.switch_db_regs = 0;
4699 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4700 vcpu->arch.dr6 = DR6_FIXED_1;
4701 vcpu->arch.dr7 = DR7_FIXED_1;
4702
e9b11c17
ZX		 4703 return kvm_x86_ops->vcpu_reset(vcpu);
4704}
4705
4706void kvm_arch_hardware_enable(void *garbage)
4707{
4708 kvm_x86_ops->hardware_enable(garbage);
4709}
4710
4711void kvm_arch_hardware_disable(void *garbage)
4712{
4713 kvm_x86_ops->hardware_disable(garbage);
4714}
4715
4716int kvm_arch_hardware_setup(void)
4717{
4718 return kvm_x86_ops->hardware_setup();
4719}
4720
4721void kvm_arch_hardware_unsetup(void)
4722{
4723 kvm_x86_ops->hardware_unsetup();
4724}
4725
4726void kvm_arch_check_processor_compat(void *rtn)
4727{
4728 kvm_x86_ops->check_processor_compatibility(rtn);
4729}
4730
4731int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4732{
4733 struct page *page;
4734 struct kvm *kvm;
4735 int r;
4736
4737 BUG_ON(vcpu->kvm == NULL);
4738 kvm = vcpu->kvm;
4739
ad312c7c 4740 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4741 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4742 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4743 else
a4535290 4744 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4745
4746 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4747 if (!page) {
4748 r = -ENOMEM;
4749 goto fail;
4750 }
ad312c7c 4751 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4752
4753 r = kvm_mmu_create(vcpu);
4754 if (r < 0)
4755 goto fail_free_pio_data;
4756
4757 if (irqchip_in_kernel(kvm)) {
4758 r = kvm_create_lapic(vcpu);
4759 if (r < 0)
4760 goto fail_mmu_destroy;
4761 }
4762
890ca9ae
HY		 4763 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4764 GFP_KERNEL);
4765 if (!vcpu->arch.mce_banks) {
4766 r = -ENOMEM;
4767 goto fail_mmu_destroy;
4768 }
4769 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4770
e9b11c17
ZX		 4771 return 0;
4772
4773fail_mmu_destroy:
4774 kvm_mmu_destroy(vcpu);
4775fail_free_pio_data:
ad312c7c 4776 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4777fail:
4778 return r;
4779}
4780
4781void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4782{
4783 kvm_free_lapic(vcpu);
3200f405 4784 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4785 kvm_mmu_destroy(vcpu);
3200f405 4786 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4787 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4788}
d19a9cd2
ZX		 4789
4790struct kvm *kvm_arch_create_vm(void)
4791{
4792 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4793
4794 if (!kvm)
4795 return ERR_PTR(-ENOMEM);
4796
f05e70ac 4797 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4798 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4799
5550af4d
SY		 4800 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4801 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4802
53f658b3
MT		 4803 rdtscll(kvm->arch.vm_init_tsc);
4804
d19a9cd2
ZX		 4805 return kvm;
4806}
4807
4808static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4809{
4810 vcpu_load(vcpu);
4811 kvm_mmu_unload(vcpu);
4812 vcpu_put(vcpu);
4813}
4814
4815static void kvm_free_vcpus(struct kvm *kvm)
4816{
4817 unsigned int i;
988a2cae 4818 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4819
4820 /*
4821 * Unpin any mmu pages first.
4822 */
988a2cae
GN		 4823 kvm_for_each_vcpu(i, vcpu, kvm)
4824 kvm_unload_vcpu_mmu(vcpu);
4825 kvm_for_each_vcpu(i, vcpu, kvm)
4826 kvm_arch_vcpu_free(vcpu);
4827
4828 mutex_lock(&kvm->lock);
4829 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4830 kvm->vcpus[i] = NULL;
d19a9cd2 4831
988a2cae
GN		 4832 atomic_set(&kvm->online_vcpus, 0);
4833 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4834}
4835
ad8ba2cd
SY		 4836void kvm_arch_sync_events(struct kvm *kvm)
4837{
ba4cef31 4838 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4839}
4840
d19a9cd2
ZX		 4841void kvm_arch_destroy_vm(struct kvm *kvm)
4842{
6eb55818 4843 kvm_iommu_unmap_guest(kvm);
7837699f 4844 kvm_free_pit(kvm);
d7deeeb0
ZX		 4845 kfree(kvm->arch.vpic);
4846 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4847 kvm_free_vcpus(kvm);
4848 kvm_free_physmem(kvm);
3d45830c
AK		 4849 if (kvm->arch.apic_access_page)
4850 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4851 if (kvm->arch.ept_identity_pagetable)
4852 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4853 kfree(kvm);
4854}
0de10343
ZX		 4855
4856int kvm_arch_set_memory_region(struct kvm *kvm,
4857 struct kvm_userspace_memory_region *mem,
4858 struct kvm_memory_slot old,
4859 int user_alloc)
4860{
4861 int npages = mem->memory_size >> PAGE_SHIFT;
4862 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4863
4864 /*To keep backward compatibility with older userspace,
4865 *x86 needs to hanlde !user_alloc case.
4866 */
4867 if (!user_alloc) {
4868 if (npages && !old.rmap) {
604b38ac
AA		 4869 unsigned long userspace_addr;
4870
72dc67a6 4871 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4872 userspace_addr = do_mmap(NULL, 0,
4873 npages * PAGE_SIZE,
4874 PROT_READ | PROT_WRITE,
acee3c04 4875 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4876 0);
72dc67a6 4877 up_write(&current->mm->mmap_sem);
0de10343 4878
604b38ac
AA		 4879 if (IS_ERR((void *)userspace_addr))
4880 return PTR_ERR((void *)userspace_addr);
4881
4882 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4883 spin_lock(&kvm->mmu_lock);
4884 memslot->userspace_addr = userspace_addr;
4885 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4886 } else {
4887 if (!old.user_alloc && old.rmap) {
4888 int ret;
4889
72dc67a6 4890 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4891 ret = do_munmap(current->mm, old.userspace_addr,
4892 old.npages * PAGE_SIZE);
72dc67a6 4893 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4894 if (ret < 0)
4895 printk(KERN_WARNING
4896 "kvm_vm_ioctl_set_memory_region: "
4897 "failed to munmap memory\n");
4898 }
4899 }
4900 }
4901
7c8a83b7 4902 spin_lock(&kvm->mmu_lock);
f05e70ac 4903 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4904 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4905 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4906 }
4907
4908 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4909 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4910
4911 return 0;
4912}
1d737c8a 4913
34d4cb8f
MT		 4914void kvm_arch_flush_shadow(struct kvm *kvm)
4915{
4916 kvm_mmu_zap_all(kvm);
8986ecc0 4917 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4918}
4919
1d737c8a
ZX		 4920int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4921{
a4535290 4922 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 4923 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4924 || vcpu->arch.nmi_pending ||
4925 (kvm_arch_interrupt_allowed(vcpu) &&
4926 kvm_cpu_has_interrupt(vcpu));
1d737c8a 4927}
5736199a 4928
5736199a
ZX		 4929void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4930{
32f88400
MT		 4931 int me;
4932 int cpu = vcpu->cpu;
5736199a
ZX		 4933
4934 if (waitqueue_active(&vcpu->wq)) {
4935 wake_up_interruptible(&vcpu->wq);
4936 ++vcpu->stat.halt_wakeup;
4937 }
32f88400
MT		 4938
4939 me = get_cpu();
4940 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4941 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4942 smp_send_reschedule(cpu);
e9571ed5 4943 put_cpu();
5736199a 4944}
78646121
GN		 4945
4946int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4947{
4948 return kvm_x86_ops->interrupt_allowed(vcpu);
4949}
229456fc
MT		 4950
4951EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4952EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4953EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4954EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4955EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Linux 6.x block layer and io_uring tree(s)