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KVM: s390: Fix prefix register checking in arch/s390/kvm/sigp.c
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
aec51dc4
AK		 41#include <trace/events/kvm.h>
42#undef TRACE_INCLUDE_FILE
229456fc
MT		 43#define CREATE_TRACE_POINTS
44#include "trace.h"
043405e1
CO		 45
46#include <asm/uaccess.h>
d825ed0a 47#include <asm/msr.h>
a5f61300 48#include <asm/desc.h>
0bed3b56 49#include <asm/mtrr.h>
890ca9ae 50#include <asm/mce.h>
043405e1 51
313a3dc7 52#define MAX_IO_MSRS 256
a03490ed
CO		 53#define CR0_RESERVED_BITS \
54 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
55 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
56 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
57#define CR4_RESERVED_BITS \
58 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
59 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
60 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
61 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
62
63#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 64
65#define KVM_MAX_MCE_BANKS 32
66#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
67
50a37eb4
JR		 68/* EFER defaults:
69 * - enable syscall per default because its emulated by KVM
70 * - enable LME and LMA per default on 64 bit KVM
71 */
72#ifdef CONFIG_X86_64
73static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
74#else
75static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
76#endif
313a3dc7 77
ba1389b7
AK		 78#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
79#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 80
cb142eb7 81static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 82static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
83 struct kvm_cpuid_entry2 __user *entries);
84
97896d04 85struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 86EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 87
ed85c068
AP		 88int ignore_msrs = 0;
89module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
90
18863bdd
AK		 91#define KVM_NR_SHARED_MSRS 16
92
93struct kvm_shared_msrs_global {
94 int nr;
95 struct kvm_shared_msr {
96 u32 msr;
97 u64 value;
98 } msrs[KVM_NR_SHARED_MSRS];
99};
100
101struct kvm_shared_msrs {
102 struct user_return_notifier urn;
103 bool registered;
104 u64 current_value[KVM_NR_SHARED_MSRS];
105};
106
107static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
108static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
109
417bc304 110struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 111 { "pf_fixed", VCPU_STAT(pf_fixed) },
112 { "pf_guest", VCPU_STAT(pf_guest) },
113 { "tlb_flush", VCPU_STAT(tlb_flush) },
114 { "invlpg", VCPU_STAT(invlpg) },
115 { "exits", VCPU_STAT(exits) },
116 { "io_exits", VCPU_STAT(io_exits) },
117 { "mmio_exits", VCPU_STAT(mmio_exits) },
118 { "signal_exits", VCPU_STAT(signal_exits) },
119 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 120 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 121 { "halt_exits", VCPU_STAT(halt_exits) },
122 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 123 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 124 { "request_irq", VCPU_STAT(request_irq_exits) },
125 { "irq_exits", VCPU_STAT(irq_exits) },
126 { "host_state_reload", VCPU_STAT(host_state_reload) },
127 { "efer_reload", VCPU_STAT(efer_reload) },
128 { "fpu_reload", VCPU_STAT(fpu_reload) },
129 { "insn_emulation", VCPU_STAT(insn_emulation) },
130 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 131 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 132 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 133 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
134 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
135 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
136 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
137 { "mmu_flooded", VM_STAT(mmu_flooded) },
138 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 139 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 140 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 141 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 142 { "largepages", VM_STAT(lpages) },
417bc304
HB		 143 { NULL }
144};
145
18863bdd
AK		 146static void kvm_on_user_return(struct user_return_notifier *urn)
147{
148 unsigned slot;
149 struct kvm_shared_msr *global;
150 struct kvm_shared_msrs *locals
151 = container_of(urn, struct kvm_shared_msrs, urn);
152
153 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
154 global = &shared_msrs_global.msrs[slot];
155 if (global->value != locals->current_value[slot]) {
156 wrmsrl(global->msr, global->value);
157 locals->current_value[slot] = global->value;
158 }
159 }
160 locals->registered = false;
161 user_return_notifier_unregister(urn);
162}
163
164void kvm_define_shared_msr(unsigned slot, u32 msr)
165{
166 int cpu;
167 u64 value;
168
169 if (slot >= shared_msrs_global.nr)
170 shared_msrs_global.nr = slot + 1;
171 shared_msrs_global.msrs[slot].msr = msr;
172 rdmsrl_safe(msr, &value);
173 shared_msrs_global.msrs[slot].value = value;
174 for_each_online_cpu(cpu)
175 per_cpu(shared_msrs, cpu).current_value[slot] = value;
176}
177EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
178
179static void kvm_shared_msr_cpu_online(void)
180{
181 unsigned i;
182 struct kvm_shared_msrs *locals = &__get_cpu_var(shared_msrs);
183
184 for (i = 0; i < shared_msrs_global.nr; ++i)
185 locals->current_value[i] = shared_msrs_global.msrs[i].value;
186}
187
188void kvm_set_shared_msr(unsigned slot, u64 value)
189{
190 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
191
192 if (value == smsr->current_value[slot])
193 return;
194 smsr->current_value[slot] = value;
195 wrmsrl(shared_msrs_global.msrs[slot].msr, value);
196 if (!smsr->registered) {
197 smsr->urn.on_user_return = kvm_on_user_return;
198 user_return_notifier_register(&smsr->urn);
199 smsr->registered = true;
200 }
201}
202EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
203
3548bab5
AK		 204static void drop_user_return_notifiers(void *ignore)
205{
206 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
207
208 if (smsr->registered)
209 kvm_on_user_return(&smsr->urn);
210}
211
5fb76f9b
CO		 212unsigned long segment_base(u16 selector)
213{
214 struct descriptor_table gdt;
a5f61300 215 struct desc_struct *d;
5fb76f9b
CO		 216 unsigned long table_base;
217 unsigned long v;
218
219 if (selector == 0)
220 return 0;
221
b792c344 222 kvm_get_gdt(&gdt);
5fb76f9b
CO		 223 table_base = gdt.base;
224
225 if (selector & 4) { /* from ldt */
b792c344 226 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 227
5fb76f9b
CO		 228 table_base = segment_base(ldt_selector);
229 }
a5f61300 230 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 231 v = get_desc_base(d);
5fb76f9b 232#ifdef CONFIG_X86_64
a5f61300
AK		 233 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
234 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 235#endif
236 return v;
237}
238EXPORT_SYMBOL_GPL(segment_base);
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
298101da
AK		 259void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
260{
ad312c7c
ZX		 261 WARN_ON(vcpu->arch.exception.pending);
262 vcpu->arch.exception.pending = true;
263 vcpu->arch.exception.has_error_code = false;
264 vcpu->arch.exception.nr = nr;
298101da
AK		 265}
266EXPORT_SYMBOL_GPL(kvm_queue_exception);
267
c3c91fee
AK		 268void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
269 u32 error_code)
270{
271 ++vcpu->stat.pf_guest;
d8017474 272
71c4dfaf 273 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 274 switch(vcpu->arch.exception.nr) {
275 case DF_VECTOR:
71c4dfaf
JR		 276 /* triple fault -> shutdown */
277 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 278 return;
279 case PF_VECTOR:
280 vcpu->arch.exception.nr = DF_VECTOR;
281 vcpu->arch.exception.error_code = 0;
282 return;
283 default:
284 /* replace previous exception with a new one in a hope
285 that instruction re-execution will regenerate lost
286 exception */
287 vcpu->arch.exception.pending = false;
288 break;
71c4dfaf 289 }
c3c91fee 290 }
ad312c7c 291 vcpu->arch.cr2 = addr;
c3c91fee
AK		 292 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
293}
294
3419ffc8
SY		 295void kvm_inject_nmi(struct kvm_vcpu *vcpu)
296{
297 vcpu->arch.nmi_pending = 1;
298}
299EXPORT_SYMBOL_GPL(kvm_inject_nmi);
300
298101da
AK		 301void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
302{
ad312c7c
ZX		 303 WARN_ON(vcpu->arch.exception.pending);
304 vcpu->arch.exception.pending = true;
305 vcpu->arch.exception.has_error_code = true;
306 vcpu->arch.exception.nr = nr;
307 vcpu->arch.exception.error_code = error_code;
298101da
AK		 308}
309EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
310
0a79b009
AK		 311/*
312 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
313 * a #GP and return false.
314 */
315bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 316{
0a79b009
AK		 317 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
318 return true;
319 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
320 return false;
298101da 321}
0a79b009 322EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 323
a03490ed
CO		 324/*
325 * Load the pae pdptrs. Return true is they are all valid.
326 */
327int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
328{
329 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
330 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
331 int i;
332 int ret;
ad312c7c 333 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 334
a03490ed
CO		 335 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
336 offset * sizeof(u64), sizeof(pdpte));
337 if (ret < 0) {
338 ret = 0;
339 goto out;
340 }
341 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 342 if (is_present_gpte(pdpte[i]) &&
20c466b5 343 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 344 ret = 0;
345 goto out;
346 }
347 }
348 ret = 1;
349
ad312c7c 350 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 351 __set_bit(VCPU_EXREG_PDPTR,
352 (unsigned long *)&vcpu->arch.regs_avail);
353 __set_bit(VCPU_EXREG_PDPTR,
354 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 355out:
a03490ed
CO		 356
357 return ret;
358}
cc4b6871 359EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 360
d835dfec
AK		 361static bool pdptrs_changed(struct kvm_vcpu *vcpu)
362{
ad312c7c 363 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 364 bool changed = true;
365 int r;
366
367 if (is_long_mode(vcpu) || !is_pae(vcpu))
368 return false;
369
6de4f3ad
AK		 370 if (!test_bit(VCPU_EXREG_PDPTR,
371 (unsigned long *)&vcpu->arch.regs_avail))
372 return true;
373
ad312c7c 374 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 375 if (r < 0)
376 goto out;
ad312c7c 377 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 378out:
d835dfec
AK		 379
380 return changed;
381}
382
2d3ad1f4 383void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 384{
385 if (cr0 & CR0_RESERVED_BITS) {
386 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 387 cr0, vcpu->arch.cr0);
c1a5d4f9 388 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 389 return;
390 }
391
392 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
393 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 394 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 395 return;
396 }
397
398 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
399 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
400 "and a clear PE flag\n");
c1a5d4f9 401 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 402 return;
403 }
404
405 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
406#ifdef CONFIG_X86_64
ad312c7c 407 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 408 int cs_db, cs_l;
409
410 if (!is_pae(vcpu)) {
411 printk(KERN_DEBUG "set_cr0: #GP, start paging "
412 "in long mode while PAE is disabled\n");
c1a5d4f9 413 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 414 return;
415 }
416 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
417 if (cs_l) {
418 printk(KERN_DEBUG "set_cr0: #GP, start paging "
419 "in long mode while CS.L == 1\n");
c1a5d4f9 420 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 421 return;
422
423 }
424 } else
425#endif
ad312c7c 426 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 427 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
428 "reserved bits\n");
c1a5d4f9 429 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 430 return;
431 }
432
433 }
434
435 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 436 vcpu->arch.cr0 = cr0;
a03490ed 437
a03490ed 438 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 439 return;
440}
2d3ad1f4 441EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 442
2d3ad1f4 443void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 444{
2d3ad1f4 445 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 446}
2d3ad1f4 447EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 448
2d3ad1f4 449void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 450{
a2edf57f
AK		 451 unsigned long old_cr4 = vcpu->arch.cr4;
452 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
453
a03490ed
CO		 454 if (cr4 & CR4_RESERVED_BITS) {
455 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 456 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 457 return;
458 }
459
460 if (is_long_mode(vcpu)) {
461 if (!(cr4 & X86_CR4_PAE)) {
462 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
463 "in long mode\n");
c1a5d4f9 464 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 465 return;
466 }
a2edf57f
AK		 467 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
468 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 469 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 470 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 471 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 472 return;
473 }
474
475 if (cr4 & X86_CR4_VMXE) {
476 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 477 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 478 return;
479 }
480 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 481 vcpu->arch.cr4 = cr4;
5a41accd 482 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 483 kvm_mmu_reset_context(vcpu);
a03490ed 484}
2d3ad1f4 485EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 486
2d3ad1f4 487void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 488{
ad312c7c 489 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 490 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 491 kvm_mmu_flush_tlb(vcpu);
492 return;
493 }
494
a03490ed
CO		 495 if (is_long_mode(vcpu)) {
496 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
497 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 498 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 499 return;
500 }
501 } else {
502 if (is_pae(vcpu)) {
503 if (cr3 & CR3_PAE_RESERVED_BITS) {
504 printk(KERN_DEBUG
505 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 506 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 507 return;
508 }
509 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
510 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
511 "reserved bits\n");
c1a5d4f9 512 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 513 return;
514 }
515 }
516 /*
517 * We don't check reserved bits in nonpae mode, because
518 * this isn't enforced, and VMware depends on this.
519 */
520 }
521
a03490ed
CO		 522 /*
523 * Does the new cr3 value map to physical memory? (Note, we
524 * catch an invalid cr3 even in real-mode, because it would
525 * cause trouble later on when we turn on paging anyway.)
526 *
527 * A real CPU would silently accept an invalid cr3 and would
528 * attempt to use it - with largely undefined (and often hard
529 * to debug) behavior on the guest side.
530 */
531 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 532 kvm_inject_gp(vcpu, 0);
a03490ed 533 else {
ad312c7c
ZX		 534 vcpu->arch.cr3 = cr3;
535 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 536 }
a03490ed 537}
2d3ad1f4 538EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 539
2d3ad1f4 540void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 541{
542 if (cr8 & CR8_RESERVED_BITS) {
543 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 544 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 545 return;
546 }
547 if (irqchip_in_kernel(vcpu->kvm))
548 kvm_lapic_set_tpr(vcpu, cr8);
549 else
ad312c7c 550 vcpu->arch.cr8 = cr8;
a03490ed 551}
2d3ad1f4 552EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 553
2d3ad1f4 554unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 555{
556 if (irqchip_in_kernel(vcpu->kvm))
557 return kvm_lapic_get_cr8(vcpu);
558 else
ad312c7c 559 return vcpu->arch.cr8;
a03490ed 560}
2d3ad1f4 561EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 562
d8017474
AG		 563static inline u32 bit(int bitno)
564{
565 return 1 << (bitno & 31);
566}
567
043405e1
CO		 568/*
569 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
570 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
571 *
572 * This list is modified at module load time to reflect the
e3267cbb
GC		 573 * capabilities of the host cpu. This capabilities test skips MSRs that are
574 * kvm-specific. Those are put in the beginning of the list.
043405e1 575 */
e3267cbb
GC		 576
577#define KVM_SAVE_MSRS_BEGIN 2
043405e1 578static u32 msrs_to_save[] = {
e3267cbb 579 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
043405e1
CO		 580 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
581 MSR_K6_STAR,
582#ifdef CONFIG_X86_64
583 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
584#endif
e3267cbb 585 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 586};
587
588static unsigned num_msrs_to_save;
589
590static u32 emulated_msrs[] = {
591 MSR_IA32_MISC_ENABLE,
592};
593
15c4a640
CO		 594static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
595{
f2b4b7dd 596 if (efer & efer_reserved_bits) {
15c4a640
CO		 597 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
598 efer);
c1a5d4f9 599 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 600 return;
601 }
602
603 if (is_paging(vcpu)
ad312c7c 604 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 605 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 606 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 607 return;
608 }
609
1b2fd70c
AG		 610 if (efer & EFER_FFXSR) {
611 struct kvm_cpuid_entry2 *feat;
612
613 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
614 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
615 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
616 kvm_inject_gp(vcpu, 0);
617 return;
618 }
619 }
620
d8017474
AG		 621 if (efer & EFER_SVME) {
622 struct kvm_cpuid_entry2 *feat;
623
624 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
625 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
626 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
627 kvm_inject_gp(vcpu, 0);
628 return;
629 }
630 }
631
15c4a640
CO		 632 kvm_x86_ops->set_efer(vcpu, efer);
633
634 efer &= ~EFER_LMA;
ad312c7c 635 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 636
ad312c7c 637 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 638
639 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
640 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 641}
642
f2b4b7dd
JR		 643void kvm_enable_efer_bits(u64 mask)
644{
645 efer_reserved_bits &= ~mask;
646}
647EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
648
649
15c4a640
CO		 650/*
651 * Writes msr value into into the appropriate "register".
652 * Returns 0 on success, non-0 otherwise.
653 * Assumes vcpu_load() was already called.
654 */
655int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
656{
657 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
658}
659
313a3dc7
CO		 660/*
661 * Adapt set_msr() to msr_io()'s calling convention
662 */
663static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
664{
665 return kvm_set_msr(vcpu, index, *data);
666}
667
18068523
GOC		 668static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
669{
670 static int version;
50d0a0f9
GH		 671 struct pvclock_wall_clock wc;
672 struct timespec now, sys, boot;
18068523
GOC		 673
674 if (!wall_clock)
675 return;
676
677 version++;
678
18068523
GOC		 679 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
680
50d0a0f9
GH		 681 /*
682 * The guest calculates current wall clock time by adding
683 * system time (updated by kvm_write_guest_time below) to the
684 * wall clock specified here. guest system time equals host
685 * system time for us, thus we must fill in host boot time here.
686 */
687 now = current_kernel_time();
688 ktime_get_ts(&sys);
689 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
690
691 wc.sec = boot.tv_sec;
692 wc.nsec = boot.tv_nsec;
693 wc.version = version;
18068523
GOC		 694
695 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
696
697 version++;
698 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 699}
700
50d0a0f9
GH		 701static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
702{
703 uint32_t quotient, remainder;
704
705 /* Don't try to replace with do_div(), this one calculates
706 * "(dividend << 32) / divisor" */
707 __asm__ ( "divl %4"
708 : "=a" (quotient), "=d" (remainder)
709 : "0" (0), "1" (dividend), "r" (divisor) );
710 return quotient;
711}
712
713static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
714{
715 uint64_t nsecs = 1000000000LL;
716 int32_t shift = 0;
717 uint64_t tps64;
718 uint32_t tps32;
719
720 tps64 = tsc_khz * 1000LL;
721 while (tps64 > nsecs*2) {
722 tps64 >>= 1;
723 shift--;
724 }
725
726 tps32 = (uint32_t)tps64;
727 while (tps32 <= (uint32_t)nsecs) {
728 tps32 <<= 1;
729 shift++;
730 }
731
732 hv_clock->tsc_shift = shift;
733 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
734
735 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 736 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 737 hv_clock->tsc_to_system_mul);
738}
739
c8076604
GH		 740static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
741
18068523
GOC		 742static void kvm_write_guest_time(struct kvm_vcpu *v)
743{
744 struct timespec ts;
745 unsigned long flags;
746 struct kvm_vcpu_arch *vcpu = &v->arch;
747 void *shared_kaddr;
463656c0 748 unsigned long this_tsc_khz;
18068523
GOC		 749
750 if ((!vcpu->time_page))
751 return;
752
463656c0
AK		 753 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
754 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
755 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
756 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 757 }
463656c0 758 put_cpu_var(cpu_tsc_khz);
50d0a0f9 759
18068523
GOC		 760 /* Keep irq disabled to prevent changes to the clock */
761 local_irq_save(flags);
af24a4e4 762 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 763 ktime_get_ts(&ts);
764 local_irq_restore(flags);
765
766 /* With all the info we got, fill in the values */
767
768 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 769 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
770
18068523
GOC		 771 /*
772 * The interface expects us to write an even number signaling that the
773 * update is finished. Since the guest won't see the intermediate
50d0a0f9 774 * state, we just increase by 2 at the end.
18068523 775 */
50d0a0f9 776 vcpu->hv_clock.version += 2;
18068523
GOC		 777
778 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
779
780 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 781 sizeof(vcpu->hv_clock));
18068523
GOC		 782
783 kunmap_atomic(shared_kaddr, KM_USER0);
784
785 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
786}
787
c8076604
GH		 788static int kvm_request_guest_time_update(struct kvm_vcpu *v)
789{
790 struct kvm_vcpu_arch *vcpu = &v->arch;
791
792 if (!vcpu->time_page)
793 return 0;
794 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
795 return 1;
796}
797
9ba075a6
AK		 798static bool msr_mtrr_valid(unsigned msr)
799{
800 switch (msr) {
801 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
802 case MSR_MTRRfix64K_00000:
803 case MSR_MTRRfix16K_80000:
804 case MSR_MTRRfix16K_A0000:
805 case MSR_MTRRfix4K_C0000:
806 case MSR_MTRRfix4K_C8000:
807 case MSR_MTRRfix4K_D0000:
808 case MSR_MTRRfix4K_D8000:
809 case MSR_MTRRfix4K_E0000:
810 case MSR_MTRRfix4K_E8000:
811 case MSR_MTRRfix4K_F0000:
812 case MSR_MTRRfix4K_F8000:
813 case MSR_MTRRdefType:
814 case MSR_IA32_CR_PAT:
815 return true;
816 case 0x2f8:
817 return true;
818 }
819 return false;
820}
821
d6289b93
MT		 822static bool valid_pat_type(unsigned t)
823{
824 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
825}
826
827static bool valid_mtrr_type(unsigned t)
828{
829 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
830}
831
832static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
833{
834 int i;
835
836 if (!msr_mtrr_valid(msr))
837 return false;
838
839 if (msr == MSR_IA32_CR_PAT) {
840 for (i = 0; i < 8; i++)
841 if (!valid_pat_type((data >> (i * 8)) & 0xff))
842 return false;
843 return true;
844 } else if (msr == MSR_MTRRdefType) {
845 if (data & ~0xcff)
846 return false;
847 return valid_mtrr_type(data & 0xff);
848 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
849 for (i = 0; i < 8 ; i++)
850 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
851 return false;
852 return true;
853 }
854
855 /* variable MTRRs */
856 return valid_mtrr_type(data & 0xff);
857}
858
9ba075a6
AK		 859static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
860{
0bed3b56
SY		 861 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
862
d6289b93 863 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 864 return 1;
865
0bed3b56
SY		 866 if (msr == MSR_MTRRdefType) {
867 vcpu->arch.mtrr_state.def_type = data;
868 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
869 } else if (msr == MSR_MTRRfix64K_00000)
870 p[0] = data;
871 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
872 p[1 + msr - MSR_MTRRfix16K_80000] = data;
873 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
874 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
875 else if (msr == MSR_IA32_CR_PAT)
876 vcpu->arch.pat = data;
877 else { /* Variable MTRRs */
878 int idx, is_mtrr_mask;
879 u64 *pt;
880
881 idx = (msr - 0x200) / 2;
882 is_mtrr_mask = msr - 0x200 - 2 * idx;
883 if (!is_mtrr_mask)
884 pt =
885 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
886 else
887 pt =
888 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
889 *pt = data;
890 }
891
892 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 893 return 0;
894}
15c4a640 895
890ca9ae 896static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 897{
890ca9ae
HY		 898 u64 mcg_cap = vcpu->arch.mcg_cap;
899 unsigned bank_num = mcg_cap & 0xff;
900
15c4a640 901 switch (msr) {
15c4a640 902 case MSR_IA32_MCG_STATUS:
890ca9ae 903 vcpu->arch.mcg_status = data;
15c4a640 904 break;
c7ac679c 905 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 906 if (!(mcg_cap & MCG_CTL_P))
907 return 1;
908 if (data != 0 && data != ~(u64)0)
909 return -1;
910 vcpu->arch.mcg_ctl = data;
911 break;
912 default:
913 if (msr >= MSR_IA32_MC0_CTL &&
914 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
915 u32 offset = msr - MSR_IA32_MC0_CTL;
916 /* only 0 or all 1s can be written to IA32_MCi_CTL */
917 if ((offset & 0x3) == 0 &&
918 data != 0 && data != ~(u64)0)
919 return -1;
920 vcpu->arch.mce_banks[offset] = data;
921 break;
922 }
923 return 1;
924 }
925 return 0;
926}
927
ffde22ac
ES		 928static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
929{
930 struct kvm *kvm = vcpu->kvm;
931 int lm = is_long_mode(vcpu);
932 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
933 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
934 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
935 : kvm->arch.xen_hvm_config.blob_size_32;
936 u32 page_num = data & ~PAGE_MASK;
937 u64 page_addr = data & PAGE_MASK;
938 u8 *page;
939 int r;
940
941 r = -E2BIG;
942 if (page_num >= blob_size)
943 goto out;
944 r = -ENOMEM;
945 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
946 if (!page)
947 goto out;
948 r = -EFAULT;
949 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
950 goto out_free;
951 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
952 goto out_free;
953 r = 0;
954out_free:
955 kfree(page);
956out:
957 return r;
958}
959
15c4a640
CO		 960int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
961{
962 switch (msr) {
15c4a640
CO		 963 case MSR_EFER:
964 set_efer(vcpu, data);
965 break;
8f1589d9
AP		 966 case MSR_K7_HWCR:
967 data &= ~(u64)0x40; /* ignore flush filter disable */
968 if (data != 0) {
969 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
970 data);
971 return 1;
972 }
15c4a640 973 break;
f7c6d140
AP		 974 case MSR_FAM10H_MMIO_CONF_BASE:
975 if (data != 0) {
976 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
977 "0x%llx\n", data);
978 return 1;
979 }
15c4a640 980 break;
c323c0e5 981 case MSR_AMD64_NB_CFG:
c7ac679c 982 break;
b5e2fec0
AG		 983 case MSR_IA32_DEBUGCTLMSR:
984 if (!data) {
985 /* We support the non-activated case already */
986 break;
987 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
988 /* Values other than LBR and BTF are vendor-specific,
989 thus reserved and should throw a #GP */
990 return 1;
991 }
992 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
993 __func__, data);
994 break;
15c4a640
CO		 995 case MSR_IA32_UCODE_REV:
996 case MSR_IA32_UCODE_WRITE:
61a6bd67 997 case MSR_VM_HSAVE_PA:
6098ca93 998 case MSR_AMD64_PATCH_LOADER:
15c4a640 999 break;
9ba075a6
AK		 1000 case 0x200 ... 0x2ff:
1001 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1002 case MSR_IA32_APICBASE:
1003 kvm_set_apic_base(vcpu, data);
1004 break;
0105d1a5
GN		 1005 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1006 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1007 case MSR_IA32_MISC_ENABLE:
ad312c7c 1008 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1009 break;
18068523
GOC		 1010 case MSR_KVM_WALL_CLOCK:
1011 vcpu->kvm->arch.wall_clock = data;
1012 kvm_write_wall_clock(vcpu->kvm, data);
1013 break;
1014 case MSR_KVM_SYSTEM_TIME: {
1015 if (vcpu->arch.time_page) {
1016 kvm_release_page_dirty(vcpu->arch.time_page);
1017 vcpu->arch.time_page = NULL;
1018 }
1019
1020 vcpu->arch.time = data;
1021
1022 /* we verify if the enable bit is set... */
1023 if (!(data & 1))
1024 break;
1025
1026 /* ...but clean it before doing the actual write */
1027 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1028
18068523
GOC		 1029 vcpu->arch.time_page =
1030 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1031
1032 if (is_error_page(vcpu->arch.time_page)) {
1033 kvm_release_page_clean(vcpu->arch.time_page);
1034 vcpu->arch.time_page = NULL;
1035 }
1036
c8076604 1037 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1038 break;
1039 }
890ca9ae
HY		 1040 case MSR_IA32_MCG_CTL:
1041 case MSR_IA32_MCG_STATUS:
1042 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1043 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1044
1045 /* Performance counters are not protected by a CPUID bit,
1046 * so we should check all of them in the generic path for the sake of
1047 * cross vendor migration.
1048 * Writing a zero into the event select MSRs disables them,
1049 * which we perfectly emulate ;-). Any other value should be at least
1050 * reported, some guests depend on them.
1051 */
1052 case MSR_P6_EVNTSEL0:
1053 case MSR_P6_EVNTSEL1:
1054 case MSR_K7_EVNTSEL0:
1055 case MSR_K7_EVNTSEL1:
1056 case MSR_K7_EVNTSEL2:
1057 case MSR_K7_EVNTSEL3:
1058 if (data != 0)
1059 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1060 "0x%x data 0x%llx\n", msr, data);
1061 break;
1062 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1063 * so we ignore writes to make it happy.
1064 */
1065 case MSR_P6_PERFCTR0:
1066 case MSR_P6_PERFCTR1:
1067 case MSR_K7_PERFCTR0:
1068 case MSR_K7_PERFCTR1:
1069 case MSR_K7_PERFCTR2:
1070 case MSR_K7_PERFCTR3:
1071 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1072 "0x%x data 0x%llx\n", msr, data);
1073 break;
15c4a640 1074 default:
ffde22ac
ES		 1075 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1076 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1077 if (!ignore_msrs) {
1078 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1079 msr, data);
1080 return 1;
1081 } else {
1082 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1083 msr, data);
1084 break;
1085 }
15c4a640
CO		 1086 }
1087 return 0;
1088}
1089EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1090
1091
1092/*
1093 * Reads an msr value (of 'msr_index') into 'pdata'.
1094 * Returns 0 on success, non-0 otherwise.
1095 * Assumes vcpu_load() was already called.
1096 */
1097int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1098{
1099 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1100}
1101
9ba075a6
AK		 1102static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1103{
0bed3b56
SY		 1104 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1105
9ba075a6
AK		 1106 if (!msr_mtrr_valid(msr))
1107 return 1;
1108
0bed3b56
SY		 1109 if (msr == MSR_MTRRdefType)
1110 *pdata = vcpu->arch.mtrr_state.def_type +
1111 (vcpu->arch.mtrr_state.enabled << 10);
1112 else if (msr == MSR_MTRRfix64K_00000)
1113 *pdata = p[0];
1114 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1115 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1116 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1117 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1118 else if (msr == MSR_IA32_CR_PAT)
1119 *pdata = vcpu->arch.pat;
1120 else { /* Variable MTRRs */
1121 int idx, is_mtrr_mask;
1122 u64 *pt;
1123
1124 idx = (msr - 0x200) / 2;
1125 is_mtrr_mask = msr - 0x200 - 2 * idx;
1126 if (!is_mtrr_mask)
1127 pt =
1128 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1129 else
1130 pt =
1131 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1132 *pdata = *pt;
1133 }
1134
9ba075a6
AK		 1135 return 0;
1136}
1137
890ca9ae 1138static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1139{
1140 u64 data;
890ca9ae
HY		 1141 u64 mcg_cap = vcpu->arch.mcg_cap;
1142 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1143
1144 switch (msr) {
15c4a640
CO		 1145 case MSR_IA32_P5_MC_ADDR:
1146 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1147 data = 0;
1148 break;
15c4a640 1149 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1150 data = vcpu->arch.mcg_cap;
1151 break;
c7ac679c 1152 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1153 if (!(mcg_cap & MCG_CTL_P))
1154 return 1;
1155 data = vcpu->arch.mcg_ctl;
1156 break;
1157 case MSR_IA32_MCG_STATUS:
1158 data = vcpu->arch.mcg_status;
1159 break;
1160 default:
1161 if (msr >= MSR_IA32_MC0_CTL &&
1162 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1163 u32 offset = msr - MSR_IA32_MC0_CTL;
1164 data = vcpu->arch.mce_banks[offset];
1165 break;
1166 }
1167 return 1;
1168 }
1169 *pdata = data;
1170 return 0;
1171}
1172
1173int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1174{
1175 u64 data;
1176
1177 switch (msr) {
890ca9ae 1178 case MSR_IA32_PLATFORM_ID:
15c4a640 1179 case MSR_IA32_UCODE_REV:
15c4a640 1180 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1181 case MSR_IA32_DEBUGCTLMSR:
1182 case MSR_IA32_LASTBRANCHFROMIP:
1183 case MSR_IA32_LASTBRANCHTOIP:
1184 case MSR_IA32_LASTINTFROMIP:
1185 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1186 case MSR_K8_SYSCFG:
1187 case MSR_K7_HWCR:
61a6bd67 1188 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1189 case MSR_P6_PERFCTR0:
1190 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1191 case MSR_P6_EVNTSEL0:
1192 case MSR_P6_EVNTSEL1:
9e699624 1193 case MSR_K7_EVNTSEL0:
1f3ee616 1194 case MSR_K7_PERFCTR0:
1fdbd48c 1195 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1196 case MSR_AMD64_NB_CFG:
f7c6d140 1197 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1198 data = 0;
1199 break;
9ba075a6
AK		 1200 case MSR_MTRRcap:
1201 data = 0x500 | KVM_NR_VAR_MTRR;
1202 break;
1203 case 0x200 ... 0x2ff:
1204 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1205 case 0xcd: /* fsb frequency */
1206 data = 3;
1207 break;
1208 case MSR_IA32_APICBASE:
1209 data = kvm_get_apic_base(vcpu);
1210 break;
0105d1a5
GN		 1211 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1212 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1213 break;
15c4a640 1214 case MSR_IA32_MISC_ENABLE:
ad312c7c 1215 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1216 break;
847f0ad8
AG		 1217 case MSR_IA32_PERF_STATUS:
1218 /* TSC increment by tick */
1219 data = 1000ULL;
1220 /* CPU multiplier */
1221 data |= (((uint64_t)4ULL) << 40);
1222 break;
15c4a640 1223 case MSR_EFER:
ad312c7c 1224 data = vcpu->arch.shadow_efer;
15c4a640 1225 break;
18068523
GOC		 1226 case MSR_KVM_WALL_CLOCK:
1227 data = vcpu->kvm->arch.wall_clock;
1228 break;
1229 case MSR_KVM_SYSTEM_TIME:
1230 data = vcpu->arch.time;
1231 break;
890ca9ae
HY		 1232 case MSR_IA32_P5_MC_ADDR:
1233 case MSR_IA32_P5_MC_TYPE:
1234 case MSR_IA32_MCG_CAP:
1235 case MSR_IA32_MCG_CTL:
1236 case MSR_IA32_MCG_STATUS:
1237 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1238 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1239 default:
ed85c068
AP		 1240 if (!ignore_msrs) {
1241 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1242 return 1;
1243 } else {
1244 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1245 data = 0;
1246 }
1247 break;
15c4a640
CO		 1248 }
1249 *pdata = data;
1250 return 0;
1251}
1252EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1253
313a3dc7
CO		 1254/*
1255 * Read or write a bunch of msrs. All parameters are kernel addresses.
1256 *
1257 * @return number of msrs set successfully.
1258 */
1259static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1260 struct kvm_msr_entry *entries,
1261 int (*do_msr)(struct kvm_vcpu *vcpu,
1262 unsigned index, u64 *data))
1263{
1264 int i;
1265
1266 vcpu_load(vcpu);
1267
3200f405 1268 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1269 for (i = 0; i < msrs->nmsrs; ++i)
1270 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1271 break;
3200f405 1272 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1273
1274 vcpu_put(vcpu);
1275
1276 return i;
1277}
1278
1279/*
1280 * Read or write a bunch of msrs. Parameters are user addresses.
1281 *
1282 * @return number of msrs set successfully.
1283 */
1284static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1285 int (*do_msr)(struct kvm_vcpu *vcpu,
1286 unsigned index, u64 *data),
1287 int writeback)
1288{
1289 struct kvm_msrs msrs;
1290 struct kvm_msr_entry *entries;
1291 int r, n;
1292 unsigned size;
1293
1294 r = -EFAULT;
1295 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1296 goto out;
1297
1298 r = -E2BIG;
1299 if (msrs.nmsrs >= MAX_IO_MSRS)
1300 goto out;
1301
1302 r = -ENOMEM;
1303 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1304 entries = vmalloc(size);
1305 if (!entries)
1306 goto out;
1307
1308 r = -EFAULT;
1309 if (copy_from_user(entries, user_msrs->entries, size))
1310 goto out_free;
1311
1312 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1313 if (r < 0)
1314 goto out_free;
1315
1316 r = -EFAULT;
1317 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1318 goto out_free;
1319
1320 r = n;
1321
1322out_free:
1323 vfree(entries);
1324out:
1325 return r;
1326}
1327
018d00d2
ZX		 1328int kvm_dev_ioctl_check_extension(long ext)
1329{
1330 int r;
1331
1332 switch (ext) {
1333 case KVM_CAP_IRQCHIP:
1334 case KVM_CAP_HLT:
1335 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1336 case KVM_CAP_SET_TSS_ADDR:
07716717 1337 case KVM_CAP_EXT_CPUID:
c8076604 1338 case KVM_CAP_CLOCKSOURCE:
7837699f 1339 case KVM_CAP_PIT:
a28e4f5a 1340 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1341 case KVM_CAP_MP_STATE:
ed848624 1342 case KVM_CAP_SYNC_MMU:
52d939a0 1343 case KVM_CAP_REINJECT_CONTROL:
4925663a 1344 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1345 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1346 case KVM_CAP_IRQFD:
d34e6b17 1347 case KVM_CAP_IOEVENTFD:
c5ff41ce 1348 case KVM_CAP_PIT2:
e9f42757 1349 case KVM_CAP_PIT_STATE2:
b927a3ce 1350 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1351 case KVM_CAP_XEN_HVM:
afbcf7ab 1352 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1353 case KVM_CAP_VCPU_EVENTS:
018d00d2
ZX		 1354 r = 1;
1355 break;
542472b5
LV		 1356 case KVM_CAP_COALESCED_MMIO:
1357 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1358 break;
774ead3a
AK		 1359 case KVM_CAP_VAPIC:
1360 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1361 break;
f725230a
AK		 1362 case KVM_CAP_NR_VCPUS:
1363 r = KVM_MAX_VCPUS;
1364 break;
a988b910
AK		 1365 case KVM_CAP_NR_MEMSLOTS:
1366 r = KVM_MEMORY_SLOTS;
1367 break;
a68a6a72
MT		 1368 case KVM_CAP_PV_MMU: /* obsolete */
1369 r = 0;
2f333bcb 1370 break;
62c476c7 1371 case KVM_CAP_IOMMU:
19de40a8 1372 r = iommu_found();
62c476c7 1373 break;
890ca9ae
HY		 1374 case KVM_CAP_MCE:
1375 r = KVM_MAX_MCE_BANKS;
1376 break;
018d00d2
ZX		 1377 default:
1378 r = 0;
1379 break;
1380 }
1381 return r;
1382
1383}
1384
043405e1
CO		 1385long kvm_arch_dev_ioctl(struct file *filp,
1386 unsigned int ioctl, unsigned long arg)
1387{
1388 void __user *argp = (void __user *)arg;
1389 long r;
1390
1391 switch (ioctl) {
1392 case KVM_GET_MSR_INDEX_LIST: {
1393 struct kvm_msr_list __user *user_msr_list = argp;
1394 struct kvm_msr_list msr_list;
1395 unsigned n;
1396
1397 r = -EFAULT;
1398 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1399 goto out;
1400 n = msr_list.nmsrs;
1401 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1402 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1403 goto out;
1404 r = -E2BIG;
e125e7b6 1405 if (n < msr_list.nmsrs)
043405e1
CO		 1406 goto out;
1407 r = -EFAULT;
1408 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1409 num_msrs_to_save * sizeof(u32)))
1410 goto out;
e125e7b6 1411 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1412 &emulated_msrs,
1413 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1414 goto out;
1415 r = 0;
1416 break;
1417 }
674eea0f
AK		 1418 case KVM_GET_SUPPORTED_CPUID: {
1419 struct kvm_cpuid2 __user *cpuid_arg = argp;
1420 struct kvm_cpuid2 cpuid;
1421
1422 r = -EFAULT;
1423 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1424 goto out;
1425 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1426 cpuid_arg->entries);
674eea0f
AK		 1427 if (r)
1428 goto out;
1429
1430 r = -EFAULT;
1431 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1432 goto out;
1433 r = 0;
1434 break;
1435 }
890ca9ae
HY		 1436 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1437 u64 mce_cap;
1438
1439 mce_cap = KVM_MCE_CAP_SUPPORTED;
1440 r = -EFAULT;
1441 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1442 goto out;
1443 r = 0;
1444 break;
1445 }
043405e1
CO		 1446 default:
1447 r = -EINVAL;
1448 }
1449out:
1450 return r;
1451}
1452
313a3dc7
CO		 1453void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1454{
1455 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1456 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1457 unsigned long khz = cpufreq_quick_get(cpu);
1458 if (!khz)
1459 khz = tsc_khz;
1460 per_cpu(cpu_tsc_khz, cpu) = khz;
1461 }
c8076604 1462 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1463}
1464
1465void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1466{
1467 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1468 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1469}
1470
07716717 1471static int is_efer_nx(void)
313a3dc7 1472{
e286e86e 1473 unsigned long long efer = 0;
313a3dc7 1474
e286e86e 1475 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1476 return efer & EFER_NX;
1477}
1478
1479static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1480{
1481 int i;
1482 struct kvm_cpuid_entry2 *e, *entry;
1483
313a3dc7 1484 entry = NULL;
ad312c7c
ZX		 1485 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1486 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1487 if (e->function == 0x80000001) {
1488 entry = e;
1489 break;
1490 }
1491 }
07716717 1492 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1493 entry->edx &= ~(1 << 20);
1494 printk(KERN_INFO "kvm: guest NX capability removed\n");
1495 }
1496}
1497
07716717 1498/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1499static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1500 struct kvm_cpuid *cpuid,
1501 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1502{
1503 int r, i;
1504 struct kvm_cpuid_entry *cpuid_entries;
1505
1506 r = -E2BIG;
1507 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1508 goto out;
1509 r = -ENOMEM;
1510 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1511 if (!cpuid_entries)
1512 goto out;
1513 r = -EFAULT;
1514 if (copy_from_user(cpuid_entries, entries,
1515 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1516 goto out_free;
1517 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1518 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1519 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1520 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1521 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1522 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1523 vcpu->arch.cpuid_entries[i].index = 0;
1524 vcpu->arch.cpuid_entries[i].flags = 0;
1525 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1526 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1527 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1528 }
1529 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1530 cpuid_fix_nx_cap(vcpu);
1531 r = 0;
fc61b800 1532 kvm_apic_set_version(vcpu);
07716717
DK		 1533
1534out_free:
1535 vfree(cpuid_entries);
1536out:
1537 return r;
1538}
1539
1540static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1541 struct kvm_cpuid2 *cpuid,
1542 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1543{
1544 int r;
1545
1546 r = -E2BIG;
1547 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1548 goto out;
1549 r = -EFAULT;
ad312c7c 1550 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1551 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1552 goto out;
ad312c7c 1553 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1554 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1555 return 0;
1556
1557out:
1558 return r;
1559}
1560
07716717 1561static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1562 struct kvm_cpuid2 *cpuid,
1563 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1564{
1565 int r;
1566
1567 r = -E2BIG;
ad312c7c 1568 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1569 goto out;
1570 r = -EFAULT;
ad312c7c 1571 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1572 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1573 goto out;
1574 return 0;
1575
1576out:
ad312c7c 1577 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1578 return r;
1579}
1580
07716717 1581static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1582 u32 index)
07716717
DK		 1583{
1584 entry->function = function;
1585 entry->index = index;
1586 cpuid_count(entry->function, entry->index,
19355475 1587 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1588 entry->flags = 0;
1589}
1590
7faa4ee1
AK		 1591#define F(x) bit(X86_FEATURE_##x)
1592
07716717
DK		 1593static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1594 u32 index, int *nent, int maxnent)
1595{
7faa4ee1 1596 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
344f414f 1597 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
07716717 1598#ifdef CONFIG_X86_64
7faa4ee1
AK		 1599 unsigned f_lm = F(LM);
1600#else
1601 unsigned f_lm = 0;
07716717 1602#endif
7faa4ee1
AK		 1603
1604 /* cpuid 1.edx */
1605 const u32 kvm_supported_word0_x86_features =
1606 F(FPU) | F(VME) | F(DE) | F(PSE) |
1607 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1608 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1609 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1610 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1611 0 /* Reserved, DS, ACPI */ | F(MMX) |
1612 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1613 0 /* HTT, TM, Reserved, PBE */;
1614 /* cpuid 0x80000001.edx */
1615 const u32 kvm_supported_word1_x86_features =
1616 F(FPU) | F(VME) | F(DE) | F(PSE) |
1617 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1618 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1619 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1620 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1621 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
344f414f 1622 F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ |
7faa4ee1
AK		 1623 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1624 /* cpuid 1.ecx */
1625 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1626 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1627 0 /* DS-CPL, VMX, SMX, EST */ |
1628 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1629 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1630 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1631 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1632 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1633 /* cpuid 0x80000001.ecx */
07716717 1634 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1635 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1636 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1637 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1638 0 /* SKINIT */ | 0 /* WDT */;
07716717 1639
19355475 1640 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1641 get_cpu();
1642 do_cpuid_1_ent(entry, function, index);
1643 ++*nent;
1644
1645 switch (function) {
1646 case 0:
1647 entry->eax = min(entry->eax, (u32)0xb);
1648 break;
1649 case 1:
1650 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1651 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1652 /* we support x2apic emulation even if host does not support
1653 * it since we emulate x2apic in software */
1654 entry->ecx |= F(X2APIC);
07716717
DK		 1655 break;
1656 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1657 * may return different values. This forces us to get_cpu() before
1658 * issuing the first command, and also to emulate this annoying behavior
1659 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1660 case 2: {
1661 int t, times = entry->eax & 0xff;
1662
1663 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1664 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1665 for (t = 1; t < times && *nent < maxnent; ++t) {
1666 do_cpuid_1_ent(&entry[t], function, 0);
1667 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1668 ++*nent;
1669 }
1670 break;
1671 }
1672 /* function 4 and 0xb have additional index. */
1673 case 4: {
14af3f3c 1674 int i, cache_type;
07716717
DK		 1675
1676 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1677 /* read more entries until cache_type is zero */
14af3f3c
HH		 1678 for (i = 1; *nent < maxnent; ++i) {
1679 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1680 if (!cache_type)
1681 break;
14af3f3c
HH		 1682 do_cpuid_1_ent(&entry[i], function, i);
1683 entry[i].flags |=
07716717
DK		 1684 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1685 ++*nent;
1686 }
1687 break;
1688 }
1689 case 0xb: {
14af3f3c 1690 int i, level_type;
07716717
DK		 1691
1692 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1693 /* read more entries until level_type is zero */
14af3f3c 1694 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1695 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1696 if (!level_type)
1697 break;
14af3f3c
HH		 1698 do_cpuid_1_ent(&entry[i], function, i);
1699 entry[i].flags |=
07716717
DK		 1700 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1701 ++*nent;
1702 }
1703 break;
1704 }
1705 case 0x80000000:
1706 entry->eax = min(entry->eax, 0x8000001a);
1707 break;
1708 case 0x80000001:
1709 entry->edx &= kvm_supported_word1_x86_features;
1710 entry->ecx &= kvm_supported_word6_x86_features;
1711 break;
1712 }
1713 put_cpu();
1714}
1715
7faa4ee1
AK		 1716#undef F
1717
674eea0f 1718static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1719 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1720{
1721 struct kvm_cpuid_entry2 *cpuid_entries;
1722 int limit, nent = 0, r = -E2BIG;
1723 u32 func;
1724
1725 if (cpuid->nent < 1)
1726 goto out;
6a544355
AK		 1727 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1728 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1729 r = -ENOMEM;
1730 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1731 if (!cpuid_entries)
1732 goto out;
1733
1734 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1735 limit = cpuid_entries[0].eax;
1736 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1737 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1738 &nent, cpuid->nent);
07716717
DK		 1739 r = -E2BIG;
1740 if (nent >= cpuid->nent)
1741 goto out_free;
1742
1743 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1744 limit = cpuid_entries[nent - 1].eax;
1745 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1746 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1747 &nent, cpuid->nent);
cb007648
MM		 1748 r = -E2BIG;
1749 if (nent >= cpuid->nent)
1750 goto out_free;
1751
07716717
DK		 1752 r = -EFAULT;
1753 if (copy_to_user(entries, cpuid_entries,
19355475 1754 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1755 goto out_free;
1756 cpuid->nent = nent;
1757 r = 0;
1758
1759out_free:
1760 vfree(cpuid_entries);
1761out:
1762 return r;
1763}
1764
313a3dc7
CO		 1765static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1766 struct kvm_lapic_state *s)
1767{
1768 vcpu_load(vcpu);
ad312c7c 1769 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1770 vcpu_put(vcpu);
1771
1772 return 0;
1773}
1774
1775static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1776 struct kvm_lapic_state *s)
1777{
1778 vcpu_load(vcpu);
ad312c7c 1779 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1780 kvm_apic_post_state_restore(vcpu);
cb142eb7 1781 update_cr8_intercept(vcpu);
313a3dc7
CO		 1782 vcpu_put(vcpu);
1783
1784 return 0;
1785}
1786
f77bc6a4
ZX		 1787static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1788 struct kvm_interrupt *irq)
1789{
1790 if (irq->irq < 0 || irq->irq >= 256)
1791 return -EINVAL;
1792 if (irqchip_in_kernel(vcpu->kvm))
1793 return -ENXIO;
1794 vcpu_load(vcpu);
1795
66fd3f7f 1796 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1797
1798 vcpu_put(vcpu);
1799
1800 return 0;
1801}
1802
c4abb7c9
JK		 1803static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1804{
1805 vcpu_load(vcpu);
1806 kvm_inject_nmi(vcpu);
1807 vcpu_put(vcpu);
1808
1809 return 0;
1810}
1811
b209749f
AK		 1812static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1813 struct kvm_tpr_access_ctl *tac)
1814{
1815 if (tac->flags)
1816 return -EINVAL;
1817 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1818 return 0;
1819}
1820
890ca9ae
HY		 1821static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1822 u64 mcg_cap)
1823{
1824 int r;
1825 unsigned bank_num = mcg_cap & 0xff, bank;
1826
1827 r = -EINVAL;
a9e38c3e 1828 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 1829 goto out;
1830 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1831 goto out;
1832 r = 0;
1833 vcpu->arch.mcg_cap = mcg_cap;
1834 /* Init IA32_MCG_CTL to all 1s */
1835 if (mcg_cap & MCG_CTL_P)
1836 vcpu->arch.mcg_ctl = ~(u64)0;
1837 /* Init IA32_MCi_CTL to all 1s */
1838 for (bank = 0; bank < bank_num; bank++)
1839 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1840out:
1841 return r;
1842}
1843
1844static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1845 struct kvm_x86_mce *mce)
1846{
1847 u64 mcg_cap = vcpu->arch.mcg_cap;
1848 unsigned bank_num = mcg_cap & 0xff;
1849 u64 *banks = vcpu->arch.mce_banks;
1850
1851 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1852 return -EINVAL;
1853 /*
1854 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1855 * reporting is disabled
1856 */
1857 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1858 vcpu->arch.mcg_ctl != ~(u64)0)
1859 return 0;
1860 banks += 4 * mce->bank;
1861 /*
1862 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1863 * reporting is disabled for the bank
1864 */
1865 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1866 return 0;
1867 if (mce->status & MCI_STATUS_UC) {
1868 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1869 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1870 printk(KERN_DEBUG "kvm: set_mce: "
1871 "injects mce exception while "
1872 "previous one is in progress!\n");
1873 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1874 return 0;
1875 }
1876 if (banks[1] & MCI_STATUS_VAL)
1877 mce->status |= MCI_STATUS_OVER;
1878 banks[2] = mce->addr;
1879 banks[3] = mce->misc;
1880 vcpu->arch.mcg_status = mce->mcg_status;
1881 banks[1] = mce->status;
1882 kvm_queue_exception(vcpu, MC_VECTOR);
1883 } else if (!(banks[1] & MCI_STATUS_VAL)
1884 || !(banks[1] & MCI_STATUS_UC)) {
1885 if (banks[1] & MCI_STATUS_VAL)
1886 mce->status |= MCI_STATUS_OVER;
1887 banks[2] = mce->addr;
1888 banks[3] = mce->misc;
1889 banks[1] = mce->status;
1890 } else
1891 banks[1] |= MCI_STATUS_OVER;
1892 return 0;
1893}
1894
3cfc3092
JK		 1895static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
1896 struct kvm_vcpu_events *events)
1897{
1898 vcpu_load(vcpu);
1899
1900 events->exception.injected = vcpu->arch.exception.pending;
1901 events->exception.nr = vcpu->arch.exception.nr;
1902 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
1903 events->exception.error_code = vcpu->arch.exception.error_code;
1904
1905 events->interrupt.injected = vcpu->arch.interrupt.pending;
1906 events->interrupt.nr = vcpu->arch.interrupt.nr;
1907 events->interrupt.soft = vcpu->arch.interrupt.soft;
1908
1909 events->nmi.injected = vcpu->arch.nmi_injected;
1910 events->nmi.pending = vcpu->arch.nmi_pending;
1911 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
1912
1913 events->sipi_vector = vcpu->arch.sipi_vector;
1914
1915 events->flags = 0;
1916
1917 vcpu_put(vcpu);
1918}
1919
1920static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
1921 struct kvm_vcpu_events *events)
1922{
1923 if (events->flags)
1924 return -EINVAL;
1925
1926 vcpu_load(vcpu);
1927
1928 vcpu->arch.exception.pending = events->exception.injected;
1929 vcpu->arch.exception.nr = events->exception.nr;
1930 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
1931 vcpu->arch.exception.error_code = events->exception.error_code;
1932
1933 vcpu->arch.interrupt.pending = events->interrupt.injected;
1934 vcpu->arch.interrupt.nr = events->interrupt.nr;
1935 vcpu->arch.interrupt.soft = events->interrupt.soft;
1936 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
1937 kvm_pic_clear_isr_ack(vcpu->kvm);
1938
1939 vcpu->arch.nmi_injected = events->nmi.injected;
1940 vcpu->arch.nmi_pending = events->nmi.pending;
1941 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
1942
1943 vcpu->arch.sipi_vector = events->sipi_vector;
1944
1945 vcpu_put(vcpu);
1946
1947 return 0;
1948}
1949
313a3dc7
CO		 1950long kvm_arch_vcpu_ioctl(struct file *filp,
1951 unsigned int ioctl, unsigned long arg)
1952{
1953 struct kvm_vcpu *vcpu = filp->private_data;
1954 void __user *argp = (void __user *)arg;
1955 int r;
b772ff36 1956 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1957
1958 switch (ioctl) {
1959 case KVM_GET_LAPIC: {
2204ae3c
MT		 1960 r = -EINVAL;
1961 if (!vcpu->arch.apic)
1962 goto out;
b772ff36 1963 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1964
b772ff36
DH		 1965 r = -ENOMEM;
1966 if (!lapic)
1967 goto out;
1968 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1969 if (r)
1970 goto out;
1971 r = -EFAULT;
b772ff36 1972 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1973 goto out;
1974 r = 0;
1975 break;
1976 }
1977 case KVM_SET_LAPIC: {
2204ae3c
MT		 1978 r = -EINVAL;
1979 if (!vcpu->arch.apic)
1980 goto out;
b772ff36
DH		 1981 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1982 r = -ENOMEM;
1983 if (!lapic)
1984 goto out;
313a3dc7 1985 r = -EFAULT;
b772ff36 1986 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1987 goto out;
b772ff36 1988 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1989 if (r)
1990 goto out;
1991 r = 0;
1992 break;
1993 }
f77bc6a4
ZX		 1994 case KVM_INTERRUPT: {
1995 struct kvm_interrupt irq;
1996
1997 r = -EFAULT;
1998 if (copy_from_user(&irq, argp, sizeof irq))
1999 goto out;
2000 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2001 if (r)
2002 goto out;
2003 r = 0;
2004 break;
2005 }
c4abb7c9
JK		 2006 case KVM_NMI: {
2007 r = kvm_vcpu_ioctl_nmi(vcpu);
2008 if (r)
2009 goto out;
2010 r = 0;
2011 break;
2012 }
313a3dc7
CO		 2013 case KVM_SET_CPUID: {
2014 struct kvm_cpuid __user *cpuid_arg = argp;
2015 struct kvm_cpuid cpuid;
2016
2017 r = -EFAULT;
2018 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2019 goto out;
2020 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2021 if (r)
2022 goto out;
2023 break;
2024 }
07716717
DK		 2025 case KVM_SET_CPUID2: {
2026 struct kvm_cpuid2 __user *cpuid_arg = argp;
2027 struct kvm_cpuid2 cpuid;
2028
2029 r = -EFAULT;
2030 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2031 goto out;
2032 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2033 cpuid_arg->entries);
07716717
DK		 2034 if (r)
2035 goto out;
2036 break;
2037 }
2038 case KVM_GET_CPUID2: {
2039 struct kvm_cpuid2 __user *cpuid_arg = argp;
2040 struct kvm_cpuid2 cpuid;
2041
2042 r = -EFAULT;
2043 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2044 goto out;
2045 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2046 cpuid_arg->entries);
07716717
DK		 2047 if (r)
2048 goto out;
2049 r = -EFAULT;
2050 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2051 goto out;
2052 r = 0;
2053 break;
2054 }
313a3dc7
CO		 2055 case KVM_GET_MSRS:
2056 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2057 break;
2058 case KVM_SET_MSRS:
2059 r = msr_io(vcpu, argp, do_set_msr, 0);
2060 break;
b209749f
AK		 2061 case KVM_TPR_ACCESS_REPORTING: {
2062 struct kvm_tpr_access_ctl tac;
2063
2064 r = -EFAULT;
2065 if (copy_from_user(&tac, argp, sizeof tac))
2066 goto out;
2067 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2068 if (r)
2069 goto out;
2070 r = -EFAULT;
2071 if (copy_to_user(argp, &tac, sizeof tac))
2072 goto out;
2073 r = 0;
2074 break;
2075 };
b93463aa
AK		 2076 case KVM_SET_VAPIC_ADDR: {
2077 struct kvm_vapic_addr va;
2078
2079 r = -EINVAL;
2080 if (!irqchip_in_kernel(vcpu->kvm))
2081 goto out;
2082 r = -EFAULT;
2083 if (copy_from_user(&va, argp, sizeof va))
2084 goto out;
2085 r = 0;
2086 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2087 break;
2088 }
890ca9ae
HY		 2089 case KVM_X86_SETUP_MCE: {
2090 u64 mcg_cap;
2091
2092 r = -EFAULT;
2093 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2094 goto out;
2095 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2096 break;
2097 }
2098 case KVM_X86_SET_MCE: {
2099 struct kvm_x86_mce mce;
2100
2101 r = -EFAULT;
2102 if (copy_from_user(&mce, argp, sizeof mce))
2103 goto out;
2104 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2105 break;
2106 }
3cfc3092
JK		 2107 case KVM_GET_VCPU_EVENTS: {
2108 struct kvm_vcpu_events events;
2109
2110 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2111
2112 r = -EFAULT;
2113 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2114 break;
2115 r = 0;
2116 break;
2117 }
2118 case KVM_SET_VCPU_EVENTS: {
2119 struct kvm_vcpu_events events;
2120
2121 r = -EFAULT;
2122 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2123 break;
2124
2125 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2126 break;
2127 }
313a3dc7
CO		 2128 default:
2129 r = -EINVAL;
2130 }
2131out:
7a6ce84c 2132 kfree(lapic);
313a3dc7
CO		 2133 return r;
2134}
2135
1fe779f8
CO		 2136static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2137{
2138 int ret;
2139
2140 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2141 return -1;
2142 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2143 return ret;
2144}
2145
b927a3ce
SY		 2146static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2147 u64 ident_addr)
2148{
2149 kvm->arch.ept_identity_map_addr = ident_addr;
2150 return 0;
2151}
2152
1fe779f8
CO		 2153static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2154 u32 kvm_nr_mmu_pages)
2155{
2156 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2157 return -EINVAL;
2158
72dc67a6 2159 down_write(&kvm->slots_lock);
7c8a83b7 2160 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2161
2162 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2163 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2164
7c8a83b7 2165 spin_unlock(&kvm->mmu_lock);
72dc67a6 2166 up_write(&kvm->slots_lock);
1fe779f8
CO		 2167 return 0;
2168}
2169
2170static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2171{
f05e70ac 2172 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2173}
2174
e9f85cde
ZX		 2175gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2176{
2177 int i;
2178 struct kvm_mem_alias *alias;
2179
d69fb81f
ZX		 2180 for (i = 0; i < kvm->arch.naliases; ++i) {
2181 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 2182 if (gfn >= alias->base_gfn
2183 && gfn < alias->base_gfn + alias->npages)
2184 return alias->target_gfn + gfn - alias->base_gfn;
2185 }
2186 return gfn;
2187}
2188
1fe779f8
CO		 2189/*
2190 * Set a new alias region. Aliases map a portion of physical memory into
2191 * another portion. This is useful for memory windows, for example the PC
2192 * VGA region.
2193 */
2194static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2195 struct kvm_memory_alias *alias)
2196{
2197 int r, n;
2198 struct kvm_mem_alias *p;
2199
2200 r = -EINVAL;
2201 /* General sanity checks */
2202 if (alias->memory_size & (PAGE_SIZE - 1))
2203 goto out;
2204 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2205 goto out;
2206 if (alias->slot >= KVM_ALIAS_SLOTS)
2207 goto out;
2208 if (alias->guest_phys_addr + alias->memory_size
2209 < alias->guest_phys_addr)
2210 goto out;
2211 if (alias->target_phys_addr + alias->memory_size
2212 < alias->target_phys_addr)
2213 goto out;
2214
72dc67a6 2215 down_write(&kvm->slots_lock);
a1708ce8 2216 spin_lock(&kvm->mmu_lock);
1fe779f8 2217
d69fb81f 2218 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 2219 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2220 p->npages = alias->memory_size >> PAGE_SHIFT;
2221 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
2222
2223 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 2224 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 2225 break;
d69fb81f 2226 kvm->arch.naliases = n;
1fe779f8 2227
a1708ce8 2228 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 2229 kvm_mmu_zap_all(kvm);
2230
72dc67a6 2231 up_write(&kvm->slots_lock);
1fe779f8
CO		 2232
2233 return 0;
2234
2235out:
2236 return r;
2237}
2238
2239static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2240{
2241 int r;
2242
2243 r = 0;
2244 switch (chip->chip_id) {
2245 case KVM_IRQCHIP_PIC_MASTER:
2246 memcpy(&chip->chip.pic,
2247 &pic_irqchip(kvm)->pics[0],
2248 sizeof(struct kvm_pic_state));
2249 break;
2250 case KVM_IRQCHIP_PIC_SLAVE:
2251 memcpy(&chip->chip.pic,
2252 &pic_irqchip(kvm)->pics[1],
2253 sizeof(struct kvm_pic_state));
2254 break;
2255 case KVM_IRQCHIP_IOAPIC:
eba0226b 2256 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2257 break;
2258 default:
2259 r = -EINVAL;
2260 break;
2261 }
2262 return r;
2263}
2264
2265static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2266{
2267 int r;
2268
2269 r = 0;
2270 switch (chip->chip_id) {
2271 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2272 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2273 memcpy(&pic_irqchip(kvm)->pics[0],
2274 &chip->chip.pic,
2275 sizeof(struct kvm_pic_state));
894a9c55 2276 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2277 break;
2278 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2279 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2280 memcpy(&pic_irqchip(kvm)->pics[1],
2281 &chip->chip.pic,
2282 sizeof(struct kvm_pic_state));
894a9c55 2283 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2284 break;
2285 case KVM_IRQCHIP_IOAPIC:
eba0226b 2286 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2287 break;
2288 default:
2289 r = -EINVAL;
2290 break;
2291 }
2292 kvm_pic_update_irq(pic_irqchip(kvm));
2293 return r;
2294}
2295
e0f63cb9
SY		 2296static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2297{
2298 int r = 0;
2299
894a9c55 2300 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2301 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2302 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2303 return r;
2304}
2305
2306static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2307{
2308 int r = 0;
2309
894a9c55 2310 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2311 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2312 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2313 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2314 return r;
2315}
2316
2317static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2318{
2319 int r = 0;
2320
2321 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2322 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2323 sizeof(ps->channels));
2324 ps->flags = kvm->arch.vpit->pit_state.flags;
2325 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2326 return r;
2327}
2328
2329static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2330{
2331 int r = 0, start = 0;
2332 u32 prev_legacy, cur_legacy;
2333 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2334 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2335 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2336 if (!prev_legacy && cur_legacy)
2337 start = 1;
2338 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2339 sizeof(kvm->arch.vpit->pit_state.channels));
2340 kvm->arch.vpit->pit_state.flags = ps->flags;
2341 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2342 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2343 return r;
2344}
2345
52d939a0
MT		 2346static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2347 struct kvm_reinject_control *control)
2348{
2349 if (!kvm->arch.vpit)
2350 return -ENXIO;
894a9c55 2351 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2352 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2353 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2354 return 0;
2355}
2356
5bb064dc
ZX		 2357/*
2358 * Get (and clear) the dirty memory log for a memory slot.
2359 */
2360int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2361 struct kvm_dirty_log *log)
2362{
2363 int r;
2364 int n;
2365 struct kvm_memory_slot *memslot;
2366 int is_dirty = 0;
2367
72dc67a6 2368 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2369
2370 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2371 if (r)
2372 goto out;
2373
2374 /* If nothing is dirty, don't bother messing with page tables. */
2375 if (is_dirty) {
7c8a83b7 2376 spin_lock(&kvm->mmu_lock);
5bb064dc 2377 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2378 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2379 memslot = &kvm->memslots[log->slot];
2380 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2381 memset(memslot->dirty_bitmap, 0, n);
2382 }
2383 r = 0;
2384out:
72dc67a6 2385 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2386 return r;
2387}
2388
1fe779f8
CO		 2389long kvm_arch_vm_ioctl(struct file *filp,
2390 unsigned int ioctl, unsigned long arg)
2391{
2392 struct kvm *kvm = filp->private_data;
2393 void __user *argp = (void __user *)arg;
367e1319 2394 int r = -ENOTTY;
f0d66275
DH		 2395 /*
2396 * This union makes it completely explicit to gcc-3.x
2397 * that these two variables' stack usage should be
2398 * combined, not added together.
2399 */
2400 union {
2401 struct kvm_pit_state ps;
e9f42757 2402 struct kvm_pit_state2 ps2;
f0d66275 2403 struct kvm_memory_alias alias;
c5ff41ce 2404 struct kvm_pit_config pit_config;
f0d66275 2405 } u;
1fe779f8
CO		 2406
2407 switch (ioctl) {
2408 case KVM_SET_TSS_ADDR:
2409 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2410 if (r < 0)
2411 goto out;
2412 break;
b927a3ce
SY		 2413 case KVM_SET_IDENTITY_MAP_ADDR: {
2414 u64 ident_addr;
2415
2416 r = -EFAULT;
2417 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2418 goto out;
2419 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2420 if (r < 0)
2421 goto out;
2422 break;
2423 }
1fe779f8
CO		 2424 case KVM_SET_MEMORY_REGION: {
2425 struct kvm_memory_region kvm_mem;
2426 struct kvm_userspace_memory_region kvm_userspace_mem;
2427
2428 r = -EFAULT;
2429 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2430 goto out;
2431 kvm_userspace_mem.slot = kvm_mem.slot;
2432 kvm_userspace_mem.flags = kvm_mem.flags;
2433 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2434 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2435 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2436 if (r)
2437 goto out;
2438 break;
2439 }
2440 case KVM_SET_NR_MMU_PAGES:
2441 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2442 if (r)
2443 goto out;
2444 break;
2445 case KVM_GET_NR_MMU_PAGES:
2446 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2447 break;
f0d66275 2448 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2449 r = -EFAULT;
f0d66275 2450 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2451 goto out;
f0d66275 2452 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2453 if (r)
2454 goto out;
2455 break;
3ddea128
MT		 2456 case KVM_CREATE_IRQCHIP: {
2457 struct kvm_pic *vpic;
2458
2459 mutex_lock(&kvm->lock);
2460 r = -EEXIST;
2461 if (kvm->arch.vpic)
2462 goto create_irqchip_unlock;
1fe779f8 2463 r = -ENOMEM;
3ddea128
MT		 2464 vpic = kvm_create_pic(kvm);
2465 if (vpic) {
1fe779f8
CO		 2466 r = kvm_ioapic_init(kvm);
2467 if (r) {
3ddea128
MT		 2468 kfree(vpic);
2469 goto create_irqchip_unlock;
1fe779f8
CO		 2470 }
2471 } else
3ddea128
MT		 2472 goto create_irqchip_unlock;
2473 smp_wmb();
2474 kvm->arch.vpic = vpic;
2475 smp_wmb();
399ec807
AK		 2476 r = kvm_setup_default_irq_routing(kvm);
2477 if (r) {
3ddea128 2478 mutex_lock(&kvm->irq_lock);
399ec807
AK		 2479 kfree(kvm->arch.vpic);
2480 kfree(kvm->arch.vioapic);
3ddea128
MT		 2481 kvm->arch.vpic = NULL;
2482 kvm->arch.vioapic = NULL;
2483 mutex_unlock(&kvm->irq_lock);
399ec807 2484 }
3ddea128
MT		 2485 create_irqchip_unlock:
2486 mutex_unlock(&kvm->lock);
1fe779f8 2487 break;
3ddea128 2488 }
7837699f 2489 case KVM_CREATE_PIT:
c5ff41ce
JK		 2490 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2491 goto create_pit;
2492 case KVM_CREATE_PIT2:
2493 r = -EFAULT;
2494 if (copy_from_user(&u.pit_config, argp,
2495 sizeof(struct kvm_pit_config)))
2496 goto out;
2497 create_pit:
108b5669 2498 down_write(&kvm->slots_lock);
269e05e4
AK		 2499 r = -EEXIST;
2500 if (kvm->arch.vpit)
2501 goto create_pit_unlock;
7837699f 2502 r = -ENOMEM;
c5ff41ce 2503 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2504 if (kvm->arch.vpit)
2505 r = 0;
269e05e4 2506 create_pit_unlock:
108b5669 2507 up_write(&kvm->slots_lock);
7837699f 2508 break;
4925663a 2509 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2510 case KVM_IRQ_LINE: {
2511 struct kvm_irq_level irq_event;
2512
2513 r = -EFAULT;
2514 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2515 goto out;
2516 if (irqchip_in_kernel(kvm)) {
4925663a 2517 __s32 status;
4925663a
GN		 2518 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2519 irq_event.irq, irq_event.level);
4925663a
GN		 2520 if (ioctl == KVM_IRQ_LINE_STATUS) {
2521 irq_event.status = status;
2522 if (copy_to_user(argp, &irq_event,
2523 sizeof irq_event))
2524 goto out;
2525 }
1fe779f8
CO		 2526 r = 0;
2527 }
2528 break;
2529 }
2530 case KVM_GET_IRQCHIP: {
2531 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2532 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2533
f0d66275
DH		 2534 r = -ENOMEM;
2535 if (!chip)
1fe779f8 2536 goto out;
f0d66275
DH		 2537 r = -EFAULT;
2538 if (copy_from_user(chip, argp, sizeof *chip))
2539 goto get_irqchip_out;
1fe779f8
CO		 2540 r = -ENXIO;
2541 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2542 goto get_irqchip_out;
2543 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2544 if (r)
f0d66275 2545 goto get_irqchip_out;
1fe779f8 2546 r = -EFAULT;
f0d66275
DH		 2547 if (copy_to_user(argp, chip, sizeof *chip))
2548 goto get_irqchip_out;
1fe779f8 2549 r = 0;
f0d66275
DH		 2550 get_irqchip_out:
2551 kfree(chip);
2552 if (r)
2553 goto out;
1fe779f8
CO		 2554 break;
2555 }
2556 case KVM_SET_IRQCHIP: {
2557 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2558 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2559
f0d66275
DH		 2560 r = -ENOMEM;
2561 if (!chip)
1fe779f8 2562 goto out;
f0d66275
DH		 2563 r = -EFAULT;
2564 if (copy_from_user(chip, argp, sizeof *chip))
2565 goto set_irqchip_out;
1fe779f8
CO		 2566 r = -ENXIO;
2567 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2568 goto set_irqchip_out;
2569 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2570 if (r)
f0d66275 2571 goto set_irqchip_out;
1fe779f8 2572 r = 0;
f0d66275
DH		 2573 set_irqchip_out:
2574 kfree(chip);
2575 if (r)
2576 goto out;
1fe779f8
CO		 2577 break;
2578 }
e0f63cb9 2579 case KVM_GET_PIT: {
e0f63cb9 2580 r = -EFAULT;
f0d66275 2581 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2582 goto out;
2583 r = -ENXIO;
2584 if (!kvm->arch.vpit)
2585 goto out;
f0d66275 2586 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2587 if (r)
2588 goto out;
2589 r = -EFAULT;
f0d66275 2590 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2591 goto out;
2592 r = 0;
2593 break;
2594 }
2595 case KVM_SET_PIT: {
e0f63cb9 2596 r = -EFAULT;
f0d66275 2597 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2598 goto out;
2599 r = -ENXIO;
2600 if (!kvm->arch.vpit)
2601 goto out;
f0d66275 2602 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2603 if (r)
2604 goto out;
2605 r = 0;
2606 break;
2607 }
e9f42757
BK		 2608 case KVM_GET_PIT2: {
2609 r = -ENXIO;
2610 if (!kvm->arch.vpit)
2611 goto out;
2612 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2613 if (r)
2614 goto out;
2615 r = -EFAULT;
2616 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2617 goto out;
2618 r = 0;
2619 break;
2620 }
2621 case KVM_SET_PIT2: {
2622 r = -EFAULT;
2623 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2624 goto out;
2625 r = -ENXIO;
2626 if (!kvm->arch.vpit)
2627 goto out;
2628 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2629 if (r)
2630 goto out;
2631 r = 0;
2632 break;
2633 }
52d939a0
MT		 2634 case KVM_REINJECT_CONTROL: {
2635 struct kvm_reinject_control control;
2636 r = -EFAULT;
2637 if (copy_from_user(&control, argp, sizeof(control)))
2638 goto out;
2639 r = kvm_vm_ioctl_reinject(kvm, &control);
2640 if (r)
2641 goto out;
2642 r = 0;
2643 break;
2644 }
ffde22ac
ES		 2645 case KVM_XEN_HVM_CONFIG: {
2646 r = -EFAULT;
2647 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2648 sizeof(struct kvm_xen_hvm_config)))
2649 goto out;
2650 r = -EINVAL;
2651 if (kvm->arch.xen_hvm_config.flags)
2652 goto out;
2653 r = 0;
2654 break;
2655 }
afbcf7ab
GC		 2656 case KVM_SET_CLOCK: {
2657 struct timespec now;
2658 struct kvm_clock_data user_ns;
2659 u64 now_ns;
2660 s64 delta;
2661
2662 r = -EFAULT;
2663 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2664 goto out;
2665
2666 r = -EINVAL;
2667 if (user_ns.flags)
2668 goto out;
2669
2670 r = 0;
2671 ktime_get_ts(&now);
2672 now_ns = timespec_to_ns(&now);
2673 delta = user_ns.clock - now_ns;
2674 kvm->arch.kvmclock_offset = delta;
2675 break;
2676 }
2677 case KVM_GET_CLOCK: {
2678 struct timespec now;
2679 struct kvm_clock_data user_ns;
2680 u64 now_ns;
2681
2682 ktime_get_ts(&now);
2683 now_ns = timespec_to_ns(&now);
2684 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2685 user_ns.flags = 0;
2686
2687 r = -EFAULT;
2688 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2689 goto out;
2690 r = 0;
2691 break;
2692 }
2693
1fe779f8
CO		 2694 default:
2695 ;
2696 }
2697out:
2698 return r;
2699}
2700
a16b043c 2701static void kvm_init_msr_list(void)
043405e1
CO		 2702{
2703 u32 dummy[2];
2704 unsigned i, j;
2705
e3267cbb
GC		 2706 /* skip the first msrs in the list. KVM-specific */
2707 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2708 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2709 continue;
2710 if (j < i)
2711 msrs_to_save[j] = msrs_to_save[i];
2712 j++;
2713 }
2714 num_msrs_to_save = j;
2715}
2716
bda9020e
MT		 2717static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2718 const void *v)
bbd9b64e 2719{
bda9020e
MT		 2720 if (vcpu->arch.apic &&
2721 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2722 return 0;
bbd9b64e 2723
bda9020e 2724 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2725}
2726
bda9020e 2727static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2728{
bda9020e
MT		 2729 if (vcpu->arch.apic &&
2730 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2731 return 0;
bbd9b64e 2732
bda9020e 2733 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2734}
2735
cded19f3
HE		 2736static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2737 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2738{
2739 void *data = val;
10589a46 2740 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2741
2742 while (bytes) {
ad312c7c 2743 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2744 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2745 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2746 int ret;
2747
10589a46
MT		 2748 if (gpa == UNMAPPED_GVA) {
2749 r = X86EMUL_PROPAGATE_FAULT;
2750 goto out;
2751 }
77c2002e 2752 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2753 if (ret < 0) {
2754 r = X86EMUL_UNHANDLEABLE;
2755 goto out;
2756 }
bbd9b64e 2757
77c2002e
IE		 2758 bytes -= toread;
2759 data += toread;
2760 addr += toread;
bbd9b64e 2761 }
10589a46 2762out:
10589a46 2763 return r;
bbd9b64e 2764}
77c2002e 2765
cded19f3
HE		 2766static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2767 struct kvm_vcpu *vcpu)
77c2002e
IE		 2768{
2769 void *data = val;
2770 int r = X86EMUL_CONTINUE;
2771
2772 while (bytes) {
2773 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2774 unsigned offset = addr & (PAGE_SIZE-1);
2775 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2776 int ret;
2777
2778 if (gpa == UNMAPPED_GVA) {
2779 r = X86EMUL_PROPAGATE_FAULT;
2780 goto out;
2781 }
2782 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2783 if (ret < 0) {
2784 r = X86EMUL_UNHANDLEABLE;
2785 goto out;
2786 }
2787
2788 bytes -= towrite;
2789 data += towrite;
2790 addr += towrite;
2791 }
2792out:
2793 return r;
2794}
2795
bbd9b64e 2796
bbd9b64e
CO		 2797static int emulator_read_emulated(unsigned long addr,
2798 void *val,
2799 unsigned int bytes,
2800 struct kvm_vcpu *vcpu)
2801{
bbd9b64e
CO		 2802 gpa_t gpa;
2803
2804 if (vcpu->mmio_read_completed) {
2805 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2806 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2807 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2808 vcpu->mmio_read_completed = 0;
2809 return X86EMUL_CONTINUE;
2810 }
2811
ad312c7c 2812 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2813
2814 /* For APIC access vmexit */
2815 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2816 goto mmio;
2817
77c2002e
IE		 2818 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2819 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2820 return X86EMUL_CONTINUE;
2821 if (gpa == UNMAPPED_GVA)
2822 return X86EMUL_PROPAGATE_FAULT;
2823
2824mmio:
2825 /*
2826 * Is this MMIO handled locally?
2827 */
aec51dc4
AK		 2828 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2829 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2830 return X86EMUL_CONTINUE;
2831 }
aec51dc4
AK		 2832
2833 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2834
2835 vcpu->mmio_needed = 1;
2836 vcpu->mmio_phys_addr = gpa;
2837 vcpu->mmio_size = bytes;
2838 vcpu->mmio_is_write = 0;
2839
2840 return X86EMUL_UNHANDLEABLE;
2841}
2842
3200f405 2843int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2844 const void *val, int bytes)
bbd9b64e
CO		 2845{
2846 int ret;
2847
2848 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2849 if (ret < 0)
bbd9b64e 2850 return 0;
ad218f85 2851 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2852 return 1;
2853}
2854
2855static int emulator_write_emulated_onepage(unsigned long addr,
2856 const void *val,
2857 unsigned int bytes,
2858 struct kvm_vcpu *vcpu)
2859{
10589a46
MT		 2860 gpa_t gpa;
2861
10589a46 2862 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2863
2864 if (gpa == UNMAPPED_GVA) {
c3c91fee 2865 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2866 return X86EMUL_PROPAGATE_FAULT;
2867 }
2868
2869 /* For APIC access vmexit */
2870 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2871 goto mmio;
2872
2873 if (emulator_write_phys(vcpu, gpa, val, bytes))
2874 return X86EMUL_CONTINUE;
2875
2876mmio:
aec51dc4 2877 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2878 /*
2879 * Is this MMIO handled locally?
2880 */
bda9020e 2881 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2882 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2883
2884 vcpu->mmio_needed = 1;
2885 vcpu->mmio_phys_addr = gpa;
2886 vcpu->mmio_size = bytes;
2887 vcpu->mmio_is_write = 1;
2888 memcpy(vcpu->mmio_data, val, bytes);
2889
2890 return X86EMUL_CONTINUE;
2891}
2892
2893int emulator_write_emulated(unsigned long addr,
2894 const void *val,
2895 unsigned int bytes,
2896 struct kvm_vcpu *vcpu)
2897{
2898 /* Crossing a page boundary? */
2899 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2900 int rc, now;
2901
2902 now = -addr & ~PAGE_MASK;
2903 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2904 if (rc != X86EMUL_CONTINUE)
2905 return rc;
2906 addr += now;
2907 val += now;
2908 bytes -= now;
2909 }
2910 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2911}
2912EXPORT_SYMBOL_GPL(emulator_write_emulated);
2913
2914static int emulator_cmpxchg_emulated(unsigned long addr,
2915 const void *old,
2916 const void *new,
2917 unsigned int bytes,
2918 struct kvm_vcpu *vcpu)
2919{
9f51e24e 2920 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 2921#ifndef CONFIG_X86_64
2922 /* guests cmpxchg8b have to be emulated atomically */
2923 if (bytes == 8) {
10589a46 2924 gpa_t gpa;
2bacc55c 2925 struct page *page;
c0b49b0d 2926 char *kaddr;
2bacc55c
MT		 2927 u64 val;
2928
10589a46
MT		 2929 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2930
2bacc55c
MT		 2931 if (gpa == UNMAPPED_GVA ||
2932 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2933 goto emul_write;
2934
2935 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2936 goto emul_write;
2937
2938 val = *(u64 *)new;
72dc67a6 2939
2bacc55c 2940 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2941
c0b49b0d
AM		 2942 kaddr = kmap_atomic(page, KM_USER0);
2943 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2944 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2945 kvm_release_page_dirty(page);
2946 }
3200f405 2947emul_write:
2bacc55c
MT		 2948#endif
2949
bbd9b64e
CO		 2950 return emulator_write_emulated(addr, new, bytes, vcpu);
2951}
2952
2953static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2954{
2955 return kvm_x86_ops->get_segment_base(vcpu, seg);
2956}
2957
2958int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2959{
a7052897 2960 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2961 return X86EMUL_CONTINUE;
2962}
2963
2964int emulate_clts(struct kvm_vcpu *vcpu)
2965{
ad312c7c 2966 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2967 return X86EMUL_CONTINUE;
2968}
2969
2970int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2971{
2972 struct kvm_vcpu *vcpu = ctxt->vcpu;
2973
2974 switch (dr) {
2975 case 0 ... 3:
2976 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2977 return X86EMUL_CONTINUE;
2978 default:
b8688d51 2979 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2980 return X86EMUL_UNHANDLEABLE;
2981 }
2982}
2983
2984int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2985{
2986 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2987 int exception;
2988
2989 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2990 if (exception) {
2991 /* FIXME: better handling */
2992 return X86EMUL_UNHANDLEABLE;
2993 }
2994 return X86EMUL_CONTINUE;
2995}
2996
2997void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2998{
bbd9b64e 2999 u8 opcodes[4];
5fdbf976 3000 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3001 unsigned long rip_linear;
3002
f76c710d 3003 if (!printk_ratelimit())
bbd9b64e
CO		 3004 return;
3005
25be4608
GC		 3006 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3007
77c2002e 3008 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 3009
3010 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3011 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3012}
3013EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3014
14af3f3c 3015static struct x86_emulate_ops emulate_ops = {
77c2002e 3016 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 3017 .read_emulated = emulator_read_emulated,
3018 .write_emulated = emulator_write_emulated,
3019 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3020};
3021
5fdbf976
MT		 3022static void cache_all_regs(struct kvm_vcpu *vcpu)
3023{
3024 kvm_register_read(vcpu, VCPU_REGS_RAX);
3025 kvm_register_read(vcpu, VCPU_REGS_RSP);
3026 kvm_register_read(vcpu, VCPU_REGS_RIP);
3027 vcpu->arch.regs_dirty = ~0;
3028}
3029
bbd9b64e 3030int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3031 unsigned long cr2,
3032 u16 error_code,
571008da 3033 int emulation_type)
bbd9b64e 3034{
310b5d30 3035 int r, shadow_mask;
571008da 3036 struct decode_cache *c;
851ba692 3037 struct kvm_run *run = vcpu->run;
bbd9b64e 3038
26eef70c 3039 kvm_clear_exception_queue(vcpu);
ad312c7c 3040 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3041 /*
56e82318 3042 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3043 * instead of direct ->regs accesses, can save hundred cycles
3044 * on Intel for instructions that don't read/change RSP, for
3045 * for example.
3046 */
3047 cache_all_regs(vcpu);
bbd9b64e
CO		 3048
3049 vcpu->mmio_is_write = 0;
ad312c7c 3050 vcpu->arch.pio.string = 0;
bbd9b64e 3051
571008da 3052 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3053 int cs_db, cs_l;
3054 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3055
ad312c7c 3056 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3057 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c
ZX		 3058 vcpu->arch.emulate_ctxt.mode =
3059 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 3060 ? X86EMUL_MODE_REAL : cs_l
3061 ? X86EMUL_MODE_PROT64 : cs_db
3062 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3063
ad312c7c 3064 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3065
0cb5762e
AP		 3066 /* Only allow emulation of specific instructions on #UD
3067 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3068 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3069 if (emulation_type & EMULTYPE_TRAP_UD) {
3070 if (!c->twobyte)
3071 return EMULATE_FAIL;
3072 switch (c->b) {
3073 case 0x01: /* VMMCALL */
3074 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3075 return EMULATE_FAIL;
3076 break;
3077 case 0x34: /* sysenter */
3078 case 0x35: /* sysexit */
3079 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3080 return EMULATE_FAIL;
3081 break;
3082 case 0x05: /* syscall */
3083 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3084 return EMULATE_FAIL;
3085 break;
3086 default:
3087 return EMULATE_FAIL;
3088 }
3089
3090 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3091 return EMULATE_FAIL;
3092 }
571008da 3093
f2b5756b 3094 ++vcpu->stat.insn_emulation;
bbd9b64e 3095 if (r) {
f2b5756b 3096 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3097 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3098 return EMULATE_DONE;
3099 return EMULATE_FAIL;
3100 }
3101 }
3102
ba8afb6b
GN		 3103 if (emulation_type & EMULTYPE_SKIP) {
3104 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3105 return EMULATE_DONE;
3106 }
3107
ad312c7c 3108 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3109 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3110
3111 if (r == 0)
3112 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3113
ad312c7c 3114 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3115 return EMULATE_DO_MMIO;
3116
3117 if ((r || vcpu->mmio_is_write) && run) {
3118 run->exit_reason = KVM_EXIT_MMIO;
3119 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3120 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3121 run->mmio.len = vcpu->mmio_size;
3122 run->mmio.is_write = vcpu->mmio_is_write;
3123 }
3124
3125 if (r) {
3126 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3127 return EMULATE_DONE;
3128 if (!vcpu->mmio_needed) {
3129 kvm_report_emulation_failure(vcpu, "mmio");
3130 return EMULATE_FAIL;
3131 }
3132 return EMULATE_DO_MMIO;
3133 }
3134
91586a3b 3135 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3136
3137 if (vcpu->mmio_is_write) {
3138 vcpu->mmio_needed = 0;
3139 return EMULATE_DO_MMIO;
3140 }
3141
3142 return EMULATE_DONE;
3143}
3144EXPORT_SYMBOL_GPL(emulate_instruction);
3145
de7d789a
CO		 3146static int pio_copy_data(struct kvm_vcpu *vcpu)
3147{
ad312c7c 3148 void *p = vcpu->arch.pio_data;
0f346074 3149 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3150 unsigned bytes;
0f346074 3151 int ret;
de7d789a 3152
ad312c7c
ZX		 3153 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3154 if (vcpu->arch.pio.in)
0f346074 3155 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 3156 else
0f346074
IE		 3157 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
3158 return ret;
de7d789a
CO		 3159}
3160
3161int complete_pio(struct kvm_vcpu *vcpu)
3162{
ad312c7c 3163 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3164 long delta;
3165 int r;
5fdbf976 3166 unsigned long val;
de7d789a
CO		 3167
3168 if (!io->string) {
5fdbf976
MT		 3169 if (io->in) {
3170 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3171 memcpy(&val, vcpu->arch.pio_data, io->size);
3172 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3173 }
de7d789a
CO		 3174 } else {
3175 if (io->in) {
3176 r = pio_copy_data(vcpu);
5fdbf976 3177 if (r)
de7d789a 3178 return r;
de7d789a
CO		 3179 }
3180
3181 delta = 1;
3182 if (io->rep) {
3183 delta *= io->cur_count;
3184 /*
3185 * The size of the register should really depend on
3186 * current address size.
3187 */
5fdbf976
MT		 3188 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3189 val -= delta;
3190 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3191 }
3192 if (io->down)
3193 delta = -delta;
3194 delta *= io->size;
5fdbf976
MT		 3195 if (io->in) {
3196 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3197 val += delta;
3198 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3199 } else {
3200 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3201 val += delta;
3202 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3203 }
de7d789a
CO		 3204 }
3205
de7d789a
CO		 3206 io->count -= io->cur_count;
3207 io->cur_count = 0;
3208
3209 return 0;
3210}
3211
bda9020e 3212static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3213{
3214 /* TODO: String I/O for in kernel device */
bda9020e 3215 int r;
de7d789a 3216
ad312c7c 3217 if (vcpu->arch.pio.in)
bda9020e
MT		 3218 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
3219 vcpu->arch.pio.size, pd);
de7d789a 3220 else
bda9020e
MT		 3221 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
3222 vcpu->arch.pio.size, pd);
3223 return r;
de7d789a
CO		 3224}
3225
bda9020e 3226static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3227{
ad312c7c
ZX		 3228 struct kvm_pio_request *io = &vcpu->arch.pio;
3229 void *pd = vcpu->arch.pio_data;
bda9020e 3230 int i, r = 0;
de7d789a 3231
de7d789a 3232 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 3233 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
3234 io->port, io->size, pd)) {
3235 r = -EOPNOTSUPP;
3236 break;
3237 }
de7d789a
CO		 3238 pd += io->size;
3239 }
bda9020e 3240 return r;
de7d789a
CO		 3241}
3242
851ba692 3243int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3244{
5fdbf976 3245 unsigned long val;
de7d789a
CO		 3246
3247 vcpu->run->exit_reason = KVM_EXIT_IO;
3248 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3249 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3250 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3251 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3252 vcpu->run->io.port = vcpu->arch.pio.port = port;
3253 vcpu->arch.pio.in = in;
3254 vcpu->arch.pio.string = 0;
3255 vcpu->arch.pio.down = 0;
ad312c7c 3256 vcpu->arch.pio.rep = 0;
de7d789a 3257
229456fc
MT		 3258 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3259 size, 1);
2714d1d3 3260
5fdbf976
MT		 3261 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3262 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 3263
bda9020e 3264 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3265 complete_pio(vcpu);
3266 return 1;
3267 }
3268 return 0;
3269}
3270EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3271
851ba692 3272int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3273 int size, unsigned long count, int down,
3274 gva_t address, int rep, unsigned port)
3275{
3276 unsigned now, in_page;
0f346074 3277 int ret = 0;
de7d789a
CO		 3278
3279 vcpu->run->exit_reason = KVM_EXIT_IO;
3280 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3281 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3282 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3283 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3284 vcpu->run->io.port = vcpu->arch.pio.port = port;
3285 vcpu->arch.pio.in = in;
3286 vcpu->arch.pio.string = 1;
3287 vcpu->arch.pio.down = down;
ad312c7c 3288 vcpu->arch.pio.rep = rep;
de7d789a 3289
229456fc
MT		 3290 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3291 size, count);
2714d1d3 3292
de7d789a
CO		 3293 if (!count) {
3294 kvm_x86_ops->skip_emulated_instruction(vcpu);
3295 return 1;
3296 }
3297
3298 if (!down)
3299 in_page = PAGE_SIZE - offset_in_page(address);
3300 else
3301 in_page = offset_in_page(address) + size;
3302 now = min(count, (unsigned long)in_page / size);
0f346074 3303 if (!now)
de7d789a 3304 now = 1;
de7d789a
CO		 3305 if (down) {
3306 /*
3307 * String I/O in reverse. Yuck. Kill the guest, fix later.
3308 */
3309 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3310 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3311 return 1;
3312 }
3313 vcpu->run->io.count = now;
ad312c7c 3314 vcpu->arch.pio.cur_count = now;
de7d789a 3315
ad312c7c 3316 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3317 kvm_x86_ops->skip_emulated_instruction(vcpu);
3318
0f346074 3319 vcpu->arch.pio.guest_gva = address;
de7d789a 3320
ad312c7c 3321 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3322 /* string PIO write */
3323 ret = pio_copy_data(vcpu);
0f346074
IE		 3324 if (ret == X86EMUL_PROPAGATE_FAULT) {
3325 kvm_inject_gp(vcpu, 0);
3326 return 1;
3327 }
bda9020e 3328 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3329 complete_pio(vcpu);
ad312c7c 3330 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3331 ret = 1;
3332 }
bda9020e
MT		 3333 }
3334 /* no string PIO read support yet */
de7d789a
CO		 3335
3336 return ret;
3337}
3338EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3339
c8076604
GH		 3340static void bounce_off(void *info)
3341{
3342 /* nothing */
3343}
3344
c8076604
GH		 3345static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3346 void *data)
3347{
3348 struct cpufreq_freqs *freq = data;
3349 struct kvm *kvm;
3350 struct kvm_vcpu *vcpu;
3351 int i, send_ipi = 0;
3352
c8076604
GH		 3353 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3354 return 0;
3355 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3356 return 0;
0cca7907 3357 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3358
3359 spin_lock(&kvm_lock);
3360 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3361 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3362 if (vcpu->cpu != freq->cpu)
3363 continue;
3364 if (!kvm_request_guest_time_update(vcpu))
3365 continue;
3366 if (vcpu->cpu != smp_processor_id())
3367 send_ipi++;
3368 }
3369 }
3370 spin_unlock(&kvm_lock);
3371
3372 if (freq->old < freq->new && send_ipi) {
3373 /*
3374 * We upscale the frequency. Must make the guest
3375 * doesn't see old kvmclock values while running with
3376 * the new frequency, otherwise we risk the guest sees
3377 * time go backwards.
3378 *
3379 * In case we update the frequency for another cpu
3380 * (which might be in guest context) send an interrupt
3381 * to kick the cpu out of guest context. Next time
3382 * guest context is entered kvmclock will be updated,
3383 * so the guest will not see stale values.
3384 */
3385 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3386 }
3387 return 0;
3388}
3389
3390static struct notifier_block kvmclock_cpufreq_notifier_block = {
3391 .notifier_call = kvmclock_cpufreq_notifier
3392};
3393
b820cc0c
ZA		 3394static void kvm_timer_init(void)
3395{
3396 int cpu;
3397
b820cc0c 3398 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3399 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3400 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3401 for_each_online_cpu(cpu) {
3402 unsigned long khz = cpufreq_get(cpu);
3403 if (!khz)
3404 khz = tsc_khz;
3405 per_cpu(cpu_tsc_khz, cpu) = khz;
3406 }
0cca7907
ZA		 3407 } else {
3408 for_each_possible_cpu(cpu)
3409 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3410 }
3411}
3412
f8c16bba 3413int kvm_arch_init(void *opaque)
043405e1 3414{
b820cc0c 3415 int r;
f8c16bba
ZX		 3416 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3417
f8c16bba
ZX		 3418 if (kvm_x86_ops) {
3419 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3420 r = -EEXIST;
3421 goto out;
f8c16bba
ZX		 3422 }
3423
3424 if (!ops->cpu_has_kvm_support()) {
3425 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3426 r = -EOPNOTSUPP;
3427 goto out;
f8c16bba
ZX		 3428 }
3429 if (ops->disabled_by_bios()) {
3430 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3431 r = -EOPNOTSUPP;
3432 goto out;
f8c16bba
ZX		 3433 }
3434
97db56ce
AK		 3435 r = kvm_mmu_module_init();
3436 if (r)
3437 goto out;
3438
3439 kvm_init_msr_list();
3440
f8c16bba 3441 kvm_x86_ops = ops;
56c6d28a 3442 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3443 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3444 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3445 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3446
b820cc0c 3447 kvm_timer_init();
c8076604 3448
f8c16bba 3449 return 0;
56c6d28a
ZX		 3450
3451out:
56c6d28a 3452 return r;
043405e1 3453}
8776e519 3454
f8c16bba
ZX		 3455void kvm_arch_exit(void)
3456{
888d256e
JK		 3457 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3458 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3459 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3460 kvm_x86_ops = NULL;
56c6d28a
ZX		 3461 kvm_mmu_module_exit();
3462}
f8c16bba 3463
8776e519
HB		 3464int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3465{
3466 ++vcpu->stat.halt_exits;
3467 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3468 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3469 return 1;
3470 } else {
3471 vcpu->run->exit_reason = KVM_EXIT_HLT;
3472 return 0;
3473 }
3474}
3475EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3476
2f333bcb
MT		 3477static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3478 unsigned long a1)
3479{
3480 if (is_long_mode(vcpu))
3481 return a0;
3482 else
3483 return a0 | ((gpa_t)a1 << 32);
3484}
3485
8776e519
HB		 3486int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3487{
3488 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3489 int r = 1;
8776e519 3490
5fdbf976
MT		 3491 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3492 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3493 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3494 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3495 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3496
229456fc 3497 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3498
8776e519
HB		 3499 if (!is_long_mode(vcpu)) {
3500 nr &= 0xFFFFFFFF;
3501 a0 &= 0xFFFFFFFF;
3502 a1 &= 0xFFFFFFFF;
3503 a2 &= 0xFFFFFFFF;
3504 a3 &= 0xFFFFFFFF;
3505 }
3506
07708c4a
JK		 3507 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3508 ret = -KVM_EPERM;
3509 goto out;
3510 }
3511
8776e519 3512 switch (nr) {
b93463aa
AK		 3513 case KVM_HC_VAPIC_POLL_IRQ:
3514 ret = 0;
3515 break;
2f333bcb
MT		 3516 case KVM_HC_MMU_OP:
3517 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3518 break;
8776e519
HB		 3519 default:
3520 ret = -KVM_ENOSYS;
3521 break;
3522 }
07708c4a 3523out:
5fdbf976 3524 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3525 ++vcpu->stat.hypercalls;
2f333bcb 3526 return r;
8776e519
HB		 3527}
3528EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3529
3530int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3531{
3532 char instruction[3];
3533 int ret = 0;
5fdbf976 3534 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3535
8776e519
HB		 3536
3537 /*
3538 * Blow out the MMU to ensure that no other VCPU has an active mapping
3539 * to ensure that the updated hypercall appears atomically across all
3540 * VCPUs.
3541 */
3542 kvm_mmu_zap_all(vcpu->kvm);
3543
8776e519 3544 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3545 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3546 != X86EMUL_CONTINUE)
3547 ret = -EFAULT;
3548
8776e519
HB		 3549 return ret;
3550}
3551
3552static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3553{
3554 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3555}
3556
3557void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3558{
3559 struct descriptor_table dt = { limit, base };
3560
3561 kvm_x86_ops->set_gdt(vcpu, &dt);
3562}
3563
3564void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3565{
3566 struct descriptor_table dt = { limit, base };
3567
3568 kvm_x86_ops->set_idt(vcpu, &dt);
3569}
3570
3571void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3572 unsigned long *rflags)
3573{
2d3ad1f4 3574 kvm_lmsw(vcpu, msw);
91586a3b 3575 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3576}
3577
3578unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3579{
54e445ca
JR		 3580 unsigned long value;
3581
8776e519
HB		 3582 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3583 switch (cr) {
3584 case 0:
54e445ca
JR		 3585 value = vcpu->arch.cr0;
3586 break;
8776e519 3587 case 2:
54e445ca
JR		 3588 value = vcpu->arch.cr2;
3589 break;
8776e519 3590 case 3:
54e445ca
JR		 3591 value = vcpu->arch.cr3;
3592 break;
8776e519 3593 case 4:
54e445ca
JR		 3594 value = vcpu->arch.cr4;
3595 break;
152ff9be 3596 case 8:
54e445ca
JR		 3597 value = kvm_get_cr8(vcpu);
3598 break;
8776e519 3599 default:
b8688d51 3600 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3601 return 0;
3602 }
54e445ca
JR		 3603
3604 return value;
8776e519
HB		 3605}
3606
3607void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3608 unsigned long *rflags)
3609{
3610 switch (cr) {
3611 case 0:
2d3ad1f4 3612 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
91586a3b 3613 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3614 break;
3615 case 2:
ad312c7c 3616 vcpu->arch.cr2 = val;
8776e519
HB		 3617 break;
3618 case 3:
2d3ad1f4 3619 kvm_set_cr3(vcpu, val);
8776e519
HB		 3620 break;
3621 case 4:
2d3ad1f4 3622 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3623 break;
152ff9be 3624 case 8:
2d3ad1f4 3625 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3626 break;
8776e519 3627 default:
b8688d51 3628 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3629 }
3630}
3631
07716717
DK		 3632static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3633{
ad312c7c
ZX		 3634 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3635 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3636
3637 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3638 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3639 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3640 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3641 if (ej->function == e->function) {
3642 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3643 return j;
3644 }
3645 }
3646 return 0; /* silence gcc, even though control never reaches here */
3647}
3648
3649/* find an entry with matching function, matching index (if needed), and that
3650 * should be read next (if it's stateful) */
3651static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3652 u32 function, u32 index)
3653{
3654 if (e->function != function)
3655 return 0;
3656 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3657 return 0;
3658 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3659 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3660 return 0;
3661 return 1;
3662}
3663
d8017474
AG		 3664struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3665 u32 function, u32 index)
8776e519
HB		 3666{
3667 int i;
d8017474 3668 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3669
ad312c7c 3670 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3671 struct kvm_cpuid_entry2 *e;
3672
ad312c7c 3673 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3674 if (is_matching_cpuid_entry(e, function, index)) {
3675 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3676 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3677 best = e;
3678 break;
3679 }
3680 /*
3681 * Both basic or both extended?
3682 */
3683 if (((e->function ^ function) & 0x80000000) == 0)
3684 if (!best || e->function > best->function)
3685 best = e;
3686 }
d8017474
AG		 3687 return best;
3688}
3689
82725b20
DE		 3690int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3691{
3692 struct kvm_cpuid_entry2 *best;
3693
3694 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3695 if (best)
3696 return best->eax & 0xff;
3697 return 36;
3698}
3699
d8017474
AG		 3700void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3701{
3702 u32 function, index;
3703 struct kvm_cpuid_entry2 *best;
3704
3705 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3706 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3707 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3708 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3709 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3710 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3711 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3712 if (best) {
5fdbf976
MT		 3713 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3714 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3715 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3716 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3717 }
8776e519 3718 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3719 trace_kvm_cpuid(function,
3720 kvm_register_read(vcpu, VCPU_REGS_RAX),
3721 kvm_register_read(vcpu, VCPU_REGS_RBX),
3722 kvm_register_read(vcpu, VCPU_REGS_RCX),
3723 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3724}
3725EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3726
b6c7a5dc
HB		 3727/*
3728 * Check if userspace requested an interrupt window, and that the
3729 * interrupt window is open.
3730 *
3731 * No need to exit to userspace if we already have an interrupt queued.
3732 */
851ba692 3733static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 3734{
8061823a 3735 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 3736 vcpu->run->request_interrupt_window &&
5df56646 3737 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3738}
3739
851ba692 3740static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 3741{
851ba692
AK		 3742 struct kvm_run *kvm_run = vcpu->run;
3743
91586a3b 3744 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3745 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3746 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3747 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3748 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3749 else
b6c7a5dc 3750 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3751 kvm_arch_interrupt_allowed(vcpu) &&
3752 !kvm_cpu_has_interrupt(vcpu) &&
3753 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3754}
3755
b93463aa
AK		 3756static void vapic_enter(struct kvm_vcpu *vcpu)
3757{
3758 struct kvm_lapic *apic = vcpu->arch.apic;
3759 struct page *page;
3760
3761 if (!apic || !apic->vapic_addr)
3762 return;
3763
3764 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3765
3766 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3767}
3768
3769static void vapic_exit(struct kvm_vcpu *vcpu)
3770{
3771 struct kvm_lapic *apic = vcpu->arch.apic;
3772
3773 if (!apic || !apic->vapic_addr)
3774 return;
3775
f8b78fa3 3776 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3777 kvm_release_page_dirty(apic->vapic_page);
3778 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3779 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3780}
3781
95ba8273
GN		 3782static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3783{
3784 int max_irr, tpr;
3785
3786 if (!kvm_x86_ops->update_cr8_intercept)
3787 return;
3788
88c808fd
AK		 3789 if (!vcpu->arch.apic)
3790 return;
3791
8db3baa2
GN		 3792 if (!vcpu->arch.apic->vapic_addr)
3793 max_irr = kvm_lapic_find_highest_irr(vcpu);
3794 else
3795 max_irr = -1;
95ba8273
GN		 3796
3797 if (max_irr != -1)
3798 max_irr >>= 4;
3799
3800 tpr = kvm_lapic_get_cr8(vcpu);
3801
3802 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3803}
3804
851ba692 3805static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 3806{
3807 /* try to reinject previous events if any */
b59bb7bd
GN		 3808 if (vcpu->arch.exception.pending) {
3809 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3810 vcpu->arch.exception.has_error_code,
3811 vcpu->arch.exception.error_code);
3812 return;
3813 }
3814
95ba8273
GN		 3815 if (vcpu->arch.nmi_injected) {
3816 kvm_x86_ops->set_nmi(vcpu);
3817 return;
3818 }
3819
3820 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3821 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3822 return;
3823 }
3824
3825 /* try to inject new event if pending */
3826 if (vcpu->arch.nmi_pending) {
3827 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3828 vcpu->arch.nmi_pending = false;
3829 vcpu->arch.nmi_injected = true;
3830 kvm_x86_ops->set_nmi(vcpu);
3831 }
3832 } else if (kvm_cpu_has_interrupt(vcpu)) {
3833 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3834 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3835 false);
3836 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3837 }
3838 }
3839}
3840
851ba692 3841static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 3842{
3843 int r;
6a8b1d13 3844 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 3845 vcpu->run->request_interrupt_window;
b6c7a5dc 3846
2e53d63a
MT		 3847 if (vcpu->requests)
3848 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3849 kvm_mmu_unload(vcpu);
3850
b6c7a5dc
HB		 3851 r = kvm_mmu_reload(vcpu);
3852 if (unlikely(r))
3853 goto out;
3854
2f52d58c
AK		 3855 if (vcpu->requests) {
3856 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3857 __kvm_migrate_timers(vcpu);
c8076604
GH		 3858 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3859 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3860 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3861 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3862 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3863 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3864 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3865 &vcpu->requests)) {
851ba692 3866 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 3867 r = 0;
3868 goto out;
3869 }
71c4dfaf 3870 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 3871 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 3872 r = 0;
3873 goto out;
3874 }
2f52d58c 3875 }
b93463aa 3876
b6c7a5dc
HB		 3877 preempt_disable();
3878
3879 kvm_x86_ops->prepare_guest_switch(vcpu);
3880 kvm_load_guest_fpu(vcpu);
3881
3882 local_irq_disable();
3883
32f88400
MT		 3884 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3885 smp_mb__after_clear_bit();
3886
d7690175 3887 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3888 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3889 local_irq_enable();
3890 preempt_enable();
3891 r = 1;
3892 goto out;
3893 }
3894
851ba692 3895 inject_pending_event(vcpu);
b6c7a5dc 3896
6a8b1d13
GN		 3897 /* enable NMI/IRQ window open exits if needed */
3898 if (vcpu->arch.nmi_pending)
3899 kvm_x86_ops->enable_nmi_window(vcpu);
3900 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3901 kvm_x86_ops->enable_irq_window(vcpu);
3902
95ba8273 3903 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3904 update_cr8_intercept(vcpu);
3905 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3906 }
b93463aa 3907
3200f405
MT		 3908 up_read(&vcpu->kvm->slots_lock);
3909
b6c7a5dc
HB		 3910 kvm_guest_enter();
3911
42dbaa5a 3912 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 3913 set_debugreg(0, 7);
3914 set_debugreg(vcpu->arch.eff_db[0], 0);
3915 set_debugreg(vcpu->arch.eff_db[1], 1);
3916 set_debugreg(vcpu->arch.eff_db[2], 2);
3917 set_debugreg(vcpu->arch.eff_db[3], 3);
3918 }
b6c7a5dc 3919
229456fc 3920 trace_kvm_entry(vcpu->vcpu_id);
851ba692 3921 kvm_x86_ops->run(vcpu);
b6c7a5dc 3922
3d53c27d
AK		 3923 if (unlikely(vcpu->arch.switch_db_regs || test_thread_flag(TIF_DEBUG))) {
3924 set_debugreg(current->thread.debugreg0, 0);
3925 set_debugreg(current->thread.debugreg1, 1);
3926 set_debugreg(current->thread.debugreg2, 2);
3927 set_debugreg(current->thread.debugreg3, 3);
3928 set_debugreg(current->thread.debugreg6, 6);
3929 set_debugreg(current->thread.debugreg7, 7);
42dbaa5a 3930 }
42dbaa5a 3931
32f88400 3932 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3933 local_irq_enable();
3934
3935 ++vcpu->stat.exits;
3936
3937 /*
3938 * We must have an instruction between local_irq_enable() and
3939 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3940 * the interrupt shadow. The stat.exits increment will do nicely.
3941 * But we need to prevent reordering, hence this barrier():
3942 */
3943 barrier();
3944
3945 kvm_guest_exit();
3946
3947 preempt_enable();
3948
3200f405
MT		 3949 down_read(&vcpu->kvm->slots_lock);
3950
b6c7a5dc
HB		 3951 /*
3952 * Profile KVM exit RIPs:
3953 */
3954 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3955 unsigned long rip = kvm_rip_read(vcpu);
3956 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3957 }
3958
298101da 3959
b93463aa
AK		 3960 kvm_lapic_sync_from_vapic(vcpu);
3961
851ba692 3962 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 3963out:
3964 return r;
3965}
b6c7a5dc 3966
09cec754 3967
851ba692 3968static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 3969{
3970 int r;
3971
3972 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3973 pr_debug("vcpu %d received sipi with vector # %x\n",
3974 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3975 kvm_lapic_reset(vcpu);
5f179287 3976 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3977 if (r)
3978 return r;
3979 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3980 }
3981
d7690175
MT		 3982 down_read(&vcpu->kvm->slots_lock);
3983 vapic_enter(vcpu);
3984
3985 r = 1;
3986 while (r > 0) {
af2152f5 3987 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 3988 r = vcpu_enter_guest(vcpu);
d7690175
MT		 3989 else {
3990 up_read(&vcpu->kvm->slots_lock);
3991 kvm_vcpu_block(vcpu);
3992 down_read(&vcpu->kvm->slots_lock);
3993 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3994 {
3995 switch(vcpu->arch.mp_state) {
3996 case KVM_MP_STATE_HALTED:
d7690175 3997 vcpu->arch.mp_state =
09cec754
GN		 3998 KVM_MP_STATE_RUNNABLE;
3999 case KVM_MP_STATE_RUNNABLE:
4000 break;
4001 case KVM_MP_STATE_SIPI_RECEIVED:
4002 default:
4003 r = -EINTR;
4004 break;
4005 }
4006 }
d7690175
MT		 4007 }
4008
09cec754
GN		 4009 if (r <= 0)
4010 break;
4011
4012 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4013 if (kvm_cpu_has_pending_timer(vcpu))
4014 kvm_inject_pending_timer_irqs(vcpu);
4015
851ba692 4016 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4017 r = -EINTR;
851ba692 4018 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4019 ++vcpu->stat.request_irq_exits;
4020 }
4021 if (signal_pending(current)) {
4022 r = -EINTR;
851ba692 4023 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4024 ++vcpu->stat.signal_exits;
4025 }
4026 if (need_resched()) {
4027 up_read(&vcpu->kvm->slots_lock);
4028 kvm_resched(vcpu);
4029 down_read(&vcpu->kvm->slots_lock);
d7690175 4030 }
b6c7a5dc
HB		 4031 }
4032
d7690175 4033 up_read(&vcpu->kvm->slots_lock);
851ba692 4034 post_kvm_run_save(vcpu);
b6c7a5dc 4035
b93463aa
AK		 4036 vapic_exit(vcpu);
4037
b6c7a5dc
HB		 4038 return r;
4039}
4040
4041int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4042{
4043 int r;
4044 sigset_t sigsaved;
4045
4046 vcpu_load(vcpu);
4047
ac9f6dc0
AK		 4048 if (vcpu->sigset_active)
4049 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4050
a4535290 4051 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4052 kvm_vcpu_block(vcpu);
d7690175 4053 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4054 r = -EAGAIN;
4055 goto out;
b6c7a5dc
HB		 4056 }
4057
b6c7a5dc
HB		 4058 /* re-sync apic's tpr */
4059 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4060 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4061
ad312c7c 4062 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4063 r = complete_pio(vcpu);
4064 if (r)
4065 goto out;
4066 }
b6c7a5dc
HB		 4067 if (vcpu->mmio_needed) {
4068 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4069 vcpu->mmio_read_completed = 1;
4070 vcpu->mmio_needed = 0;
3200f405
MT		 4071
4072 down_read(&vcpu->kvm->slots_lock);
851ba692 4073 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4074 EMULTYPE_NO_DECODE);
3200f405 4075 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 4076 if (r == EMULATE_DO_MMIO) {
4077 /*
4078 * Read-modify-write. Back to userspace.
4079 */
4080 r = 0;
4081 goto out;
4082 }
4083 }
5fdbf976
MT		 4084 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4085 kvm_register_write(vcpu, VCPU_REGS_RAX,
4086 kvm_run->hypercall.ret);
b6c7a5dc 4087
851ba692 4088 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4089
4090out:
4091 if (vcpu->sigset_active)
4092 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4093
4094 vcpu_put(vcpu);
4095 return r;
4096}
4097
4098int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4099{
4100 vcpu_load(vcpu);
4101
5fdbf976
MT		 4102 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4103 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4104 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4105 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4106 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4107 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4108 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4109 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4110#ifdef CONFIG_X86_64
5fdbf976
MT		 4111 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4112 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4113 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4114 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4115 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4116 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4117 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4118 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4119#endif
4120
5fdbf976 4121 regs->rip = kvm_rip_read(vcpu);
91586a3b 4122 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4123
4124 vcpu_put(vcpu);
4125
4126 return 0;
4127}
4128
4129int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4130{
4131 vcpu_load(vcpu);
4132
5fdbf976
MT		 4133 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4134 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4135 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4136 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4137 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4138 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4139 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4140 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4141#ifdef CONFIG_X86_64
5fdbf976
MT		 4142 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4143 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4144 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4145 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4146 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4147 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4148 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4149 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4150#endif
4151
5fdbf976 4152 kvm_rip_write(vcpu, regs->rip);
91586a3b 4153 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4154
b4f14abd
JK		 4155 vcpu->arch.exception.pending = false;
4156
b6c7a5dc
HB		 4157 vcpu_put(vcpu);
4158
4159 return 0;
4160}
4161
3e6e0aab
GT		 4162void kvm_get_segment(struct kvm_vcpu *vcpu,
4163 struct kvm_segment *var, int seg)
b6c7a5dc 4164{
14af3f3c 4165 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4166}
4167
4168void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4169{
4170 struct kvm_segment cs;
4171
3e6e0aab 4172 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4173 *db = cs.db;
4174 *l = cs.l;
4175}
4176EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4177
4178int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4179 struct kvm_sregs *sregs)
4180{
4181 struct descriptor_table dt;
b6c7a5dc
HB		 4182
4183 vcpu_load(vcpu);
4184
3e6e0aab
GT		 4185 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4186 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4187 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4188 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4189 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4190 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4191
3e6e0aab
GT		 4192 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4193 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4194
4195 kvm_x86_ops->get_idt(vcpu, &dt);
4196 sregs->idt.limit = dt.limit;
4197 sregs->idt.base = dt.base;
4198 kvm_x86_ops->get_gdt(vcpu, &dt);
4199 sregs->gdt.limit = dt.limit;
4200 sregs->gdt.base = dt.base;
4201
4202 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 4203 sregs->cr0 = vcpu->arch.cr0;
4204 sregs->cr2 = vcpu->arch.cr2;
4205 sregs->cr3 = vcpu->arch.cr3;
4206 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 4207 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 4208 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 4209 sregs->apic_base = kvm_get_apic_base(vcpu);
4210
923c61bb 4211 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4212
36752c9b 4213 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4214 set_bit(vcpu->arch.interrupt.nr,
4215 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4216
b6c7a5dc
HB		 4217 vcpu_put(vcpu);
4218
4219 return 0;
4220}
4221
62d9f0db
MT		 4222int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4223 struct kvm_mp_state *mp_state)
4224{
4225 vcpu_load(vcpu);
4226 mp_state->mp_state = vcpu->arch.mp_state;
4227 vcpu_put(vcpu);
4228 return 0;
4229}
4230
4231int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4232 struct kvm_mp_state *mp_state)
4233{
4234 vcpu_load(vcpu);
4235 vcpu->arch.mp_state = mp_state->mp_state;
4236 vcpu_put(vcpu);
4237 return 0;
4238}
4239
3e6e0aab 4240static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4241 struct kvm_segment *var, int seg)
4242{
14af3f3c 4243 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4244}
4245
37817f29
IE		 4246static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4247 struct kvm_segment *kvm_desct)
4248{
46a359e7
AM		 4249 kvm_desct->base = get_desc_base(seg_desc);
4250 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4251 if (seg_desc->g) {
4252 kvm_desct->limit <<= 12;
4253 kvm_desct->limit |= 0xfff;
4254 }
37817f29
IE		 4255 kvm_desct->selector = selector;
4256 kvm_desct->type = seg_desc->type;
4257 kvm_desct->present = seg_desc->p;
4258 kvm_desct->dpl = seg_desc->dpl;
4259 kvm_desct->db = seg_desc->d;
4260 kvm_desct->s = seg_desc->s;
4261 kvm_desct->l = seg_desc->l;
4262 kvm_desct->g = seg_desc->g;
4263 kvm_desct->avl = seg_desc->avl;
4264 if (!selector)
4265 kvm_desct->unusable = 1;
4266 else
4267 kvm_desct->unusable = 0;
4268 kvm_desct->padding = 0;
4269}
4270
b8222ad2
AS		 4271static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4272 u16 selector,
4273 struct descriptor_table *dtable)
37817f29
IE		 4274{
4275 if (selector & 1 << 2) {
4276 struct kvm_segment kvm_seg;
4277
3e6e0aab 4278 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4279
4280 if (kvm_seg.unusable)
4281 dtable->limit = 0;
4282 else
4283 dtable->limit = kvm_seg.limit;
4284 dtable->base = kvm_seg.base;
4285 }
4286 else
4287 kvm_x86_ops->get_gdt(vcpu, dtable);
4288}
4289
4290/* allowed just for 8 bytes segments */
4291static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4292 struct desc_struct *seg_desc)
4293{
4294 struct descriptor_table dtable;
4295 u16 index = selector >> 3;
4296
b8222ad2 4297 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4298
4299 if (dtable.limit < index * 8 + 7) {
4300 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4301 return 1;
4302 }
d9048d32 4303 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4304}
4305
4306/* allowed just for 8 bytes segments */
4307static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4308 struct desc_struct *seg_desc)
4309{
4310 struct descriptor_table dtable;
4311 u16 index = selector >> 3;
4312
b8222ad2 4313 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4314
4315 if (dtable.limit < index * 8 + 7)
4316 return 1;
d9048d32 4317 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4318}
4319
abb39119 4320static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
37817f29
IE		 4321 struct desc_struct *seg_desc)
4322{
46a359e7 4323 u32 base_addr = get_desc_base(seg_desc);
37817f29 4324
98899aa0 4325 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4326}
4327
37817f29
IE		 4328static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4329{
4330 struct kvm_segment kvm_seg;
4331
3e6e0aab 4332 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4333 return kvm_seg.selector;
4334}
4335
4336static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4337 u16 selector,
4338 struct kvm_segment *kvm_seg)
4339{
4340 struct desc_struct seg_desc;
4341
4342 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4343 return 1;
4344 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4345 return 0;
4346}
4347
2259e3a7 4348static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4349{
4350 struct kvm_segment segvar = {
4351 .base = selector << 4,
4352 .limit = 0xffff,
4353 .selector = selector,
4354 .type = 3,
4355 .present = 1,
4356 .dpl = 3,
4357 .db = 0,
4358 .s = 1,
4359 .l = 0,
4360 .g = 0,
4361 .avl = 0,
4362 .unusable = 0,
4363 };
4364 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4365 return 0;
4366}
4367
c0c7c04b
AL		 4368static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4369{
4370 return (seg != VCPU_SREG_LDTR) &&
4371 (seg != VCPU_SREG_TR) &&
91586a3b 4372 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4373}
4374
3e6e0aab
GT		 4375int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4376 int type_bits, int seg)
37817f29
IE		 4377{
4378 struct kvm_segment kvm_seg;
4379
c0c7c04b 4380 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
f4bbd9aa 4381 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4382 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4383 return 1;
4384 kvm_seg.type |= type_bits;
4385
4386 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4387 seg != VCPU_SREG_LDTR)
4388 if (!kvm_seg.s)
4389 kvm_seg.unusable = 1;
4390
3e6e0aab 4391 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4392 return 0;
4393}
4394
4395static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4396 struct tss_segment_32 *tss)
4397{
4398 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4399 tss->eip = kvm_rip_read(vcpu);
91586a3b 4400 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4401 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4402 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4403 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4404 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4405 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4406 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4407 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4408 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4409 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4410 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4411 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4412 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4413 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4414 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4415 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4416}
4417
4418static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4419 struct tss_segment_32 *tss)
4420{
4421 kvm_set_cr3(vcpu, tss->cr3);
4422
5fdbf976 4423 kvm_rip_write(vcpu, tss->eip);
91586a3b 4424 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4425
5fdbf976
MT		 4426 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4427 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4428 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4429 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4430 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4431 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4432 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4433 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4434
3e6e0aab 4435 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4436 return 1;
4437
3e6e0aab 4438 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4439 return 1;
4440
3e6e0aab 4441 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4442 return 1;
4443
3e6e0aab 4444 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4445 return 1;
4446
3e6e0aab 4447 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4448 return 1;
4449
3e6e0aab 4450 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4451 return 1;
4452
3e6e0aab 4453 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4454 return 1;
4455 return 0;
4456}
4457
4458static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4459 struct tss_segment_16 *tss)
4460{
5fdbf976 4461 tss->ip = kvm_rip_read(vcpu);
91586a3b 4462 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4463 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4464 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4465 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4466 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4467 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4468 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4469 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4470 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4471
4472 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4473 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4474 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4475 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4476 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4477}
4478
4479static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4480 struct tss_segment_16 *tss)
4481{
5fdbf976 4482 kvm_rip_write(vcpu, tss->ip);
91586a3b 4483 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4484 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4485 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4486 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4487 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4488 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4489 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4490 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4491 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4492
3e6e0aab 4493 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4494 return 1;
4495
3e6e0aab 4496 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4497 return 1;
4498
3e6e0aab 4499 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4500 return 1;
4501
3e6e0aab 4502 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4503 return 1;
4504
3e6e0aab 4505 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4506 return 1;
4507 return 0;
4508}
4509
8b2cf73c 4510static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4511 u16 old_tss_sel, u32 old_tss_base,
4512 struct desc_struct *nseg_desc)
37817f29
IE		 4513{
4514 struct tss_segment_16 tss_segment_16;
4515 int ret = 0;
4516
34198bf8
MT		 4517 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4518 sizeof tss_segment_16))
37817f29
IE		 4519 goto out;
4520
4521 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4522
34198bf8
MT		 4523 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4524 sizeof tss_segment_16))
37817f29 4525 goto out;
34198bf8
MT		 4526
4527 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4528 &tss_segment_16, sizeof tss_segment_16))
4529 goto out;
4530
b237ac37
GN		 4531 if (old_tss_sel != 0xffff) {
4532 tss_segment_16.prev_task_link = old_tss_sel;
4533
4534 if (kvm_write_guest(vcpu->kvm,
4535 get_tss_base_addr(vcpu, nseg_desc),
4536 &tss_segment_16.prev_task_link,
4537 sizeof tss_segment_16.prev_task_link))
4538 goto out;
4539 }
4540
37817f29
IE		 4541 if (load_state_from_tss16(vcpu, &tss_segment_16))
4542 goto out;
4543
4544 ret = 1;
4545out:
4546 return ret;
4547}
4548
8b2cf73c 4549static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4550 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4551 struct desc_struct *nseg_desc)
4552{
4553 struct tss_segment_32 tss_segment_32;
4554 int ret = 0;
4555
34198bf8
MT		 4556 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4557 sizeof tss_segment_32))
37817f29
IE		 4558 goto out;
4559
4560 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4561
34198bf8
MT		 4562 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4563 sizeof tss_segment_32))
4564 goto out;
4565
4566 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4567 &tss_segment_32, sizeof tss_segment_32))
37817f29 4568 goto out;
34198bf8 4569
b237ac37
GN		 4570 if (old_tss_sel != 0xffff) {
4571 tss_segment_32.prev_task_link = old_tss_sel;
4572
4573 if (kvm_write_guest(vcpu->kvm,
4574 get_tss_base_addr(vcpu, nseg_desc),
4575 &tss_segment_32.prev_task_link,
4576 sizeof tss_segment_32.prev_task_link))
4577 goto out;
4578 }
4579
37817f29
IE		 4580 if (load_state_from_tss32(vcpu, &tss_segment_32))
4581 goto out;
4582
4583 ret = 1;
4584out:
4585 return ret;
4586}
4587
4588int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4589{
4590 struct kvm_segment tr_seg;
4591 struct desc_struct cseg_desc;
4592 struct desc_struct nseg_desc;
4593 int ret = 0;
34198bf8
MT		 4594 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4595 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4596
34198bf8 4597 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4598
34198bf8
MT		 4599 /* FIXME: Handle errors. Failure to read either TSS or their
4600 * descriptors should generate a pagefault.
4601 */
37817f29
IE		 4602 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4603 goto out;
4604
34198bf8 4605 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4606 goto out;
4607
37817f29
IE		 4608 if (reason != TASK_SWITCH_IRET) {
4609 int cpl;
4610
4611 cpl = kvm_x86_ops->get_cpl(vcpu);
4612 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4613 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4614 return 1;
4615 }
4616 }
4617
46a359e7 4618 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4619 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4620 return 1;
4621 }
4622
4623 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4624 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4625 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4626 }
4627
4628 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 4629 u32 eflags = kvm_get_rflags(vcpu);
4630 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 4631 }
4632
b237ac37
GN		 4633 /* set back link to prev task only if NT bit is set in eflags
4634 note that old_tss_sel is not used afetr this point */
4635 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4636 old_tss_sel = 0xffff;
4637
37817f29 4638 if (nseg_desc.type & 8)
b237ac37
GN		 4639 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4640 old_tss_base, &nseg_desc);
37817f29 4641 else
b237ac37
GN		 4642 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4643 old_tss_base, &nseg_desc);
37817f29
IE		 4644
4645 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 4646 u32 eflags = kvm_get_rflags(vcpu);
4647 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 4648 }
4649
4650 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4651 nseg_desc.type |= (1 << 1);
37817f29
IE		 4652 save_guest_segment_descriptor(vcpu, tss_selector,
4653 &nseg_desc);
4654 }
4655
4656 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4657 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4658 tr_seg.type = 11;
3e6e0aab 4659 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4660out:
37817f29
IE		 4661 return ret;
4662}
4663EXPORT_SYMBOL_GPL(kvm_task_switch);
4664
b6c7a5dc
HB		 4665int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4666 struct kvm_sregs *sregs)
4667{
4668 int mmu_reset_needed = 0;
923c61bb 4669 int pending_vec, max_bits;
b6c7a5dc
HB		 4670 struct descriptor_table dt;
4671
4672 vcpu_load(vcpu);
4673
4674 dt.limit = sregs->idt.limit;
4675 dt.base = sregs->idt.base;
4676 kvm_x86_ops->set_idt(vcpu, &dt);
4677 dt.limit = sregs->gdt.limit;
4678 dt.base = sregs->gdt.base;
4679 kvm_x86_ops->set_gdt(vcpu, &dt);
4680
ad312c7c
ZX		 4681 vcpu->arch.cr2 = sregs->cr2;
4682 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4683 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4684
2d3ad1f4 4685 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4686
ad312c7c 4687 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4688 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4689 kvm_set_apic_base(vcpu, sregs->apic_base);
4690
4691 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4692
ad312c7c 4693 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4694 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4695 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4696
ad312c7c 4697 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc 4698 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4699 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4700 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4701 mmu_reset_needed = 1;
4702 }
b6c7a5dc
HB		 4703
4704 if (mmu_reset_needed)
4705 kvm_mmu_reset_context(vcpu);
4706
923c61bb
GN		 4707 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4708 pending_vec = find_first_bit(
4709 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4710 if (pending_vec < max_bits) {
66fd3f7f 4711 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4712 pr_debug("Set back pending irq %d\n", pending_vec);
4713 if (irqchip_in_kernel(vcpu->kvm))
4714 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4715 }
4716
3e6e0aab
GT		 4717 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4718 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4719 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4720 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4721 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4722 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4723
3e6e0aab
GT		 4724 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4725 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4726
5f0269f5
ME		 4727 update_cr8_intercept(vcpu);
4728
9c3e4aab 4729 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4730 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4731 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4732 !(vcpu->arch.cr0 & X86_CR0_PE))
4733 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4734
b6c7a5dc
HB		 4735 vcpu_put(vcpu);
4736
4737 return 0;
4738}
4739
d0bfb940
JK		 4740int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4741 struct kvm_guest_debug *dbg)
b6c7a5dc 4742{
355be0b9 4743 unsigned long rflags;
4f926bf2 4744 int i, r;
b6c7a5dc
HB		 4745
4746 vcpu_load(vcpu);
4747
4f926bf2
JK		 4748 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4749 r = -EBUSY;
4750 if (vcpu->arch.exception.pending)
4751 goto unlock_out;
4752 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4753 kvm_queue_exception(vcpu, DB_VECTOR);
4754 else
4755 kvm_queue_exception(vcpu, BP_VECTOR);
4756 }
4757
91586a3b
JK		 4758 /*
4759 * Read rflags as long as potentially injected trace flags are still
4760 * filtered out.
4761 */
4762 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4763
4764 vcpu->guest_debug = dbg->control;
4765 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4766 vcpu->guest_debug = 0;
4767
4768 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4769 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4770 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4771 vcpu->arch.switch_db_regs =
4772 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4773 } else {
4774 for (i = 0; i < KVM_NR_DB_REGS; i++)
4775 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4776 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4777 }
4778
94fe45da
JK		 4779 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4780 vcpu->arch.singlestep_cs =
4781 get_segment_selector(vcpu, VCPU_SREG_CS);
4782 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
4783 }
4784
91586a3b
JK		 4785 /*
4786 * Trigger an rflags update that will inject or remove the trace
4787 * flags.
4788 */
4789 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 4790
355be0b9
JK		 4791 kvm_x86_ops->set_guest_debug(vcpu, dbg);
4792
4f926bf2 4793 r = 0;
d0bfb940 4794
4f926bf2 4795unlock_out:
b6c7a5dc
HB		 4796 vcpu_put(vcpu);
4797
4f926bf2 4798 return r;
b6c7a5dc
HB		 4799}
4800
d0752060
HB		 4801/*
4802 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4803 * we have asm/x86/processor.h
4804 */
4805struct fxsave {
4806 u16 cwd;
4807 u16 swd;
4808 u16 twd;
4809 u16 fop;
4810 u64 rip;
4811 u64 rdp;
4812 u32 mxcsr;
4813 u32 mxcsr_mask;
4814 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4815#ifdef CONFIG_X86_64
4816 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4817#else
4818 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4819#endif
4820};
4821
8b006791
ZX		 4822/*
4823 * Translate a guest virtual address to a guest physical address.
4824 */
4825int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4826 struct kvm_translation *tr)
4827{
4828 unsigned long vaddr = tr->linear_address;
4829 gpa_t gpa;
4830
4831 vcpu_load(vcpu);
72dc67a6 4832 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4833 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4834 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4835 tr->physical_address = gpa;
4836 tr->valid = gpa != UNMAPPED_GVA;
4837 tr->writeable = 1;
4838 tr->usermode = 0;
8b006791
ZX		 4839 vcpu_put(vcpu);
4840
4841 return 0;
4842}
4843
d0752060
HB		 4844int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4845{
ad312c7c 4846 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4847
4848 vcpu_load(vcpu);
4849
4850 memcpy(fpu->fpr, fxsave->st_space, 128);
4851 fpu->fcw = fxsave->cwd;
4852 fpu->fsw = fxsave->swd;
4853 fpu->ftwx = fxsave->twd;
4854 fpu->last_opcode = fxsave->fop;
4855 fpu->last_ip = fxsave->rip;
4856 fpu->last_dp = fxsave->rdp;
4857 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4858
4859 vcpu_put(vcpu);
4860
4861 return 0;
4862}
4863
4864int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4865{
ad312c7c 4866 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4867
4868 vcpu_load(vcpu);
4869
4870 memcpy(fxsave->st_space, fpu->fpr, 128);
4871 fxsave->cwd = fpu->fcw;
4872 fxsave->swd = fpu->fsw;
4873 fxsave->twd = fpu->ftwx;
4874 fxsave->fop = fpu->last_opcode;
4875 fxsave->rip = fpu->last_ip;
4876 fxsave->rdp = fpu->last_dp;
4877 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4878
4879 vcpu_put(vcpu);
4880
4881 return 0;
4882}
4883
4884void fx_init(struct kvm_vcpu *vcpu)
4885{
4886 unsigned after_mxcsr_mask;
4887
bc1a34f1
AA		 4888 /*
4889 * Touch the fpu the first time in non atomic context as if
4890 * this is the first fpu instruction the exception handler
4891 * will fire before the instruction returns and it'll have to
4892 * allocate ram with GFP_KERNEL.
4893 */
4894 if (!used_math())
d6e88aec 4895 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4896
d0752060
HB		 4897 /* Initialize guest FPU by resetting ours and saving into guest's */
4898 preempt_disable();
d6e88aec
AK		 4899 kvm_fx_save(&vcpu->arch.host_fx_image);
4900 kvm_fx_finit();
4901 kvm_fx_save(&vcpu->arch.guest_fx_image);
4902 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4903 preempt_enable();
4904
ad312c7c 4905 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4906 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4907 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4908 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4909 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4910}
4911EXPORT_SYMBOL_GPL(fx_init);
4912
4913void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4914{
4915 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4916 return;
4917
4918 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4919 kvm_fx_save(&vcpu->arch.host_fx_image);
4920 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4921}
4922EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4923
4924void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4925{
4926 if (!vcpu->guest_fpu_loaded)
4927 return;
4928
4929 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4930 kvm_fx_save(&vcpu->arch.guest_fx_image);
4931 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4932 ++vcpu->stat.fpu_reload;
d0752060
HB		 4933}
4934EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4935
4936void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4937{
7f1ea208
JR		 4938 if (vcpu->arch.time_page) {
4939 kvm_release_page_dirty(vcpu->arch.time_page);
4940 vcpu->arch.time_page = NULL;
4941 }
4942
e9b11c17
ZX		 4943 kvm_x86_ops->vcpu_free(vcpu);
4944}
4945
4946struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4947 unsigned int id)
4948{
26e5215f
AK		 4949 return kvm_x86_ops->vcpu_create(kvm, id);
4950}
e9b11c17 4951
26e5215f
AK		 4952int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4953{
4954 int r;
e9b11c17
ZX		 4955
4956 /* We do fxsave: this must be aligned. */
ad312c7c 4957 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4958
0bed3b56 4959 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4960 vcpu_load(vcpu);
4961 r = kvm_arch_vcpu_reset(vcpu);
4962 if (r == 0)
4963 r = kvm_mmu_setup(vcpu);
4964 vcpu_put(vcpu);
4965 if (r < 0)
4966 goto free_vcpu;
4967
26e5215f 4968 return 0;
e9b11c17
ZX		 4969free_vcpu:
4970 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4971 return r;
e9b11c17
ZX		 4972}
4973
d40ccc62 4974void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4975{
4976 vcpu_load(vcpu);
4977 kvm_mmu_unload(vcpu);
4978 vcpu_put(vcpu);
4979
4980 kvm_x86_ops->vcpu_free(vcpu);
4981}
4982
4983int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4984{
448fa4a9
JK		 4985 vcpu->arch.nmi_pending = false;
4986 vcpu->arch.nmi_injected = false;
4987
42dbaa5a
JK		 4988 vcpu->arch.switch_db_regs = 0;
4989 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4990 vcpu->arch.dr6 = DR6_FIXED_1;
4991 vcpu->arch.dr7 = DR7_FIXED_1;
4992
e9b11c17
ZX		 4993 return kvm_x86_ops->vcpu_reset(vcpu);
4994}
4995
10474ae8 4996int kvm_arch_hardware_enable(void *garbage)
e9b11c17 4997{
0cca7907
ZA		 4998 /*
4999 * Since this may be called from a hotplug notifcation,
5000 * we can't get the CPU frequency directly.
5001 */
5002 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5003 int cpu = raw_smp_processor_id();
5004 per_cpu(cpu_tsc_khz, cpu) = 0;
5005 }
18863bdd
AK		 5006
5007 kvm_shared_msr_cpu_online();
5008
10474ae8 5009 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5010}
5011
5012void kvm_arch_hardware_disable(void *garbage)
5013{
5014 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5015 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5016}
5017
5018int kvm_arch_hardware_setup(void)
5019{
5020 return kvm_x86_ops->hardware_setup();
5021}
5022
5023void kvm_arch_hardware_unsetup(void)
5024{
5025 kvm_x86_ops->hardware_unsetup();
5026}
5027
5028void kvm_arch_check_processor_compat(void *rtn)
5029{
5030 kvm_x86_ops->check_processor_compatibility(rtn);
5031}
5032
5033int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5034{
5035 struct page *page;
5036 struct kvm *kvm;
5037 int r;
5038
5039 BUG_ON(vcpu->kvm == NULL);
5040 kvm = vcpu->kvm;
5041
ad312c7c 5042 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5043 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5044 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5045 else
a4535290 5046 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5047
5048 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5049 if (!page) {
5050 r = -ENOMEM;
5051 goto fail;
5052 }
ad312c7c 5053 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5054
5055 r = kvm_mmu_create(vcpu);
5056 if (r < 0)
5057 goto fail_free_pio_data;
5058
5059 if (irqchip_in_kernel(kvm)) {
5060 r = kvm_create_lapic(vcpu);
5061 if (r < 0)
5062 goto fail_mmu_destroy;
5063 }
5064
890ca9ae
HY		 5065 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5066 GFP_KERNEL);
5067 if (!vcpu->arch.mce_banks) {
5068 r = -ENOMEM;
5069 goto fail_mmu_destroy;
5070 }
5071 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5072
e9b11c17
ZX		 5073 return 0;
5074
5075fail_mmu_destroy:
5076 kvm_mmu_destroy(vcpu);
5077fail_free_pio_data:
ad312c7c 5078 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5079fail:
5080 return r;
5081}
5082
5083void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5084{
5085 kvm_free_lapic(vcpu);
3200f405 5086 down_read(&vcpu->kvm->slots_lock);
e9b11c17 5087 kvm_mmu_destroy(vcpu);
3200f405 5088 up_read(&vcpu->kvm->slots_lock);
ad312c7c 5089 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5090}
d19a9cd2
ZX		 5091
5092struct kvm *kvm_arch_create_vm(void)
5093{
5094 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5095
5096 if (!kvm)
5097 return ERR_PTR(-ENOMEM);
5098
f05e70ac 5099 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5100 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5101
5550af4d
SY		 5102 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5103 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5104
53f658b3
MT		 5105 rdtscll(kvm->arch.vm_init_tsc);
5106
d19a9cd2
ZX		 5107 return kvm;
5108}
5109
5110static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5111{
5112 vcpu_load(vcpu);
5113 kvm_mmu_unload(vcpu);
5114 vcpu_put(vcpu);
5115}
5116
5117static void kvm_free_vcpus(struct kvm *kvm)
5118{
5119 unsigned int i;
988a2cae 5120 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5121
5122 /*
5123 * Unpin any mmu pages first.
5124 */
988a2cae
GN		 5125 kvm_for_each_vcpu(i, vcpu, kvm)
5126 kvm_unload_vcpu_mmu(vcpu);
5127 kvm_for_each_vcpu(i, vcpu, kvm)
5128 kvm_arch_vcpu_free(vcpu);
5129
5130 mutex_lock(&kvm->lock);
5131 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5132 kvm->vcpus[i] = NULL;
d19a9cd2 5133
988a2cae
GN		 5134 atomic_set(&kvm->online_vcpus, 0);
5135 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5136}
5137
ad8ba2cd
SY		 5138void kvm_arch_sync_events(struct kvm *kvm)
5139{
ba4cef31 5140 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5141}
5142
d19a9cd2
ZX		 5143void kvm_arch_destroy_vm(struct kvm *kvm)
5144{
6eb55818 5145 kvm_iommu_unmap_guest(kvm);
7837699f 5146 kvm_free_pit(kvm);
d7deeeb0
ZX		 5147 kfree(kvm->arch.vpic);
5148 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5149 kvm_free_vcpus(kvm);
5150 kvm_free_physmem(kvm);
3d45830c
AK		 5151 if (kvm->arch.apic_access_page)
5152 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5153 if (kvm->arch.ept_identity_pagetable)
5154 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 5155 kfree(kvm);
5156}
0de10343
ZX		 5157
5158int kvm_arch_set_memory_region(struct kvm *kvm,
5159 struct kvm_userspace_memory_region *mem,
5160 struct kvm_memory_slot old,
5161 int user_alloc)
5162{
5163 int npages = mem->memory_size >> PAGE_SHIFT;
5164 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
5165
5166 /*To keep backward compatibility with older userspace,
5167 *x86 needs to hanlde !user_alloc case.
5168 */
5169 if (!user_alloc) {
5170 if (npages && !old.rmap) {
604b38ac
AA		 5171 unsigned long userspace_addr;
5172
72dc67a6 5173 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5174 userspace_addr = do_mmap(NULL, 0,
5175 npages * PAGE_SIZE,
5176 PROT_READ | PROT_WRITE,
acee3c04 5177 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5178 0);
72dc67a6 5179 up_write(&current->mm->mmap_sem);
0de10343 5180
604b38ac
AA		 5181 if (IS_ERR((void *)userspace_addr))
5182 return PTR_ERR((void *)userspace_addr);
5183
5184 /* set userspace_addr atomically for kvm_hva_to_rmapp */
5185 spin_lock(&kvm->mmu_lock);
5186 memslot->userspace_addr = userspace_addr;
5187 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 5188 } else {
5189 if (!old.user_alloc && old.rmap) {
5190 int ret;
5191
72dc67a6 5192 down_write(&current->mm->mmap_sem);
0de10343
ZX		 5193 ret = do_munmap(current->mm, old.userspace_addr,
5194 old.npages * PAGE_SIZE);
72dc67a6 5195 up_write(&current->mm->mmap_sem);
0de10343
ZX		 5196 if (ret < 0)
5197 printk(KERN_WARNING
5198 "kvm_vm_ioctl_set_memory_region: "
5199 "failed to munmap memory\n");
5200 }
5201 }
5202 }
5203
7c8a83b7 5204 spin_lock(&kvm->mmu_lock);
f05e70ac 5205 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5206 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5207 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5208 }
5209
5210 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5211 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 5212
5213 return 0;
5214}
1d737c8a 5215
34d4cb8f
MT		 5216void kvm_arch_flush_shadow(struct kvm *kvm)
5217{
5218 kvm_mmu_zap_all(kvm);
8986ecc0 5219 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5220}
5221
1d737c8a
ZX		 5222int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5223{
a4535290 5224 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5225 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5226 || vcpu->arch.nmi_pending ||
5227 (kvm_arch_interrupt_allowed(vcpu) &&
5228 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5229}
5736199a 5230
5736199a
ZX		 5231void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5232{
32f88400
MT		 5233 int me;
5234 int cpu = vcpu->cpu;
5736199a
ZX		 5235
5236 if (waitqueue_active(&vcpu->wq)) {
5237 wake_up_interruptible(&vcpu->wq);
5238 ++vcpu->stat.halt_wakeup;
5239 }
32f88400
MT		 5240
5241 me = get_cpu();
5242 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5243 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5244 smp_send_reschedule(cpu);
e9571ed5 5245 put_cpu();
5736199a 5246}
78646121
GN		 5247
5248int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5249{
5250 return kvm_x86_ops->interrupt_allowed(vcpu);
5251}
229456fc 5252
94fe45da
JK		 5253unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5254{
5255 unsigned long rflags;
5256
5257 rflags = kvm_x86_ops->get_rflags(vcpu);
5258 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5259 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5260 return rflags;
5261}
5262EXPORT_SYMBOL_GPL(kvm_get_rflags);
5263
5264void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5265{
5266 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5267 vcpu->arch.singlestep_cs ==
5268 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5269 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5270 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5271 kvm_x86_ops->set_rflags(vcpu, rflags);
5272}
5273EXPORT_SYMBOL_GPL(kvm_set_rflags);
5274
229456fc
MT		 5275EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5276EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5277EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5278EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5279EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5280EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5281EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5282EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5283EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5284EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5285EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
Linux 6.x block layer and io_uring tree(s)