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KVM: Force vmexit with virtual interrupt delivery
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
af585b92
GN		 165static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166{
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170}
171
18863bdd
AK		 172static void kvm_on_user_return(struct user_return_notifier *urn)
173{
174 unsigned slot;
18863bdd
AK		 175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 177 struct kvm_shared_msr_values *values;
18863bdd
AK		 178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
18863bdd
AK		 184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188}
189
2bf78fa7 190static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 191{
18863bdd 192 u64 value;
013f6a5d
MT		 193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 195
2bf78fa7
SY		 196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205}
206
207void kvm_define_shared_msr(unsigned slot, u32 msr)
208{
18863bdd
AK		 209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
18863bdd
AK		 214}
215EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217static void kvm_shared_msr_cpu_online(void)
218{
219 unsigned i;
18863bdd
AK		 220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 222 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 223}
224
d5696725 225void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 226{
013f6a5d
MT		 227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 229
2bf78fa7 230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 231 return;
2bf78fa7
SY		 232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
238 }
239}
240EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
3548bab5
AK		 242static void drop_user_return_notifiers(void *ignore)
243{
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
e3ba45b8
GL		 264asmlinkage void kvm_spurious_fault(void)
265{
266 /* Fault while not rebooting. We want the trace. */
267 BUG();
268}
269EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
3fd28fce
ED		 271#define EXCPT_BENIGN 0
272#define EXCPT_CONTRIBUTORY 1
273#define EXCPT_PF 2
274
275static int exception_class(int vector)
276{
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290}
291
292static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 293 unsigned nr, bool has_error, u32 error_code,
294 bool reinject)
3fd28fce
ED		 295{
296 u32 prev_nr;
297 int class1, class2;
298
3842d135
AK		 299 kvm_make_request(KVM_REQ_EVENT, vcpu);
300
3fd28fce
ED		 301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
3f0fd292 307 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 308 return;
309 }
310
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
a8eeb04a 315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 316 return;
317 }
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
327 } else
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
330 exception */
331 goto queue;
332}
333
298101da
AK		 334void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
ce7ddec4 336 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 337}
338EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
ce7ddec4
JR		 340void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341{
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
343}
344EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
db8fcefa 346void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 347{
db8fcefa
AP		 348 if (err)
349 kvm_inject_gp(vcpu, 0);
350 else
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
352}
353EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 354
6389ee94 355void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 356{
357 ++vcpu->stat.pf_guest;
6389ee94
AK		 358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 360}
27d6c865 361EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 362
6389ee94 363void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 364{
6389ee94
AK		 365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 367 else
6389ee94 368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 369}
370
3419ffc8
SY		 371void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372{
7460fb4a
AK		 373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 375}
376EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
298101da
AK		 378void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
ce7ddec4 380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 381}
382EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
ce7ddec4
JR		 384void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385{
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
387}
388EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
0a79b009
AK		 390/*
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
393 */
394bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 395{
0a79b009
AK		 396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397 return true;
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399 return false;
298101da 400}
0a79b009 401EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 402
ec92fe44
JR		 403/*
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
407 */
408int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
410 u32 access)
411{
412 gfn_t real_gfn;
413 gpa_t ngpa;
414
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
418 return -EFAULT;
419
420 real_gfn = gpa_to_gfn(real_gfn);
421
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423}
424EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
3d06b8bf
JR		 426int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
428{
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
431}
432
a03490ed
CO		 433/*
434 * Load the pae pdptrs. Return true is they are all valid.
435 */
ff03a073 436int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 437{
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440 int i;
441 int ret;
ff03a073 442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 443
ff03a073
JR		 444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 447 if (ret < 0) {
448 ret = 0;
449 goto out;
450 }
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 452 if (is_present_gpte(pdpte[i]) &&
20c466b5 453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 454 ret = 0;
455 goto out;
456 }
457 }
458 ret = 1;
459
ff03a073 460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 465out:
a03490ed
CO		 466
467 return ret;
468}
cc4b6871 469EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 470
d835dfec
AK		 471static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472{
ff03a073 473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 474 bool changed = true;
3d06b8bf
JR		 475 int offset;
476 gfn_t gfn;
d835dfec
AK		 477 int r;
478
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
480 return false;
481
6de4f3ad
AK		 482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
484 return true;
485
9f8fe504
AK		 486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 490 if (r < 0)
491 goto out;
ff03a073 492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 493out:
d835dfec
AK		 494
495 return changed;
496}
497
49a9b07e 498int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 499{
aad82703
SY		 500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
503
f9a48e6a
AK		 504 cr0 |= X86_CR0_ET;
505
ab344828 506#ifdef CONFIG_X86_64
0f12244f
GN		 507 if (cr0 & 0xffffffff00000000UL)
508 return 1;
ab344828
GN		 509#endif
510
511 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 512
0f12244f
GN		 513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514 return 1;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517 return 1;
a03490ed
CO		 518
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520#ifdef CONFIG_X86_64
f6801dff 521 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 522 int cs_db, cs_l;
523
0f12244f
GN		 524 if (!is_pae(vcpu))
525 return 1;
a03490ed 526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 527 if (cs_l)
528 return 1;
a03490ed
CO		 529 } else
530#endif
ff03a073 531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 532 kvm_read_cr3(vcpu)))
0f12244f 533 return 1;
a03490ed
CO		 534 }
535
ad756a16
MJ		 536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537 return 1;
538
a03490ed 539 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 540
d170c419 541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 542 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 543 kvm_async_pf_hash_reset(vcpu);
544 }
e5f3f027 545
aad82703
SY		 546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 548 return 0;
549}
2d3ad1f4 550EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 551
2d3ad1f4 552void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 553{
49a9b07e 554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 555}
2d3ad1f4 556EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 557
2acf923e
DC		 558int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
559{
560 u64 xcr0;
561
562 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
563 if (index != XCR_XFEATURE_ENABLED_MASK)
564 return 1;
565 xcr0 = xcr;
566 if (kvm_x86_ops->get_cpl(vcpu) != 0)
567 return 1;
568 if (!(xcr0 & XSTATE_FP))
569 return 1;
570 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
571 return 1;
572 if (xcr0 & ~host_xcr0)
573 return 1;
574 vcpu->arch.xcr0 = xcr0;
575 vcpu->guest_xcr0_loaded = 0;
576 return 0;
577}
578
579int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
580{
581 if (__kvm_set_xcr(vcpu, index, xcr)) {
582 kvm_inject_gp(vcpu, 0);
583 return 1;
584 }
585 return 0;
586}
587EXPORT_SYMBOL_GPL(kvm_set_xcr);
588
a83b29c6 589int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 590{
fc78f519 591 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 592 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
593 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 594 if (cr4 & CR4_RESERVED_BITS)
595 return 1;
a03490ed 596
2acf923e
DC		 597 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
598 return 1;
599
c68b734f
YW		 600 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
601 return 1;
602
74dc2b4f
YW		 603 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
604 return 1;
605
a03490ed 606 if (is_long_mode(vcpu)) {
0f12244f
GN		 607 if (!(cr4 & X86_CR4_PAE))
608 return 1;
a2edf57f
AK		 609 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
610 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 611 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
612 kvm_read_cr3(vcpu)))
0f12244f
GN		 613 return 1;
614
ad756a16
MJ		 615 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
616 if (!guest_cpuid_has_pcid(vcpu))
617 return 1;
618
619 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
620 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
621 return 1;
622 }
623
5e1746d6 624 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 625 return 1;
a03490ed 626
ad756a16
MJ		 627 if (((cr4 ^ old_cr4) & pdptr_bits) ||
628 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 629 kvm_mmu_reset_context(vcpu);
0f12244f 630
2acf923e 631 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 632 kvm_update_cpuid(vcpu);
2acf923e 633
0f12244f
GN		 634 return 0;
635}
2d3ad1f4 636EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 637
2390218b 638int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 639{
9f8fe504 640 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 641 kvm_mmu_sync_roots(vcpu);
d835dfec 642 kvm_mmu_flush_tlb(vcpu);
0f12244f 643 return 0;
d835dfec
AK		 644 }
645
a03490ed 646 if (is_long_mode(vcpu)) {
471842ec 647 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 648 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
649 return 1;
650 } else
651 if (cr3 & CR3_L_MODE_RESERVED_BITS)
652 return 1;
a03490ed
CO		 653 } else {
654 if (is_pae(vcpu)) {
0f12244f
GN		 655 if (cr3 & CR3_PAE_RESERVED_BITS)
656 return 1;
ff03a073
JR		 657 if (is_paging(vcpu) &&
658 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 659 return 1;
a03490ed
CO		 660 }
661 /*
662 * We don't check reserved bits in nonpae mode, because
663 * this isn't enforced, and VMware depends on this.
664 */
665 }
666
a03490ed
CO		 667 /*
668 * Does the new cr3 value map to physical memory? (Note, we
669 * catch an invalid cr3 even in real-mode, because it would
670 * cause trouble later on when we turn on paging anyway.)
671 *
672 * A real CPU would silently accept an invalid cr3 and would
673 * attempt to use it - with largely undefined (and often hard
674 * to debug) behavior on the guest side.
675 */
676 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 677 return 1;
678 vcpu->arch.cr3 = cr3;
aff48baa 679 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 680 vcpu->arch.mmu.new_cr3(vcpu);
681 return 0;
682}
2d3ad1f4 683EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 684
eea1cff9 685int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 686{
0f12244f
GN		 687 if (cr8 & CR8_RESERVED_BITS)
688 return 1;
a03490ed
CO		 689 if (irqchip_in_kernel(vcpu->kvm))
690 kvm_lapic_set_tpr(vcpu, cr8);
691 else
ad312c7c 692 vcpu->arch.cr8 = cr8;
0f12244f
GN		 693 return 0;
694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 696
2d3ad1f4 697unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 698{
699 if (irqchip_in_kernel(vcpu->kvm))
700 return kvm_lapic_get_cr8(vcpu);
701 else
ad312c7c 702 return vcpu->arch.cr8;
a03490ed 703}
2d3ad1f4 704EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 705
c8639010
JK		 706static void kvm_update_dr7(struct kvm_vcpu *vcpu)
707{
708 unsigned long dr7;
709
710 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
711 dr7 = vcpu->arch.guest_debug_dr7;
712 else
713 dr7 = vcpu->arch.dr7;
714 kvm_x86_ops->set_dr7(vcpu, dr7);
715 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
716}
717
338dbc97 718static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 719{
720 switch (dr) {
721 case 0 ... 3:
722 vcpu->arch.db[dr] = val;
723 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
724 vcpu->arch.eff_db[dr] = val;
725 break;
726 case 4:
338dbc97
GN		 727 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
728 return 1; /* #UD */
020df079
GN		 729 /* fall through */
730 case 6:
338dbc97
GN		 731 if (val & 0xffffffff00000000ULL)
732 return -1; /* #GP */
020df079
GN		 733 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
734 break;
735 case 5:
338dbc97
GN		 736 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
737 return 1; /* #UD */
020df079
GN		 738 /* fall through */
739 default: /* 7 */
338dbc97
GN		 740 if (val & 0xffffffff00000000ULL)
741 return -1; /* #GP */
020df079 742 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 743 kvm_update_dr7(vcpu);
020df079
GN		 744 break;
745 }
746
747 return 0;
748}
338dbc97
GN		 749
750int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
751{
752 int res;
753
754 res = __kvm_set_dr(vcpu, dr, val);
755 if (res > 0)
756 kvm_queue_exception(vcpu, UD_VECTOR);
757 else if (res < 0)
758 kvm_inject_gp(vcpu, 0);
759
760 return res;
761}
020df079
GN		 762EXPORT_SYMBOL_GPL(kvm_set_dr);
763
338dbc97 764static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 765{
766 switch (dr) {
767 case 0 ... 3:
768 *val = vcpu->arch.db[dr];
769 break;
770 case 4:
338dbc97 771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 772 return 1;
020df079
GN		 773 /* fall through */
774 case 6:
775 *val = vcpu->arch.dr6;
776 break;
777 case 5:
338dbc97 778 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 779 return 1;
020df079
GN		 780 /* fall through */
781 default: /* 7 */
782 *val = vcpu->arch.dr7;
783 break;
784 }
785
786 return 0;
787}
338dbc97
GN		 788
789int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
790{
791 if (_kvm_get_dr(vcpu, dr, val)) {
792 kvm_queue_exception(vcpu, UD_VECTOR);
793 return 1;
794 }
795 return 0;
796}
020df079
GN		 797EXPORT_SYMBOL_GPL(kvm_get_dr);
798
022cd0e8
AK		 799bool kvm_rdpmc(struct kvm_vcpu *vcpu)
800{
801 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
802 u64 data;
803 int err;
804
805 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
806 if (err)
807 return err;
808 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
809 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
810 return err;
811}
812EXPORT_SYMBOL_GPL(kvm_rdpmc);
813
043405e1
CO		 814/*
815 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
816 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
817 *
818 * This list is modified at module load time to reflect the
e3267cbb
GC		 819 * capabilities of the host cpu. This capabilities test skips MSRs that are
820 * kvm-specific. Those are put in the beginning of the list.
043405e1 821 */
e3267cbb 822
439793d4 823#define KVM_SAVE_MSRS_BEGIN 10
043405e1 824static u32 msrs_to_save[] = {
e3267cbb 825 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 826 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 827 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 828 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 829 MSR_KVM_PV_EOI_EN,
043405e1 830 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 831 MSR_STAR,
043405e1
CO		 832#ifdef CONFIG_X86_64
833 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
834#endif
e90aa41e 835 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 836};
837
838static unsigned num_msrs_to_save;
839
f1d24831 840static const u32 emulated_msrs[] = {
ba904635 841 MSR_IA32_TSC_ADJUST,
a3e06bbe 842 MSR_IA32_TSCDEADLINE,
043405e1 843 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 844 MSR_IA32_MCG_STATUS,
845 MSR_IA32_MCG_CTL,
043405e1
CO		 846};
847
b69e8cae 848static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 849{
aad82703
SY		 850 u64 old_efer = vcpu->arch.efer;
851
b69e8cae
RJ		 852 if (efer & efer_reserved_bits)
853 return 1;
15c4a640
CO		 854
855 if (is_paging(vcpu)
b69e8cae
RJ		 856 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
857 return 1;
15c4a640 858
1b2fd70c
AG		 859 if (efer & EFER_FFXSR) {
860 struct kvm_cpuid_entry2 *feat;
861
862 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 863 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
864 return 1;
1b2fd70c
AG		 865 }
866
d8017474
AG		 867 if (efer & EFER_SVME) {
868 struct kvm_cpuid_entry2 *feat;
869
870 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 871 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
872 return 1;
d8017474
AG		 873 }
874
15c4a640 875 efer &= ~EFER_LMA;
f6801dff 876 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 877
a3d204e2
SY		 878 kvm_x86_ops->set_efer(vcpu, efer);
879
aad82703
SY		 880 /* Update reserved bits */
881 if ((efer ^ old_efer) & EFER_NX)
882 kvm_mmu_reset_context(vcpu);
883
b69e8cae 884 return 0;
15c4a640
CO		 885}
886
f2b4b7dd
JR		 887void kvm_enable_efer_bits(u64 mask)
888{
889 efer_reserved_bits &= ~mask;
890}
891EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
892
893
15c4a640
CO		 894/*
895 * Writes msr value into into the appropriate "register".
896 * Returns 0 on success, non-0 otherwise.
897 * Assumes vcpu_load() was already called.
898 */
8fe8ab46 899int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 900{
8fe8ab46 901 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 902}
903
313a3dc7
CO		 904/*
905 * Adapt set_msr() to msr_io()'s calling convention
906 */
907static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
908{
8fe8ab46
WA		 909 struct msr_data msr;
910
911 msr.data = *data;
912 msr.index = index;
913 msr.host_initiated = true;
914 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 915}
916
16e8d74d
MT		 917#ifdef CONFIG_X86_64
918struct pvclock_gtod_data {
919 seqcount_t seq;
920
921 struct { /* extract of a clocksource struct */
922 int vclock_mode;
923 cycle_t cycle_last;
924 cycle_t mask;
925 u32 mult;
926 u32 shift;
927 } clock;
928
929 /* open coded 'struct timespec' */
930 u64 monotonic_time_snsec;
931 time_t monotonic_time_sec;
932};
933
934static struct pvclock_gtod_data pvclock_gtod_data;
935
936static void update_pvclock_gtod(struct timekeeper *tk)
937{
938 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
939
940 write_seqcount_begin(&vdata->seq);
941
942 /* copy pvclock gtod data */
943 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
944 vdata->clock.cycle_last = tk->clock->cycle_last;
945 vdata->clock.mask = tk->clock->mask;
946 vdata->clock.mult = tk->mult;
947 vdata->clock.shift = tk->shift;
948
949 vdata->monotonic_time_sec = tk->xtime_sec
950 + tk->wall_to_monotonic.tv_sec;
951 vdata->monotonic_time_snsec = tk->xtime_nsec
952 + (tk->wall_to_monotonic.tv_nsec
953 << tk->shift);
954 while (vdata->monotonic_time_snsec >=
955 (((u64)NSEC_PER_SEC) << tk->shift)) {
956 vdata->monotonic_time_snsec -=
957 ((u64)NSEC_PER_SEC) << tk->shift;
958 vdata->monotonic_time_sec++;
959 }
960
961 write_seqcount_end(&vdata->seq);
962}
963#endif
964
965
18068523
GOC		 966static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
967{
9ed3c444
AK		 968 int version;
969 int r;
50d0a0f9 970 struct pvclock_wall_clock wc;
923de3cf 971 struct timespec boot;
18068523
GOC		 972
973 if (!wall_clock)
974 return;
975
9ed3c444
AK		 976 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
977 if (r)
978 return;
979
980 if (version & 1)
981 ++version; /* first time write, random junk */
982
983 ++version;
18068523 984
18068523
GOC		 985 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
986
50d0a0f9
GH		 987 /*
988 * The guest calculates current wall clock time by adding
34c238a1 989 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 990 * wall clock specified here. guest system time equals host
991 * system time for us, thus we must fill in host boot time here.
992 */
923de3cf 993 getboottime(&boot);
50d0a0f9 994
4b648665
BR		 995 if (kvm->arch.kvmclock_offset) {
996 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
997 boot = timespec_sub(boot, ts);
998 }
50d0a0f9
GH		 999 wc.sec = boot.tv_sec;
1000 wc.nsec = boot.tv_nsec;
1001 wc.version = version;
18068523
GOC		 1002
1003 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1004
1005 version++;
1006 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1007}
1008
50d0a0f9
GH		 1009static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1010{
1011 uint32_t quotient, remainder;
1012
1013 /* Don't try to replace with do_div(), this one calculates
1014 * "(dividend << 32) / divisor" */
1015 __asm__ ( "divl %4"
1016 : "=a" (quotient), "=d" (remainder)
1017 : "0" (0), "1" (dividend), "r" (divisor) );
1018 return quotient;
1019}
1020
5f4e3f88
ZA		 1021static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1022 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1023{
5f4e3f88 1024 uint64_t scaled64;
50d0a0f9
GH		 1025 int32_t shift = 0;
1026 uint64_t tps64;
1027 uint32_t tps32;
1028
5f4e3f88
ZA		 1029 tps64 = base_khz * 1000LL;
1030 scaled64 = scaled_khz * 1000LL;
50933623 1031 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1032 tps64 >>= 1;
1033 shift--;
1034 }
1035
1036 tps32 = (uint32_t)tps64;
50933623
JK		 1037 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1038 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1039 scaled64 >>= 1;
1040 else
1041 tps32 <<= 1;
50d0a0f9
GH		 1042 shift++;
1043 }
1044
5f4e3f88
ZA		 1045 *pshift = shift;
1046 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1047
5f4e3f88
ZA		 1048 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1049 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1050}
1051
759379dd
ZA		 1052static inline u64 get_kernel_ns(void)
1053{
1054 struct timespec ts;
1055
1056 WARN_ON(preemptible());
1057 ktime_get_ts(&ts);
1058 monotonic_to_bootbased(&ts);
1059 return timespec_to_ns(&ts);
50d0a0f9
GH		 1060}
1061
d828199e 1062#ifdef CONFIG_X86_64
16e8d74d 1063static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1064#endif
16e8d74d 1065
c8076604 1066static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1067unsigned long max_tsc_khz;
c8076604 1068
cc578287 1069static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1070{
cc578287
ZA		 1071 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1072 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1073}
1074
cc578287 1075static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1076{
cc578287
ZA		 1077 u64 v = (u64)khz * (1000000 + ppm);
1078 do_div(v, 1000000);
1079 return v;
1e993611
JR		 1080}
1081
cc578287 1082static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1083{
cc578287
ZA		 1084 u32 thresh_lo, thresh_hi;
1085 int use_scaling = 0;
217fc9cf 1086
03ba32ca
MT		 1087 /* tsc_khz can be zero if TSC calibration fails */
1088 if (this_tsc_khz == 0)
1089 return;
1090
c285545f
ZA		 1091 /* Compute a scale to convert nanoseconds in TSC cycles */
1092 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1093 &vcpu->arch.virtual_tsc_shift,
1094 &vcpu->arch.virtual_tsc_mult);
1095 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1096
1097 /*
1098 * Compute the variation in TSC rate which is acceptable
1099 * within the range of tolerance and decide if the
1100 * rate being applied is within that bounds of the hardware
1101 * rate. If so, no scaling or compensation need be done.
1102 */
1103 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1104 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1105 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1106 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1107 use_scaling = 1;
1108 }
1109 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1110}
1111
1112static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1113{
e26101b1 1114 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1115 vcpu->arch.virtual_tsc_mult,
1116 vcpu->arch.virtual_tsc_shift);
e26101b1 1117 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1118 return tsc;
1119}
1120
b48aa97e
MT		 1121void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1122{
1123#ifdef CONFIG_X86_64
1124 bool vcpus_matched;
1125 bool do_request = false;
1126 struct kvm_arch *ka = &vcpu->kvm->arch;
1127 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1128
1129 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1130 atomic_read(&vcpu->kvm->online_vcpus));
1131
1132 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1133 if (!ka->use_master_clock)
1134 do_request = 1;
1135
1136 if (!vcpus_matched && ka->use_master_clock)
1137 do_request = 1;
1138
1139 if (do_request)
1140 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1141
1142 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1143 atomic_read(&vcpu->kvm->online_vcpus),
1144 ka->use_master_clock, gtod->clock.vclock_mode);
1145#endif
1146}
1147
ba904635
WA		 1148static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1149{
1150 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1151 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1152}
1153
8fe8ab46 1154void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1155{
1156 struct kvm *kvm = vcpu->kvm;
f38e098f 1157 u64 offset, ns, elapsed;
99e3e30a 1158 unsigned long flags;
02626b6a 1159 s64 usdiff;
b48aa97e 1160 bool matched;
8fe8ab46 1161 u64 data = msr->data;
99e3e30a 1162
038f8c11 1163 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1164 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1165 ns = get_kernel_ns();
f38e098f 1166 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1167
03ba32ca
MT		 1168 if (vcpu->arch.virtual_tsc_khz) {
1169 /* n.b - signed multiplication and division required */
1170 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1171#ifdef CONFIG_X86_64
03ba32ca 1172 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1173#else
03ba32ca
MT		 1174 /* do_div() only does unsigned */
1175 asm("idivl %2; xor %%edx, %%edx"
1176 : "=A"(usdiff)
1177 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1178#endif
03ba32ca
MT		 1179 do_div(elapsed, 1000);
1180 usdiff -= elapsed;
1181 if (usdiff < 0)
1182 usdiff = -usdiff;
1183 } else
1184 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1185
1186 /*
5d3cb0f6
ZA		 1187 * Special case: TSC write with a small delta (1 second) of virtual
1188 * cycle time against real time is interpreted as an attempt to
1189 * synchronize the CPU.
1190 *
1191 * For a reliable TSC, we can match TSC offsets, and for an unstable
1192 * TSC, we add elapsed time in this computation. We could let the
1193 * compensation code attempt to catch up if we fall behind, but
1194 * it's better to try to match offsets from the beginning.
1195 */
02626b6a 1196 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1197 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1198 if (!check_tsc_unstable()) {
e26101b1 1199 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1200 pr_debug("kvm: matched tsc offset for %llu\n", data);
1201 } else {
857e4099 1202 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1203 data += delta;
1204 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1205 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1206 }
b48aa97e 1207 matched = true;
e26101b1
ZA		 1208 } else {
1209 /*
1210 * We split periods of matched TSC writes into generations.
1211 * For each generation, we track the original measured
1212 * nanosecond time, offset, and write, so if TSCs are in
1213 * sync, we can match exact offset, and if not, we can match
4a969980 1214 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1215 *
1216 * These values are tracked in kvm->arch.cur_xxx variables.
1217 */
1218 kvm->arch.cur_tsc_generation++;
1219 kvm->arch.cur_tsc_nsec = ns;
1220 kvm->arch.cur_tsc_write = data;
1221 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1222 matched = false;
e26101b1
ZA		 1223 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1224 kvm->arch.cur_tsc_generation, data);
f38e098f 1225 }
e26101b1
ZA		 1226
1227 /*
1228 * We also track th most recent recorded KHZ, write and time to
1229 * allow the matching interval to be extended at each write.
1230 */
f38e098f
ZA		 1231 kvm->arch.last_tsc_nsec = ns;
1232 kvm->arch.last_tsc_write = data;
5d3cb0f6 1233 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1234
1235 /* Reset of TSC must disable overshoot protection below */
1236 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1237 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1238
1239 /* Keep track of which generation this VCPU has synchronized to */
1240 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1241 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1242 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1243
ba904635
WA		 1244 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1245 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1246 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1247 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1248
1249 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1250 if (matched)
1251 kvm->arch.nr_vcpus_matched_tsc++;
1252 else
1253 kvm->arch.nr_vcpus_matched_tsc = 0;
1254
1255 kvm_track_tsc_matching(vcpu);
1256 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1257}
e26101b1 1258
99e3e30a
ZA		 1259EXPORT_SYMBOL_GPL(kvm_write_tsc);
1260
d828199e
MT		 1261#ifdef CONFIG_X86_64
1262
1263static cycle_t read_tsc(void)
1264{
1265 cycle_t ret;
1266 u64 last;
1267
1268 /*
1269 * Empirically, a fence (of type that depends on the CPU)
1270 * before rdtsc is enough to ensure that rdtsc is ordered
1271 * with respect to loads. The various CPU manuals are unclear
1272 * as to whether rdtsc can be reordered with later loads,
1273 * but no one has ever seen it happen.
1274 */
1275 rdtsc_barrier();
1276 ret = (cycle_t)vget_cycles();
1277
1278 last = pvclock_gtod_data.clock.cycle_last;
1279
1280 if (likely(ret >= last))
1281 return ret;
1282
1283 /*
1284 * GCC likes to generate cmov here, but this branch is extremely
1285 * predictable (it's just a funciton of time and the likely is
1286 * very likely) and there's a data dependence, so force GCC
1287 * to generate a branch instead. I don't barrier() because
1288 * we don't actually need a barrier, and if this function
1289 * ever gets inlined it will generate worse code.
1290 */
1291 asm volatile ("");
1292 return last;
1293}
1294
1295static inline u64 vgettsc(cycle_t *cycle_now)
1296{
1297 long v;
1298 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1299
1300 *cycle_now = read_tsc();
1301
1302 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1303 return v * gtod->clock.mult;
1304}
1305
1306static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1307{
1308 unsigned long seq;
1309 u64 ns;
1310 int mode;
1311 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1312
1313 ts->tv_nsec = 0;
1314 do {
1315 seq = read_seqcount_begin(&gtod->seq);
1316 mode = gtod->clock.vclock_mode;
1317 ts->tv_sec = gtod->monotonic_time_sec;
1318 ns = gtod->monotonic_time_snsec;
1319 ns += vgettsc(cycle_now);
1320 ns >>= gtod->clock.shift;
1321 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1322 timespec_add_ns(ts, ns);
1323
1324 return mode;
1325}
1326
1327/* returns true if host is using tsc clocksource */
1328static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1329{
1330 struct timespec ts;
1331
1332 /* checked again under seqlock below */
1333 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1334 return false;
1335
1336 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1337 return false;
1338
1339 monotonic_to_bootbased(&ts);
1340 *kernel_ns = timespec_to_ns(&ts);
1341
1342 return true;
1343}
1344#endif
1345
1346/*
1347 *
b48aa97e
MT		 1348 * Assuming a stable TSC across physical CPUS, and a stable TSC
1349 * across virtual CPUs, the following condition is possible.
1350 * Each numbered line represents an event visible to both
d828199e
MT		 1351 * CPUs at the next numbered event.
1352 *
1353 * "timespecX" represents host monotonic time. "tscX" represents
1354 * RDTSC value.
1355 *
1356 * VCPU0 on CPU0 | VCPU1 on CPU1
1357 *
1358 * 1. read timespec0,tsc0
1359 * 2. | timespec1 = timespec0 + N
1360 * | tsc1 = tsc0 + M
1361 * 3. transition to guest | transition to guest
1362 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1363 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1364 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1365 *
1366 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1367 *
1368 * - ret0 < ret1
1369 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1370 * ...
1371 * - 0 < N - M => M < N
1372 *
1373 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1374 * always the case (the difference between two distinct xtime instances
1375 * might be smaller then the difference between corresponding TSC reads,
1376 * when updating guest vcpus pvclock areas).
1377 *
1378 * To avoid that problem, do not allow visibility of distinct
1379 * system_timestamp/tsc_timestamp values simultaneously: use a master
1380 * copy of host monotonic time values. Update that master copy
1381 * in lockstep.
1382 *
b48aa97e 1383 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1384 *
1385 */
1386
1387static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1388{
1389#ifdef CONFIG_X86_64
1390 struct kvm_arch *ka = &kvm->arch;
1391 int vclock_mode;
b48aa97e
MT		 1392 bool host_tsc_clocksource, vcpus_matched;
1393
1394 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1395 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1396
1397 /*
1398 * If the host uses TSC clock, then passthrough TSC as stable
1399 * to the guest.
1400 */
b48aa97e 1401 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1402 &ka->master_kernel_ns,
1403 &ka->master_cycle_now);
1404
b48aa97e
MT		 1405 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1406
d828199e
MT		 1407 if (ka->use_master_clock)
1408 atomic_set(&kvm_guest_has_master_clock, 1);
1409
1410 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1411 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1412 vcpus_matched);
d828199e
MT		 1413#endif
1414}
1415
34c238a1 1416static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1417{
d828199e 1418 unsigned long flags, this_tsc_khz;
18068523 1419 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1420 struct kvm_arch *ka = &v->kvm->arch;
1d5f066e 1421 s64 kernel_ns, max_kernel_ns;
d828199e 1422 u64 tsc_timestamp, host_tsc;
0b79459b 1423 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1424 u8 pvclock_flags;
d828199e
MT		 1425 bool use_master_clock;
1426
1427 kernel_ns = 0;
1428 host_tsc = 0;
18068523 1429
d828199e
MT		 1430 /*
1431 * If the host uses TSC clock, then passthrough TSC as stable
1432 * to the guest.
1433 */
1434 spin_lock(&ka->pvclock_gtod_sync_lock);
1435 use_master_clock = ka->use_master_clock;
1436 if (use_master_clock) {
1437 host_tsc = ka->master_cycle_now;
1438 kernel_ns = ka->master_kernel_ns;
1439 }
1440 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1441
1442 /* Keep irq disabled to prevent changes to the clock */
1443 local_irq_save(flags);
1444 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1445 if (unlikely(this_tsc_khz == 0)) {
1446 local_irq_restore(flags);
1447 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1448 return 1;
1449 }
d828199e
MT		 1450 if (!use_master_clock) {
1451 host_tsc = native_read_tsc();
1452 kernel_ns = get_kernel_ns();
1453 }
1454
1455 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1456
c285545f
ZA		 1457 /*
1458 * We may have to catch up the TSC to match elapsed wall clock
1459 * time for two reasons, even if kvmclock is used.
1460 * 1) CPU could have been running below the maximum TSC rate
1461 * 2) Broken TSC compensation resets the base at each VCPU
1462 * entry to avoid unknown leaps of TSC even when running
1463 * again on the same CPU. This may cause apparent elapsed
1464 * time to disappear, and the guest to stand still or run
1465 * very slowly.
1466 */
1467 if (vcpu->tsc_catchup) {
1468 u64 tsc = compute_guest_tsc(v, kernel_ns);
1469 if (tsc > tsc_timestamp) {
f1e2b260 1470 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1471 tsc_timestamp = tsc;
1472 }
50d0a0f9
GH		 1473 }
1474
18068523
GOC		 1475 local_irq_restore(flags);
1476
0b79459b 1477 if (!vcpu->pv_time_enabled)
c285545f 1478 return 0;
18068523 1479
1d5f066e
ZA		 1480 /*
1481 * Time as measured by the TSC may go backwards when resetting the base
1482 * tsc_timestamp. The reason for this is that the TSC resolution is
1483 * higher than the resolution of the other clock scales. Thus, many
1484 * possible measurments of the TSC correspond to one measurement of any
1485 * other clock, and so a spread of values is possible. This is not a
1486 * problem for the computation of the nanosecond clock; with TSC rates
1487 * around 1GHZ, there can only be a few cycles which correspond to one
1488 * nanosecond value, and any path through this code will inevitably
1489 * take longer than that. However, with the kernel_ns value itself,
1490 * the precision may be much lower, down to HZ granularity. If the
1491 * first sampling of TSC against kernel_ns ends in the low part of the
1492 * range, and the second in the high end of the range, we can get:
1493 *
1494 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1495 *
1496 * As the sampling errors potentially range in the thousands of cycles,
1497 * it is possible such a time value has already been observed by the
1498 * guest. To protect against this, we must compute the system time as
1499 * observed by the guest and ensure the new system time is greater.
1500 */
1501 max_kernel_ns = 0;
b183aa58 1502 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1503 max_kernel_ns = vcpu->last_guest_tsc -
1504 vcpu->hv_clock.tsc_timestamp;
1505 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1506 vcpu->hv_clock.tsc_to_system_mul,
1507 vcpu->hv_clock.tsc_shift);
1508 max_kernel_ns += vcpu->last_kernel_ns;
1509 }
afbcf7ab 1510
e48672fa 1511 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1512 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1513 &vcpu->hv_clock.tsc_shift,
1514 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1515 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1516 }
1517
d828199e
MT		 1518 /* with a master <monotonic time, tsc value> tuple,
1519 * pvclock clock reads always increase at the (scaled) rate
1520 * of guest TSC - no need to deal with sampling errors.
1521 */
1522 if (!use_master_clock) {
1523 if (max_kernel_ns > kernel_ns)
1524 kernel_ns = max_kernel_ns;
1525 }
8cfdc000 1526 /* With all the info we got, fill in the values */
1d5f066e 1527 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1528 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1529 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1530 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1531
18068523
GOC		 1532 /*
1533 * The interface expects us to write an even number signaling that the
1534 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1535 * state, we just increase by 2 at the end.
18068523 1536 */
50d0a0f9 1537 vcpu->hv_clock.version += 2;
18068523 1538
0b79459b
AH		 1539 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1540 &guest_hv_clock, sizeof(guest_hv_clock))))
1541 return 0;
78c0337a
MT		 1542
1543 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1544 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1545
1546 if (vcpu->pvclock_set_guest_stopped_request) {
1547 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1548 vcpu->pvclock_set_guest_stopped_request = false;
1549 }
1550
d828199e
MT		 1551 /* If the host uses TSC clocksource, then it is stable */
1552 if (use_master_clock)
1553 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1554
78c0337a
MT		 1555 vcpu->hv_clock.flags = pvclock_flags;
1556
0b79459b
AH		 1557 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1558 &vcpu->hv_clock,
1559 sizeof(vcpu->hv_clock));
8cfdc000 1560 return 0;
c8076604
GH		 1561}
1562
9ba075a6
AK		 1563static bool msr_mtrr_valid(unsigned msr)
1564{
1565 switch (msr) {
1566 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1567 case MSR_MTRRfix64K_00000:
1568 case MSR_MTRRfix16K_80000:
1569 case MSR_MTRRfix16K_A0000:
1570 case MSR_MTRRfix4K_C0000:
1571 case MSR_MTRRfix4K_C8000:
1572 case MSR_MTRRfix4K_D0000:
1573 case MSR_MTRRfix4K_D8000:
1574 case MSR_MTRRfix4K_E0000:
1575 case MSR_MTRRfix4K_E8000:
1576 case MSR_MTRRfix4K_F0000:
1577 case MSR_MTRRfix4K_F8000:
1578 case MSR_MTRRdefType:
1579 case MSR_IA32_CR_PAT:
1580 return true;
1581 case 0x2f8:
1582 return true;
1583 }
1584 return false;
1585}
1586
d6289b93
MT		 1587static bool valid_pat_type(unsigned t)
1588{
1589 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1590}
1591
1592static bool valid_mtrr_type(unsigned t)
1593{
1594 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1595}
1596
1597static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1598{
1599 int i;
1600
1601 if (!msr_mtrr_valid(msr))
1602 return false;
1603
1604 if (msr == MSR_IA32_CR_PAT) {
1605 for (i = 0; i < 8; i++)
1606 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1607 return false;
1608 return true;
1609 } else if (msr == MSR_MTRRdefType) {
1610 if (data & ~0xcff)
1611 return false;
1612 return valid_mtrr_type(data & 0xff);
1613 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1614 for (i = 0; i < 8 ; i++)
1615 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1616 return false;
1617 return true;
1618 }
1619
1620 /* variable MTRRs */
1621 return valid_mtrr_type(data & 0xff);
1622}
1623
9ba075a6
AK		 1624static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1625{
0bed3b56
SY		 1626 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1627
d6289b93 1628 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1629 return 1;
1630
0bed3b56
SY		 1631 if (msr == MSR_MTRRdefType) {
1632 vcpu->arch.mtrr_state.def_type = data;
1633 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1634 } else if (msr == MSR_MTRRfix64K_00000)
1635 p[0] = data;
1636 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1637 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1638 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1639 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1640 else if (msr == MSR_IA32_CR_PAT)
1641 vcpu->arch.pat = data;
1642 else { /* Variable MTRRs */
1643 int idx, is_mtrr_mask;
1644 u64 *pt;
1645
1646 idx = (msr - 0x200) / 2;
1647 is_mtrr_mask = msr - 0x200 - 2 * idx;
1648 if (!is_mtrr_mask)
1649 pt =
1650 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1651 else
1652 pt =
1653 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1654 *pt = data;
1655 }
1656
1657 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1658 return 0;
1659}
15c4a640 1660
890ca9ae 1661static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1662{
890ca9ae
HY		 1663 u64 mcg_cap = vcpu->arch.mcg_cap;
1664 unsigned bank_num = mcg_cap & 0xff;
1665
15c4a640 1666 switch (msr) {
15c4a640 1667 case MSR_IA32_MCG_STATUS:
890ca9ae 1668 vcpu->arch.mcg_status = data;
15c4a640 1669 break;
c7ac679c 1670 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1671 if (!(mcg_cap & MCG_CTL_P))
1672 return 1;
1673 if (data != 0 && data != ~(u64)0)
1674 return -1;
1675 vcpu->arch.mcg_ctl = data;
1676 break;
1677 default:
1678 if (msr >= MSR_IA32_MC0_CTL &&
1679 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1680 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1681 /* only 0 or all 1s can be written to IA32_MCi_CTL
1682 * some Linux kernels though clear bit 10 in bank 4 to
1683 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1684 * this to avoid an uncatched #GP in the guest
1685 */
890ca9ae 1686 if ((offset & 0x3) == 0 &&
114be429 1687 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1688 return -1;
1689 vcpu->arch.mce_banks[offset] = data;
1690 break;
1691 }
1692 return 1;
1693 }
1694 return 0;
1695}
1696
ffde22ac
ES		 1697static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1698{
1699 struct kvm *kvm = vcpu->kvm;
1700 int lm = is_long_mode(vcpu);
1701 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1702 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1703 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1704 : kvm->arch.xen_hvm_config.blob_size_32;
1705 u32 page_num = data & ~PAGE_MASK;
1706 u64 page_addr = data & PAGE_MASK;
1707 u8 *page;
1708 int r;
1709
1710 r = -E2BIG;
1711 if (page_num >= blob_size)
1712 goto out;
1713 r = -ENOMEM;
ff5c2c03
SL		 1714 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1715 if (IS_ERR(page)) {
1716 r = PTR_ERR(page);
ffde22ac 1717 goto out;
ff5c2c03 1718 }
ffde22ac
ES		 1719 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1720 goto out_free;
1721 r = 0;
1722out_free:
1723 kfree(page);
1724out:
1725 return r;
1726}
1727
55cd8e5a
GN		 1728static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1729{
1730 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1731}
1732
1733static bool kvm_hv_msr_partition_wide(u32 msr)
1734{
1735 bool r = false;
1736 switch (msr) {
1737 case HV_X64_MSR_GUEST_OS_ID:
1738 case HV_X64_MSR_HYPERCALL:
1739 r = true;
1740 break;
1741 }
1742
1743 return r;
1744}
1745
1746static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1747{
1748 struct kvm *kvm = vcpu->kvm;
1749
1750 switch (msr) {
1751 case HV_X64_MSR_GUEST_OS_ID:
1752 kvm->arch.hv_guest_os_id = data;
1753 /* setting guest os id to zero disables hypercall page */
1754 if (!kvm->arch.hv_guest_os_id)
1755 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1756 break;
1757 case HV_X64_MSR_HYPERCALL: {
1758 u64 gfn;
1759 unsigned long addr;
1760 u8 instructions[4];
1761
1762 /* if guest os id is not set hypercall should remain disabled */
1763 if (!kvm->arch.hv_guest_os_id)
1764 break;
1765 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1766 kvm->arch.hv_hypercall = data;
1767 break;
1768 }
1769 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1770 addr = gfn_to_hva(kvm, gfn);
1771 if (kvm_is_error_hva(addr))
1772 return 1;
1773 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1774 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1775 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1776 return 1;
1777 kvm->arch.hv_hypercall = data;
1778 break;
1779 }
1780 default:
a737f256
CD		 1781 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1782 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1783 return 1;
1784 }
1785 return 0;
1786}
1787
1788static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1789{
10388a07
GN		 1790 switch (msr) {
1791 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1792 unsigned long addr;
55cd8e5a 1793
10388a07
GN		 1794 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1795 vcpu->arch.hv_vapic = data;
1796 break;
1797 }
1798 addr = gfn_to_hva(vcpu->kvm, data >>
1799 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1800 if (kvm_is_error_hva(addr))
1801 return 1;
8b0cedff 1802 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1803 return 1;
1804 vcpu->arch.hv_vapic = data;
1805 break;
1806 }
1807 case HV_X64_MSR_EOI:
1808 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1809 case HV_X64_MSR_ICR:
1810 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1811 case HV_X64_MSR_TPR:
1812 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1813 default:
a737f256
CD		 1814 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1815 "data 0x%llx\n", msr, data);
10388a07
GN		 1816 return 1;
1817 }
1818
1819 return 0;
55cd8e5a
GN		 1820}
1821
344d9588
GN		 1822static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1823{
1824 gpa_t gpa = data & ~0x3f;
1825
4a969980 1826 /* Bits 2:5 are reserved, Should be zero */
6adba527 1827 if (data & 0x3c)
344d9588
GN		 1828 return 1;
1829
1830 vcpu->arch.apf.msr_val = data;
1831
1832 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1833 kvm_clear_async_pf_completion_queue(vcpu);
1834 kvm_async_pf_hash_reset(vcpu);
1835 return 0;
1836 }
1837
1838 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1839 return 1;
1840
6adba527 1841 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1842 kvm_async_pf_wakeup_all(vcpu);
1843 return 0;
1844}
1845
12f9a48f
GC		 1846static void kvmclock_reset(struct kvm_vcpu *vcpu)
1847{
0b79459b 1848 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1849}
1850
c9aaa895
GC		 1851static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1852{
1853 u64 delta;
1854
1855 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1856 return;
1857
1858 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1859 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1860 vcpu->arch.st.accum_steal = delta;
1861}
1862
1863static void record_steal_time(struct kvm_vcpu *vcpu)
1864{
1865 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1866 return;
1867
1868 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1869 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1870 return;
1871
1872 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1873 vcpu->arch.st.steal.version += 2;
1874 vcpu->arch.st.accum_steal = 0;
1875
1876 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1877 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1878}
1879
8fe8ab46 1880int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1881{
5753785f 1882 bool pr = false;
8fe8ab46
WA		 1883 u32 msr = msr_info->index;
1884 u64 data = msr_info->data;
5753785f 1885
15c4a640 1886 switch (msr) {
2e32b719
BP		 1887 case MSR_AMD64_NB_CFG:
1888 case MSR_IA32_UCODE_REV:
1889 case MSR_IA32_UCODE_WRITE:
1890 case MSR_VM_HSAVE_PA:
1891 case MSR_AMD64_PATCH_LOADER:
1892 case MSR_AMD64_BU_CFG2:
1893 break;
1894
15c4a640 1895 case MSR_EFER:
b69e8cae 1896 return set_efer(vcpu, data);
8f1589d9
AP		 1897 case MSR_K7_HWCR:
1898 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1899 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1900 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1901 if (data != 0) {
a737f256
CD		 1902 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1903 data);
8f1589d9
AP		 1904 return 1;
1905 }
15c4a640 1906 break;
f7c6d140
AP		 1907 case MSR_FAM10H_MMIO_CONF_BASE:
1908 if (data != 0) {
a737f256
CD		 1909 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1910 "0x%llx\n", data);
f7c6d140
AP		 1911 return 1;
1912 }
15c4a640 1913 break;
b5e2fec0
AG		 1914 case MSR_IA32_DEBUGCTLMSR:
1915 if (!data) {
1916 /* We support the non-activated case already */
1917 break;
1918 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1919 /* Values other than LBR and BTF are vendor-specific,
1920 thus reserved and should throw a #GP */
1921 return 1;
1922 }
a737f256
CD		 1923 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1924 __func__, data);
b5e2fec0 1925 break;
9ba075a6
AK		 1926 case 0x200 ... 0x2ff:
1927 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1928 case MSR_IA32_APICBASE:
1929 kvm_set_apic_base(vcpu, data);
1930 break;
0105d1a5
GN		 1931 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1932 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1933 case MSR_IA32_TSCDEADLINE:
1934 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1935 break;
ba904635
WA		 1936 case MSR_IA32_TSC_ADJUST:
1937 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1938 if (!msr_info->host_initiated) {
1939 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1940 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1941 }
1942 vcpu->arch.ia32_tsc_adjust_msr = data;
1943 }
1944 break;
15c4a640 1945 case MSR_IA32_MISC_ENABLE:
ad312c7c 1946 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1947 break;
11c6bffa 1948 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1949 case MSR_KVM_WALL_CLOCK:
1950 vcpu->kvm->arch.wall_clock = data;
1951 kvm_write_wall_clock(vcpu->kvm, data);
1952 break;
11c6bffa 1953 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1954 case MSR_KVM_SYSTEM_TIME: {
0b79459b 1955 u64 gpa_offset;
12f9a48f 1956 kvmclock_reset(vcpu);
18068523
GOC		 1957
1958 vcpu->arch.time = data;
c285545f 1959 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1960
1961 /* we verify if the enable bit is set... */
1962 if (!(data & 1))
1963 break;
1964
0b79459b 1965 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 1966
c300aa64 1967 /* Check that the address is 32-byte aligned. */
0b79459b 1968 if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1))
c300aa64 1969 break;
18068523 1970
0b79459b
AH		 1971 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1972 &vcpu->arch.pv_time, data & ~1ULL))
1973 vcpu->arch.pv_time_enabled = false;
1974 else
1975 vcpu->arch.pv_time_enabled = true;
32cad84f 1976
18068523
GOC		 1977 break;
1978 }
344d9588
GN		 1979 case MSR_KVM_ASYNC_PF_EN:
1980 if (kvm_pv_enable_async_pf(vcpu, data))
1981 return 1;
1982 break;
c9aaa895
GC		 1983 case MSR_KVM_STEAL_TIME:
1984
1985 if (unlikely(!sched_info_on()))
1986 return 1;
1987
1988 if (data & KVM_STEAL_RESERVED_MASK)
1989 return 1;
1990
1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1992 data & KVM_STEAL_VALID_BITS))
1993 return 1;
1994
1995 vcpu->arch.st.msr_val = data;
1996
1997 if (!(data & KVM_MSR_ENABLED))
1998 break;
1999
2000 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2001
2002 preempt_disable();
2003 accumulate_steal_time(vcpu);
2004 preempt_enable();
2005
2006 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2007
2008 break;
ae7a2a3f
MT		 2009 case MSR_KVM_PV_EOI_EN:
2010 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2011 return 1;
2012 break;
c9aaa895 2013
890ca9ae
HY		 2014 case MSR_IA32_MCG_CTL:
2015 case MSR_IA32_MCG_STATUS:
2016 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2017 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2018
2019 /* Performance counters are not protected by a CPUID bit,
2020 * so we should check all of them in the generic path for the sake of
2021 * cross vendor migration.
2022 * Writing a zero into the event select MSRs disables them,
2023 * which we perfectly emulate ;-). Any other value should be at least
2024 * reported, some guests depend on them.
2025 */
71db6023
AP		 2026 case MSR_K7_EVNTSEL0:
2027 case MSR_K7_EVNTSEL1:
2028 case MSR_K7_EVNTSEL2:
2029 case MSR_K7_EVNTSEL3:
2030 if (data != 0)
a737f256
CD		 2031 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2032 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2033 break;
2034 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2035 * so we ignore writes to make it happy.
2036 */
71db6023
AP		 2037 case MSR_K7_PERFCTR0:
2038 case MSR_K7_PERFCTR1:
2039 case MSR_K7_PERFCTR2:
2040 case MSR_K7_PERFCTR3:
a737f256
CD		 2041 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2042 "0x%x data 0x%llx\n", msr, data);
71db6023 2043 break;
5753785f
GN		 2044 case MSR_P6_PERFCTR0:
2045 case MSR_P6_PERFCTR1:
2046 pr = true;
2047 case MSR_P6_EVNTSEL0:
2048 case MSR_P6_EVNTSEL1:
2049 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2050 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2051
2052 if (pr || data != 0)
a737f256
CD		 2053 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2054 "0x%x data 0x%llx\n", msr, data);
5753785f 2055 break;
84e0cefa
JS		 2056 case MSR_K7_CLK_CTL:
2057 /*
2058 * Ignore all writes to this no longer documented MSR.
2059 * Writes are only relevant for old K7 processors,
2060 * all pre-dating SVM, but a recommended workaround from
4a969980 2061 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2062 * affected processor models on the command line, hence
2063 * the need to ignore the workaround.
2064 */
2065 break;
55cd8e5a
GN		 2066 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2067 if (kvm_hv_msr_partition_wide(msr)) {
2068 int r;
2069 mutex_lock(&vcpu->kvm->lock);
2070 r = set_msr_hyperv_pw(vcpu, msr, data);
2071 mutex_unlock(&vcpu->kvm->lock);
2072 return r;
2073 } else
2074 return set_msr_hyperv(vcpu, msr, data);
2075 break;
91c9c3ed 2076 case MSR_IA32_BBL_CR_CTL3:
2077 /* Drop writes to this legacy MSR -- see rdmsr
2078 * counterpart for further detail.
2079 */
a737f256 2080 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2081 break;
2b036c6b
BO		 2082 case MSR_AMD64_OSVW_ID_LENGTH:
2083 if (!guest_cpuid_has_osvw(vcpu))
2084 return 1;
2085 vcpu->arch.osvw.length = data;
2086 break;
2087 case MSR_AMD64_OSVW_STATUS:
2088 if (!guest_cpuid_has_osvw(vcpu))
2089 return 1;
2090 vcpu->arch.osvw.status = data;
2091 break;
15c4a640 2092 default:
ffde22ac
ES		 2093 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2094 return xen_hvm_config(vcpu, data);
f5132b01 2095 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2096 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2097 if (!ignore_msrs) {
a737f256
CD		 2098 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2099 msr, data);
ed85c068
AP		 2100 return 1;
2101 } else {
a737f256
CD		 2102 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2103 msr, data);
ed85c068
AP		 2104 break;
2105 }
15c4a640
CO		 2106 }
2107 return 0;
2108}
2109EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2110
2111
2112/*
2113 * Reads an msr value (of 'msr_index') into 'pdata'.
2114 * Returns 0 on success, non-0 otherwise.
2115 * Assumes vcpu_load() was already called.
2116 */
2117int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2118{
2119 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2120}
2121
9ba075a6
AK		 2122static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2123{
0bed3b56
SY		 2124 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2125
9ba075a6
AK		 2126 if (!msr_mtrr_valid(msr))
2127 return 1;
2128
0bed3b56
SY		 2129 if (msr == MSR_MTRRdefType)
2130 *pdata = vcpu->arch.mtrr_state.def_type +
2131 (vcpu->arch.mtrr_state.enabled << 10);
2132 else if (msr == MSR_MTRRfix64K_00000)
2133 *pdata = p[0];
2134 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2135 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2136 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2137 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2138 else if (msr == MSR_IA32_CR_PAT)
2139 *pdata = vcpu->arch.pat;
2140 else { /* Variable MTRRs */
2141 int idx, is_mtrr_mask;
2142 u64 *pt;
2143
2144 idx = (msr - 0x200) / 2;
2145 is_mtrr_mask = msr - 0x200 - 2 * idx;
2146 if (!is_mtrr_mask)
2147 pt =
2148 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2149 else
2150 pt =
2151 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2152 *pdata = *pt;
2153 }
2154
9ba075a6
AK		 2155 return 0;
2156}
2157
890ca9ae 2158static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2159{
2160 u64 data;
890ca9ae
HY		 2161 u64 mcg_cap = vcpu->arch.mcg_cap;
2162 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2163
2164 switch (msr) {
15c4a640
CO		 2165 case MSR_IA32_P5_MC_ADDR:
2166 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2167 data = 0;
2168 break;
15c4a640 2169 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2170 data = vcpu->arch.mcg_cap;
2171 break;
c7ac679c 2172 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2173 if (!(mcg_cap & MCG_CTL_P))
2174 return 1;
2175 data = vcpu->arch.mcg_ctl;
2176 break;
2177 case MSR_IA32_MCG_STATUS:
2178 data = vcpu->arch.mcg_status;
2179 break;
2180 default:
2181 if (msr >= MSR_IA32_MC0_CTL &&
2182 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2183 u32 offset = msr - MSR_IA32_MC0_CTL;
2184 data = vcpu->arch.mce_banks[offset];
2185 break;
2186 }
2187 return 1;
2188 }
2189 *pdata = data;
2190 return 0;
2191}
2192
55cd8e5a
GN		 2193static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2194{
2195 u64 data = 0;
2196 struct kvm *kvm = vcpu->kvm;
2197
2198 switch (msr) {
2199 case HV_X64_MSR_GUEST_OS_ID:
2200 data = kvm->arch.hv_guest_os_id;
2201 break;
2202 case HV_X64_MSR_HYPERCALL:
2203 data = kvm->arch.hv_hypercall;
2204 break;
2205 default:
a737f256 2206 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2207 return 1;
2208 }
2209
2210 *pdata = data;
2211 return 0;
2212}
2213
2214static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2215{
2216 u64 data = 0;
2217
2218 switch (msr) {
2219 case HV_X64_MSR_VP_INDEX: {
2220 int r;
2221 struct kvm_vcpu *v;
2222 kvm_for_each_vcpu(r, v, vcpu->kvm)
2223 if (v == vcpu)
2224 data = r;
2225 break;
2226 }
10388a07
GN		 2227 case HV_X64_MSR_EOI:
2228 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2229 case HV_X64_MSR_ICR:
2230 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2231 case HV_X64_MSR_TPR:
2232 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2233 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2234 data = vcpu->arch.hv_vapic;
2235 break;
55cd8e5a 2236 default:
a737f256 2237 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2238 return 1;
2239 }
2240 *pdata = data;
2241 return 0;
2242}
2243
890ca9ae
HY		 2244int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2245{
2246 u64 data;
2247
2248 switch (msr) {
890ca9ae 2249 case MSR_IA32_PLATFORM_ID:
15c4a640 2250 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2251 case MSR_IA32_DEBUGCTLMSR:
2252 case MSR_IA32_LASTBRANCHFROMIP:
2253 case MSR_IA32_LASTBRANCHTOIP:
2254 case MSR_IA32_LASTINTFROMIP:
2255 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2256 case MSR_K8_SYSCFG:
2257 case MSR_K7_HWCR:
61a6bd67 2258 case MSR_VM_HSAVE_PA:
9e699624 2259 case MSR_K7_EVNTSEL0:
1f3ee616 2260 case MSR_K7_PERFCTR0:
1fdbd48c 2261 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2262 case MSR_AMD64_NB_CFG:
f7c6d140 2263 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2264 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2265 data = 0;
2266 break;
5753785f
GN		 2267 case MSR_P6_PERFCTR0:
2268 case MSR_P6_PERFCTR1:
2269 case MSR_P6_EVNTSEL0:
2270 case MSR_P6_EVNTSEL1:
2271 if (kvm_pmu_msr(vcpu, msr))
2272 return kvm_pmu_get_msr(vcpu, msr, pdata);
2273 data = 0;
2274 break;
742bc670
MT		 2275 case MSR_IA32_UCODE_REV:
2276 data = 0x100000000ULL;
2277 break;
9ba075a6
AK		 2278 case MSR_MTRRcap:
2279 data = 0x500 | KVM_NR_VAR_MTRR;
2280 break;
2281 case 0x200 ... 0x2ff:
2282 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2283 case 0xcd: /* fsb frequency */
2284 data = 3;
2285 break;
7b914098
JS		 2286 /*
2287 * MSR_EBC_FREQUENCY_ID
2288 * Conservative value valid for even the basic CPU models.
2289 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2290 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2291 * and 266MHz for model 3, or 4. Set Core Clock
2292 * Frequency to System Bus Frequency Ratio to 1 (bits
2293 * 31:24) even though these are only valid for CPU
2294 * models > 2, however guests may end up dividing or
2295 * multiplying by zero otherwise.
2296 */
2297 case MSR_EBC_FREQUENCY_ID:
2298 data = 1 << 24;
2299 break;
15c4a640
CO		 2300 case MSR_IA32_APICBASE:
2301 data = kvm_get_apic_base(vcpu);
2302 break;
0105d1a5
GN		 2303 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2304 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2305 break;
a3e06bbe
LJ		 2306 case MSR_IA32_TSCDEADLINE:
2307 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2308 break;
ba904635
WA		 2309 case MSR_IA32_TSC_ADJUST:
2310 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2311 break;
15c4a640 2312 case MSR_IA32_MISC_ENABLE:
ad312c7c 2313 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2314 break;
847f0ad8
AG		 2315 case MSR_IA32_PERF_STATUS:
2316 /* TSC increment by tick */
2317 data = 1000ULL;
2318 /* CPU multiplier */
2319 data |= (((uint64_t)4ULL) << 40);
2320 break;
15c4a640 2321 case MSR_EFER:
f6801dff 2322 data = vcpu->arch.efer;
15c4a640 2323 break;
18068523 2324 case MSR_KVM_WALL_CLOCK:
11c6bffa 2325 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2326 data = vcpu->kvm->arch.wall_clock;
2327 break;
2328 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2329 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2330 data = vcpu->arch.time;
2331 break;
344d9588
GN		 2332 case MSR_KVM_ASYNC_PF_EN:
2333 data = vcpu->arch.apf.msr_val;
2334 break;
c9aaa895
GC		 2335 case MSR_KVM_STEAL_TIME:
2336 data = vcpu->arch.st.msr_val;
2337 break;
1d92128f
MT		 2338 case MSR_KVM_PV_EOI_EN:
2339 data = vcpu->arch.pv_eoi.msr_val;
2340 break;
890ca9ae
HY		 2341 case MSR_IA32_P5_MC_ADDR:
2342 case MSR_IA32_P5_MC_TYPE:
2343 case MSR_IA32_MCG_CAP:
2344 case MSR_IA32_MCG_CTL:
2345 case MSR_IA32_MCG_STATUS:
2346 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2347 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2348 case MSR_K7_CLK_CTL:
2349 /*
2350 * Provide expected ramp-up count for K7. All other
2351 * are set to zero, indicating minimum divisors for
2352 * every field.
2353 *
2354 * This prevents guest kernels on AMD host with CPU
2355 * type 6, model 8 and higher from exploding due to
2356 * the rdmsr failing.
2357 */
2358 data = 0x20000000;
2359 break;
55cd8e5a
GN		 2360 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2361 if (kvm_hv_msr_partition_wide(msr)) {
2362 int r;
2363 mutex_lock(&vcpu->kvm->lock);
2364 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2365 mutex_unlock(&vcpu->kvm->lock);
2366 return r;
2367 } else
2368 return get_msr_hyperv(vcpu, msr, pdata);
2369 break;
91c9c3ed 2370 case MSR_IA32_BBL_CR_CTL3:
2371 /* This legacy MSR exists but isn't fully documented in current
2372 * silicon. It is however accessed by winxp in very narrow
2373 * scenarios where it sets bit #19, itself documented as
2374 * a "reserved" bit. Best effort attempt to source coherent
2375 * read data here should the balance of the register be
2376 * interpreted by the guest:
2377 *
2378 * L2 cache control register 3: 64GB range, 256KB size,
2379 * enabled, latency 0x1, configured
2380 */
2381 data = 0xbe702111;
2382 break;
2b036c6b
BO		 2383 case MSR_AMD64_OSVW_ID_LENGTH:
2384 if (!guest_cpuid_has_osvw(vcpu))
2385 return 1;
2386 data = vcpu->arch.osvw.length;
2387 break;
2388 case MSR_AMD64_OSVW_STATUS:
2389 if (!guest_cpuid_has_osvw(vcpu))
2390 return 1;
2391 data = vcpu->arch.osvw.status;
2392 break;
15c4a640 2393 default:
f5132b01
GN		 2394 if (kvm_pmu_msr(vcpu, msr))
2395 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2396 if (!ignore_msrs) {
a737f256 2397 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2398 return 1;
2399 } else {
a737f256 2400 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2401 data = 0;
2402 }
2403 break;
15c4a640
CO		 2404 }
2405 *pdata = data;
2406 return 0;
2407}
2408EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2409
313a3dc7
CO		 2410/*
2411 * Read or write a bunch of msrs. All parameters are kernel addresses.
2412 *
2413 * @return number of msrs set successfully.
2414 */
2415static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2416 struct kvm_msr_entry *entries,
2417 int (*do_msr)(struct kvm_vcpu *vcpu,
2418 unsigned index, u64 *data))
2419{
f656ce01 2420 int i, idx;
313a3dc7 2421
f656ce01 2422 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2423 for (i = 0; i < msrs->nmsrs; ++i)
2424 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2425 break;
f656ce01 2426 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2427
313a3dc7
CO		 2428 return i;
2429}
2430
2431/*
2432 * Read or write a bunch of msrs. Parameters are user addresses.
2433 *
2434 * @return number of msrs set successfully.
2435 */
2436static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2437 int (*do_msr)(struct kvm_vcpu *vcpu,
2438 unsigned index, u64 *data),
2439 int writeback)
2440{
2441 struct kvm_msrs msrs;
2442 struct kvm_msr_entry *entries;
2443 int r, n;
2444 unsigned size;
2445
2446 r = -EFAULT;
2447 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2448 goto out;
2449
2450 r = -E2BIG;
2451 if (msrs.nmsrs >= MAX_IO_MSRS)
2452 goto out;
2453
313a3dc7 2454 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2455 entries = memdup_user(user_msrs->entries, size);
2456 if (IS_ERR(entries)) {
2457 r = PTR_ERR(entries);
313a3dc7 2458 goto out;
ff5c2c03 2459 }
313a3dc7
CO		 2460
2461 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2462 if (r < 0)
2463 goto out_free;
2464
2465 r = -EFAULT;
2466 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2467 goto out_free;
2468
2469 r = n;
2470
2471out_free:
7a73c028 2472 kfree(entries);
313a3dc7
CO		 2473out:
2474 return r;
2475}
2476
018d00d2
ZX		 2477int kvm_dev_ioctl_check_extension(long ext)
2478{
2479 int r;
2480
2481 switch (ext) {
2482 case KVM_CAP_IRQCHIP:
2483 case KVM_CAP_HLT:
2484 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2485 case KVM_CAP_SET_TSS_ADDR:
07716717 2486 case KVM_CAP_EXT_CPUID:
c8076604 2487 case KVM_CAP_CLOCKSOURCE:
7837699f 2488 case KVM_CAP_PIT:
a28e4f5a 2489 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2490 case KVM_CAP_MP_STATE:
ed848624 2491 case KVM_CAP_SYNC_MMU:
a355c85c 2492 case KVM_CAP_USER_NMI:
52d939a0 2493 case KVM_CAP_REINJECT_CONTROL:
4925663a 2494 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2495 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2496 case KVM_CAP_IRQFD:
d34e6b17 2497 case KVM_CAP_IOEVENTFD:
c5ff41ce 2498 case KVM_CAP_PIT2:
e9f42757 2499 case KVM_CAP_PIT_STATE2:
b927a3ce 2500 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2501 case KVM_CAP_XEN_HVM:
afbcf7ab 2502 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2503 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2504 case KVM_CAP_HYPERV:
10388a07 2505 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2506 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2507 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2508 case KVM_CAP_DEBUGREGS:
d2be1651 2509 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2510 case KVM_CAP_XSAVE:
344d9588 2511 case KVM_CAP_ASYNC_PF:
92a1f12d 2512 case KVM_CAP_GET_TSC_KHZ:
07700a94 2513 case KVM_CAP_PCI_2_3:
1c0b28c2 2514 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2515 case KVM_CAP_READONLY_MEM:
7a84428a 2516 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2517 r = 1;
2518 break;
542472b5
LV		 2519 case KVM_CAP_COALESCED_MMIO:
2520 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2521 break;
774ead3a
AK		 2522 case KVM_CAP_VAPIC:
2523 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2524 break;
f725230a 2525 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2526 r = KVM_SOFT_MAX_VCPUS;
2527 break;
2528 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2529 r = KVM_MAX_VCPUS;
2530 break;
a988b910 2531 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2532 r = KVM_USER_MEM_SLOTS;
a988b910 2533 break;
a68a6a72
MT		 2534 case KVM_CAP_PV_MMU: /* obsolete */
2535 r = 0;
2f333bcb 2536 break;
62c476c7 2537 case KVM_CAP_IOMMU:
a1b60c1c 2538 r = iommu_present(&pci_bus_type);
62c476c7 2539 break;
890ca9ae
HY		 2540 case KVM_CAP_MCE:
2541 r = KVM_MAX_MCE_BANKS;
2542 break;
2d5b5a66
SY		 2543 case KVM_CAP_XCRS:
2544 r = cpu_has_xsave;
2545 break;
92a1f12d
JR		 2546 case KVM_CAP_TSC_CONTROL:
2547 r = kvm_has_tsc_control;
2548 break;
4d25a066
JK		 2549 case KVM_CAP_TSC_DEADLINE_TIMER:
2550 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2551 break;
018d00d2
ZX		 2552 default:
2553 r = 0;
2554 break;
2555 }
2556 return r;
2557
2558}
2559
043405e1
CO		 2560long kvm_arch_dev_ioctl(struct file *filp,
2561 unsigned int ioctl, unsigned long arg)
2562{
2563 void __user *argp = (void __user *)arg;
2564 long r;
2565
2566 switch (ioctl) {
2567 case KVM_GET_MSR_INDEX_LIST: {
2568 struct kvm_msr_list __user *user_msr_list = argp;
2569 struct kvm_msr_list msr_list;
2570 unsigned n;
2571
2572 r = -EFAULT;
2573 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2574 goto out;
2575 n = msr_list.nmsrs;
2576 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2577 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2578 goto out;
2579 r = -E2BIG;
e125e7b6 2580 if (n < msr_list.nmsrs)
043405e1
CO		 2581 goto out;
2582 r = -EFAULT;
2583 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2584 num_msrs_to_save * sizeof(u32)))
2585 goto out;
e125e7b6 2586 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2587 &emulated_msrs,
2588 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2589 goto out;
2590 r = 0;
2591 break;
2592 }
674eea0f
AK		 2593 case KVM_GET_SUPPORTED_CPUID: {
2594 struct kvm_cpuid2 __user *cpuid_arg = argp;
2595 struct kvm_cpuid2 cpuid;
2596
2597 r = -EFAULT;
2598 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2599 goto out;
2600 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2601 cpuid_arg->entries);
674eea0f
AK		 2602 if (r)
2603 goto out;
2604
2605 r = -EFAULT;
2606 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2607 goto out;
2608 r = 0;
2609 break;
2610 }
890ca9ae
HY		 2611 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2612 u64 mce_cap;
2613
2614 mce_cap = KVM_MCE_CAP_SUPPORTED;
2615 r = -EFAULT;
2616 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2617 goto out;
2618 r = 0;
2619 break;
2620 }
043405e1
CO		 2621 default:
2622 r = -EINVAL;
2623 }
2624out:
2625 return r;
2626}
2627
f5f48ee1
SY		 2628static void wbinvd_ipi(void *garbage)
2629{
2630 wbinvd();
2631}
2632
2633static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2634{
2635 return vcpu->kvm->arch.iommu_domain &&
2636 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2637}
2638
313a3dc7
CO		 2639void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2640{
f5f48ee1
SY		 2641 /* Address WBINVD may be executed by guest */
2642 if (need_emulate_wbinvd(vcpu)) {
2643 if (kvm_x86_ops->has_wbinvd_exit())
2644 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2645 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2646 smp_call_function_single(vcpu->cpu,
2647 wbinvd_ipi, NULL, 1);
2648 }
2649
313a3dc7 2650 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2651
0dd6a6ed
ZA		 2652 /* Apply any externally detected TSC adjustments (due to suspend) */
2653 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2654 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2655 vcpu->arch.tsc_offset_adjustment = 0;
2656 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2657 }
8f6055cb 2658
48434c20 2659 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2660 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2661 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2662 if (tsc_delta < 0)
2663 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2664 if (check_tsc_unstable()) {
b183aa58
ZA		 2665 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2666 vcpu->arch.last_guest_tsc);
2667 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2668 vcpu->arch.tsc_catchup = 1;
c285545f 2669 }
d98d07ca
MT		 2670 /*
2671 * On a host with synchronized TSC, there is no need to update
2672 * kvmclock on vcpu->cpu migration
2673 */
2674 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2675 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2676 if (vcpu->cpu != cpu)
2677 kvm_migrate_timers(vcpu);
e48672fa 2678 vcpu->cpu = cpu;
6b7d7e76 2679 }
c9aaa895
GC		 2680
2681 accumulate_steal_time(vcpu);
2682 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2683}
2684
2685void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2686{
02daab21 2687 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2688 kvm_put_guest_fpu(vcpu);
6f526ec5 2689 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2690}
2691
313a3dc7
CO		 2692static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2693 struct kvm_lapic_state *s)
2694{
ad312c7c 2695 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2696
2697 return 0;
2698}
2699
2700static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2701 struct kvm_lapic_state *s)
2702{
64eb0620 2703 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2704 update_cr8_intercept(vcpu);
313a3dc7
CO		 2705
2706 return 0;
2707}
2708
f77bc6a4
ZX		 2709static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2710 struct kvm_interrupt *irq)
2711{
02cdb50f 2712 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2713 return -EINVAL;
2714 if (irqchip_in_kernel(vcpu->kvm))
2715 return -ENXIO;
f77bc6a4 2716
66fd3f7f 2717 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2718 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2719
f77bc6a4
ZX		 2720 return 0;
2721}
2722
c4abb7c9
JK		 2723static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2724{
c4abb7c9 2725 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2726
2727 return 0;
2728}
2729
b209749f
AK		 2730static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2731 struct kvm_tpr_access_ctl *tac)
2732{
2733 if (tac->flags)
2734 return -EINVAL;
2735 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2736 return 0;
2737}
2738
890ca9ae
HY		 2739static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2740 u64 mcg_cap)
2741{
2742 int r;
2743 unsigned bank_num = mcg_cap & 0xff, bank;
2744
2745 r = -EINVAL;
a9e38c3e 2746 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2747 goto out;
2748 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2749 goto out;
2750 r = 0;
2751 vcpu->arch.mcg_cap = mcg_cap;
2752 /* Init IA32_MCG_CTL to all 1s */
2753 if (mcg_cap & MCG_CTL_P)
2754 vcpu->arch.mcg_ctl = ~(u64)0;
2755 /* Init IA32_MCi_CTL to all 1s */
2756 for (bank = 0; bank < bank_num; bank++)
2757 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2758out:
2759 return r;
2760}
2761
2762static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2763 struct kvm_x86_mce *mce)
2764{
2765 u64 mcg_cap = vcpu->arch.mcg_cap;
2766 unsigned bank_num = mcg_cap & 0xff;
2767 u64 *banks = vcpu->arch.mce_banks;
2768
2769 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2770 return -EINVAL;
2771 /*
2772 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2773 * reporting is disabled
2774 */
2775 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2776 vcpu->arch.mcg_ctl != ~(u64)0)
2777 return 0;
2778 banks += 4 * mce->bank;
2779 /*
2780 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2781 * reporting is disabled for the bank
2782 */
2783 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2784 return 0;
2785 if (mce->status & MCI_STATUS_UC) {
2786 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2787 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2788 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2789 return 0;
2790 }
2791 if (banks[1] & MCI_STATUS_VAL)
2792 mce->status |= MCI_STATUS_OVER;
2793 banks[2] = mce->addr;
2794 banks[3] = mce->misc;
2795 vcpu->arch.mcg_status = mce->mcg_status;
2796 banks[1] = mce->status;
2797 kvm_queue_exception(vcpu, MC_VECTOR);
2798 } else if (!(banks[1] & MCI_STATUS_VAL)
2799 || !(banks[1] & MCI_STATUS_UC)) {
2800 if (banks[1] & MCI_STATUS_VAL)
2801 mce->status |= MCI_STATUS_OVER;
2802 banks[2] = mce->addr;
2803 banks[3] = mce->misc;
2804 banks[1] = mce->status;
2805 } else
2806 banks[1] |= MCI_STATUS_OVER;
2807 return 0;
2808}
2809
3cfc3092
JK		 2810static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2811 struct kvm_vcpu_events *events)
2812{
7460fb4a 2813 process_nmi(vcpu);
03b82a30
JK		 2814 events->exception.injected =
2815 vcpu->arch.exception.pending &&
2816 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2817 events->exception.nr = vcpu->arch.exception.nr;
2818 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2819 events->exception.pad = 0;
3cfc3092
JK		 2820 events->exception.error_code = vcpu->arch.exception.error_code;
2821
03b82a30
JK		 2822 events->interrupt.injected =
2823 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2824 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2825 events->interrupt.soft = 0;
48005f64
JK		 2826 events->interrupt.shadow =
2827 kvm_x86_ops->get_interrupt_shadow(vcpu,
2828 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2829
2830 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2831 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2832 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2833 events->nmi.pad = 0;
3cfc3092 2834
66450a21 2835 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2836
dab4b911 2837 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2838 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2839 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2840}
2841
2842static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2843 struct kvm_vcpu_events *events)
2844{
dab4b911 2845 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2846 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2847 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2848 return -EINVAL;
2849
7460fb4a 2850 process_nmi(vcpu);
3cfc3092
JK		 2851 vcpu->arch.exception.pending = events->exception.injected;
2852 vcpu->arch.exception.nr = events->exception.nr;
2853 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2854 vcpu->arch.exception.error_code = events->exception.error_code;
2855
2856 vcpu->arch.interrupt.pending = events->interrupt.injected;
2857 vcpu->arch.interrupt.nr = events->interrupt.nr;
2858 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2859 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2860 kvm_x86_ops->set_interrupt_shadow(vcpu,
2861 events->interrupt.shadow);
3cfc3092
JK		 2862
2863 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2864 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2865 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2866 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2867
66450a21
JK		 2868 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2869 kvm_vcpu_has_lapic(vcpu))
2870 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2871
3842d135
AK		 2872 kvm_make_request(KVM_REQ_EVENT, vcpu);
2873
3cfc3092
JK		 2874 return 0;
2875}
2876
a1efbe77
JK		 2877static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2878 struct kvm_debugregs *dbgregs)
2879{
a1efbe77
JK		 2880 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2881 dbgregs->dr6 = vcpu->arch.dr6;
2882 dbgregs->dr7 = vcpu->arch.dr7;
2883 dbgregs->flags = 0;
97e69aa6 2884 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2885}
2886
2887static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2888 struct kvm_debugregs *dbgregs)
2889{
2890 if (dbgregs->flags)
2891 return -EINVAL;
2892
a1efbe77
JK		 2893 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2894 vcpu->arch.dr6 = dbgregs->dr6;
2895 vcpu->arch.dr7 = dbgregs->dr7;
2896
a1efbe77
JK		 2897 return 0;
2898}
2899
2d5b5a66
SY		 2900static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2901 struct kvm_xsave *guest_xsave)
2902{
2903 if (cpu_has_xsave)
2904 memcpy(guest_xsave->region,
2905 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2906 xstate_size);
2d5b5a66
SY		 2907 else {
2908 memcpy(guest_xsave->region,
2909 &vcpu->arch.guest_fpu.state->fxsave,
2910 sizeof(struct i387_fxsave_struct));
2911 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2912 XSTATE_FPSSE;
2913 }
2914}
2915
2916static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2917 struct kvm_xsave *guest_xsave)
2918{
2919 u64 xstate_bv =
2920 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2921
2922 if (cpu_has_xsave)
2923 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2924 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2925 else {
2926 if (xstate_bv & ~XSTATE_FPSSE)
2927 return -EINVAL;
2928 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2929 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2930 }
2931 return 0;
2932}
2933
2934static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2935 struct kvm_xcrs *guest_xcrs)
2936{
2937 if (!cpu_has_xsave) {
2938 guest_xcrs->nr_xcrs = 0;
2939 return;
2940 }
2941
2942 guest_xcrs->nr_xcrs = 1;
2943 guest_xcrs->flags = 0;
2944 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2945 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2946}
2947
2948static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2949 struct kvm_xcrs *guest_xcrs)
2950{
2951 int i, r = 0;
2952
2953 if (!cpu_has_xsave)
2954 return -EINVAL;
2955
2956 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2957 return -EINVAL;
2958
2959 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2960 /* Only support XCR0 currently */
2961 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2962 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2963 guest_xcrs->xcrs[0].value);
2964 break;
2965 }
2966 if (r)
2967 r = -EINVAL;
2968 return r;
2969}
2970
1c0b28c2
EM		 2971/*
2972 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2973 * stopped by the hypervisor. This function will be called from the host only.
2974 * EINVAL is returned when the host attempts to set the flag for a guest that
2975 * does not support pv clocks.
2976 */
2977static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2978{
0b79459b 2979 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 2980 return -EINVAL;
51d59c6b 2981 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2982 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2983 return 0;
2984}
2985
313a3dc7
CO		 2986long kvm_arch_vcpu_ioctl(struct file *filp,
2987 unsigned int ioctl, unsigned long arg)
2988{
2989 struct kvm_vcpu *vcpu = filp->private_data;
2990 void __user *argp = (void __user *)arg;
2991 int r;
d1ac91d8
AK		 2992 union {
2993 struct kvm_lapic_state *lapic;
2994 struct kvm_xsave *xsave;
2995 struct kvm_xcrs *xcrs;
2996 void *buffer;
2997 } u;
2998
2999 u.buffer = NULL;
313a3dc7
CO		 3000 switch (ioctl) {
3001 case KVM_GET_LAPIC: {
2204ae3c
MT		 3002 r = -EINVAL;
3003 if (!vcpu->arch.apic)
3004 goto out;
d1ac91d8 3005 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3006
b772ff36 3007 r = -ENOMEM;
d1ac91d8 3008 if (!u.lapic)
b772ff36 3009 goto out;
d1ac91d8 3010 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3011 if (r)
3012 goto out;
3013 r = -EFAULT;
d1ac91d8 3014 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3015 goto out;
3016 r = 0;
3017 break;
3018 }
3019 case KVM_SET_LAPIC: {
2204ae3c
MT		 3020 r = -EINVAL;
3021 if (!vcpu->arch.apic)
3022 goto out;
ff5c2c03 3023 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3024 if (IS_ERR(u.lapic))
3025 return PTR_ERR(u.lapic);
ff5c2c03 3026
d1ac91d8 3027 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3028 break;
3029 }
f77bc6a4
ZX		 3030 case KVM_INTERRUPT: {
3031 struct kvm_interrupt irq;
3032
3033 r = -EFAULT;
3034 if (copy_from_user(&irq, argp, sizeof irq))
3035 goto out;
3036 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3037 break;
3038 }
c4abb7c9
JK		 3039 case KVM_NMI: {
3040 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3041 break;
3042 }
313a3dc7
CO		 3043 case KVM_SET_CPUID: {
3044 struct kvm_cpuid __user *cpuid_arg = argp;
3045 struct kvm_cpuid cpuid;
3046
3047 r = -EFAULT;
3048 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3049 goto out;
3050 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3051 break;
3052 }
07716717
DK		 3053 case KVM_SET_CPUID2: {
3054 struct kvm_cpuid2 __user *cpuid_arg = argp;
3055 struct kvm_cpuid2 cpuid;
3056
3057 r = -EFAULT;
3058 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3059 goto out;
3060 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3061 cpuid_arg->entries);
07716717
DK		 3062 break;
3063 }
3064 case KVM_GET_CPUID2: {
3065 struct kvm_cpuid2 __user *cpuid_arg = argp;
3066 struct kvm_cpuid2 cpuid;
3067
3068 r = -EFAULT;
3069 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3070 goto out;
3071 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3072 cpuid_arg->entries);
07716717
DK		 3073 if (r)
3074 goto out;
3075 r = -EFAULT;
3076 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3077 goto out;
3078 r = 0;
3079 break;
3080 }
313a3dc7
CO		 3081 case KVM_GET_MSRS:
3082 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3083 break;
3084 case KVM_SET_MSRS:
3085 r = msr_io(vcpu, argp, do_set_msr, 0);
3086 break;
b209749f
AK		 3087 case KVM_TPR_ACCESS_REPORTING: {
3088 struct kvm_tpr_access_ctl tac;
3089
3090 r = -EFAULT;
3091 if (copy_from_user(&tac, argp, sizeof tac))
3092 goto out;
3093 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3094 if (r)
3095 goto out;
3096 r = -EFAULT;
3097 if (copy_to_user(argp, &tac, sizeof tac))
3098 goto out;
3099 r = 0;
3100 break;
3101 };
b93463aa
AK		 3102 case KVM_SET_VAPIC_ADDR: {
3103 struct kvm_vapic_addr va;
3104
3105 r = -EINVAL;
3106 if (!irqchip_in_kernel(vcpu->kvm))
3107 goto out;
3108 r = -EFAULT;
3109 if (copy_from_user(&va, argp, sizeof va))
3110 goto out;
3111 r = 0;
3112 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3113 break;
3114 }
890ca9ae
HY		 3115 case KVM_X86_SETUP_MCE: {
3116 u64 mcg_cap;
3117
3118 r = -EFAULT;
3119 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3120 goto out;
3121 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3122 break;
3123 }
3124 case KVM_X86_SET_MCE: {
3125 struct kvm_x86_mce mce;
3126
3127 r = -EFAULT;
3128 if (copy_from_user(&mce, argp, sizeof mce))
3129 goto out;
3130 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3131 break;
3132 }
3cfc3092
JK		 3133 case KVM_GET_VCPU_EVENTS: {
3134 struct kvm_vcpu_events events;
3135
3136 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3137
3138 r = -EFAULT;
3139 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3140 break;
3141 r = 0;
3142 break;
3143 }
3144 case KVM_SET_VCPU_EVENTS: {
3145 struct kvm_vcpu_events events;
3146
3147 r = -EFAULT;
3148 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3149 break;
3150
3151 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3152 break;
3153 }
a1efbe77
JK		 3154 case KVM_GET_DEBUGREGS: {
3155 struct kvm_debugregs dbgregs;
3156
3157 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3158
3159 r = -EFAULT;
3160 if (copy_to_user(argp, &dbgregs,
3161 sizeof(struct kvm_debugregs)))
3162 break;
3163 r = 0;
3164 break;
3165 }
3166 case KVM_SET_DEBUGREGS: {
3167 struct kvm_debugregs dbgregs;
3168
3169 r = -EFAULT;
3170 if (copy_from_user(&dbgregs, argp,
3171 sizeof(struct kvm_debugregs)))
3172 break;
3173
3174 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3175 break;
3176 }
2d5b5a66 3177 case KVM_GET_XSAVE: {
d1ac91d8 3178 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3179 r = -ENOMEM;
d1ac91d8 3180 if (!u.xsave)
2d5b5a66
SY		 3181 break;
3182
d1ac91d8 3183 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3184
3185 r = -EFAULT;
d1ac91d8 3186 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3187 break;
3188 r = 0;
3189 break;
3190 }
3191 case KVM_SET_XSAVE: {
ff5c2c03 3192 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3193 if (IS_ERR(u.xsave))
3194 return PTR_ERR(u.xsave);
2d5b5a66 3195
d1ac91d8 3196 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3197 break;
3198 }
3199 case KVM_GET_XCRS: {
d1ac91d8 3200 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3201 r = -ENOMEM;
d1ac91d8 3202 if (!u.xcrs)
2d5b5a66
SY		 3203 break;
3204
d1ac91d8 3205 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3206
3207 r = -EFAULT;
d1ac91d8 3208 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3209 sizeof(struct kvm_xcrs)))
3210 break;
3211 r = 0;
3212 break;
3213 }
3214 case KVM_SET_XCRS: {
ff5c2c03 3215 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3216 if (IS_ERR(u.xcrs))
3217 return PTR_ERR(u.xcrs);
2d5b5a66 3218
d1ac91d8 3219 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3220 break;
3221 }
92a1f12d
JR		 3222 case KVM_SET_TSC_KHZ: {
3223 u32 user_tsc_khz;
3224
3225 r = -EINVAL;
92a1f12d
JR		 3226 user_tsc_khz = (u32)arg;
3227
3228 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3229 goto out;
3230
cc578287
ZA		 3231 if (user_tsc_khz == 0)
3232 user_tsc_khz = tsc_khz;
3233
3234 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3235
3236 r = 0;
3237 goto out;
3238 }
3239 case KVM_GET_TSC_KHZ: {
cc578287 3240 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3241 goto out;
3242 }
1c0b28c2
EM		 3243 case KVM_KVMCLOCK_CTRL: {
3244 r = kvm_set_guest_paused(vcpu);
3245 goto out;
3246 }
313a3dc7
CO		 3247 default:
3248 r = -EINVAL;
3249 }
3250out:
d1ac91d8 3251 kfree(u.buffer);
313a3dc7
CO		 3252 return r;
3253}
3254
5b1c1493
CO		 3255int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3256{
3257 return VM_FAULT_SIGBUS;
3258}
3259
1fe779f8
CO		 3260static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3261{
3262 int ret;
3263
3264 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3265 return -EINVAL;
1fe779f8
CO		 3266 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3267 return ret;
3268}
3269
b927a3ce
SY		 3270static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3271 u64 ident_addr)
3272{
3273 kvm->arch.ept_identity_map_addr = ident_addr;
3274 return 0;
3275}
3276
1fe779f8
CO		 3277static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3278 u32 kvm_nr_mmu_pages)
3279{
3280 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3281 return -EINVAL;
3282
79fac95e 3283 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3284
3285 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3286 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3287
79fac95e 3288 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3289 return 0;
3290}
3291
3292static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3293{
39de71ec 3294 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3295}
3296
1fe779f8
CO		 3297static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3298{
3299 int r;
3300
3301 r = 0;
3302 switch (chip->chip_id) {
3303 case KVM_IRQCHIP_PIC_MASTER:
3304 memcpy(&chip->chip.pic,
3305 &pic_irqchip(kvm)->pics[0],
3306 sizeof(struct kvm_pic_state));
3307 break;
3308 case KVM_IRQCHIP_PIC_SLAVE:
3309 memcpy(&chip->chip.pic,
3310 &pic_irqchip(kvm)->pics[1],
3311 sizeof(struct kvm_pic_state));
3312 break;
3313 case KVM_IRQCHIP_IOAPIC:
eba0226b 3314 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3315 break;
3316 default:
3317 r = -EINVAL;
3318 break;
3319 }
3320 return r;
3321}
3322
3323static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3324{
3325 int r;
3326
3327 r = 0;
3328 switch (chip->chip_id) {
3329 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3330 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3331 memcpy(&pic_irqchip(kvm)->pics[0],
3332 &chip->chip.pic,
3333 sizeof(struct kvm_pic_state));
f4f51050 3334 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3335 break;
3336 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3337 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3338 memcpy(&pic_irqchip(kvm)->pics[1],
3339 &chip->chip.pic,
3340 sizeof(struct kvm_pic_state));
f4f51050 3341 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3342 break;
3343 case KVM_IRQCHIP_IOAPIC:
eba0226b 3344 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3345 break;
3346 default:
3347 r = -EINVAL;
3348 break;
3349 }
3350 kvm_pic_update_irq(pic_irqchip(kvm));
3351 return r;
3352}
3353
e0f63cb9
SY		 3354static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3355{
3356 int r = 0;
3357
894a9c55 3358 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3359 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3360 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3361 return r;
3362}
3363
3364static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3365{
3366 int r = 0;
3367
894a9c55 3368 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3369 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3370 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3371 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3372 return r;
3373}
3374
3375static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3376{
3377 int r = 0;
3378
3379 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3380 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3381 sizeof(ps->channels));
3382 ps->flags = kvm->arch.vpit->pit_state.flags;
3383 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3384 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3385 return r;
3386}
3387
3388static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3389{
3390 int r = 0, start = 0;
3391 u32 prev_legacy, cur_legacy;
3392 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3393 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3394 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3395 if (!prev_legacy && cur_legacy)
3396 start = 1;
3397 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3398 sizeof(kvm->arch.vpit->pit_state.channels));
3399 kvm->arch.vpit->pit_state.flags = ps->flags;
3400 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3401 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3402 return r;
3403}
3404
52d939a0
MT		 3405static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3406 struct kvm_reinject_control *control)
3407{
3408 if (!kvm->arch.vpit)
3409 return -ENXIO;
894a9c55 3410 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3411 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3412 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3413 return 0;
3414}
3415
95d4c16c 3416/**
60c34612
TY		 3417 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3418 * @kvm: kvm instance
3419 * @log: slot id and address to which we copy the log
95d4c16c 3420 *
60c34612
TY		 3421 * We need to keep it in mind that VCPU threads can write to the bitmap
3422 * concurrently. So, to avoid losing data, we keep the following order for
3423 * each bit:
95d4c16c 3424 *
60c34612
TY		 3425 * 1. Take a snapshot of the bit and clear it if needed.
3426 * 2. Write protect the corresponding page.
3427 * 3. Flush TLB's if needed.
3428 * 4. Copy the snapshot to the userspace.
95d4c16c 3429 *
60c34612
TY		 3430 * Between 2 and 3, the guest may write to the page using the remaining TLB
3431 * entry. This is not a problem because the page will be reported dirty at
3432 * step 4 using the snapshot taken before and step 3 ensures that successive
3433 * writes will be logged for the next call.
5bb064dc 3434 */
60c34612 3435int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3436{
7850ac54 3437 int r;
5bb064dc 3438 struct kvm_memory_slot *memslot;
60c34612
TY		 3439 unsigned long n, i;
3440 unsigned long *dirty_bitmap;
3441 unsigned long *dirty_bitmap_buffer;
3442 bool is_dirty = false;
5bb064dc 3443
79fac95e 3444 mutex_lock(&kvm->slots_lock);
5bb064dc 3445
b050b015 3446 r = -EINVAL;
bbacc0c1 3447 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3448 goto out;
3449
28a37544 3450 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3451
3452 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3453 r = -ENOENT;
60c34612 3454 if (!dirty_bitmap)
b050b015
MT		 3455 goto out;
3456
87bf6e7d 3457 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3458
60c34612
TY		 3459 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3460 memset(dirty_bitmap_buffer, 0, n);
b050b015 3461
60c34612 3462 spin_lock(&kvm->mmu_lock);
b050b015 3463
60c34612
TY		 3464 for (i = 0; i < n / sizeof(long); i++) {
3465 unsigned long mask;
3466 gfn_t offset;
cdfca7b3 3467
60c34612
TY		 3468 if (!dirty_bitmap[i])
3469 continue;
b050b015 3470
60c34612 3471 is_dirty = true;
914ebccd 3472
60c34612
TY		 3473 mask = xchg(&dirty_bitmap[i], 0);
3474 dirty_bitmap_buffer[i] = mask;
edde99ce 3475
60c34612
TY		 3476 offset = i * BITS_PER_LONG;
3477 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3478 }
60c34612
TY		 3479 if (is_dirty)
3480 kvm_flush_remote_tlbs(kvm);
3481
3482 spin_unlock(&kvm->mmu_lock);
3483
3484 r = -EFAULT;
3485 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3486 goto out;
b050b015 3487
5bb064dc
ZX		 3488 r = 0;
3489out:
79fac95e 3490 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3491 return r;
3492}
3493
23d43cf9
CD		 3494int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3495{
3496 if (!irqchip_in_kernel(kvm))
3497 return -ENXIO;
3498
3499 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3500 irq_event->irq, irq_event->level);
3501 return 0;
3502}
3503
1fe779f8
CO		 3504long kvm_arch_vm_ioctl(struct file *filp,
3505 unsigned int ioctl, unsigned long arg)
3506{
3507 struct kvm *kvm = filp->private_data;
3508 void __user *argp = (void __user *)arg;
367e1319 3509 int r = -ENOTTY;
f0d66275
DH		 3510 /*
3511 * This union makes it completely explicit to gcc-3.x
3512 * that these two variables' stack usage should be
3513 * combined, not added together.
3514 */
3515 union {
3516 struct kvm_pit_state ps;
e9f42757 3517 struct kvm_pit_state2 ps2;
c5ff41ce 3518 struct kvm_pit_config pit_config;
f0d66275 3519 } u;
1fe779f8
CO		 3520
3521 switch (ioctl) {
3522 case KVM_SET_TSS_ADDR:
3523 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3524 break;
b927a3ce
SY		 3525 case KVM_SET_IDENTITY_MAP_ADDR: {
3526 u64 ident_addr;
3527
3528 r = -EFAULT;
3529 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3530 goto out;
3531 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3532 break;
3533 }
1fe779f8
CO		 3534 case KVM_SET_NR_MMU_PAGES:
3535 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3536 break;
3537 case KVM_GET_NR_MMU_PAGES:
3538 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3539 break;
3ddea128
MT		 3540 case KVM_CREATE_IRQCHIP: {
3541 struct kvm_pic *vpic;
3542
3543 mutex_lock(&kvm->lock);
3544 r = -EEXIST;
3545 if (kvm->arch.vpic)
3546 goto create_irqchip_unlock;
3e515705
AK		 3547 r = -EINVAL;
3548 if (atomic_read(&kvm->online_vcpus))
3549 goto create_irqchip_unlock;
1fe779f8 3550 r = -ENOMEM;
3ddea128
MT		 3551 vpic = kvm_create_pic(kvm);
3552 if (vpic) {
1fe779f8
CO		 3553 r = kvm_ioapic_init(kvm);
3554 if (r) {
175504cd 3555 mutex_lock(&kvm->slots_lock);
72bb2fcd 3556 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3557 &vpic->dev_master);
3558 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3559 &vpic->dev_slave);
3560 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3561 &vpic->dev_eclr);
175504cd 3562 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3563 kfree(vpic);
3564 goto create_irqchip_unlock;
1fe779f8
CO		 3565 }
3566 } else
3ddea128
MT		 3567 goto create_irqchip_unlock;
3568 smp_wmb();
3569 kvm->arch.vpic = vpic;
3570 smp_wmb();
399ec807
AK		 3571 r = kvm_setup_default_irq_routing(kvm);
3572 if (r) {
175504cd 3573 mutex_lock(&kvm->slots_lock);
3ddea128 3574 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3575 kvm_ioapic_destroy(kvm);
3576 kvm_destroy_pic(kvm);
3ddea128 3577 mutex_unlock(&kvm->irq_lock);
175504cd 3578 mutex_unlock(&kvm->slots_lock);
399ec807 3579 }
3ddea128
MT		 3580 create_irqchip_unlock:
3581 mutex_unlock(&kvm->lock);
1fe779f8 3582 break;
3ddea128 3583 }
7837699f 3584 case KVM_CREATE_PIT:
c5ff41ce
JK		 3585 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3586 goto create_pit;
3587 case KVM_CREATE_PIT2:
3588 r = -EFAULT;
3589 if (copy_from_user(&u.pit_config, argp,
3590 sizeof(struct kvm_pit_config)))
3591 goto out;
3592 create_pit:
79fac95e 3593 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3594 r = -EEXIST;
3595 if (kvm->arch.vpit)
3596 goto create_pit_unlock;
7837699f 3597 r = -ENOMEM;
c5ff41ce 3598 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3599 if (kvm->arch.vpit)
3600 r = 0;
269e05e4 3601 create_pit_unlock:
79fac95e 3602 mutex_unlock(&kvm->slots_lock);
7837699f 3603 break;
1fe779f8
CO		 3604 case KVM_GET_IRQCHIP: {
3605 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3606 struct kvm_irqchip *chip;
1fe779f8 3607
ff5c2c03
SL		 3608 chip = memdup_user(argp, sizeof(*chip));
3609 if (IS_ERR(chip)) {
3610 r = PTR_ERR(chip);
1fe779f8 3611 goto out;
ff5c2c03
SL		 3612 }
3613
1fe779f8
CO		 3614 r = -ENXIO;
3615 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3616 goto get_irqchip_out;
3617 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3618 if (r)
f0d66275 3619 goto get_irqchip_out;
1fe779f8 3620 r = -EFAULT;
f0d66275
DH		 3621 if (copy_to_user(argp, chip, sizeof *chip))
3622 goto get_irqchip_out;
1fe779f8 3623 r = 0;
f0d66275
DH		 3624 get_irqchip_out:
3625 kfree(chip);
1fe779f8
CO		 3626 break;
3627 }
3628 case KVM_SET_IRQCHIP: {
3629 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3630 struct kvm_irqchip *chip;
1fe779f8 3631
ff5c2c03
SL		 3632 chip = memdup_user(argp, sizeof(*chip));
3633 if (IS_ERR(chip)) {
3634 r = PTR_ERR(chip);
1fe779f8 3635 goto out;
ff5c2c03
SL		 3636 }
3637
1fe779f8
CO		 3638 r = -ENXIO;
3639 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3640 goto set_irqchip_out;
3641 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3642 if (r)
f0d66275 3643 goto set_irqchip_out;
1fe779f8 3644 r = 0;
f0d66275
DH		 3645 set_irqchip_out:
3646 kfree(chip);
1fe779f8
CO		 3647 break;
3648 }
e0f63cb9 3649 case KVM_GET_PIT: {
e0f63cb9 3650 r = -EFAULT;
f0d66275 3651 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3652 goto out;
3653 r = -ENXIO;
3654 if (!kvm->arch.vpit)
3655 goto out;
f0d66275 3656 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3657 if (r)
3658 goto out;
3659 r = -EFAULT;
f0d66275 3660 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3661 goto out;
3662 r = 0;
3663 break;
3664 }
3665 case KVM_SET_PIT: {
e0f63cb9 3666 r = -EFAULT;
f0d66275 3667 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3668 goto out;
3669 r = -ENXIO;
3670 if (!kvm->arch.vpit)
3671 goto out;
f0d66275 3672 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3673 break;
3674 }
e9f42757
BK		 3675 case KVM_GET_PIT2: {
3676 r = -ENXIO;
3677 if (!kvm->arch.vpit)
3678 goto out;
3679 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3680 if (r)
3681 goto out;
3682 r = -EFAULT;
3683 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3684 goto out;
3685 r = 0;
3686 break;
3687 }
3688 case KVM_SET_PIT2: {
3689 r = -EFAULT;
3690 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3691 goto out;
3692 r = -ENXIO;
3693 if (!kvm->arch.vpit)
3694 goto out;
3695 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3696 break;
3697 }
52d939a0
MT		 3698 case KVM_REINJECT_CONTROL: {
3699 struct kvm_reinject_control control;
3700 r = -EFAULT;
3701 if (copy_from_user(&control, argp, sizeof(control)))
3702 goto out;
3703 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3704 break;
3705 }
ffde22ac
ES		 3706 case KVM_XEN_HVM_CONFIG: {
3707 r = -EFAULT;
3708 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3709 sizeof(struct kvm_xen_hvm_config)))
3710 goto out;
3711 r = -EINVAL;
3712 if (kvm->arch.xen_hvm_config.flags)
3713 goto out;
3714 r = 0;
3715 break;
3716 }
afbcf7ab 3717 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3718 struct kvm_clock_data user_ns;
3719 u64 now_ns;
3720 s64 delta;
3721
3722 r = -EFAULT;
3723 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3724 goto out;
3725
3726 r = -EINVAL;
3727 if (user_ns.flags)
3728 goto out;
3729
3730 r = 0;
395c6b0a 3731 local_irq_disable();
759379dd 3732 now_ns = get_kernel_ns();
afbcf7ab 3733 delta = user_ns.clock - now_ns;
395c6b0a 3734 local_irq_enable();
afbcf7ab
GC		 3735 kvm->arch.kvmclock_offset = delta;
3736 break;
3737 }
3738 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3739 struct kvm_clock_data user_ns;
3740 u64 now_ns;
3741
395c6b0a 3742 local_irq_disable();
759379dd 3743 now_ns = get_kernel_ns();
afbcf7ab 3744 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3745 local_irq_enable();
afbcf7ab 3746 user_ns.flags = 0;
97e69aa6 3747 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3748
3749 r = -EFAULT;
3750 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3751 goto out;
3752 r = 0;
3753 break;
3754 }
3755
1fe779f8
CO		 3756 default:
3757 ;
3758 }
3759out:
3760 return r;
3761}
3762
a16b043c 3763static void kvm_init_msr_list(void)
043405e1
CO		 3764{
3765 u32 dummy[2];
3766 unsigned i, j;
3767
e3267cbb
GC		 3768 /* skip the first msrs in the list. KVM-specific */
3769 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3770 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3771 continue;
3772 if (j < i)
3773 msrs_to_save[j] = msrs_to_save[i];
3774 j++;
3775 }
3776 num_msrs_to_save = j;
3777}
3778
bda9020e
MT		 3779static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3780 const void *v)
bbd9b64e 3781{
70252a10
AK		 3782 int handled = 0;
3783 int n;
3784
3785 do {
3786 n = min(len, 8);
3787 if (!(vcpu->arch.apic &&
3788 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3789 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3790 break;
3791 handled += n;
3792 addr += n;
3793 len -= n;
3794 v += n;
3795 } while (len);
bbd9b64e 3796
70252a10 3797 return handled;
bbd9b64e
CO		 3798}
3799
bda9020e 3800static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3801{
70252a10
AK		 3802 int handled = 0;
3803 int n;
3804
3805 do {
3806 n = min(len, 8);
3807 if (!(vcpu->arch.apic &&
3808 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3809 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3810 break;
3811 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3812 handled += n;
3813 addr += n;
3814 len -= n;
3815 v += n;
3816 } while (len);
bbd9b64e 3817
70252a10 3818 return handled;
bbd9b64e
CO		 3819}
3820
2dafc6c2
GN		 3821static void kvm_set_segment(struct kvm_vcpu *vcpu,
3822 struct kvm_segment *var, int seg)
3823{
3824 kvm_x86_ops->set_segment(vcpu, var, seg);
3825}
3826
3827void kvm_get_segment(struct kvm_vcpu *vcpu,
3828 struct kvm_segment *var, int seg)
3829{
3830 kvm_x86_ops->get_segment(vcpu, var, seg);
3831}
3832
e459e322 3833gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3834{
3835 gpa_t t_gpa;
ab9ae313 3836 struct x86_exception exception;
02f59dc9
JR		 3837
3838 BUG_ON(!mmu_is_nested(vcpu));
3839
3840 /* NPT walks are always user-walks */
3841 access |= PFERR_USER_MASK;
ab9ae313 3842 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3843
3844 return t_gpa;
3845}
3846
ab9ae313
AK		 3847gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3848 struct x86_exception *exception)
1871c602
GN		 3849{
3850 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3851 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3852}
3853
ab9ae313
AK		 3854 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3855 struct x86_exception *exception)
1871c602
GN		 3856{
3857 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3858 access |= PFERR_FETCH_MASK;
ab9ae313 3859 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3860}
3861
ab9ae313
AK		 3862gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3863 struct x86_exception *exception)
1871c602
GN		 3864{
3865 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3866 access |= PFERR_WRITE_MASK;
ab9ae313 3867 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3868}
3869
3870/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3871gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3872 struct x86_exception *exception)
1871c602 3873{
ab9ae313 3874 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3875}
3876
3877static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3878 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3879 struct x86_exception *exception)
bbd9b64e
CO		 3880{
3881 void *data = val;
10589a46 3882 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3883
3884 while (bytes) {
14dfe855 3885 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3886 exception);
bbd9b64e 3887 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3888 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3889 int ret;
3890
bcc55cba 3891 if (gpa == UNMAPPED_GVA)
ab9ae313 3892 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3893 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3894 if (ret < 0) {
c3cd7ffa 3895 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3896 goto out;
3897 }
bbd9b64e 3898
77c2002e
IE		 3899 bytes -= toread;
3900 data += toread;
3901 addr += toread;
bbd9b64e 3902 }
10589a46 3903out:
10589a46 3904 return r;
bbd9b64e 3905}
77c2002e 3906
1871c602 3907/* used for instruction fetching */
0f65dd70
AK		 3908static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3909 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3910 struct x86_exception *exception)
1871c602 3911{
0f65dd70 3912 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3913 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3914
1871c602 3915 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3916 access | PFERR_FETCH_MASK,
3917 exception);
1871c602
GN		 3918}
3919
064aea77 3920int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3921 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3922 struct x86_exception *exception)
1871c602 3923{
0f65dd70 3924 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3925 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3926
1871c602 3927 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3928 exception);
1871c602 3929}
064aea77 3930EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3931
0f65dd70
AK		 3932static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3933 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3934 struct x86_exception *exception)
1871c602 3935{
0f65dd70 3936 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3937 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3938}
3939
6a4d7550 3940int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3941 gva_t addr, void *val,
2dafc6c2 3942 unsigned int bytes,
bcc55cba 3943 struct x86_exception *exception)
77c2002e 3944{
0f65dd70 3945 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3946 void *data = val;
3947 int r = X86EMUL_CONTINUE;
3948
3949 while (bytes) {
14dfe855
JR		 3950 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3951 PFERR_WRITE_MASK,
ab9ae313 3952 exception);
77c2002e
IE		 3953 unsigned offset = addr & (PAGE_SIZE-1);
3954 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3955 int ret;
3956
bcc55cba 3957 if (gpa == UNMAPPED_GVA)
ab9ae313 3958 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3959 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3960 if (ret < 0) {
c3cd7ffa 3961 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3962 goto out;
3963 }
3964
3965 bytes -= towrite;
3966 data += towrite;
3967 addr += towrite;
3968 }
3969out:
3970 return r;
3971}
6a4d7550 3972EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3973
af7cc7d1
XG		 3974static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3975 gpa_t *gpa, struct x86_exception *exception,
3976 bool write)
3977{
97d64b78
AK		 3978 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3979 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3980
97d64b78
AK		 3981 if (vcpu_match_mmio_gva(vcpu, gva)
3982 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3983 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3984 (gva & (PAGE_SIZE - 1));
4f022648 3985 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3986 return 1;
3987 }
3988
af7cc7d1
XG		 3989 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3990
3991 if (*gpa == UNMAPPED_GVA)
3992 return -1;
3993
3994 /* For APIC access vmexit */
3995 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3996 return 1;
3997
4f022648
XG		 3998 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3999 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4000 return 1;
4f022648 4001 }
bebb106a 4002
af7cc7d1
XG		 4003 return 0;
4004}
4005
3200f405 4006int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4007 const void *val, int bytes)
bbd9b64e
CO		 4008{
4009 int ret;
4010
4011 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4012 if (ret < 0)
bbd9b64e 4013 return 0;
f57f2ef5 4014 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4015 return 1;
4016}
4017
77d197b2
XG		 4018struct read_write_emulator_ops {
4019 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4020 int bytes);
4021 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4022 void *val, int bytes);
4023 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4024 int bytes, void *val);
4025 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4026 void *val, int bytes);
4027 bool write;
4028};
4029
4030static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4031{
4032 if (vcpu->mmio_read_completed) {
77d197b2 4033 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4034 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4035 vcpu->mmio_read_completed = 0;
4036 return 1;
4037 }
4038
4039 return 0;
4040}
4041
4042static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4043 void *val, int bytes)
4044{
4045 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4046}
4047
4048static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4049 void *val, int bytes)
4050{
4051 return emulator_write_phys(vcpu, gpa, val, bytes);
4052}
4053
4054static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4055{
4056 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4057 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4058}
4059
4060static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4061 void *val, int bytes)
4062{
4063 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4064 return X86EMUL_IO_NEEDED;
4065}
4066
4067static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4068 void *val, int bytes)
4069{
f78146b0
AK		 4070 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4071
87da7e66 4072 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4073 return X86EMUL_CONTINUE;
4074}
4075
0fbe9b0b 4076static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4077 .read_write_prepare = read_prepare,
4078 .read_write_emulate = read_emulate,
4079 .read_write_mmio = vcpu_mmio_read,
4080 .read_write_exit_mmio = read_exit_mmio,
4081};
4082
0fbe9b0b 4083static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4084 .read_write_emulate = write_emulate,
4085 .read_write_mmio = write_mmio,
4086 .read_write_exit_mmio = write_exit_mmio,
4087 .write = true,
4088};
4089
22388a3c
XG		 4090static int emulator_read_write_onepage(unsigned long addr, void *val,
4091 unsigned int bytes,
4092 struct x86_exception *exception,
4093 struct kvm_vcpu *vcpu,
0fbe9b0b 4094 const struct read_write_emulator_ops *ops)
bbd9b64e 4095{
af7cc7d1
XG		 4096 gpa_t gpa;
4097 int handled, ret;
22388a3c 4098 bool write = ops->write;
f78146b0 4099 struct kvm_mmio_fragment *frag;
10589a46 4100
22388a3c 4101 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4102
af7cc7d1 4103 if (ret < 0)
bbd9b64e 4104 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4105
4106 /* For APIC access vmexit */
af7cc7d1 4107 if (ret)
bbd9b64e
CO		 4108 goto mmio;
4109
22388a3c 4110 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4111 return X86EMUL_CONTINUE;
4112
4113mmio:
4114 /*
4115 * Is this MMIO handled locally?
4116 */
22388a3c 4117 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4118 if (handled == bytes)
bbd9b64e 4119 return X86EMUL_CONTINUE;
bbd9b64e 4120
70252a10
AK		 4121 gpa += handled;
4122 bytes -= handled;
4123 val += handled;
4124
87da7e66
XG		 4125 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4126 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4127 frag->gpa = gpa;
4128 frag->data = val;
4129 frag->len = bytes;
f78146b0 4130 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4131}
4132
22388a3c
XG		 4133int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4134 void *val, unsigned int bytes,
4135 struct x86_exception *exception,
0fbe9b0b 4136 const struct read_write_emulator_ops *ops)
bbd9b64e 4137{
0f65dd70 4138 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4139 gpa_t gpa;
4140 int rc;
4141
4142 if (ops->read_write_prepare &&
4143 ops->read_write_prepare(vcpu, val, bytes))
4144 return X86EMUL_CONTINUE;
4145
4146 vcpu->mmio_nr_fragments = 0;
0f65dd70 4147
bbd9b64e
CO		 4148 /* Crossing a page boundary? */
4149 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4150 int now;
bbd9b64e
CO		 4151
4152 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4153 rc = emulator_read_write_onepage(addr, val, now, exception,
4154 vcpu, ops);
4155
bbd9b64e
CO		 4156 if (rc != X86EMUL_CONTINUE)
4157 return rc;
4158 addr += now;
4159 val += now;
4160 bytes -= now;
4161 }
22388a3c 4162
f78146b0
AK		 4163 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4164 vcpu, ops);
4165 if (rc != X86EMUL_CONTINUE)
4166 return rc;
4167
4168 if (!vcpu->mmio_nr_fragments)
4169 return rc;
4170
4171 gpa = vcpu->mmio_fragments[0].gpa;
4172
4173 vcpu->mmio_needed = 1;
4174 vcpu->mmio_cur_fragment = 0;
4175
87da7e66 4176 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4177 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4178 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4179 vcpu->run->mmio.phys_addr = gpa;
4180
4181 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4182}
4183
4184static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4185 unsigned long addr,
4186 void *val,
4187 unsigned int bytes,
4188 struct x86_exception *exception)
4189{
4190 return emulator_read_write(ctxt, addr, val, bytes,
4191 exception, &read_emultor);
4192}
4193
4194int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4195 unsigned long addr,
4196 const void *val,
4197 unsigned int bytes,
4198 struct x86_exception *exception)
4199{
4200 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4201 exception, &write_emultor);
bbd9b64e 4202}
bbd9b64e 4203
daea3e73
AK		 4204#define CMPXCHG_TYPE(t, ptr, old, new) \
4205 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4206
4207#ifdef CONFIG_X86_64
4208# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4209#else
4210# define CMPXCHG64(ptr, old, new) \
9749a6c0 4211 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4212#endif
4213
0f65dd70
AK		 4214static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4215 unsigned long addr,
bbd9b64e
CO		 4216 const void *old,
4217 const void *new,
4218 unsigned int bytes,
0f65dd70 4219 struct x86_exception *exception)
bbd9b64e 4220{
0f65dd70 4221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4222 gpa_t gpa;
4223 struct page *page;
4224 char *kaddr;
4225 bool exchanged;
2bacc55c 4226
daea3e73
AK		 4227 /* guests cmpxchg8b have to be emulated atomically */
4228 if (bytes > 8 || (bytes & (bytes - 1)))
4229 goto emul_write;
10589a46 4230
daea3e73 4231 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4232
daea3e73
AK		 4233 if (gpa == UNMAPPED_GVA ||
4234 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4235 goto emul_write;
2bacc55c 4236
daea3e73
AK		 4237 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4238 goto emul_write;
72dc67a6 4239
daea3e73 4240 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4241 if (is_error_page(page))
c19b8bd6 4242 goto emul_write;
72dc67a6 4243
8fd75e12 4244 kaddr = kmap_atomic(page);
daea3e73
AK		 4245 kaddr += offset_in_page(gpa);
4246 switch (bytes) {
4247 case 1:
4248 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4249 break;
4250 case 2:
4251 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4252 break;
4253 case 4:
4254 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4255 break;
4256 case 8:
4257 exchanged = CMPXCHG64(kaddr, old, new);
4258 break;
4259 default:
4260 BUG();
2bacc55c 4261 }
8fd75e12 4262 kunmap_atomic(kaddr);
daea3e73
AK		 4263 kvm_release_page_dirty(page);
4264
4265 if (!exchanged)
4266 return X86EMUL_CMPXCHG_FAILED;
4267
f57f2ef5 4268 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4269
4270 return X86EMUL_CONTINUE;
4a5f48f6 4271
3200f405 4272emul_write:
daea3e73 4273 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4274
0f65dd70 4275 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4276}
4277
cf8f70bf
GN		 4278static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4279{
4280 /* TODO: String I/O for in kernel device */
4281 int r;
4282
4283 if (vcpu->arch.pio.in)
4284 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4285 vcpu->arch.pio.size, pd);
4286 else
4287 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4288 vcpu->arch.pio.port, vcpu->arch.pio.size,
4289 pd);
4290 return r;
4291}
4292
6f6fbe98
XG		 4293static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4294 unsigned short port, void *val,
4295 unsigned int count, bool in)
cf8f70bf 4296{
6f6fbe98 4297 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4298
4299 vcpu->arch.pio.port = port;
6f6fbe98 4300 vcpu->arch.pio.in = in;
7972995b 4301 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4302 vcpu->arch.pio.size = size;
4303
4304 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4305 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4306 return 1;
4307 }
4308
4309 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4310 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4311 vcpu->run->io.size = size;
4312 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4313 vcpu->run->io.count = count;
4314 vcpu->run->io.port = port;
4315
4316 return 0;
4317}
4318
6f6fbe98
XG		 4319static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4320 int size, unsigned short port, void *val,
4321 unsigned int count)
cf8f70bf 4322{
ca1d4a9e 4323 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4324 int ret;
ca1d4a9e 4325
6f6fbe98
XG		 4326 if (vcpu->arch.pio.count)
4327 goto data_avail;
cf8f70bf 4328
6f6fbe98
XG		 4329 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4330 if (ret) {
4331data_avail:
4332 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4333 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4334 return 1;
4335 }
4336
cf8f70bf
GN		 4337 return 0;
4338}
4339
6f6fbe98
XG		 4340static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4341 int size, unsigned short port,
4342 const void *val, unsigned int count)
4343{
4344 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4345
4346 memcpy(vcpu->arch.pio_data, val, size * count);
4347 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4348}
4349
bbd9b64e
CO		 4350static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4351{
4352 return kvm_x86_ops->get_segment_base(vcpu, seg);
4353}
4354
3cb16fe7 4355static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4356{
3cb16fe7 4357 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4358}
4359
f5f48ee1
SY		 4360int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4361{
4362 if (!need_emulate_wbinvd(vcpu))
4363 return X86EMUL_CONTINUE;
4364
4365 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4366 int cpu = get_cpu();
4367
4368 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4369 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4370 wbinvd_ipi, NULL, 1);
2eec7343 4371 put_cpu();
f5f48ee1 4372 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4373 } else
4374 wbinvd();
f5f48ee1
SY		 4375 return X86EMUL_CONTINUE;
4376}
4377EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4378
bcaf5cc5
AK		 4379static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4380{
4381 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4382}
4383
717746e3 4384int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4385{
717746e3 4386 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4387}
4388
717746e3 4389int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4390{
338dbc97 4391
717746e3 4392 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4393}
4394
52a46617 4395static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4396{
52a46617 4397 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4398}
4399
717746e3 4400static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4401{
717746e3 4402 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4403 unsigned long value;
4404
4405 switch (cr) {
4406 case 0:
4407 value = kvm_read_cr0(vcpu);
4408 break;
4409 case 2:
4410 value = vcpu->arch.cr2;
4411 break;
4412 case 3:
9f8fe504 4413 value = kvm_read_cr3(vcpu);
52a46617
GN		 4414 break;
4415 case 4:
4416 value = kvm_read_cr4(vcpu);
4417 break;
4418 case 8:
4419 value = kvm_get_cr8(vcpu);
4420 break;
4421 default:
a737f256 4422 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4423 return 0;
4424 }
4425
4426 return value;
4427}
4428
717746e3 4429static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4430{
717746e3 4431 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4432 int res = 0;
4433
52a46617
GN		 4434 switch (cr) {
4435 case 0:
49a9b07e 4436 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4437 break;
4438 case 2:
4439 vcpu->arch.cr2 = val;
4440 break;
4441 case 3:
2390218b 4442 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4443 break;
4444 case 4:
a83b29c6 4445 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4446 break;
4447 case 8:
eea1cff9 4448 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4449 break;
4450 default:
a737f256 4451 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4452 res = -1;
52a46617 4453 }
0f12244f
GN		 4454
4455 return res;
52a46617
GN		 4456}
4457
4cee4798
KW		 4458static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4459{
4460 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4461}
4462
717746e3 4463static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4464{
717746e3 4465 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4466}
4467
4bff1e86 4468static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4469{
4bff1e86 4470 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4471}
4472
4bff1e86 4473static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4474{
4bff1e86 4475 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4476}
4477
1ac9d0cf
AK		 4478static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4479{
4480 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4481}
4482
4483static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4484{
4485 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4486}
4487
4bff1e86
AK		 4488static unsigned long emulator_get_cached_segment_base(
4489 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4490{
4bff1e86 4491 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4492}
4493
1aa36616
AK		 4494static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4495 struct desc_struct *desc, u32 *base3,
4496 int seg)
2dafc6c2
GN		 4497{
4498 struct kvm_segment var;
4499
4bff1e86 4500 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4501 *selector = var.selector;
2dafc6c2 4502
378a8b09
GN		 4503 if (var.unusable) {
4504 memset(desc, 0, sizeof(*desc));
2dafc6c2 4505 return false;
378a8b09 4506 }
2dafc6c2
GN		 4507
4508 if (var.g)
4509 var.limit >>= 12;
4510 set_desc_limit(desc, var.limit);
4511 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4512#ifdef CONFIG_X86_64
4513 if (base3)
4514 *base3 = var.base >> 32;
4515#endif
2dafc6c2
GN		 4516 desc->type = var.type;
4517 desc->s = var.s;
4518 desc->dpl = var.dpl;
4519 desc->p = var.present;
4520 desc->avl = var.avl;
4521 desc->l = var.l;
4522 desc->d = var.db;
4523 desc->g = var.g;
4524
4525 return true;
4526}
4527
1aa36616
AK		 4528static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4529 struct desc_struct *desc, u32 base3,
4530 int seg)
2dafc6c2 4531{
4bff1e86 4532 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4533 struct kvm_segment var;
4534
1aa36616 4535 var.selector = selector;
2dafc6c2 4536 var.base = get_desc_base(desc);
5601d05b
GN		 4537#ifdef CONFIG_X86_64
4538 var.base |= ((u64)base3) << 32;
4539#endif
2dafc6c2
GN		 4540 var.limit = get_desc_limit(desc);
4541 if (desc->g)
4542 var.limit = (var.limit << 12) | 0xfff;
4543 var.type = desc->type;
4544 var.present = desc->p;
4545 var.dpl = desc->dpl;
4546 var.db = desc->d;
4547 var.s = desc->s;
4548 var.l = desc->l;
4549 var.g = desc->g;
4550 var.avl = desc->avl;
4551 var.present = desc->p;
4552 var.unusable = !var.present;
4553 var.padding = 0;
4554
4555 kvm_set_segment(vcpu, &var, seg);
4556 return;
4557}
4558
717746e3
AK		 4559static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4560 u32 msr_index, u64 *pdata)
4561{
4562 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4563}
4564
4565static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4566 u32 msr_index, u64 data)
4567{
8fe8ab46
WA		 4568 struct msr_data msr;
4569
4570 msr.data = data;
4571 msr.index = msr_index;
4572 msr.host_initiated = false;
4573 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4574}
4575
222d21aa
AK		 4576static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4577 u32 pmc, u64 *pdata)
4578{
4579 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4580}
4581
6c3287f7
AK		 4582static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4583{
4584 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4585}
4586
5037f6f3
AK		 4587static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4588{
4589 preempt_disable();
5197b808 4590 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4591 /*
4592 * CR0.TS may reference the host fpu state, not the guest fpu state,
4593 * so it may be clear at this point.
4594 */
4595 clts();
4596}
4597
4598static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4599{
4600 preempt_enable();
4601}
4602
2953538e 4603static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4604 struct x86_instruction_info *info,
c4f035c6
AK		 4605 enum x86_intercept_stage stage)
4606{
2953538e 4607 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4608}
4609
0017f93a 4610static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4611 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4612{
0017f93a 4613 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4614}
4615
dd856efa
AK		 4616static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4617{
4618 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4619}
4620
4621static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4622{
4623 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4624}
4625
0225fb50 4626static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4627 .read_gpr = emulator_read_gpr,
4628 .write_gpr = emulator_write_gpr,
1871c602 4629 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4630 .write_std = kvm_write_guest_virt_system,
1871c602 4631 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4632 .read_emulated = emulator_read_emulated,
4633 .write_emulated = emulator_write_emulated,
4634 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4635 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4636 .pio_in_emulated = emulator_pio_in_emulated,
4637 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4638 .get_segment = emulator_get_segment,
4639 .set_segment = emulator_set_segment,
5951c442 4640 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4641 .get_gdt = emulator_get_gdt,
160ce1f1 4642 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4643 .set_gdt = emulator_set_gdt,
4644 .set_idt = emulator_set_idt,
52a46617
GN		 4645 .get_cr = emulator_get_cr,
4646 .set_cr = emulator_set_cr,
4cee4798 4647 .set_rflags = emulator_set_rflags,
9c537244 4648 .cpl = emulator_get_cpl,
35aa5375
GN		 4649 .get_dr = emulator_get_dr,
4650 .set_dr = emulator_set_dr,
717746e3
AK		 4651 .set_msr = emulator_set_msr,
4652 .get_msr = emulator_get_msr,
222d21aa 4653 .read_pmc = emulator_read_pmc,
6c3287f7 4654 .halt = emulator_halt,
bcaf5cc5 4655 .wbinvd = emulator_wbinvd,
d6aa1000 4656 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4657 .get_fpu = emulator_get_fpu,
4658 .put_fpu = emulator_put_fpu,
c4f035c6 4659 .intercept = emulator_intercept,
bdb42f5a 4660 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4661};
4662
95cb2295
GN		 4663static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4664{
4665 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4666 /*
4667 * an sti; sti; sequence only disable interrupts for the first
4668 * instruction. So, if the last instruction, be it emulated or
4669 * not, left the system with the INT_STI flag enabled, it
4670 * means that the last instruction is an sti. We should not
4671 * leave the flag on in this case. The same goes for mov ss
4672 */
4673 if (!(int_shadow & mask))
4674 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4675}
4676
54b8486f
GN		 4677static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4678{
4679 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4680 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4681 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4682 else if (ctxt->exception.error_code_valid)
4683 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4684 ctxt->exception.error_code);
54b8486f 4685 else
da9cb575 4686 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4687}
4688
dd856efa 4689static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4690{
9dac77fa 4691 memset(&ctxt->twobyte, 0,
dd856efa 4692 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4693
9dac77fa
AK		 4694 ctxt->fetch.start = 0;
4695 ctxt->fetch.end = 0;
4696 ctxt->io_read.pos = 0;
4697 ctxt->io_read.end = 0;
4698 ctxt->mem_read.pos = 0;
4699 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4700}
4701
8ec4722d
MG		 4702static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4703{
adf52235 4704 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4705 int cs_db, cs_l;
4706
8ec4722d
MG		 4707 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4708
adf52235
TY		 4709 ctxt->eflags = kvm_get_rflags(vcpu);
4710 ctxt->eip = kvm_rip_read(vcpu);
4711 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4712 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4713 cs_l ? X86EMUL_MODE_PROT64 :
4714 cs_db ? X86EMUL_MODE_PROT32 :
4715 X86EMUL_MODE_PROT16;
4716 ctxt->guest_mode = is_guest_mode(vcpu);
4717
dd856efa 4718 init_decode_cache(ctxt);
7ae441ea 4719 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4720}
4721
71f9833b 4722int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4723{
9d74191a 4724 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4725 int ret;
4726
4727 init_emulate_ctxt(vcpu);
4728
9dac77fa
AK		 4729 ctxt->op_bytes = 2;
4730 ctxt->ad_bytes = 2;
4731 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4732 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4733
4734 if (ret != X86EMUL_CONTINUE)
4735 return EMULATE_FAIL;
4736
9dac77fa 4737 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4738 kvm_rip_write(vcpu, ctxt->eip);
4739 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4740
4741 if (irq == NMI_VECTOR)
7460fb4a 4742 vcpu->arch.nmi_pending = 0;
63995653
MG		 4743 else
4744 vcpu->arch.interrupt.pending = false;
4745
4746 return EMULATE_DONE;
4747}
4748EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4749
6d77dbfc
GN		 4750static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4751{
fc3a9157
JR		 4752 int r = EMULATE_DONE;
4753
6d77dbfc
GN		 4754 ++vcpu->stat.insn_emulation_fail;
4755 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4756 if (!is_guest_mode(vcpu)) {
4757 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4758 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4759 vcpu->run->internal.ndata = 0;
4760 r = EMULATE_FAIL;
4761 }
6d77dbfc 4762 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4763
4764 return r;
6d77dbfc
GN		 4765}
4766
93c05d3e 4767static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4768 bool write_fault_to_shadow_pgtable,
4769 int emulation_type)
a6f177ef 4770{
95b3cf69 4771 gpa_t gpa = cr2;
8e3d9d06 4772 pfn_t pfn;
a6f177ef 4773
991eebf9
GN		 4774 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4775 return false;
4776
95b3cf69
XG		 4777 if (!vcpu->arch.mmu.direct_map) {
4778 /*
4779 * Write permission should be allowed since only
4780 * write access need to be emulated.
4781 */
4782 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
22368028 4783
95b3cf69
XG		 4784 /*
4785 * If the mapping is invalid in guest, let cpu retry
4786 * it to generate fault.
4787 */
4788 if (gpa == UNMAPPED_GVA)
4789 return true;
4790 }
a6f177ef 4791
8e3d9d06
XG		 4792 /*
4793 * Do not retry the unhandleable instruction if it faults on the
4794 * readonly host memory, otherwise it will goto a infinite loop:
4795 * retry instruction -> write #PF -> emulation fail -> retry
4796 * instruction -> ...
4797 */
4798 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4799
4800 /*
4801 * If the instruction failed on the error pfn, it can not be fixed,
4802 * report the error to userspace.
4803 */
4804 if (is_error_noslot_pfn(pfn))
4805 return false;
4806
4807 kvm_release_pfn_clean(pfn);
4808
4809 /* The instructions are well-emulated on direct mmu. */
4810 if (vcpu->arch.mmu.direct_map) {
4811 unsigned int indirect_shadow_pages;
4812
4813 spin_lock(&vcpu->kvm->mmu_lock);
4814 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4815 spin_unlock(&vcpu->kvm->mmu_lock);
4816
4817 if (indirect_shadow_pages)
4818 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4819
a6f177ef 4820 return true;
8e3d9d06 4821 }
a6f177ef 4822
95b3cf69
XG		 4823 /*
4824 * if emulation was due to access to shadowed page table
4825 * and it failed try to unshadow page and re-enter the
4826 * guest to let CPU execute the instruction.
4827 */
4828 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4829
4830 /*
4831 * If the access faults on its page table, it can not
4832 * be fixed by unprotecting shadow page and it should
4833 * be reported to userspace.
4834 */
4835 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4836}
4837
1cb3f3ae
XG		 4838static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4839 unsigned long cr2, int emulation_type)
4840{
4841 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4842 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4843
4844 last_retry_eip = vcpu->arch.last_retry_eip;
4845 last_retry_addr = vcpu->arch.last_retry_addr;
4846
4847 /*
4848 * If the emulation is caused by #PF and it is non-page_table
4849 * writing instruction, it means the VM-EXIT is caused by shadow
4850 * page protected, we can zap the shadow page and retry this
4851 * instruction directly.
4852 *
4853 * Note: if the guest uses a non-page-table modifying instruction
4854 * on the PDE that points to the instruction, then we will unmap
4855 * the instruction and go to an infinite loop. So, we cache the
4856 * last retried eip and the last fault address, if we meet the eip
4857 * and the address again, we can break out of the potential infinite
4858 * loop.
4859 */
4860 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4861
4862 if (!(emulation_type & EMULTYPE_RETRY))
4863 return false;
4864
4865 if (x86_page_table_writing_insn(ctxt))
4866 return false;
4867
4868 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4869 return false;
4870
4871 vcpu->arch.last_retry_eip = ctxt->eip;
4872 vcpu->arch.last_retry_addr = cr2;
4873
4874 if (!vcpu->arch.mmu.direct_map)
4875 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4876
22368028 4877 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4878
4879 return true;
4880}
4881
716d51ab
GN		 4882static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4883static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4884
51d8b661
AP		 4885int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4886 unsigned long cr2,
dc25e89e
AP		 4887 int emulation_type,
4888 void *insn,
4889 int insn_len)
bbd9b64e 4890{
95cb2295 4891 int r;
9d74191a 4892 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4893 bool writeback = true;
93c05d3e 4894 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 4895
93c05d3e
XG		 4896 /*
4897 * Clear write_fault_to_shadow_pgtable here to ensure it is
4898 * never reused.
4899 */
4900 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 4901 kvm_clear_exception_queue(vcpu);
8d7d8102 4902
571008da 4903 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4904 init_emulate_ctxt(vcpu);
9d74191a
TY		 4905 ctxt->interruptibility = 0;
4906 ctxt->have_exception = false;
4907 ctxt->perm_ok = false;
bbd9b64e 4908
9d74191a 4909 ctxt->only_vendor_specific_insn
4005996e
AK		 4910 = emulation_type & EMULTYPE_TRAP_UD;
4911
9d74191a 4912 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4913
e46479f8 4914 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4915 ++vcpu->stat.insn_emulation;
1d2887e2 4916 if (r != EMULATION_OK) {
4005996e
AK		 4917 if (emulation_type & EMULTYPE_TRAP_UD)
4918 return EMULATE_FAIL;
991eebf9
GN		 4919 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4920 emulation_type))
bbd9b64e 4921 return EMULATE_DONE;
6d77dbfc
GN		 4922 if (emulation_type & EMULTYPE_SKIP)
4923 return EMULATE_FAIL;
4924 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4925 }
4926 }
4927
ba8afb6b 4928 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4929 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4930 return EMULATE_DONE;
4931 }
4932
1cb3f3ae
XG		 4933 if (retry_instruction(ctxt, cr2, emulation_type))
4934 return EMULATE_DONE;
4935
7ae441ea 4936 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4937 changes registers values during IO operation */
7ae441ea
GN		 4938 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4939 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4940 emulator_invalidate_register_cache(ctxt);
7ae441ea 4941 }
4d2179e1 4942
5cd21917 4943restart:
9d74191a 4944 r = x86_emulate_insn(ctxt);
bbd9b64e 4945
775fde86
JR		 4946 if (r == EMULATION_INTERCEPTED)
4947 return EMULATE_DONE;
4948
d2ddd1c4 4949 if (r == EMULATION_FAILED) {
991eebf9
GN		 4950 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4951 emulation_type))
c3cd7ffa
GN		 4952 return EMULATE_DONE;
4953
6d77dbfc 4954 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4955 }
4956
9d74191a 4957 if (ctxt->have_exception) {
54b8486f 4958 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4959 r = EMULATE_DONE;
4960 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4961 if (!vcpu->arch.pio.in)
4962 vcpu->arch.pio.count = 0;
716d51ab 4963 else {
7ae441ea 4964 writeback = false;
716d51ab
GN		 4965 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4966 }
e85d28f8 4967 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4968 } else if (vcpu->mmio_needed) {
4969 if (!vcpu->mmio_is_write)
4970 writeback = false;
e85d28f8 4971 r = EMULATE_DO_MMIO;
716d51ab 4972 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4973 } else if (r == EMULATION_RESTART)
5cd21917 4974 goto restart;
d2ddd1c4
GN		 4975 else
4976 r = EMULATE_DONE;
f850e2e6 4977
7ae441ea 4978 if (writeback) {
9d74191a
TY		 4979 toggle_interruptibility(vcpu, ctxt->interruptibility);
4980 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4981 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4982 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4983 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4984 } else
4985 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4986
4987 return r;
de7d789a 4988}
51d8b661 4989EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4990
cf8f70bf 4991int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4992{
cf8f70bf 4993 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4994 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4995 size, port, &val, 1);
cf8f70bf 4996 /* do not return to emulator after return from userspace */
7972995b 4997 vcpu->arch.pio.count = 0;
de7d789a
CO		 4998 return ret;
4999}
cf8f70bf 5000EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5001
8cfdc000
ZA		 5002static void tsc_bad(void *info)
5003{
0a3aee0d 5004 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5005}
5006
5007static void tsc_khz_changed(void *data)
c8076604 5008{
8cfdc000
ZA		 5009 struct cpufreq_freqs *freq = data;
5010 unsigned long khz = 0;
5011
5012 if (data)
5013 khz = freq->new;
5014 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5015 khz = cpufreq_quick_get(raw_smp_processor_id());
5016 if (!khz)
5017 khz = tsc_khz;
0a3aee0d 5018 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5019}
5020
c8076604
GH		 5021static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5022 void *data)
5023{
5024 struct cpufreq_freqs *freq = data;
5025 struct kvm *kvm;
5026 struct kvm_vcpu *vcpu;
5027 int i, send_ipi = 0;
5028
8cfdc000
ZA		 5029 /*
5030 * We allow guests to temporarily run on slowing clocks,
5031 * provided we notify them after, or to run on accelerating
5032 * clocks, provided we notify them before. Thus time never
5033 * goes backwards.
5034 *
5035 * However, we have a problem. We can't atomically update
5036 * the frequency of a given CPU from this function; it is
5037 * merely a notifier, which can be called from any CPU.
5038 * Changing the TSC frequency at arbitrary points in time
5039 * requires a recomputation of local variables related to
5040 * the TSC for each VCPU. We must flag these local variables
5041 * to be updated and be sure the update takes place with the
5042 * new frequency before any guests proceed.
5043 *
5044 * Unfortunately, the combination of hotplug CPU and frequency
5045 * change creates an intractable locking scenario; the order
5046 * of when these callouts happen is undefined with respect to
5047 * CPU hotplug, and they can race with each other. As such,
5048 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5049 * undefined; you can actually have a CPU frequency change take
5050 * place in between the computation of X and the setting of the
5051 * variable. To protect against this problem, all updates of
5052 * the per_cpu tsc_khz variable are done in an interrupt
5053 * protected IPI, and all callers wishing to update the value
5054 * must wait for a synchronous IPI to complete (which is trivial
5055 * if the caller is on the CPU already). This establishes the
5056 * necessary total order on variable updates.
5057 *
5058 * Note that because a guest time update may take place
5059 * anytime after the setting of the VCPU's request bit, the
5060 * correct TSC value must be set before the request. However,
5061 * to ensure the update actually makes it to any guest which
5062 * starts running in hardware virtualization between the set
5063 * and the acquisition of the spinlock, we must also ping the
5064 * CPU after setting the request bit.
5065 *
5066 */
5067
c8076604
GH		 5068 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5069 return 0;
5070 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5071 return 0;
8cfdc000
ZA		 5072
5073 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5074
e935b837 5075 raw_spin_lock(&kvm_lock);
c8076604 5076 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5077 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5078 if (vcpu->cpu != freq->cpu)
5079 continue;
c285545f 5080 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5081 if (vcpu->cpu != smp_processor_id())
8cfdc000 5082 send_ipi = 1;
c8076604
GH		 5083 }
5084 }
e935b837 5085 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5086
5087 if (freq->old < freq->new && send_ipi) {
5088 /*
5089 * We upscale the frequency. Must make the guest
5090 * doesn't see old kvmclock values while running with
5091 * the new frequency, otherwise we risk the guest sees
5092 * time go backwards.
5093 *
5094 * In case we update the frequency for another cpu
5095 * (which might be in guest context) send an interrupt
5096 * to kick the cpu out of guest context. Next time
5097 * guest context is entered kvmclock will be updated,
5098 * so the guest will not see stale values.
5099 */
8cfdc000 5100 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5101 }
5102 return 0;
5103}
5104
5105static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5106 .notifier_call = kvmclock_cpufreq_notifier
5107};
5108
5109static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5110 unsigned long action, void *hcpu)
5111{
5112 unsigned int cpu = (unsigned long)hcpu;
5113
5114 switch (action) {
5115 case CPU_ONLINE:
5116 case CPU_DOWN_FAILED:
5117 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5118 break;
5119 case CPU_DOWN_PREPARE:
5120 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5121 break;
5122 }
5123 return NOTIFY_OK;
5124}
5125
5126static struct notifier_block kvmclock_cpu_notifier_block = {
5127 .notifier_call = kvmclock_cpu_notifier,
5128 .priority = -INT_MAX
c8076604
GH		 5129};
5130
b820cc0c
ZA		 5131static void kvm_timer_init(void)
5132{
5133 int cpu;
5134
c285545f 5135 max_tsc_khz = tsc_khz;
8cfdc000 5136 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5137 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5138#ifdef CONFIG_CPU_FREQ
5139 struct cpufreq_policy policy;
5140 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5141 cpu = get_cpu();
5142 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5143 if (policy.cpuinfo.max_freq)
5144 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5145 put_cpu();
c285545f 5146#endif
b820cc0c
ZA		 5147 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5148 CPUFREQ_TRANSITION_NOTIFIER);
5149 }
c285545f 5150 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5151 for_each_online_cpu(cpu)
5152 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5153}
5154
ff9d07a0
ZY		 5155static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5156
f5132b01 5157int kvm_is_in_guest(void)
ff9d07a0 5158{
086c9855 5159 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5160}
5161
5162static int kvm_is_user_mode(void)
5163{
5164 int user_mode = 3;
dcf46b94 5165
086c9855
AS		 5166 if (__this_cpu_read(current_vcpu))
5167 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5168
ff9d07a0
ZY		 5169 return user_mode != 0;
5170}
5171
5172static unsigned long kvm_get_guest_ip(void)
5173{
5174 unsigned long ip = 0;
dcf46b94 5175
086c9855
AS		 5176 if (__this_cpu_read(current_vcpu))
5177 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5178
ff9d07a0
ZY		 5179 return ip;
5180}
5181
5182static struct perf_guest_info_callbacks kvm_guest_cbs = {
5183 .is_in_guest = kvm_is_in_guest,
5184 .is_user_mode = kvm_is_user_mode,
5185 .get_guest_ip = kvm_get_guest_ip,
5186};
5187
5188void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5189{
086c9855 5190 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5191}
5192EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5193
5194void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5195{
086c9855 5196 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5197}
5198EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5199
ce88decf
XG		 5200static void kvm_set_mmio_spte_mask(void)
5201{
5202 u64 mask;
5203 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5204
5205 /*
5206 * Set the reserved bits and the present bit of an paging-structure
5207 * entry to generate page fault with PFER.RSV = 1.
5208 */
5209 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5210 mask |= 1ull;
5211
5212#ifdef CONFIG_X86_64
5213 /*
5214 * If reserved bit is not supported, clear the present bit to disable
5215 * mmio page fault.
5216 */
5217 if (maxphyaddr == 52)
5218 mask &= ~1ull;
5219#endif
5220
5221 kvm_mmu_set_mmio_spte_mask(mask);
5222}
5223
16e8d74d
MT		 5224#ifdef CONFIG_X86_64
5225static void pvclock_gtod_update_fn(struct work_struct *work)
5226{
d828199e
MT		 5227 struct kvm *kvm;
5228
5229 struct kvm_vcpu *vcpu;
5230 int i;
5231
5232 raw_spin_lock(&kvm_lock);
5233 list_for_each_entry(kvm, &vm_list, vm_list)
5234 kvm_for_each_vcpu(i, vcpu, kvm)
5235 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5236 atomic_set(&kvm_guest_has_master_clock, 0);
5237 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5238}
5239
5240static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5241
5242/*
5243 * Notification about pvclock gtod data update.
5244 */
5245static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5246 void *priv)
5247{
5248 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5249 struct timekeeper *tk = priv;
5250
5251 update_pvclock_gtod(tk);
5252
5253 /* disable master clock if host does not trust, or does not
5254 * use, TSC clocksource
5255 */
5256 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5257 atomic_read(&kvm_guest_has_master_clock) != 0)
5258 queue_work(system_long_wq, &pvclock_gtod_work);
5259
5260 return 0;
5261}
5262
5263static struct notifier_block pvclock_gtod_notifier = {
5264 .notifier_call = pvclock_gtod_notify,
5265};
5266#endif
5267
f8c16bba 5268int kvm_arch_init(void *opaque)
043405e1 5269{
b820cc0c 5270 int r;
f8c16bba
ZX		 5271 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5272
f8c16bba
ZX		 5273 if (kvm_x86_ops) {
5274 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5275 r = -EEXIST;
5276 goto out;
f8c16bba
ZX		 5277 }
5278
5279 if (!ops->cpu_has_kvm_support()) {
5280 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5281 r = -EOPNOTSUPP;
5282 goto out;
f8c16bba
ZX		 5283 }
5284 if (ops->disabled_by_bios()) {
5285 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5286 r = -EOPNOTSUPP;
5287 goto out;
f8c16bba
ZX		 5288 }
5289
013f6a5d
MT		 5290 r = -ENOMEM;
5291 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5292 if (!shared_msrs) {
5293 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5294 goto out;
5295 }
5296
97db56ce
AK		 5297 r = kvm_mmu_module_init();
5298 if (r)
013f6a5d 5299 goto out_free_percpu;
97db56ce 5300
ce88decf 5301 kvm_set_mmio_spte_mask();
97db56ce
AK		 5302 kvm_init_msr_list();
5303
f8c16bba 5304 kvm_x86_ops = ops;
7b52345e 5305 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5306 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5307
b820cc0c 5308 kvm_timer_init();
c8076604 5309
ff9d07a0
ZY		 5310 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5311
2acf923e
DC		 5312 if (cpu_has_xsave)
5313 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5314
c5cc421b 5315 kvm_lapic_init();
16e8d74d
MT		 5316#ifdef CONFIG_X86_64
5317 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5318#endif
5319
f8c16bba 5320 return 0;
56c6d28a 5321
013f6a5d
MT		 5322out_free_percpu:
5323 free_percpu(shared_msrs);
56c6d28a 5324out:
56c6d28a 5325 return r;
043405e1 5326}
8776e519 5327
f8c16bba
ZX		 5328void kvm_arch_exit(void)
5329{
ff9d07a0
ZY		 5330 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5331
888d256e
JK		 5332 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5333 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5334 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5335 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5336#ifdef CONFIG_X86_64
5337 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5338#endif
f8c16bba 5339 kvm_x86_ops = NULL;
56c6d28a 5340 kvm_mmu_module_exit();
013f6a5d 5341 free_percpu(shared_msrs);
56c6d28a 5342}
f8c16bba 5343
8776e519
HB		 5344int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5345{
5346 ++vcpu->stat.halt_exits;
5347 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5348 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5349 return 1;
5350 } else {
5351 vcpu->run->exit_reason = KVM_EXIT_HLT;
5352 return 0;
5353 }
5354}
5355EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5356
55cd8e5a
GN		 5357int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5358{
5359 u64 param, ingpa, outgpa, ret;
5360 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5361 bool fast, longmode;
5362 int cs_db, cs_l;
5363
5364 /*
5365 * hypercall generates UD from non zero cpl and real mode
5366 * per HYPER-V spec
5367 */
3eeb3288 5368 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5369 kvm_queue_exception(vcpu, UD_VECTOR);
5370 return 0;
5371 }
5372
5373 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5374 longmode = is_long_mode(vcpu) && cs_l == 1;
5375
5376 if (!longmode) {
ccd46936
GN		 5377 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5378 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5379 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5380 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5381 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5382 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5383 }
5384#ifdef CONFIG_X86_64
5385 else {
5386 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5387 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5388 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5389 }
5390#endif
5391
5392 code = param & 0xffff;
5393 fast = (param >> 16) & 0x1;
5394 rep_cnt = (param >> 32) & 0xfff;
5395 rep_idx = (param >> 48) & 0xfff;
5396
5397 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5398
c25bc163
GN		 5399 switch (code) {
5400 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5401 kvm_vcpu_on_spin(vcpu);
5402 break;
5403 default:
5404 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5405 break;
5406 }
55cd8e5a
GN		 5407
5408 ret = res | (((u64)rep_done & 0xfff) << 32);
5409 if (longmode) {
5410 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5411 } else {
5412 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5413 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5414 }
5415
5416 return 1;
5417}
5418
8776e519
HB		 5419int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5420{
5421 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5422 int r = 1;
8776e519 5423
55cd8e5a
GN		 5424 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5425 return kvm_hv_hypercall(vcpu);
5426
5fdbf976
MT		 5427 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5428 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5429 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5430 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5431 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5432
229456fc 5433 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5434
8776e519
HB		 5435 if (!is_long_mode(vcpu)) {
5436 nr &= 0xFFFFFFFF;
5437 a0 &= 0xFFFFFFFF;
5438 a1 &= 0xFFFFFFFF;
5439 a2 &= 0xFFFFFFFF;
5440 a3 &= 0xFFFFFFFF;
5441 }
5442
07708c4a
JK		 5443 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5444 ret = -KVM_EPERM;
5445 goto out;
5446 }
5447
8776e519 5448 switch (nr) {
b93463aa
AK		 5449 case KVM_HC_VAPIC_POLL_IRQ:
5450 ret = 0;
5451 break;
8776e519
HB		 5452 default:
5453 ret = -KVM_ENOSYS;
5454 break;
5455 }
07708c4a 5456out:
5fdbf976 5457 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5458 ++vcpu->stat.hypercalls;
2f333bcb 5459 return r;
8776e519
HB		 5460}
5461EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5462
b6785def 5463static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5464{
d6aa1000 5465 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5466 char instruction[3];
5fdbf976 5467 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5468
8776e519
HB		 5469 /*
5470 * Blow out the MMU to ensure that no other VCPU has an active mapping
5471 * to ensure that the updated hypercall appears atomically across all
5472 * VCPUs.
5473 */
5474 kvm_mmu_zap_all(vcpu->kvm);
5475
8776e519 5476 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5477
9d74191a 5478 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5479}
5480
b6c7a5dc
HB		 5481/*
5482 * Check if userspace requested an interrupt window, and that the
5483 * interrupt window is open.
5484 *
5485 * No need to exit to userspace if we already have an interrupt queued.
5486 */
851ba692 5487static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5488{
8061823a 5489 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5490 vcpu->run->request_interrupt_window &&
5df56646 5491 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5492}
5493
851ba692 5494static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5495{
851ba692
AK		 5496 struct kvm_run *kvm_run = vcpu->run;
5497
91586a3b 5498 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5499 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5500 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5501 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5502 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5503 else
b6c7a5dc 5504 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5505 kvm_arch_interrupt_allowed(vcpu) &&
5506 !kvm_cpu_has_interrupt(vcpu) &&
5507 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5508}
5509
4484141a 5510static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5511{
5512 struct kvm_lapic *apic = vcpu->arch.apic;
5513 struct page *page;
5514
5515 if (!apic || !apic->vapic_addr)
4484141a 5516 return 0;
b93463aa
AK		 5517
5518 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5519 if (is_error_page(page))
5520 return -EFAULT;
72dc67a6
IE		 5521
5522 vcpu->arch.apic->vapic_page = page;
4484141a 5523 return 0;
b93463aa
AK		 5524}
5525
5526static void vapic_exit(struct kvm_vcpu *vcpu)
5527{
5528 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5529 int idx;
b93463aa
AK		 5530
5531 if (!apic || !apic->vapic_addr)
5532 return;
5533
f656ce01 5534 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5535 kvm_release_page_dirty(apic->vapic_page);
5536 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5537 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5538}
5539
95ba8273
GN		 5540static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5541{
5542 int max_irr, tpr;
5543
5544 if (!kvm_x86_ops->update_cr8_intercept)
5545 return;
5546
88c808fd
AK		 5547 if (!vcpu->arch.apic)
5548 return;
5549
8db3baa2
GN		 5550 if (!vcpu->arch.apic->vapic_addr)
5551 max_irr = kvm_lapic_find_highest_irr(vcpu);
5552 else
5553 max_irr = -1;
95ba8273
GN		 5554
5555 if (max_irr != -1)
5556 max_irr >>= 4;
5557
5558 tpr = kvm_lapic_get_cr8(vcpu);
5559
5560 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5561}
5562
851ba692 5563static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5564{
5565 /* try to reinject previous events if any */
b59bb7bd 5566 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5567 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5568 vcpu->arch.exception.has_error_code,
5569 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5570 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5571 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5572 vcpu->arch.exception.error_code,
5573 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5574 return;
5575 }
5576
95ba8273
GN		 5577 if (vcpu->arch.nmi_injected) {
5578 kvm_x86_ops->set_nmi(vcpu);
5579 return;
5580 }
5581
5582 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5583 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5584 return;
5585 }
5586
5587 /* try to inject new event if pending */
5588 if (vcpu->arch.nmi_pending) {
5589 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5590 --vcpu->arch.nmi_pending;
95ba8273
GN		 5591 vcpu->arch.nmi_injected = true;
5592 kvm_x86_ops->set_nmi(vcpu);
5593 }
c7c9c56c 5594 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5595 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5596 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5597 false);
5598 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5599 }
5600 }
5601}
5602
2acf923e
DC		 5603static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5604{
5605 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5606 !vcpu->guest_xcr0_loaded) {
5607 /* kvm_set_xcr() also depends on this */
5608 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5609 vcpu->guest_xcr0_loaded = 1;
5610 }
5611}
5612
5613static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5614{
5615 if (vcpu->guest_xcr0_loaded) {
5616 if (vcpu->arch.xcr0 != host_xcr0)
5617 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5618 vcpu->guest_xcr0_loaded = 0;
5619 }
5620}
5621
7460fb4a
AK		 5622static void process_nmi(struct kvm_vcpu *vcpu)
5623{
5624 unsigned limit = 2;
5625
5626 /*
5627 * x86 is limited to one NMI running, and one NMI pending after it.
5628 * If an NMI is already in progress, limit further NMIs to just one.
5629 * Otherwise, allow two (and we'll inject the first one immediately).
5630 */
5631 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5632 limit = 1;
5633
5634 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5635 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5636 kvm_make_request(KVM_REQ_EVENT, vcpu);
5637}
5638
d828199e
MT		 5639static void kvm_gen_update_masterclock(struct kvm *kvm)
5640{
5641#ifdef CONFIG_X86_64
5642 int i;
5643 struct kvm_vcpu *vcpu;
5644 struct kvm_arch *ka = &kvm->arch;
5645
5646 spin_lock(&ka->pvclock_gtod_sync_lock);
5647 kvm_make_mclock_inprogress_request(kvm);
5648 /* no guest entries from this point */
5649 pvclock_update_vm_gtod_copy(kvm);
5650
5651 kvm_for_each_vcpu(i, vcpu, kvm)
5652 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5653
5654 /* guest entries allowed */
5655 kvm_for_each_vcpu(i, vcpu, kvm)
5656 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5657
5658 spin_unlock(&ka->pvclock_gtod_sync_lock);
5659#endif
5660}
5661
c7c9c56c
YZ		 5662static void update_eoi_exitmap(struct kvm_vcpu *vcpu)
5663{
5664 u64 eoi_exit_bitmap[4];
5665
5666 memset(eoi_exit_bitmap, 0, 32);
5667
5668 kvm_ioapic_calculate_eoi_exitmap(vcpu, eoi_exit_bitmap);
5669 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5670}
5671
851ba692 5672static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5673{
5674 int r;
6a8b1d13 5675 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5676 vcpu->run->request_interrupt_window;
d6185f20 5677 bool req_immediate_exit = 0;
b6c7a5dc 5678
3e007509 5679 if (vcpu->requests) {
a8eeb04a 5680 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5681 kvm_mmu_unload(vcpu);
a8eeb04a 5682 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5683 __kvm_migrate_timers(vcpu);
d828199e
MT		 5684 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5685 kvm_gen_update_masterclock(vcpu->kvm);
34c238a1
ZA		 5686 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5687 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5688 if (unlikely(r))
5689 goto out;
5690 }
a8eeb04a 5691 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5692 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5693 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5694 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5695 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5696 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5697 r = 0;
5698 goto out;
5699 }
a8eeb04a 5700 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5701 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5702 r = 0;
5703 goto out;
5704 }
a8eeb04a 5705 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5706 vcpu->fpu_active = 0;
5707 kvm_x86_ops->fpu_deactivate(vcpu);
5708 }
af585b92
GN		 5709 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5710 /* Page is swapped out. Do synthetic halt */
5711 vcpu->arch.apf.halted = true;
5712 r = 1;
5713 goto out;
5714 }
c9aaa895
GC		 5715 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5716 record_steal_time(vcpu);
7460fb4a
AK		 5717 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5718 process_nmi(vcpu);
d6185f20
NHE		 5719 req_immediate_exit =
5720 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5721 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5722 kvm_handle_pmu_event(vcpu);
5723 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5724 kvm_deliver_pmi(vcpu);
c7c9c56c
YZ		 5725 if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
5726 update_eoi_exitmap(vcpu);
2f52d58c 5727 }
b93463aa 5728
b463a6f7 5729 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5730 kvm_apic_accept_events(vcpu);
5731 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5732 r = 1;
5733 goto out;
5734 }
5735
b463a6f7
AK		 5736 inject_pending_event(vcpu);
5737
5738 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5739 if (vcpu->arch.nmi_pending)
b463a6f7 5740 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5741 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
b463a6f7
AK		 5742 kvm_x86_ops->enable_irq_window(vcpu);
5743
5744 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5745 /*
5746 * Update architecture specific hints for APIC
5747 * virtual interrupt delivery.
5748 */
5749 if (kvm_x86_ops->hwapic_irr_update)
5750 kvm_x86_ops->hwapic_irr_update(vcpu,
5751 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5752 update_cr8_intercept(vcpu);
5753 kvm_lapic_sync_to_vapic(vcpu);
5754 }
5755 }
5756
d8368af8
AK		 5757 r = kvm_mmu_reload(vcpu);
5758 if (unlikely(r)) {
d905c069 5759 goto cancel_injection;
d8368af8
AK		 5760 }
5761
b6c7a5dc
HB		 5762 preempt_disable();
5763
5764 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5765 if (vcpu->fpu_active)
5766 kvm_load_guest_fpu(vcpu);
2acf923e 5767 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5768
6b7e2d09
XG		 5769 vcpu->mode = IN_GUEST_MODE;
5770
5771 /* We should set ->mode before check ->requests,
5772 * see the comment in make_all_cpus_request.
5773 */
5774 smp_mb();
b6c7a5dc 5775
d94e1dc9 5776 local_irq_disable();
32f88400 5777
6b7e2d09 5778 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5779 || need_resched() || signal_pending(current)) {
6b7e2d09 5780 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5781 smp_wmb();
6c142801
AK		 5782 local_irq_enable();
5783 preempt_enable();
5784 r = 1;
d905c069 5785 goto cancel_injection;
6c142801
AK		 5786 }
5787
f656ce01 5788 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5789
d6185f20
NHE		 5790 if (req_immediate_exit)
5791 smp_send_reschedule(vcpu->cpu);
5792
b6c7a5dc
HB		 5793 kvm_guest_enter();
5794
42dbaa5a 5795 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5796 set_debugreg(0, 7);
5797 set_debugreg(vcpu->arch.eff_db[0], 0);
5798 set_debugreg(vcpu->arch.eff_db[1], 1);
5799 set_debugreg(vcpu->arch.eff_db[2], 2);
5800 set_debugreg(vcpu->arch.eff_db[3], 3);
5801 }
b6c7a5dc 5802
229456fc 5803 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5804 kvm_x86_ops->run(vcpu);
b6c7a5dc 5805
24f1e32c
FW		 5806 /*
5807 * If the guest has used debug registers, at least dr7
5808 * will be disabled while returning to the host.
5809 * If we don't have active breakpoints in the host, we don't
5810 * care about the messed up debug address registers. But if
5811 * we have some of them active, restore the old state.
5812 */
59d8eb53 5813 if (hw_breakpoint_active())
24f1e32c 5814 hw_breakpoint_restore();
42dbaa5a 5815
886b470c
MT		 5816 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5817 native_read_tsc());
1d5f066e 5818
6b7e2d09 5819 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5820 smp_wmb();
b6c7a5dc
HB		 5821 local_irq_enable();
5822
5823 ++vcpu->stat.exits;
5824
5825 /*
5826 * We must have an instruction between local_irq_enable() and
5827 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5828 * the interrupt shadow. The stat.exits increment will do nicely.
5829 * But we need to prevent reordering, hence this barrier():
5830 */
5831 barrier();
5832
5833 kvm_guest_exit();
5834
5835 preempt_enable();
5836
f656ce01 5837 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5838
b6c7a5dc
HB		 5839 /*
5840 * Profile KVM exit RIPs:
5841 */
5842 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5843 unsigned long rip = kvm_rip_read(vcpu);
5844 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5845 }
5846
cc578287
ZA		 5847 if (unlikely(vcpu->arch.tsc_always_catchup))
5848 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5849
5cfb1d5a
MT		 5850 if (vcpu->arch.apic_attention)
5851 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5852
851ba692 5853 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5854 return r;
5855
5856cancel_injection:
5857 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5858 if (unlikely(vcpu->arch.apic_attention))
5859 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5860out:
5861 return r;
5862}
b6c7a5dc 5863
09cec754 5864
851ba692 5865static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5866{
5867 int r;
f656ce01 5868 struct kvm *kvm = vcpu->kvm;
d7690175 5869
f656ce01 5870 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5871 r = vapic_enter(vcpu);
5872 if (r) {
5873 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5874 return r;
5875 }
d7690175
MT		 5876
5877 r = 1;
5878 while (r > 0) {
af585b92
GN		 5879 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5880 !vcpu->arch.apf.halted)
851ba692 5881 r = vcpu_enter_guest(vcpu);
d7690175 5882 else {
f656ce01 5883 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5884 kvm_vcpu_block(vcpu);
f656ce01 5885 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 5886 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5887 kvm_apic_accept_events(vcpu);
09cec754
GN		 5888 switch(vcpu->arch.mp_state) {
5889 case KVM_MP_STATE_HALTED:
d7690175 5890 vcpu->arch.mp_state =
09cec754
GN		 5891 KVM_MP_STATE_RUNNABLE;
5892 case KVM_MP_STATE_RUNNABLE:
af585b92 5893 vcpu->arch.apf.halted = false;
09cec754 5894 break;
66450a21
JK		 5895 case KVM_MP_STATE_INIT_RECEIVED:
5896 break;
09cec754
GN		 5897 default:
5898 r = -EINTR;
5899 break;
5900 }
5901 }
d7690175
MT		 5902 }
5903
09cec754
GN		 5904 if (r <= 0)
5905 break;
5906
5907 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5908 if (kvm_cpu_has_pending_timer(vcpu))
5909 kvm_inject_pending_timer_irqs(vcpu);
5910
851ba692 5911 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5912 r = -EINTR;
851ba692 5913 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5914 ++vcpu->stat.request_irq_exits;
5915 }
af585b92
GN		 5916
5917 kvm_check_async_pf_completion(vcpu);
5918
09cec754
GN		 5919 if (signal_pending(current)) {
5920 r = -EINTR;
851ba692 5921 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5922 ++vcpu->stat.signal_exits;
5923 }
5924 if (need_resched()) {
f656ce01 5925 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5926 kvm_resched(vcpu);
f656ce01 5927 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5928 }
b6c7a5dc
HB		 5929 }
5930
f656ce01 5931 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5932
b93463aa
AK		 5933 vapic_exit(vcpu);
5934
b6c7a5dc
HB		 5935 return r;
5936}
5937
716d51ab
GN		 5938static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5939{
5940 int r;
5941 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5942 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5943 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5944 if (r != EMULATE_DONE)
5945 return 0;
5946 return 1;
5947}
5948
5949static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5950{
5951 BUG_ON(!vcpu->arch.pio.count);
5952
5953 return complete_emulated_io(vcpu);
5954}
5955
f78146b0
AK		 5956/*
5957 * Implements the following, as a state machine:
5958 *
5959 * read:
5960 * for each fragment
87da7e66
XG		 5961 * for each mmio piece in the fragment
5962 * write gpa, len
5963 * exit
5964 * copy data
f78146b0
AK		 5965 * execute insn
5966 *
5967 * write:
5968 * for each fragment
87da7e66
XG		 5969 * for each mmio piece in the fragment
5970 * write gpa, len
5971 * copy data
5972 * exit
f78146b0 5973 */
716d51ab 5974static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5975{
5976 struct kvm_run *run = vcpu->run;
f78146b0 5977 struct kvm_mmio_fragment *frag;
87da7e66 5978 unsigned len;
5287f194 5979
716d51ab 5980 BUG_ON(!vcpu->mmio_needed);
5287f194 5981
716d51ab 5982 /* Complete previous fragment */
87da7e66
XG		 5983 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
5984 len = min(8u, frag->len);
716d51ab 5985 if (!vcpu->mmio_is_write)
87da7e66
XG		 5986 memcpy(frag->data, run->mmio.data, len);
5987
5988 if (frag->len <= 8) {
5989 /* Switch to the next fragment. */
5990 frag++;
5991 vcpu->mmio_cur_fragment++;
5992 } else {
5993 /* Go forward to the next mmio piece. */
5994 frag->data += len;
5995 frag->gpa += len;
5996 frag->len -= len;
5997 }
5998
716d51ab
GN		 5999 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6000 vcpu->mmio_needed = 0;
cef4dea0 6001 if (vcpu->mmio_is_write)
716d51ab
GN		 6002 return 1;
6003 vcpu->mmio_read_completed = 1;
6004 return complete_emulated_io(vcpu);
6005 }
87da7e66 6006
716d51ab
GN		 6007 run->exit_reason = KVM_EXIT_MMIO;
6008 run->mmio.phys_addr = frag->gpa;
6009 if (vcpu->mmio_is_write)
87da7e66
XG		 6010 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6011 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6012 run->mmio.is_write = vcpu->mmio_is_write;
6013 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6014 return 0;
5287f194
AK		 6015}
6016
716d51ab 6017
b6c7a5dc
HB		 6018int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6019{
6020 int r;
6021 sigset_t sigsaved;
6022
e5c30142
AK		 6023 if (!tsk_used_math(current) && init_fpu(current))
6024 return -ENOMEM;
6025
ac9f6dc0
AK		 6026 if (vcpu->sigset_active)
6027 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6028
a4535290 6029 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6030 kvm_vcpu_block(vcpu);
66450a21 6031 kvm_apic_accept_events(vcpu);
d7690175 6032 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6033 r = -EAGAIN;
6034 goto out;
b6c7a5dc
HB		 6035 }
6036
b6c7a5dc 6037 /* re-sync apic's tpr */
eea1cff9
AP		 6038 if (!irqchip_in_kernel(vcpu->kvm)) {
6039 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6040 r = -EINVAL;
6041 goto out;
6042 }
6043 }
b6c7a5dc 6044
716d51ab
GN		 6045 if (unlikely(vcpu->arch.complete_userspace_io)) {
6046 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6047 vcpu->arch.complete_userspace_io = NULL;
6048 r = cui(vcpu);
6049 if (r <= 0)
6050 goto out;
6051 } else
6052 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6053
851ba692 6054 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6055
6056out:
f1d86e46 6057 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6058 if (vcpu->sigset_active)
6059 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6060
b6c7a5dc
HB		 6061 return r;
6062}
6063
6064int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6065{
7ae441ea
GN		 6066 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6067 /*
6068 * We are here if userspace calls get_regs() in the middle of
6069 * instruction emulation. Registers state needs to be copied
4a969980 6070 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6071 * that usually, but some bad designed PV devices (vmware
6072 * backdoor interface) need this to work
6073 */
dd856efa 6074 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6075 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6076 }
5fdbf976
MT		 6077 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6078 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6079 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6080 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6081 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6082 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6083 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6084 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6085#ifdef CONFIG_X86_64
5fdbf976
MT		 6086 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6087 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6088 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6089 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6090 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6091 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6092 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6093 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6094#endif
6095
5fdbf976 6096 regs->rip = kvm_rip_read(vcpu);
91586a3b 6097 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6098
b6c7a5dc
HB		 6099 return 0;
6100}
6101
6102int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6103{
7ae441ea
GN		 6104 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6105 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6106
5fdbf976
MT		 6107 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6108 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6109 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6110 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6111 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6112 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6113 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6114 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6115#ifdef CONFIG_X86_64
5fdbf976
MT		 6116 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6117 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6118 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6119 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6120 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6121 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6122 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6123 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6124#endif
6125
5fdbf976 6126 kvm_rip_write(vcpu, regs->rip);
91586a3b 6127 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6128
b4f14abd
JK		 6129 vcpu->arch.exception.pending = false;
6130
3842d135
AK		 6131 kvm_make_request(KVM_REQ_EVENT, vcpu);
6132
b6c7a5dc
HB		 6133 return 0;
6134}
6135
b6c7a5dc
HB		 6136void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6137{
6138 struct kvm_segment cs;
6139
3e6e0aab 6140 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6141 *db = cs.db;
6142 *l = cs.l;
6143}
6144EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6145
6146int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6147 struct kvm_sregs *sregs)
6148{
89a27f4d 6149 struct desc_ptr dt;
b6c7a5dc 6150
3e6e0aab
GT		 6151 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6152 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6153 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6154 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6155 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6156 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6157
3e6e0aab
GT		 6158 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6159 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6160
6161 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6162 sregs->idt.limit = dt.size;
6163 sregs->idt.base = dt.address;
b6c7a5dc 6164 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6165 sregs->gdt.limit = dt.size;
6166 sregs->gdt.base = dt.address;
b6c7a5dc 6167
4d4ec087 6168 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6169 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6170 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6171 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6172 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6173 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6174 sregs->apic_base = kvm_get_apic_base(vcpu);
6175
923c61bb 6176 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6177
36752c9b 6178 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6179 set_bit(vcpu->arch.interrupt.nr,
6180 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6181
b6c7a5dc
HB		 6182 return 0;
6183}
6184
62d9f0db
MT		 6185int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6186 struct kvm_mp_state *mp_state)
6187{
66450a21 6188 kvm_apic_accept_events(vcpu);
62d9f0db 6189 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6190 return 0;
6191}
6192
6193int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6194 struct kvm_mp_state *mp_state)
6195{
66450a21
JK		 6196 if (!kvm_vcpu_has_lapic(vcpu) &&
6197 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6198 return -EINVAL;
6199
6200 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6201 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6202 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6203 } else
6204 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6205 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6206 return 0;
6207}
6208
7f3d35fd
KW		 6209int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6210 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6211{
9d74191a 6212 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6213 int ret;
e01c2426 6214
8ec4722d 6215 init_emulate_ctxt(vcpu);
c697518a 6216
7f3d35fd 6217 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6218 has_error_code, error_code);
c697518a 6219
c697518a 6220 if (ret)
19d04437 6221 return EMULATE_FAIL;
37817f29 6222
9d74191a
TY		 6223 kvm_rip_write(vcpu, ctxt->eip);
6224 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6225 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6226 return EMULATE_DONE;
37817f29
IE		 6227}
6228EXPORT_SYMBOL_GPL(kvm_task_switch);
6229
b6c7a5dc
HB		 6230int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6231 struct kvm_sregs *sregs)
6232{
6233 int mmu_reset_needed = 0;
63f42e02 6234 int pending_vec, max_bits, idx;
89a27f4d 6235 struct desc_ptr dt;
b6c7a5dc 6236
6d1068b3
PM		 6237 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6238 return -EINVAL;
6239
89a27f4d
GN		 6240 dt.size = sregs->idt.limit;
6241 dt.address = sregs->idt.base;
b6c7a5dc 6242 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6243 dt.size = sregs->gdt.limit;
6244 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6245 kvm_x86_ops->set_gdt(vcpu, &dt);
6246
ad312c7c 6247 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6248 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6249 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6250 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6251
2d3ad1f4 6252 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6253
f6801dff 6254 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6255 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6256 kvm_set_apic_base(vcpu, sregs->apic_base);
6257
4d4ec087 6258 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6259 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6260 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6261
fc78f519 6262 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6263 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6264 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6265 kvm_update_cpuid(vcpu);
63f42e02
XG		 6266
6267 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6268 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6269 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6270 mmu_reset_needed = 1;
6271 }
63f42e02 6272 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6273
6274 if (mmu_reset_needed)
6275 kvm_mmu_reset_context(vcpu);
6276
a50abc3b 6277 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6278 pending_vec = find_first_bit(
6279 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6280 if (pending_vec < max_bits) {
66fd3f7f 6281 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6282 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6283 }
6284
3e6e0aab
GT		 6285 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6286 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6287 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6288 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6289 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6290 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6291
3e6e0aab
GT		 6292 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6293 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6294
5f0269f5
ME		 6295 update_cr8_intercept(vcpu);
6296
9c3e4aab 6297 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6298 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6299 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6300 !is_protmode(vcpu))
9c3e4aab
MT		 6301 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6302
3842d135
AK		 6303 kvm_make_request(KVM_REQ_EVENT, vcpu);
6304
b6c7a5dc
HB		 6305 return 0;
6306}
6307
d0bfb940
JK		 6308int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6309 struct kvm_guest_debug *dbg)
b6c7a5dc 6310{
355be0b9 6311 unsigned long rflags;
ae675ef0 6312 int i, r;
b6c7a5dc 6313
4f926bf2
JK		 6314 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6315 r = -EBUSY;
6316 if (vcpu->arch.exception.pending)
2122ff5e 6317 goto out;
4f926bf2
JK		 6318 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6319 kvm_queue_exception(vcpu, DB_VECTOR);
6320 else
6321 kvm_queue_exception(vcpu, BP_VECTOR);
6322 }
6323
91586a3b
JK		 6324 /*
6325 * Read rflags as long as potentially injected trace flags are still
6326 * filtered out.
6327 */
6328 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6329
6330 vcpu->guest_debug = dbg->control;
6331 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6332 vcpu->guest_debug = 0;
6333
6334 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6335 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6336 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6337 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6338 } else {
6339 for (i = 0; i < KVM_NR_DB_REGS; i++)
6340 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6341 }
c8639010 6342 kvm_update_dr7(vcpu);
ae675ef0 6343
f92653ee
JK		 6344 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6345 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6346 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6347
91586a3b
JK		 6348 /*
6349 * Trigger an rflags update that will inject or remove the trace
6350 * flags.
6351 */
6352 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6353
c8639010 6354 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6355
4f926bf2 6356 r = 0;
d0bfb940 6357
2122ff5e 6358out:
b6c7a5dc
HB		 6359
6360 return r;
6361}
6362
8b006791
ZX		 6363/*
6364 * Translate a guest virtual address to a guest physical address.
6365 */
6366int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6367 struct kvm_translation *tr)
6368{
6369 unsigned long vaddr = tr->linear_address;
6370 gpa_t gpa;
f656ce01 6371 int idx;
8b006791 6372
f656ce01 6373 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6374 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6375 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6376 tr->physical_address = gpa;
6377 tr->valid = gpa != UNMAPPED_GVA;
6378 tr->writeable = 1;
6379 tr->usermode = 0;
8b006791
ZX		 6380
6381 return 0;
6382}
6383
d0752060
HB		 6384int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6385{
98918833
SY		 6386 struct i387_fxsave_struct *fxsave =
6387 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6388
d0752060
HB		 6389 memcpy(fpu->fpr, fxsave->st_space, 128);
6390 fpu->fcw = fxsave->cwd;
6391 fpu->fsw = fxsave->swd;
6392 fpu->ftwx = fxsave->twd;
6393 fpu->last_opcode = fxsave->fop;
6394 fpu->last_ip = fxsave->rip;
6395 fpu->last_dp = fxsave->rdp;
6396 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6397
d0752060
HB		 6398 return 0;
6399}
6400
6401int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6402{
98918833
SY		 6403 struct i387_fxsave_struct *fxsave =
6404 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6405
d0752060
HB		 6406 memcpy(fxsave->st_space, fpu->fpr, 128);
6407 fxsave->cwd = fpu->fcw;
6408 fxsave->swd = fpu->fsw;
6409 fxsave->twd = fpu->ftwx;
6410 fxsave->fop = fpu->last_opcode;
6411 fxsave->rip = fpu->last_ip;
6412 fxsave->rdp = fpu->last_dp;
6413 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6414
d0752060
HB		 6415 return 0;
6416}
6417
10ab25cd 6418int fx_init(struct kvm_vcpu *vcpu)
d0752060 6419{
10ab25cd
JK		 6420 int err;
6421
6422 err = fpu_alloc(&vcpu->arch.guest_fpu);
6423 if (err)
6424 return err;
6425
98918833 6426 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6427
2acf923e
DC		 6428 /*
6429 * Ensure guest xcr0 is valid for loading
6430 */
6431 vcpu->arch.xcr0 = XSTATE_FP;
6432
ad312c7c 6433 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6434
6435 return 0;
d0752060
HB		 6436}
6437EXPORT_SYMBOL_GPL(fx_init);
6438
98918833
SY		 6439static void fx_free(struct kvm_vcpu *vcpu)
6440{
6441 fpu_free(&vcpu->arch.guest_fpu);
6442}
6443
d0752060
HB		 6444void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6445{
2608d7a1 6446 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6447 return;
6448
2acf923e
DC		 6449 /*
6450 * Restore all possible states in the guest,
6451 * and assume host would use all available bits.
6452 * Guest xcr0 would be loaded later.
6453 */
6454 kvm_put_guest_xcr0(vcpu);
d0752060 6455 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6456 __kernel_fpu_begin();
98918833 6457 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6458 trace_kvm_fpu(1);
d0752060 6459}
d0752060
HB		 6460
6461void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6462{
2acf923e
DC		 6463 kvm_put_guest_xcr0(vcpu);
6464
d0752060
HB		 6465 if (!vcpu->guest_fpu_loaded)
6466 return;
6467
6468 vcpu->guest_fpu_loaded = 0;
98918833 6469 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6470 __kernel_fpu_end();
f096ed85 6471 ++vcpu->stat.fpu_reload;
a8eeb04a 6472 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6473 trace_kvm_fpu(0);
d0752060 6474}
e9b11c17
ZX		 6475
6476void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6477{
12f9a48f 6478 kvmclock_reset(vcpu);
7f1ea208 6479
f5f48ee1 6480 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6481 fx_free(vcpu);
e9b11c17
ZX		 6482 kvm_x86_ops->vcpu_free(vcpu);
6483}
6484
6485struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6486 unsigned int id)
6487{
6755bae8
ZA		 6488 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6489 printk_once(KERN_WARNING
6490 "kvm: SMP vm created on host with unstable TSC; "
6491 "guest TSC will not be reliable\n");
26e5215f
AK		 6492 return kvm_x86_ops->vcpu_create(kvm, id);
6493}
e9b11c17 6494
26e5215f
AK		 6495int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6496{
6497 int r;
e9b11c17 6498
0bed3b56 6499 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6500 r = vcpu_load(vcpu);
6501 if (r)
6502 return r;
57f252f2
JK		 6503 kvm_vcpu_reset(vcpu);
6504 r = kvm_mmu_setup(vcpu);
e9b11c17 6505 vcpu_put(vcpu);
e9b11c17 6506
26e5215f 6507 return r;
e9b11c17
ZX		 6508}
6509
42897d86
MT		 6510int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6511{
6512 int r;
8fe8ab46 6513 struct msr_data msr;
42897d86
MT		 6514
6515 r = vcpu_load(vcpu);
6516 if (r)
6517 return r;
8fe8ab46
WA		 6518 msr.data = 0x0;
6519 msr.index = MSR_IA32_TSC;
6520 msr.host_initiated = true;
6521 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6522 vcpu_put(vcpu);
6523
6524 return r;
6525}
6526
d40ccc62 6527void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6528{
9fc77441 6529 int r;
344d9588
GN		 6530 vcpu->arch.apf.msr_val = 0;
6531
9fc77441
MT		 6532 r = vcpu_load(vcpu);
6533 BUG_ON(r);
e9b11c17
ZX		 6534 kvm_mmu_unload(vcpu);
6535 vcpu_put(vcpu);
6536
98918833 6537 fx_free(vcpu);
e9b11c17
ZX		 6538 kvm_x86_ops->vcpu_free(vcpu);
6539}
6540
66450a21 6541void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6542{
7460fb4a
AK		 6543 atomic_set(&vcpu->arch.nmi_queued, 0);
6544 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6545 vcpu->arch.nmi_injected = false;
6546
42dbaa5a
JK		 6547 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6548 vcpu->arch.dr6 = DR6_FIXED_1;
6549 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6550 kvm_update_dr7(vcpu);
42dbaa5a 6551
3842d135 6552 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6553 vcpu->arch.apf.msr_val = 0;
c9aaa895 6554 vcpu->arch.st.msr_val = 0;
3842d135 6555
12f9a48f
GC		 6556 kvmclock_reset(vcpu);
6557
af585b92
GN		 6558 kvm_clear_async_pf_completion_queue(vcpu);
6559 kvm_async_pf_hash_reset(vcpu);
6560 vcpu->arch.apf.halted = false;
3842d135 6561
f5132b01
GN		 6562 kvm_pmu_reset(vcpu);
6563
66f7b72e
JS		 6564 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6565 vcpu->arch.regs_avail = ~0;
6566 vcpu->arch.regs_dirty = ~0;
6567
57f252f2 6568 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6569}
6570
66450a21
JK		 6571void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6572{
6573 struct kvm_segment cs;
6574
6575 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6576 cs.selector = vector << 8;
6577 cs.base = vector << 12;
6578 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6579 kvm_rip_write(vcpu, 0);
6580}
6581
10474ae8 6582int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6583{
ca84d1a2
ZA		 6584 struct kvm *kvm;
6585 struct kvm_vcpu *vcpu;
6586 int i;
0dd6a6ed
ZA		 6587 int ret;
6588 u64 local_tsc;
6589 u64 max_tsc = 0;
6590 bool stable, backwards_tsc = false;
18863bdd
AK		 6591
6592 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6593 ret = kvm_x86_ops->hardware_enable(garbage);
6594 if (ret != 0)
6595 return ret;
6596
6597 local_tsc = native_read_tsc();
6598 stable = !check_tsc_unstable();
6599 list_for_each_entry(kvm, &vm_list, vm_list) {
6600 kvm_for_each_vcpu(i, vcpu, kvm) {
6601 if (!stable && vcpu->cpu == smp_processor_id())
6602 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6603 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6604 backwards_tsc = true;
6605 if (vcpu->arch.last_host_tsc > max_tsc)
6606 max_tsc = vcpu->arch.last_host_tsc;
6607 }
6608 }
6609 }
6610
6611 /*
6612 * Sometimes, even reliable TSCs go backwards. This happens on
6613 * platforms that reset TSC during suspend or hibernate actions, but
6614 * maintain synchronization. We must compensate. Fortunately, we can
6615 * detect that condition here, which happens early in CPU bringup,
6616 * before any KVM threads can be running. Unfortunately, we can't
6617 * bring the TSCs fully up to date with real time, as we aren't yet far
6618 * enough into CPU bringup that we know how much real time has actually
6619 * elapsed; our helper function, get_kernel_ns() will be using boot
6620 * variables that haven't been updated yet.
6621 *
6622 * So we simply find the maximum observed TSC above, then record the
6623 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6624 * the adjustment will be applied. Note that we accumulate
6625 * adjustments, in case multiple suspend cycles happen before some VCPU
6626 * gets a chance to run again. In the event that no KVM threads get a
6627 * chance to run, we will miss the entire elapsed period, as we'll have
6628 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6629 * loose cycle time. This isn't too big a deal, since the loss will be
6630 * uniform across all VCPUs (not to mention the scenario is extremely
6631 * unlikely). It is possible that a second hibernate recovery happens
6632 * much faster than a first, causing the observed TSC here to be
6633 * smaller; this would require additional padding adjustment, which is
6634 * why we set last_host_tsc to the local tsc observed here.
6635 *
6636 * N.B. - this code below runs only on platforms with reliable TSC,
6637 * as that is the only way backwards_tsc is set above. Also note
6638 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6639 * have the same delta_cyc adjustment applied if backwards_tsc
6640 * is detected. Note further, this adjustment is only done once,
6641 * as we reset last_host_tsc on all VCPUs to stop this from being
6642 * called multiple times (one for each physical CPU bringup).
6643 *
4a969980 6644 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6645 * will be compensated by the logic in vcpu_load, which sets the TSC to
6646 * catchup mode. This will catchup all VCPUs to real time, but cannot
6647 * guarantee that they stay in perfect synchronization.
6648 */
6649 if (backwards_tsc) {
6650 u64 delta_cyc = max_tsc - local_tsc;
6651 list_for_each_entry(kvm, &vm_list, vm_list) {
6652 kvm_for_each_vcpu(i, vcpu, kvm) {
6653 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6654 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6655 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6656 &vcpu->requests);
0dd6a6ed
ZA		 6657 }
6658
6659 /*
6660 * We have to disable TSC offset matching.. if you were
6661 * booting a VM while issuing an S4 host suspend....
6662 * you may have some problem. Solving this issue is
6663 * left as an exercise to the reader.
6664 */
6665 kvm->arch.last_tsc_nsec = 0;
6666 kvm->arch.last_tsc_write = 0;
6667 }
6668
6669 }
6670 return 0;
e9b11c17
ZX		 6671}
6672
6673void kvm_arch_hardware_disable(void *garbage)
6674{
6675 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6676 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6677}
6678
6679int kvm_arch_hardware_setup(void)
6680{
6681 return kvm_x86_ops->hardware_setup();
6682}
6683
6684void kvm_arch_hardware_unsetup(void)
6685{
6686 kvm_x86_ops->hardware_unsetup();
6687}
6688
6689void kvm_arch_check_processor_compat(void *rtn)
6690{
6691 kvm_x86_ops->check_processor_compatibility(rtn);
6692}
6693
3e515705
AK		 6694bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6695{
6696 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6697}
6698
54e9818f
GN		 6699struct static_key kvm_no_apic_vcpu __read_mostly;
6700
e9b11c17
ZX		 6701int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6702{
6703 struct page *page;
6704 struct kvm *kvm;
6705 int r;
6706
6707 BUG_ON(vcpu->kvm == NULL);
6708 kvm = vcpu->kvm;
6709
9aabc88f 6710 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6711 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6712 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6713 else
a4535290 6714 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6715
6716 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6717 if (!page) {
6718 r = -ENOMEM;
6719 goto fail;
6720 }
ad312c7c 6721 vcpu->arch.pio_data = page_address(page);
e9b11c17 6722
cc578287 6723 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6724
e9b11c17
ZX		 6725 r = kvm_mmu_create(vcpu);
6726 if (r < 0)
6727 goto fail_free_pio_data;
6728
6729 if (irqchip_in_kernel(kvm)) {
6730 r = kvm_create_lapic(vcpu);
6731 if (r < 0)
6732 goto fail_mmu_destroy;
54e9818f
GN		 6733 } else
6734 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6735
890ca9ae
HY		 6736 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6737 GFP_KERNEL);
6738 if (!vcpu->arch.mce_banks) {
6739 r = -ENOMEM;
443c39bc 6740 goto fail_free_lapic;
890ca9ae
HY		 6741 }
6742 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6743
f5f48ee1
SY		 6744 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6745 goto fail_free_mce_banks;
6746
66f7b72e
JS		 6747 r = fx_init(vcpu);
6748 if (r)
6749 goto fail_free_wbinvd_dirty_mask;
6750
ba904635 6751 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6752 vcpu->arch.pv_time_enabled = false;
af585b92 6753 kvm_async_pf_hash_reset(vcpu);
f5132b01 6754 kvm_pmu_init(vcpu);
af585b92 6755
e9b11c17 6756 return 0;
66f7b72e
JS		 6757fail_free_wbinvd_dirty_mask:
6758 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6759fail_free_mce_banks:
6760 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6761fail_free_lapic:
6762 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6763fail_mmu_destroy:
6764 kvm_mmu_destroy(vcpu);
6765fail_free_pio_data:
ad312c7c 6766 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6767fail:
6768 return r;
6769}
6770
6771void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6772{
f656ce01
MT		 6773 int idx;
6774
f5132b01 6775 kvm_pmu_destroy(vcpu);
36cb93fd 6776 kfree(vcpu->arch.mce_banks);
e9b11c17 6777 kvm_free_lapic(vcpu);
f656ce01 6778 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6779 kvm_mmu_destroy(vcpu);
f656ce01 6780 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6781 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6782 if (!irqchip_in_kernel(vcpu->kvm))
6783 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6784}
d19a9cd2 6785
e08b9637 6786int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6787{
e08b9637
CO		 6788 if (type)
6789 return -EINVAL;
6790
f05e70ac 6791 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6792 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6793
5550af4d
SY		 6794 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6795 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6796 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6797 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6798 &kvm->arch.irq_sources_bitmap);
5550af4d 6799
038f8c11 6800 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6801 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6802 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6803
6804 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6805
d89f5eff 6806 return 0;
d19a9cd2
ZX		 6807}
6808
6809static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6810{
9fc77441
MT		 6811 int r;
6812 r = vcpu_load(vcpu);
6813 BUG_ON(r);
d19a9cd2
ZX		 6814 kvm_mmu_unload(vcpu);
6815 vcpu_put(vcpu);
6816}
6817
6818static void kvm_free_vcpus(struct kvm *kvm)
6819{
6820 unsigned int i;
988a2cae 6821 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6822
6823 /*
6824 * Unpin any mmu pages first.
6825 */
af585b92
GN		 6826 kvm_for_each_vcpu(i, vcpu, kvm) {
6827 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6828 kvm_unload_vcpu_mmu(vcpu);
af585b92 6829 }
988a2cae
GN		 6830 kvm_for_each_vcpu(i, vcpu, kvm)
6831 kvm_arch_vcpu_free(vcpu);
6832
6833 mutex_lock(&kvm->lock);
6834 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6835 kvm->vcpus[i] = NULL;
d19a9cd2 6836
988a2cae
GN		 6837 atomic_set(&kvm->online_vcpus, 0);
6838 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6839}
6840
ad8ba2cd
SY		 6841void kvm_arch_sync_events(struct kvm *kvm)
6842{
ba4cef31 6843 kvm_free_all_assigned_devices(kvm);
aea924f6 6844 kvm_free_pit(kvm);
ad8ba2cd
SY		 6845}
6846
d19a9cd2
ZX		 6847void kvm_arch_destroy_vm(struct kvm *kvm)
6848{
6eb55818 6849 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6850 kfree(kvm->arch.vpic);
6851 kfree(kvm->arch.vioapic);
d19a9cd2 6852 kvm_free_vcpus(kvm);
3d45830c
AK		 6853 if (kvm->arch.apic_access_page)
6854 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6855 if (kvm->arch.ept_identity_pagetable)
6856 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6857 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6858}
0de10343 6859
db3fe4eb
TY		 6860void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6861 struct kvm_memory_slot *dont)
6862{
6863 int i;
6864
d89cc617
TY		 6865 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6866 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6867 kvm_kvfree(free->arch.rmap[i]);
6868 free->arch.rmap[i] = NULL;
77d11309 6869 }
d89cc617
TY		 6870 if (i == 0)
6871 continue;
6872
6873 if (!dont || free->arch.lpage_info[i - 1] !=
6874 dont->arch.lpage_info[i - 1]) {
6875 kvm_kvfree(free->arch.lpage_info[i - 1]);
6876 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6877 }
6878 }
6879}
6880
6881int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6882{
6883 int i;
6884
d89cc617 6885 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6886 unsigned long ugfn;
6887 int lpages;
d89cc617 6888 int level = i + 1;
db3fe4eb
TY		 6889
6890 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6891 slot->base_gfn, level) + 1;
6892
d89cc617
TY		 6893 slot->arch.rmap[i] =
6894 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6895 if (!slot->arch.rmap[i])
77d11309 6896 goto out_free;
d89cc617
TY		 6897 if (i == 0)
6898 continue;
77d11309 6899
d89cc617
TY		 6900 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6901 sizeof(*slot->arch.lpage_info[i - 1]));
6902 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6903 goto out_free;
6904
6905 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6906 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6907 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6908 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6909 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6910 /*
6911 * If the gfn and userspace address are not aligned wrt each
6912 * other, or if explicitly asked to, disable large page
6913 * support for this slot
6914 */
6915 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6916 !kvm_largepages_enabled()) {
6917 unsigned long j;
6918
6919 for (j = 0; j < lpages; ++j)
d89cc617 6920 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6921 }
6922 }
6923
6924 return 0;
6925
6926out_free:
d89cc617
TY		 6927 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6928 kvm_kvfree(slot->arch.rmap[i]);
6929 slot->arch.rmap[i] = NULL;
6930 if (i == 0)
6931 continue;
6932
6933 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6934 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6935 }
6936 return -ENOMEM;
6937}
6938
f7784b8e
MT		 6939int kvm_arch_prepare_memory_region(struct kvm *kvm,
6940 struct kvm_memory_slot *memslot,
7b6195a9
TY		 6941 struct kvm_userspace_memory_region *mem,
6942 enum kvm_mr_change change)
0de10343 6943{
7a905b14
TY		 6944 /*
6945 * Only private memory slots need to be mapped here since
6946 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 6947 */
7b6195a9 6948 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 6949 unsigned long userspace_addr;
604b38ac 6950
7a905b14
TY		 6951 /*
6952 * MAP_SHARED to prevent internal slot pages from being moved
6953 * by fork()/COW.
6954 */
7b6195a9 6955 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 6956 PROT_READ | PROT_WRITE,
6957 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 6958
7a905b14
TY		 6959 if (IS_ERR((void *)userspace_addr))
6960 return PTR_ERR((void *)userspace_addr);
604b38ac 6961
7a905b14 6962 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6963 }
6964
f7784b8e
MT		 6965 return 0;
6966}
6967
6968void kvm_arch_commit_memory_region(struct kvm *kvm,
6969 struct kvm_userspace_memory_region *mem,
8482644a
TY		 6970 const struct kvm_memory_slot *old,
6971 enum kvm_mr_change change)
f7784b8e
MT		 6972{
6973
8482644a 6974 int nr_mmu_pages = 0;
f7784b8e 6975
8482644a 6976 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 6977 int ret;
6978
8482644a
TY		 6979 ret = vm_munmap(old->userspace_addr,
6980 old->npages * PAGE_SIZE);
f7784b8e
MT		 6981 if (ret < 0)
6982 printk(KERN_WARNING
6983 "kvm_vm_ioctl_set_memory_region: "
6984 "failed to munmap memory\n");
6985 }
6986
48c0e4e9
XG		 6987 if (!kvm->arch.n_requested_mmu_pages)
6988 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6989
48c0e4e9 6990 if (nr_mmu_pages)
0de10343 6991 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 6992 /*
6993 * Write protect all pages for dirty logging.
6994 * Existing largepage mappings are destroyed here and new ones will
6995 * not be created until the end of the logging.
6996 */
8482644a 6997 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 6998 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3b4dc3a0
MT		 6999 /*
7000 * If memory slot is created, or moved, we need to clear all
7001 * mmio sptes.
7002 */
8482644a 7003 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
982b3394 7004 kvm_mmu_zap_mmio_sptes(kvm);
3b4dc3a0
MT		 7005 kvm_reload_remote_mmus(kvm);
7006 }
0de10343 7007}
1d737c8a 7008
2df72e9b 7009void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 7010{
7011 kvm_mmu_zap_all(kvm);
8986ecc0 7012 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 7013}
7014
2df72e9b
MT		 7015void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7016 struct kvm_memory_slot *slot)
7017{
7018 kvm_arch_flush_shadow_all(kvm);
7019}
7020
1d737c8a
ZX		 7021int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7022{
af585b92
GN		 7023 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7024 !vcpu->arch.apf.halted)
7025 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7026 || kvm_apic_has_events(vcpu)
7460fb4a 7027 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7028 (kvm_arch_interrupt_allowed(vcpu) &&
7029 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7030}
5736199a 7031
b6d33834 7032int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7033{
b6d33834 7034 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7035}
78646121
GN		 7036
7037int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7038{
7039 return kvm_x86_ops->interrupt_allowed(vcpu);
7040}
229456fc 7041
f92653ee
JK		 7042bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7043{
7044 unsigned long current_rip = kvm_rip_read(vcpu) +
7045 get_segment_base(vcpu, VCPU_SREG_CS);
7046
7047 return current_rip == linear_rip;
7048}
7049EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7050
94fe45da
JK		 7051unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7052{
7053 unsigned long rflags;
7054
7055 rflags = kvm_x86_ops->get_rflags(vcpu);
7056 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7057 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7058 return rflags;
7059}
7060EXPORT_SYMBOL_GPL(kvm_get_rflags);
7061
7062void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7063{
7064 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7065 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7066 rflags |= X86_EFLAGS_TF;
94fe45da 7067 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7068 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7069}
7070EXPORT_SYMBOL_GPL(kvm_set_rflags);
7071
56028d08
GN		 7072void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7073{
7074 int r;
7075
fb67e14f 7076 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7077 is_error_page(work->page))
56028d08
GN		 7078 return;
7079
7080 r = kvm_mmu_reload(vcpu);
7081 if (unlikely(r))
7082 return;
7083
fb67e14f
XG		 7084 if (!vcpu->arch.mmu.direct_map &&
7085 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7086 return;
7087
56028d08
GN		 7088 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7089}
7090
af585b92
GN		 7091static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7092{
7093 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7094}
7095
7096static inline u32 kvm_async_pf_next_probe(u32 key)
7097{
7098 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7099}
7100
7101static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7102{
7103 u32 key = kvm_async_pf_hash_fn(gfn);
7104
7105 while (vcpu->arch.apf.gfns[key] != ~0)
7106 key = kvm_async_pf_next_probe(key);
7107
7108 vcpu->arch.apf.gfns[key] = gfn;
7109}
7110
7111static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7112{
7113 int i;
7114 u32 key = kvm_async_pf_hash_fn(gfn);
7115
7116 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7117 (vcpu->arch.apf.gfns[key] != gfn &&
7118 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7119 key = kvm_async_pf_next_probe(key);
7120
7121 return key;
7122}
7123
7124bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7125{
7126 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7127}
7128
7129static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7130{
7131 u32 i, j, k;
7132
7133 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7134 while (true) {
7135 vcpu->arch.apf.gfns[i] = ~0;
7136 do {
7137 j = kvm_async_pf_next_probe(j);
7138 if (vcpu->arch.apf.gfns[j] == ~0)
7139 return;
7140 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7141 /*
7142 * k lies cyclically in ]i,j]
7143 * | i.k.j |
7144 * |....j i.k.| or |.k..j i...|
7145 */
7146 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7147 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7148 i = j;
7149 }
7150}
7151
7c90705b
GN		 7152static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7153{
7154
7155 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7156 sizeof(val));
7157}
7158
af585b92
GN		 7159void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7160 struct kvm_async_pf *work)
7161{
6389ee94
AK		 7162 struct x86_exception fault;
7163
7c90705b 7164 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7165 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7166
7167 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7168 (vcpu->arch.apf.send_user_only &&
7169 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7170 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7171 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7172 fault.vector = PF_VECTOR;
7173 fault.error_code_valid = true;
7174 fault.error_code = 0;
7175 fault.nested_page_fault = false;
7176 fault.address = work->arch.token;
7177 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7178 }
af585b92
GN		 7179}
7180
7181void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7182 struct kvm_async_pf *work)
7183{
6389ee94
AK		 7184 struct x86_exception fault;
7185
7c90705b
GN		 7186 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7187 if (is_error_page(work->page))
7188 work->arch.token = ~0; /* broadcast wakeup */
7189 else
7190 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7191
7192 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7193 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7194 fault.vector = PF_VECTOR;
7195 fault.error_code_valid = true;
7196 fault.error_code = 0;
7197 fault.nested_page_fault = false;
7198 fault.address = work->arch.token;
7199 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7200 }
e6d53e3b 7201 vcpu->arch.apf.halted = false;
a4fa1635 7202 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7203}
7204
7205bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7206{
7207 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7208 return true;
7209 else
7210 return !kvm_event_needs_reinjection(vcpu) &&
7211 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7212}
7213
229456fc
MT		 7214EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7215EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7216EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7217EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7218EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7219EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7220EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7221EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7222EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7223EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7224EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7225EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)