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KVM: X86: support paravirtualized help for TLB shootdowns
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM		 110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
9ed96e87
MT		 113unsigned int min_timer_period_us = 500;
114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT		 116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW		 138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK		 141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY		 151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
188 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
191 { "mmu_flooded", VM_STAT(mmu_flooded) },
192 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 194 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 196 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 197 { "max_mmu_page_hash_collisions",
198 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 199 { NULL }
200};
201
2acf923e
DC		 202u64 __read_mostly host_xcr0;
203
b6785def 204static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 205
af585b92
GN		 206static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
207{
208 int i;
209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
210 vcpu->arch.apf.gfns[i] = ~0;
211}
212
18863bdd
AK		 213static void kvm_on_user_return(struct user_return_notifier *urn)
214{
215 unsigned slot;
18863bdd
AK		 216 struct kvm_shared_msrs *locals
217 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 218 struct kvm_shared_msr_values *values;
1650b4eb
IA		 219 unsigned long flags;
220
221 /*
222 * Disabling irqs at this point since the following code could be
223 * interrupted and executed through kvm_arch_hardware_disable()
224 */
225 local_irq_save(flags);
226 if (locals->registered) {
227 locals->registered = false;
228 user_return_notifier_unregister(urn);
229 }
230 local_irq_restore(flags);
18863bdd 231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 232 values = &locals->values[slot];
233 if (values->host != values->curr) {
234 wrmsrl(shared_msrs_global.msrs[slot], values->host);
235 values->curr = values->host;
18863bdd
AK		 236 }
237 }
18863bdd
AK		 238}
239
2bf78fa7 240static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 241{
18863bdd 242 u64 value;
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 245
2bf78fa7
SY		 246 /* only read, and nobody should modify it at this time,
247 * so don't need lock */
248 if (slot >= shared_msrs_global.nr) {
249 printk(KERN_ERR "kvm: invalid MSR slot!");
250 return;
251 }
252 rdmsrl_safe(msr, &value);
253 smsr->values[slot].host = value;
254 smsr->values[slot].curr = value;
255}
256
257void kvm_define_shared_msr(unsigned slot, u32 msr)
258{
0123be42 259 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 260 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 261 if (slot >= shared_msrs_global.nr)
262 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 263}
264EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
265
266static void kvm_shared_msr_cpu_online(void)
267{
268 unsigned i;
18863bdd
AK		 269
270 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 271 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 272}
273
8b3c3104 274int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 278 int err;
18863bdd 279
2bf78fa7 280 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 281 return 0;
2bf78fa7 282 smsr->values[slot].curr = value;
8b3c3104
AH		 283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
284 if (err)
285 return 1;
286
18863bdd
AK		 287 if (!smsr->registered) {
288 smsr->urn.on_user_return = kvm_on_user_return;
289 user_return_notifier_register(&smsr->urn);
290 smsr->registered = true;
291 }
8b3c3104 292 return 0;
18863bdd
AK		 293}
294EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
295
13a34e06 296static void drop_user_return_notifiers(void)
3548bab5 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 300
301 if (smsr->registered)
302 kvm_on_user_return(&smsr->urn);
303}
304
6866b83e
CO		 305u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
306{
8a5a87d9 307 return vcpu->arch.apic_base;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_get_apic_base);
310
58cb628d
JK		 311int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
312{
313 u64 old_state = vcpu->arch.apic_base &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 new_state = msr_info->data &
316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 319
d3802286
JM		 320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
321 return 1;
58cb628d 322 if (!msr_info->host_initiated &&
d3802286 323 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
326 old_state == 0)))
327 return 1;
328
329 kvm_lapic_set_base(vcpu, msr_info->data);
330 return 0;
6866b83e
CO		 331}
332EXPORT_SYMBOL_GPL(kvm_set_apic_base);
333
2605fc21 334asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 335{
336 /* Fault while not rebooting. We want the trace. */
337 BUG();
338}
339EXPORT_SYMBOL_GPL(kvm_spurious_fault);
340
3fd28fce
ED		 341#define EXCPT_BENIGN 0
342#define EXCPT_CONTRIBUTORY 1
343#define EXCPT_PF 2
344
345static int exception_class(int vector)
346{
347 switch (vector) {
348 case PF_VECTOR:
349 return EXCPT_PF;
350 case DE_VECTOR:
351 case TS_VECTOR:
352 case NP_VECTOR:
353 case SS_VECTOR:
354 case GP_VECTOR:
355 return EXCPT_CONTRIBUTORY;
356 default:
357 break;
358 }
359 return EXCPT_BENIGN;
360}
361
d6e8c854
NA		 362#define EXCPT_FAULT 0
363#define EXCPT_TRAP 1
364#define EXCPT_ABORT 2
365#define EXCPT_INTERRUPT 3
366
367static int exception_type(int vector)
368{
369 unsigned int mask;
370
371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
372 return EXCPT_INTERRUPT;
373
374 mask = 1 << vector;
375
376 /* #DB is trap, as instruction watchpoints are handled elsewhere */
377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
378 return EXCPT_TRAP;
379
380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
381 return EXCPT_ABORT;
382
383 /* Reserved exceptions will result in fault */
384 return EXCPT_FAULT;
385}
386
3fd28fce 387static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 388 unsigned nr, bool has_error, u32 error_code,
389 bool reinject)
3fd28fce
ED		 390{
391 u32 prev_nr;
392 int class1, class2;
393
3842d135
AK		 394 kvm_make_request(KVM_REQ_EVENT, vcpu);
395
664f8e26 396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 397 queue:
3ffb2468
NA		 398 if (has_error && !is_protmode(vcpu))
399 has_error = false;
664f8e26
WL		 400 if (reinject) {
401 /*
402 * On vmentry, vcpu->arch.exception.pending is only
403 * true if an event injection was blocked by
404 * nested_run_pending. In that case, however,
405 * vcpu_enter_guest requests an immediate exit,
406 * and the guest shouldn't proceed far enough to
407 * need reinjection.
408 */
409 WARN_ON_ONCE(vcpu->arch.exception.pending);
410 vcpu->arch.exception.injected = true;
411 } else {
412 vcpu->arch.exception.pending = true;
413 vcpu->arch.exception.injected = false;
414 }
3fd28fce
ED		 415 vcpu->arch.exception.has_error_code = has_error;
416 vcpu->arch.exception.nr = nr;
417 vcpu->arch.exception.error_code = error_code;
418 return;
419 }
420
421 /* to check exception */
422 prev_nr = vcpu->arch.exception.nr;
423 if (prev_nr == DF_VECTOR) {
424 /* triple fault -> shutdown */
a8eeb04a 425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 426 return;
427 }
428 class1 = exception_class(prev_nr);
429 class2 = exception_class(nr);
430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 432 /*
433 * Generate double fault per SDM Table 5-5. Set
434 * exception.pending = true so that the double fault
435 * can trigger a nested vmexit.
436 */
3fd28fce 437 vcpu->arch.exception.pending = true;
664f8e26 438 vcpu->arch.exception.injected = false;
3fd28fce
ED		 439 vcpu->arch.exception.has_error_code = true;
440 vcpu->arch.exception.nr = DF_VECTOR;
441 vcpu->arch.exception.error_code = 0;
442 } else
443 /* replace previous exception with a new one in a hope
444 that instruction re-execution will regenerate lost
445 exception */
446 goto queue;
447}
448
298101da
AK		 449void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
450{
ce7ddec4 451 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 452}
453EXPORT_SYMBOL_GPL(kvm_queue_exception);
454
ce7ddec4
JR		 455void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
456{
457 kvm_multiple_exception(vcpu, nr, false, 0, true);
458}
459EXPORT_SYMBOL_GPL(kvm_requeue_exception);
460
6affcbed 461int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 462{
db8fcefa
AP		 463 if (err)
464 kvm_inject_gp(vcpu, 0);
465 else
6affcbed
KH		 466 return kvm_skip_emulated_instruction(vcpu);
467
468 return 1;
db8fcefa
AP		 469}
470EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 471
6389ee94 472void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 473{
474 ++vcpu->stat.pf_guest;
adfe20fb
WL		 475 vcpu->arch.exception.nested_apf =
476 is_guest_mode(vcpu) && fault->async_page_fault;
477 if (vcpu->arch.exception.nested_apf)
478 vcpu->arch.apf.nested_apf_token = fault->address;
479 else
480 vcpu->arch.cr2 = fault->address;
6389ee94 481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 482}
27d6c865 483EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 484
ef54bcfe 485static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 486{
6389ee94
AK		 487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 489 else
6389ee94 490 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 491
492 return fault->nested_page_fault;
d4f8cf66
JR		 493}
494
3419ffc8
SY		 495void kvm_inject_nmi(struct kvm_vcpu *vcpu)
496{
7460fb4a
AK		 497 atomic_inc(&vcpu->arch.nmi_queued);
498 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 499}
500EXPORT_SYMBOL_GPL(kvm_inject_nmi);
501
298101da
AK		 502void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
503{
ce7ddec4 504 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 505}
506EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
507
ce7ddec4
JR		 508void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
509{
510 kvm_multiple_exception(vcpu, nr, true, error_code, true);
511}
512EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
513
0a79b009
AK		 514/*
515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
516 * a #GP and return false.
517 */
518bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 519{
0a79b009
AK		 520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
521 return true;
522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
523 return false;
298101da 524}
0a79b009 525EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 526
16f8a6f9
NA		 527bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
528{
529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
530 return true;
531
532 kvm_queue_exception(vcpu, UD_VECTOR);
533 return false;
534}
535EXPORT_SYMBOL_GPL(kvm_require_dr);
536
ec92fe44
JR		 537/*
538 * This function will be used to read from the physical memory of the currently
54bf36aa 539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 540 * can read from guest physical or from the guest's guest physical memory.
541 */
542int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
543 gfn_t ngfn, void *data, int offset, int len,
544 u32 access)
545{
54987b7a 546 struct x86_exception exception;
ec92fe44
JR		 547 gfn_t real_gfn;
548 gpa_t ngpa;
549
550 ngpa = gfn_to_gpa(ngfn);
54987b7a 551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 552 if (real_gfn == UNMAPPED_GVA)
553 return -EFAULT;
554
555 real_gfn = gpa_to_gfn(real_gfn);
556
54bf36aa 557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 558}
559EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
560
69b0049a 561static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 562 void *data, int offset, int len, u32 access)
563{
564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
565 data, offset, len, access);
566}
567
a03490ed
CO		 568/*
569 * Load the pae pdptrs. Return true is they are all valid.
570 */
ff03a073 571int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 572{
573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
575 int i;
576 int ret;
ff03a073 577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 578
ff03a073
JR		 579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
580 offset * sizeof(u64), sizeof(pdpte),
581 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 582 if (ret < 0) {
583 ret = 0;
584 goto out;
585 }
586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 587 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 588 (pdpte[i] &
589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 590 ret = 0;
591 goto out;
592 }
593 }
594 ret = 1;
595
ff03a073 596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 597 __set_bit(VCPU_EXREG_PDPTR,
598 (unsigned long *)&vcpu->arch.regs_avail);
599 __set_bit(VCPU_EXREG_PDPTR,
600 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 601out:
a03490ed
CO		 602
603 return ret;
604}
cc4b6871 605EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 606
9ed38ffa 607bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 608{
ff03a073 609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 610 bool changed = true;
3d06b8bf
JR		 611 int offset;
612 gfn_t gfn;
d835dfec
AK		 613 int r;
614
615 if (is_long_mode(vcpu) || !is_pae(vcpu))
616 return false;
617
6de4f3ad
AK		 618 if (!test_bit(VCPU_EXREG_PDPTR,
619 (unsigned long *)&vcpu->arch.regs_avail))
620 return true;
621
a512177e
PB		 622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
625 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 626 if (r < 0)
627 goto out;
ff03a073 628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 629out:
d835dfec
AK		 630
631 return changed;
632}
9ed38ffa 633EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 634
49a9b07e 635int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 636{
aad82703 637 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 639
f9a48e6a
AK		 640 cr0 |= X86_CR0_ET;
641
ab344828 642#ifdef CONFIG_X86_64
0f12244f
GN		 643 if (cr0 & 0xffffffff00000000UL)
644 return 1;
ab344828
GN		 645#endif
646
647 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
650 return 1;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
653 return 1;
a03490ed
CO		 654
655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
656#ifdef CONFIG_X86_64
f6801dff 657 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 658 int cs_db, cs_l;
659
0f12244f
GN		 660 if (!is_pae(vcpu))
661 return 1;
a03490ed 662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 663 if (cs_l)
664 return 1;
a03490ed
CO		 665 } else
666#endif
ff03a073 667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 668 kvm_read_cr3(vcpu)))
0f12244f 669 return 1;
a03490ed
CO		 670 }
671
ad756a16
MJ		 672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
673 return 1;
674
a03490ed 675 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 676
d170c419 677 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 678 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 679 kvm_async_pf_hash_reset(vcpu);
680 }
e5f3f027 681
aad82703
SY		 682 if ((cr0 ^ old_cr0) & update_bits)
683 kvm_mmu_reset_context(vcpu);
b18d5431 684
879ae188
LE		 685 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
686 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
689
0f12244f
GN		 690 return 0;
691}
2d3ad1f4 692EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 693
2d3ad1f4 694void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 695{
49a9b07e 696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 697}
2d3ad1f4 698EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 699
42bdf991
MT		 700static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
701{
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
703 !vcpu->guest_xcr0_loaded) {
704 /* kvm_set_xcr() also depends on this */
705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
706 vcpu->guest_xcr0_loaded = 1;
707 }
708}
709
710static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (vcpu->guest_xcr0_loaded) {
713 if (vcpu->arch.xcr0 != host_xcr0)
714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
715 vcpu->guest_xcr0_loaded = 0;
716 }
717}
718
69b0049a 719static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 720{
56c103ec
LJ		 721 u64 xcr0 = xcr;
722 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 723 u64 valid_bits;
2acf923e
DC		 724
725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
726 if (index != XCR_XFEATURE_ENABLED_MASK)
727 return 1;
d91cab78 728 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 729 return 1;
d91cab78 730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 731 return 1;
46c34cb0
PB		 732
733 /*
734 * Do not allow the guest to set bits that we do not support
735 * saving. However, xcr0 bit 0 is always set, even if the
736 * emulated CPU does not support XSAVE (see fx_init).
737 */
d91cab78 738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 739 if (xcr0 & ~valid_bits)
2acf923e 740 return 1;
46c34cb0 741
d91cab78
DH		 742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
743 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 744 return 1;
745
d91cab78
DH		 746 if (xcr0 & XFEATURE_MASK_AVX512) {
747 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 748 return 1;
d91cab78 749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 750 return 1;
751 }
2acf923e 752 vcpu->arch.xcr0 = xcr0;
56c103ec 753
d91cab78 754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 755 kvm_update_cpuid(vcpu);
2acf923e
DC		 756 return 0;
757}
758
759int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
760{
764bcbc5
Z		 761 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
762 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 763 kvm_inject_gp(vcpu, 0);
764 return 1;
765 }
766 return 0;
767}
768EXPORT_SYMBOL_GPL(kvm_set_xcr);
769
a83b29c6 770int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 771{
fc78f519 772 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 775
0f12244f
GN		 776 if (cr4 & CR4_RESERVED_BITS)
777 return 1;
a03490ed 778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 789 return 1;
790
d6321d49 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 792 return 1;
793
fd8cb433 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 795 return 1;
796
ae3e61e1
PB		 797 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
798 return 1;
799
a03490ed 800 if (is_long_mode(vcpu)) {
0f12244f
GN		 801 if (!(cr4 & X86_CR4_PAE))
802 return 1;
a2edf57f
AK		 803 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
804 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 805 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
806 kvm_read_cr3(vcpu)))
0f12244f
GN		 807 return 1;
808
ad756a16 809 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 810 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 811 return 1;
812
813 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
814 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
815 return 1;
816 }
817
5e1746d6 818 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 819 return 1;
a03490ed 820
ad756a16
MJ		 821 if (((cr4 ^ old_cr4) & pdptr_bits) ||
822 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 823 kvm_mmu_reset_context(vcpu);
0f12244f 824
b9baba86 825 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 826 kvm_update_cpuid(vcpu);
2acf923e 827
0f12244f
GN		 828 return 0;
829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 831
2390218b 832int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 833{
ac146235 834#ifdef CONFIG_X86_64
9d88fca7 835 cr3 &= ~CR3_PCID_INVD;
ac146235 836#endif
9d88fca7 837
9f8fe504 838 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 839 kvm_mmu_sync_roots(vcpu);
77c3913b 840 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 841 return 0;
d835dfec
AK		 842 }
843
d1cd3ce9
YZ		 844 if (is_long_mode(vcpu) &&
845 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
846 return 1;
847 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 848 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 849 return 1;
a03490ed 850
0f12244f 851 vcpu->arch.cr3 = cr3;
aff48baa 852 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 853 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 854 return 0;
855}
2d3ad1f4 856EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 857
eea1cff9 858int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 859{
0f12244f
GN		 860 if (cr8 & CR8_RESERVED_BITS)
861 return 1;
35754c98 862 if (lapic_in_kernel(vcpu))
a03490ed
CO		 863 kvm_lapic_set_tpr(vcpu, cr8);
864 else
ad312c7c 865 vcpu->arch.cr8 = cr8;
0f12244f
GN		 866 return 0;
867}
2d3ad1f4 868EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 869
2d3ad1f4 870unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 871{
35754c98 872 if (lapic_in_kernel(vcpu))
a03490ed
CO		 873 return kvm_lapic_get_cr8(vcpu);
874 else
ad312c7c 875 return vcpu->arch.cr8;
a03490ed 876}
2d3ad1f4 877EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 878
ae561ede
NA		 879static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
880{
881 int i;
882
883 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
884 for (i = 0; i < KVM_NR_DB_REGS; i++)
885 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
886 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
887 }
888}
889
73aaf249
JK		 890static void kvm_update_dr6(struct kvm_vcpu *vcpu)
891{
892 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
893 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
894}
895
c8639010
JK		 896static void kvm_update_dr7(struct kvm_vcpu *vcpu)
897{
898 unsigned long dr7;
899
900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
901 dr7 = vcpu->arch.guest_debug_dr7;
902 else
903 dr7 = vcpu->arch.dr7;
904 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 905 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
906 if (dr7 & DR7_BP_EN_MASK)
907 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 908}
909
6f43ed01
NA		 910static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
911{
912 u64 fixed = DR6_FIXED_1;
913
d6321d49 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 915 fixed |= DR6_RTM;
916 return fixed;
917}
918
338dbc97 919static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 920{
921 switch (dr) {
922 case 0 ... 3:
923 vcpu->arch.db[dr] = val;
924 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
925 vcpu->arch.eff_db[dr] = val;
926 break;
927 case 4:
020df079
GN		 928 /* fall through */
929 case 6:
338dbc97
GN		 930 if (val & 0xffffffff00000000ULL)
931 return -1; /* #GP */
6f43ed01 932 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 933 kvm_update_dr6(vcpu);
020df079
GN		 934 break;
935 case 5:
020df079
GN		 936 /* fall through */
937 default: /* 7 */
338dbc97
GN		 938 if (val & 0xffffffff00000000ULL)
939 return -1; /* #GP */
020df079 940 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 941 kvm_update_dr7(vcpu);
020df079
GN		 942 break;
943 }
944
945 return 0;
946}
338dbc97
GN		 947
948int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
949{
16f8a6f9 950 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 951 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 952 return 1;
953 }
954 return 0;
338dbc97 955}
020df079
GN		 956EXPORT_SYMBOL_GPL(kvm_set_dr);
957
16f8a6f9 958int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 959{
960 switch (dr) {
961 case 0 ... 3:
962 *val = vcpu->arch.db[dr];
963 break;
964 case 4:
020df079
GN		 965 /* fall through */
966 case 6:
73aaf249
JK		 967 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
968 *val = vcpu->arch.dr6;
969 else
970 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 971 break;
972 case 5:
020df079
GN		 973 /* fall through */
974 default: /* 7 */
975 *val = vcpu->arch.dr7;
976 break;
977 }
338dbc97
GN		 978 return 0;
979}
020df079
GN		 980EXPORT_SYMBOL_GPL(kvm_get_dr);
981
022cd0e8
AK		 982bool kvm_rdpmc(struct kvm_vcpu *vcpu)
983{
984 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
985 u64 data;
986 int err;
987
c6702c9d 988 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 989 if (err)
990 return err;
991 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
992 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
993 return err;
994}
995EXPORT_SYMBOL_GPL(kvm_rdpmc);
996
043405e1
CO		 997/*
998 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
999 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1000 *
1001 * This list is modified at module load time to reflect the
e3267cbb 1002 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1003 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1004 * may depend on host virtualization features rather than host cpu features.
043405e1 1005 */
e3267cbb 1006
043405e1
CO		 1007static u32 msrs_to_save[] = {
1008 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1009 MSR_STAR,
043405e1
CO		 1010#ifdef CONFIG_X86_64
1011 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1012#endif
b3897a49 1013 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1014 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1015};
1016
1017static unsigned num_msrs_to_save;
1018
62ef68bb
PB		 1019static u32 emulated_msrs[] = {
1020 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1021 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1022 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1023 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1024 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1025 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1026 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1027 HV_X64_MSR_RESET,
11c4b1ca 1028 HV_X64_MSR_VP_INDEX,
9eec50b8 1029 HV_X64_MSR_VP_RUNTIME,
5c919412 1030 HV_X64_MSR_SCONTROL,
1f4b34f8 1031 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1032 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1033 MSR_KVM_PV_EOI_EN,
1034
ba904635 1035 MSR_IA32_TSC_ADJUST,
a3e06bbe 1036 MSR_IA32_TSCDEADLINE,
043405e1 1037 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1038 MSR_IA32_MCG_STATUS,
1039 MSR_IA32_MCG_CTL,
c45dcc71 1040 MSR_IA32_MCG_EXT_CTL,
64d60670 1041 MSR_IA32_SMBASE,
52797bf9 1042 MSR_SMI_COUNT,
db2336a8
KH		 1043 MSR_PLATFORM_INFO,
1044 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1045};
1046
62ef68bb
PB		 1047static unsigned num_emulated_msrs;
1048
384bb783 1049bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1050{
b69e8cae 1051 if (efer & efer_reserved_bits)
384bb783 1052 return false;
15c4a640 1053
1b4d56b8 1054 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1055 return false;
1b2fd70c 1056
1b4d56b8 1057 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1058 return false;
d8017474 1059
384bb783
JK		 1060 return true;
1061}
1062EXPORT_SYMBOL_GPL(kvm_valid_efer);
1063
1064static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1065{
1066 u64 old_efer = vcpu->arch.efer;
1067
1068 if (!kvm_valid_efer(vcpu, efer))
1069 return 1;
1070
1071 if (is_paging(vcpu)
1072 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1073 return 1;
1074
15c4a640 1075 efer &= ~EFER_LMA;
f6801dff 1076 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1077
a3d204e2
SY		 1078 kvm_x86_ops->set_efer(vcpu, efer);
1079
aad82703
SY		 1080 /* Update reserved bits */
1081 if ((efer ^ old_efer) & EFER_NX)
1082 kvm_mmu_reset_context(vcpu);
1083
b69e8cae 1084 return 0;
15c4a640
CO		 1085}
1086
f2b4b7dd
JR		 1087void kvm_enable_efer_bits(u64 mask)
1088{
1089 efer_reserved_bits &= ~mask;
1090}
1091EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1092
15c4a640
CO		 1093/*
1094 * Writes msr value into into the appropriate "register".
1095 * Returns 0 on success, non-0 otherwise.
1096 * Assumes vcpu_load() was already called.
1097 */
8fe8ab46 1098int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1099{
854e8bb1
NA		 1100 switch (msr->index) {
1101 case MSR_FS_BASE:
1102 case MSR_GS_BASE:
1103 case MSR_KERNEL_GS_BASE:
1104 case MSR_CSTAR:
1105 case MSR_LSTAR:
fd8cb433 1106 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1107 return 1;
1108 break;
1109 case MSR_IA32_SYSENTER_EIP:
1110 case MSR_IA32_SYSENTER_ESP:
1111 /*
1112 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1113 * non-canonical address is written on Intel but not on
1114 * AMD (which ignores the top 32-bits, because it does
1115 * not implement 64-bit SYSENTER).
1116 *
1117 * 64-bit code should hence be able to write a non-canonical
1118 * value on AMD. Making the address canonical ensures that
1119 * vmentry does not fail on Intel after writing a non-canonical
1120 * value, and that something deterministic happens if the guest
1121 * invokes 64-bit SYSENTER.
1122 */
fd8cb433 1123 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1124 }
8fe8ab46 1125 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1126}
854e8bb1 1127EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1128
313a3dc7
CO		 1129/*
1130 * Adapt set_msr() to msr_io()'s calling convention
1131 */
609e36d3
PB		 1132static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1133{
1134 struct msr_data msr;
1135 int r;
1136
1137 msr.index = index;
1138 msr.host_initiated = true;
1139 r = kvm_get_msr(vcpu, &msr);
1140 if (r)
1141 return r;
1142
1143 *data = msr.data;
1144 return 0;
1145}
1146
313a3dc7
CO		 1147static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1148{
8fe8ab46
WA		 1149 struct msr_data msr;
1150
1151 msr.data = *data;
1152 msr.index = index;
1153 msr.host_initiated = true;
1154 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1155}
1156
16e8d74d
MT		 1157#ifdef CONFIG_X86_64
1158struct pvclock_gtod_data {
1159 seqcount_t seq;
1160
1161 struct { /* extract of a clocksource struct */
1162 int vclock_mode;
a5a1d1c2
TG		 1163 u64 cycle_last;
1164 u64 mask;
16e8d74d
MT		 1165 u32 mult;
1166 u32 shift;
1167 } clock;
1168
cbcf2dd3
TG		 1169 u64 boot_ns;
1170 u64 nsec_base;
55dd00a7 1171 u64 wall_time_sec;
16e8d74d
MT		 1172};
1173
1174static struct pvclock_gtod_data pvclock_gtod_data;
1175
1176static void update_pvclock_gtod(struct timekeeper *tk)
1177{
1178 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1179 u64 boot_ns;
1180
876e7881 1181 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1182
1183 write_seqcount_begin(&vdata->seq);
1184
1185 /* copy pvclock gtod data */
876e7881
PZ		 1186 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1187 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1188 vdata->clock.mask = tk->tkr_mono.mask;
1189 vdata->clock.mult = tk->tkr_mono.mult;
1190 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1191
cbcf2dd3 1192 vdata->boot_ns = boot_ns;
876e7881 1193 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1194
55dd00a7
MT		 1195 vdata->wall_time_sec = tk->xtime_sec;
1196
16e8d74d
MT		 1197 write_seqcount_end(&vdata->seq);
1198}
1199#endif
1200
bab5bb39
NK		 1201void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1202{
1203 /*
1204 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1205 * vcpu_enter_guest. This function is only called from
1206 * the physical CPU that is running vcpu.
1207 */
1208 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1209}
16e8d74d 1210
18068523
GOC		 1211static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1212{
9ed3c444
AK		 1213 int version;
1214 int r;
50d0a0f9 1215 struct pvclock_wall_clock wc;
87aeb54f 1216 struct timespec64 boot;
18068523
GOC		 1217
1218 if (!wall_clock)
1219 return;
1220
9ed3c444
AK		 1221 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1222 if (r)
1223 return;
1224
1225 if (version & 1)
1226 ++version; /* first time write, random junk */
1227
1228 ++version;
18068523 1229
1dab1345
NK		 1230 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1231 return;
18068523 1232
50d0a0f9
GH		 1233 /*
1234 * The guest calculates current wall clock time by adding
34c238a1 1235 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1236 * wall clock specified here. guest system time equals host
1237 * system time for us, thus we must fill in host boot time here.
1238 */
87aeb54f 1239 getboottime64(&boot);
50d0a0f9 1240
4b648665 1241 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1242 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1243 boot = timespec64_sub(boot, ts);
4b648665 1244 }
87aeb54f 1245 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1246 wc.nsec = boot.tv_nsec;
1247 wc.version = version;
18068523
GOC		 1248
1249 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1250
1251 version++;
1252 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1253}
1254
50d0a0f9
GH		 1255static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1256{
b51012de
PB		 1257 do_shl32_div32(dividend, divisor);
1258 return dividend;
50d0a0f9
GH		 1259}
1260
3ae13faa 1261static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1262 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1263{
5f4e3f88 1264 uint64_t scaled64;
50d0a0f9
GH		 1265 int32_t shift = 0;
1266 uint64_t tps64;
1267 uint32_t tps32;
1268
3ae13faa
PB		 1269 tps64 = base_hz;
1270 scaled64 = scaled_hz;
50933623 1271 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1272 tps64 >>= 1;
1273 shift--;
1274 }
1275
1276 tps32 = (uint32_t)tps64;
50933623
JK		 1277 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1278 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1279 scaled64 >>= 1;
1280 else
1281 tps32 <<= 1;
50d0a0f9
GH		 1282 shift++;
1283 }
1284
5f4e3f88
ZA		 1285 *pshift = shift;
1286 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1287
3ae13faa
PB		 1288 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1289 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1290}
1291
d828199e 1292#ifdef CONFIG_X86_64
16e8d74d 1293static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1294#endif
16e8d74d 1295
c8076604 1296static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1297static unsigned long max_tsc_khz;
c8076604 1298
cc578287 1299static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1300{
cc578287
ZA		 1301 u64 v = (u64)khz * (1000000 + ppm);
1302 do_div(v, 1000000);
1303 return v;
1e993611
JR		 1304}
1305
381d585c
HZ		 1306static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1307{
1308 u64 ratio;
1309
1310 /* Guest TSC same frequency as host TSC? */
1311 if (!scale) {
1312 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1313 return 0;
1314 }
1315
1316 /* TSC scaling supported? */
1317 if (!kvm_has_tsc_control) {
1318 if (user_tsc_khz > tsc_khz) {
1319 vcpu->arch.tsc_catchup = 1;
1320 vcpu->arch.tsc_always_catchup = 1;
1321 return 0;
1322 } else {
1323 WARN(1, "user requested TSC rate below hardware speed\n");
1324 return -1;
1325 }
1326 }
1327
1328 /* TSC scaling required - calculate ratio */
1329 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1330 user_tsc_khz, tsc_khz);
1331
1332 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1333 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1334 user_tsc_khz);
1335 return -1;
1336 }
1337
1338 vcpu->arch.tsc_scaling_ratio = ratio;
1339 return 0;
1340}
1341
4941b8cb 1342static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1343{
cc578287
ZA		 1344 u32 thresh_lo, thresh_hi;
1345 int use_scaling = 0;
217fc9cf 1346
03ba32ca 1347 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1348 if (user_tsc_khz == 0) {
ad721883
HZ		 1349 /* set tsc_scaling_ratio to a safe value */
1350 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1351 return -1;
ad721883 1352 }
03ba32ca 1353
c285545f 1354 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1355 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1356 &vcpu->arch.virtual_tsc_shift,
1357 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1358 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1359
1360 /*
1361 * Compute the variation in TSC rate which is acceptable
1362 * within the range of tolerance and decide if the
1363 * rate being applied is within that bounds of the hardware
1364 * rate. If so, no scaling or compensation need be done.
1365 */
1366 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1367 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1368 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1369 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1370 use_scaling = 1;
1371 }
4941b8cb 1372 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1373}
1374
1375static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1376{
e26101b1 1377 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1378 vcpu->arch.virtual_tsc_mult,
1379 vcpu->arch.virtual_tsc_shift);
e26101b1 1380 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1381 return tsc;
1382}
1383
69b0049a 1384static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1385{
1386#ifdef CONFIG_X86_64
1387 bool vcpus_matched;
b48aa97e
MT		 1388 struct kvm_arch *ka = &vcpu->kvm->arch;
1389 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1390
1391 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1392 atomic_read(&vcpu->kvm->online_vcpus));
1393
7f187922
MT		 1394 /*
1395 * Once the masterclock is enabled, always perform request in
1396 * order to update it.
1397 *
1398 * In order to enable masterclock, the host clocksource must be TSC
1399 * and the vcpus need to have matched TSCs. When that happens,
1400 * perform request to enable masterclock.
1401 */
1402 if (ka->use_master_clock ||
1403 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1404 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1405
1406 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1407 atomic_read(&vcpu->kvm->online_vcpus),
1408 ka->use_master_clock, gtod->clock.vclock_mode);
1409#endif
1410}
1411
ba904635
WA		 1412static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1413{
3e3f5026 1414 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1415 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1416}
1417
35181e86
HZ		 1418/*
1419 * Multiply tsc by a fixed point number represented by ratio.
1420 *
1421 * The most significant 64-N bits (mult) of ratio represent the
1422 * integral part of the fixed point number; the remaining N bits
1423 * (frac) represent the fractional part, ie. ratio represents a fixed
1424 * point number (mult + frac * 2^(-N)).
1425 *
1426 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1427 */
1428static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1429{
1430 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1431}
1432
1433u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1434{
1435 u64 _tsc = tsc;
1436 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1437
1438 if (ratio != kvm_default_tsc_scaling_ratio)
1439 _tsc = __scale_tsc(ratio, tsc);
1440
1441 return _tsc;
1442}
1443EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1444
07c1419a
HZ		 1445static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1446{
1447 u64 tsc;
1448
1449 tsc = kvm_scale_tsc(vcpu, rdtsc());
1450
1451 return target_tsc - tsc;
1452}
1453
4ba76538
HZ		 1454u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1455{
ea26e4ec 1456 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1457}
1458EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1459
a545ab6a
LC		 1460static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1461{
1462 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1463 vcpu->arch.tsc_offset = offset;
1464}
1465
8fe8ab46 1466void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1467{
1468 struct kvm *kvm = vcpu->kvm;
f38e098f 1469 u64 offset, ns, elapsed;
99e3e30a 1470 unsigned long flags;
b48aa97e 1471 bool matched;
0d3da0d2 1472 bool already_matched;
8fe8ab46 1473 u64 data = msr->data;
c5e8ec8e 1474 bool synchronizing = false;
99e3e30a 1475
038f8c11 1476 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1477 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1478 ns = ktime_get_boot_ns();
f38e098f 1479 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1480
03ba32ca 1481 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1482 if (data == 0 && msr->host_initiated) {
1483 /*
1484 * detection of vcpu initialization -- need to sync
1485 * with other vCPUs. This particularly helps to keep
1486 * kvm_clock stable after CPU hotplug
1487 */
1488 synchronizing = true;
1489 } else {
1490 u64 tsc_exp = kvm->arch.last_tsc_write +
1491 nsec_to_cycles(vcpu, elapsed);
1492 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1493 /*
1494 * Special case: TSC write with a small delta (1 second)
1495 * of virtual cycle time against real time is
1496 * interpreted as an attempt to synchronize the CPU.
1497 */
1498 synchronizing = data < tsc_exp + tsc_hz &&
1499 data + tsc_hz > tsc_exp;
1500 }
c5e8ec8e 1501 }
f38e098f
ZA		 1502
1503 /*
5d3cb0f6
ZA		 1504 * For a reliable TSC, we can match TSC offsets, and for an unstable
1505 * TSC, we add elapsed time in this computation. We could let the
1506 * compensation code attempt to catch up if we fall behind, but
1507 * it's better to try to match offsets from the beginning.
1508 */
c5e8ec8e 1509 if (synchronizing &&
5d3cb0f6 1510 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1511 if (!check_tsc_unstable()) {
e26101b1 1512 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1513 pr_debug("kvm: matched tsc offset for %llu\n", data);
1514 } else {
857e4099 1515 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1516 data += delta;
07c1419a 1517 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1518 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1519 }
b48aa97e 1520 matched = true;
0d3da0d2 1521 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1522 } else {
1523 /*
1524 * We split periods of matched TSC writes into generations.
1525 * For each generation, we track the original measured
1526 * nanosecond time, offset, and write, so if TSCs are in
1527 * sync, we can match exact offset, and if not, we can match
4a969980 1528 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1529 *
1530 * These values are tracked in kvm->arch.cur_xxx variables.
1531 */
1532 kvm->arch.cur_tsc_generation++;
1533 kvm->arch.cur_tsc_nsec = ns;
1534 kvm->arch.cur_tsc_write = data;
1535 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1536 matched = false;
0d3da0d2 1537 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1538 kvm->arch.cur_tsc_generation, data);
f38e098f 1539 }
e26101b1
ZA		 1540
1541 /*
1542 * We also track th most recent recorded KHZ, write and time to
1543 * allow the matching interval to be extended at each write.
1544 */
f38e098f
ZA		 1545 kvm->arch.last_tsc_nsec = ns;
1546 kvm->arch.last_tsc_write = data;
5d3cb0f6 1547 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1548
b183aa58 1549 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1550
1551 /* Keep track of which generation this VCPU has synchronized to */
1552 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1553 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1554 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1555
d6321d49 1556 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1557 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1558
a545ab6a 1559 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1560 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1561
1562 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1563 if (!matched) {
b48aa97e 1564 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1565 } else if (!already_matched) {
1566 kvm->arch.nr_vcpus_matched_tsc++;
1567 }
b48aa97e
MT		 1568
1569 kvm_track_tsc_matching(vcpu);
1570 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1571}
e26101b1 1572
99e3e30a
ZA		 1573EXPORT_SYMBOL_GPL(kvm_write_tsc);
1574
58ea6767
HZ		 1575static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1576 s64 adjustment)
1577{
ea26e4ec 1578 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1579}
1580
1581static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1582{
1583 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1584 WARN_ON(adjustment < 0);
1585 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1586 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1587}
1588
d828199e
MT		 1589#ifdef CONFIG_X86_64
1590
a5a1d1c2 1591static u64 read_tsc(void)
d828199e 1592{
a5a1d1c2 1593 u64 ret = (u64)rdtsc_ordered();
03b9730b 1594 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1595
1596 if (likely(ret >= last))
1597 return ret;
1598
1599 /*
1600 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1601 * predictable (it's just a function of time and the likely is
d828199e
MT		 1602 * very likely) and there's a data dependence, so force GCC
1603 * to generate a branch instead. I don't barrier() because
1604 * we don't actually need a barrier, and if this function
1605 * ever gets inlined it will generate worse code.
1606 */
1607 asm volatile ("");
1608 return last;
1609}
1610
a5a1d1c2 1611static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1612{
1613 long v;
1614 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1615
1616 *cycle_now = read_tsc();
1617
1618 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1619 return v * gtod->clock.mult;
1620}
1621
a5a1d1c2 1622static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1623{
cbcf2dd3 1624 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1625 unsigned long seq;
d828199e 1626 int mode;
cbcf2dd3 1627 u64 ns;
d828199e 1628
d828199e
MT		 1629 do {
1630 seq = read_seqcount_begin(&gtod->seq);
1631 mode = gtod->clock.vclock_mode;
cbcf2dd3 1632 ns = gtod->nsec_base;
d828199e
MT		 1633 ns += vgettsc(cycle_now);
1634 ns >>= gtod->clock.shift;
cbcf2dd3 1635 ns += gtod->boot_ns;
d828199e 1636 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1637 *t = ns;
d828199e
MT		 1638
1639 return mode;
1640}
1641
55dd00a7
MT		 1642static int do_realtime(struct timespec *ts, u64 *cycle_now)
1643{
1644 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1645 unsigned long seq;
1646 int mode;
1647 u64 ns;
1648
1649 do {
1650 seq = read_seqcount_begin(&gtod->seq);
1651 mode = gtod->clock.vclock_mode;
1652 ts->tv_sec = gtod->wall_time_sec;
1653 ns = gtod->nsec_base;
1654 ns += vgettsc(cycle_now);
1655 ns >>= gtod->clock.shift;
1656 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1657
1658 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1659 ts->tv_nsec = ns;
1660
1661 return mode;
1662}
1663
d828199e 1664/* returns true if host is using tsc clocksource */
a5a1d1c2 1665static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1666{
d828199e
MT		 1667 /* checked again under seqlock below */
1668 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1669 return false;
1670
cbcf2dd3 1671 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1672}
55dd00a7
MT		 1673
1674/* returns true if host is using tsc clocksource */
1675static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1676 u64 *cycle_now)
1677{
1678 /* checked again under seqlock below */
1679 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1680 return false;
1681
1682 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1683}
d828199e
MT		 1684#endif
1685
1686/*
1687 *
b48aa97e
MT		 1688 * Assuming a stable TSC across physical CPUS, and a stable TSC
1689 * across virtual CPUs, the following condition is possible.
1690 * Each numbered line represents an event visible to both
d828199e
MT		 1691 * CPUs at the next numbered event.
1692 *
1693 * "timespecX" represents host monotonic time. "tscX" represents
1694 * RDTSC value.
1695 *
1696 * VCPU0 on CPU0 | VCPU1 on CPU1
1697 *
1698 * 1. read timespec0,tsc0
1699 * 2. | timespec1 = timespec0 + N
1700 * | tsc1 = tsc0 + M
1701 * 3. transition to guest | transition to guest
1702 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1703 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1704 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1705 *
1706 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1707 *
1708 * - ret0 < ret1
1709 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1710 * ...
1711 * - 0 < N - M => M < N
1712 *
1713 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1714 * always the case (the difference between two distinct xtime instances
1715 * might be smaller then the difference between corresponding TSC reads,
1716 * when updating guest vcpus pvclock areas).
1717 *
1718 * To avoid that problem, do not allow visibility of distinct
1719 * system_timestamp/tsc_timestamp values simultaneously: use a master
1720 * copy of host monotonic time values. Update that master copy
1721 * in lockstep.
1722 *
b48aa97e 1723 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1724 *
1725 */
1726
1727static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1728{
1729#ifdef CONFIG_X86_64
1730 struct kvm_arch *ka = &kvm->arch;
1731 int vclock_mode;
b48aa97e
MT		 1732 bool host_tsc_clocksource, vcpus_matched;
1733
1734 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1735 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1736
1737 /*
1738 * If the host uses TSC clock, then passthrough TSC as stable
1739 * to the guest.
1740 */
b48aa97e 1741 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1742 &ka->master_kernel_ns,
1743 &ka->master_cycle_now);
1744
16a96021 1745 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1746 && !ka->backwards_tsc_observed
54750f2c 1747 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1748
d828199e
MT		 1749 if (ka->use_master_clock)
1750 atomic_set(&kvm_guest_has_master_clock, 1);
1751
1752 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1753 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1754 vcpus_matched);
d828199e
MT		 1755#endif
1756}
1757
2860c4b1
PB		 1758void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1759{
1760 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1761}
1762
2e762ff7
MT		 1763static void kvm_gen_update_masterclock(struct kvm *kvm)
1764{
1765#ifdef CONFIG_X86_64
1766 int i;
1767 struct kvm_vcpu *vcpu;
1768 struct kvm_arch *ka = &kvm->arch;
1769
1770 spin_lock(&ka->pvclock_gtod_sync_lock);
1771 kvm_make_mclock_inprogress_request(kvm);
1772 /* no guest entries from this point */
1773 pvclock_update_vm_gtod_copy(kvm);
1774
1775 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1776 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1777
1778 /* guest entries allowed */
1779 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1780 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1781
1782 spin_unlock(&ka->pvclock_gtod_sync_lock);
1783#endif
1784}
1785
e891a32e 1786u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1787{
108b249c 1788 struct kvm_arch *ka = &kvm->arch;
8b953440 1789 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1790 u64 ret;
108b249c 1791
8b953440
PB		 1792 spin_lock(&ka->pvclock_gtod_sync_lock);
1793 if (!ka->use_master_clock) {
1794 spin_unlock(&ka->pvclock_gtod_sync_lock);
1795 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1796 }
1797
8b953440
PB		 1798 hv_clock.tsc_timestamp = ka->master_cycle_now;
1799 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1800 spin_unlock(&ka->pvclock_gtod_sync_lock);
1801
e2c2206a
WL		 1802 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1803 get_cpu();
1804
e70b57a6
WL		 1805 if (__this_cpu_read(cpu_tsc_khz)) {
1806 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1807 &hv_clock.tsc_shift,
1808 &hv_clock.tsc_to_system_mul);
1809 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1810 } else
1811 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1812
1813 put_cpu();
1814
1815 return ret;
108b249c
PB		 1816}
1817
0d6dd2ff
PB		 1818static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1819{
1820 struct kvm_vcpu_arch *vcpu = &v->arch;
1821 struct pvclock_vcpu_time_info guest_hv_clock;
1822
4e335d9e 1823 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1824 &guest_hv_clock, sizeof(guest_hv_clock))))
1825 return;
1826
1827 /* This VCPU is paused, but it's legal for a guest to read another
1828 * VCPU's kvmclock, so we really have to follow the specification where
1829 * it says that version is odd if data is being modified, and even after
1830 * it is consistent.
1831 *
1832 * Version field updates must be kept separate. This is because
1833 * kvm_write_guest_cached might use a "rep movs" instruction, and
1834 * writes within a string instruction are weakly ordered. So there
1835 * are three writes overall.
1836 *
1837 * As a small optimization, only write the version field in the first
1838 * and third write. The vcpu->pv_time cache is still valid, because the
1839 * version field is the first in the struct.
1840 */
1841 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1842
51c4b8bb
LA		 1843 if (guest_hv_clock.version & 1)
1844 ++guest_hv_clock.version; /* first time write, random junk */
1845
0d6dd2ff 1846 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1847 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1848 &vcpu->hv_clock,
1849 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1850
1851 smp_wmb();
1852
1853 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1854 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1855
1856 if (vcpu->pvclock_set_guest_stopped_request) {
1857 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1858 vcpu->pvclock_set_guest_stopped_request = false;
1859 }
1860
1861 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1862
4e335d9e
PB		 1863 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1864 &vcpu->hv_clock,
1865 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1866
1867 smp_wmb();
1868
1869 vcpu->hv_clock.version++;
4e335d9e
PB		 1870 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1871 &vcpu->hv_clock,
1872 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1873}
1874
34c238a1 1875static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1876{
78db6a50 1877 unsigned long flags, tgt_tsc_khz;
18068523 1878 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1879 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1880 s64 kernel_ns;
d828199e 1881 u64 tsc_timestamp, host_tsc;
51d59c6b 1882 u8 pvclock_flags;
d828199e
MT		 1883 bool use_master_clock;
1884
1885 kernel_ns = 0;
1886 host_tsc = 0;
18068523 1887
d828199e
MT		 1888 /*
1889 * If the host uses TSC clock, then passthrough TSC as stable
1890 * to the guest.
1891 */
1892 spin_lock(&ka->pvclock_gtod_sync_lock);
1893 use_master_clock = ka->use_master_clock;
1894 if (use_master_clock) {
1895 host_tsc = ka->master_cycle_now;
1896 kernel_ns = ka->master_kernel_ns;
1897 }
1898 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1899
1900 /* Keep irq disabled to prevent changes to the clock */
1901 local_irq_save(flags);
78db6a50
PB		 1902 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1903 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1904 local_irq_restore(flags);
1905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1906 return 1;
1907 }
d828199e 1908 if (!use_master_clock) {
4ea1636b 1909 host_tsc = rdtsc();
108b249c 1910 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1911 }
1912
4ba76538 1913 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1914
c285545f
ZA		 1915 /*
1916 * We may have to catch up the TSC to match elapsed wall clock
1917 * time for two reasons, even if kvmclock is used.
1918 * 1) CPU could have been running below the maximum TSC rate
1919 * 2) Broken TSC compensation resets the base at each VCPU
1920 * entry to avoid unknown leaps of TSC even when running
1921 * again on the same CPU. This may cause apparent elapsed
1922 * time to disappear, and the guest to stand still or run
1923 * very slowly.
1924 */
1925 if (vcpu->tsc_catchup) {
1926 u64 tsc = compute_guest_tsc(v, kernel_ns);
1927 if (tsc > tsc_timestamp) {
f1e2b260 1928 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1929 tsc_timestamp = tsc;
1930 }
50d0a0f9
GH		 1931 }
1932
18068523
GOC		 1933 local_irq_restore(flags);
1934
0d6dd2ff 1935 /* With all the info we got, fill in the values */
18068523 1936
78db6a50
PB		 1937 if (kvm_has_tsc_control)
1938 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1939
1940 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1941 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1942 &vcpu->hv_clock.tsc_shift,
1943 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1944 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1945 }
1946
1d5f066e 1947 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1948 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1949 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1950
d828199e 1951 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1952 pvclock_flags = 0;
d828199e
MT		 1953 if (use_master_clock)
1954 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1955
78c0337a
MT		 1956 vcpu->hv_clock.flags = pvclock_flags;
1957
095cf55d
PB		 1958 if (vcpu->pv_time_enabled)
1959 kvm_setup_pvclock_page(v);
1960 if (v == kvm_get_vcpu(v->kvm, 0))
1961 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1962 return 0;
c8076604
GH		 1963}
1964
0061d53d
MT		 1965/*
1966 * kvmclock updates which are isolated to a given vcpu, such as
1967 * vcpu->cpu migration, should not allow system_timestamp from
1968 * the rest of the vcpus to remain static. Otherwise ntp frequency
1969 * correction applies to one vcpu's system_timestamp but not
1970 * the others.
1971 *
1972 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1973 * We need to rate-limit these requests though, as they can
1974 * considerably slow guests that have a large number of vcpus.
1975 * The time for a remote vcpu to update its kvmclock is bound
1976 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1977 */
1978
7e44e449
AJ		 1979#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1980
1981static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1982{
1983 int i;
7e44e449
AJ		 1984 struct delayed_work *dwork = to_delayed_work(work);
1985 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1986 kvmclock_update_work);
1987 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1988 struct kvm_vcpu *vcpu;
1989
1990 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1991 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1992 kvm_vcpu_kick(vcpu);
1993 }
1994}
1995
7e44e449
AJ		 1996static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1997{
1998 struct kvm *kvm = v->kvm;
1999
105b21bb 2000 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2001 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2002 KVMCLOCK_UPDATE_DELAY);
2003}
2004
332967a3
AJ		 2005#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2006
2007static void kvmclock_sync_fn(struct work_struct *work)
2008{
2009 struct delayed_work *dwork = to_delayed_work(work);
2010 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2011 kvmclock_sync_work);
2012 struct kvm *kvm = container_of(ka, struct kvm, arch);
2013
630994b3
MT		 2014 if (!kvmclock_periodic_sync)
2015 return;
2016
332967a3
AJ		 2017 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2018 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2019 KVMCLOCK_SYNC_PERIOD);
2020}
2021
9ffd986c 2022static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2023{
890ca9ae
HY		 2024 u64 mcg_cap = vcpu->arch.mcg_cap;
2025 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2026 u32 msr = msr_info->index;
2027 u64 data = msr_info->data;
890ca9ae 2028
15c4a640 2029 switch (msr) {
15c4a640 2030 case MSR_IA32_MCG_STATUS:
890ca9ae 2031 vcpu->arch.mcg_status = data;
15c4a640 2032 break;
c7ac679c 2033 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2034 if (!(mcg_cap & MCG_CTL_P))
2035 return 1;
2036 if (data != 0 && data != ~(u64)0)
2037 return -1;
2038 vcpu->arch.mcg_ctl = data;
2039 break;
2040 default:
2041 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2042 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2043 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2044 /* only 0 or all 1s can be written to IA32_MCi_CTL
2045 * some Linux kernels though clear bit 10 in bank 4 to
2046 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2047 * this to avoid an uncatched #GP in the guest
2048 */
890ca9ae 2049 if ((offset & 0x3) == 0 &&
114be429 2050 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2051 return -1;
9ffd986c
WL		 2052 if (!msr_info->host_initiated &&
2053 (offset & 0x3) == 1 && data != 0)
2054 return -1;
890ca9ae
HY		 2055 vcpu->arch.mce_banks[offset] = data;
2056 break;
2057 }
2058 return 1;
2059 }
2060 return 0;
2061}
2062
ffde22ac
ES		 2063static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2064{
2065 struct kvm *kvm = vcpu->kvm;
2066 int lm = is_long_mode(vcpu);
2067 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2068 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2069 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2070 : kvm->arch.xen_hvm_config.blob_size_32;
2071 u32 page_num = data & ~PAGE_MASK;
2072 u64 page_addr = data & PAGE_MASK;
2073 u8 *page;
2074 int r;
2075
2076 r = -E2BIG;
2077 if (page_num >= blob_size)
2078 goto out;
2079 r = -ENOMEM;
ff5c2c03
SL		 2080 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2081 if (IS_ERR(page)) {
2082 r = PTR_ERR(page);
ffde22ac 2083 goto out;
ff5c2c03 2084 }
54bf36aa 2085 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2086 goto out_free;
2087 r = 0;
2088out_free:
2089 kfree(page);
2090out:
2091 return r;
2092}
2093
344d9588
GN		 2094static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2095{
2096 gpa_t gpa = data & ~0x3f;
2097
52a5c155
WL		 2098 /* Bits 3:5 are reserved, Should be zero */
2099 if (data & 0x38)
344d9588
GN		 2100 return 1;
2101
2102 vcpu->arch.apf.msr_val = data;
2103
2104 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2105 kvm_clear_async_pf_completion_queue(vcpu);
2106 kvm_async_pf_hash_reset(vcpu);
2107 return 0;
2108 }
2109
4e335d9e 2110 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2111 sizeof(u32)))
344d9588
GN		 2112 return 1;
2113
6adba527 2114 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2115 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2116 kvm_async_pf_wakeup_all(vcpu);
2117 return 0;
2118}
2119
12f9a48f
GC		 2120static void kvmclock_reset(struct kvm_vcpu *vcpu)
2121{
0b79459b 2122 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2123}
2124
f38a7b75
WL		 2125static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2126{
2127 ++vcpu->stat.tlb_flush;
2128 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2129}
2130
c9aaa895
GC		 2131static void record_steal_time(struct kvm_vcpu *vcpu)
2132{
2133 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2134 return;
2135
4e335d9e 2136 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2137 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2138 return;
2139
f38a7b75
WL		 2140 /*
2141 * Doing a TLB flush here, on the guest's behalf, can avoid
2142 * expensive IPIs.
2143 */
2144 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2145 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2146
35f3fae1
WL		 2147 if (vcpu->arch.st.steal.version & 1)
2148 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2149
2150 vcpu->arch.st.steal.version += 1;
2151
4e335d9e 2152 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2153 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2154
2155 smp_wmb();
2156
c54cdf14
LC		 2157 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2158 vcpu->arch.st.last_steal;
2159 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2160
4e335d9e 2161 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2162 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2163
2164 smp_wmb();
2165
2166 vcpu->arch.st.steal.version += 1;
c9aaa895 2167
4e335d9e 2168 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2169 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2170}
2171
8fe8ab46 2172int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2173{
5753785f 2174 bool pr = false;
8fe8ab46
WA		 2175 u32 msr = msr_info->index;
2176 u64 data = msr_info->data;
5753785f 2177
15c4a640 2178 switch (msr) {
2e32b719
BP		 2179 case MSR_AMD64_NB_CFG:
2180 case MSR_IA32_UCODE_REV:
2181 case MSR_IA32_UCODE_WRITE:
2182 case MSR_VM_HSAVE_PA:
2183 case MSR_AMD64_PATCH_LOADER:
2184 case MSR_AMD64_BU_CFG2:
405a353a 2185 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2186 break;
2187
15c4a640 2188 case MSR_EFER:
b69e8cae 2189 return set_efer(vcpu, data);
8f1589d9
AP		 2190 case MSR_K7_HWCR:
2191 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2192 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2193 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2194 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2195 if (data != 0) {
a737f256
CD		 2196 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2197 data);
8f1589d9
AP		 2198 return 1;
2199 }
15c4a640 2200 break;
f7c6d140
AP		 2201 case MSR_FAM10H_MMIO_CONF_BASE:
2202 if (data != 0) {
a737f256
CD		 2203 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2204 "0x%llx\n", data);
f7c6d140
AP		 2205 return 1;
2206 }
15c4a640 2207 break;
b5e2fec0
AG		 2208 case MSR_IA32_DEBUGCTLMSR:
2209 if (!data) {
2210 /* We support the non-activated case already */
2211 break;
2212 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2213 /* Values other than LBR and BTF are vendor-specific,
2214 thus reserved and should throw a #GP */
2215 return 1;
2216 }
a737f256
CD		 2217 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2218 __func__, data);
b5e2fec0 2219 break;
9ba075a6 2220 case 0x200 ... 0x2ff:
ff53604b 2221 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2222 case MSR_IA32_APICBASE:
58cb628d 2223 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2224 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2225 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2226 case MSR_IA32_TSCDEADLINE:
2227 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2228 break;
ba904635 2229 case MSR_IA32_TSC_ADJUST:
d6321d49 2230 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2231 if (!msr_info->host_initiated) {
d913b904 2232 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2233 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2234 }
2235 vcpu->arch.ia32_tsc_adjust_msr = data;
2236 }
2237 break;
15c4a640 2238 case MSR_IA32_MISC_ENABLE:
ad312c7c 2239 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2240 break;
64d60670
PB		 2241 case MSR_IA32_SMBASE:
2242 if (!msr_info->host_initiated)
2243 return 1;
2244 vcpu->arch.smbase = data;
2245 break;
52797bf9
LA		 2246 case MSR_SMI_COUNT:
2247 if (!msr_info->host_initiated)
2248 return 1;
2249 vcpu->arch.smi_count = data;
2250 break;
11c6bffa 2251 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2252 case MSR_KVM_WALL_CLOCK:
2253 vcpu->kvm->arch.wall_clock = data;
2254 kvm_write_wall_clock(vcpu->kvm, data);
2255 break;
11c6bffa 2256 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2257 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2258 struct kvm_arch *ka = &vcpu->kvm->arch;
2259
12f9a48f 2260 kvmclock_reset(vcpu);
18068523 2261
54750f2c
MT		 2262 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2263 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2264
2265 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2266 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2267
2268 ka->boot_vcpu_runs_old_kvmclock = tmp;
2269 }
2270
18068523 2271 vcpu->arch.time = data;
0061d53d 2272 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2273
2274 /* we verify if the enable bit is set... */
2275 if (!(data & 1))
2276 break;
2277
4e335d9e 2278 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2279 &vcpu->arch.pv_time, data & ~1ULL,
2280 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2281 vcpu->arch.pv_time_enabled = false;
2282 else
2283 vcpu->arch.pv_time_enabled = true;
32cad84f 2284
18068523
GOC		 2285 break;
2286 }
344d9588
GN		 2287 case MSR_KVM_ASYNC_PF_EN:
2288 if (kvm_pv_enable_async_pf(vcpu, data))
2289 return 1;
2290 break;
c9aaa895
GC		 2291 case MSR_KVM_STEAL_TIME:
2292
2293 if (unlikely(!sched_info_on()))
2294 return 1;
2295
2296 if (data & KVM_STEAL_RESERVED_MASK)
2297 return 1;
2298
4e335d9e 2299 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2300 data & KVM_STEAL_VALID_BITS,
2301 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2302 return 1;
2303
2304 vcpu->arch.st.msr_val = data;
2305
2306 if (!(data & KVM_MSR_ENABLED))
2307 break;
2308
c9aaa895
GC		 2309 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2310
2311 break;
ae7a2a3f
MT		 2312 case MSR_KVM_PV_EOI_EN:
2313 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2314 return 1;
2315 break;
c9aaa895 2316
890ca9ae
HY		 2317 case MSR_IA32_MCG_CTL:
2318 case MSR_IA32_MCG_STATUS:
81760dcc 2319 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2320 return set_msr_mce(vcpu, msr_info);
71db6023 2321
6912ac32
WH		 2322 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2323 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2324 pr = true; /* fall through */
2325 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2326 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2327 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2328 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2329
2330 if (pr || data != 0)
a737f256
CD		 2331 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2332 "0x%x data 0x%llx\n", msr, data);
5753785f 2333 break;
84e0cefa
JS		 2334 case MSR_K7_CLK_CTL:
2335 /*
2336 * Ignore all writes to this no longer documented MSR.
2337 * Writes are only relevant for old K7 processors,
2338 * all pre-dating SVM, but a recommended workaround from
4a969980 2339 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2340 * affected processor models on the command line, hence
2341 * the need to ignore the workaround.
2342 */
2343 break;
55cd8e5a 2344 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2345 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2346 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2347 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2348 return kvm_hv_set_msr_common(vcpu, msr, data,
2349 msr_info->host_initiated);
91c9c3ed 2350 case MSR_IA32_BBL_CR_CTL3:
2351 /* Drop writes to this legacy MSR -- see rdmsr
2352 * counterpart for further detail.
2353 */
fab0aa3b
EM		 2354 if (report_ignored_msrs)
2355 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2356 msr, data);
91c9c3ed 2357 break;
2b036c6b 2358 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2359 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2360 return 1;
2361 vcpu->arch.osvw.length = data;
2362 break;
2363 case MSR_AMD64_OSVW_STATUS:
d6321d49 2364 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2365 return 1;
2366 vcpu->arch.osvw.status = data;
2367 break;
db2336a8
KH		 2368 case MSR_PLATFORM_INFO:
2369 if (!msr_info->host_initiated ||
2370 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2371 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2372 cpuid_fault_enabled(vcpu)))
2373 return 1;
2374 vcpu->arch.msr_platform_info = data;
2375 break;
2376 case MSR_MISC_FEATURES_ENABLES:
2377 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2378 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2379 !supports_cpuid_fault(vcpu)))
2380 return 1;
2381 vcpu->arch.msr_misc_features_enables = data;
2382 break;
15c4a640 2383 default:
ffde22ac
ES		 2384 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2385 return xen_hvm_config(vcpu, data);
c6702c9d 2386 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2387 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2388 if (!ignore_msrs) {
ae0f5499 2389 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2390 msr, data);
ed85c068
AP		 2391 return 1;
2392 } else {
fab0aa3b
EM		 2393 if (report_ignored_msrs)
2394 vcpu_unimpl(vcpu,
2395 "ignored wrmsr: 0x%x data 0x%llx\n",
2396 msr, data);
ed85c068
AP		 2397 break;
2398 }
15c4a640
CO		 2399 }
2400 return 0;
2401}
2402EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2403
2404
2405/*
2406 * Reads an msr value (of 'msr_index') into 'pdata'.
2407 * Returns 0 on success, non-0 otherwise.
2408 * Assumes vcpu_load() was already called.
2409 */
609e36d3 2410int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2411{
609e36d3 2412 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2413}
ff651cb6 2414EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2415
890ca9ae 2416static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2417{
2418 u64 data;
890ca9ae
HY		 2419 u64 mcg_cap = vcpu->arch.mcg_cap;
2420 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2421
2422 switch (msr) {
15c4a640
CO		 2423 case MSR_IA32_P5_MC_ADDR:
2424 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2425 data = 0;
2426 break;
15c4a640 2427 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2428 data = vcpu->arch.mcg_cap;
2429 break;
c7ac679c 2430 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2431 if (!(mcg_cap & MCG_CTL_P))
2432 return 1;
2433 data = vcpu->arch.mcg_ctl;
2434 break;
2435 case MSR_IA32_MCG_STATUS:
2436 data = vcpu->arch.mcg_status;
2437 break;
2438 default:
2439 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2440 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2441 u32 offset = msr - MSR_IA32_MC0_CTL;
2442 data = vcpu->arch.mce_banks[offset];
2443 break;
2444 }
2445 return 1;
2446 }
2447 *pdata = data;
2448 return 0;
2449}
2450
609e36d3 2451int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2452{
609e36d3 2453 switch (msr_info->index) {
890ca9ae 2454 case MSR_IA32_PLATFORM_ID:
15c4a640 2455 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2456 case MSR_IA32_DEBUGCTLMSR:
2457 case MSR_IA32_LASTBRANCHFROMIP:
2458 case MSR_IA32_LASTBRANCHTOIP:
2459 case MSR_IA32_LASTINTFROMIP:
2460 case MSR_IA32_LASTINTTOIP:
60af2ecd 2461 case MSR_K8_SYSCFG:
3afb1121
PB		 2462 case MSR_K8_TSEG_ADDR:
2463 case MSR_K8_TSEG_MASK:
60af2ecd 2464 case MSR_K7_HWCR:
61a6bd67 2465 case MSR_VM_HSAVE_PA:
1fdbd48c 2466 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2467 case MSR_AMD64_NB_CFG:
f7c6d140 2468 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2469 case MSR_AMD64_BU_CFG2:
0c2df2a1 2470 case MSR_IA32_PERF_CTL:
405a353a 2471 case MSR_AMD64_DC_CFG:
609e36d3 2472 msr_info->data = 0;
15c4a640 2473 break;
6912ac32
WH		 2474 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2475 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2476 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2477 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2478 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2479 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2480 msr_info->data = 0;
5753785f 2481 break;
742bc670 2482 case MSR_IA32_UCODE_REV:
609e36d3 2483 msr_info->data = 0x100000000ULL;
742bc670 2484 break;
9ba075a6 2485 case MSR_MTRRcap:
9ba075a6 2486 case 0x200 ... 0x2ff:
ff53604b 2487 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2488 case 0xcd: /* fsb frequency */
609e36d3 2489 msr_info->data = 3;
15c4a640 2490 break;
7b914098
JS		 2491 /*
2492 * MSR_EBC_FREQUENCY_ID
2493 * Conservative value valid for even the basic CPU models.
2494 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2495 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2496 * and 266MHz for model 3, or 4. Set Core Clock
2497 * Frequency to System Bus Frequency Ratio to 1 (bits
2498 * 31:24) even though these are only valid for CPU
2499 * models > 2, however guests may end up dividing or
2500 * multiplying by zero otherwise.
2501 */
2502 case MSR_EBC_FREQUENCY_ID:
609e36d3 2503 msr_info->data = 1 << 24;
7b914098 2504 break;
15c4a640 2505 case MSR_IA32_APICBASE:
609e36d3 2506 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2507 break;
0105d1a5 2508 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2509 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2510 break;
a3e06bbe 2511 case MSR_IA32_TSCDEADLINE:
609e36d3 2512 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2513 break;
ba904635 2514 case MSR_IA32_TSC_ADJUST:
609e36d3 2515 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2516 break;
15c4a640 2517 case MSR_IA32_MISC_ENABLE:
609e36d3 2518 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2519 break;
64d60670
PB		 2520 case MSR_IA32_SMBASE:
2521 if (!msr_info->host_initiated)
2522 return 1;
2523 msr_info->data = vcpu->arch.smbase;
15c4a640 2524 break;
52797bf9
LA		 2525 case MSR_SMI_COUNT:
2526 msr_info->data = vcpu->arch.smi_count;
2527 break;
847f0ad8
AG		 2528 case MSR_IA32_PERF_STATUS:
2529 /* TSC increment by tick */
609e36d3 2530 msr_info->data = 1000ULL;
847f0ad8 2531 /* CPU multiplier */
b0996ae4 2532 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2533 break;
15c4a640 2534 case MSR_EFER:
609e36d3 2535 msr_info->data = vcpu->arch.efer;
15c4a640 2536 break;
18068523 2537 case MSR_KVM_WALL_CLOCK:
11c6bffa 2538 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2539 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2540 break;
2541 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2542 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2543 msr_info->data = vcpu->arch.time;
18068523 2544 break;
344d9588 2545 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2546 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2547 break;
c9aaa895 2548 case MSR_KVM_STEAL_TIME:
609e36d3 2549 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2550 break;
1d92128f 2551 case MSR_KVM_PV_EOI_EN:
609e36d3 2552 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2553 break;
890ca9ae
HY		 2554 case MSR_IA32_P5_MC_ADDR:
2555 case MSR_IA32_P5_MC_TYPE:
2556 case MSR_IA32_MCG_CAP:
2557 case MSR_IA32_MCG_CTL:
2558 case MSR_IA32_MCG_STATUS:
81760dcc 2559 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2560 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2561 case MSR_K7_CLK_CTL:
2562 /*
2563 * Provide expected ramp-up count for K7. All other
2564 * are set to zero, indicating minimum divisors for
2565 * every field.
2566 *
2567 * This prevents guest kernels on AMD host with CPU
2568 * type 6, model 8 and higher from exploding due to
2569 * the rdmsr failing.
2570 */
609e36d3 2571 msr_info->data = 0x20000000;
84e0cefa 2572 break;
55cd8e5a 2573 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2574 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2575 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2576 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2577 return kvm_hv_get_msr_common(vcpu,
2578 msr_info->index, &msr_info->data);
55cd8e5a 2579 break;
91c9c3ed 2580 case MSR_IA32_BBL_CR_CTL3:
2581 /* This legacy MSR exists but isn't fully documented in current
2582 * silicon. It is however accessed by winxp in very narrow
2583 * scenarios where it sets bit #19, itself documented as
2584 * a "reserved" bit. Best effort attempt to source coherent
2585 * read data here should the balance of the register be
2586 * interpreted by the guest:
2587 *
2588 * L2 cache control register 3: 64GB range, 256KB size,
2589 * enabled, latency 0x1, configured
2590 */
609e36d3 2591 msr_info->data = 0xbe702111;
91c9c3ed 2592 break;
2b036c6b 2593 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2594 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2595 return 1;
609e36d3 2596 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2597 break;
2598 case MSR_AMD64_OSVW_STATUS:
d6321d49 2599 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2600 return 1;
609e36d3 2601 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2602 break;
db2336a8
KH		 2603 case MSR_PLATFORM_INFO:
2604 msr_info->data = vcpu->arch.msr_platform_info;
2605 break;
2606 case MSR_MISC_FEATURES_ENABLES:
2607 msr_info->data = vcpu->arch.msr_misc_features_enables;
2608 break;
15c4a640 2609 default:
c6702c9d 2610 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2611 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2612 if (!ignore_msrs) {
ae0f5499
BD		 2613 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2614 msr_info->index);
ed85c068
AP		 2615 return 1;
2616 } else {
fab0aa3b
EM		 2617 if (report_ignored_msrs)
2618 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2619 msr_info->index);
609e36d3 2620 msr_info->data = 0;
ed85c068
AP		 2621 }
2622 break;
15c4a640 2623 }
15c4a640
CO		 2624 return 0;
2625}
2626EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2627
313a3dc7
CO		 2628/*
2629 * Read or write a bunch of msrs. All parameters are kernel addresses.
2630 *
2631 * @return number of msrs set successfully.
2632 */
2633static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2634 struct kvm_msr_entry *entries,
2635 int (*do_msr)(struct kvm_vcpu *vcpu,
2636 unsigned index, u64 *data))
2637{
f656ce01 2638 int i, idx;
313a3dc7 2639
f656ce01 2640 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2641 for (i = 0; i < msrs->nmsrs; ++i)
2642 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2643 break;
f656ce01 2644 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2645
313a3dc7
CO		 2646 return i;
2647}
2648
2649/*
2650 * Read or write a bunch of msrs. Parameters are user addresses.
2651 *
2652 * @return number of msrs set successfully.
2653 */
2654static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2655 int (*do_msr)(struct kvm_vcpu *vcpu,
2656 unsigned index, u64 *data),
2657 int writeback)
2658{
2659 struct kvm_msrs msrs;
2660 struct kvm_msr_entry *entries;
2661 int r, n;
2662 unsigned size;
2663
2664 r = -EFAULT;
2665 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2666 goto out;
2667
2668 r = -E2BIG;
2669 if (msrs.nmsrs >= MAX_IO_MSRS)
2670 goto out;
2671
313a3dc7 2672 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2673 entries = memdup_user(user_msrs->entries, size);
2674 if (IS_ERR(entries)) {
2675 r = PTR_ERR(entries);
313a3dc7 2676 goto out;
ff5c2c03 2677 }
313a3dc7
CO		 2678
2679 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2680 if (r < 0)
2681 goto out_free;
2682
2683 r = -EFAULT;
2684 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2685 goto out_free;
2686
2687 r = n;
2688
2689out_free:
7a73c028 2690 kfree(entries);
313a3dc7
CO		 2691out:
2692 return r;
2693}
2694
784aa3d7 2695int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2696{
2697 int r;
2698
2699 switch (ext) {
2700 case KVM_CAP_IRQCHIP:
2701 case KVM_CAP_HLT:
2702 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2703 case KVM_CAP_SET_TSS_ADDR:
07716717 2704 case KVM_CAP_EXT_CPUID:
9c15bb1d 2705 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2706 case KVM_CAP_CLOCKSOURCE:
7837699f 2707 case KVM_CAP_PIT:
a28e4f5a 2708 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2709 case KVM_CAP_MP_STATE:
ed848624 2710 case KVM_CAP_SYNC_MMU:
a355c85c 2711 case KVM_CAP_USER_NMI:
52d939a0 2712 case KVM_CAP_REINJECT_CONTROL:
4925663a 2713 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2714 case KVM_CAP_IOEVENTFD:
f848a5a8 2715 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2716 case KVM_CAP_PIT2:
e9f42757 2717 case KVM_CAP_PIT_STATE2:
b927a3ce 2718 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2719 case KVM_CAP_XEN_HVM:
3cfc3092 2720 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2721 case KVM_CAP_HYPERV:
10388a07 2722 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2723 case KVM_CAP_HYPERV_SPIN:
5c919412 2724 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2725 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2726 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2727 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2728 case KVM_CAP_DEBUGREGS:
d2be1651 2729 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2730 case KVM_CAP_XSAVE:
344d9588 2731 case KVM_CAP_ASYNC_PF:
92a1f12d 2732 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2733 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2734 case KVM_CAP_READONLY_MEM:
5f66b620 2735 case KVM_CAP_HYPERV_TIME:
100943c5 2736 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2737 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2738 case KVM_CAP_ENABLE_CAP_VM:
2739 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2740 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2741 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2742 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2743 r = 1;
2744 break;
e3fd9a93
PB		 2745 case KVM_CAP_ADJUST_CLOCK:
2746 r = KVM_CLOCK_TSC_STABLE;
2747 break;
668fffa3
MT		 2748 case KVM_CAP_X86_GUEST_MWAIT:
2749 r = kvm_mwait_in_guest();
2750 break;
6d396b55
PB		 2751 case KVM_CAP_X86_SMM:
2752 /* SMBASE is usually relocated above 1M on modern chipsets,
2753 * and SMM handlers might indeed rely on 4G segment limits,
2754 * so do not report SMM to be available if real mode is
2755 * emulated via vm86 mode. Still, do not go to great lengths
2756 * to avoid userspace's usage of the feature, because it is a
2757 * fringe case that is not enabled except via specific settings
2758 * of the module parameters.
2759 */
2760 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2761 break;
774ead3a
AK		 2762 case KVM_CAP_VAPIC:
2763 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2764 break;
f725230a 2765 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2766 r = KVM_SOFT_MAX_VCPUS;
2767 break;
2768 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2769 r = KVM_MAX_VCPUS;
2770 break;
a988b910 2771 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2772 r = KVM_USER_MEM_SLOTS;
a988b910 2773 break;
a68a6a72
MT		 2774 case KVM_CAP_PV_MMU: /* obsolete */
2775 r = 0;
2f333bcb 2776 break;
890ca9ae
HY		 2777 case KVM_CAP_MCE:
2778 r = KVM_MAX_MCE_BANKS;
2779 break;
2d5b5a66 2780 case KVM_CAP_XCRS:
d366bf7e 2781 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2782 break;
92a1f12d
JR		 2783 case KVM_CAP_TSC_CONTROL:
2784 r = kvm_has_tsc_control;
2785 break;
37131313
RK		 2786 case KVM_CAP_X2APIC_API:
2787 r = KVM_X2APIC_API_VALID_FLAGS;
2788 break;
018d00d2
ZX		 2789 default:
2790 r = 0;
2791 break;
2792 }
2793 return r;
2794
2795}
2796
043405e1
CO		 2797long kvm_arch_dev_ioctl(struct file *filp,
2798 unsigned int ioctl, unsigned long arg)
2799{
2800 void __user *argp = (void __user *)arg;
2801 long r;
2802
2803 switch (ioctl) {
2804 case KVM_GET_MSR_INDEX_LIST: {
2805 struct kvm_msr_list __user *user_msr_list = argp;
2806 struct kvm_msr_list msr_list;
2807 unsigned n;
2808
2809 r = -EFAULT;
2810 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2811 goto out;
2812 n = msr_list.nmsrs;
62ef68bb 2813 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2814 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2815 goto out;
2816 r = -E2BIG;
e125e7b6 2817 if (n < msr_list.nmsrs)
043405e1
CO		 2818 goto out;
2819 r = -EFAULT;
2820 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2821 num_msrs_to_save * sizeof(u32)))
2822 goto out;
e125e7b6 2823 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2824 &emulated_msrs,
62ef68bb 2825 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2826 goto out;
2827 r = 0;
2828 break;
2829 }
9c15bb1d
BP		 2830 case KVM_GET_SUPPORTED_CPUID:
2831 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2832 struct kvm_cpuid2 __user *cpuid_arg = argp;
2833 struct kvm_cpuid2 cpuid;
2834
2835 r = -EFAULT;
2836 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2837 goto out;
9c15bb1d
BP		 2838
2839 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2840 ioctl);
674eea0f
AK		 2841 if (r)
2842 goto out;
2843
2844 r = -EFAULT;
2845 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2846 goto out;
2847 r = 0;
2848 break;
2849 }
890ca9ae 2850 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2851 r = -EFAULT;
c45dcc71
AR		 2852 if (copy_to_user(argp, &kvm_mce_cap_supported,
2853 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2854 goto out;
2855 r = 0;
2856 break;
2857 }
043405e1
CO		 2858 default:
2859 r = -EINVAL;
2860 }
2861out:
2862 return r;
2863}
2864
f5f48ee1
SY		 2865static void wbinvd_ipi(void *garbage)
2866{
2867 wbinvd();
2868}
2869
2870static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2871{
e0f0bbc5 2872 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2873}
2874
313a3dc7
CO		 2875void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2876{
f5f48ee1
SY		 2877 /* Address WBINVD may be executed by guest */
2878 if (need_emulate_wbinvd(vcpu)) {
2879 if (kvm_x86_ops->has_wbinvd_exit())
2880 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2881 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2882 smp_call_function_single(vcpu->cpu,
2883 wbinvd_ipi, NULL, 1);
2884 }
2885
313a3dc7 2886 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2887
0dd6a6ed
ZA		 2888 /* Apply any externally detected TSC adjustments (due to suspend) */
2889 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2890 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2891 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2892 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2893 }
8f6055cb 2894
48434c20 2895 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2896 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2897 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2898 if (tsc_delta < 0)
2899 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2900
c285545f 2901 if (check_tsc_unstable()) {
07c1419a 2902 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2903 vcpu->arch.last_guest_tsc);
a545ab6a 2904 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2905 vcpu->arch.tsc_catchup = 1;
c285545f 2906 }
a749e247
PB		 2907
2908 if (kvm_lapic_hv_timer_in_use(vcpu))
2909 kvm_lapic_restart_hv_timer(vcpu);
2910
d98d07ca
MT		 2911 /*
2912 * On a host with synchronized TSC, there is no need to update
2913 * kvmclock on vcpu->cpu migration
2914 */
2915 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2916 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2917 if (vcpu->cpu != cpu)
1bd2009e 2918 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2919 vcpu->cpu = cpu;
6b7d7e76 2920 }
c9aaa895 2921
c9aaa895 2922 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2923}
2924
0b9f6c46
PX		 2925static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2926{
2927 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2928 return;
2929
fa55eedd 2930 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 2931
4e335d9e 2932 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2933 &vcpu->arch.st.steal.preempted,
2934 offsetof(struct kvm_steal_time, preempted),
2935 sizeof(vcpu->arch.st.steal.preempted));
2936}
2937
313a3dc7
CO		 2938void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2939{
cc0d907c 2940 int idx;
de63ad4c
LM		 2941
2942 if (vcpu->preempted)
2943 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2944
931f261b
AA		 2945 /*
2946 * Disable page faults because we're in atomic context here.
2947 * kvm_write_guest_offset_cached() would call might_fault()
2948 * that relies on pagefault_disable() to tell if there's a
2949 * bug. NOTE: the write to guest memory may not go through if
2950 * during postcopy live migration or if there's heavy guest
2951 * paging.
2952 */
2953 pagefault_disable();
cc0d907c
AA		 2954 /*
2955 * kvm_memslots() will be called by
2956 * kvm_write_guest_offset_cached() so take the srcu lock.
2957 */
2958 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2959 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2960 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2961 pagefault_enable();
02daab21 2962 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 2963 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2964}
2965
313a3dc7
CO		 2966static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2967 struct kvm_lapic_state *s)
2968{
76dfafd5 2969 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2970 kvm_x86_ops->sync_pir_to_irr(vcpu);
2971
a92e2543 2972 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2973}
2974
2975static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2976 struct kvm_lapic_state *s)
2977{
a92e2543
RK		 2978 int r;
2979
2980 r = kvm_apic_set_state(vcpu, s);
2981 if (r)
2982 return r;
cb142eb7 2983 update_cr8_intercept(vcpu);
313a3dc7
CO		 2984
2985 return 0;
2986}
2987
127a457a
MG		 2988static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2989{
2990 return (!lapic_in_kernel(vcpu) ||
2991 kvm_apic_accept_pic_intr(vcpu));
2992}
2993
782d422b
MG		 2994/*
2995 * if userspace requested an interrupt window, check that the
2996 * interrupt window is open.
2997 *
2998 * No need to exit to userspace if we already have an interrupt queued.
2999 */
3000static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3001{
3002 return kvm_arch_interrupt_allowed(vcpu) &&
3003 !kvm_cpu_has_interrupt(vcpu) &&
3004 !kvm_event_needs_reinjection(vcpu) &&
3005 kvm_cpu_accept_dm_intr(vcpu);
3006}
3007
f77bc6a4
ZX		 3008static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3009 struct kvm_interrupt *irq)
3010{
02cdb50f 3011 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3012 return -EINVAL;
1c1a9ce9
SR		 3013
3014 if (!irqchip_in_kernel(vcpu->kvm)) {
3015 kvm_queue_interrupt(vcpu, irq->irq, false);
3016 kvm_make_request(KVM_REQ_EVENT, vcpu);
3017 return 0;
3018 }
3019
3020 /*
3021 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3022 * fail for in-kernel 8259.
3023 */
3024 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3025 return -ENXIO;
f77bc6a4 3026
1c1a9ce9
SR		 3027 if (vcpu->arch.pending_external_vector != -1)
3028 return -EEXIST;
f77bc6a4 3029
1c1a9ce9 3030 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3031 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3032 return 0;
3033}
3034
c4abb7c9
JK		 3035static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3036{
c4abb7c9 3037 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3038
3039 return 0;
3040}
3041
f077825a
PB		 3042static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3043{
64d60670
PB		 3044 kvm_make_request(KVM_REQ_SMI, vcpu);
3045
f077825a
PB		 3046 return 0;
3047}
3048
b209749f
AK		 3049static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3050 struct kvm_tpr_access_ctl *tac)
3051{
3052 if (tac->flags)
3053 return -EINVAL;
3054 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3055 return 0;
3056}
3057
890ca9ae
HY		 3058static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3059 u64 mcg_cap)
3060{
3061 int r;
3062 unsigned bank_num = mcg_cap & 0xff, bank;
3063
3064 r = -EINVAL;
a9e38c3e 3065 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3066 goto out;
c45dcc71 3067 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3068 goto out;
3069 r = 0;
3070 vcpu->arch.mcg_cap = mcg_cap;
3071 /* Init IA32_MCG_CTL to all 1s */
3072 if (mcg_cap & MCG_CTL_P)
3073 vcpu->arch.mcg_ctl = ~(u64)0;
3074 /* Init IA32_MCi_CTL to all 1s */
3075 for (bank = 0; bank < bank_num; bank++)
3076 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3077
3078 if (kvm_x86_ops->setup_mce)
3079 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3080out:
3081 return r;
3082}
3083
3084static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3085 struct kvm_x86_mce *mce)
3086{
3087 u64 mcg_cap = vcpu->arch.mcg_cap;
3088 unsigned bank_num = mcg_cap & 0xff;
3089 u64 *banks = vcpu->arch.mce_banks;
3090
3091 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3092 return -EINVAL;
3093 /*
3094 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3095 * reporting is disabled
3096 */
3097 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3098 vcpu->arch.mcg_ctl != ~(u64)0)
3099 return 0;
3100 banks += 4 * mce->bank;
3101 /*
3102 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3103 * reporting is disabled for the bank
3104 */
3105 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3106 return 0;
3107 if (mce->status & MCI_STATUS_UC) {
3108 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3109 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3110 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3111 return 0;
3112 }
3113 if (banks[1] & MCI_STATUS_VAL)
3114 mce->status |= MCI_STATUS_OVER;
3115 banks[2] = mce->addr;
3116 banks[3] = mce->misc;
3117 vcpu->arch.mcg_status = mce->mcg_status;
3118 banks[1] = mce->status;
3119 kvm_queue_exception(vcpu, MC_VECTOR);
3120 } else if (!(banks[1] & MCI_STATUS_VAL)
3121 || !(banks[1] & MCI_STATUS_UC)) {
3122 if (banks[1] & MCI_STATUS_VAL)
3123 mce->status |= MCI_STATUS_OVER;
3124 banks[2] = mce->addr;
3125 banks[3] = mce->misc;
3126 banks[1] = mce->status;
3127 } else
3128 banks[1] |= MCI_STATUS_OVER;
3129 return 0;
3130}
3131
3cfc3092
JK		 3132static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3133 struct kvm_vcpu_events *events)
3134{
7460fb4a 3135 process_nmi(vcpu);
664f8e26
WL		 3136 /*
3137 * FIXME: pass injected and pending separately. This is only
3138 * needed for nested virtualization, whose state cannot be
3139 * migrated yet. For now we can combine them.
3140 */
03b82a30 3141 events->exception.injected =
664f8e26
WL		 3142 (vcpu->arch.exception.pending ||
3143 vcpu->arch.exception.injected) &&
03b82a30 3144 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3145 events->exception.nr = vcpu->arch.exception.nr;
3146 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3147 events->exception.pad = 0;
3cfc3092
JK		 3148 events->exception.error_code = vcpu->arch.exception.error_code;
3149
03b82a30
JK		 3150 events->interrupt.injected =
3151 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3152 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3153 events->interrupt.soft = 0;
37ccdcbe 3154 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3155
3156 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3157 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3158 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3159 events->nmi.pad = 0;
3cfc3092 3160
66450a21 3161 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3162
f077825a
PB		 3163 events->smi.smm = is_smm(vcpu);
3164 events->smi.pending = vcpu->arch.smi_pending;
3165 events->smi.smm_inside_nmi =
3166 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3167 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3168
dab4b911 3169 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3170 | KVM_VCPUEVENT_VALID_SHADOW
3171 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3172 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3173}
3174
6ef4e07e
XG		 3175static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3176
3cfc3092
JK		 3177static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3178 struct kvm_vcpu_events *events)
3179{
dab4b911 3180 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3181 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3182 | KVM_VCPUEVENT_VALID_SHADOW
3183 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3184 return -EINVAL;
3185
78e546c8 3186 if (events->exception.injected &&
28d06353
JM		 3187 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3188 is_guest_mode(vcpu)))
78e546c8
PB		 3189 return -EINVAL;
3190
28bf2888
DH		 3191 /* INITs are latched while in SMM */
3192 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3193 (events->smi.smm || events->smi.pending) &&
3194 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3195 return -EINVAL;
3196
7460fb4a 3197 process_nmi(vcpu);
664f8e26 3198 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3199 vcpu->arch.exception.pending = events->exception.injected;
3200 vcpu->arch.exception.nr = events->exception.nr;
3201 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3202 vcpu->arch.exception.error_code = events->exception.error_code;
3203
3204 vcpu->arch.interrupt.pending = events->interrupt.injected;
3205 vcpu->arch.interrupt.nr = events->interrupt.nr;
3206 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3207 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3208 kvm_x86_ops->set_interrupt_shadow(vcpu,
3209 events->interrupt.shadow);
3cfc3092
JK		 3210
3211 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3212 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3213 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3214 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3215
66450a21 3216 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3217 lapic_in_kernel(vcpu))
66450a21 3218 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3219
f077825a 3220 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3221 u32 hflags = vcpu->arch.hflags;
f077825a 3222 if (events->smi.smm)
6ef4e07e 3223 hflags |= HF_SMM_MASK;
f077825a 3224 else
6ef4e07e
XG		 3225 hflags &= ~HF_SMM_MASK;
3226 kvm_set_hflags(vcpu, hflags);
3227
f077825a 3228 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3229
3230 if (events->smi.smm) {
3231 if (events->smi.smm_inside_nmi)
3232 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3233 else
f4ef1910
WL		 3234 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3235 if (lapic_in_kernel(vcpu)) {
3236 if (events->smi.latched_init)
3237 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3238 else
3239 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3240 }
f077825a
PB		 3241 }
3242 }
3243
3842d135
AK		 3244 kvm_make_request(KVM_REQ_EVENT, vcpu);
3245
3cfc3092
JK		 3246 return 0;
3247}
3248
a1efbe77
JK		 3249static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3250 struct kvm_debugregs *dbgregs)
3251{
73aaf249
JK		 3252 unsigned long val;
3253
a1efbe77 3254 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3255 kvm_get_dr(vcpu, 6, &val);
73aaf249 3256 dbgregs->dr6 = val;
a1efbe77
JK		 3257 dbgregs->dr7 = vcpu->arch.dr7;
3258 dbgregs->flags = 0;
97e69aa6 3259 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3260}
3261
3262static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3263 struct kvm_debugregs *dbgregs)
3264{
3265 if (dbgregs->flags)
3266 return -EINVAL;
3267
d14bdb55
PB		 3268 if (dbgregs->dr6 & ~0xffffffffull)
3269 return -EINVAL;
3270 if (dbgregs->dr7 & ~0xffffffffull)
3271 return -EINVAL;
3272
a1efbe77 3273 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3274 kvm_update_dr0123(vcpu);
a1efbe77 3275 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3276 kvm_update_dr6(vcpu);
a1efbe77 3277 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3278 kvm_update_dr7(vcpu);
a1efbe77 3279
a1efbe77
JK		 3280 return 0;
3281}
3282
df1daba7
PB		 3283#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3284
3285static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3286{
c47ada30 3287 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3288 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3289 u64 valid;
3290
3291 /*
3292 * Copy legacy XSAVE area, to avoid complications with CPUID
3293 * leaves 0 and 1 in the loop below.
3294 */
3295 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3296
3297 /* Set XSTATE_BV */
00c87e9a 3298 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3299 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3300
3301 /*
3302 * Copy each region from the possibly compacted offset to the
3303 * non-compacted offset.
3304 */
d91cab78 3305 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3306 while (valid) {
3307 u64 feature = valid & -valid;
3308 int index = fls64(feature) - 1;
3309 void *src = get_xsave_addr(xsave, feature);
3310
3311 if (src) {
3312 u32 size, offset, ecx, edx;
3313 cpuid_count(XSTATE_CPUID, index,
3314 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3315 if (feature == XFEATURE_MASK_PKRU)
3316 memcpy(dest + offset, &vcpu->arch.pkru,
3317 sizeof(vcpu->arch.pkru));
3318 else
3319 memcpy(dest + offset, src, size);
3320
df1daba7
PB		 3321 }
3322
3323 valid -= feature;
3324 }
3325}
3326
3327static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3328{
c47ada30 3329 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3330 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3331 u64 valid;
3332
3333 /*
3334 * Copy legacy XSAVE area, to avoid complications with CPUID
3335 * leaves 0 and 1 in the loop below.
3336 */
3337 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3338
3339 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3340 xsave->header.xfeatures = xstate_bv;
782511b0 3341 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3342 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3343
3344 /*
3345 * Copy each region from the non-compacted offset to the
3346 * possibly compacted offset.
3347 */
d91cab78 3348 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3349 while (valid) {
3350 u64 feature = valid & -valid;
3351 int index = fls64(feature) - 1;
3352 void *dest = get_xsave_addr(xsave, feature);
3353
3354 if (dest) {
3355 u32 size, offset, ecx, edx;
3356 cpuid_count(XSTATE_CPUID, index,
3357 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3358 if (feature == XFEATURE_MASK_PKRU)
3359 memcpy(&vcpu->arch.pkru, src + offset,
3360 sizeof(vcpu->arch.pkru));
3361 else
3362 memcpy(dest, src + offset, size);
ee4100da 3363 }
df1daba7
PB		 3364
3365 valid -= feature;
3366 }
3367}
3368
2d5b5a66
SY		 3369static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3370 struct kvm_xsave *guest_xsave)
3371{
d366bf7e 3372 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3373 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3374 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3375 } else {
2d5b5a66 3376 memcpy(guest_xsave->region,
7366ed77 3377 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3378 sizeof(struct fxregs_state));
2d5b5a66 3379 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3380 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3381 }
3382}
3383
a575813b
WL		 3384#define XSAVE_MXCSR_OFFSET 24
3385
2d5b5a66
SY		 3386static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3387 struct kvm_xsave *guest_xsave)
3388{
3389 u64 xstate_bv =
3390 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3391 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3392
d366bf7e 3393 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3394 /*
3395 * Here we allow setting states that are not present in
3396 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3397 * with old userspace.
3398 */
a575813b
WL		 3399 if (xstate_bv & ~kvm_supported_xcr0() ||
3400 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3401 return -EINVAL;
df1daba7 3402 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3403 } else {
a575813b
WL		 3404 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3405 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3406 return -EINVAL;
7366ed77 3407 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3408 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3409 }
3410 return 0;
3411}
3412
3413static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3414 struct kvm_xcrs *guest_xcrs)
3415{
d366bf7e 3416 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3417 guest_xcrs->nr_xcrs = 0;
3418 return;
3419 }
3420
3421 guest_xcrs->nr_xcrs = 1;
3422 guest_xcrs->flags = 0;
3423 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3424 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3425}
3426
3427static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3428 struct kvm_xcrs *guest_xcrs)
3429{
3430 int i, r = 0;
3431
d366bf7e 3432 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3433 return -EINVAL;
3434
3435 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3436 return -EINVAL;
3437
3438 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3439 /* Only support XCR0 currently */
c67a04cb 3440 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3441 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3442 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3443 break;
3444 }
3445 if (r)
3446 r = -EINVAL;
3447 return r;
3448}
3449
1c0b28c2
EM		 3450/*
3451 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3452 * stopped by the hypervisor. This function will be called from the host only.
3453 * EINVAL is returned when the host attempts to set the flag for a guest that
3454 * does not support pv clocks.
3455 */
3456static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3457{
0b79459b 3458 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3459 return -EINVAL;
51d59c6b 3460 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3461 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3462 return 0;
3463}
3464
5c919412
AS		 3465static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3466 struct kvm_enable_cap *cap)
3467{
3468 if (cap->flags)
3469 return -EINVAL;
3470
3471 switch (cap->cap) {
efc479e6
RK		 3472 case KVM_CAP_HYPERV_SYNIC2:
3473 if (cap->args[0])
3474 return -EINVAL;
5c919412 3475 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3476 if (!irqchip_in_kernel(vcpu->kvm))
3477 return -EINVAL;
efc479e6
RK		 3478 return kvm_hv_activate_synic(vcpu, cap->cap ==
3479 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3480 default:
3481 return -EINVAL;
3482 }
3483}
3484
313a3dc7
CO		 3485long kvm_arch_vcpu_ioctl(struct file *filp,
3486 unsigned int ioctl, unsigned long arg)
3487{
3488 struct kvm_vcpu *vcpu = filp->private_data;
3489 void __user *argp = (void __user *)arg;
3490 int r;
d1ac91d8
AK		 3491 union {
3492 struct kvm_lapic_state *lapic;
3493 struct kvm_xsave *xsave;
3494 struct kvm_xcrs *xcrs;
3495 void *buffer;
3496 } u;
3497
9b062471
CD		 3498 vcpu_load(vcpu);
3499
d1ac91d8 3500 u.buffer = NULL;
313a3dc7
CO		 3501 switch (ioctl) {
3502 case KVM_GET_LAPIC: {
2204ae3c 3503 r = -EINVAL;
bce87cce 3504 if (!lapic_in_kernel(vcpu))
2204ae3c 3505 goto out;
d1ac91d8 3506 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3507
b772ff36 3508 r = -ENOMEM;
d1ac91d8 3509 if (!u.lapic)
b772ff36 3510 goto out;
d1ac91d8 3511 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3512 if (r)
3513 goto out;
3514 r = -EFAULT;
d1ac91d8 3515 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3516 goto out;
3517 r = 0;
3518 break;
3519 }
3520 case KVM_SET_LAPIC: {
2204ae3c 3521 r = -EINVAL;
bce87cce 3522 if (!lapic_in_kernel(vcpu))
2204ae3c 3523 goto out;
ff5c2c03 3524 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3525 if (IS_ERR(u.lapic)) {
3526 r = PTR_ERR(u.lapic);
3527 goto out_nofree;
3528 }
ff5c2c03 3529
d1ac91d8 3530 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3531 break;
3532 }
f77bc6a4
ZX		 3533 case KVM_INTERRUPT: {
3534 struct kvm_interrupt irq;
3535
3536 r = -EFAULT;
3537 if (copy_from_user(&irq, argp, sizeof irq))
3538 goto out;
3539 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3540 break;
3541 }
c4abb7c9
JK		 3542 case KVM_NMI: {
3543 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3544 break;
3545 }
f077825a
PB		 3546 case KVM_SMI: {
3547 r = kvm_vcpu_ioctl_smi(vcpu);
3548 break;
3549 }
313a3dc7
CO		 3550 case KVM_SET_CPUID: {
3551 struct kvm_cpuid __user *cpuid_arg = argp;
3552 struct kvm_cpuid cpuid;
3553
3554 r = -EFAULT;
3555 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3556 goto out;
3557 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3558 break;
3559 }
07716717
DK		 3560 case KVM_SET_CPUID2: {
3561 struct kvm_cpuid2 __user *cpuid_arg = argp;
3562 struct kvm_cpuid2 cpuid;
3563
3564 r = -EFAULT;
3565 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3566 goto out;
3567 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3568 cpuid_arg->entries);
07716717
DK		 3569 break;
3570 }
3571 case KVM_GET_CPUID2: {
3572 struct kvm_cpuid2 __user *cpuid_arg = argp;
3573 struct kvm_cpuid2 cpuid;
3574
3575 r = -EFAULT;
3576 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3577 goto out;
3578 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3579 cpuid_arg->entries);
07716717
DK		 3580 if (r)
3581 goto out;
3582 r = -EFAULT;
3583 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3584 goto out;
3585 r = 0;
3586 break;
3587 }
313a3dc7 3588 case KVM_GET_MSRS:
609e36d3 3589 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3590 break;
3591 case KVM_SET_MSRS:
3592 r = msr_io(vcpu, argp, do_set_msr, 0);
3593 break;
b209749f
AK		 3594 case KVM_TPR_ACCESS_REPORTING: {
3595 struct kvm_tpr_access_ctl tac;
3596
3597 r = -EFAULT;
3598 if (copy_from_user(&tac, argp, sizeof tac))
3599 goto out;
3600 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3601 if (r)
3602 goto out;
3603 r = -EFAULT;
3604 if (copy_to_user(argp, &tac, sizeof tac))
3605 goto out;
3606 r = 0;
3607 break;
3608 };
b93463aa
AK		 3609 case KVM_SET_VAPIC_ADDR: {
3610 struct kvm_vapic_addr va;
7301d6ab 3611 int idx;
b93463aa
AK		 3612
3613 r = -EINVAL;
35754c98 3614 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3615 goto out;
3616 r = -EFAULT;
3617 if (copy_from_user(&va, argp, sizeof va))
3618 goto out;
7301d6ab 3619 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3620 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3621 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3622 break;
3623 }
890ca9ae
HY		 3624 case KVM_X86_SETUP_MCE: {
3625 u64 mcg_cap;
3626
3627 r = -EFAULT;
3628 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3629 goto out;
3630 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3631 break;
3632 }
3633 case KVM_X86_SET_MCE: {
3634 struct kvm_x86_mce mce;
3635
3636 r = -EFAULT;
3637 if (copy_from_user(&mce, argp, sizeof mce))
3638 goto out;
3639 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3640 break;
3641 }
3cfc3092
JK		 3642 case KVM_GET_VCPU_EVENTS: {
3643 struct kvm_vcpu_events events;
3644
3645 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3646
3647 r = -EFAULT;
3648 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3649 break;
3650 r = 0;
3651 break;
3652 }
3653 case KVM_SET_VCPU_EVENTS: {
3654 struct kvm_vcpu_events events;
3655
3656 r = -EFAULT;
3657 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3658 break;
3659
3660 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3661 break;
3662 }
a1efbe77
JK		 3663 case KVM_GET_DEBUGREGS: {
3664 struct kvm_debugregs dbgregs;
3665
3666 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3667
3668 r = -EFAULT;
3669 if (copy_to_user(argp, &dbgregs,
3670 sizeof(struct kvm_debugregs)))
3671 break;
3672 r = 0;
3673 break;
3674 }
3675 case KVM_SET_DEBUGREGS: {
3676 struct kvm_debugregs dbgregs;
3677
3678 r = -EFAULT;
3679 if (copy_from_user(&dbgregs, argp,
3680 sizeof(struct kvm_debugregs)))
3681 break;
3682
3683 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3684 break;
3685 }
2d5b5a66 3686 case KVM_GET_XSAVE: {
d1ac91d8 3687 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3688 r = -ENOMEM;
d1ac91d8 3689 if (!u.xsave)
2d5b5a66
SY		 3690 break;
3691
d1ac91d8 3692 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3693
3694 r = -EFAULT;
d1ac91d8 3695 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3696 break;
3697 r = 0;
3698 break;
3699 }
3700 case KVM_SET_XSAVE: {
ff5c2c03 3701 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3702 if (IS_ERR(u.xsave)) {
3703 r = PTR_ERR(u.xsave);
3704 goto out_nofree;
3705 }
2d5b5a66 3706
d1ac91d8 3707 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3708 break;
3709 }
3710 case KVM_GET_XCRS: {
d1ac91d8 3711 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3712 r = -ENOMEM;
d1ac91d8 3713 if (!u.xcrs)
2d5b5a66
SY		 3714 break;
3715
d1ac91d8 3716 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3717
3718 r = -EFAULT;
d1ac91d8 3719 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3720 sizeof(struct kvm_xcrs)))
3721 break;
3722 r = 0;
3723 break;
3724 }
3725 case KVM_SET_XCRS: {
ff5c2c03 3726 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3727 if (IS_ERR(u.xcrs)) {
3728 r = PTR_ERR(u.xcrs);
3729 goto out_nofree;
3730 }
2d5b5a66 3731
d1ac91d8 3732 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3733 break;
3734 }
92a1f12d
JR		 3735 case KVM_SET_TSC_KHZ: {
3736 u32 user_tsc_khz;
3737
3738 r = -EINVAL;
92a1f12d
JR		 3739 user_tsc_khz = (u32)arg;
3740
3741 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3742 goto out;
3743
cc578287
ZA		 3744 if (user_tsc_khz == 0)
3745 user_tsc_khz = tsc_khz;
3746
381d585c
HZ		 3747 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3748 r = 0;
92a1f12d 3749
92a1f12d
JR		 3750 goto out;
3751 }
3752 case KVM_GET_TSC_KHZ: {
cc578287 3753 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3754 goto out;
3755 }
1c0b28c2
EM		 3756 case KVM_KVMCLOCK_CTRL: {
3757 r = kvm_set_guest_paused(vcpu);
3758 goto out;
3759 }
5c919412
AS		 3760 case KVM_ENABLE_CAP: {
3761 struct kvm_enable_cap cap;
3762
3763 r = -EFAULT;
3764 if (copy_from_user(&cap, argp, sizeof(cap)))
3765 goto out;
3766 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3767 break;
3768 }
313a3dc7
CO		 3769 default:
3770 r = -EINVAL;
3771 }
3772out:
d1ac91d8 3773 kfree(u.buffer);
9b062471
CD		 3774out_nofree:
3775 vcpu_put(vcpu);
313a3dc7
CO		 3776 return r;
3777}
3778
5b1c1493
CO		 3779int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3780{
3781 return VM_FAULT_SIGBUS;
3782}
3783
1fe779f8
CO		 3784static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3785{
3786 int ret;
3787
3788 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3789 return -EINVAL;
1fe779f8
CO		 3790 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3791 return ret;
3792}
3793
b927a3ce
SY		 3794static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3795 u64 ident_addr)
3796{
3797 kvm->arch.ept_identity_map_addr = ident_addr;
3798 return 0;
3799}
3800
1fe779f8
CO		 3801static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3802 u32 kvm_nr_mmu_pages)
3803{
3804 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3805 return -EINVAL;
3806
79fac95e 3807 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3808
3809 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3810 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3811
79fac95e 3812 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3813 return 0;
3814}
3815
3816static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3817{
39de71ec 3818 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3819}
3820
1fe779f8
CO		 3821static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3822{
90bca052 3823 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3824 int r;
3825
3826 r = 0;
3827 switch (chip->chip_id) {
3828 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3829 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3830 sizeof(struct kvm_pic_state));
3831 break;
3832 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3833 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3834 sizeof(struct kvm_pic_state));
3835 break;
3836 case KVM_IRQCHIP_IOAPIC:
33392b49 3837 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3838 break;
3839 default:
3840 r = -EINVAL;
3841 break;
3842 }
3843 return r;
3844}
3845
3846static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3847{
90bca052 3848 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3849 int r;
3850
3851 r = 0;
3852 switch (chip->chip_id) {
3853 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3854 spin_lock(&pic->lock);
3855 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3856 sizeof(struct kvm_pic_state));
90bca052 3857 spin_unlock(&pic->lock);
1fe779f8
CO		 3858 break;
3859 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3860 spin_lock(&pic->lock);
3861 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3862 sizeof(struct kvm_pic_state));
90bca052 3863 spin_unlock(&pic->lock);
1fe779f8
CO		 3864 break;
3865 case KVM_IRQCHIP_IOAPIC:
33392b49 3866 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3867 break;
3868 default:
3869 r = -EINVAL;
3870 break;
3871 }
90bca052 3872 kvm_pic_update_irq(pic);
1fe779f8
CO		 3873 return r;
3874}
3875
e0f63cb9
SY		 3876static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3877{
34f3941c
RK		 3878 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3879
3880 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3881
3882 mutex_lock(&kps->lock);
3883 memcpy(ps, &kps->channels, sizeof(*ps));
3884 mutex_unlock(&kps->lock);
2da29bcc 3885 return 0;
e0f63cb9
SY		 3886}
3887
3888static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3889{
0185604c 3890 int i;
09edea72
RK		 3891 struct kvm_pit *pit = kvm->arch.vpit;
3892
3893 mutex_lock(&pit->pit_state.lock);
34f3941c 3894 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3895 for (i = 0; i < 3; i++)
09edea72
RK		 3896 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3897 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3898 return 0;
e9f42757
BK		 3899}
3900
3901static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3902{
e9f42757
BK		 3903 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3904 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3905 sizeof(ps->channels));
3906 ps->flags = kvm->arch.vpit->pit_state.flags;
3907 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3908 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3909 return 0;
e9f42757
BK		 3910}
3911
3912static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3913{
2da29bcc 3914 int start = 0;
0185604c 3915 int i;
e9f42757 3916 u32 prev_legacy, cur_legacy;
09edea72
RK		 3917 struct kvm_pit *pit = kvm->arch.vpit;
3918
3919 mutex_lock(&pit->pit_state.lock);
3920 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3921 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3922 if (!prev_legacy && cur_legacy)
3923 start = 1;
09edea72
RK		 3924 memcpy(&pit->pit_state.channels, &ps->channels,
3925 sizeof(pit->pit_state.channels));
3926 pit->pit_state.flags = ps->flags;
0185604c 3927 for (i = 0; i < 3; i++)
09edea72 3928 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3929 start && i == 0);
09edea72 3930 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3931 return 0;
e0f63cb9
SY		 3932}
3933
52d939a0
MT		 3934static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3935 struct kvm_reinject_control *control)
3936{
71474e2f
RK		 3937 struct kvm_pit *pit = kvm->arch.vpit;
3938
3939 if (!pit)
52d939a0 3940 return -ENXIO;
b39c90b6 3941
71474e2f
RK		 3942 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3943 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3944 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3945 */
3946 mutex_lock(&pit->pit_state.lock);
3947 kvm_pit_set_reinject(pit, control->pit_reinject);
3948 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3949
52d939a0
MT		 3950 return 0;
3951}
3952
95d4c16c 3953/**
60c34612
TY		 3954 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3955 * @kvm: kvm instance
3956 * @log: slot id and address to which we copy the log
95d4c16c 3957 *
e108ff2f
PB		 3958 * Steps 1-4 below provide general overview of dirty page logging. See
3959 * kvm_get_dirty_log_protect() function description for additional details.
3960 *
3961 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3962 * always flush the TLB (step 4) even if previous step failed and the dirty
3963 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3964 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3965 * writes will be marked dirty for next log read.
95d4c16c 3966 *
60c34612
TY		 3967 * 1. Take a snapshot of the bit and clear it if needed.
3968 * 2. Write protect the corresponding page.
e108ff2f
PB		 3969 * 3. Copy the snapshot to the userspace.
3970 * 4. Flush TLB's if needed.
5bb064dc 3971 */
60c34612 3972int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3973{
60c34612 3974 bool is_dirty = false;
e108ff2f 3975 int r;
5bb064dc 3976
79fac95e 3977 mutex_lock(&kvm->slots_lock);
5bb064dc 3978
88178fd4
KH		 3979 /*
3980 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3981 */
3982 if (kvm_x86_ops->flush_log_dirty)
3983 kvm_x86_ops->flush_log_dirty(kvm);
3984
e108ff2f 3985 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3986
3987 /*
3988 * All the TLBs can be flushed out of mmu lock, see the comments in
3989 * kvm_mmu_slot_remove_write_access().
3990 */
e108ff2f 3991 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3992 if (is_dirty)
3993 kvm_flush_remote_tlbs(kvm);
3994
79fac95e 3995 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3996 return r;
3997}
3998
aa2fbe6d
YZ		 3999int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4000 bool line_status)
23d43cf9
CD		 4001{
4002 if (!irqchip_in_kernel(kvm))
4003 return -ENXIO;
4004
4005 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4006 irq_event->irq, irq_event->level,
4007 line_status);
23d43cf9
CD		 4008 return 0;
4009}
4010
90de4a18
NA		 4011static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4012 struct kvm_enable_cap *cap)
4013{
4014 int r;
4015
4016 if (cap->flags)
4017 return -EINVAL;
4018
4019 switch (cap->cap) {
4020 case KVM_CAP_DISABLE_QUIRKS:
4021 kvm->arch.disabled_quirks = cap->args[0];
4022 r = 0;
4023 break;
49df6397
SR		 4024 case KVM_CAP_SPLIT_IRQCHIP: {
4025 mutex_lock(&kvm->lock);
b053b2ae
SR		 4026 r = -EINVAL;
4027 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4028 goto split_irqchip_unlock;
49df6397
SR		 4029 r = -EEXIST;
4030 if (irqchip_in_kernel(kvm))
4031 goto split_irqchip_unlock;
557abc40 4032 if (kvm->created_vcpus)
49df6397
SR		 4033 goto split_irqchip_unlock;
4034 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4035 if (r)
49df6397
SR		 4036 goto split_irqchip_unlock;
4037 /* Pairs with irqchip_in_kernel. */
4038 smp_wmb();
49776faf 4039 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4040 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4041 r = 0;
4042split_irqchip_unlock:
4043 mutex_unlock(&kvm->lock);
4044 break;
4045 }
37131313
RK		 4046 case KVM_CAP_X2APIC_API:
4047 r = -EINVAL;
4048 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4049 break;
4050
4051 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4052 kvm->arch.x2apic_format = true;
c519265f
RK		 4053 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4054 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4055
4056 r = 0;
4057 break;
90de4a18
NA		 4058 default:
4059 r = -EINVAL;
4060 break;
4061 }
4062 return r;
4063}
4064
1fe779f8
CO		 4065long kvm_arch_vm_ioctl(struct file *filp,
4066 unsigned int ioctl, unsigned long arg)
4067{
4068 struct kvm *kvm = filp->private_data;
4069 void __user *argp = (void __user *)arg;
367e1319 4070 int r = -ENOTTY;
f0d66275
DH		 4071 /*
4072 * This union makes it completely explicit to gcc-3.x
4073 * that these two variables' stack usage should be
4074 * combined, not added together.
4075 */
4076 union {
4077 struct kvm_pit_state ps;
e9f42757 4078 struct kvm_pit_state2 ps2;
c5ff41ce 4079 struct kvm_pit_config pit_config;
f0d66275 4080 } u;
1fe779f8
CO		 4081
4082 switch (ioctl) {
4083 case KVM_SET_TSS_ADDR:
4084 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4085 break;
b927a3ce
SY		 4086 case KVM_SET_IDENTITY_MAP_ADDR: {
4087 u64 ident_addr;
4088
1af1ac91
DH		 4089 mutex_lock(&kvm->lock);
4090 r = -EINVAL;
4091 if (kvm->created_vcpus)
4092 goto set_identity_unlock;
b927a3ce
SY		 4093 r = -EFAULT;
4094 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4095 goto set_identity_unlock;
b927a3ce 4096 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4097set_identity_unlock:
4098 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4099 break;
4100 }
1fe779f8
CO		 4101 case KVM_SET_NR_MMU_PAGES:
4102 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4103 break;
4104 case KVM_GET_NR_MMU_PAGES:
4105 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4106 break;
3ddea128 4107 case KVM_CREATE_IRQCHIP: {
3ddea128 4108 mutex_lock(&kvm->lock);
09941366 4109
3ddea128 4110 r = -EEXIST;
35e6eaa3 4111 if (irqchip_in_kernel(kvm))
3ddea128 4112 goto create_irqchip_unlock;
09941366 4113
3e515705 4114 r = -EINVAL;
557abc40 4115 if (kvm->created_vcpus)
3e515705 4116 goto create_irqchip_unlock;
09941366
RK		 4117
4118 r = kvm_pic_init(kvm);
4119 if (r)
3ddea128 4120 goto create_irqchip_unlock;
09941366
RK		 4121
4122 r = kvm_ioapic_init(kvm);
4123 if (r) {
09941366 4124 kvm_pic_destroy(kvm);
3ddea128 4125 goto create_irqchip_unlock;
09941366
RK		 4126 }
4127
399ec807
AK		 4128 r = kvm_setup_default_irq_routing(kvm);
4129 if (r) {
72bb2fcd 4130 kvm_ioapic_destroy(kvm);
09941366 4131 kvm_pic_destroy(kvm);
71ba994c 4132 goto create_irqchip_unlock;
399ec807 4133 }
49776faf 4134 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4135 smp_wmb();
49776faf 4136 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4137 create_irqchip_unlock:
4138 mutex_unlock(&kvm->lock);
1fe779f8 4139 break;
3ddea128 4140 }
7837699f 4141 case KVM_CREATE_PIT:
c5ff41ce
JK		 4142 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4143 goto create_pit;
4144 case KVM_CREATE_PIT2:
4145 r = -EFAULT;
4146 if (copy_from_user(&u.pit_config, argp,
4147 sizeof(struct kvm_pit_config)))
4148 goto out;
4149 create_pit:
250715a6 4150 mutex_lock(&kvm->lock);
269e05e4
AK		 4151 r = -EEXIST;
4152 if (kvm->arch.vpit)
4153 goto create_pit_unlock;
7837699f 4154 r = -ENOMEM;
c5ff41ce 4155 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4156 if (kvm->arch.vpit)
4157 r = 0;
269e05e4 4158 create_pit_unlock:
250715a6 4159 mutex_unlock(&kvm->lock);
7837699f 4160 break;
1fe779f8
CO		 4161 case KVM_GET_IRQCHIP: {
4162 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4163 struct kvm_irqchip *chip;
1fe779f8 4164
ff5c2c03
SL		 4165 chip = memdup_user(argp, sizeof(*chip));
4166 if (IS_ERR(chip)) {
4167 r = PTR_ERR(chip);
1fe779f8 4168 goto out;
ff5c2c03
SL		 4169 }
4170
1fe779f8 4171 r = -ENXIO;
826da321 4172 if (!irqchip_kernel(kvm))
f0d66275
DH		 4173 goto get_irqchip_out;
4174 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4175 if (r)
f0d66275 4176 goto get_irqchip_out;
1fe779f8 4177 r = -EFAULT;
f0d66275
DH		 4178 if (copy_to_user(argp, chip, sizeof *chip))
4179 goto get_irqchip_out;
1fe779f8 4180 r = 0;
f0d66275
DH		 4181 get_irqchip_out:
4182 kfree(chip);
1fe779f8
CO		 4183 break;
4184 }
4185 case KVM_SET_IRQCHIP: {
4186 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4187 struct kvm_irqchip *chip;
1fe779f8 4188
ff5c2c03
SL		 4189 chip = memdup_user(argp, sizeof(*chip));
4190 if (IS_ERR(chip)) {
4191 r = PTR_ERR(chip);
1fe779f8 4192 goto out;
ff5c2c03
SL		 4193 }
4194
1fe779f8 4195 r = -ENXIO;
826da321 4196 if (!irqchip_kernel(kvm))
f0d66275
DH		 4197 goto set_irqchip_out;
4198 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4199 if (r)
f0d66275 4200 goto set_irqchip_out;
1fe779f8 4201 r = 0;
f0d66275
DH		 4202 set_irqchip_out:
4203 kfree(chip);
1fe779f8
CO		 4204 break;
4205 }
e0f63cb9 4206 case KVM_GET_PIT: {
e0f63cb9 4207 r = -EFAULT;
f0d66275 4208 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4209 goto out;
4210 r = -ENXIO;
4211 if (!kvm->arch.vpit)
4212 goto out;
f0d66275 4213 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4214 if (r)
4215 goto out;
4216 r = -EFAULT;
f0d66275 4217 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4218 goto out;
4219 r = 0;
4220 break;
4221 }
4222 case KVM_SET_PIT: {
e0f63cb9 4223 r = -EFAULT;
f0d66275 4224 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4225 goto out;
4226 r = -ENXIO;
4227 if (!kvm->arch.vpit)
4228 goto out;
f0d66275 4229 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4230 break;
4231 }
e9f42757
BK		 4232 case KVM_GET_PIT2: {
4233 r = -ENXIO;
4234 if (!kvm->arch.vpit)
4235 goto out;
4236 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4237 if (r)
4238 goto out;
4239 r = -EFAULT;
4240 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4241 goto out;
4242 r = 0;
4243 break;
4244 }
4245 case KVM_SET_PIT2: {
4246 r = -EFAULT;
4247 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4248 goto out;
4249 r = -ENXIO;
4250 if (!kvm->arch.vpit)
4251 goto out;
4252 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4253 break;
4254 }
52d939a0
MT		 4255 case KVM_REINJECT_CONTROL: {
4256 struct kvm_reinject_control control;
4257 r = -EFAULT;
4258 if (copy_from_user(&control, argp, sizeof(control)))
4259 goto out;
4260 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4261 break;
4262 }
d71ba788
PB		 4263 case KVM_SET_BOOT_CPU_ID:
4264 r = 0;
4265 mutex_lock(&kvm->lock);
557abc40 4266 if (kvm->created_vcpus)
d71ba788
PB		 4267 r = -EBUSY;
4268 else
4269 kvm->arch.bsp_vcpu_id = arg;
4270 mutex_unlock(&kvm->lock);
4271 break;
ffde22ac
ES		 4272 case KVM_XEN_HVM_CONFIG: {
4273 r = -EFAULT;
4274 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4275 sizeof(struct kvm_xen_hvm_config)))
4276 goto out;
4277 r = -EINVAL;
4278 if (kvm->arch.xen_hvm_config.flags)
4279 goto out;
4280 r = 0;
4281 break;
4282 }
afbcf7ab 4283 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4284 struct kvm_clock_data user_ns;
4285 u64 now_ns;
afbcf7ab
GC		 4286
4287 r = -EFAULT;
4288 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4289 goto out;
4290
4291 r = -EINVAL;
4292 if (user_ns.flags)
4293 goto out;
4294
4295 r = 0;
0bc48bea
RK		 4296 /*
4297 * TODO: userspace has to take care of races with VCPU_RUN, so
4298 * kvm_gen_update_masterclock() can be cut down to locked
4299 * pvclock_update_vm_gtod_copy().
4300 */
4301 kvm_gen_update_masterclock(kvm);
e891a32e 4302 now_ns = get_kvmclock_ns(kvm);
108b249c 4303 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4304 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4305 break;
4306 }
4307 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4308 struct kvm_clock_data user_ns;
4309 u64 now_ns;
4310
e891a32e 4311 now_ns = get_kvmclock_ns(kvm);
108b249c 4312 user_ns.clock = now_ns;
e3fd9a93 4313 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4314 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4315
4316 r = -EFAULT;
4317 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4318 goto out;
4319 r = 0;
4320 break;
4321 }
90de4a18
NA		 4322 case KVM_ENABLE_CAP: {
4323 struct kvm_enable_cap cap;
afbcf7ab 4324
90de4a18
NA		 4325 r = -EFAULT;
4326 if (copy_from_user(&cap, argp, sizeof(cap)))
4327 goto out;
4328 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4329 break;
4330 }
1fe779f8 4331 default:
ad6260da 4332 r = -ENOTTY;
1fe779f8
CO		 4333 }
4334out:
4335 return r;
4336}
4337
a16b043c 4338static void kvm_init_msr_list(void)
043405e1
CO		 4339{
4340 u32 dummy[2];
4341 unsigned i, j;
4342
62ef68bb 4343 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4344 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4345 continue;
93c4adc7
PB		 4346
4347 /*
4348 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4349 * to the guests in some cases.
93c4adc7
PB		 4350 */
4351 switch (msrs_to_save[i]) {
4352 case MSR_IA32_BNDCFGS:
4353 if (!kvm_x86_ops->mpx_supported())
4354 continue;
4355 break;
9dbe6cf9
PB		 4356 case MSR_TSC_AUX:
4357 if (!kvm_x86_ops->rdtscp_supported())
4358 continue;
4359 break;
93c4adc7
PB		 4360 default:
4361 break;
4362 }
4363
043405e1
CO		 4364 if (j < i)
4365 msrs_to_save[j] = msrs_to_save[i];
4366 j++;
4367 }
4368 num_msrs_to_save = j;
62ef68bb
PB		 4369
4370 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4371 switch (emulated_msrs[i]) {
6d396b55
PB		 4372 case MSR_IA32_SMBASE:
4373 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4374 continue;
4375 break;
62ef68bb
PB		 4376 default:
4377 break;
4378 }
4379
4380 if (j < i)
4381 emulated_msrs[j] = emulated_msrs[i];
4382 j++;
4383 }
4384 num_emulated_msrs = j;
043405e1
CO		 4385}
4386
bda9020e
MT		 4387static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4388 const void *v)
bbd9b64e 4389{
70252a10
AK		 4390 int handled = 0;
4391 int n;
4392
4393 do {
4394 n = min(len, 8);
bce87cce 4395 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4396 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4397 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4398 break;
4399 handled += n;
4400 addr += n;
4401 len -= n;
4402 v += n;
4403 } while (len);
bbd9b64e 4404
70252a10 4405 return handled;
bbd9b64e
CO		 4406}
4407
bda9020e 4408static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4409{
70252a10
AK		 4410 int handled = 0;
4411 int n;
4412
4413 do {
4414 n = min(len, 8);
bce87cce 4415 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4416 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4417 addr, n, v))
4418 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4419 break;
4420 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4421 handled += n;
4422 addr += n;
4423 len -= n;
4424 v += n;
4425 } while (len);
bbd9b64e 4426
70252a10 4427 return handled;
bbd9b64e
CO		 4428}
4429
2dafc6c2
GN		 4430static void kvm_set_segment(struct kvm_vcpu *vcpu,
4431 struct kvm_segment *var, int seg)
4432{
4433 kvm_x86_ops->set_segment(vcpu, var, seg);
4434}
4435
4436void kvm_get_segment(struct kvm_vcpu *vcpu,
4437 struct kvm_segment *var, int seg)
4438{
4439 kvm_x86_ops->get_segment(vcpu, var, seg);
4440}
4441
54987b7a
PB		 4442gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4443 struct x86_exception *exception)
02f59dc9
JR		 4444{
4445 gpa_t t_gpa;
02f59dc9
JR		 4446
4447 BUG_ON(!mmu_is_nested(vcpu));
4448
4449 /* NPT walks are always user-walks */
4450 access |= PFERR_USER_MASK;
54987b7a 4451 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4452
4453 return t_gpa;
4454}
4455
ab9ae313
AK		 4456gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4457 struct x86_exception *exception)
1871c602
GN		 4458{
4459 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4460 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4461}
4462
ab9ae313
AK		 4463 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4464 struct x86_exception *exception)
1871c602
GN		 4465{
4466 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4467 access |= PFERR_FETCH_MASK;
ab9ae313 4468 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4469}
4470
ab9ae313
AK		 4471gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4472 struct x86_exception *exception)
1871c602
GN		 4473{
4474 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4475 access |= PFERR_WRITE_MASK;
ab9ae313 4476 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4477}
4478
4479/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4480gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4481 struct x86_exception *exception)
1871c602 4482{
ab9ae313 4483 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4484}
4485
4486static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4487 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4488 struct x86_exception *exception)
bbd9b64e
CO		 4489{
4490 void *data = val;
10589a46 4491 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4492
4493 while (bytes) {
14dfe855 4494 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4495 exception);
bbd9b64e 4496 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4497 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4498 int ret;
4499
bcc55cba 4500 if (gpa == UNMAPPED_GVA)
ab9ae313 4501 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4502 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4503 offset, toread);
10589a46 4504 if (ret < 0) {
c3cd7ffa 4505 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4506 goto out;
4507 }
bbd9b64e 4508
77c2002e
IE		 4509 bytes -= toread;
4510 data += toread;
4511 addr += toread;
bbd9b64e 4512 }
10589a46 4513out:
10589a46 4514 return r;
bbd9b64e 4515}
77c2002e 4516
1871c602 4517/* used for instruction fetching */
0f65dd70
AK		 4518static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4519 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4520 struct x86_exception *exception)
1871c602 4521{
0f65dd70 4522 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4523 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4524 unsigned offset;
4525 int ret;
0f65dd70 4526
44583cba
PB		 4527 /* Inline kvm_read_guest_virt_helper for speed. */
4528 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4529 exception);
4530 if (unlikely(gpa == UNMAPPED_GVA))
4531 return X86EMUL_PROPAGATE_FAULT;
4532
4533 offset = addr & (PAGE_SIZE-1);
4534 if (WARN_ON(offset + bytes > PAGE_SIZE))
4535 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4536 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4537 offset, bytes);
44583cba
PB		 4538 if (unlikely(ret < 0))
4539 return X86EMUL_IO_NEEDED;
4540
4541 return X86EMUL_CONTINUE;
1871c602
GN		 4542}
4543
064aea77 4544int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4545 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4546 struct x86_exception *exception)
1871c602 4547{
0f65dd70 4548 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4549 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4550
1871c602 4551 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4552 exception);
1871c602 4553}
064aea77 4554EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4555
0f65dd70
AK		 4556static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4557 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4558 struct x86_exception *exception)
1871c602 4559{
0f65dd70 4560 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4561 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4562}
4563
7a036a6f
RK		 4564static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4565 unsigned long addr, void *val, unsigned int bytes)
4566{
4567 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4568 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4569
4570 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4571}
4572
6a4d7550 4573int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4574 gva_t addr, void *val,
2dafc6c2 4575 unsigned int bytes,
bcc55cba 4576 struct x86_exception *exception)
77c2002e 4577{
0f65dd70 4578 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4579 void *data = val;
4580 int r = X86EMUL_CONTINUE;
4581
4582 while (bytes) {
14dfe855
JR		 4583 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4584 PFERR_WRITE_MASK,
ab9ae313 4585 exception);
77c2002e
IE		 4586 unsigned offset = addr & (PAGE_SIZE-1);
4587 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4588 int ret;
4589
bcc55cba 4590 if (gpa == UNMAPPED_GVA)
ab9ae313 4591 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4592 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4593 if (ret < 0) {
c3cd7ffa 4594 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4595 goto out;
4596 }
4597
4598 bytes -= towrite;
4599 data += towrite;
4600 addr += towrite;
4601 }
4602out:
4603 return r;
4604}
6a4d7550 4605EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4606
0f89b207
TL		 4607static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4608 gpa_t gpa, bool write)
4609{
4610 /* For APIC access vmexit */
4611 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4612 return 1;
4613
4614 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4615 trace_vcpu_match_mmio(gva, gpa, write, true);
4616 return 1;
4617 }
4618
4619 return 0;
4620}
4621
af7cc7d1
XG		 4622static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4623 gpa_t *gpa, struct x86_exception *exception,
4624 bool write)
4625{
97d64b78
AK		 4626 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4627 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4628
be94f6b7
HH		 4629 /*
4630 * currently PKRU is only applied to ept enabled guest so
4631 * there is no pkey in EPT page table for L1 guest or EPT
4632 * shadow page table for L2 guest.
4633 */
97d64b78 4634 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4635 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4636 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4637 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4638 (gva & (PAGE_SIZE - 1));
4f022648 4639 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4640 return 1;
4641 }
4642
af7cc7d1
XG		 4643 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4644
4645 if (*gpa == UNMAPPED_GVA)
4646 return -1;
4647
0f89b207 4648 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4649}
4650
3200f405 4651int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4652 const void *val, int bytes)
bbd9b64e
CO		 4653{
4654 int ret;
4655
54bf36aa 4656 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4657 if (ret < 0)
bbd9b64e 4658 return 0;
0eb05bf2 4659 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4660 return 1;
4661}
4662
77d197b2
XG		 4663struct read_write_emulator_ops {
4664 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4665 int bytes);
4666 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4667 void *val, int bytes);
4668 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4669 int bytes, void *val);
4670 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4671 void *val, int bytes);
4672 bool write;
4673};
4674
4675static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4676{
4677 if (vcpu->mmio_read_completed) {
77d197b2 4678 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4679 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4680 vcpu->mmio_read_completed = 0;
4681 return 1;
4682 }
4683
4684 return 0;
4685}
4686
4687static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4688 void *val, int bytes)
4689{
54bf36aa 4690 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4691}
4692
4693static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4694 void *val, int bytes)
4695{
4696 return emulator_write_phys(vcpu, gpa, val, bytes);
4697}
4698
4699static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4700{
4701 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4702 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4703}
4704
4705static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4706 void *val, int bytes)
4707{
4708 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4709 return X86EMUL_IO_NEEDED;
4710}
4711
4712static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4713 void *val, int bytes)
4714{
f78146b0
AK		 4715 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4716
87da7e66 4717 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4718 return X86EMUL_CONTINUE;
4719}
4720
0fbe9b0b 4721static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4722 .read_write_prepare = read_prepare,
4723 .read_write_emulate = read_emulate,
4724 .read_write_mmio = vcpu_mmio_read,
4725 .read_write_exit_mmio = read_exit_mmio,
4726};
4727
0fbe9b0b 4728static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4729 .read_write_emulate = write_emulate,
4730 .read_write_mmio = write_mmio,
4731 .read_write_exit_mmio = write_exit_mmio,
4732 .write = true,
4733};
4734
22388a3c
XG		 4735static int emulator_read_write_onepage(unsigned long addr, void *val,
4736 unsigned int bytes,
4737 struct x86_exception *exception,
4738 struct kvm_vcpu *vcpu,
0fbe9b0b 4739 const struct read_write_emulator_ops *ops)
bbd9b64e 4740{
af7cc7d1
XG		 4741 gpa_t gpa;
4742 int handled, ret;
22388a3c 4743 bool write = ops->write;
f78146b0 4744 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4745 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4746
4747 /*
4748 * If the exit was due to a NPF we may already have a GPA.
4749 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4750 * Note, this cannot be used on string operations since string
4751 * operation using rep will only have the initial GPA from the NPF
4752 * occurred.
4753 */
4754 if (vcpu->arch.gpa_available &&
4755 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4756 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4757 gpa = vcpu->arch.gpa_val;
4758 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4759 } else {
4760 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4761 if (ret < 0)
4762 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4763 }
10589a46 4764
618232e2 4765 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4766 return X86EMUL_CONTINUE;
4767
bbd9b64e
CO		 4768 /*
4769 * Is this MMIO handled locally?
4770 */
22388a3c 4771 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4772 if (handled == bytes)
bbd9b64e 4773 return X86EMUL_CONTINUE;
bbd9b64e 4774
70252a10
AK		 4775 gpa += handled;
4776 bytes -= handled;
4777 val += handled;
4778
87da7e66
XG		 4779 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4780 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4781 frag->gpa = gpa;
4782 frag->data = val;
4783 frag->len = bytes;
f78146b0 4784 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4785}
4786
52eb5a6d
XL		 4787static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4788 unsigned long addr,
22388a3c
XG		 4789 void *val, unsigned int bytes,
4790 struct x86_exception *exception,
0fbe9b0b 4791 const struct read_write_emulator_ops *ops)
bbd9b64e 4792{
0f65dd70 4793 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4794 gpa_t gpa;
4795 int rc;
4796
4797 if (ops->read_write_prepare &&
4798 ops->read_write_prepare(vcpu, val, bytes))
4799 return X86EMUL_CONTINUE;
4800
4801 vcpu->mmio_nr_fragments = 0;
0f65dd70 4802
bbd9b64e
CO		 4803 /* Crossing a page boundary? */
4804 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4805 int now;
bbd9b64e
CO		 4806
4807 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4808 rc = emulator_read_write_onepage(addr, val, now, exception,
4809 vcpu, ops);
4810
bbd9b64e
CO		 4811 if (rc != X86EMUL_CONTINUE)
4812 return rc;
4813 addr += now;
bac15531
NA		 4814 if (ctxt->mode != X86EMUL_MODE_PROT64)
4815 addr = (u32)addr;
bbd9b64e
CO		 4816 val += now;
4817 bytes -= now;
4818 }
22388a3c 4819
f78146b0
AK		 4820 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4821 vcpu, ops);
4822 if (rc != X86EMUL_CONTINUE)
4823 return rc;
4824
4825 if (!vcpu->mmio_nr_fragments)
4826 return rc;
4827
4828 gpa = vcpu->mmio_fragments[0].gpa;
4829
4830 vcpu->mmio_needed = 1;
4831 vcpu->mmio_cur_fragment = 0;
4832
87da7e66 4833 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4834 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4835 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4836 vcpu->run->mmio.phys_addr = gpa;
4837
4838 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4839}
4840
4841static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4842 unsigned long addr,
4843 void *val,
4844 unsigned int bytes,
4845 struct x86_exception *exception)
4846{
4847 return emulator_read_write(ctxt, addr, val, bytes,
4848 exception, &read_emultor);
4849}
4850
52eb5a6d 4851static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4852 unsigned long addr,
4853 const void *val,
4854 unsigned int bytes,
4855 struct x86_exception *exception)
4856{
4857 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4858 exception, &write_emultor);
bbd9b64e 4859}
bbd9b64e 4860
daea3e73
AK		 4861#define CMPXCHG_TYPE(t, ptr, old, new) \
4862 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4863
4864#ifdef CONFIG_X86_64
4865# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4866#else
4867# define CMPXCHG64(ptr, old, new) \
9749a6c0 4868 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4869#endif
4870
0f65dd70
AK		 4871static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4872 unsigned long addr,
bbd9b64e
CO		 4873 const void *old,
4874 const void *new,
4875 unsigned int bytes,
0f65dd70 4876 struct x86_exception *exception)
bbd9b64e 4877{
0f65dd70 4878 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4879 gpa_t gpa;
4880 struct page *page;
4881 char *kaddr;
4882 bool exchanged;
2bacc55c 4883
daea3e73
AK		 4884 /* guests cmpxchg8b have to be emulated atomically */
4885 if (bytes > 8 || (bytes & (bytes - 1)))
4886 goto emul_write;
10589a46 4887
daea3e73 4888 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4889
daea3e73
AK		 4890 if (gpa == UNMAPPED_GVA ||
4891 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4892 goto emul_write;
2bacc55c 4893
daea3e73
AK		 4894 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4895 goto emul_write;
72dc67a6 4896
54bf36aa 4897 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4898 if (is_error_page(page))
c19b8bd6 4899 goto emul_write;
72dc67a6 4900
8fd75e12 4901 kaddr = kmap_atomic(page);
daea3e73
AK		 4902 kaddr += offset_in_page(gpa);
4903 switch (bytes) {
4904 case 1:
4905 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4906 break;
4907 case 2:
4908 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4909 break;
4910 case 4:
4911 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4912 break;
4913 case 8:
4914 exchanged = CMPXCHG64(kaddr, old, new);
4915 break;
4916 default:
4917 BUG();
2bacc55c 4918 }
8fd75e12 4919 kunmap_atomic(kaddr);
daea3e73
AK		 4920 kvm_release_page_dirty(page);
4921
4922 if (!exchanged)
4923 return X86EMUL_CMPXCHG_FAILED;
4924
54bf36aa 4925 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4926 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4927
4928 return X86EMUL_CONTINUE;
4a5f48f6 4929
3200f405 4930emul_write:
daea3e73 4931 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4932
0f65dd70 4933 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4934}
4935
cf8f70bf
GN		 4936static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4937{
cbfc6c91 4938 int r = 0, i;
cf8f70bf 4939
cbfc6c91
WL		 4940 for (i = 0; i < vcpu->arch.pio.count; i++) {
4941 if (vcpu->arch.pio.in)
4942 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4943 vcpu->arch.pio.size, pd);
4944 else
4945 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4946 vcpu->arch.pio.port, vcpu->arch.pio.size,
4947 pd);
4948 if (r)
4949 break;
4950 pd += vcpu->arch.pio.size;
4951 }
cf8f70bf
GN		 4952 return r;
4953}
4954
6f6fbe98
XG		 4955static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4956 unsigned short port, void *val,
4957 unsigned int count, bool in)
cf8f70bf 4958{
cf8f70bf 4959 vcpu->arch.pio.port = port;
6f6fbe98 4960 vcpu->arch.pio.in = in;
7972995b 4961 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4962 vcpu->arch.pio.size = size;
4963
4964 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4965 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4966 return 1;
4967 }
4968
4969 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4970 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4971 vcpu->run->io.size = size;
4972 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4973 vcpu->run->io.count = count;
4974 vcpu->run->io.port = port;
4975
4976 return 0;
4977}
4978
6f6fbe98
XG		 4979static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4980 int size, unsigned short port, void *val,
4981 unsigned int count)
cf8f70bf 4982{
ca1d4a9e 4983 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4984 int ret;
ca1d4a9e 4985
6f6fbe98
XG		 4986 if (vcpu->arch.pio.count)
4987 goto data_avail;
cf8f70bf 4988
cbfc6c91
WL		 4989 memset(vcpu->arch.pio_data, 0, size * count);
4990
6f6fbe98
XG		 4991 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4992 if (ret) {
4993data_avail:
4994 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4995 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4996 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4997 return 1;
4998 }
4999
cf8f70bf
GN		 5000 return 0;
5001}
5002
6f6fbe98
XG		 5003static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5004 int size, unsigned short port,
5005 const void *val, unsigned int count)
5006{
5007 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5008
5009 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5010 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5011 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5012}
5013
bbd9b64e
CO		 5014static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5015{
5016 return kvm_x86_ops->get_segment_base(vcpu, seg);
5017}
5018
3cb16fe7 5019static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5020{
3cb16fe7 5021 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5022}
5023
ae6a2375 5024static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5025{
5026 if (!need_emulate_wbinvd(vcpu))
5027 return X86EMUL_CONTINUE;
5028
5029 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5030 int cpu = get_cpu();
5031
5032 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5033 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5034 wbinvd_ipi, NULL, 1);
2eec7343 5035 put_cpu();
f5f48ee1 5036 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5037 } else
5038 wbinvd();
f5f48ee1
SY		 5039 return X86EMUL_CONTINUE;
5040}
5cb56059
JS		 5041
5042int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5043{
6affcbed
KH		 5044 kvm_emulate_wbinvd_noskip(vcpu);
5045 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5046}
f5f48ee1
SY		 5047EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5048
5cb56059
JS		 5049
5050
bcaf5cc5
AK		 5051static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5052{
5cb56059 5053 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5054}
5055
52eb5a6d
XL		 5056static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5057 unsigned long *dest)
bbd9b64e 5058{
16f8a6f9 5059 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5060}
5061
52eb5a6d
XL		 5062static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5063 unsigned long value)
bbd9b64e 5064{
338dbc97 5065
717746e3 5066 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5067}
5068
52a46617 5069static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5070{
52a46617 5071 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5072}
5073
717746e3 5074static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5075{
717746e3 5076 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5077 unsigned long value;
5078
5079 switch (cr) {
5080 case 0:
5081 value = kvm_read_cr0(vcpu);
5082 break;
5083 case 2:
5084 value = vcpu->arch.cr2;
5085 break;
5086 case 3:
9f8fe504 5087 value = kvm_read_cr3(vcpu);
52a46617
GN		 5088 break;
5089 case 4:
5090 value = kvm_read_cr4(vcpu);
5091 break;
5092 case 8:
5093 value = kvm_get_cr8(vcpu);
5094 break;
5095 default:
a737f256 5096 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5097 return 0;
5098 }
5099
5100 return value;
5101}
5102
717746e3 5103static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5104{
717746e3 5105 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5106 int res = 0;
5107
52a46617
GN		 5108 switch (cr) {
5109 case 0:
49a9b07e 5110 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5111 break;
5112 case 2:
5113 vcpu->arch.cr2 = val;
5114 break;
5115 case 3:
2390218b 5116 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5117 break;
5118 case 4:
a83b29c6 5119 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5120 break;
5121 case 8:
eea1cff9 5122 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5123 break;
5124 default:
a737f256 5125 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5126 res = -1;
52a46617 5127 }
0f12244f
GN		 5128
5129 return res;
52a46617
GN		 5130}
5131
717746e3 5132static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5133{
717746e3 5134 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5135}
5136
4bff1e86 5137static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5138{
4bff1e86 5139 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5140}
5141
4bff1e86 5142static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5143{
4bff1e86 5144 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5145}
5146
1ac9d0cf
AK		 5147static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5148{
5149 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5150}
5151
5152static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5153{
5154 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5155}
5156
4bff1e86
AK		 5157static unsigned long emulator_get_cached_segment_base(
5158 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5159{
4bff1e86 5160 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5161}
5162
1aa36616
AK		 5163static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5164 struct desc_struct *desc, u32 *base3,
5165 int seg)
2dafc6c2
GN		 5166{
5167 struct kvm_segment var;
5168
4bff1e86 5169 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5170 *selector = var.selector;
2dafc6c2 5171
378a8b09
GN		 5172 if (var.unusable) {
5173 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5174 if (base3)
5175 *base3 = 0;
2dafc6c2 5176 return false;
378a8b09 5177 }
2dafc6c2
GN		 5178
5179 if (var.g)
5180 var.limit >>= 12;
5181 set_desc_limit(desc, var.limit);
5182 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5183#ifdef CONFIG_X86_64
5184 if (base3)
5185 *base3 = var.base >> 32;
5186#endif
2dafc6c2
GN		 5187 desc->type = var.type;
5188 desc->s = var.s;
5189 desc->dpl = var.dpl;
5190 desc->p = var.present;
5191 desc->avl = var.avl;
5192 desc->l = var.l;
5193 desc->d = var.db;
5194 desc->g = var.g;
5195
5196 return true;
5197}
5198
1aa36616
AK		 5199static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5200 struct desc_struct *desc, u32 base3,
5201 int seg)
2dafc6c2 5202{
4bff1e86 5203 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5204 struct kvm_segment var;
5205
1aa36616 5206 var.selector = selector;
2dafc6c2 5207 var.base = get_desc_base(desc);
5601d05b
GN		 5208#ifdef CONFIG_X86_64
5209 var.base |= ((u64)base3) << 32;
5210#endif
2dafc6c2
GN		 5211 var.limit = get_desc_limit(desc);
5212 if (desc->g)
5213 var.limit = (var.limit << 12) | 0xfff;
5214 var.type = desc->type;
2dafc6c2
GN		 5215 var.dpl = desc->dpl;
5216 var.db = desc->d;
5217 var.s = desc->s;
5218 var.l = desc->l;
5219 var.g = desc->g;
5220 var.avl = desc->avl;
5221 var.present = desc->p;
5222 var.unusable = !var.present;
5223 var.padding = 0;
5224
5225 kvm_set_segment(vcpu, &var, seg);
5226 return;
5227}
5228
717746e3
AK		 5229static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5230 u32 msr_index, u64 *pdata)
5231{
609e36d3
PB		 5232 struct msr_data msr;
5233 int r;
5234
5235 msr.index = msr_index;
5236 msr.host_initiated = false;
5237 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5238 if (r)
5239 return r;
5240
5241 *pdata = msr.data;
5242 return 0;
717746e3
AK		 5243}
5244
5245static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5246 u32 msr_index, u64 data)
5247{
8fe8ab46
WA		 5248 struct msr_data msr;
5249
5250 msr.data = data;
5251 msr.index = msr_index;
5252 msr.host_initiated = false;
5253 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5254}
5255
64d60670
PB		 5256static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5257{
5258 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5259
5260 return vcpu->arch.smbase;
5261}
5262
5263static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5264{
5265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5266
5267 vcpu->arch.smbase = smbase;
5268}
5269
67f4d428
NA		 5270static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5271 u32 pmc)
5272{
c6702c9d 5273 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5274}
5275
222d21aa
AK		 5276static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5277 u32 pmc, u64 *pdata)
5278{
c6702c9d 5279 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5280}
5281
6c3287f7
AK		 5282static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5283{
5284 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5285}
5286
2953538e 5287static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5288 struct x86_instruction_info *info,
c4f035c6
AK		 5289 enum x86_intercept_stage stage)
5290{
2953538e 5291 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5292}
5293
e911eb3b
YZ		 5294static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5295 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5296{
e911eb3b 5297 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5298}
5299
dd856efa
AK		 5300static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5301{
5302 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5303}
5304
5305static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5306{
5307 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5308}
5309
801806d9
NA		 5310static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5311{
5312 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5313}
5314
6ed071f0
LP		 5315static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5316{
5317 return emul_to_vcpu(ctxt)->arch.hflags;
5318}
5319
5320static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5321{
5322 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5323}
5324
0234bf88
LP		 5325static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5326{
5327 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5328}
5329
0225fb50 5330static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5331 .read_gpr = emulator_read_gpr,
5332 .write_gpr = emulator_write_gpr,
1871c602 5333 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5334 .write_std = kvm_write_guest_virt_system,
7a036a6f 5335 .read_phys = kvm_read_guest_phys_system,
1871c602 5336 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5337 .read_emulated = emulator_read_emulated,
5338 .write_emulated = emulator_write_emulated,
5339 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5340 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5341 .pio_in_emulated = emulator_pio_in_emulated,
5342 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5343 .get_segment = emulator_get_segment,
5344 .set_segment = emulator_set_segment,
5951c442 5345 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5346 .get_gdt = emulator_get_gdt,
160ce1f1 5347 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5348 .set_gdt = emulator_set_gdt,
5349 .set_idt = emulator_set_idt,
52a46617
GN		 5350 .get_cr = emulator_get_cr,
5351 .set_cr = emulator_set_cr,
9c537244 5352 .cpl = emulator_get_cpl,
35aa5375
GN		 5353 .get_dr = emulator_get_dr,
5354 .set_dr = emulator_set_dr,
64d60670
PB		 5355 .get_smbase = emulator_get_smbase,
5356 .set_smbase = emulator_set_smbase,
717746e3
AK		 5357 .set_msr = emulator_set_msr,
5358 .get_msr = emulator_get_msr,
67f4d428 5359 .check_pmc = emulator_check_pmc,
222d21aa 5360 .read_pmc = emulator_read_pmc,
6c3287f7 5361 .halt = emulator_halt,
bcaf5cc5 5362 .wbinvd = emulator_wbinvd,
d6aa1000 5363 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5364 .intercept = emulator_intercept,
bdb42f5a 5365 .get_cpuid = emulator_get_cpuid,
801806d9 5366 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5367 .get_hflags = emulator_get_hflags,
5368 .set_hflags = emulator_set_hflags,
0234bf88 5369 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5370};
5371
95cb2295
GN		 5372static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5373{
37ccdcbe 5374 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5375 /*
5376 * an sti; sti; sequence only disable interrupts for the first
5377 * instruction. So, if the last instruction, be it emulated or
5378 * not, left the system with the INT_STI flag enabled, it
5379 * means that the last instruction is an sti. We should not
5380 * leave the flag on in this case. The same goes for mov ss
5381 */
37ccdcbe
PB		 5382 if (int_shadow & mask)
5383 mask = 0;
6addfc42 5384 if (unlikely(int_shadow || mask)) {
95cb2295 5385 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5386 if (!mask)
5387 kvm_make_request(KVM_REQ_EVENT, vcpu);
5388 }
95cb2295
GN		 5389}
5390
ef54bcfe 5391static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5392{
5393 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5394 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5395 return kvm_propagate_fault(vcpu, &ctxt->exception);
5396
5397 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5398 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5399 ctxt->exception.error_code);
54b8486f 5400 else
da9cb575 5401 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5402 return false;
54b8486f
GN		 5403}
5404
8ec4722d
MG		 5405static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5406{
adf52235 5407 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5408 int cs_db, cs_l;
5409
8ec4722d
MG		 5410 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5411
adf52235 5412 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5413 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5414
adf52235
TY		 5415 ctxt->eip = kvm_rip_read(vcpu);
5416 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5417 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5418 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5419 cs_db ? X86EMUL_MODE_PROT32 :
5420 X86EMUL_MODE_PROT16;
a584539b 5421 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5422 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5423 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5424
dd856efa 5425 init_decode_cache(ctxt);
7ae441ea 5426 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5427}
5428
71f9833b 5429int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5430{
9d74191a 5431 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5432 int ret;
5433
5434 init_emulate_ctxt(vcpu);
5435
9dac77fa
AK		 5436 ctxt->op_bytes = 2;
5437 ctxt->ad_bytes = 2;
5438 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5439 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5440
5441 if (ret != X86EMUL_CONTINUE)
5442 return EMULATE_FAIL;
5443
9dac77fa 5444 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5445 kvm_rip_write(vcpu, ctxt->eip);
5446 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5447
5448 if (irq == NMI_VECTOR)
7460fb4a 5449 vcpu->arch.nmi_pending = 0;
63995653
MG		 5450 else
5451 vcpu->arch.interrupt.pending = false;
5452
5453 return EMULATE_DONE;
5454}
5455EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5456
6d77dbfc
GN		 5457static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5458{
fc3a9157
JR		 5459 int r = EMULATE_DONE;
5460
6d77dbfc
GN		 5461 ++vcpu->stat.insn_emulation_fail;
5462 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5463 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5464 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5465 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5466 vcpu->run->internal.ndata = 0;
1f4dcb3b 5467 r = EMULATE_USER_EXIT;
fc3a9157 5468 }
6d77dbfc 5469 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5470
5471 return r;
6d77dbfc
GN		 5472}
5473
93c05d3e 5474static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5475 bool write_fault_to_shadow_pgtable,
5476 int emulation_type)
a6f177ef 5477{
95b3cf69 5478 gpa_t gpa = cr2;
ba049e93 5479 kvm_pfn_t pfn;
a6f177ef 5480
991eebf9
GN		 5481 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5482 return false;
5483
95b3cf69
XG		 5484 if (!vcpu->arch.mmu.direct_map) {
5485 /*
5486 * Write permission should be allowed since only
5487 * write access need to be emulated.
5488 */
5489 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5490
95b3cf69
XG		 5491 /*
5492 * If the mapping is invalid in guest, let cpu retry
5493 * it to generate fault.
5494 */
5495 if (gpa == UNMAPPED_GVA)
5496 return true;
5497 }
a6f177ef 5498
8e3d9d06
XG		 5499 /*
5500 * Do not retry the unhandleable instruction if it faults on the
5501 * readonly host memory, otherwise it will goto a infinite loop:
5502 * retry instruction -> write #PF -> emulation fail -> retry
5503 * instruction -> ...
5504 */
5505 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5506
5507 /*
5508 * If the instruction failed on the error pfn, it can not be fixed,
5509 * report the error to userspace.
5510 */
5511 if (is_error_noslot_pfn(pfn))
5512 return false;
5513
5514 kvm_release_pfn_clean(pfn);
5515
5516 /* The instructions are well-emulated on direct mmu. */
5517 if (vcpu->arch.mmu.direct_map) {
5518 unsigned int indirect_shadow_pages;
5519
5520 spin_lock(&vcpu->kvm->mmu_lock);
5521 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5522 spin_unlock(&vcpu->kvm->mmu_lock);
5523
5524 if (indirect_shadow_pages)
5525 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5526
a6f177ef 5527 return true;
8e3d9d06 5528 }
a6f177ef 5529
95b3cf69
XG		 5530 /*
5531 * if emulation was due to access to shadowed page table
5532 * and it failed try to unshadow page and re-enter the
5533 * guest to let CPU execute the instruction.
5534 */
5535 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5536
5537 /*
5538 * If the access faults on its page table, it can not
5539 * be fixed by unprotecting shadow page and it should
5540 * be reported to userspace.
5541 */
5542 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5543}
5544
1cb3f3ae
XG		 5545static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5546 unsigned long cr2, int emulation_type)
5547{
5548 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5549 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5550
5551 last_retry_eip = vcpu->arch.last_retry_eip;
5552 last_retry_addr = vcpu->arch.last_retry_addr;
5553
5554 /*
5555 * If the emulation is caused by #PF and it is non-page_table
5556 * writing instruction, it means the VM-EXIT is caused by shadow
5557 * page protected, we can zap the shadow page and retry this
5558 * instruction directly.
5559 *
5560 * Note: if the guest uses a non-page-table modifying instruction
5561 * on the PDE that points to the instruction, then we will unmap
5562 * the instruction and go to an infinite loop. So, we cache the
5563 * last retried eip and the last fault address, if we meet the eip
5564 * and the address again, we can break out of the potential infinite
5565 * loop.
5566 */
5567 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5568
5569 if (!(emulation_type & EMULTYPE_RETRY))
5570 return false;
5571
5572 if (x86_page_table_writing_insn(ctxt))
5573 return false;
5574
5575 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5576 return false;
5577
5578 vcpu->arch.last_retry_eip = ctxt->eip;
5579 vcpu->arch.last_retry_addr = cr2;
5580
5581 if (!vcpu->arch.mmu.direct_map)
5582 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5583
22368028 5584 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5585
5586 return true;
5587}
5588
716d51ab
GN		 5589static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5590static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5591
64d60670 5592static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5593{
64d60670 5594 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5595 /* This is a good place to trace that we are exiting SMM. */
5596 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5597
c43203ca
PB		 5598 /* Process a latched INIT or SMI, if any. */
5599 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5600 }
699023e2
PB		 5601
5602 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5603}
5604
5605static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5606{
5607 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5608
a584539b 5609 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5610
5611 if (changed & HF_SMM_MASK)
5612 kvm_smm_changed(vcpu);
a584539b
PB		 5613}
5614
4a1e10d5
PB		 5615static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5616 unsigned long *db)
5617{
5618 u32 dr6 = 0;
5619 int i;
5620 u32 enable, rwlen;
5621
5622 enable = dr7;
5623 rwlen = dr7 >> 16;
5624 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5625 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5626 dr6 |= (1 << i);
5627 return dr6;
5628}
5629
c8401dda 5630static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5631{
5632 struct kvm_run *kvm_run = vcpu->run;
5633
c8401dda
PB		 5634 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5635 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5636 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5637 kvm_run->debug.arch.exception = DB_VECTOR;
5638 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5639 *r = EMULATE_USER_EXIT;
5640 } else {
5641 /*
5642 * "Certain debug exceptions may clear bit 0-3. The
5643 * remaining contents of the DR6 register are never
5644 * cleared by the processor".
5645 */
5646 vcpu->arch.dr6 &= ~15;
5647 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5648 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5649 }
5650}
5651
6affcbed
KH		 5652int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5653{
5654 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5655 int r = EMULATE_DONE;
5656
5657 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5658
5659 /*
5660 * rflags is the old, "raw" value of the flags. The new value has
5661 * not been saved yet.
5662 *
5663 * This is correct even for TF set by the guest, because "the
5664 * processor will not generate this exception after the instruction
5665 * that sets the TF flag".
5666 */
5667 if (unlikely(rflags & X86_EFLAGS_TF))
5668 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5669 return r == EMULATE_DONE;
5670}
5671EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5672
4a1e10d5
PB		 5673static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5674{
4a1e10d5
PB		 5675 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5676 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5677 struct kvm_run *kvm_run = vcpu->run;
5678 unsigned long eip = kvm_get_linear_rip(vcpu);
5679 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5680 vcpu->arch.guest_debug_dr7,
5681 vcpu->arch.eff_db);
5682
5683 if (dr6 != 0) {
6f43ed01 5684 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5685 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5686 kvm_run->debug.arch.exception = DB_VECTOR;
5687 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5688 *r = EMULATE_USER_EXIT;
5689 return true;
5690 }
5691 }
5692
4161a569
NA		 5693 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5694 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5695 unsigned long eip = kvm_get_linear_rip(vcpu);
5696 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5697 vcpu->arch.dr7,
5698 vcpu->arch.db);
5699
5700 if (dr6 != 0) {
5701 vcpu->arch.dr6 &= ~15;
6f43ed01 5702 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5703 kvm_queue_exception(vcpu, DB_VECTOR);
5704 *r = EMULATE_DONE;
5705 return true;
5706 }
5707 }
5708
5709 return false;
5710}
5711
51d8b661
AP		 5712int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5713 unsigned long cr2,
dc25e89e
AP		 5714 int emulation_type,
5715 void *insn,
5716 int insn_len)
bbd9b64e 5717{
95cb2295 5718 int r;
9d74191a 5719 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5720 bool writeback = true;
93c05d3e 5721 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5722
93c05d3e
XG		 5723 /*
5724 * Clear write_fault_to_shadow_pgtable here to ensure it is
5725 * never reused.
5726 */
5727 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5728 kvm_clear_exception_queue(vcpu);
8d7d8102 5729
571008da 5730 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5731 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5732
5733 /*
5734 * We will reenter on the same instruction since
5735 * we do not set complete_userspace_io. This does not
5736 * handle watchpoints yet, those would be handled in
5737 * the emulate_ops.
5738 */
5739 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5740 return r;
5741
9d74191a
TY		 5742 ctxt->interruptibility = 0;
5743 ctxt->have_exception = false;
e0ad0b47 5744 ctxt->exception.vector = -1;
9d74191a 5745 ctxt->perm_ok = false;
bbd9b64e 5746
b51e974f 5747 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5748
9d74191a 5749 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5750
e46479f8 5751 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5752 ++vcpu->stat.insn_emulation;
1d2887e2 5753 if (r != EMULATION_OK) {
4005996e
AK		 5754 if (emulation_type & EMULTYPE_TRAP_UD)
5755 return EMULATE_FAIL;
991eebf9
GN		 5756 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5757 emulation_type))
bbd9b64e 5758 return EMULATE_DONE;
6ea6e843
PB		 5759 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5760 return EMULATE_DONE;
6d77dbfc
GN		 5761 if (emulation_type & EMULTYPE_SKIP)
5762 return EMULATE_FAIL;
5763 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5764 }
5765 }
5766
ba8afb6b 5767 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5768 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5769 if (ctxt->eflags & X86_EFLAGS_RF)
5770 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5771 return EMULATE_DONE;
5772 }
5773
1cb3f3ae
XG		 5774 if (retry_instruction(ctxt, cr2, emulation_type))
5775 return EMULATE_DONE;
5776
7ae441ea 5777 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5778 changes registers values during IO operation */
7ae441ea
GN		 5779 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5780 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5781 emulator_invalidate_register_cache(ctxt);
7ae441ea 5782 }
4d2179e1 5783
5cd21917 5784restart:
0f89b207
TL		 5785 /* Save the faulting GPA (cr2) in the address field */
5786 ctxt->exception.address = cr2;
5787
9d74191a 5788 r = x86_emulate_insn(ctxt);
bbd9b64e 5789
775fde86
JR		 5790 if (r == EMULATION_INTERCEPTED)
5791 return EMULATE_DONE;
5792
d2ddd1c4 5793 if (r == EMULATION_FAILED) {
991eebf9
GN		 5794 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5795 emulation_type))
c3cd7ffa
GN		 5796 return EMULATE_DONE;
5797
6d77dbfc 5798 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5799 }
5800
9d74191a 5801 if (ctxt->have_exception) {
d2ddd1c4 5802 r = EMULATE_DONE;
ef54bcfe
PB		 5803 if (inject_emulated_exception(vcpu))
5804 return r;
d2ddd1c4 5805 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5806 if (!vcpu->arch.pio.in) {
5807 /* FIXME: return into emulator if single-stepping. */
3457e419 5808 vcpu->arch.pio.count = 0;
0912c977 5809 } else {
7ae441ea 5810 writeback = false;
716d51ab
GN		 5811 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5812 }
ac0a48c3 5813 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5814 } else if (vcpu->mmio_needed) {
5815 if (!vcpu->mmio_is_write)
5816 writeback = false;
ac0a48c3 5817 r = EMULATE_USER_EXIT;
716d51ab 5818 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5819 } else if (r == EMULATION_RESTART)
5cd21917 5820 goto restart;
d2ddd1c4
GN		 5821 else
5822 r = EMULATE_DONE;
f850e2e6 5823
7ae441ea 5824 if (writeback) {
6addfc42 5825 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5826 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5827 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5828 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5829 if (r == EMULATE_DONE &&
5830 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5831 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5832 if (!ctxt->have_exception ||
5833 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5834 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5835
5836 /*
5837 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5838 * do nothing, and it will be requested again as soon as
5839 * the shadow expires. But we still need to check here,
5840 * because POPF has no interrupt shadow.
5841 */
5842 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5843 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5844 } else
5845 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5846
5847 return r;
de7d789a 5848}
51d8b661 5849EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5850
cf8f70bf 5851int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5852{
cf8f70bf 5853 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5854 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5855 size, port, &val, 1);
cf8f70bf 5856 /* do not return to emulator after return from userspace */
7972995b 5857 vcpu->arch.pio.count = 0;
de7d789a
CO		 5858 return ret;
5859}
cf8f70bf 5860EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5861
8370c3d0
TL		 5862static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5863{
5864 unsigned long val;
5865
5866 /* We should only ever be called with arch.pio.count equal to 1 */
5867 BUG_ON(vcpu->arch.pio.count != 1);
5868
5869 /* For size less than 4 we merge, else we zero extend */
5870 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5871 : 0;
5872
5873 /*
5874 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5875 * the copy and tracing
5876 */
5877 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5878 vcpu->arch.pio.port, &val, 1);
5879 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5880
5881 return 1;
5882}
5883
5884int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5885{
5886 unsigned long val;
5887 int ret;
5888
5889 /* For size less than 4 we merge, else we zero extend */
5890 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5891
5892 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5893 &val, 1);
5894 if (ret) {
5895 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5896 return ret;
5897 }
5898
5899 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5900
5901 return 0;
5902}
5903EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5904
251a5fd6 5905static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5906{
0a3aee0d 5907 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5908 return 0;
8cfdc000
ZA		 5909}
5910
5911static void tsc_khz_changed(void *data)
c8076604 5912{
8cfdc000
ZA		 5913 struct cpufreq_freqs *freq = data;
5914 unsigned long khz = 0;
5915
5916 if (data)
5917 khz = freq->new;
5918 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5919 khz = cpufreq_quick_get(raw_smp_processor_id());
5920 if (!khz)
5921 khz = tsc_khz;
0a3aee0d 5922 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5923}
5924
c8076604
GH		 5925static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5926 void *data)
5927{
5928 struct cpufreq_freqs *freq = data;
5929 struct kvm *kvm;
5930 struct kvm_vcpu *vcpu;
5931 int i, send_ipi = 0;
5932
8cfdc000
ZA		 5933 /*
5934 * We allow guests to temporarily run on slowing clocks,
5935 * provided we notify them after, or to run on accelerating
5936 * clocks, provided we notify them before. Thus time never
5937 * goes backwards.
5938 *
5939 * However, we have a problem. We can't atomically update
5940 * the frequency of a given CPU from this function; it is
5941 * merely a notifier, which can be called from any CPU.
5942 * Changing the TSC frequency at arbitrary points in time
5943 * requires a recomputation of local variables related to
5944 * the TSC for each VCPU. We must flag these local variables
5945 * to be updated and be sure the update takes place with the
5946 * new frequency before any guests proceed.
5947 *
5948 * Unfortunately, the combination of hotplug CPU and frequency
5949 * change creates an intractable locking scenario; the order
5950 * of when these callouts happen is undefined with respect to
5951 * CPU hotplug, and they can race with each other. As such,
5952 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5953 * undefined; you can actually have a CPU frequency change take
5954 * place in between the computation of X and the setting of the
5955 * variable. To protect against this problem, all updates of
5956 * the per_cpu tsc_khz variable are done in an interrupt
5957 * protected IPI, and all callers wishing to update the value
5958 * must wait for a synchronous IPI to complete (which is trivial
5959 * if the caller is on the CPU already). This establishes the
5960 * necessary total order on variable updates.
5961 *
5962 * Note that because a guest time update may take place
5963 * anytime after the setting of the VCPU's request bit, the
5964 * correct TSC value must be set before the request. However,
5965 * to ensure the update actually makes it to any guest which
5966 * starts running in hardware virtualization between the set
5967 * and the acquisition of the spinlock, we must also ping the
5968 * CPU after setting the request bit.
5969 *
5970 */
5971
c8076604
GH		 5972 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5973 return 0;
5974 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5975 return 0;
8cfdc000
ZA		 5976
5977 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5978
2f303b74 5979 spin_lock(&kvm_lock);
c8076604 5980 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5981 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5982 if (vcpu->cpu != freq->cpu)
5983 continue;
c285545f 5984 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5985 if (vcpu->cpu != smp_processor_id())
8cfdc000 5986 send_ipi = 1;
c8076604
GH		 5987 }
5988 }
2f303b74 5989 spin_unlock(&kvm_lock);
c8076604
GH		 5990
5991 if (freq->old < freq->new && send_ipi) {
5992 /*
5993 * We upscale the frequency. Must make the guest
5994 * doesn't see old kvmclock values while running with
5995 * the new frequency, otherwise we risk the guest sees
5996 * time go backwards.
5997 *
5998 * In case we update the frequency for another cpu
5999 * (which might be in guest context) send an interrupt
6000 * to kick the cpu out of guest context. Next time
6001 * guest context is entered kvmclock will be updated,
6002 * so the guest will not see stale values.
6003 */
8cfdc000 6004 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6005 }
6006 return 0;
6007}
6008
6009static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6010 .notifier_call = kvmclock_cpufreq_notifier
6011};
6012
251a5fd6 6013static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6014{
251a5fd6
SAS		 6015 tsc_khz_changed(NULL);
6016 return 0;
8cfdc000
ZA		 6017}
6018
b820cc0c
ZA		 6019static void kvm_timer_init(void)
6020{
c285545f 6021 max_tsc_khz = tsc_khz;
460dd42e 6022
b820cc0c 6023 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6024#ifdef CONFIG_CPU_FREQ
6025 struct cpufreq_policy policy;
758f588d
BP		 6026 int cpu;
6027
c285545f 6028 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6029 cpu = get_cpu();
6030 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6031 if (policy.cpuinfo.max_freq)
6032 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6033 put_cpu();
c285545f 6034#endif
b820cc0c
ZA		 6035 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6036 CPUFREQ_TRANSITION_NOTIFIER);
6037 }
c285545f 6038 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6039
73c1b41e 6040 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6041 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6042}
6043
ff9d07a0
ZY		 6044static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6045
f5132b01 6046int kvm_is_in_guest(void)
ff9d07a0 6047{
086c9855 6048 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6049}
6050
6051static int kvm_is_user_mode(void)
6052{
6053 int user_mode = 3;
dcf46b94 6054
086c9855
AS		 6055 if (__this_cpu_read(current_vcpu))
6056 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6057
ff9d07a0
ZY		 6058 return user_mode != 0;
6059}
6060
6061static unsigned long kvm_get_guest_ip(void)
6062{
6063 unsigned long ip = 0;
dcf46b94 6064
086c9855
AS		 6065 if (__this_cpu_read(current_vcpu))
6066 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6067
ff9d07a0
ZY		 6068 return ip;
6069}
6070
6071static struct perf_guest_info_callbacks kvm_guest_cbs = {
6072 .is_in_guest = kvm_is_in_guest,
6073 .is_user_mode = kvm_is_user_mode,
6074 .get_guest_ip = kvm_get_guest_ip,
6075};
6076
6077void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6078{
086c9855 6079 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6080}
6081EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6082
6083void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6084{
086c9855 6085 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6086}
6087EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6088
ce88decf
XG		 6089static void kvm_set_mmio_spte_mask(void)
6090{
6091 u64 mask;
6092 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6093
6094 /*
6095 * Set the reserved bits and the present bit of an paging-structure
6096 * entry to generate page fault with PFER.RSV = 1.
6097 */
885032b9 6098 /* Mask the reserved physical address bits. */
d1431483 6099 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6100
885032b9 6101 /* Set the present bit. */
ce88decf
XG		 6102 mask |= 1ull;
6103
6104#ifdef CONFIG_X86_64
6105 /*
6106 * If reserved bit is not supported, clear the present bit to disable
6107 * mmio page fault.
6108 */
6109 if (maxphyaddr == 52)
6110 mask &= ~1ull;
6111#endif
6112
dcdca5fe 6113 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6114}
6115
16e8d74d
MT		 6116#ifdef CONFIG_X86_64
6117static void pvclock_gtod_update_fn(struct work_struct *work)
6118{
d828199e
MT		 6119 struct kvm *kvm;
6120
6121 struct kvm_vcpu *vcpu;
6122 int i;
6123
2f303b74 6124 spin_lock(&kvm_lock);
d828199e
MT		 6125 list_for_each_entry(kvm, &vm_list, vm_list)
6126 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6127 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6128 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6129 spin_unlock(&kvm_lock);
16e8d74d
MT		 6130}
6131
6132static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6133
6134/*
6135 * Notification about pvclock gtod data update.
6136 */
6137static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6138 void *priv)
6139{
6140 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6141 struct timekeeper *tk = priv;
6142
6143 update_pvclock_gtod(tk);
6144
6145 /* disable master clock if host does not trust, or does not
6146 * use, TSC clocksource
6147 */
6148 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6149 atomic_read(&kvm_guest_has_master_clock) != 0)
6150 queue_work(system_long_wq, &pvclock_gtod_work);
6151
6152 return 0;
6153}
6154
6155static struct notifier_block pvclock_gtod_notifier = {
6156 .notifier_call = pvclock_gtod_notify,
6157};
6158#endif
6159
f8c16bba 6160int kvm_arch_init(void *opaque)
043405e1 6161{
b820cc0c 6162 int r;
6b61edf7 6163 struct kvm_x86_ops *ops = opaque;
f8c16bba 6164
f8c16bba
ZX		 6165 if (kvm_x86_ops) {
6166 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6167 r = -EEXIST;
6168 goto out;
f8c16bba
ZX		 6169 }
6170
6171 if (!ops->cpu_has_kvm_support()) {
6172 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6173 r = -EOPNOTSUPP;
6174 goto out;
f8c16bba
ZX		 6175 }
6176 if (ops->disabled_by_bios()) {
6177 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6178 r = -EOPNOTSUPP;
6179 goto out;
f8c16bba
ZX		 6180 }
6181
013f6a5d
MT		 6182 r = -ENOMEM;
6183 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6184 if (!shared_msrs) {
6185 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6186 goto out;
6187 }
6188
97db56ce
AK		 6189 r = kvm_mmu_module_init();
6190 if (r)
013f6a5d 6191 goto out_free_percpu;
97db56ce 6192
ce88decf 6193 kvm_set_mmio_spte_mask();
97db56ce 6194
f8c16bba 6195 kvm_x86_ops = ops;
920c8377 6196
7b52345e 6197 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6198 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6199 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6200 kvm_timer_init();
c8076604 6201
ff9d07a0
ZY		 6202 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6203
d366bf7e 6204 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6205 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6206
c5cc421b 6207 kvm_lapic_init();
16e8d74d
MT		 6208#ifdef CONFIG_X86_64
6209 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6210#endif
6211
f8c16bba 6212 return 0;
56c6d28a 6213
013f6a5d
MT		 6214out_free_percpu:
6215 free_percpu(shared_msrs);
56c6d28a 6216out:
56c6d28a 6217 return r;
043405e1 6218}
8776e519 6219
f8c16bba
ZX		 6220void kvm_arch_exit(void)
6221{
cef84c30 6222 kvm_lapic_exit();
ff9d07a0
ZY		 6223 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6224
888d256e
JK		 6225 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6226 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6227 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6228 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6229#ifdef CONFIG_X86_64
6230 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6231#endif
f8c16bba 6232 kvm_x86_ops = NULL;
56c6d28a 6233 kvm_mmu_module_exit();
013f6a5d 6234 free_percpu(shared_msrs);
56c6d28a 6235}
f8c16bba 6236
5cb56059 6237int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6238{
6239 ++vcpu->stat.halt_exits;
35754c98 6240 if (lapic_in_kernel(vcpu)) {
a4535290 6241 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6242 return 1;
6243 } else {
6244 vcpu->run->exit_reason = KVM_EXIT_HLT;
6245 return 0;
6246 }
6247}
5cb56059
JS		 6248EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6249
6250int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6251{
6affcbed
KH		 6252 int ret = kvm_skip_emulated_instruction(vcpu);
6253 /*
6254 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6255 * KVM_EXIT_DEBUG here.
6256 */
6257 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6258}
8776e519
HB		 6259EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6260
8ef81a9a 6261#ifdef CONFIG_X86_64
55dd00a7
MT		 6262static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6263 unsigned long clock_type)
6264{
6265 struct kvm_clock_pairing clock_pairing;
6266 struct timespec ts;
80fbd89c 6267 u64 cycle;
55dd00a7
MT		 6268 int ret;
6269
6270 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6271 return -KVM_EOPNOTSUPP;
6272
6273 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6274 return -KVM_EOPNOTSUPP;
6275
6276 clock_pairing.sec = ts.tv_sec;
6277 clock_pairing.nsec = ts.tv_nsec;
6278 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6279 clock_pairing.flags = 0;
6280
6281 ret = 0;
6282 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6283 sizeof(struct kvm_clock_pairing)))
6284 ret = -KVM_EFAULT;
6285
6286 return ret;
6287}
8ef81a9a 6288#endif
55dd00a7 6289
6aef266c
SV		 6290/*
6291 * kvm_pv_kick_cpu_op: Kick a vcpu.
6292 *
6293 * @apicid - apicid of vcpu to be kicked.
6294 */
6295static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6296{
24d2166b 6297 struct kvm_lapic_irq lapic_irq;
6aef266c 6298
24d2166b
R		 6299 lapic_irq.shorthand = 0;
6300 lapic_irq.dest_mode = 0;
ebd28fcb 6301 lapic_irq.level = 0;
24d2166b 6302 lapic_irq.dest_id = apicid;
93bbf0b8 6303 lapic_irq.msi_redir_hint = false;
6aef266c 6304
24d2166b 6305 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6306 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6307}
6308
d62caabb
AS		 6309void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6310{
6311 vcpu->arch.apicv_active = false;
6312 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6313}
6314
8776e519
HB		 6315int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6316{
6317 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6318 int op_64_bit, r;
8776e519 6319
6affcbed 6320 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6321
55cd8e5a
GN		 6322 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6323 return kvm_hv_hypercall(vcpu);
6324
5fdbf976
MT		 6325 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6326 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6327 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6328 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6329 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6330
229456fc 6331 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6332
a449c7aa
NA		 6333 op_64_bit = is_64_bit_mode(vcpu);
6334 if (!op_64_bit) {
8776e519
HB		 6335 nr &= 0xFFFFFFFF;
6336 a0 &= 0xFFFFFFFF;
6337 a1 &= 0xFFFFFFFF;
6338 a2 &= 0xFFFFFFFF;
6339 a3 &= 0xFFFFFFFF;
6340 }
6341
07708c4a
JK		 6342 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6343 ret = -KVM_EPERM;
6344 goto out;
6345 }
6346
8776e519 6347 switch (nr) {
b93463aa
AK		 6348 case KVM_HC_VAPIC_POLL_IRQ:
6349 ret = 0;
6350 break;
6aef266c
SV		 6351 case KVM_HC_KICK_CPU:
6352 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6353 ret = 0;
6354 break;
8ef81a9a 6355#ifdef CONFIG_X86_64
55dd00a7
MT		 6356 case KVM_HC_CLOCK_PAIRING:
6357 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6358 break;
8ef81a9a 6359#endif
8776e519
HB		 6360 default:
6361 ret = -KVM_ENOSYS;
6362 break;
6363 }
07708c4a 6364out:
a449c7aa
NA		 6365 if (!op_64_bit)
6366 ret = (u32)ret;
5fdbf976 6367 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6368 ++vcpu->stat.hypercalls;
2f333bcb 6369 return r;
8776e519
HB		 6370}
6371EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6372
b6785def 6373static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6374{
d6aa1000 6375 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6376 char instruction[3];
5fdbf976 6377 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6378
8776e519 6379 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6380
ce2e852e
DV		 6381 return emulator_write_emulated(ctxt, rip, instruction, 3,
6382 &ctxt->exception);
8776e519
HB		 6383}
6384
851ba692 6385static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6386{
782d422b
MG		 6387 return vcpu->run->request_interrupt_window &&
6388 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6389}
6390
851ba692 6391static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6392{
851ba692
AK		 6393 struct kvm_run *kvm_run = vcpu->run;
6394
91586a3b 6395 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6396 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6397 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6398 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6399 kvm_run->ready_for_interrupt_injection =
6400 pic_in_kernel(vcpu->kvm) ||
782d422b 6401 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6402}
6403
95ba8273
GN		 6404static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6405{
6406 int max_irr, tpr;
6407
6408 if (!kvm_x86_ops->update_cr8_intercept)
6409 return;
6410
bce87cce 6411 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6412 return;
6413
d62caabb
AS		 6414 if (vcpu->arch.apicv_active)
6415 return;
6416
8db3baa2
GN		 6417 if (!vcpu->arch.apic->vapic_addr)
6418 max_irr = kvm_lapic_find_highest_irr(vcpu);
6419 else
6420 max_irr = -1;
95ba8273
GN		 6421
6422 if (max_irr != -1)
6423 max_irr >>= 4;
6424
6425 tpr = kvm_lapic_get_cr8(vcpu);
6426
6427 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6428}
6429
b6b8a145 6430static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6431{
b6b8a145
JK		 6432 int r;
6433
95ba8273 6434 /* try to reinject previous events if any */
664f8e26
WL		 6435 if (vcpu->arch.exception.injected) {
6436 kvm_x86_ops->queue_exception(vcpu);
6437 return 0;
6438 }
6439
6440 /*
6441 * Exceptions must be injected immediately, or the exception
6442 * frame will have the address of the NMI or interrupt handler.
6443 */
6444 if (!vcpu->arch.exception.pending) {
6445 if (vcpu->arch.nmi_injected) {
6446 kvm_x86_ops->set_nmi(vcpu);
6447 return 0;
6448 }
6449
6450 if (vcpu->arch.interrupt.pending) {
6451 kvm_x86_ops->set_irq(vcpu);
6452 return 0;
6453 }
6454 }
6455
6456 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6457 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6458 if (r != 0)
6459 return r;
6460 }
6461
6462 /* try to inject new event if pending */
b59bb7bd 6463 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6464 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6465 vcpu->arch.exception.has_error_code,
6466 vcpu->arch.exception.error_code);
d6e8c854 6467
664f8e26
WL		 6468 vcpu->arch.exception.pending = false;
6469 vcpu->arch.exception.injected = true;
6470
d6e8c854
NA		 6471 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6472 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6473 X86_EFLAGS_RF);
6474
6bdf0662
NA		 6475 if (vcpu->arch.exception.nr == DB_VECTOR &&
6476 (vcpu->arch.dr7 & DR7_GD)) {
6477 vcpu->arch.dr7 &= ~DR7_GD;
6478 kvm_update_dr7(vcpu);
6479 }
6480
cfcd20e5 6481 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6482 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6483 vcpu->arch.smi_pending = false;
52797bf9 6484 ++vcpu->arch.smi_count;
ee2cd4b7 6485 enter_smm(vcpu);
c43203ca 6486 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6487 --vcpu->arch.nmi_pending;
6488 vcpu->arch.nmi_injected = true;
6489 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6490 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6491 /*
6492 * Because interrupts can be injected asynchronously, we are
6493 * calling check_nested_events again here to avoid a race condition.
6494 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6495 * proposal and current concerns. Perhaps we should be setting
6496 * KVM_REQ_EVENT only on certain events and not unconditionally?
6497 */
6498 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6499 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6500 if (r != 0)
6501 return r;
6502 }
95ba8273 6503 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6504 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6505 false);
6506 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6507 }
6508 }
ee2cd4b7 6509
b6b8a145 6510 return 0;
95ba8273
GN		 6511}
6512
7460fb4a
AK		 6513static void process_nmi(struct kvm_vcpu *vcpu)
6514{
6515 unsigned limit = 2;
6516
6517 /*
6518 * x86 is limited to one NMI running, and one NMI pending after it.
6519 * If an NMI is already in progress, limit further NMIs to just one.
6520 * Otherwise, allow two (and we'll inject the first one immediately).
6521 */
6522 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6523 limit = 1;
6524
6525 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6526 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6527 kvm_make_request(KVM_REQ_EVENT, vcpu);
6528}
6529
ee2cd4b7 6530static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6531{
6532 u32 flags = 0;
6533 flags |= seg->g << 23;
6534 flags |= seg->db << 22;
6535 flags |= seg->l << 21;
6536 flags |= seg->avl << 20;
6537 flags |= seg->present << 15;
6538 flags |= seg->dpl << 13;
6539 flags |= seg->s << 12;
6540 flags |= seg->type << 8;
6541 return flags;
6542}
6543
ee2cd4b7 6544static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6545{
6546 struct kvm_segment seg;
6547 int offset;
6548
6549 kvm_get_segment(vcpu, &seg, n);
6550 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6551
6552 if (n < 3)
6553 offset = 0x7f84 + n * 12;
6554 else
6555 offset = 0x7f2c + (n - 3) * 12;
6556
6557 put_smstate(u32, buf, offset + 8, seg.base);
6558 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6559 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6560}
6561
efbb288a 6562#ifdef CONFIG_X86_64
ee2cd4b7 6563static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6564{
6565 struct kvm_segment seg;
6566 int offset;
6567 u16 flags;
6568
6569 kvm_get_segment(vcpu, &seg, n);
6570 offset = 0x7e00 + n * 16;
6571
ee2cd4b7 6572 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6573 put_smstate(u16, buf, offset, seg.selector);
6574 put_smstate(u16, buf, offset + 2, flags);
6575 put_smstate(u32, buf, offset + 4, seg.limit);
6576 put_smstate(u64, buf, offset + 8, seg.base);
6577}
efbb288a 6578#endif
660a5d51 6579
ee2cd4b7 6580static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6581{
6582 struct desc_ptr dt;
6583 struct kvm_segment seg;
6584 unsigned long val;
6585 int i;
6586
6587 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6588 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6589 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6590 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6591
6592 for (i = 0; i < 8; i++)
6593 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6594
6595 kvm_get_dr(vcpu, 6, &val);
6596 put_smstate(u32, buf, 0x7fcc, (u32)val);
6597 kvm_get_dr(vcpu, 7, &val);
6598 put_smstate(u32, buf, 0x7fc8, (u32)val);
6599
6600 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6601 put_smstate(u32, buf, 0x7fc4, seg.selector);
6602 put_smstate(u32, buf, 0x7f64, seg.base);
6603 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6604 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6605
6606 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6607 put_smstate(u32, buf, 0x7fc0, seg.selector);
6608 put_smstate(u32, buf, 0x7f80, seg.base);
6609 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6610 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6611
6612 kvm_x86_ops->get_gdt(vcpu, &dt);
6613 put_smstate(u32, buf, 0x7f74, dt.address);
6614 put_smstate(u32, buf, 0x7f70, dt.size);
6615
6616 kvm_x86_ops->get_idt(vcpu, &dt);
6617 put_smstate(u32, buf, 0x7f58, dt.address);
6618 put_smstate(u32, buf, 0x7f54, dt.size);
6619
6620 for (i = 0; i < 6; i++)
ee2cd4b7 6621 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6622
6623 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6624
6625 /* revision id */
6626 put_smstate(u32, buf, 0x7efc, 0x00020000);
6627 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6628}
6629
ee2cd4b7 6630static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6631{
6632#ifdef CONFIG_X86_64
6633 struct desc_ptr dt;
6634 struct kvm_segment seg;
6635 unsigned long val;
6636 int i;
6637
6638 for (i = 0; i < 16; i++)
6639 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6640
6641 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6642 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6643
6644 kvm_get_dr(vcpu, 6, &val);
6645 put_smstate(u64, buf, 0x7f68, val);
6646 kvm_get_dr(vcpu, 7, &val);
6647 put_smstate(u64, buf, 0x7f60, val);
6648
6649 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6650 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6651 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6652
6653 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6654
6655 /* revision id */
6656 put_smstate(u32, buf, 0x7efc, 0x00020064);
6657
6658 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6659
6660 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6661 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6662 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6663 put_smstate(u32, buf, 0x7e94, seg.limit);
6664 put_smstate(u64, buf, 0x7e98, seg.base);
6665
6666 kvm_x86_ops->get_idt(vcpu, &dt);
6667 put_smstate(u32, buf, 0x7e84, dt.size);
6668 put_smstate(u64, buf, 0x7e88, dt.address);
6669
6670 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6671 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6672 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6673 put_smstate(u32, buf, 0x7e74, seg.limit);
6674 put_smstate(u64, buf, 0x7e78, seg.base);
6675
6676 kvm_x86_ops->get_gdt(vcpu, &dt);
6677 put_smstate(u32, buf, 0x7e64, dt.size);
6678 put_smstate(u64, buf, 0x7e68, dt.address);
6679
6680 for (i = 0; i < 6; i++)
ee2cd4b7 6681 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6682#else
6683 WARN_ON_ONCE(1);
6684#endif
6685}
6686
ee2cd4b7 6687static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6688{
660a5d51 6689 struct kvm_segment cs, ds;
18c3626e 6690 struct desc_ptr dt;
660a5d51
PB		 6691 char buf[512];
6692 u32 cr0;
6693
660a5d51 6694 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6695 memset(buf, 0, 512);
d6321d49 6696 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6697 enter_smm_save_state_64(vcpu, buf);
660a5d51 6698 else
ee2cd4b7 6699 enter_smm_save_state_32(vcpu, buf);
660a5d51 6700
0234bf88
LP		 6701 /*
6702 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6703 * vCPU state (e.g. leave guest mode) after we've saved the state into
6704 * the SMM state-save area.
6705 */
6706 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6707
6708 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6709 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6710
6711 if (kvm_x86_ops->get_nmi_mask(vcpu))
6712 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6713 else
6714 kvm_x86_ops->set_nmi_mask(vcpu, true);
6715
6716 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6717 kvm_rip_write(vcpu, 0x8000);
6718
6719 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6720 kvm_x86_ops->set_cr0(vcpu, cr0);
6721 vcpu->arch.cr0 = cr0;
6722
6723 kvm_x86_ops->set_cr4(vcpu, 0);
6724
18c3626e
PB		 6725 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6726 dt.address = dt.size = 0;
6727 kvm_x86_ops->set_idt(vcpu, &dt);
6728
660a5d51
PB		 6729 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6730
6731 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6732 cs.base = vcpu->arch.smbase;
6733
6734 ds.selector = 0;
6735 ds.base = 0;
6736
6737 cs.limit = ds.limit = 0xffffffff;
6738 cs.type = ds.type = 0x3;
6739 cs.dpl = ds.dpl = 0;
6740 cs.db = ds.db = 0;
6741 cs.s = ds.s = 1;
6742 cs.l = ds.l = 0;
6743 cs.g = ds.g = 1;
6744 cs.avl = ds.avl = 0;
6745 cs.present = ds.present = 1;
6746 cs.unusable = ds.unusable = 0;
6747 cs.padding = ds.padding = 0;
6748
6749 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6750 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6751 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6752 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6753 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6754 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6755
d6321d49 6756 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6757 kvm_x86_ops->set_efer(vcpu, 0);
6758
6759 kvm_update_cpuid(vcpu);
6760 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6761}
6762
ee2cd4b7 6763static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6764{
6765 vcpu->arch.smi_pending = true;
6766 kvm_make_request(KVM_REQ_EVENT, vcpu);
6767}
6768
2860c4b1
PB		 6769void kvm_make_scan_ioapic_request(struct kvm *kvm)
6770{
6771 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6772}
6773
3d81bc7e 6774static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6775{
5c919412
AS		 6776 u64 eoi_exit_bitmap[4];
6777
3d81bc7e
YZ		 6778 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6779 return;
c7c9c56c 6780
6308630b 6781 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6782
b053b2ae 6783 if (irqchip_split(vcpu->kvm))
6308630b 6784 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6785 else {
76dfafd5 6786 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6787 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6788 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6789 }
5c919412
AS		 6790 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6791 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6792 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6793}
6794
b1394e74
RK		 6795void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6796 unsigned long start, unsigned long end)
6797{
6798 unsigned long apic_address;
6799
6800 /*
6801 * The physical address of apic access page is stored in the VMCS.
6802 * Update it when it becomes invalid.
6803 */
6804 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6805 if (start <= apic_address && apic_address < end)
6806 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6807}
6808
4256f43f
TC		 6809void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6810{
c24ae0dc
TC		 6811 struct page *page = NULL;
6812
35754c98 6813 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6814 return;
6815
4256f43f
TC		 6816 if (!kvm_x86_ops->set_apic_access_page_addr)
6817 return;
6818
c24ae0dc 6819 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6820 if (is_error_page(page))
6821 return;
c24ae0dc
TC		 6822 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6823
6824 /*
6825 * Do not pin apic access page in memory, the MMU notifier
6826 * will call us again if it is migrated or swapped out.
6827 */
6828 put_page(page);
4256f43f
TC		 6829}
6830EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6831
9357d939 6832/*
362c698f 6833 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6834 * exiting to the userspace. Otherwise, the value will be returned to the
6835 * userspace.
6836 */
851ba692 6837static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6838{
6839 int r;
62a193ed
MG		 6840 bool req_int_win =
6841 dm_request_for_irq_injection(vcpu) &&
6842 kvm_cpu_accept_dm_intr(vcpu);
6843
730dca42 6844 bool req_immediate_exit = false;
b6c7a5dc 6845
2fa6e1e1 6846 if (kvm_request_pending(vcpu)) {
a8eeb04a 6847 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6848 kvm_mmu_unload(vcpu);
a8eeb04a 6849 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6850 __kvm_migrate_timers(vcpu);
d828199e
MT		 6851 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6852 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6853 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6854 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6855 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6856 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6857 if (unlikely(r))
6858 goto out;
6859 }
a8eeb04a 6860 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6861 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6862 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 6863 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 6864 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6865 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6866 r = 0;
6867 goto out;
6868 }
a8eeb04a 6869 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6870 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6871 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6872 r = 0;
6873 goto out;
6874 }
af585b92
GN		 6875 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6876 /* Page is swapped out. Do synthetic halt */
6877 vcpu->arch.apf.halted = true;
6878 r = 1;
6879 goto out;
6880 }
c9aaa895
GC		 6881 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6882 record_steal_time(vcpu);
64d60670
PB		 6883 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6884 process_smi(vcpu);
7460fb4a
AK		 6885 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6886 process_nmi(vcpu);
f5132b01 6887 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6888 kvm_pmu_handle_event(vcpu);
f5132b01 6889 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6890 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6891 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6892 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6893 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6894 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6895 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6896 vcpu->run->eoi.vector =
6897 vcpu->arch.pending_ioapic_eoi;
6898 r = 0;
6899 goto out;
6900 }
6901 }
3d81bc7e
YZ		 6902 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6903 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6904 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6905 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6906 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6907 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6908 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6909 r = 0;
6910 goto out;
6911 }
e516cebb
AS		 6912 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6913 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6914 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6915 r = 0;
6916 goto out;
6917 }
db397571
AS		 6918 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6919 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6920 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6921 r = 0;
6922 goto out;
6923 }
f3b138c5
AS		 6924
6925 /*
6926 * KVM_REQ_HV_STIMER has to be processed after
6927 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6928 * depend on the guest clock being up-to-date
6929 */
1f4b34f8
AS		 6930 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6931 kvm_hv_process_stimers(vcpu);
2f52d58c 6932 }
b93463aa 6933
b463a6f7 6934 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6935 ++vcpu->stat.req_event;
66450a21
JK		 6936 kvm_apic_accept_events(vcpu);
6937 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6938 r = 1;
6939 goto out;
6940 }
6941
b6b8a145
JK		 6942 if (inject_pending_event(vcpu, req_int_win) != 0)
6943 req_immediate_exit = true;
321c5658 6944 else {
cc3d967f 6945 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6946 *
cc3d967f
LP		 6947 * SMIs have three cases:
6948 * 1) They can be nested, and then there is nothing to
6949 * do here because RSM will cause a vmexit anyway.
6950 * 2) There is an ISA-specific reason why SMI cannot be
6951 * injected, and the moment when this changes can be
6952 * intercepted.
6953 * 3) Or the SMI can be pending because
6954 * inject_pending_event has completed the injection
6955 * of an IRQ or NMI from the previous vmexit, and
6956 * then we request an immediate exit to inject the
6957 * SMI.
c43203ca
PB		 6958 */
6959 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6960 if (!kvm_x86_ops->enable_smi_window(vcpu))
6961 req_immediate_exit = true;
321c5658
YS		 6962 if (vcpu->arch.nmi_pending)
6963 kvm_x86_ops->enable_nmi_window(vcpu);
6964 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6965 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6966 WARN_ON(vcpu->arch.exception.pending);
321c5658 6967 }
b463a6f7
AK		 6968
6969 if (kvm_lapic_enabled(vcpu)) {
6970 update_cr8_intercept(vcpu);
6971 kvm_lapic_sync_to_vapic(vcpu);
6972 }
6973 }
6974
d8368af8
AK		 6975 r = kvm_mmu_reload(vcpu);
6976 if (unlikely(r)) {
d905c069 6977 goto cancel_injection;
d8368af8
AK		 6978 }
6979
b6c7a5dc
HB		 6980 preempt_disable();
6981
6982 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 6983
6984 /*
6985 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6986 * IPI are then delayed after guest entry, which ensures that they
6987 * result in virtual interrupt delivery.
6988 */
6989 local_irq_disable();
6b7e2d09
XG		 6990 vcpu->mode = IN_GUEST_MODE;
6991
01b71917
MT		 6992 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6993
0f127d12 6994 /*
b95234c8 6995 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6996 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6997 *
6998 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6999 * pairs with the memory barrier implicit in pi_test_and_set_on
7000 * (see vmx_deliver_posted_interrupt).
7001 *
7002 * 3) This also orders the write to mode from any reads to the page
7003 * tables done while the VCPU is running. Please see the comment
7004 * in kvm_flush_remote_tlbs.
6b7e2d09 7005 */
01b71917 7006 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7007
b95234c8
PB		 7008 /*
7009 * This handles the case where a posted interrupt was
7010 * notified with kvm_vcpu_kick.
7011 */
7012 if (kvm_lapic_enabled(vcpu)) {
7013 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7014 kvm_x86_ops->sync_pir_to_irr(vcpu);
7015 }
32f88400 7016
2fa6e1e1 7017 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7018 || need_resched() || signal_pending(current)) {
6b7e2d09 7019 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7020 smp_wmb();
6c142801
AK		 7021 local_irq_enable();
7022 preempt_enable();
01b71917 7023 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7024 r = 1;
d905c069 7025 goto cancel_injection;
6c142801
AK		 7026 }
7027
fc5b7f3b
DM		 7028 kvm_load_guest_xcr0(vcpu);
7029
c43203ca
PB		 7030 if (req_immediate_exit) {
7031 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7032 smp_send_reschedule(vcpu->cpu);
c43203ca 7033 }
d6185f20 7034
8b89fe1f 7035 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7036 if (lapic_timer_advance_ns)
7037 wait_lapic_expire(vcpu);
6edaa530 7038 guest_enter_irqoff();
b6c7a5dc 7039
42dbaa5a 7040 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7041 set_debugreg(0, 7);
7042 set_debugreg(vcpu->arch.eff_db[0], 0);
7043 set_debugreg(vcpu->arch.eff_db[1], 1);
7044 set_debugreg(vcpu->arch.eff_db[2], 2);
7045 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7046 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7047 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7048 }
b6c7a5dc 7049
851ba692 7050 kvm_x86_ops->run(vcpu);
b6c7a5dc 7051
c77fb5fe
PB		 7052 /*
7053 * Do this here before restoring debug registers on the host. And
7054 * since we do this before handling the vmexit, a DR access vmexit
7055 * can (a) read the correct value of the debug registers, (b) set
7056 * KVM_DEBUGREG_WONT_EXIT again.
7057 */
7058 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7059 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7060 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7061 kvm_update_dr0123(vcpu);
7062 kvm_update_dr6(vcpu);
7063 kvm_update_dr7(vcpu);
7064 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7065 }
7066
24f1e32c
FW		 7067 /*
7068 * If the guest has used debug registers, at least dr7
7069 * will be disabled while returning to the host.
7070 * If we don't have active breakpoints in the host, we don't
7071 * care about the messed up debug address registers. But if
7072 * we have some of them active, restore the old state.
7073 */
59d8eb53 7074 if (hw_breakpoint_active())
24f1e32c 7075 hw_breakpoint_restore();
42dbaa5a 7076
4ba76538 7077 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7078
6b7e2d09 7079 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7080 smp_wmb();
a547c6db 7081
fc5b7f3b
DM		 7082 kvm_put_guest_xcr0(vcpu);
7083
a547c6db 7084 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7085
7086 ++vcpu->stat.exits;
7087
f2485b3e 7088 guest_exit_irqoff();
b6c7a5dc 7089
f2485b3e 7090 local_irq_enable();
b6c7a5dc
HB		 7091 preempt_enable();
7092
f656ce01 7093 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7094
b6c7a5dc
HB		 7095 /*
7096 * Profile KVM exit RIPs:
7097 */
7098 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7099 unsigned long rip = kvm_rip_read(vcpu);
7100 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7101 }
7102
cc578287
ZA		 7103 if (unlikely(vcpu->arch.tsc_always_catchup))
7104 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7105
5cfb1d5a
MT		 7106 if (vcpu->arch.apic_attention)
7107 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7108
618232e2 7109 vcpu->arch.gpa_available = false;
851ba692 7110 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7111 return r;
7112
7113cancel_injection:
7114 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7115 if (unlikely(vcpu->arch.apic_attention))
7116 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7117out:
7118 return r;
7119}
b6c7a5dc 7120
362c698f
PB		 7121static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7122{
bf9f6ac8
FW		 7123 if (!kvm_arch_vcpu_runnable(vcpu) &&
7124 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7125 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7126 kvm_vcpu_block(vcpu);
7127 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7128
7129 if (kvm_x86_ops->post_block)
7130 kvm_x86_ops->post_block(vcpu);
7131
9c8fd1ba
PB		 7132 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7133 return 1;
7134 }
362c698f
PB		 7135
7136 kvm_apic_accept_events(vcpu);
7137 switch(vcpu->arch.mp_state) {
7138 case KVM_MP_STATE_HALTED:
7139 vcpu->arch.pv.pv_unhalted = false;
7140 vcpu->arch.mp_state =
7141 KVM_MP_STATE_RUNNABLE;
7142 case KVM_MP_STATE_RUNNABLE:
7143 vcpu->arch.apf.halted = false;
7144 break;
7145 case KVM_MP_STATE_INIT_RECEIVED:
7146 break;
7147 default:
7148 return -EINTR;
7149 break;
7150 }
7151 return 1;
7152}
09cec754 7153
5d9bc648
PB		 7154static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7155{
0ad3bed6
PB		 7156 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7157 kvm_x86_ops->check_nested_events(vcpu, false);
7158
5d9bc648
PB		 7159 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7160 !vcpu->arch.apf.halted);
7161}
7162
362c698f 7163static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7164{
7165 int r;
f656ce01 7166 struct kvm *kvm = vcpu->kvm;
d7690175 7167
f656ce01 7168 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7169
362c698f 7170 for (;;) {
58f800d5 7171 if (kvm_vcpu_running(vcpu)) {
851ba692 7172 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7173 } else {
362c698f 7174 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7175 }
7176
09cec754
GN		 7177 if (r <= 0)
7178 break;
7179
72875d8a 7180 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7181 if (kvm_cpu_has_pending_timer(vcpu))
7182 kvm_inject_pending_timer_irqs(vcpu);
7183
782d422b
MG		 7184 if (dm_request_for_irq_injection(vcpu) &&
7185 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7186 r = 0;
7187 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7188 ++vcpu->stat.request_irq_exits;
362c698f 7189 break;
09cec754 7190 }
af585b92
GN		 7191
7192 kvm_check_async_pf_completion(vcpu);
7193
09cec754
GN		 7194 if (signal_pending(current)) {
7195 r = -EINTR;
851ba692 7196 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7197 ++vcpu->stat.signal_exits;
362c698f 7198 break;
09cec754
GN		 7199 }
7200 if (need_resched()) {
f656ce01 7201 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7202 cond_resched();
f656ce01 7203 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7204 }
b6c7a5dc
HB		 7205 }
7206
f656ce01 7207 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7208
7209 return r;
7210}
7211
716d51ab
GN		 7212static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7213{
7214 int r;
7215 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7216 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7217 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7218 if (r != EMULATE_DONE)
7219 return 0;
7220 return 1;
7221}
7222
7223static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7224{
7225 BUG_ON(!vcpu->arch.pio.count);
7226
7227 return complete_emulated_io(vcpu);
7228}
7229
f78146b0
AK		 7230/*
7231 * Implements the following, as a state machine:
7232 *
7233 * read:
7234 * for each fragment
87da7e66
XG		 7235 * for each mmio piece in the fragment
7236 * write gpa, len
7237 * exit
7238 * copy data
f78146b0
AK		 7239 * execute insn
7240 *
7241 * write:
7242 * for each fragment
87da7e66
XG		 7243 * for each mmio piece in the fragment
7244 * write gpa, len
7245 * copy data
7246 * exit
f78146b0 7247 */
716d51ab 7248static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7249{
7250 struct kvm_run *run = vcpu->run;
f78146b0 7251 struct kvm_mmio_fragment *frag;
87da7e66 7252 unsigned len;
5287f194 7253
716d51ab 7254 BUG_ON(!vcpu->mmio_needed);
5287f194 7255
716d51ab 7256 /* Complete previous fragment */
87da7e66
XG		 7257 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7258 len = min(8u, frag->len);
716d51ab 7259 if (!vcpu->mmio_is_write)
87da7e66
XG		 7260 memcpy(frag->data, run->mmio.data, len);
7261
7262 if (frag->len <= 8) {
7263 /* Switch to the next fragment. */
7264 frag++;
7265 vcpu->mmio_cur_fragment++;
7266 } else {
7267 /* Go forward to the next mmio piece. */
7268 frag->data += len;
7269 frag->gpa += len;
7270 frag->len -= len;
7271 }
7272
a08d3b3b 7273 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7274 vcpu->mmio_needed = 0;
0912c977
PB		 7275
7276 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7277 if (vcpu->mmio_is_write)
716d51ab
GN		 7278 return 1;
7279 vcpu->mmio_read_completed = 1;
7280 return complete_emulated_io(vcpu);
7281 }
87da7e66 7282
716d51ab
GN		 7283 run->exit_reason = KVM_EXIT_MMIO;
7284 run->mmio.phys_addr = frag->gpa;
7285 if (vcpu->mmio_is_write)
87da7e66
XG		 7286 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7287 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7288 run->mmio.is_write = vcpu->mmio_is_write;
7289 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7290 return 0;
5287f194
AK		 7291}
7292
716d51ab 7293
b6c7a5dc
HB		 7294int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7295{
7296 int r;
b6c7a5dc 7297
accb757d 7298 vcpu_load(vcpu);
20b7035c 7299 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7300 kvm_load_guest_fpu(vcpu);
7301
a4535290 7302 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7303 if (kvm_run->immediate_exit) {
7304 r = -EINTR;
7305 goto out;
7306 }
b6c7a5dc 7307 kvm_vcpu_block(vcpu);
66450a21 7308 kvm_apic_accept_events(vcpu);
72875d8a 7309 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7310 r = -EAGAIN;
a0595000
JS		 7311 if (signal_pending(current)) {
7312 r = -EINTR;
7313 vcpu->run->exit_reason = KVM_EXIT_INTR;
7314 ++vcpu->stat.signal_exits;
7315 }
ac9f6dc0 7316 goto out;
b6c7a5dc
HB		 7317 }
7318
b6c7a5dc 7319 /* re-sync apic's tpr */
35754c98 7320 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7321 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7322 r = -EINVAL;
7323 goto out;
7324 }
7325 }
b6c7a5dc 7326
716d51ab
GN		 7327 if (unlikely(vcpu->arch.complete_userspace_io)) {
7328 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7329 vcpu->arch.complete_userspace_io = NULL;
7330 r = cui(vcpu);
7331 if (r <= 0)
5663d8f9 7332 goto out;
716d51ab
GN		 7333 } else
7334 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7335
460df4c1
PB		 7336 if (kvm_run->immediate_exit)
7337 r = -EINTR;
7338 else
7339 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7340
7341out:
5663d8f9 7342 kvm_put_guest_fpu(vcpu);
f1d86e46 7343 post_kvm_run_save(vcpu);
20b7035c 7344 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7345
accb757d 7346 vcpu_put(vcpu);
b6c7a5dc
HB		 7347 return r;
7348}
7349
7350int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7351{
1fc9b76b
CD		 7352 vcpu_load(vcpu);
7353
7ae441ea
GN		 7354 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7355 /*
7356 * We are here if userspace calls get_regs() in the middle of
7357 * instruction emulation. Registers state needs to be copied
4a969980 7358 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7359 * that usually, but some bad designed PV devices (vmware
7360 * backdoor interface) need this to work
7361 */
dd856efa 7362 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7363 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7364 }
5fdbf976
MT		 7365 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7366 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7367 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7368 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7369 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7370 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7371 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7372 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7373#ifdef CONFIG_X86_64
5fdbf976
MT		 7374 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7375 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7376 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7377 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7378 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7379 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7380 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7381 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7382#endif
7383
5fdbf976 7384 regs->rip = kvm_rip_read(vcpu);
91586a3b 7385 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7386
1fc9b76b 7387 vcpu_put(vcpu);
b6c7a5dc
HB		 7388 return 0;
7389}
7390
7391int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7392{
875656fe
CD		 7393 vcpu_load(vcpu);
7394
7ae441ea
GN		 7395 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7396 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7397
5fdbf976
MT		 7398 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7399 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7400 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7401 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7402 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7403 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7404 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7405 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7406#ifdef CONFIG_X86_64
5fdbf976
MT		 7407 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7408 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7409 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7410 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7411 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7412 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7413 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7414 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7415#endif
7416
5fdbf976 7417 kvm_rip_write(vcpu, regs->rip);
d73235d1 7418 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7419
b4f14abd
JK		 7420 vcpu->arch.exception.pending = false;
7421
3842d135
AK		 7422 kvm_make_request(KVM_REQ_EVENT, vcpu);
7423
875656fe 7424 vcpu_put(vcpu);
b6c7a5dc
HB		 7425 return 0;
7426}
7427
b6c7a5dc
HB		 7428void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7429{
7430 struct kvm_segment cs;
7431
3e6e0aab 7432 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7433 *db = cs.db;
7434 *l = cs.l;
7435}
7436EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7437
7438int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7439 struct kvm_sregs *sregs)
7440{
89a27f4d 7441 struct desc_ptr dt;
b6c7a5dc 7442
bcdec41c
CD		 7443 vcpu_load(vcpu);
7444
3e6e0aab
GT		 7445 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7446 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7447 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7448 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7449 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7450 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7451
3e6e0aab
GT		 7452 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7453 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7454
7455 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7456 sregs->idt.limit = dt.size;
7457 sregs->idt.base = dt.address;
b6c7a5dc 7458 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7459 sregs->gdt.limit = dt.size;
7460 sregs->gdt.base = dt.address;
b6c7a5dc 7461
4d4ec087 7462 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7463 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7464 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7465 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7466 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7467 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7468 sregs->apic_base = kvm_get_apic_base(vcpu);
7469
923c61bb 7470 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7471
36752c9b 7472 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7473 set_bit(vcpu->arch.interrupt.nr,
7474 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7475
bcdec41c 7476 vcpu_put(vcpu);
b6c7a5dc
HB		 7477 return 0;
7478}
7479
62d9f0db
MT		 7480int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7481 struct kvm_mp_state *mp_state)
7482{
fd232561
CD		 7483 vcpu_load(vcpu);
7484
66450a21 7485 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7486 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7487 vcpu->arch.pv.pv_unhalted)
7488 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7489 else
7490 mp_state->mp_state = vcpu->arch.mp_state;
7491
fd232561 7492 vcpu_put(vcpu);
62d9f0db
MT		 7493 return 0;
7494}
7495
7496int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7497 struct kvm_mp_state *mp_state)
7498{
e83dff5e
CD		 7499 int ret = -EINVAL;
7500
7501 vcpu_load(vcpu);
7502
bce87cce 7503 if (!lapic_in_kernel(vcpu) &&
66450a21 7504 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7505 goto out;
66450a21 7506
28bf2888
DH		 7507 /* INITs are latched while in SMM */
7508 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7509 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7510 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7511 goto out;
28bf2888 7512
66450a21
JK		 7513 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7514 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7515 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7516 } else
7517 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7518 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7519
7520 ret = 0;
7521out:
7522 vcpu_put(vcpu);
7523 return ret;
62d9f0db
MT		 7524}
7525
7f3d35fd
KW		 7526int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7527 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7528{
9d74191a 7529 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7530 int ret;
e01c2426 7531
8ec4722d 7532 init_emulate_ctxt(vcpu);
c697518a 7533
7f3d35fd 7534 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7535 has_error_code, error_code);
c697518a 7536
c697518a 7537 if (ret)
19d04437 7538 return EMULATE_FAIL;
37817f29 7539
9d74191a
TY		 7540 kvm_rip_write(vcpu, ctxt->eip);
7541 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7542 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7543 return EMULATE_DONE;
37817f29
IE		 7544}
7545EXPORT_SYMBOL_GPL(kvm_task_switch);
7546
b6c7a5dc
HB		 7547int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7548 struct kvm_sregs *sregs)
7549{
58cb628d 7550 struct msr_data apic_base_msr;
b6c7a5dc 7551 int mmu_reset_needed = 0;
63f42e02 7552 int pending_vec, max_bits, idx;
89a27f4d 7553 struct desc_ptr dt;
b4ef9d4e
CD		 7554 int ret = -EINVAL;
7555
7556 vcpu_load(vcpu);
b6c7a5dc 7557
d6321d49
RK		 7558 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7559 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7560 goto out;
6d1068b3 7561
d3802286
JM		 7562 apic_base_msr.data = sregs->apic_base;
7563 apic_base_msr.host_initiated = true;
7564 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7565 goto out;
6d1068b3 7566
89a27f4d
GN		 7567 dt.size = sregs->idt.limit;
7568 dt.address = sregs->idt.base;
b6c7a5dc 7569 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7570 dt.size = sregs->gdt.limit;
7571 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7572 kvm_x86_ops->set_gdt(vcpu, &dt);
7573
ad312c7c 7574 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7575 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7576 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7577 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7578
2d3ad1f4 7579 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7580
f6801dff 7581 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7582 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7583
4d4ec087 7584 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7585 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7586 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7587
fc78f519 7588 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7589 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7590 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7591 kvm_update_cpuid(vcpu);
63f42e02
XG		 7592
7593 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7594 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7595 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7596 mmu_reset_needed = 1;
7597 }
63f42e02 7598 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7599
7600 if (mmu_reset_needed)
7601 kvm_mmu_reset_context(vcpu);
7602
a50abc3b 7603 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7604 pending_vec = find_first_bit(
7605 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7606 if (pending_vec < max_bits) {
66fd3f7f 7607 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7608 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7609 }
7610
3e6e0aab
GT		 7611 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7612 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7613 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7614 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7615 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7616 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7617
3e6e0aab
GT		 7618 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7619 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7620
5f0269f5
ME		 7621 update_cr8_intercept(vcpu);
7622
9c3e4aab 7623 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7624 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7625 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7626 !is_protmode(vcpu))
9c3e4aab
MT		 7627 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7628
3842d135
AK		 7629 kvm_make_request(KVM_REQ_EVENT, vcpu);
7630
b4ef9d4e
CD		 7631 ret = 0;
7632out:
7633 vcpu_put(vcpu);
7634 return ret;
b6c7a5dc
HB		 7635}
7636
d0bfb940
JK		 7637int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7638 struct kvm_guest_debug *dbg)
b6c7a5dc 7639{
355be0b9 7640 unsigned long rflags;
ae675ef0 7641 int i, r;
b6c7a5dc 7642
66b56562
CD		 7643 vcpu_load(vcpu);
7644
4f926bf2
JK		 7645 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7646 r = -EBUSY;
7647 if (vcpu->arch.exception.pending)
2122ff5e 7648 goto out;
4f926bf2
JK		 7649 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7650 kvm_queue_exception(vcpu, DB_VECTOR);
7651 else
7652 kvm_queue_exception(vcpu, BP_VECTOR);
7653 }
7654
91586a3b
JK		 7655 /*
7656 * Read rflags as long as potentially injected trace flags are still
7657 * filtered out.
7658 */
7659 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7660
7661 vcpu->guest_debug = dbg->control;
7662 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7663 vcpu->guest_debug = 0;
7664
7665 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7666 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7667 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7668 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7669 } else {
7670 for (i = 0; i < KVM_NR_DB_REGS; i++)
7671 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7672 }
c8639010 7673 kvm_update_dr7(vcpu);
ae675ef0 7674
f92653ee
JK		 7675 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7676 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7677 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7678
91586a3b
JK		 7679 /*
7680 * Trigger an rflags update that will inject or remove the trace
7681 * flags.
7682 */
7683 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7684
a96036b8 7685 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7686
4f926bf2 7687 r = 0;
d0bfb940 7688
2122ff5e 7689out:
66b56562 7690 vcpu_put(vcpu);
b6c7a5dc
HB		 7691 return r;
7692}
7693
8b006791
ZX		 7694/*
7695 * Translate a guest virtual address to a guest physical address.
7696 */
7697int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7698 struct kvm_translation *tr)
7699{
7700 unsigned long vaddr = tr->linear_address;
7701 gpa_t gpa;
f656ce01 7702 int idx;
8b006791 7703
1da5b61d
CD		 7704 vcpu_load(vcpu);
7705
f656ce01 7706 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7707 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7708 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7709 tr->physical_address = gpa;
7710 tr->valid = gpa != UNMAPPED_GVA;
7711 tr->writeable = 1;
7712 tr->usermode = 0;
8b006791 7713
1da5b61d 7714 vcpu_put(vcpu);
8b006791
ZX		 7715 return 0;
7716}
7717
d0752060
HB		 7718int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7719{
1393123e 7720 struct fxregs_state *fxsave;
d0752060 7721
1393123e
CD		 7722 vcpu_load(vcpu);
7723
7724 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 7725 memcpy(fpu->fpr, fxsave->st_space, 128);
7726 fpu->fcw = fxsave->cwd;
7727 fpu->fsw = fxsave->swd;
7728 fpu->ftwx = fxsave->twd;
7729 fpu->last_opcode = fxsave->fop;
7730 fpu->last_ip = fxsave->rip;
7731 fpu->last_dp = fxsave->rdp;
7732 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7733
1393123e 7734 vcpu_put(vcpu);
d0752060
HB		 7735 return 0;
7736}
7737
7738int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7739{
6a96bc7f
CD		 7740 struct fxregs_state *fxsave;
7741
7742 vcpu_load(vcpu);
7743
7744 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7745
d0752060
HB		 7746 memcpy(fxsave->st_space, fpu->fpr, 128);
7747 fxsave->cwd = fpu->fcw;
7748 fxsave->swd = fpu->fsw;
7749 fxsave->twd = fpu->ftwx;
7750 fxsave->fop = fpu->last_opcode;
7751 fxsave->rip = fpu->last_ip;
7752 fxsave->rdp = fpu->last_dp;
7753 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7754
6a96bc7f 7755 vcpu_put(vcpu);
d0752060
HB		 7756 return 0;
7757}
7758
0ee6a517 7759static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7760{
bf935b0b 7761 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7762 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7763 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7764 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7765
2acf923e
DC		 7766 /*
7767 * Ensure guest xcr0 is valid for loading
7768 */
d91cab78 7769 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7770
ad312c7c 7771 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7772}
d0752060 7773
f775b13e 7774/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7775void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7776{
f775b13e
RR		 7777 preempt_disable();
7778 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7779 /* PKRU is separately restored in kvm_x86_ops->run. */
7780 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7781 ~XFEATURE_MASK_PKRU);
f775b13e 7782 preempt_enable();
0c04851c 7783 trace_kvm_fpu(1);
d0752060 7784}
d0752060 7785
f775b13e 7786/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 7787void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7788{
f775b13e 7789 preempt_disable();
4f836347 7790 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 7791 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7792 preempt_enable();
f096ed85 7793 ++vcpu->stat.fpu_reload;
0c04851c 7794 trace_kvm_fpu(0);
d0752060 7795}
e9b11c17
ZX		 7796
7797void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7798{
bd768e14
IY		 7799 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7800
12f9a48f 7801 kvmclock_reset(vcpu);
7f1ea208 7802
e9b11c17 7803 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7804 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7805}
7806
7807struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7808 unsigned int id)
7809{
c447e76b
LL		 7810 struct kvm_vcpu *vcpu;
7811
6755bae8
ZA		 7812 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7813 printk_once(KERN_WARNING
7814 "kvm: SMP vm created on host with unstable TSC; "
7815 "guest TSC will not be reliable\n");
c447e76b
LL		 7816
7817 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7818
c447e76b 7819 return vcpu;
26e5215f 7820}
e9b11c17 7821
26e5215f
AK		 7822int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7823{
19efffa2 7824 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 7825 vcpu_load(vcpu);
d28bc9dd 7826 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7827 kvm_mmu_setup(vcpu);
e9b11c17 7828 vcpu_put(vcpu);
ec7660cc 7829 return 0;
e9b11c17
ZX		 7830}
7831
31928aa5 7832void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7833{
8fe8ab46 7834 struct msr_data msr;
332967a3 7835 struct kvm *kvm = vcpu->kvm;
42897d86 7836
d3457c87
RK		 7837 kvm_hv_vcpu_postcreate(vcpu);
7838
ec7660cc 7839 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 7840 return;
ec7660cc 7841 vcpu_load(vcpu);
8fe8ab46
WA		 7842 msr.data = 0x0;
7843 msr.index = MSR_IA32_TSC;
7844 msr.host_initiated = true;
7845 kvm_write_tsc(vcpu, &msr);
42897d86 7846 vcpu_put(vcpu);
ec7660cc 7847 mutex_unlock(&vcpu->mutex);
42897d86 7848
630994b3
MT		 7849 if (!kvmclock_periodic_sync)
7850 return;
7851
332967a3
AJ		 7852 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7853 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7854}
7855
d40ccc62 7856void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7857{
344d9588
GN		 7858 vcpu->arch.apf.msr_val = 0;
7859
ec7660cc 7860 vcpu_load(vcpu);
e9b11c17
ZX		 7861 kvm_mmu_unload(vcpu);
7862 vcpu_put(vcpu);
7863
7864 kvm_x86_ops->vcpu_free(vcpu);
7865}
7866
d28bc9dd 7867void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7868{
e69fab5d
PB		 7869 vcpu->arch.hflags = 0;
7870
c43203ca 7871 vcpu->arch.smi_pending = 0;
52797bf9 7872 vcpu->arch.smi_count = 0;
7460fb4a
AK		 7873 atomic_set(&vcpu->arch.nmi_queued, 0);
7874 vcpu->arch.nmi_pending = 0;
448fa4a9 7875 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7876 kvm_clear_interrupt_queue(vcpu);
7877 kvm_clear_exception_queue(vcpu);
664f8e26 7878 vcpu->arch.exception.pending = false;
448fa4a9 7879
42dbaa5a 7880 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7881 kvm_update_dr0123(vcpu);
6f43ed01 7882 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7883 kvm_update_dr6(vcpu);
42dbaa5a 7884 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7885 kvm_update_dr7(vcpu);
42dbaa5a 7886
1119022c
NA		 7887 vcpu->arch.cr2 = 0;
7888
3842d135 7889 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7890 vcpu->arch.apf.msr_val = 0;
c9aaa895 7891 vcpu->arch.st.msr_val = 0;
3842d135 7892
12f9a48f
GC		 7893 kvmclock_reset(vcpu);
7894
af585b92
GN		 7895 kvm_clear_async_pf_completion_queue(vcpu);
7896 kvm_async_pf_hash_reset(vcpu);
7897 vcpu->arch.apf.halted = false;
3842d135 7898
a554d207
WL		 7899 if (kvm_mpx_supported()) {
7900 void *mpx_state_buffer;
7901
7902 /*
7903 * To avoid have the INIT path from kvm_apic_has_events() that be
7904 * called with loaded FPU and does not let userspace fix the state.
7905 */
f775b13e
RR		 7906 if (init_event)
7907 kvm_put_guest_fpu(vcpu);
a554d207
WL		 7908 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7909 XFEATURE_MASK_BNDREGS);
7910 if (mpx_state_buffer)
7911 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7912 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7913 XFEATURE_MASK_BNDCSR);
7914 if (mpx_state_buffer)
7915 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 7916 if (init_event)
7917 kvm_load_guest_fpu(vcpu);
a554d207
WL		 7918 }
7919
64d60670 7920 if (!init_event) {
d28bc9dd 7921 kvm_pmu_reset(vcpu);
64d60670 7922 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7923
7924 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7925 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7926
7927 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7928 }
f5132b01 7929
66f7b72e
JS		 7930 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7931 vcpu->arch.regs_avail = ~0;
7932 vcpu->arch.regs_dirty = ~0;
7933
a554d207
WL		 7934 vcpu->arch.ia32_xss = 0;
7935
d28bc9dd 7936 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7937}
7938
2b4a273b 7939void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7940{
7941 struct kvm_segment cs;
7942
7943 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7944 cs.selector = vector << 8;
7945 cs.base = vector << 12;
7946 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7947 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7948}
7949
13a34e06 7950int kvm_arch_hardware_enable(void)
e9b11c17 7951{
ca84d1a2
ZA		 7952 struct kvm *kvm;
7953 struct kvm_vcpu *vcpu;
7954 int i;
0dd6a6ed
ZA		 7955 int ret;
7956 u64 local_tsc;
7957 u64 max_tsc = 0;
7958 bool stable, backwards_tsc = false;
18863bdd
AK		 7959
7960 kvm_shared_msr_cpu_online();
13a34e06 7961 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7962 if (ret != 0)
7963 return ret;
7964
4ea1636b 7965 local_tsc = rdtsc();
0dd6a6ed
ZA		 7966 stable = !check_tsc_unstable();
7967 list_for_each_entry(kvm, &vm_list, vm_list) {
7968 kvm_for_each_vcpu(i, vcpu, kvm) {
7969 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7970 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7971 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7972 backwards_tsc = true;
7973 if (vcpu->arch.last_host_tsc > max_tsc)
7974 max_tsc = vcpu->arch.last_host_tsc;
7975 }
7976 }
7977 }
7978
7979 /*
7980 * Sometimes, even reliable TSCs go backwards. This happens on
7981 * platforms that reset TSC during suspend or hibernate actions, but
7982 * maintain synchronization. We must compensate. Fortunately, we can
7983 * detect that condition here, which happens early in CPU bringup,
7984 * before any KVM threads can be running. Unfortunately, we can't
7985 * bring the TSCs fully up to date with real time, as we aren't yet far
7986 * enough into CPU bringup that we know how much real time has actually
108b249c 7987 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7988 * variables that haven't been updated yet.
7989 *
7990 * So we simply find the maximum observed TSC above, then record the
7991 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7992 * the adjustment will be applied. Note that we accumulate
7993 * adjustments, in case multiple suspend cycles happen before some VCPU
7994 * gets a chance to run again. In the event that no KVM threads get a
7995 * chance to run, we will miss the entire elapsed period, as we'll have
7996 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7997 * loose cycle time. This isn't too big a deal, since the loss will be
7998 * uniform across all VCPUs (not to mention the scenario is extremely
7999 * unlikely). It is possible that a second hibernate recovery happens
8000 * much faster than a first, causing the observed TSC here to be
8001 * smaller; this would require additional padding adjustment, which is
8002 * why we set last_host_tsc to the local tsc observed here.
8003 *
8004 * N.B. - this code below runs only on platforms with reliable TSC,
8005 * as that is the only way backwards_tsc is set above. Also note
8006 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8007 * have the same delta_cyc adjustment applied if backwards_tsc
8008 * is detected. Note further, this adjustment is only done once,
8009 * as we reset last_host_tsc on all VCPUs to stop this from being
8010 * called multiple times (one for each physical CPU bringup).
8011 *
4a969980 8012 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8013 * will be compensated by the logic in vcpu_load, which sets the TSC to
8014 * catchup mode. This will catchup all VCPUs to real time, but cannot
8015 * guarantee that they stay in perfect synchronization.
8016 */
8017 if (backwards_tsc) {
8018 u64 delta_cyc = max_tsc - local_tsc;
8019 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8020 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8021 kvm_for_each_vcpu(i, vcpu, kvm) {
8022 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8023 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8024 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8025 }
8026
8027 /*
8028 * We have to disable TSC offset matching.. if you were
8029 * booting a VM while issuing an S4 host suspend....
8030 * you may have some problem. Solving this issue is
8031 * left as an exercise to the reader.
8032 */
8033 kvm->arch.last_tsc_nsec = 0;
8034 kvm->arch.last_tsc_write = 0;
8035 }
8036
8037 }
8038 return 0;
e9b11c17
ZX		 8039}
8040
13a34e06 8041void kvm_arch_hardware_disable(void)
e9b11c17 8042{
13a34e06
RK		 8043 kvm_x86_ops->hardware_disable();
8044 drop_user_return_notifiers();
e9b11c17
ZX		 8045}
8046
8047int kvm_arch_hardware_setup(void)
8048{
9e9c3fe4
NA		 8049 int r;
8050
8051 r = kvm_x86_ops->hardware_setup();
8052 if (r != 0)
8053 return r;
8054
35181e86
HZ		 8055 if (kvm_has_tsc_control) {
8056 /*
8057 * Make sure the user can only configure tsc_khz values that
8058 * fit into a signed integer.
8059 * A min value is not calculated needed because it will always
8060 * be 1 on all machines.
8061 */
8062 u64 max = min(0x7fffffffULL,
8063 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8064 kvm_max_guest_tsc_khz = max;
8065
ad721883 8066 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8067 }
ad721883 8068
9e9c3fe4
NA		 8069 kvm_init_msr_list();
8070 return 0;
e9b11c17
ZX		 8071}
8072
8073void kvm_arch_hardware_unsetup(void)
8074{
8075 kvm_x86_ops->hardware_unsetup();
8076}
8077
8078void kvm_arch_check_processor_compat(void *rtn)
8079{
8080 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8081}
8082
8083bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8084{
8085 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8086}
8087EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8088
8089bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8090{
8091 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8092}
8093
54e9818f 8094struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8095EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8096
e9b11c17
ZX		 8097int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8098{
8099 struct page *page;
e9b11c17
ZX		 8100 int r;
8101
b2a05fef 8102 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8103 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8104 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8105 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8106 else
a4535290 8107 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8108
8109 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8110 if (!page) {
8111 r = -ENOMEM;
8112 goto fail;
8113 }
ad312c7c 8114 vcpu->arch.pio_data = page_address(page);
e9b11c17 8115
cc578287 8116 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8117
e9b11c17
ZX		 8118 r = kvm_mmu_create(vcpu);
8119 if (r < 0)
8120 goto fail_free_pio_data;
8121
26de7988 8122 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8123 r = kvm_create_lapic(vcpu);
8124 if (r < 0)
8125 goto fail_mmu_destroy;
54e9818f
GN		 8126 } else
8127 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8128
890ca9ae
HY		 8129 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8130 GFP_KERNEL);
8131 if (!vcpu->arch.mce_banks) {
8132 r = -ENOMEM;
443c39bc 8133 goto fail_free_lapic;
890ca9ae
HY		 8134 }
8135 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8136
f1797359
WY		 8137 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8138 r = -ENOMEM;
f5f48ee1 8139 goto fail_free_mce_banks;
f1797359 8140 }
f5f48ee1 8141
0ee6a517 8142 fx_init(vcpu);
66f7b72e 8143
4344ee98 8144 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8145
5a4f55cd
EK		 8146 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8147
74545705
RK		 8148 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8149
af585b92 8150 kvm_async_pf_hash_reset(vcpu);
f5132b01 8151 kvm_pmu_init(vcpu);
af585b92 8152
1c1a9ce9 8153 vcpu->arch.pending_external_vector = -1;
de63ad4c 8154 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8155
5c919412
AS		 8156 kvm_hv_vcpu_init(vcpu);
8157
e9b11c17 8158 return 0;
0ee6a517 8159
f5f48ee1
SY		 8160fail_free_mce_banks:
8161 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8162fail_free_lapic:
8163 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8164fail_mmu_destroy:
8165 kvm_mmu_destroy(vcpu);
8166fail_free_pio_data:
ad312c7c 8167 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8168fail:
8169 return r;
8170}
8171
8172void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8173{
f656ce01
MT		 8174 int idx;
8175
1f4b34f8 8176 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8177 kvm_pmu_destroy(vcpu);
36cb93fd 8178 kfree(vcpu->arch.mce_banks);
e9b11c17 8179 kvm_free_lapic(vcpu);
f656ce01 8180 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8181 kvm_mmu_destroy(vcpu);
f656ce01 8182 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8183 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8184 if (!lapic_in_kernel(vcpu))
54e9818f 8185 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8186}
d19a9cd2 8187
e790d9ef
RK		 8188void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8189{
ae97a3b8 8190 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8191}
8192
e08b9637 8193int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8194{
e08b9637
CO		 8195 if (type)
8196 return -EINVAL;
8197
6ef768fa 8198 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8199 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8200 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8201 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8202 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8203
5550af4d
SY		 8204 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8205 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8206 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8207 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8208 &kvm->arch.irq_sources_bitmap);
5550af4d 8209
038f8c11 8210 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8211 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8212 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8213 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8214
108b249c 8215 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8216 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8217
7e44e449 8218 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8219 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8220
0eb05bf2 8221 kvm_page_track_init(kvm);
13d268ca 8222 kvm_mmu_init_vm(kvm);
0eb05bf2 8223
03543133
SS		 8224 if (kvm_x86_ops->vm_init)
8225 return kvm_x86_ops->vm_init(kvm);
8226
d89f5eff 8227 return 0;
d19a9cd2
ZX		 8228}
8229
8230static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8231{
ec7660cc 8232 vcpu_load(vcpu);
d19a9cd2
ZX		 8233 kvm_mmu_unload(vcpu);
8234 vcpu_put(vcpu);
8235}
8236
8237static void kvm_free_vcpus(struct kvm *kvm)
8238{
8239 unsigned int i;
988a2cae 8240 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8241
8242 /*
8243 * Unpin any mmu pages first.
8244 */
af585b92
GN		 8245 kvm_for_each_vcpu(i, vcpu, kvm) {
8246 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8247 kvm_unload_vcpu_mmu(vcpu);
af585b92 8248 }
988a2cae
GN		 8249 kvm_for_each_vcpu(i, vcpu, kvm)
8250 kvm_arch_vcpu_free(vcpu);
8251
8252 mutex_lock(&kvm->lock);
8253 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8254 kvm->vcpus[i] = NULL;
d19a9cd2 8255
988a2cae
GN		 8256 atomic_set(&kvm->online_vcpus, 0);
8257 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8258}
8259
ad8ba2cd
SY		 8260void kvm_arch_sync_events(struct kvm *kvm)
8261{
332967a3 8262 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8263 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8264 kvm_free_pit(kvm);
ad8ba2cd
SY		 8265}
8266
1d8007bd 8267int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8268{
8269 int i, r;
25188b99 8270 unsigned long hva;
f0d648bd
PB		 8271 struct kvm_memslots *slots = kvm_memslots(kvm);
8272 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8273
8274 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8275 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8276 return -EINVAL;
9da0e4d5 8277
f0d648bd
PB		 8278 slot = id_to_memslot(slots, id);
8279 if (size) {
b21629da 8280 if (slot->npages)
f0d648bd
PB		 8281 return -EEXIST;
8282
8283 /*
8284 * MAP_SHARED to prevent internal slot pages from being moved
8285 * by fork()/COW.
8286 */
8287 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8288 MAP_SHARED | MAP_ANONYMOUS, 0);
8289 if (IS_ERR((void *)hva))
8290 return PTR_ERR((void *)hva);
8291 } else {
8292 if (!slot->npages)
8293 return 0;
8294
8295 hva = 0;
8296 }
8297
8298 old = *slot;
9da0e4d5 8299 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8300 struct kvm_userspace_memory_region m;
9da0e4d5 8301
1d8007bd
PB		 8302 m.slot = id | (i << 16);
8303 m.flags = 0;
8304 m.guest_phys_addr = gpa;
f0d648bd 8305 m.userspace_addr = hva;
1d8007bd 8306 m.memory_size = size;
9da0e4d5
PB		 8307 r = __kvm_set_memory_region(kvm, &m);
8308 if (r < 0)
8309 return r;
8310 }
8311
f0d648bd
PB		 8312 if (!size) {
8313 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8314 WARN_ON(r < 0);
8315 }
8316
9da0e4d5
PB		 8317 return 0;
8318}
8319EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8320
1d8007bd 8321int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8322{
8323 int r;
8324
8325 mutex_lock(&kvm->slots_lock);
1d8007bd 8326 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8327 mutex_unlock(&kvm->slots_lock);
8328
8329 return r;
8330}
8331EXPORT_SYMBOL_GPL(x86_set_memory_region);
8332
d19a9cd2
ZX		 8333void kvm_arch_destroy_vm(struct kvm *kvm)
8334{
27469d29
AH		 8335 if (current->mm == kvm->mm) {
8336 /*
8337 * Free memory regions allocated on behalf of userspace,
8338 * unless the the memory map has changed due to process exit
8339 * or fd copying.
8340 */
1d8007bd
PB		 8341 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8342 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8343 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8344 }
03543133
SS		 8345 if (kvm_x86_ops->vm_destroy)
8346 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8347 kvm_pic_destroy(kvm);
8348 kvm_ioapic_destroy(kvm);
d19a9cd2 8349 kvm_free_vcpus(kvm);
af1bae54 8350 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8351 kvm_mmu_uninit_vm(kvm);
2beb6dad 8352 kvm_page_track_cleanup(kvm);
d19a9cd2 8353}
0de10343 8354
5587027c 8355void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8356 struct kvm_memory_slot *dont)
8357{
8358 int i;
8359
d89cc617
TY		 8360 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8361 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8362 kvfree(free->arch.rmap[i]);
d89cc617 8363 free->arch.rmap[i] = NULL;
77d11309 8364 }
d89cc617
TY		 8365 if (i == 0)
8366 continue;
8367
8368 if (!dont || free->arch.lpage_info[i - 1] !=
8369 dont->arch.lpage_info[i - 1]) {
548ef284 8370 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8371 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8372 }
8373 }
21ebbeda
XG		 8374
8375 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8376}
8377
5587027c
AK		 8378int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8379 unsigned long npages)
db3fe4eb
TY		 8380{
8381 int i;
8382
d89cc617 8383 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8384 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8385 unsigned long ugfn;
8386 int lpages;
d89cc617 8387 int level = i + 1;
db3fe4eb
TY		 8388
8389 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8390 slot->base_gfn, level) + 1;
8391
d89cc617 8392 slot->arch.rmap[i] =
a7c3e901 8393 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8394 if (!slot->arch.rmap[i])
77d11309 8395 goto out_free;
d89cc617
TY		 8396 if (i == 0)
8397 continue;
77d11309 8398
a7c3e901 8399 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8400 if (!linfo)
db3fe4eb
TY		 8401 goto out_free;
8402
92f94f1e
XG		 8403 slot->arch.lpage_info[i - 1] = linfo;
8404
db3fe4eb 8405 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8406 linfo[0].disallow_lpage = 1;
db3fe4eb 8407 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8408 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8409 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8410 /*
8411 * If the gfn and userspace address are not aligned wrt each
8412 * other, or if explicitly asked to, disable large page
8413 * support for this slot
8414 */
8415 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8416 !kvm_largepages_enabled()) {
8417 unsigned long j;
8418
8419 for (j = 0; j < lpages; ++j)
92f94f1e 8420 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8421 }
8422 }
8423
21ebbeda
XG		 8424 if (kvm_page_track_create_memslot(slot, npages))
8425 goto out_free;
8426
db3fe4eb
TY		 8427 return 0;
8428
8429out_free:
d89cc617 8430 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8431 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8432 slot->arch.rmap[i] = NULL;
8433 if (i == 0)
8434 continue;
8435
548ef284 8436 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8437 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8438 }
8439 return -ENOMEM;
8440}
8441
15f46015 8442void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8443{
e6dff7d1
TY		 8444 /*
8445 * memslots->generation has been incremented.
8446 * mmio generation may have reached its maximum value.
8447 */
54bf36aa 8448 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8449}
8450
f7784b8e
MT		 8451int kvm_arch_prepare_memory_region(struct kvm *kvm,
8452 struct kvm_memory_slot *memslot,
09170a49 8453 const struct kvm_userspace_memory_region *mem,
7b6195a9 8454 enum kvm_mr_change change)
0de10343 8455{
f7784b8e
MT		 8456 return 0;
8457}
8458
88178fd4
KH		 8459static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8460 struct kvm_memory_slot *new)
8461{
8462 /* Still write protect RO slot */
8463 if (new->flags & KVM_MEM_READONLY) {
8464 kvm_mmu_slot_remove_write_access(kvm, new);
8465 return;
8466 }
8467
8468 /*
8469 * Call kvm_x86_ops dirty logging hooks when they are valid.
8470 *
8471 * kvm_x86_ops->slot_disable_log_dirty is called when:
8472 *
8473 * - KVM_MR_CREATE with dirty logging is disabled
8474 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8475 *
8476 * The reason is, in case of PML, we need to set D-bit for any slots
8477 * with dirty logging disabled in order to eliminate unnecessary GPA
8478 * logging in PML buffer (and potential PML buffer full VMEXT). This
8479 * guarantees leaving PML enabled during guest's lifetime won't have
8480 * any additonal overhead from PML when guest is running with dirty
8481 * logging disabled for memory slots.
8482 *
8483 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8484 * to dirty logging mode.
8485 *
8486 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8487 *
8488 * In case of write protect:
8489 *
8490 * Write protect all pages for dirty logging.
8491 *
8492 * All the sptes including the large sptes which point to this
8493 * slot are set to readonly. We can not create any new large
8494 * spte on this slot until the end of the logging.
8495 *
8496 * See the comments in fast_page_fault().
8497 */
8498 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8499 if (kvm_x86_ops->slot_enable_log_dirty)
8500 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8501 else
8502 kvm_mmu_slot_remove_write_access(kvm, new);
8503 } else {
8504 if (kvm_x86_ops->slot_disable_log_dirty)
8505 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8506 }
8507}
8508
f7784b8e 8509void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8510 const struct kvm_userspace_memory_region *mem,
8482644a 8511 const struct kvm_memory_slot *old,
f36f3f28 8512 const struct kvm_memory_slot *new,
8482644a 8513 enum kvm_mr_change change)
f7784b8e 8514{
8482644a 8515 int nr_mmu_pages = 0;
f7784b8e 8516
48c0e4e9
XG		 8517 if (!kvm->arch.n_requested_mmu_pages)
8518 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8519
48c0e4e9 8520 if (nr_mmu_pages)
0de10343 8521 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8522
3ea3b7fa
WL		 8523 /*
8524 * Dirty logging tracks sptes in 4k granularity, meaning that large
8525 * sptes have to be split. If live migration is successful, the guest
8526 * in the source machine will be destroyed and large sptes will be
8527 * created in the destination. However, if the guest continues to run
8528 * in the source machine (for example if live migration fails), small
8529 * sptes will remain around and cause bad performance.
8530 *
8531 * Scan sptes if dirty logging has been stopped, dropping those
8532 * which can be collapsed into a single large-page spte. Later
8533 * page faults will create the large-page sptes.
8534 */
8535 if ((change != KVM_MR_DELETE) &&
8536 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8537 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8538 kvm_mmu_zap_collapsible_sptes(kvm, new);
8539
c972f3b1 8540 /*
88178fd4 8541 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8542 *
88178fd4
KH		 8543 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8544 * been zapped so no dirty logging staff is needed for old slot. For
8545 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8546 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8547 *
8548 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8549 */
88178fd4 8550 if (change != KVM_MR_DELETE)
f36f3f28 8551 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8552}
1d737c8a 8553
2df72e9b 8554void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8555{
6ca18b69 8556 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8557}
8558
2df72e9b
MT		 8559void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8560 struct kvm_memory_slot *slot)
8561{
ae7cd873 8562 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8563}
8564
5d9bc648
PB		 8565static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8566{
8567 if (!list_empty_careful(&vcpu->async_pf.done))
8568 return true;
8569
8570 if (kvm_apic_has_events(vcpu))
8571 return true;
8572
8573 if (vcpu->arch.pv.pv_unhalted)
8574 return true;
8575
a5f01f8e
WL		 8576 if (vcpu->arch.exception.pending)
8577 return true;
8578
47a66eed
Z		 8579 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8580 (vcpu->arch.nmi_pending &&
8581 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8582 return true;
8583
47a66eed
Z		 8584 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8585 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8586 return true;
8587
5d9bc648
PB		 8588 if (kvm_arch_interrupt_allowed(vcpu) &&
8589 kvm_cpu_has_interrupt(vcpu))
8590 return true;
8591
1f4b34f8
AS		 8592 if (kvm_hv_has_stimer_pending(vcpu))
8593 return true;
8594
5d9bc648
PB		 8595 return false;
8596}
8597
1d737c8a
ZX		 8598int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8599{
5d9bc648 8600 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8601}
5736199a 8602
199b5763
LM		 8603bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8604{
de63ad4c 8605 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8606}
8607
b6d33834 8608int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8609{
b6d33834 8610 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8611}
78646121
GN		 8612
8613int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8614{
8615 return kvm_x86_ops->interrupt_allowed(vcpu);
8616}
229456fc 8617
82b32774 8618unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8619{
82b32774
NA		 8620 if (is_64_bit_mode(vcpu))
8621 return kvm_rip_read(vcpu);
8622 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8623 kvm_rip_read(vcpu));
8624}
8625EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8626
82b32774
NA		 8627bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8628{
8629 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8630}
8631EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8632
94fe45da
JK		 8633unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8634{
8635 unsigned long rflags;
8636
8637 rflags = kvm_x86_ops->get_rflags(vcpu);
8638 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8639 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8640 return rflags;
8641}
8642EXPORT_SYMBOL_GPL(kvm_get_rflags);
8643
6addfc42 8644static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8645{
8646 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8647 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8648 rflags |= X86_EFLAGS_TF;
94fe45da 8649 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8650}
8651
8652void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8653{
8654 __kvm_set_rflags(vcpu, rflags);
3842d135 8655 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8656}
8657EXPORT_SYMBOL_GPL(kvm_set_rflags);
8658
56028d08
GN		 8659void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8660{
8661 int r;
8662
fb67e14f 8663 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8664 work->wakeup_all)
56028d08
GN		 8665 return;
8666
8667 r = kvm_mmu_reload(vcpu);
8668 if (unlikely(r))
8669 return;
8670
fb67e14f
XG		 8671 if (!vcpu->arch.mmu.direct_map &&
8672 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8673 return;
8674
56028d08
GN		 8675 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8676}
8677
af585b92
GN		 8678static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8679{
8680 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8681}
8682
8683static inline u32 kvm_async_pf_next_probe(u32 key)
8684{
8685 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8686}
8687
8688static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8689{
8690 u32 key = kvm_async_pf_hash_fn(gfn);
8691
8692 while (vcpu->arch.apf.gfns[key] != ~0)
8693 key = kvm_async_pf_next_probe(key);
8694
8695 vcpu->arch.apf.gfns[key] = gfn;
8696}
8697
8698static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8699{
8700 int i;
8701 u32 key = kvm_async_pf_hash_fn(gfn);
8702
8703 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8704 (vcpu->arch.apf.gfns[key] != gfn &&
8705 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8706 key = kvm_async_pf_next_probe(key);
8707
8708 return key;
8709}
8710
8711bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8712{
8713 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8714}
8715
8716static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8717{
8718 u32 i, j, k;
8719
8720 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8721 while (true) {
8722 vcpu->arch.apf.gfns[i] = ~0;
8723 do {
8724 j = kvm_async_pf_next_probe(j);
8725 if (vcpu->arch.apf.gfns[j] == ~0)
8726 return;
8727 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8728 /*
8729 * k lies cyclically in ]i,j]
8730 * | i.k.j |
8731 * |....j i.k.| or |.k..j i...|
8732 */
8733 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8734 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8735 i = j;
8736 }
8737}
8738
7c90705b
GN		 8739static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8740{
4e335d9e
PB		 8741
8742 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8743 sizeof(val));
7c90705b
GN		 8744}
8745
9a6e7c39
WL		 8746static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8747{
8748
8749 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8750 sizeof(u32));
8751}
8752
af585b92
GN		 8753void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8754 struct kvm_async_pf *work)
8755{
6389ee94
AK		 8756 struct x86_exception fault;
8757
7c90705b 8758 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8759 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8760
8761 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8762 (vcpu->arch.apf.send_user_only &&
8763 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8764 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8765 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8766 fault.vector = PF_VECTOR;
8767 fault.error_code_valid = true;
8768 fault.error_code = 0;
8769 fault.nested_page_fault = false;
8770 fault.address = work->arch.token;
adfe20fb 8771 fault.async_page_fault = true;
6389ee94 8772 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8773 }
af585b92
GN		 8774}
8775
8776void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8777 struct kvm_async_pf *work)
8778{
6389ee94 8779 struct x86_exception fault;
9a6e7c39 8780 u32 val;
6389ee94 8781
f2e10669 8782 if (work->wakeup_all)
7c90705b
GN		 8783 work->arch.token = ~0; /* broadcast wakeup */
8784 else
8785 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8786 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8787
9a6e7c39
WL		 8788 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8789 !apf_get_user(vcpu, &val)) {
8790 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8791 vcpu->arch.exception.pending &&
8792 vcpu->arch.exception.nr == PF_VECTOR &&
8793 !apf_put_user(vcpu, 0)) {
8794 vcpu->arch.exception.injected = false;
8795 vcpu->arch.exception.pending = false;
8796 vcpu->arch.exception.nr = 0;
8797 vcpu->arch.exception.has_error_code = false;
8798 vcpu->arch.exception.error_code = 0;
8799 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8800 fault.vector = PF_VECTOR;
8801 fault.error_code_valid = true;
8802 fault.error_code = 0;
8803 fault.nested_page_fault = false;
8804 fault.address = work->arch.token;
8805 fault.async_page_fault = true;
8806 kvm_inject_page_fault(vcpu, &fault);
8807 }
7c90705b 8808 }
e6d53e3b 8809 vcpu->arch.apf.halted = false;
a4fa1635 8810 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8811}
8812
8813bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8814{
8815 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8816 return true;
8817 else
9bc1f09f 8818 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8819}
8820
5544eb9b
PB		 8821void kvm_arch_start_assignment(struct kvm *kvm)
8822{
8823 atomic_inc(&kvm->arch.assigned_device_count);
8824}
8825EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8826
8827void kvm_arch_end_assignment(struct kvm *kvm)
8828{
8829 atomic_dec(&kvm->arch.assigned_device_count);
8830}
8831EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8832
8833bool kvm_arch_has_assigned_device(struct kvm *kvm)
8834{
8835 return atomic_read(&kvm->arch.assigned_device_count);
8836}
8837EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8838
e0f0bbc5
AW		 8839void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8840{
8841 atomic_inc(&kvm->arch.noncoherent_dma_count);
8842}
8843EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8844
8845void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8846{
8847 atomic_dec(&kvm->arch.noncoherent_dma_count);
8848}
8849EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8850
8851bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8852{
8853 return atomic_read(&kvm->arch.noncoherent_dma_count);
8854}
8855EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8856
14717e20
AW		 8857bool kvm_arch_has_irq_bypass(void)
8858{
8859 return kvm_x86_ops->update_pi_irte != NULL;
8860}
8861
87276880
FW		 8862int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8863 struct irq_bypass_producer *prod)
8864{
8865 struct kvm_kernel_irqfd *irqfd =
8866 container_of(cons, struct kvm_kernel_irqfd, consumer);
8867
14717e20 8868 irqfd->producer = prod;
87276880 8869
14717e20
AW		 8870 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8871 prod->irq, irqfd->gsi, 1);
87276880
FW		 8872}
8873
8874void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8875 struct irq_bypass_producer *prod)
8876{
8877 int ret;
8878 struct kvm_kernel_irqfd *irqfd =
8879 container_of(cons, struct kvm_kernel_irqfd, consumer);
8880
87276880
FW		 8881 WARN_ON(irqfd->producer != prod);
8882 irqfd->producer = NULL;
8883
8884 /*
8885 * When producer of consumer is unregistered, we change back to
8886 * remapped mode, so we can re-use the current implementation
bb3541f1 8887 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8888 * int this case doesn't want to receive the interrupts.
8889 */
8890 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8891 if (ret)
8892 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8893 " fails: %d\n", irqfd->consumer.token, ret);
8894}
8895
8896int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8897 uint32_t guest_irq, bool set)
8898{
8899 if (!kvm_x86_ops->update_pi_irte)
8900 return -EINVAL;
8901
8902 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8903}
8904
52004014
FW		 8905bool kvm_vector_hashing_enabled(void)
8906{
8907 return vector_hashing;
8908}
8909EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8910
229456fc 8911EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8912EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8913EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8914EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8915EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8916EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8918EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8919EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8920EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8921EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8922EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8923EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8924EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8925EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8926EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8927EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8928EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8929EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)