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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 | 17 | */ |
8d20bd63 | 18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
043405e1 | 19 | |
edf88417 | 20 | #include <linux/kvm_host.h> |
313a3dc7 | 21 | #include "irq.h" |
88197e6a | 22 | #include "ioapic.h" |
1d737c8a | 23 | #include "mmu.h" |
7837699f | 24 | #include "i8254.h" |
37817f29 | 25 | #include "tss.h" |
5fdbf976 | 26 | #include "kvm_cache_regs.h" |
2f728d66 | 27 | #include "kvm_emulate.h" |
58ea7cf7 | 28 | #include "mmu/page_track.h" |
26eef70c | 29 | #include "x86.h" |
00b27a3e | 30 | #include "cpuid.h" |
474a5bb9 | 31 | #include "pmu.h" |
e83d5887 | 32 | #include "hyperv.h" |
8df14af4 | 33 | #include "lapic.h" |
23200b7a | 34 | #include "xen.h" |
b0b42197 | 35 | #include "smm.h" |
313a3dc7 | 36 | |
18068523 | 37 | #include <linux/clocksource.h> |
4d5c5d0f | 38 | #include <linux/interrupt.h> |
313a3dc7 CO |
39 | #include <linux/kvm.h> |
40 | #include <linux/fs.h> | |
41 | #include <linux/vmalloc.h> | |
1767e931 PG |
42 | #include <linux/export.h> |
43 | #include <linux/moduleparam.h> | |
0de10343 | 44 | #include <linux/mman.h> |
2bacc55c | 45 | #include <linux/highmem.h> |
19de40a8 | 46 | #include <linux/iommu.h> |
c8076604 | 47 | #include <linux/cpufreq.h> |
18863bdd | 48 | #include <linux/user-return-notifier.h> |
a983fb23 | 49 | #include <linux/srcu.h> |
5a0e3ad6 | 50 | #include <linux/slab.h> |
ff9d07a0 | 51 | #include <linux/perf_event.h> |
7bee342a | 52 | #include <linux/uaccess.h> |
af585b92 | 53 | #include <linux/hash.h> |
a1b60c1c | 54 | #include <linux/pci.h> |
16e8d74d MT |
55 | #include <linux/timekeeper_internal.h> |
56 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
57 | #include <linux/kvm_irqfd.h> |
58 | #include <linux/irqbypass.h> | |
3905f9ad | 59 | #include <linux/sched/stat.h> |
0c5f81da | 60 | #include <linux/sched/isolation.h> |
d0ec49d4 | 61 | #include <linux/mem_encrypt.h> |
72c3c0fe | 62 | #include <linux/entry-kvm.h> |
7d62874f | 63 | #include <linux/suspend.h> |
4c8c3c7f | 64 | #include <linux/smp.h> |
3905f9ad | 65 | |
4c8c3c7f | 66 | #include <trace/events/ipi.h> |
aec51dc4 | 67 | #include <trace/events/kvm.h> |
2ed152af | 68 | |
24f1e32c | 69 | #include <asm/debugreg.h> |
d825ed0a | 70 | #include <asm/msr.h> |
a5f61300 | 71 | #include <asm/desc.h> |
890ca9ae | 72 | #include <asm/mce.h> |
784a4661 | 73 | #include <asm/pkru.h> |
f89e32e0 | 74 | #include <linux/kernel_stat.h> |
a0ff0611 TG |
75 | #include <asm/fpu/api.h> |
76 | #include <asm/fpu/xcr.h> | |
77 | #include <asm/fpu/xstate.h> | |
1d5f066e | 78 | #include <asm/pvclock.h> |
217fc9cf | 79 | #include <asm/div64.h> |
efc64404 | 80 | #include <asm/irq_remapping.h> |
b0c39dc6 | 81 | #include <asm/mshyperv.h> |
0092e434 | 82 | #include <asm/hypervisor.h> |
9715092f | 83 | #include <asm/tlbflush.h> |
bf8c55d8 | 84 | #include <asm/intel_pt.h> |
b3dc0695 | 85 | #include <asm/emulate_prefix.h> |
fe7e9488 | 86 | #include <asm/sgx.h> |
dd2cb348 | 87 | #include <clocksource/hyperv_timer.h> |
043405e1 | 88 | |
d1898b73 DH |
89 | #define CREATE_TRACE_POINTS |
90 | #include "trace.h" | |
91 | ||
313a3dc7 | 92 | #define MAX_IO_MSRS 256 |
890ca9ae | 93 | #define KVM_MAX_MCE_BANKS 32 |
938c8745 SC |
94 | |
95 | struct kvm_caps kvm_caps __read_mostly = { | |
96 | .supported_mce_cap = MCG_CTL_P | MCG_SER_P, | |
97 | }; | |
98 | EXPORT_SYMBOL_GPL(kvm_caps); | |
890ca9ae | 99 | |
6e37ec88 SC |
100 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
101 | ||
0f65dd70 | 102 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 103 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 104 | |
50a37eb4 JR |
105 | /* EFER defaults: |
106 | * - enable syscall per default because its emulated by KVM | |
107 | * - enable LME and LMA per default on 64 bit KVM | |
108 | */ | |
109 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
110 | static |
111 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 112 | #else |
1260edbe | 113 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 114 | #endif |
313a3dc7 | 115 | |
b11306b5 SC |
116 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
117 | ||
0dbb1123 AK |
118 | #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) |
119 | ||
ba7bb663 DD |
120 | #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE |
121 | ||
c519265f RK |
122 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
123 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 124 | |
cb142eb7 | 125 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 126 | static void process_nmi(struct kvm_vcpu *vcpu); |
6addfc42 | 127 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
128 | static void store_regs(struct kvm_vcpu *vcpu); |
129 | static int sync_regs(struct kvm_vcpu *vcpu); | |
d2f7d498 | 130 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); |
674eea0f | 131 | |
6dba9403 ML |
132 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); |
133 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); | |
134 | ||
3af4a9e6 | 135 | static DEFINE_MUTEX(vendor_module_lock); |
afaf0b2f | 136 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
97896d04 | 137 | |
9af5471b JB |
138 | #define KVM_X86_OP(func) \ |
139 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
140 | *(((struct kvm_x86_ops *)0)->func)); | |
e4fc23ba | 141 | #define KVM_X86_OP_OPTIONAL KVM_X86_OP |
5be2226f | 142 | #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP |
9af5471b JB |
143 | #include <asm/kvm-x86-ops.h> |
144 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
145 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
9af5471b | 146 | |
893590c7 | 147 | static bool __read_mostly ignore_msrs = 0; |
26951ec8 | 148 | module_param(ignore_msrs, bool, 0644); |
ed85c068 | 149 | |
d855066f | 150 | bool __read_mostly report_ignored_msrs = true; |
26951ec8 | 151 | module_param(report_ignored_msrs, bool, 0644); |
d855066f | 152 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 153 | |
4c27625b | 154 | unsigned int min_timer_period_us = 200; |
26951ec8 | 155 | module_param(min_timer_period_us, uint, 0644); |
9ed96e87 | 156 | |
630994b3 | 157 | static bool __read_mostly kvmclock_periodic_sync = true; |
26951ec8 | 158 | module_param(kvmclock_periodic_sync, bool, 0444); |
630994b3 | 159 | |
cc578287 | 160 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 161 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
26951ec8 | 162 | module_param(tsc_tolerance_ppm, uint, 0644); |
cc578287 | 163 | |
c3941d9e SC |
164 | /* |
165 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
d9f6e12f | 166 | * adaptive tuning starting from default advancement of 1000ns. '0' disables |
c3941d9e | 167 | * advancement entirely. Any other value is used as-is and disables adaptive |
d9f6e12f | 168 | * tuning, i.e. allows privileged userspace to set an exact advancement time. |
c3941d9e SC |
169 | */ |
170 | static int __read_mostly lapic_timer_advance_ns = -1; | |
26951ec8 | 171 | module_param(lapic_timer_advance_ns, int, 0644); |
d0659d94 | 172 | |
52004014 | 173 | static bool __read_mostly vector_hashing = true; |
26951ec8 | 174 | module_param(vector_hashing, bool, 0444); |
52004014 | 175 | |
c4ae60e4 | 176 | bool __read_mostly enable_vmware_backdoor = false; |
26951ec8 | 177 | module_param(enable_vmware_backdoor, bool, 0444); |
c4ae60e4 LA |
178 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); |
179 | ||
d500e1ed SC |
180 | /* |
181 | * Flags to manipulate forced emulation behavior (any non-zero value will | |
182 | * enable forced emulation). | |
183 | */ | |
184 | #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1) | |
185 | static int __read_mostly force_emulation_prefix; | |
40aaa5b6 | 186 | module_param(force_emulation_prefix, int, 0644); |
6c86eedc | 187 | |
0c5f81da | 188 | int __read_mostly pi_inject_timer = -1; |
26951ec8 | 189 | module_param(pi_inject_timer, bint, 0644); |
0c5f81da | 190 | |
4732f244 LX |
191 | /* Enable/disable PMU virtualization */ |
192 | bool __read_mostly enable_pmu = true; | |
193 | EXPORT_SYMBOL_GPL(enable_pmu); | |
194 | module_param(enable_pmu, bool, 0444); | |
195 | ||
cb00a70b | 196 | bool __read_mostly eager_page_split = true; |
a3fe5dbd DM |
197 | module_param(eager_page_split, bool, 0644); |
198 | ||
6f0f2d5e | 199 | /* Enable/disable SMT_RSB bug mitigation */ |
944a8dad | 200 | static bool __read_mostly mitigate_smt_rsb; |
6f0f2d5e TL |
201 | module_param(mitigate_smt_rsb, bool, 0444); |
202 | ||
7e34fbd0 SC |
203 | /* |
204 | * Restoring the host value for MSRs that are only consumed when running in | |
205 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
206 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
207 | */ | |
208 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 209 | |
7e34fbd0 | 210 | struct kvm_user_return_msrs { |
18863bdd AK |
211 | struct user_return_notifier urn; |
212 | bool registered; | |
7e34fbd0 | 213 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
214 | u64 host; |
215 | u64 curr; | |
7e34fbd0 | 216 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
217 | }; |
218 | ||
9cc39a5a SC |
219 | u32 __read_mostly kvm_nr_uret_msrs; |
220 | EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); | |
221 | static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; | |
7e34fbd0 | 222 | static struct kvm_user_return_msrs __percpu *user_return_msrs; |
18863bdd | 223 | |
cfc48181 SC |
224 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
225 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
226 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
86aff7a4 | 227 | | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) |
cfc48181 | 228 | |
91661989 SC |
229 | u64 __read_mostly host_efer; |
230 | EXPORT_SYMBOL_GPL(host_efer); | |
231 | ||
b96e6506 | 232 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
233 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
234 | ||
fdf513e3 VK |
235 | bool __read_mostly enable_apicv = true; |
236 | EXPORT_SYMBOL_GPL(enable_apicv); | |
237 | ||
86137773 TL |
238 | u64 __read_mostly host_xss; |
239 | EXPORT_SYMBOL_GPL(host_xss); | |
139a12cf | 240 | |
a2fd5d02 SC |
241 | u64 __read_mostly host_arch_capabilities; |
242 | EXPORT_SYMBOL_GPL(host_arch_capabilities); | |
243 | ||
fcfe1bae JZ |
244 | const struct _kvm_stats_desc kvm_vm_stats_desc[] = { |
245 | KVM_GENERIC_VM_STATS(), | |
246 | STATS_DESC_COUNTER(VM, mmu_shadow_zapped), | |
247 | STATS_DESC_COUNTER(VM, mmu_pte_write), | |
248 | STATS_DESC_COUNTER(VM, mmu_pde_zapped), | |
249 | STATS_DESC_COUNTER(VM, mmu_flooded), | |
250 | STATS_DESC_COUNTER(VM, mmu_recycled), | |
251 | STATS_DESC_COUNTER(VM, mmu_cache_miss), | |
252 | STATS_DESC_ICOUNTER(VM, mmu_unsync), | |
71f51d2c MZ |
253 | STATS_DESC_ICOUNTER(VM, pages_4k), |
254 | STATS_DESC_ICOUNTER(VM, pages_2m), | |
255 | STATS_DESC_ICOUNTER(VM, pages_1g), | |
fcfe1bae | 256 | STATS_DESC_ICOUNTER(VM, nx_lpage_splits), |
ec1cf69c | 257 | STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), |
bc9e9e67 | 258 | STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) |
fcfe1bae | 259 | }; |
fcfe1bae JZ |
260 | |
261 | const struct kvm_stats_header kvm_vm_stats_header = { | |
262 | .name_size = KVM_STATS_NAME_SIZE, | |
263 | .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), | |
264 | .id_offset = sizeof(struct kvm_stats_header), | |
265 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
266 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
267 | sizeof(kvm_vm_stats_desc), | |
268 | }; | |
269 | ||
ce55c049 JZ |
270 | const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { |
271 | KVM_GENERIC_VCPU_STATS(), | |
1075d41e | 272 | STATS_DESC_COUNTER(VCPU, pf_taken), |
ce55c049 | 273 | STATS_DESC_COUNTER(VCPU, pf_fixed), |
1075d41e SC |
274 | STATS_DESC_COUNTER(VCPU, pf_emulate), |
275 | STATS_DESC_COUNTER(VCPU, pf_spurious), | |
276 | STATS_DESC_COUNTER(VCPU, pf_fast), | |
277 | STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created), | |
ce55c049 JZ |
278 | STATS_DESC_COUNTER(VCPU, pf_guest), |
279 | STATS_DESC_COUNTER(VCPU, tlb_flush), | |
280 | STATS_DESC_COUNTER(VCPU, invlpg), | |
281 | STATS_DESC_COUNTER(VCPU, exits), | |
282 | STATS_DESC_COUNTER(VCPU, io_exits), | |
283 | STATS_DESC_COUNTER(VCPU, mmio_exits), | |
284 | STATS_DESC_COUNTER(VCPU, signal_exits), | |
285 | STATS_DESC_COUNTER(VCPU, irq_window_exits), | |
286 | STATS_DESC_COUNTER(VCPU, nmi_window_exits), | |
287 | STATS_DESC_COUNTER(VCPU, l1d_flush), | |
288 | STATS_DESC_COUNTER(VCPU, halt_exits), | |
289 | STATS_DESC_COUNTER(VCPU, request_irq_exits), | |
290 | STATS_DESC_COUNTER(VCPU, irq_exits), | |
291 | STATS_DESC_COUNTER(VCPU, host_state_reload), | |
292 | STATS_DESC_COUNTER(VCPU, fpu_reload), | |
293 | STATS_DESC_COUNTER(VCPU, insn_emulation), | |
294 | STATS_DESC_COUNTER(VCPU, insn_emulation_fail), | |
295 | STATS_DESC_COUNTER(VCPU, hypercalls), | |
296 | STATS_DESC_COUNTER(VCPU, irq_injections), | |
297 | STATS_DESC_COUNTER(VCPU, nmi_injections), | |
298 | STATS_DESC_COUNTER(VCPU, req_event), | |
299 | STATS_DESC_COUNTER(VCPU, nested_run), | |
300 | STATS_DESC_COUNTER(VCPU, directed_yield_attempted), | |
301 | STATS_DESC_COUNTER(VCPU, directed_yield_successful), | |
6cd88243 PB |
302 | STATS_DESC_COUNTER(VCPU, preemption_reported), |
303 | STATS_DESC_COUNTER(VCPU, preemption_other), | |
63f4b210 | 304 | STATS_DESC_IBOOLEAN(VCPU, guest_mode), |
2f4073e0 | 305 | STATS_DESC_COUNTER(VCPU, notify_window_exits), |
ce55c049 | 306 | }; |
ce55c049 JZ |
307 | |
308 | const struct kvm_stats_header kvm_vcpu_stats_header = { | |
309 | .name_size = KVM_STATS_NAME_SIZE, | |
310 | .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), | |
311 | .id_offset = sizeof(struct kvm_stats_header), | |
312 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
313 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
314 | sizeof(kvm_vcpu_stats_desc), | |
315 | }; | |
316 | ||
2acf923e DC |
317 | u64 __read_mostly host_xcr0; |
318 | ||
c9b8b07c SC |
319 | static struct kmem_cache *x86_emulator_cache; |
320 | ||
6abe9c13 PX |
321 | /* |
322 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 323 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 324 | */ |
d632826f | 325 | static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) |
6abe9c13 PX |
326 | { |
327 | const char *op = write ? "wrmsr" : "rdmsr"; | |
328 | ||
329 | if (ignore_msrs) { | |
330 | if (report_ignored_msrs) | |
d383b314 TI |
331 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
332 | op, msr, data); | |
6abe9c13 | 333 | /* Mask the error */ |
cc4cb017 | 334 | return true; |
6abe9c13 | 335 | } else { |
d383b314 TI |
336 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
337 | op, msr, data); | |
cc4cb017 | 338 | return false; |
6abe9c13 PX |
339 | } |
340 | } | |
341 | ||
c9b8b07c SC |
342 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
343 | { | |
06add254 SC |
344 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
345 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
346 | ||
347 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 348 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
349 | SLAB_ACCOUNT, useroffset, |
350 | size - useroffset, NULL); | |
c9b8b07c SC |
351 | } |
352 | ||
b6785def | 353 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 354 | |
af585b92 GN |
355 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
356 | { | |
357 | int i; | |
dd03bcaa | 358 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
359 | vcpu->arch.apf.gfns[i] = ~0; |
360 | } | |
361 | ||
18863bdd AK |
362 | static void kvm_on_user_return(struct user_return_notifier *urn) |
363 | { | |
364 | unsigned slot; | |
7e34fbd0 SC |
365 | struct kvm_user_return_msrs *msrs |
366 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
367 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
368 | unsigned long flags; |
369 | ||
370 | /* | |
371 | * Disabling irqs at this point since the following code could be | |
372 | * interrupted and executed through kvm_arch_hardware_disable() | |
373 | */ | |
374 | local_irq_save(flags); | |
7e34fbd0 SC |
375 | if (msrs->registered) { |
376 | msrs->registered = false; | |
1650b4eb IA |
377 | user_return_notifier_unregister(urn); |
378 | } | |
379 | local_irq_restore(flags); | |
9cc39a5a | 380 | for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { |
7e34fbd0 | 381 | values = &msrs->values[slot]; |
2bf78fa7 | 382 | if (values->host != values->curr) { |
9cc39a5a | 383 | wrmsrl(kvm_uret_msrs_list[slot], values->host); |
2bf78fa7 | 384 | values->curr = values->host; |
18863bdd AK |
385 | } |
386 | } | |
18863bdd AK |
387 | } |
388 | ||
e5fda4bb | 389 | static int kvm_probe_user_return_msr(u32 msr) |
5104d7ff SC |
390 | { |
391 | u64 val; | |
392 | int ret; | |
393 | ||
394 | preempt_disable(); | |
395 | ret = rdmsrl_safe(msr, &val); | |
396 | if (ret) | |
397 | goto out; | |
398 | ret = wrmsrl_safe(msr, val); | |
399 | out: | |
400 | preempt_enable(); | |
401 | return ret; | |
402 | } | |
5104d7ff | 403 | |
e5fda4bb | 404 | int kvm_add_user_return_msr(u32 msr) |
2bf78fa7 | 405 | { |
e5fda4bb SC |
406 | BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); |
407 | ||
408 | if (kvm_probe_user_return_msr(msr)) | |
409 | return -1; | |
410 | ||
411 | kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; | |
412 | return kvm_nr_uret_msrs++; | |
18863bdd | 413 | } |
e5fda4bb | 414 | EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); |
18863bdd | 415 | |
8ea8b8d6 SC |
416 | int kvm_find_user_return_msr(u32 msr) |
417 | { | |
418 | int i; | |
419 | ||
9cc39a5a SC |
420 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
421 | if (kvm_uret_msrs_list[i] == msr) | |
8ea8b8d6 SC |
422 | return i; |
423 | } | |
424 | return -1; | |
425 | } | |
426 | EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); | |
427 | ||
7e34fbd0 | 428 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 429 | { |
05c19c2f | 430 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 431 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
432 | u64 value; |
433 | int i; | |
18863bdd | 434 | |
9cc39a5a SC |
435 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
436 | rdmsrl_safe(kvm_uret_msrs_list[i], &value); | |
7e34fbd0 SC |
437 | msrs->values[i].host = value; |
438 | msrs->values[i].curr = value; | |
05c19c2f | 439 | } |
18863bdd AK |
440 | } |
441 | ||
7e34fbd0 | 442 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 443 | { |
013f6a5d | 444 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 445 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 446 | int err; |
18863bdd | 447 | |
7e34fbd0 SC |
448 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
449 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 450 | return 0; |
9cc39a5a | 451 | err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); |
8b3c3104 AH |
452 | if (err) |
453 | return 1; | |
454 | ||
7e34fbd0 SC |
455 | msrs->values[slot].curr = value; |
456 | if (!msrs->registered) { | |
457 | msrs->urn.on_user_return = kvm_on_user_return; | |
458 | user_return_notifier_register(&msrs->urn); | |
459 | msrs->registered = true; | |
18863bdd | 460 | } |
8b3c3104 | 461 | return 0; |
18863bdd | 462 | } |
7e34fbd0 | 463 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 464 | |
13a34e06 | 465 | static void drop_user_return_notifiers(void) |
3548bab5 | 466 | { |
013f6a5d | 467 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 468 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 469 | |
7e34fbd0 SC |
470 | if (msrs->registered) |
471 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
472 | } |
473 | ||
6866b83e CO |
474 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
475 | { | |
8a5a87d9 | 476 | return vcpu->arch.apic_base; |
6866b83e | 477 | } |
6866b83e | 478 | |
58871649 JM |
479 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
480 | { | |
481 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
482 | } | |
483 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
484 | ||
58cb628d JK |
485 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
486 | { | |
58871649 JM |
487 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
488 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
a8ac864a | 489 | u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | |
d6321d49 | 490 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); |
58cb628d | 491 | |
58871649 | 492 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 493 | return 1; |
58871649 JM |
494 | if (!msr_info->host_initiated) { |
495 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
496 | return 1; | |
497 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
498 | return 1; | |
499 | } | |
58cb628d JK |
500 | |
501 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 502 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 503 | return 0; |
6866b83e | 504 | } |
6866b83e | 505 | |
ad0577c3 SC |
506 | /* |
507 | * Handle a fault on a hardware virtualization (VMX or SVM) instruction. | |
508 | * | |
509 | * Hardware virtualization extension instructions may fault if a reboot turns | |
510 | * off virtualization while processes are running. Usually after catching the | |
511 | * fault we just panic; during reboot instead the instruction is ignored. | |
512 | */ | |
513 | noinstr void kvm_spurious_fault(void) | |
e3ba45b8 GL |
514 | { |
515 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 516 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
517 | } |
518 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
519 | ||
3fd28fce ED |
520 | #define EXCPT_BENIGN 0 |
521 | #define EXCPT_CONTRIBUTORY 1 | |
522 | #define EXCPT_PF 2 | |
523 | ||
524 | static int exception_class(int vector) | |
525 | { | |
526 | switch (vector) { | |
527 | case PF_VECTOR: | |
528 | return EXCPT_PF; | |
529 | case DE_VECTOR: | |
530 | case TS_VECTOR: | |
531 | case NP_VECTOR: | |
532 | case SS_VECTOR: | |
533 | case GP_VECTOR: | |
534 | return EXCPT_CONTRIBUTORY; | |
535 | default: | |
536 | break; | |
537 | } | |
538 | return EXCPT_BENIGN; | |
539 | } | |
540 | ||
d6e8c854 NA |
541 | #define EXCPT_FAULT 0 |
542 | #define EXCPT_TRAP 1 | |
543 | #define EXCPT_ABORT 2 | |
544 | #define EXCPT_INTERRUPT 3 | |
5623f751 | 545 | #define EXCPT_DB 4 |
d6e8c854 NA |
546 | |
547 | static int exception_type(int vector) | |
548 | { | |
549 | unsigned int mask; | |
550 | ||
551 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
552 | return EXCPT_INTERRUPT; | |
553 | ||
554 | mask = 1 << vector; | |
555 | ||
5623f751 SC |
556 | /* |
557 | * #DBs can be trap-like or fault-like, the caller must check other CPU | |
558 | * state, e.g. DR6, to determine whether a #DB is a trap or fault. | |
559 | */ | |
560 | if (mask & (1 << DB_VECTOR)) | |
561 | return EXCPT_DB; | |
562 | ||
563 | if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
d6e8c854 NA |
564 | return EXCPT_TRAP; |
565 | ||
566 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
567 | return EXCPT_ABORT; | |
568 | ||
569 | /* Reserved exceptions will result in fault */ | |
570 | return EXCPT_FAULT; | |
571 | } | |
572 | ||
d4963e31 SC |
573 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu, |
574 | struct kvm_queued_exception *ex) | |
da998b46 | 575 | { |
d4963e31 | 576 | if (!ex->has_payload) |
da998b46 JM |
577 | return; |
578 | ||
d4963e31 | 579 | switch (ex->vector) { |
f10c729f JM |
580 | case DB_VECTOR: |
581 | /* | |
582 | * "Certain debug exceptions may clear bit 0-3. The | |
583 | * remaining contents of the DR6 register are never | |
584 | * cleared by the processor". | |
585 | */ | |
586 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
587 | /* | |
9a3ecd5e CQ |
588 | * In order to reflect the #DB exception payload in guest |
589 | * dr6, three components need to be considered: active low | |
590 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
591 | * DR6_BS and DR6_BT) | |
592 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
593 | * In the target guest dr6: | |
594 | * FIXED_1 bits should always be set. | |
595 | * Active low bits should be cleared if 1-setting in payload. | |
596 | * Active high bits should be set if 1-setting in payload. | |
597 | * | |
598 | * Note, the payload is compatible with the pending debug | |
599 | * exceptions/exit qualification under VMX, that active_low bits | |
600 | * are active high in payload. | |
601 | * So they need to be flipped for DR6. | |
f10c729f | 602 | */ |
9a3ecd5e | 603 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
d4963e31 SC |
604 | vcpu->arch.dr6 |= ex->payload; |
605 | vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW; | |
307f1cfa OU |
606 | |
607 | /* | |
608 | * The #DB payload is defined as compatible with the 'pending | |
609 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
610 | * defined in the 'pending debug exceptions' field (enabled | |
611 | * breakpoint), it is reserved and must be zero in DR6. | |
612 | */ | |
613 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 614 | break; |
da998b46 | 615 | case PF_VECTOR: |
d4963e31 | 616 | vcpu->arch.cr2 = ex->payload; |
da998b46 JM |
617 | break; |
618 | } | |
619 | ||
d4963e31 SC |
620 | ex->has_payload = false; |
621 | ex->payload = 0; | |
da998b46 JM |
622 | } |
623 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
624 | ||
7709aba8 SC |
625 | static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector, |
626 | bool has_error_code, u32 error_code, | |
627 | bool has_payload, unsigned long payload) | |
628 | { | |
629 | struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit; | |
630 | ||
631 | ex->vector = vector; | |
632 | ex->injected = false; | |
633 | ex->pending = true; | |
634 | ex->has_error_code = has_error_code; | |
635 | ex->error_code = error_code; | |
636 | ex->has_payload = has_payload; | |
637 | ex->payload = payload; | |
638 | } | |
639 | ||
f9697df2 ML |
640 | /* Forcibly leave the nested mode in cases like a vCPU reset */ |
641 | static void kvm_leave_nested(struct kvm_vcpu *vcpu) | |
642 | { | |
643 | kvm_x86_ops.nested_ops->leave_nested(vcpu); | |
644 | } | |
645 | ||
3fd28fce | 646 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 647 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 648 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
649 | { |
650 | u32 prev_nr; | |
651 | int class1, class2; | |
652 | ||
3842d135 AK |
653 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
654 | ||
7709aba8 SC |
655 | /* |
656 | * If the exception is destined for L2 and isn't being reinjected, | |
657 | * morph it to a VM-Exit if L1 wants to intercept the exception. A | |
658 | * previously injected exception is not checked because it was checked | |
659 | * when it was original queued, and re-checking is incorrect if _L1_ | |
660 | * injected the exception, in which case it's exempt from interception. | |
661 | */ | |
662 | if (!reinject && is_guest_mode(vcpu) && | |
663 | kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) { | |
664 | kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code, | |
665 | has_payload, payload); | |
666 | return; | |
667 | } | |
668 | ||
664f8e26 | 669 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 670 | queue: |
664f8e26 WL |
671 | if (reinject) { |
672 | /* | |
7709aba8 SC |
673 | * On VM-Entry, an exception can be pending if and only |
674 | * if event injection was blocked by nested_run_pending. | |
675 | * In that case, however, vcpu_enter_guest() requests an | |
676 | * immediate exit, and the guest shouldn't proceed far | |
677 | * enough to need reinjection. | |
664f8e26 | 678 | */ |
7709aba8 | 679 | WARN_ON_ONCE(kvm_is_exception_pending(vcpu)); |
664f8e26 | 680 | vcpu->arch.exception.injected = true; |
91e86d22 JM |
681 | if (WARN_ON_ONCE(has_payload)) { |
682 | /* | |
683 | * A reinjected event has already | |
684 | * delivered its payload. | |
685 | */ | |
686 | has_payload = false; | |
687 | payload = 0; | |
688 | } | |
664f8e26 WL |
689 | } else { |
690 | vcpu->arch.exception.pending = true; | |
691 | vcpu->arch.exception.injected = false; | |
692 | } | |
3fd28fce | 693 | vcpu->arch.exception.has_error_code = has_error; |
d4963e31 | 694 | vcpu->arch.exception.vector = nr; |
3fd28fce | 695 | vcpu->arch.exception.error_code = error_code; |
91e86d22 JM |
696 | vcpu->arch.exception.has_payload = has_payload; |
697 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 698 | if (!is_guest_mode(vcpu)) |
d4963e31 SC |
699 | kvm_deliver_exception_payload(vcpu, |
700 | &vcpu->arch.exception); | |
3fd28fce ED |
701 | return; |
702 | } | |
703 | ||
704 | /* to check exception */ | |
d4963e31 | 705 | prev_nr = vcpu->arch.exception.vector; |
3fd28fce ED |
706 | if (prev_nr == DF_VECTOR) { |
707 | /* triple fault -> shutdown */ | |
a8eeb04a | 708 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
709 | return; |
710 | } | |
711 | class1 = exception_class(prev_nr); | |
712 | class2 = exception_class(nr); | |
81601495 SC |
713 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) || |
714 | (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 | 715 | /* |
81601495 SC |
716 | * Synthesize #DF. Clear the previously injected or pending |
717 | * exception so as not to incorrectly trigger shutdown. | |
664f8e26 | 718 | */ |
664f8e26 | 719 | vcpu->arch.exception.injected = false; |
81601495 SC |
720 | vcpu->arch.exception.pending = false; |
721 | ||
722 | kvm_queue_exception_e(vcpu, DF_VECTOR, 0); | |
723 | } else { | |
3fd28fce ED |
724 | /* replace previous exception with a new one in a hope |
725 | that instruction re-execution will regenerate lost | |
726 | exception */ | |
727 | goto queue; | |
81601495 | 728 | } |
3fd28fce ED |
729 | } |
730 | ||
298101da AK |
731 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
732 | { | |
91e86d22 | 733 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
734 | } |
735 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
736 | ||
ce7ddec4 JR |
737 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
738 | { | |
91e86d22 | 739 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
740 | } |
741 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
742 | ||
4d5523cf PB |
743 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
744 | unsigned long payload) | |
f10c729f JM |
745 | { |
746 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
747 | } | |
4d5523cf | 748 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 749 | |
da998b46 JM |
750 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
751 | u32 error_code, unsigned long payload) | |
752 | { | |
753 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
754 | true, payload, false); | |
755 | } | |
756 | ||
6affcbed | 757 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 758 | { |
db8fcefa AP |
759 | if (err) |
760 | kvm_inject_gp(vcpu, 0); | |
761 | else | |
6affcbed KH |
762 | return kvm_skip_emulated_instruction(vcpu); |
763 | ||
764 | return 1; | |
db8fcefa AP |
765 | } |
766 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 767 | |
d2f7d498 HW |
768 | static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) |
769 | { | |
770 | if (err) { | |
771 | kvm_inject_gp(vcpu, 0); | |
772 | return 1; | |
773 | } | |
774 | ||
775 | return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | | |
776 | EMULTYPE_COMPLETE_USER_EXIT); | |
777 | } | |
778 | ||
6389ee94 | 779 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
780 | { |
781 | ++vcpu->stat.pf_guest; | |
7709aba8 SC |
782 | |
783 | /* | |
784 | * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of | |
785 | * whether or not L1 wants to intercept "regular" #PF. | |
786 | */ | |
787 | if (is_guest_mode(vcpu) && fault->async_page_fault) | |
788 | kvm_queue_exception_vmexit(vcpu, PF_VECTOR, | |
789 | true, fault->error_code, | |
790 | true, fault->address); | |
791 | else | |
da998b46 JM |
792 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, |
793 | fault->address); | |
c3c91fee AK |
794 | } |
795 | ||
7709aba8 | 796 | void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
53b3d8e9 | 797 | struct x86_exception *fault) |
d4f8cf66 | 798 | { |
0cd665bd | 799 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
800 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
801 | ||
0cd665bd PB |
802 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
803 | vcpu->arch.walk_mmu; | |
ef54bcfe | 804 | |
ee1fa209 JS |
805 | /* |
806 | * Invalidate the TLB entry for the faulting address, if it exists, | |
807 | * else the access will fault indefinitely (and to emulate hardware). | |
808 | */ | |
809 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
810 | !(fault->error_code & PFERR_RSVD_MASK)) | |
753b43c9 | 811 | kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address, |
cd42853e | 812 | KVM_MMU_ROOT_CURRENT); |
ee1fa209 JS |
813 | |
814 | fault_mmu->inject_page_fault(vcpu, fault); | |
d4f8cf66 | 815 | } |
53b3d8e9 | 816 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 817 | |
3419ffc8 SY |
818 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
819 | { | |
7460fb4a AK |
820 | atomic_inc(&vcpu->arch.nmi_queued); |
821 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 | 822 | } |
3419ffc8 | 823 | |
298101da AK |
824 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
825 | { | |
91e86d22 | 826 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
827 | } |
828 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
829 | ||
ce7ddec4 JR |
830 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
831 | { | |
91e86d22 | 832 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
833 | } |
834 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
835 | ||
0a79b009 AK |
836 | /* |
837 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
838 | * a #GP and return false. | |
839 | */ | |
840 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 841 | { |
b3646477 | 842 | if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) |
0a79b009 AK |
843 | return true; |
844 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
845 | return false; | |
298101da AK |
846 | } |
847 | ||
16f8a6f9 NA |
848 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
849 | { | |
607475cf | 850 | if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE)) |
16f8a6f9 NA |
851 | return true; |
852 | ||
853 | kvm_queue_exception(vcpu, UD_VECTOR); | |
854 | return false; | |
855 | } | |
856 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
857 | ||
16cfacc8 SC |
858 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
859 | { | |
5b7f575c | 860 | return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); |
16cfacc8 SC |
861 | } |
862 | ||
a03490ed | 863 | /* |
16cfacc8 | 864 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 865 | */ |
2df4a5eb | 866 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 867 | { |
2df4a5eb | 868 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
a03490ed | 869 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; |
15cabbc2 | 870 | gpa_t real_gpa; |
a03490ed CO |
871 | int i; |
872 | int ret; | |
ff03a073 | 873 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 874 | |
15cabbc2 SC |
875 | /* |
876 | * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated | |
877 | * to an L1 GPA. | |
878 | */ | |
c59a0f57 LJ |
879 | real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), |
880 | PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); | |
6e1d2a3f | 881 | if (real_gpa == INVALID_GPA) |
15cabbc2 SC |
882 | return 0; |
883 | ||
94c641ba | 884 | /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ |
15cabbc2 | 885 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, |
94c641ba | 886 | cr3 & GENMASK(11, 5), sizeof(pdpte)); |
15cabbc2 SC |
887 | if (ret < 0) |
888 | return 0; | |
889 | ||
a03490ed | 890 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { |
812f30b2 | 891 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 892 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
15cabbc2 | 893 | return 0; |
a03490ed CO |
894 | } |
895 | } | |
a03490ed | 896 | |
6b123c3a LJ |
897 | /* |
898 | * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. | |
899 | * Shadow page roots need to be reconstructed instead. | |
900 | */ | |
901 | if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) | |
0c1c92f1 | 902 | kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT); |
6b123c3a | 903 | |
46cbc040 PB |
904 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
905 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
906 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
158a48ec ML |
907 | vcpu->arch.pdptrs_from_userspace = false; |
908 | ||
15cabbc2 | 909 | return 1; |
a03490ed | 910 | } |
cc4b6871 | 911 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 912 | |
26a0652c SC |
913 | static bool kvm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
914 | { | |
915 | #ifdef CONFIG_X86_64 | |
916 | if (cr0 & 0xffffffff00000000UL) | |
917 | return false; | |
918 | #endif | |
919 | ||
920 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) | |
921 | return false; | |
922 | ||
923 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) | |
924 | return false; | |
925 | ||
926 | return static_call(kvm_x86_is_valid_cr0)(vcpu, cr0); | |
927 | } | |
928 | ||
f27ad38a TL |
929 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
930 | { | |
01b31714 MK |
931 | /* |
932 | * CR0.WP is incorporated into the MMU role, but only for non-nested, | |
e40bcf9f MK |
933 | * indirect shadow MMUs. If paging is disabled, no updates are needed |
934 | * as there are no permission bits to emulate. If TDP is enabled, the | |
935 | * MMU's metadata needs to be updated, e.g. so that emulating guest | |
936 | * translations does the right thing, but there's no need to unload the | |
937 | * root as CR0.WP doesn't affect SPTEs. | |
01b31714 | 938 | */ |
e40bcf9f MK |
939 | if ((cr0 ^ old_cr0) == X86_CR0_WP) { |
940 | if (!(cr0 & X86_CR0_PG)) | |
941 | return; | |
942 | ||
943 | if (tdp_enabled) { | |
944 | kvm_init_mmu(vcpu); | |
945 | return; | |
946 | } | |
01b31714 MK |
947 | } |
948 | ||
f27ad38a TL |
949 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
950 | kvm_clear_async_pf_completion_queue(vcpu); | |
951 | kvm_async_pf_hash_reset(vcpu); | |
b5f61c03 PB |
952 | |
953 | /* | |
954 | * Clearing CR0.PG is defined to flush the TLB from the guest's | |
955 | * perspective. | |
956 | */ | |
957 | if (!(cr0 & X86_CR0_PG)) | |
958 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
f27ad38a TL |
959 | } |
960 | ||
20f632bd | 961 | if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) |
f27ad38a TL |
962 | kvm_mmu_reset_context(vcpu); |
963 | ||
964 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
7a18c7c2 | 965 | kvm_mmu_honors_guest_mtrrs(vcpu->kvm) && |
f27ad38a TL |
966 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
967 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
968 | } | |
969 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
970 | ||
49a9b07e | 971 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 972 | { |
aad82703 | 973 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
aad82703 | 974 | |
26a0652c | 975 | if (!kvm_is_valid_cr0(vcpu, cr0)) |
0f12244f | 976 | return 1; |
a03490ed | 977 | |
26a0652c | 978 | cr0 |= X86_CR0_ET; |
a03490ed | 979 | |
26a0652c SC |
980 | /* Write to CR0 reserved bits are ignored, even on Intel. */ |
981 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 982 | |
a03490ed | 983 | #ifdef CONFIG_X86_64 |
05487215 SC |
984 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
985 | (cr0 & X86_CR0_PG)) { | |
986 | int cs_db, cs_l; | |
987 | ||
988 | if (!is_pae(vcpu)) | |
989 | return 1; | |
b3646477 | 990 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
05487215 | 991 | if (cs_l) |
0f12244f | 992 | return 1; |
a03490ed | 993 | } |
05487215 SC |
994 | #endif |
995 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
e63f315d | 996 | is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && |
2df4a5eb | 997 | !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) |
05487215 | 998 | return 1; |
a03490ed | 999 | |
777ab82d | 1000 | if (!(cr0 & X86_CR0_PG) && |
607475cf | 1001 | (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))) |
ad756a16 MJ |
1002 | return 1; |
1003 | ||
b3646477 | 1004 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
a03490ed | 1005 | |
f27ad38a | 1006 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 1007 | |
0f12244f GN |
1008 | return 0; |
1009 | } | |
2d3ad1f4 | 1010 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 1011 | |
2d3ad1f4 | 1012 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 1013 | { |
49a9b07e | 1014 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 1015 | } |
2d3ad1f4 | 1016 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 1017 | |
139a12cf | 1018 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 1019 | { |
16809ecd TL |
1020 | if (vcpu->arch.guest_state_protected) |
1021 | return; | |
1022 | ||
607475cf | 1023 | if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { |
139a12cf AL |
1024 | |
1025 | if (vcpu->arch.xcr0 != host_xcr0) | |
1026 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
1027 | ||
fe60e8f6 | 1028 | if (guest_can_use(vcpu, X86_FEATURE_XSAVES) && |
139a12cf AL |
1029 | vcpu->arch.ia32_xss != host_xss) |
1030 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
1031 | } | |
37486135 | 1032 | |
056b9919 | 1033 | if (cpu_feature_enabled(X86_FEATURE_PKU) && |
945024d7 JK |
1034 | vcpu->arch.pkru != vcpu->arch.host_pkru && |
1035 | ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || | |
607475cf | 1036 | kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) |
72a6c08c | 1037 | write_pkru(vcpu->arch.pkru); |
42bdf991 | 1038 | } |
139a12cf | 1039 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 1040 | |
139a12cf | 1041 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 1042 | { |
16809ecd TL |
1043 | if (vcpu->arch.guest_state_protected) |
1044 | return; | |
1045 | ||
056b9919 | 1046 | if (cpu_feature_enabled(X86_FEATURE_PKU) && |
945024d7 | 1047 | ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || |
607475cf | 1048 | kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) { |
37486135 BM |
1049 | vcpu->arch.pkru = rdpkru(); |
1050 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 1051 | write_pkru(vcpu->arch.host_pkru); |
37486135 BM |
1052 | } |
1053 | ||
607475cf | 1054 | if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { |
139a12cf AL |
1055 | |
1056 | if (vcpu->arch.xcr0 != host_xcr0) | |
1057 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
1058 | ||
fe60e8f6 | 1059 | if (guest_can_use(vcpu, X86_FEATURE_XSAVES) && |
139a12cf AL |
1060 | vcpu->arch.ia32_xss != host_xss) |
1061 | wrmsrl(MSR_IA32_XSS, host_xss); | |
1062 | } | |
1063 | ||
42bdf991 | 1064 | } |
139a12cf | 1065 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 1066 | |
ba1f77c5 | 1067 | #ifdef CONFIG_X86_64 |
988896bb LB |
1068 | static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu) |
1069 | { | |
ee519b3a | 1070 | return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC; |
988896bb | 1071 | } |
ba1f77c5 | 1072 | #endif |
988896bb | 1073 | |
69b0049a | 1074 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 1075 | { |
56c103ec LJ |
1076 | u64 xcr0 = xcr; |
1077 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 1078 | u64 valid_bits; |
2acf923e DC |
1079 | |
1080 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
1081 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
1082 | return 1; | |
d91cab78 | 1083 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 1084 | return 1; |
d91cab78 | 1085 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 1086 | return 1; |
46c34cb0 PB |
1087 | |
1088 | /* | |
1089 | * Do not allow the guest to set bits that we do not support | |
1090 | * saving. However, xcr0 bit 0 is always set, even if the | |
e8f65b9b | 1091 | * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). |
46c34cb0 | 1092 | */ |
ee519b3a | 1093 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 1094 | if (xcr0 & ~valid_bits) |
2acf923e | 1095 | return 1; |
46c34cb0 | 1096 | |
d91cab78 DH |
1097 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
1098 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
1099 | return 1; |
1100 | ||
d91cab78 DH |
1101 | if (xcr0 & XFEATURE_MASK_AVX512) { |
1102 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 1103 | return 1; |
d91cab78 | 1104 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
1105 | return 1; |
1106 | } | |
86aff7a4 JL |
1107 | |
1108 | if ((xcr0 & XFEATURE_MASK_XTILE) && | |
1109 | ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) | |
1110 | return 1; | |
1111 | ||
2acf923e | 1112 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 1113 | |
d91cab78 | 1114 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 1115 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
1116 | return 0; |
1117 | } | |
1118 | ||
92f9895c | 1119 | int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) |
2acf923e | 1120 | { |
50b2d49b | 1121 | /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */ |
92f9895c SC |
1122 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || |
1123 | __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { | |
1124 | kvm_inject_gp(vcpu, 0); | |
1125 | return 1; | |
1126 | } | |
bbefd4fc | 1127 | |
92f9895c | 1128 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e | 1129 | } |
92f9895c | 1130 | EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); |
2acf923e | 1131 | |
c33f6f22 | 1132 | bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 1133 | { |
b11306b5 | 1134 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1135 | return false; |
b9baba86 | 1136 | |
b899c132 | 1137 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1138 | return false; |
3ca94192 | 1139 | |
c33f6f22 SC |
1140 | return true; |
1141 | } | |
1142 | EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4); | |
1143 | ||
1144 | static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1145 | { | |
1146 | return __kvm_is_valid_cr4(vcpu, cr4) && | |
1147 | static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); | |
3ca94192 WL |
1148 | } |
1149 | ||
5b51cb13 TL |
1150 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1151 | { | |
b5f61c03 PB |
1152 | if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) |
1153 | kvm_mmu_reset_context(vcpu); | |
1154 | ||
509bfe3d | 1155 | /* |
509bfe3d LJ |
1156 | * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB |
1157 | * according to the SDM; however, stale prev_roots could be reused | |
1158 | * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we | |
b5f61c03 PB |
1159 | * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST |
1160 | * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed, | |
1161 | * so fall through. | |
509bfe3d | 1162 | */ |
b5f61c03 PB |
1163 | if (!tdp_enabled && |
1164 | (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) | |
f6d0a252 | 1165 | kvm_mmu_unload(vcpu); |
b5f61c03 PB |
1166 | |
1167 | /* | |
1168 | * The TLB has to be flushed for all PCIDs if any of the following | |
1169 | * (architecturally required) changes happen: | |
1170 | * - CR4.PCIDE is changed from 1 to 0 | |
1171 | * - CR4.PGE is toggled | |
509bfe3d | 1172 | * |
b5f61c03 | 1173 | * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT. |
509bfe3d | 1174 | */ |
b5f61c03 PB |
1175 | if (((cr4 ^ old_cr4) & X86_CR4_PGE) || |
1176 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
55261738 | 1177 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
b5f61c03 PB |
1178 | |
1179 | /* | |
1180 | * The TLB has to be flushed for the current PCID if any of the | |
1181 | * following (architecturally required) changes happen: | |
1182 | * - CR4.SMEP is changed from 0 to 1 | |
1183 | * - CR4.PAE is toggled | |
1184 | */ | |
1185 | else if (((cr4 ^ old_cr4) & X86_CR4_PAE) || | |
1186 | ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP))) | |
1187 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
1188 | ||
3ca94192 | 1189 | } |
5b51cb13 | 1190 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1191 | |
1192 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1193 | { | |
1194 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
3ca94192 | 1195 | |
ee69c92b | 1196 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1197 | return 1; |
1198 | ||
a03490ed | 1199 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1200 | if (!(cr4 & X86_CR4_PAE)) |
1201 | return 1; | |
d74fcfc1 SC |
1202 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1203 | return 1; | |
a2edf57f | 1204 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
a37ebdce | 1205 | && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) |
2df4a5eb | 1206 | && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) |
0f12244f GN |
1207 | return 1; |
1208 | ||
ad756a16 | 1209 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
ad756a16 MJ |
1210 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ |
1211 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1212 | return 1; | |
1213 | } | |
1214 | ||
b3646477 | 1215 | static_call(kvm_x86_set_cr4)(vcpu, cr4); |
a03490ed | 1216 | |
5b51cb13 | 1217 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1218 | |
0f12244f GN |
1219 | return 0; |
1220 | } | |
2d3ad1f4 | 1221 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1222 | |
21823fbd SC |
1223 | static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) |
1224 | { | |
1225 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
1226 | unsigned long roots_to_free = 0; | |
1227 | int i; | |
1228 | ||
e45e9e39 LJ |
1229 | /* |
1230 | * MOV CR3 and INVPCID are usually not intercepted when using TDP, but | |
1231 | * this is reachable when running EPT=1 and unrestricted_guest=0, and | |
1232 | * also via the emulator. KVM's TDP page tables are not in the scope of | |
1233 | * the invalidation, but the guest's TLB entries need to be flushed as | |
1234 | * the CPU may have cached entries in its TLB for the target PCID. | |
1235 | */ | |
1236 | if (unlikely(tdp_enabled)) { | |
1237 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
1238 | return; | |
1239 | } | |
1240 | ||
21823fbd SC |
1241 | /* |
1242 | * If neither the current CR3 nor any of the prev_roots use the given | |
1243 | * PCID, then nothing needs to be done here because a resync will | |
1244 | * happen anyway before switching to any other CR3. | |
1245 | */ | |
1246 | if (kvm_get_active_pcid(vcpu) == pcid) { | |
e62f1aa8 | 1247 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
21823fbd SC |
1248 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1249 | } | |
1250 | ||
509bfe3d LJ |
1251 | /* |
1252 | * If PCID is disabled, there is no need to free prev_roots even if the | |
1253 | * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB | |
1254 | * with PCIDE=0. | |
1255 | */ | |
607475cf | 1256 | if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) |
509bfe3d LJ |
1257 | return; |
1258 | ||
21823fbd SC |
1259 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
1260 | if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) | |
1261 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
1262 | ||
0c1c92f1 | 1263 | kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); |
21823fbd SC |
1264 | } |
1265 | ||
2390218b | 1266 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1267 | { |
ade61e28 | 1268 | bool skip_tlb_flush = false; |
21823fbd | 1269 | unsigned long pcid = 0; |
ac146235 | 1270 | #ifdef CONFIG_X86_64 |
607475cf | 1271 | if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) { |
208320ba JS |
1272 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1273 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
21823fbd | 1274 | pcid = cr3 & X86_CR3_PCID_MASK; |
ade61e28 | 1275 | } |
ac146235 | 1276 | #endif |
9d88fca7 | 1277 | |
c7313155 | 1278 | /* PDPTRs are always reloaded for PAE paging. */ |
21823fbd SC |
1279 | if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) |
1280 | goto handle_tlb_flush; | |
d835dfec | 1281 | |
886bbcc7 SC |
1282 | /* |
1283 | * Do not condition the GPA check on long mode, this helper is used to | |
1284 | * stuff CR3, e.g. for RSM emulation, and there is no guarantee that | |
1285 | * the current vCPU mode is accurate. | |
1286 | */ | |
2c49db45 | 1287 | if (!kvm_vcpu_is_legal_cr3(vcpu, cr3)) |
d1cd3ce9 | 1288 | return 1; |
886bbcc7 | 1289 | |
2df4a5eb | 1290 | if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) |
346874c9 | 1291 | return 1; |
a03490ed | 1292 | |
21823fbd | 1293 | if (cr3 != kvm_read_cr3(vcpu)) |
b5129100 | 1294 | kvm_mmu_new_pgd(vcpu, cr3); |
21823fbd | 1295 | |
0f12244f | 1296 | vcpu->arch.cr3 = cr3; |
3883bc9d | 1297 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); |
405329fc | 1298 | /* Do not call post_set_cr3, we do not get here for confidential guests. */ |
7c390d35 | 1299 | |
21823fbd SC |
1300 | handle_tlb_flush: |
1301 | /* | |
1302 | * A load of CR3 that flushes the TLB flushes only the current PCID, | |
1303 | * even if PCID is disabled, in which case PCID=0 is flushed. It's a | |
1304 | * moot point in the end because _disabling_ PCID will flush all PCIDs, | |
1305 | * and it's impossible to use a non-zero PCID when PCID is disabled, | |
1306 | * i.e. only PCID=0 can be relevant. | |
1307 | */ | |
1308 | if (!skip_tlb_flush) | |
1309 | kvm_invalidate_pcid(vcpu, pcid); | |
1310 | ||
0f12244f GN |
1311 | return 0; |
1312 | } | |
2d3ad1f4 | 1313 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1314 | |
eea1cff9 | 1315 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1316 | { |
0f12244f GN |
1317 | if (cr8 & CR8_RESERVED_BITS) |
1318 | return 1; | |
35754c98 | 1319 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1320 | kvm_lapic_set_tpr(vcpu, cr8); |
1321 | else | |
ad312c7c | 1322 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1323 | return 0; |
1324 | } | |
2d3ad1f4 | 1325 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1326 | |
2d3ad1f4 | 1327 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1328 | { |
35754c98 | 1329 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1330 | return kvm_lapic_get_cr8(vcpu); |
1331 | else | |
ad312c7c | 1332 | return vcpu->arch.cr8; |
a03490ed | 1333 | } |
2d3ad1f4 | 1334 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1335 | |
ae561ede NA |
1336 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1337 | { | |
1338 | int i; | |
1339 | ||
1340 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1341 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1342 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae561ede NA |
1343 | } |
1344 | } | |
1345 | ||
7c86663b | 1346 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1347 | { |
1348 | unsigned long dr7; | |
1349 | ||
1350 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1351 | dr7 = vcpu->arch.guest_debug_dr7; | |
1352 | else | |
1353 | dr7 = vcpu->arch.dr7; | |
b3646477 | 1354 | static_call(kvm_x86_set_dr7)(vcpu, dr7); |
360b948d PB |
1355 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1356 | if (dr7 & DR7_BP_EN_MASK) | |
1357 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1358 | } |
7c86663b | 1359 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1360 | |
6f43ed01 NA |
1361 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1362 | { | |
1363 | u64 fixed = DR6_FIXED_1; | |
1364 | ||
d6321d49 | 1365 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 | 1366 | fixed |= DR6_RTM; |
e8ea85fb CQ |
1367 | |
1368 | if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) | |
1369 | fixed |= DR6_BUS_LOCK; | |
6f43ed01 NA |
1370 | return fixed; |
1371 | } | |
1372 | ||
996ff542 | 1373 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1374 | { |
ea740059 MP |
1375 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1376 | ||
020df079 GN |
1377 | switch (dr) { |
1378 | case 0 ... 3: | |
ea740059 | 1379 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1380 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1381 | vcpu->arch.eff_db[dr] = val; | |
1382 | break; | |
1383 | case 4: | |
020df079 | 1384 | case 6: |
f5f6145e | 1385 | if (!kvm_dr6_valid(val)) |
996ff542 | 1386 | return 1; /* #GP */ |
6f43ed01 | 1387 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1388 | break; |
1389 | case 5: | |
020df079 | 1390 | default: /* 7 */ |
b91991bf | 1391 | if (!kvm_dr7_valid(val)) |
996ff542 | 1392 | return 1; /* #GP */ |
020df079 | 1393 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1394 | kvm_update_dr7(vcpu); |
020df079 GN |
1395 | break; |
1396 | } | |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
1401 | ||
29d6ca41 | 1402 | void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1403 | { |
ea740059 MP |
1404 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1405 | ||
020df079 GN |
1406 | switch (dr) { |
1407 | case 0 ... 3: | |
ea740059 | 1408 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1409 | break; |
1410 | case 4: | |
020df079 | 1411 | case 6: |
5679b803 | 1412 | *val = vcpu->arch.dr6; |
020df079 GN |
1413 | break; |
1414 | case 5: | |
020df079 GN |
1415 | default: /* 7 */ |
1416 | *val = vcpu->arch.dr7; | |
1417 | break; | |
1418 | } | |
338dbc97 | 1419 | } |
020df079 GN |
1420 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1421 | ||
c483c454 | 1422 | int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) |
022cd0e8 | 1423 | { |
de3cd117 | 1424 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 | 1425 | u64 data; |
022cd0e8 | 1426 | |
c483c454 SC |
1427 | if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { |
1428 | kvm_inject_gp(vcpu, 0); | |
1429 | return 1; | |
1430 | } | |
1431 | ||
de3cd117 SC |
1432 | kvm_rax_write(vcpu, (u32)data); |
1433 | kvm_rdx_write(vcpu, data >> 32); | |
c483c454 | 1434 | return kvm_skip_emulated_instruction(vcpu); |
022cd0e8 | 1435 | } |
c483c454 | 1436 | EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); |
022cd0e8 | 1437 | |
043405e1 | 1438 | /* |
a3064257 SC |
1439 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) track |
1440 | * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS, | |
1441 | * KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. msrs_to_save holds MSRs that | |
1442 | * require host support, i.e. should be probed via RDMSR. emulated_msrs holds | |
1443 | * MSRs that KVM emulates without strictly requiring host support. | |
1444 | * msr_based_features holds MSRs that enumerate features, i.e. are effectively | |
1445 | * CPUID leafs. Note, msr_based_features isn't mutually exclusive with | |
1446 | * msrs_to_save and emulated_msrs. | |
043405e1 | 1447 | */ |
e3267cbb | 1448 | |
2374b731 | 1449 | static const u32 msrs_to_save_base[] = { |
043405e1 | 1450 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1451 | MSR_STAR, |
043405e1 CO |
1452 | #ifdef CONFIG_X86_64 |
1453 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1454 | #endif | |
b3897a49 | 1455 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1456 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
b9846a69 | 1457 | MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL, |
bf8c55d8 CP |
1458 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1459 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1460 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1461 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1462 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1463 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1464 | MSR_IA32_UMWAIT_CONTROL, |
1465 | ||
2374b731 SC |
1466 | MSR_IA32_XFD, MSR_IA32_XFD_ERR, |
1467 | }; | |
1468 | ||
1469 | static const u32 msrs_to_save_pmu[] = { | |
e2ada66e | 1470 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
9fb12fe5 | 1471 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, |
e2ada66e JM |
1472 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, |
1473 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
4f1fa2a1 LX |
1474 | MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, |
1475 | ||
1476 | /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */ | |
e2ada66e JM |
1477 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, |
1478 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1479 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1480 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
e2ada66e JM |
1481 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1482 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1483 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1484 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
e1fc1553 FM |
1485 | |
1486 | MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, | |
1487 | MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, | |
556f3c9a LX |
1488 | |
1489 | /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */ | |
e1fc1553 FM |
1490 | MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, |
1491 | MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, | |
1492 | MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, | |
1493 | MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, | |
4a277189 LX |
1494 | |
1495 | MSR_AMD64_PERF_CNTR_GLOBAL_CTL, | |
1496 | MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, | |
1497 | MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, | |
043405e1 CO |
1498 | }; |
1499 | ||
2374b731 SC |
1500 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) + |
1501 | ARRAY_SIZE(msrs_to_save_pmu)]; | |
043405e1 CO |
1502 | static unsigned num_msrs_to_save; |
1503 | ||
7a5ee6ed | 1504 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1505 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1506 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
b4f69df0 VK |
1507 | |
1508 | #ifdef CONFIG_KVM_HYPERV | |
62ef68bb PB |
1509 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
1510 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1511 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1512 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1513 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1514 | HV_X64_MSR_RESET, |
11c4b1ca | 1515 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1516 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1517 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1518 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1519 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 | 1520 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
2be1bd3a | 1521 | HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL, |
f97f5a56 JD |
1522 | HV_X64_MSR_SYNDBG_OPTIONS, |
1523 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1524 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1525 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
b4f69df0 | 1526 | #endif |
a2e164e7 VK |
1527 | |
1528 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1529 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1530 | |
ba904635 | 1531 | MSR_IA32_TSC_ADJUST, |
09141ec0 | 1532 | MSR_IA32_TSC_DEADLINE, |
2bdb76c0 | 1533 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1534 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1535 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1536 | MSR_IA32_MCG_STATUS, |
1537 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1538 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1539 | MSR_IA32_SMBASE, |
52797bf9 | 1540 | MSR_SMI_COUNT, |
db2336a8 KH |
1541 | MSR_PLATFORM_INFO, |
1542 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1543 | MSR_AMD64_VIRT_SPEC_CTRL, |
5228eb96 | 1544 | MSR_AMD64_TSC_RATIO, |
6c6a2ab9 | 1545 | MSR_IA32_POWER_CTL, |
99634e3e | 1546 | MSR_IA32_UCODE_REV, |
191c8137 | 1547 | |
95c5c7c7 | 1548 | /* |
a3064257 SC |
1549 | * KVM always supports the "true" VMX control MSRs, even if the host |
1550 | * does not. The VMX MSRs as a whole are considered "emulated" as KVM | |
1551 | * doesn't strictly require them to exist in the host (ignoring that | |
1552 | * KVM would refuse to load in the first place if the core set of MSRs | |
1553 | * aren't supported). | |
95c5c7c7 PB |
1554 | */ |
1555 | MSR_IA32_VMX_BASIC, | |
1556 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1557 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1558 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1559 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1560 | MSR_IA32_VMX_MISC, | |
1561 | MSR_IA32_VMX_CR0_FIXED0, | |
1562 | MSR_IA32_VMX_CR4_FIXED0, | |
1563 | MSR_IA32_VMX_VMCS_ENUM, | |
1564 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1565 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1566 | MSR_IA32_VMX_VMFUNC, | |
1567 | ||
191c8137 | 1568 | MSR_K7_HWCR, |
2d5ba19b | 1569 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1570 | }; |
1571 | ||
7a5ee6ed | 1572 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1573 | static unsigned num_emulated_msrs; |
1574 | ||
801e459a | 1575 | /* |
9eb6ba31 SC |
1576 | * List of MSRs that control the existence of MSR-based features, i.e. MSRs |
1577 | * that are effectively CPUID leafs. VMX MSRs are also included in the set of | |
1578 | * feature MSRs, but are handled separately to allow expedited lookups. | |
801e459a | 1579 | */ |
9eb6ba31 | 1580 | static const u32 msr_based_features_all_except_vmx[] = { |
2632daeb | 1581 | MSR_AMD64_DE_CFG, |
518e7b94 | 1582 | MSR_IA32_UCODE_REV, |
cd283252 | 1583 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1584 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1585 | }; |
1586 | ||
9eb6ba31 SC |
1587 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) + |
1588 | (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)]; | |
801e459a TL |
1589 | static unsigned int num_msr_based_features; |
1590 | ||
0094f62c SC |
1591 | /* |
1592 | * All feature MSRs except uCode revID, which tracks the currently loaded uCode | |
1593 | * patch, are immutable once the vCPU model is defined. | |
1594 | */ | |
1595 | static bool kvm_is_immutable_feature_msr(u32 msr) | |
1596 | { | |
1597 | int i; | |
1598 | ||
1599 | if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR) | |
1600 | return true; | |
1601 | ||
1602 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) { | |
1603 | if (msr == msr_based_features_all_except_vmx[i]) | |
1604 | return msr != MSR_IA32_UCODE_REV; | |
1605 | } | |
1606 | ||
1607 | return false; | |
1608 | } | |
1609 | ||
0204750b JM |
1610 | /* |
1611 | * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM | |
1612 | * does not yet virtualize. These include: | |
1613 | * 10 - MISC_PACKAGE_CTRLS | |
1614 | * 11 - ENERGY_FILTERING_CTL | |
1615 | * 12 - DOITM | |
1616 | * 18 - FB_CLEAR_CTRL | |
1617 | * 21 - XAPIC_DISABLE_STATUS | |
1618 | * 23 - OVERCLOCKING_STATUS | |
1619 | */ | |
1620 | ||
1621 | #define KVM_SUPPORTED_ARCH_CAP \ | |
1622 | (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \ | |
1623 | ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \ | |
1624 | ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \ | |
1625 | ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \ | |
81ac7e5d | 1626 | ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO) |
0204750b | 1627 | |
4d22c17c | 1628 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1629 | { |
a2fd5d02 | 1630 | u64 data = host_arch_capabilities & KVM_SUPPORTED_ARCH_CAP; |
5b76a3cf | 1631 | |
b8e8c830 PB |
1632 | /* |
1633 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1634 | * the nested hypervisor runs with NX huge pages. If it is not, | |
d9f6e12f | 1635 | * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other |
b8e8c830 PB |
1636 | * L1 guests, so it need not worry about its own (L2) guests. |
1637 | */ | |
1638 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1639 | ||
5b76a3cf PB |
1640 | /* |
1641 | * If we're doing cache flushes (either "always" or "cond") | |
1642 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1643 | * If an outer hypervisor is doing the cache flush for us | |
02f1b0b7 | 1644 | * (ARCH_CAP_SKIP_VMENTRY_L1DFLUSH), we can safely pass that |
5b76a3cf PB |
1645 | * capability to the guest too, and if EPT is disabled we're not |
1646 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1647 | * require a nested hypervisor to do a flush of its own. | |
1648 | */ | |
1649 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1650 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1651 | ||
0c54914d PB |
1652 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1653 | data |= ARCH_CAP_RDCL_NO; | |
1654 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1655 | data |= ARCH_CAP_SSB_NO; | |
1656 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1657 | data |= ARCH_CAP_MDS_NO; | |
1658 | ||
7131636e PB |
1659 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1660 | /* | |
1661 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1662 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1663 | * and therefore knows that there cannot be TAA) but keep | |
1664 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1665 | * and we want to allow migrating those guests to tsx=off hosts. | |
1666 | */ | |
1667 | data &= ~ARCH_CAP_TAA_NO; | |
1668 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1669 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1670 | } else { |
1671 | /* | |
1672 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1673 | * host so the guest can choose between disabling TSX or | |
1674 | * using VERW to clear CPU buffers. | |
1675 | */ | |
1676 | } | |
e1d38b63 | 1677 | |
81ac7e5d DS |
1678 | if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated()) |
1679 | data |= ARCH_CAP_GDS_NO; | |
1680 | ||
5b76a3cf PB |
1681 | return data; |
1682 | } | |
5b76a3cf | 1683 | |
66421c1e WL |
1684 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1685 | { | |
1686 | switch (msr->index) { | |
cd283252 | 1687 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1688 | msr->data = kvm_get_arch_capabilities(); |
1689 | break; | |
5fe9805d SC |
1690 | case MSR_IA32_PERF_CAPABILITIES: |
1691 | msr->data = kvm_caps.supported_perf_cap; | |
1692 | break; | |
5b76a3cf | 1693 | case MSR_IA32_UCODE_REV: |
cd283252 | 1694 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1695 | break; |
66421c1e | 1696 | default: |
b3646477 | 1697 | return static_call(kvm_x86_get_msr_feature)(msr); |
66421c1e WL |
1698 | } |
1699 | return 0; | |
1700 | } | |
1701 | ||
801e459a TL |
1702 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1703 | { | |
1704 | struct kvm_msr_entry msr; | |
66421c1e | 1705 | int r; |
801e459a TL |
1706 | |
1707 | msr.index = index; | |
66421c1e | 1708 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1709 | |
1710 | if (r == KVM_MSR_RET_INVALID) { | |
1711 | /* Unconditionally clear the output for simplicity */ | |
1712 | *data = 0; | |
d632826f | 1713 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1714 | r = 0; |
12bc2132 PX |
1715 | } |
1716 | ||
66421c1e WL |
1717 | if (r) |
1718 | return r; | |
801e459a TL |
1719 | |
1720 | *data = msr.data; | |
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
11988499 | 1725 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1726 | { |
8c19b6f2 KP |
1727 | if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS)) |
1728 | return false; | |
1729 | ||
1b4d56b8 | 1730 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1731 | return false; |
1b2fd70c | 1732 | |
1b4d56b8 | 1733 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1734 | return false; |
d8017474 | 1735 | |
0a629563 SC |
1736 | if (efer & (EFER_LME | EFER_LMA) && |
1737 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1738 | return false; | |
1739 | ||
1740 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1741 | return false; | |
d8017474 | 1742 | |
384bb783 | 1743 | return true; |
11988499 SC |
1744 | |
1745 | } | |
1746 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1747 | { | |
1748 | if (efer & efer_reserved_bits) | |
1749 | return false; | |
1750 | ||
1751 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1752 | } |
1753 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1754 | ||
11988499 | 1755 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1756 | { |
1757 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1758 | u64 efer = msr_info->data; |
72f211ec | 1759 | int r; |
384bb783 | 1760 | |
11988499 | 1761 | if (efer & efer_reserved_bits) |
66f61c92 | 1762 | return 1; |
384bb783 | 1763 | |
11988499 SC |
1764 | if (!msr_info->host_initiated) { |
1765 | if (!__kvm_valid_efer(vcpu, efer)) | |
1766 | return 1; | |
1767 | ||
1768 | if (is_paging(vcpu) && | |
1769 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1770 | return 1; | |
1771 | } | |
384bb783 | 1772 | |
15c4a640 | 1773 | efer &= ~EFER_LMA; |
f6801dff | 1774 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1775 | |
b3646477 | 1776 | r = static_call(kvm_x86_set_efer)(vcpu, efer); |
72f211ec ML |
1777 | if (r) { |
1778 | WARN_ON(r > 0); | |
1779 | return r; | |
1780 | } | |
a3d204e2 | 1781 | |
d6174299 | 1782 | if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS) |
aad82703 SY |
1783 | kvm_mmu_reset_context(vcpu); |
1784 | ||
b69e8cae | 1785 | return 0; |
15c4a640 CO |
1786 | } |
1787 | ||
f2b4b7dd JR |
1788 | void kvm_enable_efer_bits(u64 mask) |
1789 | { | |
1790 | efer_reserved_bits &= ~mask; | |
1791 | } | |
1792 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1793 | ||
51de8151 AG |
1794 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1795 | { | |
b318e8de SC |
1796 | struct kvm_x86_msr_filter *msr_filter; |
1797 | struct msr_bitmap_range *ranges; | |
1a155254 | 1798 | struct kvm *kvm = vcpu->kvm; |
b318e8de | 1799 | bool allowed; |
1a155254 | 1800 | int idx; |
b318e8de | 1801 | u32 i; |
1a155254 | 1802 | |
b318e8de SC |
1803 | /* x2APIC MSRs do not support filtering. */ |
1804 | if (index >= 0x800 && index <= 0x8ff) | |
1a155254 AG |
1805 | return true; |
1806 | ||
1a155254 AG |
1807 | idx = srcu_read_lock(&kvm->srcu); |
1808 | ||
b318e8de SC |
1809 | msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); |
1810 | if (!msr_filter) { | |
1811 | allowed = true; | |
1812 | goto out; | |
1813 | } | |
1814 | ||
1815 | allowed = msr_filter->default_allow; | |
1816 | ranges = msr_filter->ranges; | |
1817 | ||
1818 | for (i = 0; i < msr_filter->count; i++) { | |
1a155254 AG |
1819 | u32 start = ranges[i].base; |
1820 | u32 end = start + ranges[i].nmsrs; | |
1821 | u32 flags = ranges[i].flags; | |
1822 | unsigned long *bitmap = ranges[i].bitmap; | |
1823 | ||
1824 | if ((index >= start) && (index < end) && (flags & type)) { | |
e12fa4b9 | 1825 | allowed = test_bit(index - start, bitmap); |
1a155254 AG |
1826 | break; |
1827 | } | |
1828 | } | |
1829 | ||
b318e8de | 1830 | out: |
1a155254 AG |
1831 | srcu_read_unlock(&kvm->srcu, idx); |
1832 | ||
b318e8de | 1833 | return allowed; |
51de8151 AG |
1834 | } |
1835 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1836 | ||
15c4a640 | 1837 | /* |
f20935d8 SC |
1838 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1839 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1840 | * Returns 0 on success, non-0 otherwise. |
1841 | * Assumes vcpu_load() was already called. | |
1842 | */ | |
f20935d8 SC |
1843 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1844 | bool host_initiated) | |
15c4a640 | 1845 | { |
f20935d8 SC |
1846 | struct msr_data msr; |
1847 | ||
1848 | switch (index) { | |
854e8bb1 NA |
1849 | case MSR_FS_BASE: |
1850 | case MSR_GS_BASE: | |
1851 | case MSR_KERNEL_GS_BASE: | |
1852 | case MSR_CSTAR: | |
1853 | case MSR_LSTAR: | |
f20935d8 | 1854 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1855 | return 1; |
1856 | break; | |
1857 | case MSR_IA32_SYSENTER_EIP: | |
1858 | case MSR_IA32_SYSENTER_ESP: | |
1859 | /* | |
1860 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1861 | * non-canonical address is written on Intel but not on | |
1862 | * AMD (which ignores the top 32-bits, because it does | |
1863 | * not implement 64-bit SYSENTER). | |
1864 | * | |
1865 | * 64-bit code should hence be able to write a non-canonical | |
1866 | * value on AMD. Making the address canonical ensures that | |
1867 | * vmentry does not fail on Intel after writing a non-canonical | |
1868 | * value, and that something deterministic happens if the guest | |
1869 | * invokes 64-bit SYSENTER. | |
1870 | */ | |
1fb85d06 | 1871 | data = __canonical_address(data, vcpu_virt_addr_bits(vcpu)); |
61a05d44 SC |
1872 | break; |
1873 | case MSR_TSC_AUX: | |
1874 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1875 | return 1; | |
1876 | ||
1877 | if (!host_initiated && | |
1878 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1879 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1880 | return 1; | |
1881 | ||
1882 | /* | |
1883 | * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has | |
1884 | * incomplete and conflicting architectural behavior. Current | |
1885 | * AMD CPUs completely ignore bits 63:32, i.e. they aren't | |
1886 | * reserved and always read as zeros. Enforce Intel's reserved | |
1887 | * bits check if and only if the guest CPU is Intel, and clear | |
1888 | * the bits in all other cases. This ensures cross-vendor | |
1889 | * migration will provide consistent behavior for the guest. | |
1890 | */ | |
1891 | if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) | |
1892 | return 1; | |
1893 | ||
1894 | data = (u32)data; | |
1895 | break; | |
854e8bb1 | 1896 | } |
f20935d8 SC |
1897 | |
1898 | msr.data = data; | |
1899 | msr.index = index; | |
1900 | msr.host_initiated = host_initiated; | |
1901 | ||
b3646477 | 1902 | return static_call(kvm_x86_set_msr)(vcpu, &msr); |
15c4a640 CO |
1903 | } |
1904 | ||
6abe9c13 PX |
1905 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1906 | u32 index, u64 data, bool host_initiated) | |
1907 | { | |
1908 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1909 | ||
1910 | if (ret == KVM_MSR_RET_INVALID) | |
d632826f | 1911 | if (kvm_msr_ignored_check(index, data, true)) |
cc4cb017 | 1912 | ret = 0; |
6abe9c13 PX |
1913 | |
1914 | return ret; | |
1915 | } | |
1916 | ||
313a3dc7 | 1917 | /* |
f20935d8 SC |
1918 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1919 | * checks are bypassed if @host_initiated is %true. | |
1920 | * Returns 0 on success, non-0 otherwise. | |
1921 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1922 | */ |
edef5c36 PB |
1923 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1924 | bool host_initiated) | |
609e36d3 PB |
1925 | { |
1926 | struct msr_data msr; | |
f20935d8 | 1927 | int ret; |
609e36d3 | 1928 | |
61a05d44 SC |
1929 | switch (index) { |
1930 | case MSR_TSC_AUX: | |
1931 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1932 | return 1; | |
1933 | ||
1934 | if (!host_initiated && | |
1935 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1936 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1937 | return 1; | |
1938 | break; | |
1939 | } | |
1940 | ||
609e36d3 | 1941 | msr.index = index; |
f20935d8 | 1942 | msr.host_initiated = host_initiated; |
609e36d3 | 1943 | |
b3646477 | 1944 | ret = static_call(kvm_x86_get_msr)(vcpu, &msr); |
f20935d8 SC |
1945 | if (!ret) |
1946 | *data = msr.data; | |
1947 | return ret; | |
609e36d3 PB |
1948 | } |
1949 | ||
6abe9c13 PX |
1950 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1951 | u32 index, u64 *data, bool host_initiated) | |
1952 | { | |
1953 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1954 | ||
1955 | if (ret == KVM_MSR_RET_INVALID) { | |
1956 | /* Unconditionally clear *data for simplicity */ | |
1957 | *data = 0; | |
d632826f | 1958 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1959 | ret = 0; |
6abe9c13 PX |
1960 | } |
1961 | ||
1962 | return ret; | |
1963 | } | |
1964 | ||
ac8d6cad HW |
1965 | static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
1966 | { | |
1967 | if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) | |
1968 | return KVM_MSR_RET_FILTERED; | |
1969 | return kvm_get_msr_ignored_check(vcpu, index, data, false); | |
1970 | } | |
1971 | ||
1972 | static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data) | |
1973 | { | |
1974 | if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) | |
1975 | return KVM_MSR_RET_FILTERED; | |
1976 | return kvm_set_msr_ignored_check(vcpu, index, data, false); | |
1977 | } | |
1978 | ||
f20935d8 | 1979 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1980 | { |
6abe9c13 | 1981 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1982 | } |
1983 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1984 | |
f20935d8 SC |
1985 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1986 | { | |
6abe9c13 | 1987 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1988 | } |
1989 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1990 | ||
d2f7d498 | 1991 | static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1992 | { |
d2f7d498 | 1993 | if (!vcpu->run->msr.error) { |
1ae09954 AG |
1994 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1995 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1996 | } | |
d2f7d498 | 1997 | } |
1ae09954 | 1998 | |
d2f7d498 HW |
1999 | static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) |
2000 | { | |
2001 | return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); | |
1ae09954 AG |
2002 | } |
2003 | ||
d2f7d498 HW |
2004 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
2005 | { | |
2006 | complete_userspace_rdmsr(vcpu); | |
2007 | return complete_emulated_msr_access(vcpu); | |
2008 | } | |
2009 | ||
2010 | static int complete_fast_msr_access(struct kvm_vcpu *vcpu) | |
1ae09954 | 2011 | { |
b3646477 | 2012 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
2013 | } |
2014 | ||
d2f7d498 HW |
2015 | static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) |
2016 | { | |
2017 | complete_userspace_rdmsr(vcpu); | |
2018 | return complete_fast_msr_access(vcpu); | |
2019 | } | |
2020 | ||
1ae09954 AG |
2021 | static u64 kvm_msr_reason(int r) |
2022 | { | |
2023 | switch (r) { | |
cc4cb017 | 2024 | case KVM_MSR_RET_INVALID: |
1ae09954 | 2025 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 2026 | case KVM_MSR_RET_FILTERED: |
1a155254 | 2027 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
2028 | default: |
2029 | return KVM_MSR_EXIT_REASON_INVAL; | |
2030 | } | |
2031 | } | |
2032 | ||
2033 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
2034 | u32 exit_reason, u64 data, | |
2035 | int (*completion)(struct kvm_vcpu *vcpu), | |
2036 | int r) | |
2037 | { | |
2038 | u64 msr_reason = kvm_msr_reason(r); | |
2039 | ||
2040 | /* Check if the user wanted to know about this MSR fault */ | |
2041 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
2042 | return 0; | |
2043 | ||
2044 | vcpu->run->exit_reason = exit_reason; | |
2045 | vcpu->run->msr.error = 0; | |
2046 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
2047 | vcpu->run->msr.reason = msr_reason; | |
2048 | vcpu->run->msr.index = index; | |
2049 | vcpu->run->msr.data = data; | |
2050 | vcpu->arch.complete_userspace_io = completion; | |
2051 | ||
2052 | return 1; | |
2053 | } | |
2054 | ||
1edce0a9 SC |
2055 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
2056 | { | |
2057 | u32 ecx = kvm_rcx_read(vcpu); | |
2058 | u64 data; | |
1ae09954 AG |
2059 | int r; |
2060 | ||
ac8d6cad | 2061 | r = kvm_get_msr_with_filter(vcpu, ecx, &data); |
1edce0a9 | 2062 | |
8b474427 PB |
2063 | if (!r) { |
2064 | trace_kvm_msr_read(ecx, data); | |
2065 | ||
2066 | kvm_rax_write(vcpu, data & -1u); | |
2067 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
2068 | } else { | |
d2f7d498 HW |
2069 | /* MSR read failed? See if we should ask user space */ |
2070 | if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, | |
2071 | complete_fast_rdmsr, r)) | |
2072 | return 0; | |
1edce0a9 | 2073 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
2074 | } |
2075 | ||
b3646477 | 2076 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
2077 | } |
2078 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
2079 | ||
2080 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
2081 | { | |
2082 | u32 ecx = kvm_rcx_read(vcpu); | |
2083 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 2084 | int r; |
1edce0a9 | 2085 | |
ac8d6cad | 2086 | r = kvm_set_msr_with_filter(vcpu, ecx, data); |
1ae09954 | 2087 | |
d2f7d498 | 2088 | if (!r) { |
8b474427 | 2089 | trace_kvm_msr_write(ecx, data); |
d2f7d498 HW |
2090 | } else { |
2091 | /* MSR write failed? See if we should ask user space */ | |
2092 | if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, | |
2093 | complete_fast_msr_access, r)) | |
2094 | return 0; | |
2095 | /* Signal all other negative errors to userspace */ | |
2096 | if (r < 0) | |
2097 | return r; | |
1edce0a9 | 2098 | trace_kvm_msr_write_ex(ecx, data); |
d2f7d498 | 2099 | } |
1edce0a9 | 2100 | |
b3646477 | 2101 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
2102 | } |
2103 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
2104 | ||
5ff3a351 SC |
2105 | int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) |
2106 | { | |
2107 | return kvm_skip_emulated_instruction(vcpu); | |
2108 | } | |
5ff3a351 SC |
2109 | |
2110 | int kvm_emulate_invd(struct kvm_vcpu *vcpu) | |
2111 | { | |
2112 | /* Treat an INVD instruction as a NOP and just skip it. */ | |
2113 | return kvm_emulate_as_nop(vcpu); | |
2114 | } | |
2115 | EXPORT_SYMBOL_GPL(kvm_emulate_invd); | |
2116 | ||
5ff3a351 SC |
2117 | int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) |
2118 | { | |
2119 | kvm_queue_exception(vcpu, UD_VECTOR); | |
2120 | return 1; | |
2121 | } | |
2122 | EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); | |
2123 | ||
bfbcc81b SC |
2124 | |
2125 | static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn) | |
5ff3a351 | 2126 | { |
43bb9e00 | 2127 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) && |
bfbcc81b SC |
2128 | !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT)) |
2129 | return kvm_handle_invalid_op(vcpu); | |
2130 | ||
8d20bd63 | 2131 | pr_warn_once("%s instruction emulated as NOP!\n", insn); |
5ff3a351 SC |
2132 | return kvm_emulate_as_nop(vcpu); |
2133 | } | |
bfbcc81b SC |
2134 | int kvm_emulate_mwait(struct kvm_vcpu *vcpu) |
2135 | { | |
2136 | return kvm_emulate_monitor_mwait(vcpu, "MWAIT"); | |
2137 | } | |
2138 | EXPORT_SYMBOL_GPL(kvm_emulate_mwait); | |
2139 | ||
2140 | int kvm_emulate_monitor(struct kvm_vcpu *vcpu) | |
2141 | { | |
2142 | return kvm_emulate_monitor_mwait(vcpu, "MONITOR"); | |
2143 | } | |
5ff3a351 SC |
2144 | EXPORT_SYMBOL_GPL(kvm_emulate_monitor); |
2145 | ||
d89d04ab | 2146 | static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
5a9f5443 | 2147 | { |
4ae7dc97 | 2148 | xfer_to_guest_mode_prepare(); |
5a9f5443 | 2149 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || |
72c3c0fe | 2150 | xfer_to_guest_mode_work_pending(); |
5a9f5443 | 2151 | } |
5a9f5443 | 2152 | |
1e9e2622 WL |
2153 | /* |
2154 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
2155 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
2156 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
2157 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
2158 | * other cases which must be called after interrupts are enabled on the host. | |
2159 | */ | |
2160 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
2161 | { | |
e1be9ac8 WL |
2162 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
2163 | return 1; | |
2164 | ||
2165 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
bd17f417 SC |
2166 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
2167 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && | |
b9964ee3 SC |
2168 | ((u32)(data >> 32) != X2APIC_BROADCAST)) |
2169 | return kvm_x2apic_icr_write(vcpu->arch.apic, data); | |
1e9e2622 WL |
2170 | |
2171 | return 1; | |
2172 | } | |
2173 | ||
ae95f566 WL |
2174 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
2175 | { | |
2176 | if (!kvm_can_use_hv_timer(vcpu)) | |
2177 | return 1; | |
2178 | ||
2179 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2180 | return 0; | |
2181 | } | |
2182 | ||
404d5d7b | 2183 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
2184 | { |
2185 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 2186 | u64 data; |
404d5d7b | 2187 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 | 2188 | |
3f2739bd SC |
2189 | kvm_vcpu_srcu_read_lock(vcpu); |
2190 | ||
1e9e2622 WL |
2191 | switch (msr) { |
2192 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 2193 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
2194 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
2195 | kvm_skip_emulated_instruction(vcpu); | |
2196 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 2197 | } |
1e9e2622 | 2198 | break; |
09141ec0 | 2199 | case MSR_IA32_TSC_DEADLINE: |
ae95f566 WL |
2200 | data = kvm_read_edx_eax(vcpu); |
2201 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
2202 | kvm_skip_emulated_instruction(vcpu); | |
2203 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
2204 | } | |
2205 | break; | |
1e9e2622 | 2206 | default: |
404d5d7b | 2207 | break; |
1e9e2622 WL |
2208 | } |
2209 | ||
404d5d7b | 2210 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 2211 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 2212 | |
3f2739bd SC |
2213 | kvm_vcpu_srcu_read_unlock(vcpu); |
2214 | ||
404d5d7b | 2215 | return ret; |
1e9e2622 WL |
2216 | } |
2217 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
2218 | ||
f20935d8 SC |
2219 | /* |
2220 | * Adapt set_msr() to msr_io()'s calling convention | |
2221 | */ | |
2222 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2223 | { | |
6abe9c13 | 2224 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
2225 | } |
2226 | ||
2227 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2228 | { | |
0094f62c SC |
2229 | u64 val; |
2230 | ||
2231 | /* | |
2232 | * Disallow writes to immutable feature MSRs after KVM_RUN. KVM does | |
2233 | * not support modifying the guest vCPU model on the fly, e.g. changing | |
2234 | * the nVMX capabilities while L2 is running is nonsensical. Ignore | |
2235 | * writes of the same value, e.g. to allow userspace to blindly stuff | |
2236 | * all MSRs when emulating RESET. | |
2237 | */ | |
2238 | if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index)) { | |
2239 | if (do_get_msr(vcpu, index, &val) || *data != val) | |
2240 | return -EINVAL; | |
2241 | ||
2242 | return 0; | |
2243 | } | |
2244 | ||
6abe9c13 | 2245 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
2246 | } |
2247 | ||
16e8d74d | 2248 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
2249 | struct pvclock_clock { |
2250 | int vclock_mode; | |
2251 | u64 cycle_last; | |
2252 | u64 mask; | |
2253 | u32 mult; | |
2254 | u32 shift; | |
917f9475 PB |
2255 | u64 base_cycles; |
2256 | u64 offset; | |
53fafdbb MT |
2257 | }; |
2258 | ||
16e8d74d MT |
2259 | struct pvclock_gtod_data { |
2260 | seqcount_t seq; | |
2261 | ||
53fafdbb MT |
2262 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
2263 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 2264 | |
917f9475 | 2265 | ktime_t offs_boot; |
55dd00a7 | 2266 | u64 wall_time_sec; |
16e8d74d MT |
2267 | }; |
2268 | ||
2269 | static struct pvclock_gtod_data pvclock_gtod_data; | |
2270 | ||
2271 | static void update_pvclock_gtod(struct timekeeper *tk) | |
2272 | { | |
2273 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
2274 | ||
2275 | write_seqcount_begin(&vdata->seq); | |
2276 | ||
2277 | /* copy pvclock gtod data */ | |
b95a8a27 | 2278 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
2279 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
2280 | vdata->clock.mask = tk->tkr_mono.mask; | |
2281 | vdata->clock.mult = tk->tkr_mono.mult; | |
2282 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
2283 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
2284 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 2285 | |
b95a8a27 | 2286 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
2287 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
2288 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
2289 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
2290 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
2291 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
2292 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 2293 | |
55dd00a7 MT |
2294 | vdata->wall_time_sec = tk->xtime_sec; |
2295 | ||
917f9475 | 2296 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 2297 | |
16e8d74d MT |
2298 | write_seqcount_end(&vdata->seq); |
2299 | } | |
8171cd68 PB |
2300 | |
2301 | static s64 get_kvmclock_base_ns(void) | |
2302 | { | |
2303 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
2304 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
2305 | } | |
2306 | #else | |
2307 | static s64 get_kvmclock_base_ns(void) | |
2308 | { | |
2309 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
2310 | return ktime_get_boottime_ns(); | |
2311 | } | |
16e8d74d MT |
2312 | #endif |
2313 | ||
55749769 | 2314 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) |
18068523 | 2315 | { |
9ed3c444 AK |
2316 | int version; |
2317 | int r; | |
50d0a0f9 | 2318 | struct pvclock_wall_clock wc; |
629b5348 | 2319 | u32 wc_sec_hi; |
8171cd68 | 2320 | u64 wall_nsec; |
18068523 GOC |
2321 | |
2322 | if (!wall_clock) | |
2323 | return; | |
2324 | ||
9ed3c444 AK |
2325 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
2326 | if (r) | |
2327 | return; | |
2328 | ||
2329 | if (version & 1) | |
2330 | ++version; /* first time write, random junk */ | |
2331 | ||
2332 | ++version; | |
18068523 | 2333 | |
1dab1345 NK |
2334 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
2335 | return; | |
18068523 | 2336 | |
5d6d6a7d | 2337 | wall_nsec = kvm_get_wall_clock_epoch(kvm); |
50d0a0f9 | 2338 | |
5d6d6a7d | 2339 | wc.nsec = do_div(wall_nsec, NSEC_PER_SEC); |
8171cd68 | 2340 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ |
50d0a0f9 | 2341 | wc.version = version; |
18068523 GOC |
2342 | |
2343 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
2344 | ||
629b5348 JM |
2345 | if (sec_hi_ofs) { |
2346 | wc_sec_hi = wall_nsec >> 32; | |
2347 | kvm_write_guest(kvm, wall_clock + sec_hi_ofs, | |
2348 | &wc_sec_hi, sizeof(wc_sec_hi)); | |
2349 | } | |
2350 | ||
18068523 GOC |
2351 | version++; |
2352 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
2353 | } |
2354 | ||
5b9bb0eb OU |
2355 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
2356 | bool old_msr, bool host_initiated) | |
2357 | { | |
2358 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
2359 | ||
2360 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2361 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2362 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2363 | ||
2364 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2365 | } | |
2366 | ||
2367 | vcpu->arch.time = system_time; | |
2368 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2369 | ||
2370 | /* we verify if the enable bit is set... */ | |
8c82a0b3 ML |
2371 | if (system_time & 1) |
2372 | kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL, | |
52491a38 | 2373 | sizeof(struct pvclock_vcpu_time_info)); |
8c82a0b3 ML |
2374 | else |
2375 | kvm_gpc_deactivate(&vcpu->arch.pv_time); | |
5b9bb0eb OU |
2376 | |
2377 | return; | |
2378 | } | |
2379 | ||
50d0a0f9 GH |
2380 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2381 | { | |
b51012de PB |
2382 | do_shl32_div32(dividend, divisor); |
2383 | return dividend; | |
50d0a0f9 GH |
2384 | } |
2385 | ||
3ae13faa | 2386 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2387 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2388 | { |
5f4e3f88 | 2389 | uint64_t scaled64; |
50d0a0f9 GH |
2390 | int32_t shift = 0; |
2391 | uint64_t tps64; | |
2392 | uint32_t tps32; | |
2393 | ||
3ae13faa PB |
2394 | tps64 = base_hz; |
2395 | scaled64 = scaled_hz; | |
50933623 | 2396 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2397 | tps64 >>= 1; |
2398 | shift--; | |
2399 | } | |
2400 | ||
2401 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2402 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2403 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2404 | scaled64 >>= 1; |
2405 | else | |
2406 | tps32 <<= 1; | |
50d0a0f9 GH |
2407 | shift++; |
2408 | } | |
2409 | ||
5f4e3f88 ZA |
2410 | *pshift = shift; |
2411 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2412 | } |
2413 | ||
d828199e | 2414 | #ifdef CONFIG_X86_64 |
16e8d74d | 2415 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2416 | #endif |
16e8d74d | 2417 | |
c8076604 | 2418 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2419 | static unsigned long max_tsc_khz; |
c8076604 | 2420 | |
cc578287 | 2421 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2422 | { |
cc578287 ZA |
2423 | u64 v = (u64)khz * (1000000 + ppm); |
2424 | do_div(v, 1000000); | |
2425 | return v; | |
1e993611 JR |
2426 | } |
2427 | ||
1ab9287a IS |
2428 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); |
2429 | ||
381d585c HZ |
2430 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2431 | { | |
2432 | u64 ratio; | |
2433 | ||
2434 | /* Guest TSC same frequency as host TSC? */ | |
2435 | if (!scale) { | |
938c8745 | 2436 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); |
381d585c HZ |
2437 | return 0; |
2438 | } | |
2439 | ||
2440 | /* TSC scaling supported? */ | |
938c8745 | 2441 | if (!kvm_caps.has_tsc_control) { |
381d585c HZ |
2442 | if (user_tsc_khz > tsc_khz) { |
2443 | vcpu->arch.tsc_catchup = 1; | |
2444 | vcpu->arch.tsc_always_catchup = 1; | |
2445 | return 0; | |
2446 | } else { | |
3f16a5c3 | 2447 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2448 | return -1; |
2449 | } | |
2450 | } | |
2451 | ||
2452 | /* TSC scaling required - calculate ratio */ | |
938c8745 | 2453 | ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits, |
381d585c HZ |
2454 | user_tsc_khz, tsc_khz); |
2455 | ||
938c8745 | 2456 | if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) { |
3f16a5c3 PB |
2457 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2458 | user_tsc_khz); | |
381d585c HZ |
2459 | return -1; |
2460 | } | |
2461 | ||
1ab9287a | 2462 | kvm_vcpu_write_tsc_multiplier(vcpu, ratio); |
381d585c HZ |
2463 | return 0; |
2464 | } | |
2465 | ||
4941b8cb | 2466 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2467 | { |
cc578287 ZA |
2468 | u32 thresh_lo, thresh_hi; |
2469 | int use_scaling = 0; | |
217fc9cf | 2470 | |
03ba32ca | 2471 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2472 | if (user_tsc_khz == 0) { |
ad721883 | 2473 | /* set tsc_scaling_ratio to a safe value */ |
938c8745 | 2474 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); |
381d585c | 2475 | return -1; |
ad721883 | 2476 | } |
03ba32ca | 2477 | |
c285545f | 2478 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2479 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2480 | &vcpu->arch.virtual_tsc_shift, |
2481 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2482 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2483 | |
2484 | /* | |
2485 | * Compute the variation in TSC rate which is acceptable | |
2486 | * within the range of tolerance and decide if the | |
2487 | * rate being applied is within that bounds of the hardware | |
2488 | * rate. If so, no scaling or compensation need be done. | |
2489 | */ | |
2490 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2491 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb | 2492 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
8d20bd63 SC |
2493 | pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n", |
2494 | user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2495 | use_scaling = 1; |
2496 | } | |
4941b8cb | 2497 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2498 | } |
2499 | ||
2500 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2501 | { | |
e26101b1 | 2502 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2503 | vcpu->arch.virtual_tsc_mult, |
2504 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2505 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2506 | return tsc; |
2507 | } | |
2508 | ||
ba1f77c5 | 2509 | #ifdef CONFIG_X86_64 |
b0c39dc6 VK |
2510 | static inline int gtod_is_based_on_tsc(int mode) |
2511 | { | |
b95a8a27 | 2512 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 | 2513 | } |
ba1f77c5 | 2514 | #endif |
b0c39dc6 | 2515 | |
c52ffadc | 2516 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu, bool new_generation) |
b48aa97e MT |
2517 | { |
2518 | #ifdef CONFIG_X86_64 | |
b48aa97e MT |
2519 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2520 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2521 | ||
c52ffadc SC |
2522 | /* |
2523 | * To use the masterclock, the host clocksource must be based on TSC | |
2524 | * and all vCPUs must have matching TSCs. Note, the count for matching | |
2525 | * vCPUs doesn't include the reference vCPU, hence "+1". | |
2526 | */ | |
2527 | bool use_master_clock = (ka->nr_vcpus_matched_tsc + 1 == | |
2528 | atomic_read(&vcpu->kvm->online_vcpus)) && | |
2529 | gtod_is_based_on_tsc(gtod->clock.vclock_mode); | |
b48aa97e | 2530 | |
7f187922 | 2531 | /* |
c52ffadc SC |
2532 | * Request a masterclock update if the masterclock needs to be toggled |
2533 | * on/off, or when starting a new generation and the masterclock is | |
2534 | * enabled (compute_guest_tsc() requires the masterclock snapshot to be | |
2535 | * taken _after_ the new generation is created). | |
7f187922 | 2536 | */ |
c52ffadc SC |
2537 | if ((ka->use_master_clock && new_generation) || |
2538 | (ka->use_master_clock != use_master_clock)) | |
b48aa97e MT |
2539 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2540 | ||
2541 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2542 | atomic_read(&vcpu->kvm->online_vcpus), | |
2543 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2544 | #endif | |
2545 | } | |
2546 | ||
35181e86 HZ |
2547 | /* |
2548 | * Multiply tsc by a fixed point number represented by ratio. | |
2549 | * | |
2550 | * The most significant 64-N bits (mult) of ratio represent the | |
2551 | * integral part of the fixed point number; the remaining N bits | |
2552 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2553 | * point number (mult + frac * 2^(-N)). | |
2554 | * | |
938c8745 | 2555 | * N equals to kvm_caps.tsc_scaling_ratio_frac_bits. |
35181e86 HZ |
2556 | */ |
2557 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2558 | { | |
938c8745 | 2559 | return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits); |
35181e86 HZ |
2560 | } |
2561 | ||
62711e5a | 2562 | u64 kvm_scale_tsc(u64 tsc, u64 ratio) |
35181e86 HZ |
2563 | { |
2564 | u64 _tsc = tsc; | |
35181e86 | 2565 | |
938c8745 | 2566 | if (ratio != kvm_caps.default_tsc_scaling_ratio) |
35181e86 HZ |
2567 | _tsc = __scale_tsc(ratio, tsc); |
2568 | ||
2569 | return _tsc; | |
2570 | } | |
35181e86 | 2571 | |
9b399dfd | 2572 | static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
07c1419a HZ |
2573 | { |
2574 | u64 tsc; | |
2575 | ||
62711e5a | 2576 | tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); |
07c1419a HZ |
2577 | |
2578 | return target_tsc - tsc; | |
2579 | } | |
2580 | ||
4ba76538 HZ |
2581 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2582 | { | |
fe3eb504 | 2583 | return vcpu->arch.l1_tsc_offset + |
62711e5a | 2584 | kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio); |
4ba76538 HZ |
2585 | } |
2586 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2587 | ||
83150f29 IS |
2588 | u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) |
2589 | { | |
2590 | u64 nested_offset; | |
2591 | ||
938c8745 | 2592 | if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio) |
83150f29 IS |
2593 | nested_offset = l1_offset; |
2594 | else | |
2595 | nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, | |
938c8745 | 2596 | kvm_caps.tsc_scaling_ratio_frac_bits); |
83150f29 IS |
2597 | |
2598 | nested_offset += l2_offset; | |
2599 | return nested_offset; | |
2600 | } | |
2601 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); | |
2602 | ||
2603 | u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) | |
2604 | { | |
938c8745 | 2605 | if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio) |
83150f29 | 2606 | return mul_u64_u64_shr(l1_multiplier, l2_multiplier, |
938c8745 | 2607 | kvm_caps.tsc_scaling_ratio_frac_bits); |
83150f29 IS |
2608 | |
2609 | return l1_multiplier; | |
2610 | } | |
2611 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); | |
2612 | ||
edcfe540 | 2613 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) |
a545ab6a | 2614 | { |
edcfe540 IS |
2615 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2616 | vcpu->arch.l1_tsc_offset, | |
2617 | l1_offset); | |
2618 | ||
2619 | vcpu->arch.l1_tsc_offset = l1_offset; | |
2620 | ||
2621 | /* | |
2622 | * If we are here because L1 chose not to trap WRMSR to TSC then | |
2623 | * according to the spec this should set L1's TSC (as opposed to | |
2624 | * setting L1's offset for L2). | |
2625 | */ | |
2626 | if (is_guest_mode(vcpu)) | |
2627 | vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( | |
2628 | l1_offset, | |
2629 | static_call(kvm_x86_get_l2_tsc_offset)(vcpu), | |
2630 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2631 | else | |
2632 | vcpu->arch.tsc_offset = l1_offset; | |
2633 | ||
2d636990 | 2634 | static_call(kvm_x86_write_tsc_offset)(vcpu); |
a545ab6a LC |
2635 | } |
2636 | ||
1ab9287a IS |
2637 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) |
2638 | { | |
2639 | vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; | |
2640 | ||
2641 | /* Userspace is changing the multiplier while L2 is active */ | |
2642 | if (is_guest_mode(vcpu)) | |
2643 | vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( | |
2644 | l1_multiplier, | |
2645 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2646 | else | |
2647 | vcpu->arch.tsc_scaling_ratio = l1_multiplier; | |
2648 | ||
938c8745 | 2649 | if (kvm_caps.has_tsc_control) |
2d636990 | 2650 | static_call(kvm_x86_write_tsc_multiplier)(vcpu); |
1ab9287a IS |
2651 | } |
2652 | ||
b0c39dc6 VK |
2653 | static inline bool kvm_check_tsc_unstable(void) |
2654 | { | |
2655 | #ifdef CONFIG_X86_64 | |
2656 | /* | |
2657 | * TSC is marked unstable when we're running on Hyper-V, | |
2658 | * 'TSC page' clocksource is good. | |
2659 | */ | |
b95a8a27 | 2660 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2661 | return false; |
2662 | #endif | |
2663 | return check_tsc_unstable(); | |
2664 | } | |
2665 | ||
58d4277b OU |
2666 | /* |
2667 | * Infers attempts to synchronize the guest's tsc from host writes. Sets the | |
2668 | * offset for the vcpu and tracks the TSC matching generation that the vcpu | |
2669 | * participates in. | |
2670 | */ | |
2671 | static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, | |
2672 | u64 ns, bool matched) | |
2673 | { | |
2674 | struct kvm *kvm = vcpu->kvm; | |
2675 | ||
2676 | lockdep_assert_held(&kvm->arch.tsc_write_lock); | |
2677 | ||
2678 | /* | |
2679 | * We also track th most recent recorded KHZ, write and time to | |
2680 | * allow the matching interval to be extended at each write. | |
2681 | */ | |
2682 | kvm->arch.last_tsc_nsec = ns; | |
2683 | kvm->arch.last_tsc_write = tsc; | |
2684 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
828ca896 | 2685 | kvm->arch.last_tsc_offset = offset; |
58d4277b OU |
2686 | |
2687 | vcpu->arch.last_guest_tsc = tsc; | |
2688 | ||
2689 | kvm_vcpu_write_tsc_offset(vcpu, offset); | |
2690 | ||
2691 | if (!matched) { | |
2692 | /* | |
2693 | * We split periods of matched TSC writes into generations. | |
2694 | * For each generation, we track the original measured | |
2695 | * nanosecond time, offset, and write, so if TSCs are in | |
2696 | * sync, we can match exact offset, and if not, we can match | |
2697 | * exact software computation in compute_guest_tsc() | |
2698 | * | |
2699 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2700 | */ | |
2701 | kvm->arch.cur_tsc_generation++; | |
2702 | kvm->arch.cur_tsc_nsec = ns; | |
2703 | kvm->arch.cur_tsc_write = tsc; | |
2704 | kvm->arch.cur_tsc_offset = offset; | |
2705 | kvm->arch.nr_vcpus_matched_tsc = 0; | |
2706 | } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { | |
2707 | kvm->arch.nr_vcpus_matched_tsc++; | |
2708 | } | |
2709 | ||
2710 | /* Keep track of which generation this VCPU has synchronized to */ | |
2711 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2712 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2713 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2714 | ||
c52ffadc | 2715 | kvm_track_tsc_matching(vcpu, !matched); |
58d4277b OU |
2716 | } |
2717 | ||
bf328e22 | 2718 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 *user_value) |
99e3e30a | 2719 | { |
bf328e22 | 2720 | u64 data = user_value ? *user_value : 0; |
99e3e30a | 2721 | struct kvm *kvm = vcpu->kvm; |
f38e098f | 2722 | u64 offset, ns, elapsed; |
99e3e30a | 2723 | unsigned long flags; |
58d4277b | 2724 | bool matched = false; |
c5e8ec8e | 2725 | bool synchronizing = false; |
99e3e30a | 2726 | |
038f8c11 | 2727 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
9b399dfd | 2728 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
8171cd68 | 2729 | ns = get_kvmclock_base_ns(); |
f38e098f | 2730 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2731 | |
03ba32ca | 2732 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2733 | if (data == 0) { |
bd8fab39 | 2734 | /* |
bf328e22 LX |
2735 | * Force synchronization when creating a vCPU, or when |
2736 | * userspace explicitly writes a zero value. | |
bd8fab39 DP |
2737 | */ |
2738 | synchronizing = true; | |
bf328e22 | 2739 | } else if (kvm->arch.user_set_tsc) { |
bd8fab39 DP |
2740 | u64 tsc_exp = kvm->arch.last_tsc_write + |
2741 | nsec_to_cycles(vcpu, elapsed); | |
2742 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2743 | /* | |
bf328e22 LX |
2744 | * Here lies UAPI baggage: when a user-initiated TSC write has |
2745 | * a small delta (1 second) of virtual cycle time against the | |
2746 | * previously set vCPU, we assume that they were intended to be | |
2747 | * in sync and the delta was only due to the racy nature of the | |
2748 | * legacy API. | |
2749 | * | |
2750 | * This trick falls down when restoring a guest which genuinely | |
2751 | * has been running for less time than the 1 second of imprecision | |
2752 | * which we allow for in the legacy API. In this case, the first | |
2753 | * value written by userspace (on any vCPU) should not be subject | |
2754 | * to this 'correction' to make it sync up with values that only | |
2755 | * come from the kernel's default vCPU creation. Make the 1-second | |
2756 | * slop hack only trigger if the user_set_tsc flag is already set. | |
bd8fab39 DP |
2757 | */ |
2758 | synchronizing = data < tsc_exp + tsc_hz && | |
2759 | data + tsc_hz > tsc_exp; | |
2760 | } | |
c5e8ec8e | 2761 | } |
f38e098f | 2762 | |
bf328e22 LX |
2763 | if (user_value) |
2764 | kvm->arch.user_set_tsc = true; | |
2765 | ||
f38e098f | 2766 | /* |
5d3cb0f6 ZA |
2767 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2768 | * TSC, we add elapsed time in this computation. We could let the | |
2769 | * compensation code attempt to catch up if we fall behind, but | |
2770 | * it's better to try to match offsets from the beginning. | |
2771 | */ | |
c5e8ec8e | 2772 | if (synchronizing && |
5d3cb0f6 | 2773 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2774 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2775 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2776 | } else { |
857e4099 | 2777 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2778 | data += delta; |
9b399dfd | 2779 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
f38e098f | 2780 | } |
b48aa97e | 2781 | matched = true; |
f38e098f | 2782 | } |
e26101b1 | 2783 | |
58d4277b | 2784 | __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); |
e26101b1 | 2785 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
99e3e30a | 2786 | } |
e26101b1 | 2787 | |
58ea6767 HZ |
2788 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2789 | s64 adjustment) | |
2790 | { | |
56ba77a4 | 2791 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2792 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2793 | } |
2794 | ||
2795 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2796 | { | |
938c8745 | 2797 | if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio) |
58ea6767 | 2798 | WARN_ON(adjustment < 0); |
62711e5a | 2799 | adjustment = kvm_scale_tsc((u64) adjustment, |
fe3eb504 | 2800 | vcpu->arch.l1_tsc_scaling_ratio); |
ea26e4ec | 2801 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2802 | } |
2803 | ||
d828199e MT |
2804 | #ifdef CONFIG_X86_64 |
2805 | ||
a5a1d1c2 | 2806 | static u64 read_tsc(void) |
d828199e | 2807 | { |
a5a1d1c2 | 2808 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2809 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2810 | |
2811 | if (likely(ret >= last)) | |
2812 | return ret; | |
2813 | ||
2814 | /* | |
2815 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2816 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2817 | * very likely) and there's a data dependence, so force GCC |
2818 | * to generate a branch instead. I don't barrier() because | |
2819 | * we don't actually need a barrier, and if this function | |
2820 | * ever gets inlined it will generate worse code. | |
2821 | */ | |
2822 | asm volatile (""); | |
2823 | return last; | |
2824 | } | |
2825 | ||
53fafdbb MT |
2826 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2827 | int *mode) | |
d828199e | 2828 | { |
b0c39dc6 | 2829 | u64 tsc_pg_val; |
9397fa2e | 2830 | long v; |
b0c39dc6 | 2831 | |
53fafdbb | 2832 | switch (clock->vclock_mode) { |
b95a8a27 | 2833 | case VDSO_CLOCKMODE_HVCLOCK: |
9397fa2e PZ |
2834 | if (hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2835 | tsc_timestamp, &tsc_pg_val)) { | |
b0c39dc6 | 2836 | /* TSC page valid */ |
b95a8a27 | 2837 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2838 | v = (tsc_pg_val - clock->cycle_last) & |
2839 | clock->mask; | |
b0c39dc6 VK |
2840 | } else { |
2841 | /* TSC page invalid */ | |
b95a8a27 | 2842 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2843 | } |
2844 | break; | |
b95a8a27 TG |
2845 | case VDSO_CLOCKMODE_TSC: |
2846 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2847 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2848 | v = (*tsc_timestamp - clock->cycle_last) & |
2849 | clock->mask; | |
b0c39dc6 VK |
2850 | break; |
2851 | default: | |
b95a8a27 | 2852 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2853 | } |
d828199e | 2854 | |
b95a8a27 | 2855 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2856 | *tsc_timestamp = v = 0; |
d828199e | 2857 | |
53fafdbb | 2858 | return v * clock->mult; |
d828199e MT |
2859 | } |
2860 | ||
53fafdbb | 2861 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2862 | { |
cbcf2dd3 | 2863 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2864 | unsigned long seq; |
d828199e | 2865 | int mode; |
cbcf2dd3 | 2866 | u64 ns; |
d828199e | 2867 | |
d828199e MT |
2868 | do { |
2869 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2870 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2871 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2872 | ns >>= gtod->raw_clock.shift; |
2873 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2874 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2875 | *t = ns; |
d828199e MT |
2876 | |
2877 | return mode; | |
2878 | } | |
2879 | ||
899a31f5 | 2880 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2881 | { |
2882 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2883 | unsigned long seq; | |
2884 | int mode; | |
2885 | u64 ns; | |
2886 | ||
2887 | do { | |
2888 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2889 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2890 | ns = gtod->clock.base_cycles; |
53fafdbb | 2891 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2892 | ns >>= gtod->clock.shift; |
2893 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2894 | ||
2895 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2896 | ts->tv_nsec = ns; | |
2897 | ||
2898 | return mode; | |
2899 | } | |
2900 | ||
b0c39dc6 VK |
2901 | /* returns true if host is using TSC based clocksource */ |
2902 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2903 | { |
d828199e | 2904 | /* checked again under seqlock below */ |
b0c39dc6 | 2905 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2906 | return false; |
2907 | ||
53fafdbb | 2908 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2909 | tsc_timestamp)); |
d828199e | 2910 | } |
55dd00a7 | 2911 | |
b0c39dc6 | 2912 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2913 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2914 | u64 *tsc_timestamp) |
55dd00a7 MT |
2915 | { |
2916 | /* checked again under seqlock below */ | |
b0c39dc6 | 2917 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2918 | return false; |
2919 | ||
b0c39dc6 | 2920 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2921 | } |
d828199e MT |
2922 | #endif |
2923 | ||
2924 | /* | |
2925 | * | |
b48aa97e MT |
2926 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2927 | * across virtual CPUs, the following condition is possible. | |
2928 | * Each numbered line represents an event visible to both | |
d828199e MT |
2929 | * CPUs at the next numbered event. |
2930 | * | |
2931 | * "timespecX" represents host monotonic time. "tscX" represents | |
2932 | * RDTSC value. | |
2933 | * | |
2934 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2935 | * | |
2936 | * 1. read timespec0,tsc0 | |
2937 | * 2. | timespec1 = timespec0 + N | |
2938 | * | tsc1 = tsc0 + M | |
2939 | * 3. transition to guest | transition to guest | |
2940 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2941 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2942 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2943 | * | |
2944 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2945 | * | |
2946 | * - ret0 < ret1 | |
2947 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2948 | * ... | |
2949 | * - 0 < N - M => M < N | |
2950 | * | |
2951 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2952 | * always the case (the difference between two distinct xtime instances | |
2953 | * might be smaller then the difference between corresponding TSC reads, | |
2954 | * when updating guest vcpus pvclock areas). | |
2955 | * | |
2956 | * To avoid that problem, do not allow visibility of distinct | |
2957 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2958 | * copy of host monotonic time values. Update that master copy | |
2959 | * in lockstep. | |
2960 | * | |
b48aa97e | 2961 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2962 | * |
2963 | */ | |
2964 | ||
2965 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2966 | { | |
2967 | #ifdef CONFIG_X86_64 | |
2968 | struct kvm_arch *ka = &kvm->arch; | |
2969 | int vclock_mode; | |
b48aa97e MT |
2970 | bool host_tsc_clocksource, vcpus_matched; |
2971 | ||
869b4421 | 2972 | lockdep_assert_held(&kvm->arch.tsc_write_lock); |
b48aa97e MT |
2973 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == |
2974 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2975 | |
2976 | /* | |
2977 | * If the host uses TSC clock, then passthrough TSC as stable | |
2978 | * to the guest. | |
2979 | */ | |
b48aa97e | 2980 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2981 | &ka->master_kernel_ns, |
2982 | &ka->master_cycle_now); | |
2983 | ||
16a96021 | 2984 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2985 | && !ka->backwards_tsc_observed |
54750f2c | 2986 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2987 | |
d828199e MT |
2988 | if (ka->use_master_clock) |
2989 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2990 | ||
2991 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2992 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2993 | vcpus_matched); | |
d828199e MT |
2994 | #endif |
2995 | } | |
2996 | ||
6b6fcd28 | 2997 | static void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2860c4b1 PB |
2998 | { |
2999 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
3000 | } | |
3001 | ||
869b4421 | 3002 | static void __kvm_start_pvclock_update(struct kvm *kvm) |
2e762ff7 | 3003 | { |
869b4421 PB |
3004 | raw_spin_lock_irq(&kvm->arch.tsc_write_lock); |
3005 | write_seqcount_begin(&kvm->arch.pvclock_sc); | |
3006 | } | |
e880c6ea | 3007 | |
869b4421 PB |
3008 | static void kvm_start_pvclock_update(struct kvm *kvm) |
3009 | { | |
2e762ff7 | 3010 | kvm_make_mclock_inprogress_request(kvm); |
c2c647f9 | 3011 | |
2e762ff7 | 3012 | /* no guest entries from this point */ |
869b4421 | 3013 | __kvm_start_pvclock_update(kvm); |
6b6fcd28 | 3014 | } |
2e762ff7 | 3015 | |
6b6fcd28 PB |
3016 | static void kvm_end_pvclock_update(struct kvm *kvm) |
3017 | { | |
3018 | struct kvm_arch *ka = &kvm->arch; | |
3019 | struct kvm_vcpu *vcpu; | |
46808a4c | 3020 | unsigned long i; |
2e762ff7 | 3021 | |
869b4421 PB |
3022 | write_seqcount_end(&ka->pvclock_sc); |
3023 | raw_spin_unlock_irq(&ka->tsc_write_lock); | |
2e762ff7 | 3024 | kvm_for_each_vcpu(i, vcpu, kvm) |
105b21bb | 3025 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
3026 | |
3027 | /* guest entries allowed */ | |
3028 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 3029 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
3030 | } |
3031 | ||
6b6fcd28 PB |
3032 | static void kvm_update_masterclock(struct kvm *kvm) |
3033 | { | |
42dcbe7d | 3034 | kvm_hv_request_tsc_page_update(kvm); |
6b6fcd28 PB |
3035 | kvm_start_pvclock_update(kvm); |
3036 | pvclock_update_vm_gtod_copy(kvm); | |
3037 | kvm_end_pvclock_update(kvm); | |
2e762ff7 MT |
3038 | } |
3039 | ||
3ebcbd22 AR |
3040 | /* |
3041 | * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's | |
3042 | * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz | |
3043 | * can change during boot even if the TSC is constant, as it's possible for KVM | |
3044 | * to be loaded before TSC calibration completes. Ideally, KVM would get a | |
3045 | * notification when calibration completes, but practically speaking calibration | |
3046 | * will complete before userspace is alive enough to create VMs. | |
3047 | */ | |
3048 | static unsigned long get_cpu_tsc_khz(void) | |
3049 | { | |
3050 | if (static_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
3051 | return tsc_khz; | |
3052 | else | |
3053 | return __this_cpu_read(cpu_tsc_khz); | |
3054 | } | |
3055 | ||
869b4421 PB |
3056 | /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ |
3057 | static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) | |
108b249c | 3058 | { |
108b249c | 3059 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 3060 | struct pvclock_vcpu_time_info hv_clock; |
8b953440 | 3061 | |
e2c2206a WL |
3062 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
3063 | get_cpu(); | |
3064 | ||
869b4421 | 3065 | data->flags = 0; |
3ebcbd22 AR |
3066 | if (ka->use_master_clock && |
3067 | (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) { | |
c68dc1b5 OU |
3068 | #ifdef CONFIG_X86_64 |
3069 | struct timespec64 ts; | |
3070 | ||
3071 | if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { | |
3072 | data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; | |
3073 | data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; | |
3074 | } else | |
3075 | #endif | |
3076 | data->host_tsc = rdtsc(); | |
3077 | ||
869b4421 PB |
3078 | data->flags |= KVM_CLOCK_TSC_STABLE; |
3079 | hv_clock.tsc_timestamp = ka->master_cycle_now; | |
3080 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
3ebcbd22 | 3081 | kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL, |
e70b57a6 WL |
3082 | &hv_clock.tsc_shift, |
3083 | &hv_clock.tsc_to_system_mul); | |
c68dc1b5 | 3084 | data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); |
55c0cefb OU |
3085 | } else { |
3086 | data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; | |
3087 | } | |
e2c2206a WL |
3088 | |
3089 | put_cpu(); | |
55c0cefb | 3090 | } |
e2c2206a | 3091 | |
869b4421 PB |
3092 | static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) |
3093 | { | |
3094 | struct kvm_arch *ka = &kvm->arch; | |
3095 | unsigned seq; | |
3096 | ||
3097 | do { | |
3098 | seq = read_seqcount_begin(&ka->pvclock_sc); | |
3099 | __get_kvmclock(kvm, data); | |
3100 | } while (read_seqcount_retry(&ka->pvclock_sc, seq)); | |
3101 | } | |
3102 | ||
55c0cefb OU |
3103 | u64 get_kvmclock_ns(struct kvm *kvm) |
3104 | { | |
3105 | struct kvm_clock_data data; | |
3106 | ||
55c0cefb OU |
3107 | get_kvmclock(kvm, &data); |
3108 | return data.clock; | |
108b249c PB |
3109 | } |
3110 | ||
916d3608 DW |
3111 | static void kvm_setup_guest_pvclock(struct kvm_vcpu *v, |
3112 | struct gfn_to_pfn_cache *gpc, | |
6d722835 PD |
3113 | unsigned int offset, |
3114 | bool force_tsc_unstable) | |
0d6dd2ff PB |
3115 | { |
3116 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
916d3608 DW |
3117 | struct pvclock_vcpu_time_info *guest_hv_clock; |
3118 | unsigned long flags; | |
0d6dd2ff | 3119 | |
916d3608 | 3120 | read_lock_irqsave(&gpc->lock, flags); |
58f5ee5f | 3121 | while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) { |
916d3608 DW |
3122 | read_unlock_irqrestore(&gpc->lock, flags); |
3123 | ||
58f5ee5f | 3124 | if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock))) |
916d3608 | 3125 | return; |
0d6dd2ff | 3126 | |
916d3608 DW |
3127 | read_lock_irqsave(&gpc->lock, flags); |
3128 | } | |
3129 | ||
3130 | guest_hv_clock = (void *)(gpc->khva + offset); | |
3131 | ||
3132 | /* | |
3133 | * This VCPU is paused, but it's legal for a guest to read another | |
0d6dd2ff PB |
3134 | * VCPU's kvmclock, so we really have to follow the specification where |
3135 | * it says that version is odd if data is being modified, and even after | |
3136 | * it is consistent. | |
0d6dd2ff | 3137 | */ |
0d6dd2ff | 3138 | |
916d3608 | 3139 | guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1; |
0d6dd2ff PB |
3140 | smp_wmb(); |
3141 | ||
3142 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
916d3608 | 3143 | vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED); |
0d6dd2ff PB |
3144 | |
3145 | if (vcpu->pvclock_set_guest_stopped_request) { | |
3146 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
3147 | vcpu->pvclock_set_guest_stopped_request = false; | |
3148 | } | |
3149 | ||
916d3608 | 3150 | memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock)); |
6d722835 PD |
3151 | |
3152 | if (force_tsc_unstable) | |
3153 | guest_hv_clock->flags &= ~PVCLOCK_TSC_STABLE_BIT; | |
3154 | ||
916d3608 | 3155 | smp_wmb(); |
0d6dd2ff | 3156 | |
916d3608 | 3157 | guest_hv_clock->version = ++vcpu->hv_clock.version; |
0d6dd2ff | 3158 | |
916d3608 DW |
3159 | mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT); |
3160 | read_unlock_irqrestore(&gpc->lock, flags); | |
0d6dd2ff | 3161 | |
916d3608 | 3162 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
0d6dd2ff PB |
3163 | } |
3164 | ||
34c238a1 | 3165 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 3166 | { |
78db6a50 | 3167 | unsigned long flags, tgt_tsc_khz; |
869b4421 | 3168 | unsigned seq; |
18068523 | 3169 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 3170 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 3171 | s64 kernel_ns; |
d828199e | 3172 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 3173 | u8 pvclock_flags; |
d828199e | 3174 | bool use_master_clock; |
6d722835 PD |
3175 | #ifdef CONFIG_KVM_XEN |
3176 | /* | |
3177 | * For Xen guests we may need to override PVCLOCK_TSC_STABLE_BIT as unless | |
3178 | * explicitly told to use TSC as its clocksource Xen will not set this bit. | |
3179 | * This default behaviour led to bugs in some guest kernels which cause | |
3180 | * problems if they observe PVCLOCK_TSC_STABLE_BIT in the pvclock flags. | |
3181 | */ | |
3182 | bool xen_pvclock_tsc_unstable = | |
3183 | ka->xen_hvm_config.flags & KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE; | |
3184 | #endif | |
d828199e MT |
3185 | |
3186 | kernel_ns = 0; | |
3187 | host_tsc = 0; | |
18068523 | 3188 | |
d828199e MT |
3189 | /* |
3190 | * If the host uses TSC clock, then passthrough TSC as stable | |
3191 | * to the guest. | |
3192 | */ | |
869b4421 PB |
3193 | do { |
3194 | seq = read_seqcount_begin(&ka->pvclock_sc); | |
3195 | use_master_clock = ka->use_master_clock; | |
3196 | if (use_master_clock) { | |
3197 | host_tsc = ka->master_cycle_now; | |
3198 | kernel_ns = ka->master_kernel_ns; | |
3199 | } | |
3200 | } while (read_seqcount_retry(&ka->pvclock_sc, seq)); | |
c09664bb MT |
3201 | |
3202 | /* Keep irq disabled to prevent changes to the clock */ | |
3203 | local_irq_save(flags); | |
3ebcbd22 | 3204 | tgt_tsc_khz = get_cpu_tsc_khz(); |
78db6a50 | 3205 | if (unlikely(tgt_tsc_khz == 0)) { |
c09664bb MT |
3206 | local_irq_restore(flags); |
3207 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
3208 | return 1; | |
3209 | } | |
d828199e | 3210 | if (!use_master_clock) { |
4ea1636b | 3211 | host_tsc = rdtsc(); |
8171cd68 | 3212 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
3213 | } |
3214 | ||
4ba76538 | 3215 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 3216 | |
c285545f ZA |
3217 | /* |
3218 | * We may have to catch up the TSC to match elapsed wall clock | |
3219 | * time for two reasons, even if kvmclock is used. | |
3220 | * 1) CPU could have been running below the maximum TSC rate | |
3221 | * 2) Broken TSC compensation resets the base at each VCPU | |
3222 | * entry to avoid unknown leaps of TSC even when running | |
3223 | * again on the same CPU. This may cause apparent elapsed | |
3224 | * time to disappear, and the guest to stand still or run | |
3225 | * very slowly. | |
3226 | */ | |
3227 | if (vcpu->tsc_catchup) { | |
3228 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
3229 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 3230 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
3231 | tsc_timestamp = tsc; |
3232 | } | |
50d0a0f9 GH |
3233 | } |
3234 | ||
18068523 GOC |
3235 | local_irq_restore(flags); |
3236 | ||
0d6dd2ff | 3237 | /* With all the info we got, fill in the values */ |
18068523 | 3238 | |
938c8745 | 3239 | if (kvm_caps.has_tsc_control) |
62711e5a | 3240 | tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz, |
fe3eb504 | 3241 | v->arch.l1_tsc_scaling_ratio); |
78db6a50 PB |
3242 | |
3243 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 3244 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
3245 | &vcpu->hv_clock.tsc_shift, |
3246 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 3247 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
f422f853 | 3248 | kvm_xen_update_tsc_info(v); |
8cfdc000 ZA |
3249 | } |
3250 | ||
1d5f066e | 3251 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 3252 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 3253 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 3254 | |
d828199e | 3255 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 3256 | pvclock_flags = 0; |
d828199e MT |
3257 | if (use_master_clock) |
3258 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
3259 | ||
78c0337a MT |
3260 | vcpu->hv_clock.flags = pvclock_flags; |
3261 | ||
916d3608 | 3262 | if (vcpu->pv_time.active) |
6d722835 | 3263 | kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0, false); |
ee11ab6b | 3264 | #ifdef CONFIG_KVM_XEN |
7caf9571 DW |
3265 | if (vcpu->xen.vcpu_info_cache.active) |
3266 | kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache, | |
6d722835 PD |
3267 | offsetof(struct compat_vcpu_info, time), |
3268 | xen_pvclock_tsc_unstable); | |
69d413cf | 3269 | if (vcpu->xen.vcpu_time_info_cache.active) |
6d722835 PD |
3270 | kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0, |
3271 | xen_pvclock_tsc_unstable); | |
ee11ab6b | 3272 | #endif |
42dcbe7d | 3273 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); |
8cfdc000 | 3274 | return 0; |
c8076604 GH |
3275 | } |
3276 | ||
5d6d6a7d DW |
3277 | /* |
3278 | * The pvclock_wall_clock ABI tells the guest the wall clock time at | |
3279 | * which it started (i.e. its epoch, when its kvmclock was zero). | |
3280 | * | |
3281 | * In fact those clocks are subtly different; wall clock frequency is | |
3282 | * adjusted by NTP and has leap seconds, while the kvmclock is a | |
3283 | * simple function of the TSC without any such adjustment. | |
3284 | * | |
3285 | * Perhaps the ABI should have exposed CLOCK_TAI and a ratio between | |
3286 | * that and kvmclock, but even that would be subject to change over | |
3287 | * time. | |
3288 | * | |
3289 | * Attempt to calculate the epoch at a given moment using the *same* | |
3290 | * TSC reading via kvm_get_walltime_and_clockread() to obtain both | |
3291 | * wallclock and kvmclock times, and subtracting one from the other. | |
3292 | * | |
3293 | * Fall back to using their values at slightly different moments by | |
3294 | * calling ktime_get_real_ns() and get_kvmclock_ns() separately. | |
3295 | */ | |
3296 | uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm) | |
3297 | { | |
3298 | #ifdef CONFIG_X86_64 | |
3299 | struct pvclock_vcpu_time_info hv_clock; | |
3300 | struct kvm_arch *ka = &kvm->arch; | |
3301 | unsigned long seq, local_tsc_khz; | |
3302 | struct timespec64 ts; | |
3303 | uint64_t host_tsc; | |
3304 | ||
3305 | do { | |
3306 | seq = read_seqcount_begin(&ka->pvclock_sc); | |
3307 | ||
3308 | local_tsc_khz = 0; | |
3309 | if (!ka->use_master_clock) | |
3310 | break; | |
3311 | ||
3312 | /* | |
3313 | * The TSC read and the call to get_cpu_tsc_khz() must happen | |
3314 | * on the same CPU. | |
3315 | */ | |
3316 | get_cpu(); | |
3317 | ||
3318 | local_tsc_khz = get_cpu_tsc_khz(); | |
3319 | ||
3320 | if (local_tsc_khz && | |
3321 | !kvm_get_walltime_and_clockread(&ts, &host_tsc)) | |
3322 | local_tsc_khz = 0; /* Fall back to old method */ | |
3323 | ||
3324 | put_cpu(); | |
3325 | ||
3326 | /* | |
3327 | * These values must be snapshotted within the seqcount loop. | |
3328 | * After that, it's just mathematics which can happen on any | |
3329 | * CPU at any time. | |
3330 | */ | |
3331 | hv_clock.tsc_timestamp = ka->master_cycle_now; | |
3332 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
3333 | ||
3334 | } while (read_seqcount_retry(&ka->pvclock_sc, seq)); | |
3335 | ||
3336 | /* | |
3337 | * If the conditions were right, and obtaining the wallclock+TSC was | |
3338 | * successful, calculate the KVM clock at the corresponding time and | |
3339 | * subtract one from the other to get the guest's epoch in nanoseconds | |
3340 | * since 1970-01-01. | |
3341 | */ | |
3342 | if (local_tsc_khz) { | |
3343 | kvm_get_time_scale(NSEC_PER_SEC, local_tsc_khz * NSEC_PER_USEC, | |
3344 | &hv_clock.tsc_shift, | |
3345 | &hv_clock.tsc_to_system_mul); | |
3346 | return ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec - | |
3347 | __pvclock_read_cycles(&hv_clock, host_tsc); | |
3348 | } | |
3349 | #endif | |
3350 | return ktime_get_real_ns() - get_kvmclock_ns(kvm); | |
3351 | } | |
3352 | ||
0061d53d MT |
3353 | /* |
3354 | * kvmclock updates which are isolated to a given vcpu, such as | |
3355 | * vcpu->cpu migration, should not allow system_timestamp from | |
3356 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
3357 | * correction applies to one vcpu's system_timestamp but not | |
3358 | * the others. | |
3359 | * | |
3360 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
3361 | * We need to rate-limit these requests though, as they can |
3362 | * considerably slow guests that have a large number of vcpus. | |
3363 | * The time for a remote vcpu to update its kvmclock is bound | |
3364 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
3365 | */ |
3366 | ||
7e44e449 AJ |
3367 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
3368 | ||
3369 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d | 3370 | { |
46808a4c | 3371 | unsigned long i; |
7e44e449 AJ |
3372 | struct delayed_work *dwork = to_delayed_work(work); |
3373 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3374 | kvmclock_update_work); | |
3375 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
3376 | struct kvm_vcpu *vcpu; |
3377 | ||
3378 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 3379 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
3380 | kvm_vcpu_kick(vcpu); |
3381 | } | |
3382 | } | |
3383 | ||
7e44e449 AJ |
3384 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
3385 | { | |
3386 | struct kvm *kvm = v->kvm; | |
3387 | ||
105b21bb | 3388 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
3389 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
3390 | KVMCLOCK_UPDATE_DELAY); | |
3391 | } | |
3392 | ||
332967a3 AJ |
3393 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
3394 | ||
3395 | static void kvmclock_sync_fn(struct work_struct *work) | |
3396 | { | |
3397 | struct delayed_work *dwork = to_delayed_work(work); | |
3398 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3399 | kvmclock_sync_work); | |
3400 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
3401 | ||
3402 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); | |
3403 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
3404 | KVMCLOCK_SYNC_PERIOD); | |
3405 | } | |
3406 | ||
281b5278 JW |
3407 | /* These helpers are safe iff @msr is known to be an MCx bank MSR. */ |
3408 | static bool is_mci_control_msr(u32 msr) | |
3409 | { | |
3410 | return (msr & 3) == 0; | |
3411 | } | |
3412 | static bool is_mci_status_msr(u32 msr) | |
3413 | { | |
3414 | return (msr & 3) == 1; | |
3415 | } | |
3416 | ||
191c8137 BP |
3417 | /* |
3418 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
3419 | */ | |
3420 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
3421 | { | |
3422 | /* McStatusWrEn enabled? */ | |
23493d0a | 3423 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
3424 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
3425 | ||
3426 | return false; | |
3427 | } | |
3428 | ||
9ffd986c | 3429 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3430 | { |
890ca9ae HY |
3431 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3432 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
3433 | u32 msr = msr_info->index; |
3434 | u64 data = msr_info->data; | |
281b5278 | 3435 | u32 offset, last_msr; |
890ca9ae | 3436 | |
15c4a640 | 3437 | switch (msr) { |
15c4a640 | 3438 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 3439 | vcpu->arch.mcg_status = data; |
15c4a640 | 3440 | break; |
c7ac679c | 3441 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
3442 | if (!(mcg_cap & MCG_CTL_P) && |
3443 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
3444 | return 1; |
3445 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 3446 | return 1; |
890ca9ae HY |
3447 | vcpu->arch.mcg_ctl = data; |
3448 | break; | |
281b5278 JW |
3449 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
3450 | last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; | |
3451 | if (msr > last_msr) | |
3452 | return 1; | |
191c8137 | 3453 | |
281b5278 JW |
3454 | if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated)) |
3455 | return 1; | |
3456 | /* An attempt to write a 1 to a reserved bit raises #GP */ | |
3457 | if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK)) | |
3458 | return 1; | |
3459 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, | |
3460 | last_msr + 1 - MSR_IA32_MC0_CTL2); | |
3461 | vcpu->arch.mci_ctl2_banks[offset] = data; | |
3462 | break; | |
3463 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: | |
3464 | last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; | |
3465 | if (msr > last_msr) | |
3466 | return 1; | |
3467 | ||
3468 | /* | |
3469 | * Only 0 or all 1s can be written to IA32_MCi_CTL, all other | |
3470 | * values are architecturally undefined. But, some Linux | |
3471 | * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB | |
3472 | * issue on AMD K8s, allow bit 10 to be clear when setting all | |
3473 | * other bits in order to avoid an uncaught #GP in the guest. | |
f5223a33 SC |
3474 | * |
3475 | * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable, | |
3476 | * single-bit ECC data errors. | |
281b5278 JW |
3477 | */ |
3478 | if (is_mci_control_msr(msr) && | |
3479 | data != 0 && (data | (1 << 10) | 1) != ~(u64)0) | |
3480 | return 1; | |
191c8137 | 3481 | |
281b5278 JW |
3482 | /* |
3483 | * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR. | |
3484 | * AMD-based CPUs allow non-zero values, but if and only if | |
3485 | * HWCR[McStatusWrEn] is set. | |
3486 | */ | |
3487 | if (!msr_info->host_initiated && is_mci_status_msr(msr) && | |
3488 | data != 0 && !can_set_mci_status(vcpu)) | |
3489 | return 1; | |
3490 | ||
3491 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, | |
3492 | last_msr + 1 - MSR_IA32_MC0_CTL); | |
3493 | vcpu->arch.mce_banks[offset] = data; | |
3494 | break; | |
3495 | default: | |
890ca9ae HY |
3496 | return 1; |
3497 | } | |
3498 | return 0; | |
3499 | } | |
3500 | ||
2635b5c4 VK |
3501 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
3502 | { | |
3503 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
3504 | ||
3505 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
3506 | } | |
3507 | ||
344d9588 GN |
3508 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
3509 | { | |
3510 | gpa_t gpa = data & ~0x3f; | |
3511 | ||
2635b5c4 VK |
3512 | /* Bits 4:5 are reserved, Should be zero */ |
3513 | if (data & 0x30) | |
344d9588 GN |
3514 | return 1; |
3515 | ||
66570e96 OU |
3516 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
3517 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
3518 | return 1; | |
3519 | ||
3520 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
3521 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
3522 | return 1; | |
3523 | ||
9d3c447c | 3524 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 3525 | return data ? 1 : 0; |
9d3c447c | 3526 | |
2635b5c4 | 3527 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 3528 | |
2635b5c4 | 3529 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
3530 | kvm_clear_async_pf_completion_queue(vcpu); |
3531 | kvm_async_pf_hash_reset(vcpu); | |
3532 | return 0; | |
3533 | } | |
3534 | ||
4e335d9e | 3535 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 3536 | sizeof(u64))) |
344d9588 GN |
3537 | return 1; |
3538 | ||
6adba527 | 3539 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 3540 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 3541 | |
344d9588 | 3542 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
3543 | |
3544 | return 0; | |
3545 | } | |
3546 | ||
3547 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
3548 | { | |
3549 | /* Bits 8-63 are reserved */ | |
3550 | if (data >> 8) | |
3551 | return 1; | |
3552 | ||
3553 | if (!lapic_in_kernel(vcpu)) | |
3554 | return 1; | |
3555 | ||
3556 | vcpu->arch.apf.msr_int_val = data; | |
3557 | ||
3558 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
3559 | ||
344d9588 GN |
3560 | return 0; |
3561 | } | |
3562 | ||
12f9a48f GC |
3563 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
3564 | { | |
8c82a0b3 | 3565 | kvm_gpc_deactivate(&vcpu->arch.pv_time); |
49dedf0d | 3566 | vcpu->arch.time = 0; |
12f9a48f GC |
3567 | } |
3568 | ||
7780938c | 3569 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
3570 | { |
3571 | ++vcpu->stat.tlb_flush; | |
e27bc044 | 3572 | static_call(kvm_x86_flush_tlb_all)(vcpu); |
e94cea09 SC |
3573 | |
3574 | /* Flushing all ASIDs flushes the current ASID... */ | |
3575 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
f38a7b75 WL |
3576 | } |
3577 | ||
0baedd79 VK |
3578 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
3579 | { | |
3580 | ++vcpu->stat.tlb_flush; | |
b53e84ee LJ |
3581 | |
3582 | if (!tdp_enabled) { | |
61b05a9f | 3583 | /* |
b53e84ee LJ |
3584 | * A TLB flush on behalf of the guest is equivalent to |
3585 | * INVPCID(all), toggling CR4.PGE, etc., which requires | |
61b05a9f LJ |
3586 | * a forced sync of the shadow page tables. Ensure all the |
3587 | * roots are synced and the guest TLB in hardware is clean. | |
b53e84ee | 3588 | */ |
61b05a9f LJ |
3589 | kvm_mmu_sync_roots(vcpu); |
3590 | kvm_mmu_sync_prev_roots(vcpu); | |
b53e84ee LJ |
3591 | } |
3592 | ||
e27bc044 | 3593 | static_call(kvm_x86_flush_tlb_guest)(vcpu); |
adc43caa VK |
3594 | |
3595 | /* | |
3596 | * Flushing all "guest" TLB is always a superset of Hyper-V's fine | |
3597 | * grained flushing. | |
3598 | */ | |
0823570f | 3599 | kvm_hv_vcpu_purge_flush_tlb(vcpu); |
0baedd79 VK |
3600 | } |
3601 | ||
40e5f908 SC |
3602 | |
3603 | static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) | |
3604 | { | |
3605 | ++vcpu->stat.tlb_flush; | |
e27bc044 | 3606 | static_call(kvm_x86_flush_tlb_current)(vcpu); |
40e5f908 SC |
3607 | } |
3608 | ||
3609 | /* | |
3610 | * Service "local" TLB flush requests, which are specific to the current MMU | |
3611 | * context. In addition to the generic event handling in vcpu_enter_guest(), | |
3612 | * TLB flushes that are targeted at an MMU context also need to be serviced | |
3613 | * prior before nested VM-Enter/VM-Exit. | |
3614 | */ | |
3615 | void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) | |
3616 | { | |
3617 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
3618 | kvm_vcpu_flush_tlb_current(vcpu); | |
3619 | ||
3620 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) | |
3621 | kvm_vcpu_flush_tlb_guest(vcpu); | |
3622 | } | |
3623 | EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); | |
3624 | ||
c9aaa895 GC |
3625 | static void record_steal_time(struct kvm_vcpu *vcpu) |
3626 | { | |
7e2175eb DW |
3627 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
3628 | struct kvm_steal_time __user *st; | |
3629 | struct kvm_memslots *slots; | |
901d3765 | 3630 | gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; |
7e2175eb DW |
3631 | u64 steal; |
3632 | u32 version; | |
b0431382 | 3633 | |
30b5c851 DW |
3634 | if (kvm_xen_msr_enabled(vcpu->kvm)) { |
3635 | kvm_xen_runstate_set_running(vcpu); | |
3636 | return; | |
3637 | } | |
3638 | ||
c9aaa895 GC |
3639 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3640 | return; | |
3641 | ||
7e2175eb | 3642 | if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) |
c9aaa895 GC |
3643 | return; |
3644 | ||
7e2175eb DW |
3645 | slots = kvm_memslots(vcpu->kvm); |
3646 | ||
3647 | if (unlikely(slots->generation != ghc->generation || | |
901d3765 | 3648 | gpa != ghc->gpa || |
7e2175eb | 3649 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { |
7e2175eb DW |
3650 | /* We rely on the fact that it fits in a single page. */ |
3651 | BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); | |
3652 | ||
901d3765 | 3653 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) || |
7e2175eb DW |
3654 | kvm_is_error_hva(ghc->hva) || !ghc->memslot) |
3655 | return; | |
3656 | } | |
3657 | ||
3658 | st = (struct kvm_steal_time __user *)ghc->hva; | |
f38a7b75 WL |
3659 | /* |
3660 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3661 | * expensive IPIs. | |
3662 | */ | |
66570e96 | 3663 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
7e2175eb DW |
3664 | u8 st_preempted = 0; |
3665 | int err = -EFAULT; | |
3666 | ||
3e067fd8 PB |
3667 | if (!user_access_begin(st, sizeof(*st))) |
3668 | return; | |
3669 | ||
7e2175eb DW |
3670 | asm volatile("1: xchgb %0, %2\n" |
3671 | "xor %1, %1\n" | |
3672 | "2:\n" | |
3673 | _ASM_EXTABLE_UA(1b, 2b) | |
964b7aa0 DW |
3674 | : "+q" (st_preempted), |
3675 | "+&r" (err), | |
3676 | "+m" (st->preempted)); | |
7e2175eb DW |
3677 | if (err) |
3678 | goto out; | |
3679 | ||
3680 | user_access_end(); | |
3681 | ||
3682 | vcpu->arch.st.preempted = 0; | |
af3511ff | 3683 | |
66570e96 | 3684 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
af3511ff LJ |
3685 | st_preempted & KVM_VCPU_FLUSH_TLB); |
3686 | if (st_preempted & KVM_VCPU_FLUSH_TLB) | |
66570e96 | 3687 | kvm_vcpu_flush_tlb_guest(vcpu); |
7e2175eb DW |
3688 | |
3689 | if (!user_access_begin(st, sizeof(*st))) | |
3690 | goto dirty; | |
1eff0ada | 3691 | } else { |
3e067fd8 PB |
3692 | if (!user_access_begin(st, sizeof(*st))) |
3693 | return; | |
3694 | ||
7e2175eb DW |
3695 | unsafe_put_user(0, &st->preempted, out); |
3696 | vcpu->arch.st.preempted = 0; | |
66570e96 | 3697 | } |
0b9f6c46 | 3698 | |
7e2175eb DW |
3699 | unsafe_get_user(version, &st->version, out); |
3700 | if (version & 1) | |
3701 | version += 1; /* first time write, random junk */ | |
35f3fae1 | 3702 | |
7e2175eb DW |
3703 | version += 1; |
3704 | unsafe_put_user(version, &st->version, out); | |
35f3fae1 WL |
3705 | |
3706 | smp_wmb(); | |
3707 | ||
7e2175eb DW |
3708 | unsafe_get_user(steal, &st->steal, out); |
3709 | steal += current->sched_info.run_delay - | |
c54cdf14 LC |
3710 | vcpu->arch.st.last_steal; |
3711 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
7e2175eb | 3712 | unsafe_put_user(steal, &st->steal, out); |
35f3fae1 | 3713 | |
7e2175eb DW |
3714 | version += 1; |
3715 | unsafe_put_user(version, &st->version, out); | |
35f3fae1 | 3716 | |
7e2175eb DW |
3717 | out: |
3718 | user_access_end(); | |
3719 | dirty: | |
3720 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); | |
c9aaa895 GC |
3721 | } |
3722 | ||
2de154f5 SC |
3723 | static bool kvm_is_msr_to_save(u32 msr_index) |
3724 | { | |
3725 | unsigned int i; | |
3726 | ||
3727 | for (i = 0; i < num_msrs_to_save; i++) { | |
3728 | if (msrs_to_save[i] == msr_index) | |
3729 | return true; | |
3730 | } | |
3731 | ||
3732 | return false; | |
3733 | } | |
3734 | ||
8fe8ab46 | 3735 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3736 | { |
8fe8ab46 WA |
3737 | u32 msr = msr_info->index; |
3738 | u64 data = msr_info->data; | |
5753785f | 3739 | |
1232f8e6 | 3740 | if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) |
23200b7a | 3741 | return kvm_xen_write_hypercall_page(vcpu, data); |
1232f8e6 | 3742 | |
15c4a640 | 3743 | switch (msr) { |
2e32b719 | 3744 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3745 | case MSR_IA32_UCODE_WRITE: |
3746 | case MSR_VM_HSAVE_PA: | |
3747 | case MSR_AMD64_PATCH_LOADER: | |
3748 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3749 | case MSR_AMD64_DC_CFG: |
2770d472 | 3750 | case MSR_AMD64_TW_CFG: |
0e1b869f | 3751 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3752 | break; |
3753 | ||
518e7b94 WL |
3754 | case MSR_IA32_UCODE_REV: |
3755 | if (msr_info->host_initiated) | |
3756 | vcpu->arch.microcode_version = data; | |
3757 | break; | |
0cf9135b SC |
3758 | case MSR_IA32_ARCH_CAPABILITIES: |
3759 | if (!msr_info->host_initiated) | |
3760 | return 1; | |
3761 | vcpu->arch.arch_capabilities = data; | |
3762 | break; | |
686e0f03 | 3763 | case MSR_IA32_PERF_CAPABILITIES: |
d574c539 VK |
3764 | if (!msr_info->host_initiated) |
3765 | return 1; | |
686e0f03 | 3766 | if (data & ~kvm_caps.supported_perf_cap) |
d574c539 VK |
3767 | return 1; |
3768 | ||
3a6de51a SC |
3769 | /* |
3770 | * Note, this is not just a performance optimization! KVM | |
3771 | * disallows changing feature MSRs after the vCPU has run; PMU | |
3772 | * refresh will bug the VM if called after the vCPU has run. | |
3773 | */ | |
3774 | if (vcpu->arch.perf_capabilities == data) | |
3775 | break; | |
3776 | ||
d574c539 | 3777 | vcpu->arch.perf_capabilities = data; |
17a024a8 | 3778 | kvm_pmu_refresh(vcpu); |
3a6de51a | 3779 | break; |
e47d8608 JP |
3780 | case MSR_IA32_PRED_CMD: { |
3781 | u64 reserved_bits = ~(PRED_CMD_IBPB | PRED_CMD_SBPB); | |
3782 | ||
3783 | if (!msr_info->host_initiated) { | |
3784 | if ((!guest_has_pred_cmd_msr(vcpu))) | |
3785 | return 1; | |
3786 | ||
3787 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) && | |
3788 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB)) | |
3789 | reserved_bits |= PRED_CMD_IBPB; | |
3790 | ||
3791 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SBPB)) | |
3792 | reserved_bits |= PRED_CMD_SBPB; | |
3793 | } | |
903358c7 | 3794 | |
e47d8608 JP |
3795 | if (!boot_cpu_has(X86_FEATURE_IBPB)) |
3796 | reserved_bits |= PRED_CMD_IBPB; | |
3797 | ||
3798 | if (!boot_cpu_has(X86_FEATURE_SBPB)) | |
3799 | reserved_bits |= PRED_CMD_SBPB; | |
3800 | ||
3801 | if (data & reserved_bits) | |
903358c7 | 3802 | return 1; |
e47d8608 | 3803 | |
903358c7 SC |
3804 | if (!data) |
3805 | break; | |
3806 | ||
e47d8608 | 3807 | wrmsrl(MSR_IA32_PRED_CMD, data); |
903358c7 | 3808 | break; |
e47d8608 | 3809 | } |
da3db168 SC |
3810 | case MSR_IA32_FLUSH_CMD: |
3811 | if (!msr_info->host_initiated && | |
3812 | !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D)) | |
3813 | return 1; | |
3814 | ||
3815 | if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH)) | |
3816 | return 1; | |
3817 | if (!data) | |
3818 | break; | |
3819 | ||
3820 | wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); | |
3821 | break; | |
15c4a640 | 3822 | case MSR_EFER: |
11988499 | 3823 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3824 | case MSR_K7_HWCR: |
3825 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3826 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3827 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 | 3828 | |
8b0e00fb JM |
3829 | /* |
3830 | * Allow McStatusWrEn and TscFreqSel. (Linux guests from v3.2 | |
3831 | * through at least v6.6 whine if TscFreqSel is clear, | |
3832 | * depending on F/M/S. | |
3833 | */ | |
3834 | if (data & ~(BIT_ULL(18) | BIT_ULL(24))) { | |
e76ae527 | 3835 | kvm_pr_unimpl_wrmsr(vcpu, msr, data); |
8f1589d9 AP |
3836 | return 1; |
3837 | } | |
598a790f | 3838 | vcpu->arch.msr_hwcr = data; |
15c4a640 | 3839 | break; |
f7c6d140 AP |
3840 | case MSR_FAM10H_MMIO_CONF_BASE: |
3841 | if (data != 0) { | |
e76ae527 | 3842 | kvm_pr_unimpl_wrmsr(vcpu, msr, data); |
f7c6d140 AP |
3843 | return 1; |
3844 | } | |
15c4a640 | 3845 | break; |
34a83dea | 3846 | case MSR_IA32_CR_PAT: |
bc7fe2f0 SC |
3847 | if (!kvm_pat_valid(data)) |
3848 | return 1; | |
3849 | ||
3850 | vcpu->arch.pat = data; | |
3851 | break; | |
34a83dea SC |
3852 | case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000: |
3853 | case MSR_MTRRdefType: | |
ff53604b | 3854 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3855 | case MSR_IA32_APICBASE: |
58cb628d | 3856 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3857 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3858 | return kvm_x2apic_msr_write(vcpu, msr, data); |
09141ec0 | 3859 | case MSR_IA32_TSC_DEADLINE: |
a3e06bbe LJ |
3860 | kvm_set_lapic_tscdeadline_msr(vcpu, data); |
3861 | break; | |
ba904635 | 3862 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3863 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3864 | if (!msr_info->host_initiated) { |
d913b904 | 3865 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3866 | adjust_tsc_offset_guest(vcpu, adj); |
d9130a2d ZD |
3867 | /* Before back to guest, tsc_timestamp must be adjusted |
3868 | * as well, otherwise guest's percpu pvclock time could jump. | |
3869 | */ | |
3870 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
ba904635 WA |
3871 | } |
3872 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3873 | } | |
3874 | break; | |
bef6ecca LX |
3875 | case MSR_IA32_MISC_ENABLE: { |
3876 | u64 old_val = vcpu->arch.ia32_misc_enable_msr; | |
d1055173 | 3877 | |
9fc22296 SC |
3878 | if (!msr_info->host_initiated) { |
3879 | /* RO bits */ | |
3880 | if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK) | |
3881 | return 1; | |
3882 | ||
3883 | /* R bits, i.e. writes are ignored, but don't fault. */ | |
3884 | data = data & ~MSR_IA32_MISC_ENABLE_EMON; | |
3885 | data |= old_val & MSR_IA32_MISC_ENABLE_EMON; | |
3886 | } | |
bef6ecca | 3887 | |
511a8556 | 3888 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
bef6ecca | 3889 | ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { |
511a8556 WL |
3890 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) |
3891 | return 1; | |
3892 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3893 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3894 | } else { |
3895 | vcpu->arch.ia32_misc_enable_msr = data; | |
3896 | } | |
15c4a640 | 3897 | break; |
bef6ecca | 3898 | } |
64d60670 | 3899 | case MSR_IA32_SMBASE: |
4b8e1b32 | 3900 | if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) |
64d60670 PB |
3901 | return 1; |
3902 | vcpu->arch.smbase = data; | |
3903 | break; | |
73f624f4 PB |
3904 | case MSR_IA32_POWER_CTL: |
3905 | vcpu->arch.msr_ia32_power_ctl = data; | |
3906 | break; | |
dd259935 | 3907 | case MSR_IA32_TSC: |
0c899c25 | 3908 | if (msr_info->host_initiated) { |
bf328e22 | 3909 | kvm_synchronize_tsc(vcpu, &data); |
0c899c25 | 3910 | } else { |
9b399dfd | 3911 | u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; |
0c899c25 PB |
3912 | adjust_tsc_offset_guest(vcpu, adj); |
3913 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3914 | } | |
dd259935 | 3915 | break; |
864e2ab2 AL |
3916 | case MSR_IA32_XSS: |
3917 | if (!msr_info->host_initiated && | |
3918 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3919 | return 1; | |
3920 | /* | |
a1bead2a SC |
3921 | * KVM supports exposing PT to the guest, but does not support |
3922 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3923 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3924 | */ |
938c8745 | 3925 | if (data & ~kvm_caps.supported_xss) |
864e2ab2 AL |
3926 | return 1; |
3927 | vcpu->arch.ia32_xss = data; | |
4c282e51 | 3928 | kvm_update_cpuid_runtime(vcpu); |
864e2ab2 | 3929 | break; |
52797bf9 LA |
3930 | case MSR_SMI_COUNT: |
3931 | if (!msr_info->host_initiated) | |
3932 | return 1; | |
3933 | vcpu->arch.smi_count = data; | |
3934 | break; | |
11c6bffa | 3935 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3936 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3937 | return 1; | |
3938 | ||
629b5348 JM |
3939 | vcpu->kvm->arch.wall_clock = data; |
3940 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
66570e96 | 3941 | break; |
18068523 | 3942 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3943 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3944 | return 1; | |
3945 | ||
629b5348 JM |
3946 | vcpu->kvm->arch.wall_clock = data; |
3947 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
18068523 | 3948 | break; |
11c6bffa | 3949 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3950 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3951 | return 1; | |
3952 | ||
5b9bb0eb OU |
3953 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3954 | break; | |
3955 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3956 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3957 | return 1; | |
3958 | ||
3959 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3960 | break; |
344d9588 | 3961 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3962 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3963 | return 1; | |
3964 | ||
344d9588 GN |
3965 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3966 | return 1; | |
3967 | break; | |
2635b5c4 | 3968 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3969 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3970 | return 1; | |
3971 | ||
2635b5c4 VK |
3972 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3973 | return 1; | |
3974 | break; | |
557a961a | 3975 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3976 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
66570e96 | 3977 | return 1; |
557a961a VK |
3978 | if (data & 0x1) { |
3979 | vcpu->arch.apf.pageready_pending = false; | |
3980 | kvm_check_async_pf_completion(vcpu); | |
3981 | } | |
3982 | break; | |
c9aaa895 | 3983 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3984 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3985 | return 1; | |
c9aaa895 GC |
3986 | |
3987 | if (unlikely(!sched_info_on())) | |
3988 | return 1; | |
3989 | ||
3990 | if (data & KVM_STEAL_RESERVED_MASK) | |
3991 | return 1; | |
3992 | ||
c9aaa895 GC |
3993 | vcpu->arch.st.msr_val = data; |
3994 | ||
3995 | if (!(data & KVM_MSR_ENABLED)) | |
3996 | break; | |
3997 | ||
c9aaa895 GC |
3998 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3999 | ||
4000 | break; | |
ae7a2a3f | 4001 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
4002 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
4003 | return 1; | |
4004 | ||
77c3323f | 4005 | if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
4006 | return 1; |
4007 | break; | |
c9aaa895 | 4008 | |
2d5ba19b | 4009 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
4010 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
4011 | return 1; | |
4012 | ||
2d5ba19b MT |
4013 | /* only enable bit supported */ |
4014 | if (data & (-1ULL << 1)) | |
4015 | return 1; | |
4016 | ||
4017 | vcpu->arch.msr_kvm_poll_control = data; | |
4018 | break; | |
4019 | ||
890ca9ae HY |
4020 | case MSR_IA32_MCG_CTL: |
4021 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 4022 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
281b5278 | 4023 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 4024 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 4025 | |
6912ac32 WH |
4026 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
4027 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
6912ac32 WH |
4028 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
4029 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 4030 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 4031 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f | 4032 | |
e76ae527 SC |
4033 | if (data) |
4034 | kvm_pr_unimpl_wrmsr(vcpu, msr, data); | |
5753785f | 4035 | break; |
84e0cefa JS |
4036 | case MSR_K7_CLK_CTL: |
4037 | /* | |
4038 | * Ignore all writes to this no longer documented MSR. | |
4039 | * Writes are only relevant for old K7 processors, | |
4040 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 4041 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
4042 | * affected processor models on the command line, hence |
4043 | * the need to ignore the workaround. | |
4044 | */ | |
4045 | break; | |
b4f69df0 | 4046 | #ifdef CONFIG_KVM_HYPERV |
55cd8e5a | 4047 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
4048 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
4049 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
4050 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
4051 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 4052 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
4053 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
4054 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
4055 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
2be1bd3a | 4056 | case HV_X64_MSR_TSC_INVARIANT_CONTROL: |
e7d9513b AS |
4057 | return kvm_hv_set_msr_common(vcpu, msr, data, |
4058 | msr_info->host_initiated); | |
b4f69df0 | 4059 | #endif |
91c9c3ed | 4060 | case MSR_IA32_BBL_CR_CTL3: |
4061 | /* Drop writes to this legacy MSR -- see rdmsr | |
4062 | * counterpart for further detail. | |
4063 | */ | |
e76ae527 | 4064 | kvm_pr_unimpl_wrmsr(vcpu, msr, data); |
91c9c3ed | 4065 | break; |
2b036c6b | 4066 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 4067 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
4068 | return 1; |
4069 | vcpu->arch.osvw.length = data; | |
4070 | break; | |
4071 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 4072 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
4073 | return 1; |
4074 | vcpu->arch.osvw.status = data; | |
4075 | break; | |
db2336a8 KH |
4076 | case MSR_PLATFORM_INFO: |
4077 | if (!msr_info->host_initiated || | |
db2336a8 KH |
4078 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
4079 | cpuid_fault_enabled(vcpu))) | |
4080 | return 1; | |
4081 | vcpu->arch.msr_platform_info = data; | |
4082 | break; | |
4083 | case MSR_MISC_FEATURES_ENABLES: | |
4084 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
4085 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
4086 | !supports_cpuid_fault(vcpu))) | |
4087 | return 1; | |
4088 | vcpu->arch.msr_misc_features_enables = data; | |
4089 | break; | |
820a6ee9 JL |
4090 | #ifdef CONFIG_X86_64 |
4091 | case MSR_IA32_XFD: | |
4092 | if (!msr_info->host_initiated && | |
4093 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
4094 | return 1; | |
4095 | ||
988896bb | 4096 | if (data & ~kvm_guest_supported_xfd(vcpu)) |
820a6ee9 JL |
4097 | return 1; |
4098 | ||
4099 | fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); | |
4100 | break; | |
548e8365 JL |
4101 | case MSR_IA32_XFD_ERR: |
4102 | if (!msr_info->host_initiated && | |
4103 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
4104 | return 1; | |
4105 | ||
988896bb | 4106 | if (data & ~kvm_guest_supported_xfd(vcpu)) |
548e8365 JL |
4107 | return 1; |
4108 | ||
4109 | vcpu->arch.guest_fpu.xfd_err = data; | |
4110 | break; | |
820a6ee9 | 4111 | #endif |
2de154f5 | 4112 | default: |
157fc497 SC |
4113 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
4114 | return kvm_pmu_set_msr(vcpu, msr_info); | |
2de154f5 | 4115 | |
157fc497 SC |
4116 | /* |
4117 | * Userspace is allowed to write '0' to MSRs that KVM reports | |
4118 | * as to-be-saved, even if an MSRs isn't fully supported. | |
4119 | */ | |
2de154f5 SC |
4120 | if (msr_info->host_initiated && !data && |
4121 | kvm_is_msr_to_save(msr)) | |
4122 | break; | |
4123 | ||
6abe9c13 | 4124 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
4125 | } |
4126 | return 0; | |
4127 | } | |
4128 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
4129 | ||
44883f01 | 4130 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
4131 | { |
4132 | u64 data; | |
890ca9ae HY |
4133 | u64 mcg_cap = vcpu->arch.mcg_cap; |
4134 | unsigned bank_num = mcg_cap & 0xff; | |
281b5278 | 4135 | u32 offset, last_msr; |
15c4a640 CO |
4136 | |
4137 | switch (msr) { | |
15c4a640 CO |
4138 | case MSR_IA32_P5_MC_ADDR: |
4139 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
4140 | data = 0; |
4141 | break; | |
15c4a640 | 4142 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
4143 | data = vcpu->arch.mcg_cap; |
4144 | break; | |
c7ac679c | 4145 | case MSR_IA32_MCG_CTL: |
44883f01 | 4146 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
4147 | return 1; |
4148 | data = vcpu->arch.mcg_ctl; | |
4149 | break; | |
4150 | case MSR_IA32_MCG_STATUS: | |
4151 | data = vcpu->arch.mcg_status; | |
4152 | break; | |
281b5278 JW |
4153 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
4154 | last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; | |
4155 | if (msr > last_msr) | |
4156 | return 1; | |
6ec4c5ee | 4157 | |
281b5278 JW |
4158 | if (!(mcg_cap & MCG_CMCI_P) && !host) |
4159 | return 1; | |
4160 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, | |
4161 | last_msr + 1 - MSR_IA32_MC0_CTL2); | |
4162 | data = vcpu->arch.mci_ctl2_banks[offset]; | |
4163 | break; | |
4164 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: | |
4165 | last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; | |
4166 | if (msr > last_msr) | |
4167 | return 1; | |
4168 | ||
4169 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, | |
4170 | last_msr + 1 - MSR_IA32_MC0_CTL); | |
4171 | data = vcpu->arch.mce_banks[offset]; | |
4172 | break; | |
4173 | default: | |
890ca9ae HY |
4174 | return 1; |
4175 | } | |
4176 | *pdata = data; | |
4177 | return 0; | |
4178 | } | |
4179 | ||
609e36d3 | 4180 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 4181 | { |
609e36d3 | 4182 | switch (msr_info->index) { |
890ca9ae | 4183 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 4184 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
4185 | case MSR_IA32_LASTBRANCHFROMIP: |
4186 | case MSR_IA32_LASTBRANCHTOIP: | |
4187 | case MSR_IA32_LASTINTFROMIP: | |
4188 | case MSR_IA32_LASTINTTOIP: | |
059e5c32 | 4189 | case MSR_AMD64_SYSCFG: |
3afb1121 PB |
4190 | case MSR_K8_TSEG_ADDR: |
4191 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 4192 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 4193 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 4194 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 4195 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 4196 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 4197 | case MSR_IA32_PERF_CTL: |
405a353a | 4198 | case MSR_AMD64_DC_CFG: |
2770d472 | 4199 | case MSR_AMD64_TW_CFG: |
0e1b869f | 4200 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
4201 | /* |
4202 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
4203 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
4204 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
4205 | * so for existing CPU-specific MSRs. | |
4206 | */ | |
4207 | case MSR_RAPL_POWER_UNIT: | |
4208 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
4209 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
4210 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
4211 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 4212 | msr_info->data = 0; |
15c4a640 | 4213 | break; |
6912ac32 WH |
4214 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
4215 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
4216 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
4217 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 4218 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 4219 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 4220 | msr_info->data = 0; |
5753785f | 4221 | break; |
742bc670 | 4222 | case MSR_IA32_UCODE_REV: |
518e7b94 | 4223 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 4224 | break; |
0cf9135b SC |
4225 | case MSR_IA32_ARCH_CAPABILITIES: |
4226 | if (!msr_info->host_initiated && | |
4227 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
4228 | return 1; | |
4229 | msr_info->data = vcpu->arch.arch_capabilities; | |
4230 | break; | |
d574c539 VK |
4231 | case MSR_IA32_PERF_CAPABILITIES: |
4232 | if (!msr_info->host_initiated && | |
4233 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
4234 | return 1; | |
4235 | msr_info->data = vcpu->arch.perf_capabilities; | |
4236 | break; | |
73f624f4 PB |
4237 | case MSR_IA32_POWER_CTL: |
4238 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
4239 | break; | |
cc5b54dd ML |
4240 | case MSR_IA32_TSC: { |
4241 | /* | |
4242 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
4243 | * even when not intercepted. AMD manual doesn't explicitly | |
4244 | * state this but appears to behave the same. | |
4245 | * | |
ee6fa053 | 4246 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 4247 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 4248 | * behavior for migration. |
cc5b54dd | 4249 | */ |
fe3eb504 | 4250 | u64 offset, ratio; |
cc5b54dd | 4251 | |
fe3eb504 IS |
4252 | if (msr_info->host_initiated) { |
4253 | offset = vcpu->arch.l1_tsc_offset; | |
4254 | ratio = vcpu->arch.l1_tsc_scaling_ratio; | |
4255 | } else { | |
4256 | offset = vcpu->arch.tsc_offset; | |
4257 | ratio = vcpu->arch.tsc_scaling_ratio; | |
4258 | } | |
4259 | ||
62711e5a | 4260 | msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset; |
dd259935 | 4261 | break; |
cc5b54dd | 4262 | } |
34a83dea | 4263 | case MSR_IA32_CR_PAT: |
bc7fe2f0 SC |
4264 | msr_info->data = vcpu->arch.pat; |
4265 | break; | |
9ba075a6 | 4266 | case MSR_MTRRcap: |
34a83dea SC |
4267 | case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000: |
4268 | case MSR_MTRRdefType: | |
ff53604b | 4269 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 4270 | case 0xcd: /* fsb frequency */ |
609e36d3 | 4271 | msr_info->data = 3; |
15c4a640 | 4272 | break; |
7b914098 JS |
4273 | /* |
4274 | * MSR_EBC_FREQUENCY_ID | |
4275 | * Conservative value valid for even the basic CPU models. | |
4276 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
4277 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
4278 | * and 266MHz for model 3, or 4. Set Core Clock | |
4279 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
4280 | * 31:24) even though these are only valid for CPU | |
4281 | * models > 2, however guests may end up dividing or | |
4282 | * multiplying by zero otherwise. | |
4283 | */ | |
4284 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 4285 | msr_info->data = 1 << 24; |
7b914098 | 4286 | break; |
15c4a640 | 4287 | case MSR_IA32_APICBASE: |
609e36d3 | 4288 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 4289 | break; |
bf10bd0b | 4290 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 4291 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
09141ec0 | 4292 | case MSR_IA32_TSC_DEADLINE: |
609e36d3 | 4293 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 4294 | break; |
ba904635 | 4295 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 4296 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 4297 | break; |
15c4a640 | 4298 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 4299 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 4300 | break; |
64d60670 | 4301 | case MSR_IA32_SMBASE: |
4b8e1b32 | 4302 | if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) |
64d60670 PB |
4303 | return 1; |
4304 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 4305 | break; |
52797bf9 LA |
4306 | case MSR_SMI_COUNT: |
4307 | msr_info->data = vcpu->arch.smi_count; | |
4308 | break; | |
847f0ad8 AG |
4309 | case MSR_IA32_PERF_STATUS: |
4310 | /* TSC increment by tick */ | |
609e36d3 | 4311 | msr_info->data = 1000ULL; |
847f0ad8 | 4312 | /* CPU multiplier */ |
b0996ae4 | 4313 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 4314 | break; |
15c4a640 | 4315 | case MSR_EFER: |
609e36d3 | 4316 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 4317 | break; |
18068523 | 4318 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
4319 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
4320 | return 1; | |
4321 | ||
4322 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
4323 | break; | |
11c6bffa | 4324 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
4325 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
4326 | return 1; | |
4327 | ||
609e36d3 | 4328 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
4329 | break; |
4330 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
4331 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
4332 | return 1; | |
4333 | ||
4334 | msr_info->data = vcpu->arch.time; | |
4335 | break; | |
11c6bffa | 4336 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
4337 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
4338 | return 1; | |
4339 | ||
609e36d3 | 4340 | msr_info->data = vcpu->arch.time; |
18068523 | 4341 | break; |
344d9588 | 4342 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
4343 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
4344 | return 1; | |
4345 | ||
2635b5c4 VK |
4346 | msr_info->data = vcpu->arch.apf.msr_en_val; |
4347 | break; | |
4348 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
4349 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
4350 | return 1; | |
4351 | ||
2635b5c4 | 4352 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 4353 | break; |
557a961a | 4354 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 4355 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
1930e5dd OU |
4356 | return 1; |
4357 | ||
557a961a VK |
4358 | msr_info->data = 0; |
4359 | break; | |
c9aaa895 | 4360 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
4361 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
4362 | return 1; | |
4363 | ||
609e36d3 | 4364 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 4365 | break; |
1d92128f | 4366 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
4367 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
4368 | return 1; | |
4369 | ||
609e36d3 | 4370 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 4371 | break; |
2d5ba19b | 4372 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
4373 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
4374 | return 1; | |
4375 | ||
2d5ba19b MT |
4376 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
4377 | break; | |
890ca9ae HY |
4378 | case MSR_IA32_P5_MC_ADDR: |
4379 | case MSR_IA32_P5_MC_TYPE: | |
4380 | case MSR_IA32_MCG_CAP: | |
4381 | case MSR_IA32_MCG_CTL: | |
4382 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 4383 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
281b5278 | 4384 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
4385 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
4386 | msr_info->host_initiated); | |
864e2ab2 AL |
4387 | case MSR_IA32_XSS: |
4388 | if (!msr_info->host_initiated && | |
4389 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
4390 | return 1; | |
4391 | msr_info->data = vcpu->arch.ia32_xss; | |
4392 | break; | |
84e0cefa JS |
4393 | case MSR_K7_CLK_CTL: |
4394 | /* | |
4395 | * Provide expected ramp-up count for K7. All other | |
4396 | * are set to zero, indicating minimum divisors for | |
4397 | * every field. | |
4398 | * | |
4399 | * This prevents guest kernels on AMD host with CPU | |
4400 | * type 6, model 8 and higher from exploding due to | |
4401 | * the rdmsr failing. | |
4402 | */ | |
609e36d3 | 4403 | msr_info->data = 0x20000000; |
84e0cefa | 4404 | break; |
b4f69df0 | 4405 | #ifdef CONFIG_KVM_HYPERV |
55cd8e5a | 4406 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
4407 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
4408 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
4409 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
4410 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 4411 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
4412 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
4413 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
4414 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
2be1bd3a | 4415 | case HV_X64_MSR_TSC_INVARIANT_CONTROL: |
e83d5887 | 4416 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
4417 | msr_info->index, &msr_info->data, |
4418 | msr_info->host_initiated); | |
b4f69df0 | 4419 | #endif |
91c9c3ed | 4420 | case MSR_IA32_BBL_CR_CTL3: |
4421 | /* This legacy MSR exists but isn't fully documented in current | |
4422 | * silicon. It is however accessed by winxp in very narrow | |
4423 | * scenarios where it sets bit #19, itself documented as | |
4424 | * a "reserved" bit. Best effort attempt to source coherent | |
4425 | * read data here should the balance of the register be | |
4426 | * interpreted by the guest: | |
4427 | * | |
4428 | * L2 cache control register 3: 64GB range, 256KB size, | |
4429 | * enabled, latency 0x1, configured | |
4430 | */ | |
609e36d3 | 4431 | msr_info->data = 0xbe702111; |
91c9c3ed | 4432 | break; |
2b036c6b | 4433 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 4434 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 4435 | return 1; |
609e36d3 | 4436 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
4437 | break; |
4438 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 4439 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 4440 | return 1; |
609e36d3 | 4441 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 4442 | break; |
db2336a8 | 4443 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
4444 | if (!msr_info->host_initiated && |
4445 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
4446 | return 1; | |
db2336a8 KH |
4447 | msr_info->data = vcpu->arch.msr_platform_info; |
4448 | break; | |
4449 | case MSR_MISC_FEATURES_ENABLES: | |
4450 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
4451 | break; | |
191c8137 BP |
4452 | case MSR_K7_HWCR: |
4453 | msr_info->data = vcpu->arch.msr_hwcr; | |
4454 | break; | |
820a6ee9 JL |
4455 | #ifdef CONFIG_X86_64 |
4456 | case MSR_IA32_XFD: | |
4457 | if (!msr_info->host_initiated && | |
4458 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
4459 | return 1; | |
4460 | ||
4461 | msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; | |
4462 | break; | |
548e8365 JL |
4463 | case MSR_IA32_XFD_ERR: |
4464 | if (!msr_info->host_initiated && | |
4465 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
4466 | return 1; | |
4467 | ||
4468 | msr_info->data = vcpu->arch.guest_fpu.xfd_err; | |
4469 | break; | |
820a6ee9 | 4470 | #endif |
15c4a640 | 4471 | default: |
c6702c9d | 4472 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 4473 | return kvm_pmu_get_msr(vcpu, msr_info); |
2de154f5 SC |
4474 | |
4475 | /* | |
4476 | * Userspace is allowed to read MSRs that KVM reports as | |
4477 | * to-be-saved, even if an MSR isn't fully supported. | |
4478 | */ | |
4479 | if (msr_info->host_initiated && | |
4480 | kvm_is_msr_to_save(msr_info->index)) { | |
4481 | msr_info->data = 0; | |
4482 | break; | |
4483 | } | |
4484 | ||
6abe9c13 | 4485 | return KVM_MSR_RET_INVALID; |
15c4a640 | 4486 | } |
15c4a640 CO |
4487 | return 0; |
4488 | } | |
4489 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
4490 | ||
313a3dc7 CO |
4491 | /* |
4492 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
4493 | * | |
4494 | * @return number of msrs set successfully. | |
4495 | */ | |
4496 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
4497 | struct kvm_msr_entry *entries, | |
4498 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
4499 | unsigned index, u64 *data)) | |
4500 | { | |
801e459a | 4501 | int i; |
313a3dc7 | 4502 | |
313a3dc7 CO |
4503 | for (i = 0; i < msrs->nmsrs; ++i) |
4504 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
4505 | break; | |
4506 | ||
313a3dc7 CO |
4507 | return i; |
4508 | } | |
4509 | ||
4510 | /* | |
4511 | * Read or write a bunch of msrs. Parameters are user addresses. | |
4512 | * | |
4513 | * @return number of msrs set successfully. | |
4514 | */ | |
4515 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
4516 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
4517 | unsigned index, u64 *data), | |
4518 | int writeback) | |
4519 | { | |
4520 | struct kvm_msrs msrs; | |
4521 | struct kvm_msr_entry *entries; | |
313a3dc7 | 4522 | unsigned size; |
e73ba25f | 4523 | int r; |
313a3dc7 CO |
4524 | |
4525 | r = -EFAULT; | |
0e96f31e | 4526 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
4527 | goto out; |
4528 | ||
4529 | r = -E2BIG; | |
4530 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
4531 | goto out; | |
4532 | ||
313a3dc7 | 4533 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
4534 | entries = memdup_user(user_msrs->entries, size); |
4535 | if (IS_ERR(entries)) { | |
4536 | r = PTR_ERR(entries); | |
313a3dc7 | 4537 | goto out; |
ff5c2c03 | 4538 | } |
313a3dc7 | 4539 | |
e73ba25f | 4540 | r = __msr_io(vcpu, &msrs, entries, do_msr); |
313a3dc7 | 4541 | |
313a3dc7 | 4542 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) |
e73ba25f | 4543 | r = -EFAULT; |
313a3dc7 | 4544 | |
7a73c028 | 4545 | kfree(entries); |
313a3dc7 CO |
4546 | out: |
4547 | return r; | |
4548 | } | |
4549 | ||
4d5422ce WL |
4550 | static inline bool kvm_can_mwait_in_guest(void) |
4551 | { | |
4552 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
4553 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
4554 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
4555 | } |
4556 | ||
b4f69df0 | 4557 | #ifdef CONFIG_KVM_HYPERV |
c21d54f0 VK |
4558 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
4559 | struct kvm_cpuid2 __user *cpuid_arg) | |
4560 | { | |
4561 | struct kvm_cpuid2 cpuid; | |
4562 | int r; | |
4563 | ||
4564 | r = -EFAULT; | |
4565 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4566 | return r; | |
4567 | ||
4568 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
4569 | if (r) | |
4570 | return r; | |
4571 | ||
4572 | r = -EFAULT; | |
4573 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4574 | return r; | |
4575 | ||
4576 | return 0; | |
4577 | } | |
b4f69df0 | 4578 | #endif |
c21d54f0 | 4579 | |
89ea60c2 SC |
4580 | static bool kvm_is_vm_type_supported(unsigned long type) |
4581 | { | |
4582 | return type == KVM_X86_DEFAULT_VM || | |
4583 | (type == KVM_X86_SW_PROTECTED_VM && | |
4584 | IS_ENABLED(CONFIG_KVM_SW_PROTECTED_VM) && tdp_enabled); | |
4585 | } | |
c21d54f0 | 4586 | |
784aa3d7 | 4587 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 4588 | { |
4d5422ce | 4589 | int r = 0; |
018d00d2 ZX |
4590 | |
4591 | switch (ext) { | |
4592 | case KVM_CAP_IRQCHIP: | |
4593 | case KVM_CAP_HLT: | |
4594 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 4595 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 4596 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 4597 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 4598 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 4599 | case KVM_CAP_PIT: |
a28e4f5a | 4600 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 4601 | case KVM_CAP_MP_STATE: |
ed848624 | 4602 | case KVM_CAP_SYNC_MMU: |
a355c85c | 4603 | case KVM_CAP_USER_NMI: |
52d939a0 | 4604 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 4605 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 4606 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 4607 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 4608 | case KVM_CAP_PIT2: |
e9f42757 | 4609 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 4610 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
3cfc3092 | 4611 | case KVM_CAP_VCPU_EVENTS: |
b4f69df0 | 4612 | #ifdef CONFIG_KVM_HYPERV |
55cd8e5a | 4613 | case KVM_CAP_HYPERV: |
10388a07 | 4614 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 4615 | case KVM_CAP_HYPERV_SPIN: |
b4f69df0 | 4616 | case KVM_CAP_HYPERV_TIME: |
5c919412 | 4617 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 4618 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 4619 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 4620 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 4621 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 4622 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 4623 | case KVM_CAP_HYPERV_CPUID: |
644f7067 | 4624 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
c21d54f0 | 4625 | case KVM_CAP_SYS_HYPERV_CPUID: |
b4f69df0 | 4626 | #endif |
ab9f4ecb | 4627 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 4628 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 4629 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 4630 | case KVM_CAP_XSAVE: |
344d9588 | 4631 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 4632 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 4633 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 4634 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 4635 | case KVM_CAP_READONLY_MEM: |
100943c5 | 4636 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 4637 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 4638 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 4639 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 4640 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 4641 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 4642 | case KVM_CAP_PMU_EVENT_FILTER: |
14329b82 | 4643 | case KVM_CAP_PMU_EVENT_MASKED_EVENTS: |
801e459a | 4644 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 4645 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 4646 | case KVM_CAP_EXCEPTION_PAYLOAD: |
ed235117 | 4647 | case KVM_CAP_X86_TRIPLE_FAULT_EVENT: |
b9b2782c | 4648 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 4649 | case KVM_CAP_LAST_CPU: |
1ae09954 | 4650 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 4651 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 4652 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
fe7e9488 SC |
4653 | #ifdef CONFIG_X86_SGX_KVM |
4654 | case KVM_CAP_SGX_ATTRIBUTE: | |
4655 | #endif | |
54526d1f | 4656 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
30d7c5d6 | 4657 | case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: |
6dba9403 | 4658 | case KVM_CAP_SREGS2: |
19238e75 | 4659 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
828ca896 | 4660 | case KVM_CAP_VCPU_ATTRIBUTES: |
dd6e6312 | 4661 | case KVM_CAP_SYS_ATTRIBUTES: |
8a289785 | 4662 | case KVM_CAP_VAPIC: |
127770ac | 4663 | case KVM_CAP_ENABLE_CAP: |
084cc29f | 4664 | case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: |
52882b9c | 4665 | case KVM_CAP_IRQFD_RESAMPLE: |
16f95f3b | 4666 | case KVM_CAP_MEMORY_FAULT_INFO: |
018d00d2 ZX |
4667 | r = 1; |
4668 | break; | |
0dbb1123 AK |
4669 | case KVM_CAP_EXIT_HYPERCALL: |
4670 | r = KVM_EXIT_HYPERCALL_VALID_MASK; | |
4671 | break; | |
7e582ccb ML |
4672 | case KVM_CAP_SET_GUEST_DEBUG2: |
4673 | return KVM_GUESTDBG_VALID_MASK; | |
b59b153d | 4674 | #ifdef CONFIG_KVM_XEN |
23200b7a JM |
4675 | case KVM_CAP_XEN_HVM: |
4676 | r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | | |
8d4e7e80 | 4677 | KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | |
14243b38 | 4678 | KVM_XEN_HVM_CONFIG_SHARED_INFO | |
661a20fa | 4679 | KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL | |
6d722835 PD |
4680 | KVM_XEN_HVM_CONFIG_EVTCHN_SEND | |
4681 | KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE; | |
30b5c851 | 4682 | if (sched_info_on()) |
d8ba8ba4 DW |
4683 | r |= KVM_XEN_HVM_CONFIG_RUNSTATE | |
4684 | KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG; | |
23200b7a | 4685 | break; |
b59b153d | 4686 | #endif |
01643c51 KH |
4687 | case KVM_CAP_SYNC_REGS: |
4688 | r = KVM_SYNC_X86_VALID_FIELDS; | |
4689 | break; | |
e3fd9a93 | 4690 | case KVM_CAP_ADJUST_CLOCK: |
c68dc1b5 | 4691 | r = KVM_CLOCK_VALID_FLAGS; |
e3fd9a93 | 4692 | break; |
4d5422ce | 4693 | case KVM_CAP_X86_DISABLE_EXITS: |
6f0f2d5e TL |
4694 | r = KVM_X86_DISABLE_EXITS_PAUSE; |
4695 | ||
4696 | if (!mitigate_smt_rsb) { | |
4697 | r |= KVM_X86_DISABLE_EXITS_HLT | | |
4698 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4699 | ||
4700 | if (kvm_can_mwait_in_guest()) | |
4701 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
4702 | } | |
668fffa3 | 4703 | break; |
6d396b55 | 4704 | case KVM_CAP_X86_SMM: |
4b8e1b32 PB |
4705 | if (!IS_ENABLED(CONFIG_KVM_SMM)) |
4706 | break; | |
4707 | ||
6d396b55 PB |
4708 | /* SMBASE is usually relocated above 1M on modern chipsets, |
4709 | * and SMM handlers might indeed rely on 4G segment limits, | |
4710 | * so do not report SMM to be available if real mode is | |
4711 | * emulated via vm86 mode. Still, do not go to great lengths | |
4712 | * to avoid userspace's usage of the feature, because it is a | |
4713 | * fringe case that is not enabled except via specific settings | |
4714 | * of the module parameters. | |
4715 | */ | |
b3646477 | 4716 | r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); |
6d396b55 | 4717 | break; |
f725230a | 4718 | case KVM_CAP_NR_VCPUS: |
2845e735 | 4719 | r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); |
8c3ba334 SL |
4720 | break; |
4721 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
4722 | r = KVM_MAX_VCPUS; |
4723 | break; | |
a86cb413 | 4724 | case KVM_CAP_MAX_VCPU_ID: |
a1c42dde | 4725 | r = KVM_MAX_VCPU_IDS; |
a86cb413 | 4726 | break; |
a68a6a72 MT |
4727 | case KVM_CAP_PV_MMU: /* obsolete */ |
4728 | r = 0; | |
2f333bcb | 4729 | break; |
890ca9ae HY |
4730 | case KVM_CAP_MCE: |
4731 | r = KVM_MAX_MCE_BANKS; | |
4732 | break; | |
2d5b5a66 | 4733 | case KVM_CAP_XCRS: |
d366bf7e | 4734 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 4735 | break; |
92a1f12d | 4736 | case KVM_CAP_TSC_CONTROL: |
ffbb61d0 | 4737 | case KVM_CAP_VM_TSC_CONTROL: |
938c8745 | 4738 | r = kvm_caps.has_tsc_control; |
92a1f12d | 4739 | break; |
37131313 RK |
4740 | case KVM_CAP_X2APIC_API: |
4741 | r = KVM_X2APIC_API_VALID_FLAGS; | |
4742 | break; | |
8fcc4b59 | 4743 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
4744 | r = kvm_x86_ops.nested_ops->get_state ? |
4745 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 4746 | break; |
b4f69df0 | 4747 | #ifdef CONFIG_KVM_HYPERV |
344c6c80 | 4748 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
b83237ad | 4749 | r = kvm_x86_ops.enable_l2_tlb_flush != NULL; |
5a0165f6 VK |
4750 | break; |
4751 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 4752 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 4753 | break; |
b4f69df0 | 4754 | #endif |
3edd6839 MG |
4755 | case KVM_CAP_SMALLER_MAXPHYADDR: |
4756 | r = (int) allow_smaller_maxphyaddr; | |
4757 | break; | |
004a0124 AJ |
4758 | case KVM_CAP_STEAL_TIME: |
4759 | r = sched_info_on(); | |
4760 | break; | |
fe6b6bc8 | 4761 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
938c8745 | 4762 | if (kvm_caps.has_bus_lock_exit) |
fe6b6bc8 CQ |
4763 | r = KVM_BUS_LOCK_DETECTION_OFF | |
4764 | KVM_BUS_LOCK_DETECTION_EXIT; | |
4765 | else | |
4766 | r = 0; | |
4767 | break; | |
be50b206 | 4768 | case KVM_CAP_XSAVE2: { |
6be3ae45 | 4769 | r = xstate_required_size(kvm_get_filtered_xcr0(), false); |
be50b206 GZ |
4770 | if (r < sizeof(struct kvm_xsave)) |
4771 | r = sizeof(struct kvm_xsave); | |
4772 | break; | |
1c4dc573 | 4773 | } |
ba7bb663 DD |
4774 | case KVM_CAP_PMU_CAPABILITY: |
4775 | r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; | |
4776 | break; | |
6d849191 OU |
4777 | case KVM_CAP_DISABLE_QUIRKS2: |
4778 | r = KVM_X86_VALID_QUIRKS; | |
4779 | break; | |
2f4073e0 TX |
4780 | case KVM_CAP_X86_NOTIFY_VMEXIT: |
4781 | r = kvm_caps.has_notify_vmexit; | |
4782 | break; | |
89ea60c2 SC |
4783 | case KVM_CAP_VM_TYPES: |
4784 | r = BIT(KVM_X86_DEFAULT_VM); | |
4785 | if (kvm_is_vm_type_supported(KVM_X86_SW_PROTECTED_VM)) | |
4786 | r |= BIT(KVM_X86_SW_PROTECTED_VM); | |
4787 | break; | |
018d00d2 | 4788 | default: |
018d00d2 ZX |
4789 | break; |
4790 | } | |
4791 | return r; | |
56f289a8 SC |
4792 | } |
4793 | ||
4794 | static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr) | |
4795 | { | |
4796 | void __user *uaddr = (void __user*)(unsigned long)attr->addr; | |
018d00d2 | 4797 | |
56f289a8 | 4798 | if ((u64)(unsigned long)uaddr != attr->addr) |
6e37ec88 | 4799 | return ERR_PTR_USR(-EFAULT); |
56f289a8 | 4800 | return uaddr; |
018d00d2 ZX |
4801 | } |
4802 | ||
dd6e6312 PB |
4803 | static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr) |
4804 | { | |
4805 | u64 __user *uaddr = kvm_get_attr_addr(attr); | |
4806 | ||
4807 | if (attr->group) | |
4808 | return -ENXIO; | |
4809 | ||
4810 | if (IS_ERR(uaddr)) | |
4811 | return PTR_ERR(uaddr); | |
4812 | ||
4813 | switch (attr->attr) { | |
4814 | case KVM_X86_XCOMP_GUEST_SUPP: | |
938c8745 | 4815 | if (put_user(kvm_caps.supported_xcr0, uaddr)) |
dd6e6312 PB |
4816 | return -EFAULT; |
4817 | return 0; | |
4818 | default: | |
4819 | return -ENXIO; | |
dd6e6312 PB |
4820 | } |
4821 | } | |
4822 | ||
4823 | static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr) | |
4824 | { | |
4825 | if (attr->group) | |
4826 | return -ENXIO; | |
4827 | ||
4828 | switch (attr->attr) { | |
4829 | case KVM_X86_XCOMP_GUEST_SUPP: | |
4830 | return 0; | |
4831 | default: | |
4832 | return -ENXIO; | |
4833 | } | |
4834 | } | |
4835 | ||
043405e1 CO |
4836 | long kvm_arch_dev_ioctl(struct file *filp, |
4837 | unsigned int ioctl, unsigned long arg) | |
4838 | { | |
4839 | void __user *argp = (void __user *)arg; | |
4840 | long r; | |
4841 | ||
4842 | switch (ioctl) { | |
4843 | case KVM_GET_MSR_INDEX_LIST: { | |
4844 | struct kvm_msr_list __user *user_msr_list = argp; | |
4845 | struct kvm_msr_list msr_list; | |
4846 | unsigned n; | |
4847 | ||
4848 | r = -EFAULT; | |
0e96f31e | 4849 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
4850 | goto out; |
4851 | n = msr_list.nmsrs; | |
62ef68bb | 4852 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 4853 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
4854 | goto out; |
4855 | r = -E2BIG; | |
e125e7b6 | 4856 | if (n < msr_list.nmsrs) |
043405e1 CO |
4857 | goto out; |
4858 | r = -EFAULT; | |
4859 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
4860 | num_msrs_to_save * sizeof(u32))) | |
4861 | goto out; | |
e125e7b6 | 4862 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 4863 | &emulated_msrs, |
62ef68bb | 4864 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
4865 | goto out; |
4866 | r = 0; | |
4867 | break; | |
4868 | } | |
9c15bb1d BP |
4869 | case KVM_GET_SUPPORTED_CPUID: |
4870 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
4871 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
4872 | struct kvm_cpuid2 cpuid; | |
4873 | ||
4874 | r = -EFAULT; | |
0e96f31e | 4875 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 4876 | goto out; |
9c15bb1d BP |
4877 | |
4878 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
4879 | ioctl); | |
674eea0f AK |
4880 | if (r) |
4881 | goto out; | |
4882 | ||
4883 | r = -EFAULT; | |
0e96f31e | 4884 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
4885 | goto out; |
4886 | r = 0; | |
4887 | break; | |
4888 | } | |
cf6c26ec | 4889 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 4890 | r = -EFAULT; |
938c8745 SC |
4891 | if (copy_to_user(argp, &kvm_caps.supported_mce_cap, |
4892 | sizeof(kvm_caps.supported_mce_cap))) | |
890ca9ae HY |
4893 | goto out; |
4894 | r = 0; | |
4895 | break; | |
801e459a TL |
4896 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
4897 | struct kvm_msr_list __user *user_msr_list = argp; | |
4898 | struct kvm_msr_list msr_list; | |
4899 | unsigned int n; | |
4900 | ||
4901 | r = -EFAULT; | |
4902 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
4903 | goto out; | |
4904 | n = msr_list.nmsrs; | |
4905 | msr_list.nmsrs = num_msr_based_features; | |
4906 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
4907 | goto out; | |
4908 | r = -E2BIG; | |
4909 | if (n < msr_list.nmsrs) | |
4910 | goto out; | |
4911 | r = -EFAULT; | |
4912 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
4913 | num_msr_based_features * sizeof(u32))) | |
4914 | goto out; | |
4915 | r = 0; | |
4916 | break; | |
4917 | } | |
4918 | case KVM_GET_MSRS: | |
4919 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
4920 | break; | |
b4f69df0 | 4921 | #ifdef CONFIG_KVM_HYPERV |
c21d54f0 VK |
4922 | case KVM_GET_SUPPORTED_HV_CPUID: |
4923 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
4924 | break; | |
b4f69df0 | 4925 | #endif |
dd6e6312 PB |
4926 | case KVM_GET_DEVICE_ATTR: { |
4927 | struct kvm_device_attr attr; | |
4928 | r = -EFAULT; | |
4929 | if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) | |
4930 | break; | |
4931 | r = kvm_x86_dev_get_attr(&attr); | |
4932 | break; | |
4933 | } | |
4934 | case KVM_HAS_DEVICE_ATTR: { | |
4935 | struct kvm_device_attr attr; | |
4936 | r = -EFAULT; | |
4937 | if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) | |
4938 | break; | |
4939 | r = kvm_x86_dev_has_attr(&attr); | |
4940 | break; | |
4941 | } | |
043405e1 CO |
4942 | default: |
4943 | r = -EINVAL; | |
cf6c26ec | 4944 | break; |
043405e1 CO |
4945 | } |
4946 | out: | |
4947 | return r; | |
4948 | } | |
4949 | ||
f5f48ee1 SY |
4950 | static void wbinvd_ipi(void *garbage) |
4951 | { | |
4952 | wbinvd(); | |
4953 | } | |
4954 | ||
4955 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4956 | { | |
e0f0bbc5 | 4957 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
4958 | } |
4959 | ||
313a3dc7 CO |
4960 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
4961 | { | |
f5f48ee1 SY |
4962 | /* Address WBINVD may be executed by guest */ |
4963 | if (need_emulate_wbinvd(vcpu)) { | |
b3646477 | 4964 | if (static_call(kvm_x86_has_wbinvd_exit)()) |
f5f48ee1 SY |
4965 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
4966 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
4967 | smp_call_function_single(vcpu->cpu, | |
4968 | wbinvd_ipi, NULL, 1); | |
4969 | } | |
4970 | ||
b3646477 | 4971 | static_call(kvm_x86_vcpu_load)(vcpu, cpu); |
8f6055cb | 4972 | |
37486135 BM |
4973 | /* Save host pkru register if supported */ |
4974 | vcpu->arch.host_pkru = read_pkru(); | |
4975 | ||
0dd6a6ed ZA |
4976 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
4977 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
4978 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
4979 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 4980 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 4981 | } |
8f6055cb | 4982 | |
b0c39dc6 | 4983 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 4984 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 4985 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
4986 | if (tsc_delta < 0) |
4987 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 4988 | |
b0c39dc6 | 4989 | if (kvm_check_tsc_unstable()) { |
9b399dfd | 4990 | u64 offset = kvm_compute_l1_tsc_offset(vcpu, |
b183aa58 | 4991 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4992 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4993 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4994 | } |
a749e247 PB |
4995 | |
4996 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4997 | kvm_lapic_restart_hv_timer(vcpu); | |
4998 | ||
d98d07ca MT |
4999 | /* |
5000 | * On a host with synchronized TSC, there is no need to update | |
5001 | * kvmclock on vcpu->cpu migration | |
5002 | */ | |
5003 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 5004 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 5005 | if (vcpu->cpu != cpu) |
1bd2009e | 5006 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 5007 | vcpu->cpu = cpu; |
6b7d7e76 | 5008 | } |
c9aaa895 | 5009 | |
c9aaa895 | 5010 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
5011 | } |
5012 | ||
0b9f6c46 PX |
5013 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
5014 | { | |
7e2175eb DW |
5015 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
5016 | struct kvm_steal_time __user *st; | |
5017 | struct kvm_memslots *slots; | |
5018 | static const u8 preempted = KVM_VCPU_PREEMPTED; | |
c3c28d24 | 5019 | gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; |
b0431382 | 5020 | |
6cd88243 PB |
5021 | /* |
5022 | * The vCPU can be marked preempted if and only if the VM-Exit was on | |
5023 | * an instruction boundary and will not trigger guest emulation of any | |
5024 | * kind (see vcpu_run). Vendor specific code controls (conservatively) | |
5025 | * when this is true, for example allowing the vCPU to be marked | |
5026 | * preempted if and only if the VM-Exit was due to a host interrupt. | |
5027 | */ | |
5028 | if (!vcpu->arch.at_instruction_boundary) { | |
5029 | vcpu->stat.preemption_other++; | |
5030 | return; | |
5031 | } | |
5032 | ||
5033 | vcpu->stat.preemption_reported++; | |
0b9f6c46 PX |
5034 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
5035 | return; | |
5036 | ||
a6bd811f | 5037 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
5038 | return; |
5039 | ||
7e2175eb DW |
5040 | /* This happens on process exit */ |
5041 | if (unlikely(current->mm != vcpu->kvm->mm)) | |
9c1a0744 | 5042 | return; |
b0431382 | 5043 | |
7e2175eb DW |
5044 | slots = kvm_memslots(vcpu->kvm); |
5045 | ||
5046 | if (unlikely(slots->generation != ghc->generation || | |
c3c28d24 | 5047 | gpa != ghc->gpa || |
7e2175eb | 5048 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) |
9c1a0744 | 5049 | return; |
b0431382 | 5050 | |
7e2175eb DW |
5051 | st = (struct kvm_steal_time __user *)ghc->hva; |
5052 | BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); | |
0b9f6c46 | 5053 | |
7e2175eb DW |
5054 | if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) |
5055 | vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; | |
0b9f6c46 | 5056 | |
7e2175eb | 5057 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); |
0b9f6c46 PX |
5058 | } |
5059 | ||
313a3dc7 CO |
5060 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
5061 | { | |
9c1a0744 WL |
5062 | int idx; |
5063 | ||
54aa83c9 PB |
5064 | if (vcpu->preempted) { |
5065 | if (!vcpu->arch.guest_state_protected) | |
5066 | vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); | |
de63ad4c | 5067 | |
54aa83c9 PB |
5068 | /* |
5069 | * Take the srcu lock as memslots will be accessed to check the gfn | |
5070 | * cache generation against the memslots generation. | |
5071 | */ | |
5072 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
5073 | if (kvm_xen_msr_enabled(vcpu->kvm)) | |
5074 | kvm_xen_runstate_set_preempted(vcpu); | |
5075 | else | |
5076 | kvm_steal_time_set_preempted(vcpu); | |
5077 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
5078 | } | |
30b5c851 | 5079 | |
b3646477 | 5080 | static_call(kvm_x86_vcpu_put)(vcpu); |
4ea1636b | 5081 | vcpu->arch.last_host_tsc = rdtsc(); |
313a3dc7 CO |
5082 | } |
5083 | ||
313a3dc7 CO |
5084 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
5085 | struct kvm_lapic_state *s) | |
5086 | { | |
37c4dbf3 | 5087 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); |
d62caabb | 5088 | |
a92e2543 | 5089 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
5090 | } |
5091 | ||
5092 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
5093 | struct kvm_lapic_state *s) | |
5094 | { | |
a92e2543 RK |
5095 | int r; |
5096 | ||
5097 | r = kvm_apic_set_state(vcpu, s); | |
5098 | if (r) | |
5099 | return r; | |
cb142eb7 | 5100 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
5101 | |
5102 | return 0; | |
5103 | } | |
5104 | ||
127a457a MG |
5105 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
5106 | { | |
71cc849b PB |
5107 | /* |
5108 | * We can accept userspace's request for interrupt injection | |
5109 | * as long as we have a place to store the interrupt number. | |
5110 | * The actual injection will happen when the CPU is able to | |
5111 | * deliver the interrupt. | |
5112 | */ | |
5113 | if (kvm_cpu_has_extint(vcpu)) | |
5114 | return false; | |
5115 | ||
5116 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
5117 | return (!lapic_in_kernel(vcpu) || |
5118 | kvm_apic_accept_pic_intr(vcpu)); | |
5119 | } | |
5120 | ||
782d422b MG |
5121 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
5122 | { | |
fa7a549d PB |
5123 | /* |
5124 | * Do not cause an interrupt window exit if an exception | |
5125 | * is pending or an event needs reinjection; userspace | |
5126 | * might want to inject the interrupt manually using KVM_SET_REGS | |
5127 | * or KVM_SET_SREGS. For that to work, we must be at an | |
5128 | * instruction boundary and with no events half-injected. | |
5129 | */ | |
5130 | return (kvm_arch_interrupt_allowed(vcpu) && | |
5131 | kvm_cpu_accept_dm_intr(vcpu) && | |
5132 | !kvm_event_needs_reinjection(vcpu) && | |
7709aba8 | 5133 | !kvm_is_exception_pending(vcpu)); |
782d422b MG |
5134 | } |
5135 | ||
f77bc6a4 ZX |
5136 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
5137 | struct kvm_interrupt *irq) | |
5138 | { | |
02cdb50f | 5139 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 5140 | return -EINVAL; |
1c1a9ce9 SR |
5141 | |
5142 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
5143 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
5144 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5145 | return 0; | |
5146 | } | |
5147 | ||
5148 | /* | |
5149 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
5150 | * fail for in-kernel 8259. | |
5151 | */ | |
5152 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 5153 | return -ENXIO; |
f77bc6a4 | 5154 | |
1c1a9ce9 SR |
5155 | if (vcpu->arch.pending_external_vector != -1) |
5156 | return -EEXIST; | |
f77bc6a4 | 5157 | |
1c1a9ce9 | 5158 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 5159 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
5160 | return 0; |
5161 | } | |
5162 | ||
c4abb7c9 JK |
5163 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
5164 | { | |
c4abb7c9 | 5165 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
5166 | |
5167 | return 0; | |
5168 | } | |
5169 | ||
b209749f AK |
5170 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
5171 | struct kvm_tpr_access_ctl *tac) | |
5172 | { | |
5173 | if (tac->flags) | |
5174 | return -EINVAL; | |
5175 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
5176 | return 0; | |
5177 | } | |
5178 | ||
890ca9ae HY |
5179 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
5180 | u64 mcg_cap) | |
5181 | { | |
5182 | int r; | |
5183 | unsigned bank_num = mcg_cap & 0xff, bank; | |
5184 | ||
5185 | r = -EINVAL; | |
c4e0e4ab | 5186 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 5187 | goto out; |
938c8745 | 5188 | if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000)) |
890ca9ae HY |
5189 | goto out; |
5190 | r = 0; | |
5191 | vcpu->arch.mcg_cap = mcg_cap; | |
5192 | /* Init IA32_MCG_CTL to all 1s */ | |
5193 | if (mcg_cap & MCG_CTL_P) | |
5194 | vcpu->arch.mcg_ctl = ~(u64)0; | |
281b5278 JW |
5195 | /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */ |
5196 | for (bank = 0; bank < bank_num; bank++) { | |
890ca9ae | 5197 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; |
281b5278 JW |
5198 | if (mcg_cap & MCG_CMCI_P) |
5199 | vcpu->arch.mci_ctl2_banks[bank] = 0; | |
5200 | } | |
f83894b2 SC |
5201 | |
5202 | kvm_apic_after_set_mcg_cap(vcpu); | |
c45dcc71 | 5203 | |
b3646477 | 5204 | static_call(kvm_x86_setup_mce)(vcpu); |
890ca9ae HY |
5205 | out: |
5206 | return r; | |
5207 | } | |
5208 | ||
aebc3ca1 JW |
5209 | /* |
5210 | * Validate this is an UCNA (uncorrectable no action) error by checking the | |
5211 | * MCG_STATUS and MCi_STATUS registers: | |
5212 | * - none of the bits for Machine Check Exceptions are set | |
5213 | * - both the VAL (valid) and UC (uncorrectable) bits are set | |
5214 | * MCI_STATUS_PCC - Processor Context Corrupted | |
5215 | * MCI_STATUS_S - Signaled as a Machine Check Exception | |
5216 | * MCI_STATUS_AR - Software recoverable Action Required | |
5217 | */ | |
5218 | static bool is_ucna(struct kvm_x86_mce *mce) | |
5219 | { | |
5220 | return !mce->mcg_status && | |
5221 | !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) && | |
5222 | (mce->status & MCI_STATUS_VAL) && | |
5223 | (mce->status & MCI_STATUS_UC); | |
5224 | } | |
5225 | ||
5226 | static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks) | |
5227 | { | |
5228 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
5229 | ||
5230 | banks[1] = mce->status; | |
5231 | banks[2] = mce->addr; | |
5232 | banks[3] = mce->misc; | |
5233 | vcpu->arch.mcg_status = mce->mcg_status; | |
5234 | ||
5235 | if (!(mcg_cap & MCG_CMCI_P) || | |
5236 | !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN)) | |
5237 | return 0; | |
5238 | ||
5239 | if (lapic_in_kernel(vcpu)) | |
5240 | kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI); | |
5241 | ||
5242 | return 0; | |
5243 | } | |
5244 | ||
890ca9ae HY |
5245 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, |
5246 | struct kvm_x86_mce *mce) | |
5247 | { | |
5248 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
5249 | unsigned bank_num = mcg_cap & 0xff; | |
5250 | u64 *banks = vcpu->arch.mce_banks; | |
5251 | ||
5252 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
5253 | return -EINVAL; | |
aebc3ca1 JW |
5254 | |
5255 | banks += array_index_nospec(4 * mce->bank, 4 * bank_num); | |
5256 | ||
5257 | if (is_ucna(mce)) | |
5258 | return kvm_vcpu_x86_set_ucna(vcpu, mce, banks); | |
5259 | ||
890ca9ae HY |
5260 | /* |
5261 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
5262 | * reporting is disabled | |
5263 | */ | |
5264 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
5265 | vcpu->arch.mcg_ctl != ~(u64)0) | |
5266 | return 0; | |
890ca9ae HY |
5267 | /* |
5268 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
5269 | * reporting is disabled for the bank | |
5270 | */ | |
5271 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
5272 | return 0; | |
5273 | if (mce->status & MCI_STATUS_UC) { | |
5274 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
607475cf | 5275 | !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 5276 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
5277 | return 0; |
5278 | } | |
5279 | if (banks[1] & MCI_STATUS_VAL) | |
5280 | mce->status |= MCI_STATUS_OVER; | |
5281 | banks[2] = mce->addr; | |
5282 | banks[3] = mce->misc; | |
5283 | vcpu->arch.mcg_status = mce->mcg_status; | |
5284 | banks[1] = mce->status; | |
5285 | kvm_queue_exception(vcpu, MC_VECTOR); | |
5286 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
5287 | || !(banks[1] & MCI_STATUS_UC)) { | |
5288 | if (banks[1] & MCI_STATUS_VAL) | |
5289 | mce->status |= MCI_STATUS_OVER; | |
5290 | banks[2] = mce->addr; | |
5291 | banks[3] = mce->misc; | |
5292 | banks[1] = mce->status; | |
5293 | } else | |
5294 | banks[1] |= MCI_STATUS_OVER; | |
5295 | return 0; | |
5296 | } | |
5297 | ||
3cfc3092 JK |
5298 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
5299 | struct kvm_vcpu_events *events) | |
5300 | { | |
7709aba8 | 5301 | struct kvm_queued_exception *ex; |
d4963e31 | 5302 | |
7460fb4a | 5303 | process_nmi(vcpu); |
59073aaf | 5304 | |
cf7316d0 | 5305 | #ifdef CONFIG_KVM_SMM |
1f7becf1 JZ |
5306 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
5307 | process_smi(vcpu); | |
cf7316d0 | 5308 | #endif |
1f7becf1 | 5309 | |
a06230b6 | 5310 | /* |
7709aba8 SC |
5311 | * KVM's ABI only allows for one exception to be migrated. Luckily, |
5312 | * the only time there can be two queued exceptions is if there's a | |
5313 | * non-exiting _injected_ exception, and a pending exiting exception. | |
5314 | * In that case, ignore the VM-Exiting exception as it's an extension | |
5315 | * of the injected exception. | |
5316 | */ | |
5317 | if (vcpu->arch.exception_vmexit.pending && | |
5318 | !vcpu->arch.exception.pending && | |
5319 | !vcpu->arch.exception.injected) | |
5320 | ex = &vcpu->arch.exception_vmexit; | |
5321 | else | |
5322 | ex = &vcpu->arch.exception; | |
5323 | ||
a06230b6 | 5324 | /* |
d4963e31 SC |
5325 | * In guest mode, payload delivery should be deferred if the exception |
5326 | * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1 | |
5327 | * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability, | |
5328 | * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not | |
5329 | * propagate the payload and so it cannot be safely deferred. Deliver | |
5330 | * the payload if the capability hasn't been requested. | |
a06230b6 OU |
5331 | */ |
5332 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
d4963e31 SC |
5333 | ex->pending && ex->has_payload) |
5334 | kvm_deliver_exception_payload(vcpu, ex); | |
a06230b6 | 5335 | |
85672346 PB |
5336 | memset(events, 0, sizeof(*events)); |
5337 | ||
664f8e26 | 5338 | /* |
59073aaf JM |
5339 | * The API doesn't provide the instruction length for software |
5340 | * exceptions, so don't report them. As long as the guest RIP | |
5341 | * isn't advanced, we should expect to encounter the exception | |
5342 | * again. | |
664f8e26 | 5343 | */ |
85672346 | 5344 | if (!kvm_exception_is_soft(ex->vector)) { |
d4963e31 SC |
5345 | events->exception.injected = ex->injected; |
5346 | events->exception.pending = ex->pending; | |
59073aaf JM |
5347 | /* |
5348 | * For ABI compatibility, deliberately conflate | |
5349 | * pending and injected exceptions when | |
5350 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
5351 | */ | |
5352 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
d4963e31 | 5353 | events->exception.injected |= ex->pending; |
59073aaf | 5354 | } |
d4963e31 SC |
5355 | events->exception.nr = ex->vector; |
5356 | events->exception.has_error_code = ex->has_error_code; | |
5357 | events->exception.error_code = ex->error_code; | |
5358 | events->exception_has_payload = ex->has_payload; | |
5359 | events->exception_payload = ex->payload; | |
3cfc3092 | 5360 | |
03b82a30 | 5361 | events->interrupt.injected = |
04140b41 | 5362 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 5363 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
b3646477 | 5364 | events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
3cfc3092 JK |
5365 | |
5366 | events->nmi.injected = vcpu->arch.nmi_injected; | |
fa4c027a | 5367 | events->nmi.pending = kvm_get_nr_pending_nmis(vcpu); |
b3646477 | 5368 | events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); |
3cfc3092 | 5369 | |
85672346 | 5370 | /* events->sipi_vector is never valid when reporting to user space */ |
3cfc3092 | 5371 | |
a7662aa5 | 5372 | #ifdef CONFIG_KVM_SMM |
f077825a PB |
5373 | events->smi.smm = is_smm(vcpu); |
5374 | events->smi.pending = vcpu->arch.smi_pending; | |
5375 | events->smi.smm_inside_nmi = | |
5376 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
a7662aa5 | 5377 | #endif |
f077825a PB |
5378 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); |
5379 | ||
dab4b911 | 5380 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
5381 | | KVM_VCPUEVENT_VALID_SHADOW |
5382 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
5383 | if (vcpu->kvm->arch.exception_payload_enabled) |
5384 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
ed235117 CQ |
5385 | if (vcpu->kvm->arch.triple_fault_event) { |
5386 | events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5387 | events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT; | |
5388 | } | |
3cfc3092 JK |
5389 | } |
5390 | ||
5391 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
5392 | struct kvm_vcpu_events *events) | |
5393 | { | |
dab4b911 | 5394 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 5395 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 5396 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf | 5397 | | KVM_VCPUEVENT_VALID_SMM |
ed235117 CQ |
5398 | | KVM_VCPUEVENT_VALID_PAYLOAD |
5399 | | KVM_VCPUEVENT_VALID_TRIPLE_FAULT)) | |
3cfc3092 JK |
5400 | return -EINVAL; |
5401 | ||
59073aaf JM |
5402 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
5403 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
5404 | return -EINVAL; | |
5405 | if (events->exception.pending) | |
5406 | events->exception.injected = 0; | |
5407 | else | |
5408 | events->exception_has_payload = 0; | |
5409 | } else { | |
5410 | events->exception.pending = 0; | |
5411 | events->exception_has_payload = 0; | |
5412 | } | |
5413 | ||
5414 | if ((events->exception.injected || events->exception.pending) && | |
5415 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
5416 | return -EINVAL; |
5417 | ||
28bf2888 DH |
5418 | /* INITs are latched while in SMM */ |
5419 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
5420 | (events->smi.smm || events->smi.pending) && | |
5421 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
5422 | return -EINVAL; | |
5423 | ||
7460fb4a | 5424 | process_nmi(vcpu); |
7709aba8 SC |
5425 | |
5426 | /* | |
5427 | * Flag that userspace is stuffing an exception, the next KVM_RUN will | |
5428 | * morph the exception to a VM-Exit if appropriate. Do this only for | |
5429 | * pending exceptions, already-injected exceptions are not subject to | |
5430 | * intercpetion. Note, userspace that conflates pending and injected | |
5431 | * is hosed, and will incorrectly convert an injected exception into a | |
5432 | * pending exception, which in turn may cause a spurious VM-Exit. | |
5433 | */ | |
5434 | vcpu->arch.exception_from_userspace = events->exception.pending; | |
5435 | ||
5436 | vcpu->arch.exception_vmexit.pending = false; | |
5437 | ||
59073aaf JM |
5438 | vcpu->arch.exception.injected = events->exception.injected; |
5439 | vcpu->arch.exception.pending = events->exception.pending; | |
d4963e31 | 5440 | vcpu->arch.exception.vector = events->exception.nr; |
3cfc3092 JK |
5441 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; |
5442 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
5443 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
5444 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 5445 | |
04140b41 | 5446 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
5447 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
5448 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 5449 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
b3646477 JB |
5450 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, |
5451 | events->interrupt.shadow); | |
3cfc3092 JK |
5452 | |
5453 | vcpu->arch.nmi_injected = events->nmi.injected; | |
ab2ee212 | 5454 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) { |
bdedff26 SC |
5455 | vcpu->arch.nmi_pending = 0; |
5456 | atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending); | |
5457 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
ab2ee212 | 5458 | } |
b3646477 | 5459 | static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); |
3cfc3092 | 5460 | |
66450a21 | 5461 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 5462 | lapic_in_kernel(vcpu)) |
66450a21 | 5463 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 5464 | |
f077825a | 5465 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
4b8e1b32 | 5466 | #ifdef CONFIG_KVM_SMM |
f7e57078 | 5467 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
f9697df2 | 5468 | kvm_leave_nested(vcpu); |
dc87275f | 5469 | kvm_smm_changed(vcpu, events->smi.smm); |
f7e57078 | 5470 | } |
6ef4e07e | 5471 | |
f077825a | 5472 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
5473 | |
5474 | if (events->smi.smm) { | |
5475 | if (events->smi.smm_inside_nmi) | |
5476 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 5477 | else |
f4ef1910 | 5478 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
5479 | } |
5480 | ||
4b8e1b32 PB |
5481 | #else |
5482 | if (events->smi.smm || events->smi.pending || | |
5483 | events->smi.smm_inside_nmi) | |
5484 | return -EINVAL; | |
5485 | #endif | |
5486 | ||
ff90afa7 LA |
5487 | if (lapic_in_kernel(vcpu)) { |
5488 | if (events->smi.latched_init) | |
5489 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
5490 | else | |
5491 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
5492 | } |
5493 | } | |
5494 | ||
ed235117 CQ |
5495 | if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) { |
5496 | if (!vcpu->kvm->arch.triple_fault_event) | |
5497 | return -EINVAL; | |
5498 | if (events->triple_fault.pending) | |
5499 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5500 | else | |
5501 | kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5502 | } | |
5503 | ||
3842d135 AK |
5504 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5505 | ||
3cfc3092 JK |
5506 | return 0; |
5507 | } | |
5508 | ||
a1efbe77 JK |
5509 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
5510 | struct kvm_debugregs *dbgregs) | |
5511 | { | |
73aaf249 JK |
5512 | unsigned long val; |
5513 | ||
2c10b614 | 5514 | memset(dbgregs, 0, sizeof(*dbgregs)); |
a1efbe77 | 5515 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 5516 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 5517 | dbgregs->dr6 = val; |
a1efbe77 | 5518 | dbgregs->dr7 = vcpu->arch.dr7; |
a1efbe77 JK |
5519 | } |
5520 | ||
5521 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
5522 | struct kvm_debugregs *dbgregs) | |
5523 | { | |
5524 | if (dbgregs->flags) | |
5525 | return -EINVAL; | |
5526 | ||
fd238002 | 5527 | if (!kvm_dr6_valid(dbgregs->dr6)) |
d14bdb55 | 5528 | return -EINVAL; |
fd238002 | 5529 | if (!kvm_dr7_valid(dbgregs->dr7)) |
d14bdb55 PB |
5530 | return -EINVAL; |
5531 | ||
a1efbe77 | 5532 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 5533 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
5534 | vcpu->arch.dr6 = dbgregs->dr6; |
5535 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 5536 | kvm_update_dr7(vcpu); |
a1efbe77 | 5537 | |
a1efbe77 JK |
5538 | return 0; |
5539 | } | |
5540 | ||
18164f66 SC |
5541 | |
5542 | static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, | |
5543 | u8 *state, unsigned int size) | |
2d5b5a66 | 5544 | { |
8647c52e SC |
5545 | /* |
5546 | * Only copy state for features that are enabled for the guest. The | |
5547 | * state itself isn't problematic, but setting bits in the header for | |
5548 | * features that are supported in *this* host but not exposed to the | |
5549 | * guest can result in KVM_SET_XSAVE failing when live migrating to a | |
5550 | * compatible host without the features that are NOT exposed to the | |
5551 | * guest. | |
5552 | * | |
5553 | * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if | |
5554 | * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't | |
5555 | * supported by the host. | |
5556 | */ | |
5557 | u64 supported_xcr0 = vcpu->arch.guest_supported_xcr0 | | |
5558 | XFEATURE_MASK_FPSSE; | |
5559 | ||
d69c1382 | 5560 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
5561 | return; |
5562 | ||
18164f66 | 5563 | fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, state, size, |
8647c52e | 5564 | supported_xcr0, vcpu->arch.pkru); |
2d5b5a66 SY |
5565 | } |
5566 | ||
18164f66 SC |
5567 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
5568 | struct kvm_xsave *guest_xsave) | |
be50b206 | 5569 | { |
ef8d8903 LX |
5570 | kvm_vcpu_ioctl_x86_get_xsave2(vcpu, (void *)guest_xsave->region, |
5571 | sizeof(guest_xsave->region)); | |
be50b206 GZ |
5572 | } |
5573 | ||
2d5b5a66 SY |
5574 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
5575 | struct kvm_xsave *guest_xsave) | |
5576 | { | |
d69c1382 | 5577 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
5578 | return 0; |
5579 | ||
d69c1382 TG |
5580 | return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, |
5581 | guest_xsave->region, | |
938c8745 SC |
5582 | kvm_caps.supported_xcr0, |
5583 | &vcpu->arch.pkru); | |
2d5b5a66 SY |
5584 | } |
5585 | ||
5586 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
5587 | struct kvm_xcrs *guest_xcrs) | |
5588 | { | |
d366bf7e | 5589 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
5590 | guest_xcrs->nr_xcrs = 0; |
5591 | return; | |
5592 | } | |
5593 | ||
5594 | guest_xcrs->nr_xcrs = 1; | |
5595 | guest_xcrs->flags = 0; | |
5596 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
5597 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
5598 | } | |
5599 | ||
5600 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
5601 | struct kvm_xcrs *guest_xcrs) | |
5602 | { | |
5603 | int i, r = 0; | |
5604 | ||
d366bf7e | 5605 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
5606 | return -EINVAL; |
5607 | ||
5608 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
5609 | return -EINVAL; | |
5610 | ||
5611 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
5612 | /* Only support XCR0 currently */ | |
c67a04cb | 5613 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 5614 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 5615 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
5616 | break; |
5617 | } | |
5618 | if (r) | |
5619 | r = -EINVAL; | |
5620 | return r; | |
5621 | } | |
5622 | ||
1c0b28c2 EM |
5623 | /* |
5624 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
5625 | * stopped by the hypervisor. This function will be called from the host only. | |
5626 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
5627 | * does not support pv clocks. | |
5628 | */ | |
5629 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
5630 | { | |
916d3608 | 5631 | if (!vcpu->arch.pv_time.active) |
1c0b28c2 | 5632 | return -EINVAL; |
51d59c6b | 5633 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
5634 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
5635 | return 0; | |
5636 | } | |
5637 | ||
828ca896 OU |
5638 | static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, |
5639 | struct kvm_device_attr *attr) | |
5640 | { | |
5641 | int r; | |
5642 | ||
5643 | switch (attr->attr) { | |
5644 | case KVM_VCPU_TSC_OFFSET: | |
5645 | r = 0; | |
5646 | break; | |
5647 | default: | |
5648 | r = -ENXIO; | |
5649 | } | |
5650 | ||
5651 | return r; | |
5652 | } | |
5653 | ||
5654 | static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, | |
5655 | struct kvm_device_attr *attr) | |
5656 | { | |
56f289a8 | 5657 | u64 __user *uaddr = kvm_get_attr_addr(attr); |
828ca896 OU |
5658 | int r; |
5659 | ||
56f289a8 SC |
5660 | if (IS_ERR(uaddr)) |
5661 | return PTR_ERR(uaddr); | |
828ca896 OU |
5662 | |
5663 | switch (attr->attr) { | |
5664 | case KVM_VCPU_TSC_OFFSET: | |
5665 | r = -EFAULT; | |
5666 | if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) | |
5667 | break; | |
5668 | r = 0; | |
5669 | break; | |
5670 | default: | |
5671 | r = -ENXIO; | |
5672 | } | |
5673 | ||
5674 | return r; | |
5675 | } | |
5676 | ||
5677 | static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, | |
5678 | struct kvm_device_attr *attr) | |
5679 | { | |
56f289a8 | 5680 | u64 __user *uaddr = kvm_get_attr_addr(attr); |
828ca896 OU |
5681 | struct kvm *kvm = vcpu->kvm; |
5682 | int r; | |
5683 | ||
56f289a8 SC |
5684 | if (IS_ERR(uaddr)) |
5685 | return PTR_ERR(uaddr); | |
828ca896 OU |
5686 | |
5687 | switch (attr->attr) { | |
5688 | case KVM_VCPU_TSC_OFFSET: { | |
5689 | u64 offset, tsc, ns; | |
5690 | unsigned long flags; | |
5691 | bool matched; | |
5692 | ||
5693 | r = -EFAULT; | |
5694 | if (get_user(offset, uaddr)) | |
5695 | break; | |
5696 | ||
5697 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
5698 | ||
5699 | matched = (vcpu->arch.virtual_tsc_khz && | |
5700 | kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && | |
5701 | kvm->arch.last_tsc_offset == offset); | |
5702 | ||
62711e5a | 5703 | tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; |
828ca896 OU |
5704 | ns = get_kvmclock_base_ns(); |
5705 | ||
bf328e22 | 5706 | kvm->arch.user_set_tsc = true; |
828ca896 OU |
5707 | __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); |
5708 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
5709 | ||
5710 | r = 0; | |
5711 | break; | |
5712 | } | |
5713 | default: | |
5714 | r = -ENXIO; | |
5715 | } | |
5716 | ||
5717 | return r; | |
5718 | } | |
5719 | ||
5720 | static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, | |
5721 | unsigned int ioctl, | |
5722 | void __user *argp) | |
5723 | { | |
5724 | struct kvm_device_attr attr; | |
5725 | int r; | |
5726 | ||
5727 | if (copy_from_user(&attr, argp, sizeof(attr))) | |
5728 | return -EFAULT; | |
5729 | ||
5730 | if (attr.group != KVM_VCPU_TSC_CTRL) | |
5731 | return -ENXIO; | |
5732 | ||
5733 | switch (ioctl) { | |
5734 | case KVM_HAS_DEVICE_ATTR: | |
5735 | r = kvm_arch_tsc_has_attr(vcpu, &attr); | |
5736 | break; | |
5737 | case KVM_GET_DEVICE_ATTR: | |
5738 | r = kvm_arch_tsc_get_attr(vcpu, &attr); | |
5739 | break; | |
5740 | case KVM_SET_DEVICE_ATTR: | |
5741 | r = kvm_arch_tsc_set_attr(vcpu, &attr); | |
5742 | break; | |
5743 | } | |
5744 | ||
5745 | return r; | |
5746 | } | |
5747 | ||
5c919412 AS |
5748 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
5749 | struct kvm_enable_cap *cap) | |
5750 | { | |
5751 | if (cap->flags) | |
5752 | return -EINVAL; | |
5753 | ||
5754 | switch (cap->cap) { | |
b4f69df0 | 5755 | #ifdef CONFIG_KVM_HYPERV |
efc479e6 RK |
5756 | case KVM_CAP_HYPERV_SYNIC2: |
5757 | if (cap->args[0]) | |
5758 | return -EINVAL; | |
df561f66 | 5759 | fallthrough; |
b2869f28 | 5760 | |
5c919412 | 5761 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
5762 | if (!irqchip_in_kernel(vcpu->kvm)) |
5763 | return -EINVAL; | |
efc479e6 RK |
5764 | return kvm_hv_activate_synic(vcpu, cap->cap == |
5765 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 5766 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
b4f69df0 VK |
5767 | { |
5768 | int r; | |
5769 | uint16_t vmcs_version; | |
5770 | void __user *user_ptr; | |
5771 | ||
5772 | if (!kvm_x86_ops.nested_ops->enable_evmcs) | |
5773 | return -ENOTTY; | |
5774 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); | |
5775 | if (!r) { | |
5776 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
5777 | if (copy_to_user(user_ptr, &vmcs_version, | |
5778 | sizeof(vmcs_version))) | |
5779 | r = -EFAULT; | |
5780 | } | |
5781 | return r; | |
57b119da | 5782 | } |
344c6c80 | 5783 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
b83237ad | 5784 | if (!kvm_x86_ops.enable_l2_tlb_flush) |
344c6c80 TL |
5785 | return -ENOTTY; |
5786 | ||
b83237ad | 5787 | return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu); |
57b119da | 5788 | |
644f7067 VK |
5789 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
5790 | return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); | |
b4f69df0 | 5791 | #endif |
644f7067 | 5792 | |
66570e96 OU |
5793 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
5794 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
5795 | if (vcpu->arch.pv_cpuid.enforce) |
5796 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
5797 | |
5798 | return 0; | |
5c919412 AS |
5799 | default: |
5800 | return -EINVAL; | |
5801 | } | |
5802 | } | |
5803 | ||
313a3dc7 CO |
5804 | long kvm_arch_vcpu_ioctl(struct file *filp, |
5805 | unsigned int ioctl, unsigned long arg) | |
5806 | { | |
5807 | struct kvm_vcpu *vcpu = filp->private_data; | |
5808 | void __user *argp = (void __user *)arg; | |
5809 | int r; | |
d1ac91d8 | 5810 | union { |
6dba9403 | 5811 | struct kvm_sregs2 *sregs2; |
d1ac91d8 AK |
5812 | struct kvm_lapic_state *lapic; |
5813 | struct kvm_xsave *xsave; | |
5814 | struct kvm_xcrs *xcrs; | |
5815 | void *buffer; | |
5816 | } u; | |
5817 | ||
9b062471 CD |
5818 | vcpu_load(vcpu); |
5819 | ||
d1ac91d8 | 5820 | u.buffer = NULL; |
313a3dc7 CO |
5821 | switch (ioctl) { |
5822 | case KVM_GET_LAPIC: { | |
2204ae3c | 5823 | r = -EINVAL; |
bce87cce | 5824 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5825 | goto out; |
254272ce BG |
5826 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
5827 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 5828 | |
b772ff36 | 5829 | r = -ENOMEM; |
d1ac91d8 | 5830 | if (!u.lapic) |
b772ff36 | 5831 | goto out; |
d1ac91d8 | 5832 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5833 | if (r) |
5834 | goto out; | |
5835 | r = -EFAULT; | |
d1ac91d8 | 5836 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
5837 | goto out; |
5838 | r = 0; | |
5839 | break; | |
5840 | } | |
5841 | case KVM_SET_LAPIC: { | |
2204ae3c | 5842 | r = -EINVAL; |
bce87cce | 5843 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5844 | goto out; |
ff5c2c03 | 5845 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
5846 | if (IS_ERR(u.lapic)) { |
5847 | r = PTR_ERR(u.lapic); | |
5848 | goto out_nofree; | |
5849 | } | |
ff5c2c03 | 5850 | |
d1ac91d8 | 5851 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5852 | break; |
5853 | } | |
f77bc6a4 ZX |
5854 | case KVM_INTERRUPT: { |
5855 | struct kvm_interrupt irq; | |
5856 | ||
5857 | r = -EFAULT; | |
0e96f31e | 5858 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
5859 | goto out; |
5860 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
5861 | break; |
5862 | } | |
c4abb7c9 JK |
5863 | case KVM_NMI: { |
5864 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
5865 | break; |
5866 | } | |
f077825a | 5867 | case KVM_SMI: { |
b0b42197 | 5868 | r = kvm_inject_smi(vcpu); |
f077825a PB |
5869 | break; |
5870 | } | |
313a3dc7 CO |
5871 | case KVM_SET_CPUID: { |
5872 | struct kvm_cpuid __user *cpuid_arg = argp; | |
5873 | struct kvm_cpuid cpuid; | |
5874 | ||
5875 | r = -EFAULT; | |
0e96f31e | 5876 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
5877 | goto out; |
5878 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
5879 | break; |
5880 | } | |
07716717 DK |
5881 | case KVM_SET_CPUID2: { |
5882 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5883 | struct kvm_cpuid2 cpuid; | |
5884 | ||
5885 | r = -EFAULT; | |
0e96f31e | 5886 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5887 | goto out; |
5888 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 5889 | cpuid_arg->entries); |
07716717 DK |
5890 | break; |
5891 | } | |
5892 | case KVM_GET_CPUID2: { | |
5893 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5894 | struct kvm_cpuid2 cpuid; | |
5895 | ||
5896 | r = -EFAULT; | |
0e96f31e | 5897 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5898 | goto out; |
5899 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 5900 | cpuid_arg->entries); |
07716717 DK |
5901 | if (r) |
5902 | goto out; | |
5903 | r = -EFAULT; | |
0e96f31e | 5904 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
5905 | goto out; |
5906 | r = 0; | |
5907 | break; | |
5908 | } | |
801e459a TL |
5909 | case KVM_GET_MSRS: { |
5910 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 5911 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 5912 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5913 | break; |
801e459a TL |
5914 | } |
5915 | case KVM_SET_MSRS: { | |
5916 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 5917 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 5918 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5919 | break; |
801e459a | 5920 | } |
b209749f AK |
5921 | case KVM_TPR_ACCESS_REPORTING: { |
5922 | struct kvm_tpr_access_ctl tac; | |
5923 | ||
5924 | r = -EFAULT; | |
0e96f31e | 5925 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
5926 | goto out; |
5927 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
5928 | if (r) | |
5929 | goto out; | |
5930 | r = -EFAULT; | |
0e96f31e | 5931 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
5932 | goto out; |
5933 | r = 0; | |
5934 | break; | |
5935 | }; | |
b93463aa AK |
5936 | case KVM_SET_VAPIC_ADDR: { |
5937 | struct kvm_vapic_addr va; | |
7301d6ab | 5938 | int idx; |
b93463aa AK |
5939 | |
5940 | r = -EINVAL; | |
35754c98 | 5941 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
5942 | goto out; |
5943 | r = -EFAULT; | |
0e96f31e | 5944 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 5945 | goto out; |
7301d6ab | 5946 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 5947 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 5948 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5949 | break; |
5950 | } | |
890ca9ae HY |
5951 | case KVM_X86_SETUP_MCE: { |
5952 | u64 mcg_cap; | |
5953 | ||
5954 | r = -EFAULT; | |
0e96f31e | 5955 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
5956 | goto out; |
5957 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
5958 | break; | |
5959 | } | |
5960 | case KVM_X86_SET_MCE: { | |
5961 | struct kvm_x86_mce mce; | |
5962 | ||
5963 | r = -EFAULT; | |
0e96f31e | 5964 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
5965 | goto out; |
5966 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
5967 | break; | |
5968 | } | |
3cfc3092 JK |
5969 | case KVM_GET_VCPU_EVENTS: { |
5970 | struct kvm_vcpu_events events; | |
5971 | ||
5972 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
5973 | ||
5974 | r = -EFAULT; | |
5975 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
5976 | break; | |
5977 | r = 0; | |
5978 | break; | |
5979 | } | |
5980 | case KVM_SET_VCPU_EVENTS: { | |
5981 | struct kvm_vcpu_events events; | |
5982 | ||
5983 | r = -EFAULT; | |
5984 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
5985 | break; | |
5986 | ||
5987 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
5988 | break; | |
5989 | } | |
a1efbe77 JK |
5990 | case KVM_GET_DEBUGREGS: { |
5991 | struct kvm_debugregs dbgregs; | |
5992 | ||
5993 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
5994 | ||
5995 | r = -EFAULT; | |
5996 | if (copy_to_user(argp, &dbgregs, | |
5997 | sizeof(struct kvm_debugregs))) | |
5998 | break; | |
5999 | r = 0; | |
6000 | break; | |
6001 | } | |
6002 | case KVM_SET_DEBUGREGS: { | |
6003 | struct kvm_debugregs dbgregs; | |
6004 | ||
6005 | r = -EFAULT; | |
6006 | if (copy_from_user(&dbgregs, argp, | |
6007 | sizeof(struct kvm_debugregs))) | |
6008 | break; | |
6009 | ||
6010 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
6011 | break; | |
6012 | } | |
2d5b5a66 | 6013 | case KVM_GET_XSAVE: { |
be50b206 GZ |
6014 | r = -EINVAL; |
6015 | if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) | |
6016 | break; | |
6017 | ||
254272ce | 6018 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 6019 | r = -ENOMEM; |
d1ac91d8 | 6020 | if (!u.xsave) |
2d5b5a66 SY |
6021 | break; |
6022 | ||
d1ac91d8 | 6023 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
6024 | |
6025 | r = -EFAULT; | |
d1ac91d8 | 6026 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
6027 | break; |
6028 | r = 0; | |
6029 | break; | |
6030 | } | |
6031 | case KVM_SET_XSAVE: { | |
be50b206 GZ |
6032 | int size = vcpu->arch.guest_fpu.uabi_size; |
6033 | ||
6034 | u.xsave = memdup_user(argp, size); | |
9b062471 CD |
6035 | if (IS_ERR(u.xsave)) { |
6036 | r = PTR_ERR(u.xsave); | |
6037 | goto out_nofree; | |
6038 | } | |
2d5b5a66 | 6039 | |
d1ac91d8 | 6040 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
6041 | break; |
6042 | } | |
be50b206 GZ |
6043 | |
6044 | case KVM_GET_XSAVE2: { | |
6045 | int size = vcpu->arch.guest_fpu.uabi_size; | |
6046 | ||
6047 | u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT); | |
6048 | r = -ENOMEM; | |
6049 | if (!u.xsave) | |
6050 | break; | |
6051 | ||
6052 | kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); | |
6053 | ||
6054 | r = -EFAULT; | |
6055 | if (copy_to_user(argp, u.xsave, size)) | |
6056 | break; | |
6057 | ||
6058 | r = 0; | |
6059 | break; | |
6060 | } | |
6061 | ||
2d5b5a66 | 6062 | case KVM_GET_XCRS: { |
254272ce | 6063 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 6064 | r = -ENOMEM; |
d1ac91d8 | 6065 | if (!u.xcrs) |
2d5b5a66 SY |
6066 | break; |
6067 | ||
d1ac91d8 | 6068 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
6069 | |
6070 | r = -EFAULT; | |
d1ac91d8 | 6071 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
6072 | sizeof(struct kvm_xcrs))) |
6073 | break; | |
6074 | r = 0; | |
6075 | break; | |
6076 | } | |
6077 | case KVM_SET_XCRS: { | |
ff5c2c03 | 6078 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
6079 | if (IS_ERR(u.xcrs)) { |
6080 | r = PTR_ERR(u.xcrs); | |
6081 | goto out_nofree; | |
6082 | } | |
2d5b5a66 | 6083 | |
d1ac91d8 | 6084 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
6085 | break; |
6086 | } | |
92a1f12d JR |
6087 | case KVM_SET_TSC_KHZ: { |
6088 | u32 user_tsc_khz; | |
6089 | ||
6090 | r = -EINVAL; | |
92a1f12d JR |
6091 | user_tsc_khz = (u32)arg; |
6092 | ||
938c8745 SC |
6093 | if (kvm_caps.has_tsc_control && |
6094 | user_tsc_khz >= kvm_caps.max_guest_tsc_khz) | |
92a1f12d JR |
6095 | goto out; |
6096 | ||
cc578287 ZA |
6097 | if (user_tsc_khz == 0) |
6098 | user_tsc_khz = tsc_khz; | |
6099 | ||
381d585c HZ |
6100 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
6101 | r = 0; | |
92a1f12d | 6102 | |
92a1f12d JR |
6103 | goto out; |
6104 | } | |
6105 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 6106 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
6107 | goto out; |
6108 | } | |
1c0b28c2 EM |
6109 | case KVM_KVMCLOCK_CTRL: { |
6110 | r = kvm_set_guest_paused(vcpu); | |
6111 | goto out; | |
6112 | } | |
5c919412 AS |
6113 | case KVM_ENABLE_CAP: { |
6114 | struct kvm_enable_cap cap; | |
6115 | ||
6116 | r = -EFAULT; | |
6117 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
6118 | goto out; | |
6119 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
6120 | break; | |
6121 | } | |
8fcc4b59 JM |
6122 | case KVM_GET_NESTED_STATE: { |
6123 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
6124 | u32 user_data_size; | |
6125 | ||
6126 | r = -EINVAL; | |
33b22172 | 6127 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
6128 | break; |
6129 | ||
6130 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 6131 | r = -EFAULT; |
8fcc4b59 | 6132 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 6133 | break; |
8fcc4b59 | 6134 | |
33b22172 PB |
6135 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
6136 | user_data_size); | |
8fcc4b59 | 6137 | if (r < 0) |
26b471c7 | 6138 | break; |
8fcc4b59 JM |
6139 | |
6140 | if (r > user_data_size) { | |
6141 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
6142 | r = -EFAULT; |
6143 | else | |
6144 | r = -E2BIG; | |
6145 | break; | |
8fcc4b59 | 6146 | } |
26b471c7 | 6147 | |
8fcc4b59 JM |
6148 | r = 0; |
6149 | break; | |
6150 | } | |
6151 | case KVM_SET_NESTED_STATE: { | |
6152 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
6153 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 6154 | int idx; |
8fcc4b59 JM |
6155 | |
6156 | r = -EINVAL; | |
33b22172 | 6157 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
6158 | break; |
6159 | ||
26b471c7 | 6160 | r = -EFAULT; |
8fcc4b59 | 6161 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 6162 | break; |
8fcc4b59 | 6163 | |
26b471c7 | 6164 | r = -EINVAL; |
8fcc4b59 | 6165 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 6166 | break; |
8fcc4b59 JM |
6167 | |
6168 | if (kvm_state.flags & | |
8cab6507 | 6169 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
6170 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
6171 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 6172 | break; |
8fcc4b59 JM |
6173 | |
6174 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
6175 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
6176 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 6177 | break; |
8fcc4b59 | 6178 | |
ad5996d9 | 6179 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 6180 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 6181 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
6182 | break; |
6183 | } | |
b4f69df0 | 6184 | #ifdef CONFIG_KVM_HYPERV |
c21d54f0 VK |
6185 | case KVM_GET_SUPPORTED_HV_CPUID: |
6186 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 6187 | break; |
b4f69df0 | 6188 | #endif |
b59b153d | 6189 | #ifdef CONFIG_KVM_XEN |
3e324615 DW |
6190 | case KVM_XEN_VCPU_GET_ATTR: { |
6191 | struct kvm_xen_vcpu_attr xva; | |
6192 | ||
6193 | r = -EFAULT; | |
6194 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
6195 | goto out; | |
6196 | r = kvm_xen_vcpu_get_attr(vcpu, &xva); | |
6197 | if (!r && copy_to_user(argp, &xva, sizeof(xva))) | |
6198 | r = -EFAULT; | |
6199 | break; | |
6200 | } | |
6201 | case KVM_XEN_VCPU_SET_ATTR: { | |
6202 | struct kvm_xen_vcpu_attr xva; | |
6203 | ||
6204 | r = -EFAULT; | |
6205 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
6206 | goto out; | |
6207 | r = kvm_xen_vcpu_set_attr(vcpu, &xva); | |
6208 | break; | |
6209 | } | |
b59b153d | 6210 | #endif |
6dba9403 ML |
6211 | case KVM_GET_SREGS2: { |
6212 | u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); | |
6213 | r = -ENOMEM; | |
6214 | if (!u.sregs2) | |
6215 | goto out; | |
6216 | __get_sregs2(vcpu, u.sregs2); | |
6217 | r = -EFAULT; | |
6218 | if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) | |
6219 | goto out; | |
6220 | r = 0; | |
6221 | break; | |
6222 | } | |
6223 | case KVM_SET_SREGS2: { | |
6224 | u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); | |
6225 | if (IS_ERR(u.sregs2)) { | |
6226 | r = PTR_ERR(u.sregs2); | |
6227 | u.sregs2 = NULL; | |
6228 | goto out; | |
6229 | } | |
6230 | r = __set_sregs2(vcpu, u.sregs2); | |
6231 | break; | |
6232 | } | |
828ca896 OU |
6233 | case KVM_HAS_DEVICE_ATTR: |
6234 | case KVM_GET_DEVICE_ATTR: | |
6235 | case KVM_SET_DEVICE_ATTR: | |
6236 | r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); | |
6237 | break; | |
313a3dc7 CO |
6238 | default: |
6239 | r = -EINVAL; | |
6240 | } | |
6241 | out: | |
d1ac91d8 | 6242 | kfree(u.buffer); |
9b062471 CD |
6243 | out_nofree: |
6244 | vcpu_put(vcpu); | |
313a3dc7 CO |
6245 | return r; |
6246 | } | |
6247 | ||
1499fa80 | 6248 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
6249 | { |
6250 | return VM_FAULT_SIGBUS; | |
6251 | } | |
6252 | ||
1fe779f8 CO |
6253 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
6254 | { | |
6255 | int ret; | |
6256 | ||
6257 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 6258 | return -EINVAL; |
b3646477 | 6259 | ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); |
1fe779f8 CO |
6260 | return ret; |
6261 | } | |
6262 | ||
b927a3ce SY |
6263 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
6264 | u64 ident_addr) | |
6265 | { | |
b3646477 | 6266 | return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); |
b927a3ce SY |
6267 | } |
6268 | ||
1fe779f8 | 6269 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 6270 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
6271 | { |
6272 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
6273 | return -EINVAL; | |
6274 | ||
79fac95e | 6275 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
6276 | |
6277 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 6278 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 6279 | |
79fac95e | 6280 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
6281 | return 0; |
6282 | } | |
6283 | ||
1fe779f8 CO |
6284 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
6285 | { | |
90bca052 | 6286 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
6287 | int r; |
6288 | ||
6289 | r = 0; | |
6290 | switch (chip->chip_id) { | |
6291 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 6292 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
6293 | sizeof(struct kvm_pic_state)); |
6294 | break; | |
6295 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 6296 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
6297 | sizeof(struct kvm_pic_state)); |
6298 | break; | |
6299 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 6300 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
6301 | break; |
6302 | default: | |
6303 | r = -EINVAL; | |
6304 | break; | |
6305 | } | |
6306 | return r; | |
6307 | } | |
6308 | ||
6309 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
6310 | { | |
90bca052 | 6311 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
6312 | int r; |
6313 | ||
6314 | r = 0; | |
6315 | switch (chip->chip_id) { | |
6316 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
6317 | spin_lock(&pic->lock); |
6318 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 6319 | sizeof(struct kvm_pic_state)); |
90bca052 | 6320 | spin_unlock(&pic->lock); |
1fe779f8 CO |
6321 | break; |
6322 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
6323 | spin_lock(&pic->lock); |
6324 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 6325 | sizeof(struct kvm_pic_state)); |
90bca052 | 6326 | spin_unlock(&pic->lock); |
1fe779f8 CO |
6327 | break; |
6328 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 6329 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
6330 | break; |
6331 | default: | |
6332 | r = -EINVAL; | |
6333 | break; | |
6334 | } | |
90bca052 | 6335 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
6336 | return r; |
6337 | } | |
6338 | ||
e0f63cb9 SY |
6339 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
6340 | { | |
34f3941c RK |
6341 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
6342 | ||
6343 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
6344 | ||
6345 | mutex_lock(&kps->lock); | |
6346 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
6347 | mutex_unlock(&kps->lock); | |
2da29bcc | 6348 | return 0; |
e0f63cb9 SY |
6349 | } |
6350 | ||
6351 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
6352 | { | |
0185604c | 6353 | int i; |
09edea72 RK |
6354 | struct kvm_pit *pit = kvm->arch.vpit; |
6355 | ||
6356 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 6357 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 6358 | for (i = 0; i < 3; i++) |
09edea72 RK |
6359 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
6360 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 6361 | return 0; |
e9f42757 BK |
6362 | } |
6363 | ||
6364 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
6365 | { | |
e9f42757 BK |
6366 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
6367 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
6368 | sizeof(ps->channels)); | |
6369 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
6370 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 6371 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 6372 | return 0; |
e9f42757 BK |
6373 | } |
6374 | ||
6375 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
6376 | { | |
2da29bcc | 6377 | int start = 0; |
0185604c | 6378 | int i; |
e9f42757 | 6379 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
6380 | struct kvm_pit *pit = kvm->arch.vpit; |
6381 | ||
6382 | mutex_lock(&pit->pit_state.lock); | |
6383 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
6384 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
6385 | if (!prev_legacy && cur_legacy) | |
6386 | start = 1; | |
09edea72 RK |
6387 | memcpy(&pit->pit_state.channels, &ps->channels, |
6388 | sizeof(pit->pit_state.channels)); | |
6389 | pit->pit_state.flags = ps->flags; | |
0185604c | 6390 | for (i = 0; i < 3; i++) |
09edea72 | 6391 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 6392 | start && i == 0); |
09edea72 | 6393 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 6394 | return 0; |
e0f63cb9 SY |
6395 | } |
6396 | ||
52d939a0 MT |
6397 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
6398 | struct kvm_reinject_control *control) | |
6399 | { | |
71474e2f RK |
6400 | struct kvm_pit *pit = kvm->arch.vpit; |
6401 | ||
71474e2f RK |
6402 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
6403 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
6404 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
6405 | */ | |
6406 | mutex_lock(&pit->pit_state.lock); | |
6407 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
6408 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 6409 | |
52d939a0 MT |
6410 | return 0; |
6411 | } | |
6412 | ||
0dff0846 | 6413 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 6414 | { |
a018eba5 | 6415 | |
88178fd4 | 6416 | /* |
a018eba5 SC |
6417 | * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called |
6418 | * before reporting dirty_bitmap to userspace. KVM flushes the buffers | |
6419 | * on all VM-Exits, thus we only need to kick running vCPUs to force a | |
6420 | * VM-Exit. | |
88178fd4 | 6421 | */ |
a018eba5 | 6422 | struct kvm_vcpu *vcpu; |
46808a4c | 6423 | unsigned long i; |
a018eba5 | 6424 | |
3d30bfcb DM |
6425 | if (!kvm_x86_ops.cpu_dirty_log_size) |
6426 | return; | |
6427 | ||
a018eba5 SC |
6428 | kvm_for_each_vcpu(i, vcpu, kvm) |
6429 | kvm_vcpu_kick(vcpu); | |
5bb064dc ZX |
6430 | } |
6431 | ||
aa2fbe6d YZ |
6432 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
6433 | bool line_status) | |
23d43cf9 CD |
6434 | { |
6435 | if (!irqchip_in_kernel(kvm)) | |
6436 | return -ENXIO; | |
6437 | ||
6438 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
6439 | irq_event->irq, irq_event->level, |
6440 | line_status); | |
23d43cf9 CD |
6441 | return 0; |
6442 | } | |
6443 | ||
e5d83c74 PB |
6444 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
6445 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
6446 | { |
6447 | int r; | |
6448 | ||
6449 | if (cap->flags) | |
6450 | return -EINVAL; | |
6451 | ||
6452 | switch (cap->cap) { | |
6d849191 OU |
6453 | case KVM_CAP_DISABLE_QUIRKS2: |
6454 | r = -EINVAL; | |
6455 | if (cap->args[0] & ~KVM_X86_VALID_QUIRKS) | |
6456 | break; | |
6457 | fallthrough; | |
90de4a18 NA |
6458 | case KVM_CAP_DISABLE_QUIRKS: |
6459 | kvm->arch.disabled_quirks = cap->args[0]; | |
6460 | r = 0; | |
6461 | break; | |
49df6397 SR |
6462 | case KVM_CAP_SPLIT_IRQCHIP: { |
6463 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
6464 | r = -EINVAL; |
6465 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
6466 | goto split_irqchip_unlock; | |
49df6397 SR |
6467 | r = -EEXIST; |
6468 | if (irqchip_in_kernel(kvm)) | |
6469 | goto split_irqchip_unlock; | |
557abc40 | 6470 | if (kvm->created_vcpus) |
49df6397 SR |
6471 | goto split_irqchip_unlock; |
6472 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 6473 | if (r) |
49df6397 SR |
6474 | goto split_irqchip_unlock; |
6475 | /* Pairs with irqchip_in_kernel. */ | |
6476 | smp_wmb(); | |
49776faf | 6477 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 6478 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
320af55a | 6479 | kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); |
49df6397 SR |
6480 | r = 0; |
6481 | split_irqchip_unlock: | |
6482 | mutex_unlock(&kvm->lock); | |
6483 | break; | |
6484 | } | |
37131313 RK |
6485 | case KVM_CAP_X2APIC_API: |
6486 | r = -EINVAL; | |
6487 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
6488 | break; | |
6489 | ||
6490 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
6491 | kvm->arch.x2apic_format = true; | |
c519265f RK |
6492 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
6493 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
6494 | |
6495 | r = 0; | |
6496 | break; | |
4d5422ce WL |
6497 | case KVM_CAP_X86_DISABLE_EXITS: |
6498 | r = -EINVAL; | |
6499 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
6500 | break; | |
6501 | ||
b31c114b WL |
6502 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
6503 | kvm->arch.pause_in_guest = true; | |
6f0f2d5e TL |
6504 | |
6505 | #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \ | |
6506 | "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests." | |
6507 | ||
6508 | if (!mitigate_smt_rsb) { | |
6509 | if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() && | |
6510 | (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE)) | |
6511 | pr_warn_once(SMT_RSB_MSG); | |
6512 | ||
6513 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
6514 | kvm_can_mwait_in_guest()) | |
6515 | kvm->arch.mwait_in_guest = true; | |
6516 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) | |
6517 | kvm->arch.hlt_in_guest = true; | |
6518 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) | |
6519 | kvm->arch.cstate_in_guest = true; | |
6520 | } | |
6521 | ||
4d5422ce WL |
6522 | r = 0; |
6523 | break; | |
6fbbde9a DS |
6524 | case KVM_CAP_MSR_PLATFORM_INFO: |
6525 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
6526 | r = 0; | |
c4f55198 JM |
6527 | break; |
6528 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
6529 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
6530 | r = 0; | |
6fbbde9a | 6531 | break; |
ed235117 CQ |
6532 | case KVM_CAP_X86_TRIPLE_FAULT_EVENT: |
6533 | kvm->arch.triple_fault_event = cap->args[0]; | |
6534 | r = 0; | |
6535 | break; | |
1ae09954 | 6536 | case KVM_CAP_X86_USER_SPACE_MSR: |
cf5029d5 | 6537 | r = -EINVAL; |
db205f7e | 6538 | if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK) |
cf5029d5 | 6539 | break; |
1ae09954 AG |
6540 | kvm->arch.user_space_msr_mask = cap->args[0]; |
6541 | r = 0; | |
6542 | break; | |
fe6b6bc8 CQ |
6543 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
6544 | r = -EINVAL; | |
6545 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
6546 | break; | |
6547 | ||
6548 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
6549 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
6550 | break; | |
6551 | ||
938c8745 | 6552 | if (kvm_caps.has_bus_lock_exit && |
fe6b6bc8 CQ |
6553 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) |
6554 | kvm->arch.bus_lock_detection_enabled = true; | |
6555 | r = 0; | |
6556 | break; | |
fe7e9488 SC |
6557 | #ifdef CONFIG_X86_SGX_KVM |
6558 | case KVM_CAP_SGX_ATTRIBUTE: { | |
6559 | unsigned long allowed_attributes = 0; | |
6560 | ||
6561 | r = sgx_set_attribute(&allowed_attributes, cap->args[0]); | |
6562 | if (r) | |
6563 | break; | |
6564 | ||
6565 | /* KVM only supports the PROVISIONKEY privileged attribute. */ | |
6566 | if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && | |
6567 | !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) | |
6568 | kvm->arch.sgx_provisioning_allowed = true; | |
6569 | else | |
6570 | r = -EINVAL; | |
6571 | break; | |
6572 | } | |
6573 | #endif | |
54526d1f NT |
6574 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
6575 | r = -EINVAL; | |
7ad02ef0 SC |
6576 | if (!kvm_x86_ops.vm_copy_enc_context_from) |
6577 | break; | |
6578 | ||
6579 | r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]); | |
6580 | break; | |
b5663931 PG |
6581 | case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: |
6582 | r = -EINVAL; | |
7ad02ef0 SC |
6583 | if (!kvm_x86_ops.vm_move_enc_context_from) |
6584 | break; | |
6585 | ||
6586 | r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]); | |
6587 | break; | |
0dbb1123 AK |
6588 | case KVM_CAP_EXIT_HYPERCALL: |
6589 | if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { | |
6590 | r = -EINVAL; | |
6591 | break; | |
6592 | } | |
6593 | kvm->arch.hypercall_exit_enabled = cap->args[0]; | |
6594 | r = 0; | |
6595 | break; | |
19238e75 AL |
6596 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
6597 | r = -EINVAL; | |
6598 | if (cap->args[0] & ~1) | |
6599 | break; | |
6600 | kvm->arch.exit_on_emulation_error = cap->args[0]; | |
6601 | r = 0; | |
6602 | break; | |
ba7bb663 DD |
6603 | case KVM_CAP_PMU_CAPABILITY: |
6604 | r = -EINVAL; | |
6605 | if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK)) | |
6606 | break; | |
6607 | ||
6608 | mutex_lock(&kvm->lock); | |
6609 | if (!kvm->created_vcpus) { | |
6610 | kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); | |
6611 | r = 0; | |
6612 | } | |
6613 | mutex_unlock(&kvm->lock); | |
6614 | break; | |
35875316 ZG |
6615 | case KVM_CAP_MAX_VCPU_ID: |
6616 | r = -EINVAL; | |
6617 | if (cap->args[0] > KVM_MAX_VCPU_IDS) | |
6618 | break; | |
6619 | ||
6620 | mutex_lock(&kvm->lock); | |
6621 | if (kvm->arch.max_vcpu_ids == cap->args[0]) { | |
6622 | r = 0; | |
6623 | } else if (!kvm->arch.max_vcpu_ids) { | |
6624 | kvm->arch.max_vcpu_ids = cap->args[0]; | |
6625 | r = 0; | |
6626 | } | |
6627 | mutex_unlock(&kvm->lock); | |
6628 | break; | |
2f4073e0 TX |
6629 | case KVM_CAP_X86_NOTIFY_VMEXIT: |
6630 | r = -EINVAL; | |
6631 | if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS) | |
6632 | break; | |
6633 | if (!kvm_caps.has_notify_vmexit) | |
6634 | break; | |
6635 | if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED)) | |
6636 | break; | |
6637 | mutex_lock(&kvm->lock); | |
6638 | if (!kvm->created_vcpus) { | |
6639 | kvm->arch.notify_window = cap->args[0] >> 32; | |
6640 | kvm->arch.notify_vmexit_flags = (u32)cap->args[0]; | |
6641 | r = 0; | |
6642 | } | |
6643 | mutex_unlock(&kvm->lock); | |
6644 | break; | |
084cc29f BG |
6645 | case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: |
6646 | r = -EINVAL; | |
6647 | ||
6648 | /* | |
6649 | * Since the risk of disabling NX hugepages is a guest crashing | |
6650 | * the system, ensure the userspace process has permission to | |
6651 | * reboot the system. | |
6652 | * | |
6653 | * Note that unlike the reboot() syscall, the process must have | |
6654 | * this capability in the root namespace because exposing | |
6655 | * /dev/kvm into a container does not limit the scope of the | |
6656 | * iTLB multihit bug to that container. In other words, | |
6657 | * this must use capable(), not ns_capable(). | |
6658 | */ | |
6659 | if (!capable(CAP_SYS_BOOT)) { | |
6660 | r = -EPERM; | |
6661 | break; | |
6662 | } | |
6663 | ||
6664 | if (cap->args[0]) | |
6665 | break; | |
6666 | ||
6667 | mutex_lock(&kvm->lock); | |
6668 | if (!kvm->created_vcpus) { | |
6669 | kvm->arch.disable_nx_huge_pages = true; | |
6670 | r = 0; | |
6671 | } | |
6672 | mutex_unlock(&kvm->lock); | |
6673 | break; | |
90de4a18 NA |
6674 | default: |
6675 | r = -EINVAL; | |
6676 | break; | |
6677 | } | |
6678 | return r; | |
6679 | } | |
6680 | ||
b318e8de SC |
6681 | static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) |
6682 | { | |
6683 | struct kvm_x86_msr_filter *msr_filter; | |
6684 | ||
6685 | msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); | |
6686 | if (!msr_filter) | |
6687 | return NULL; | |
6688 | ||
6689 | msr_filter->default_allow = default_allow; | |
6690 | return msr_filter; | |
6691 | } | |
6692 | ||
6693 | static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) | |
1a155254 AG |
6694 | { |
6695 | u32 i; | |
1a155254 | 6696 | |
b318e8de SC |
6697 | if (!msr_filter) |
6698 | return; | |
6699 | ||
6700 | for (i = 0; i < msr_filter->count; i++) | |
6701 | kfree(msr_filter->ranges[i].bitmap); | |
1a155254 | 6702 | |
b318e8de | 6703 | kfree(msr_filter); |
1a155254 AG |
6704 | } |
6705 | ||
b318e8de SC |
6706 | static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, |
6707 | struct kvm_msr_filter_range *user_range) | |
1a155254 | 6708 | { |
392a5324 | 6709 | unsigned long *bitmap; |
1a155254 | 6710 | size_t bitmap_size; |
1a155254 AG |
6711 | |
6712 | if (!user_range->nmsrs) | |
6713 | return 0; | |
6714 | ||
8aff460f | 6715 | if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK) |
aca35288 SC |
6716 | return -EINVAL; |
6717 | ||
6718 | if (!user_range->flags) | |
6719 | return -EINVAL; | |
6720 | ||
1a155254 AG |
6721 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); |
6722 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
6723 | return -EINVAL; | |
6724 | ||
6725 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
6726 | if (IS_ERR(bitmap)) | |
6727 | return PTR_ERR(bitmap); | |
6728 | ||
aca35288 | 6729 | msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { |
1a155254 AG |
6730 | .flags = user_range->flags, |
6731 | .base = user_range->base, | |
6732 | .nmsrs = user_range->nmsrs, | |
6733 | .bitmap = bitmap, | |
6734 | }; | |
6735 | ||
b318e8de | 6736 | msr_filter->count++; |
1a155254 | 6737 | return 0; |
1a155254 AG |
6738 | } |
6739 | ||
2e3272bc AG |
6740 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, |
6741 | struct kvm_msr_filter *filter) | |
1a155254 | 6742 | { |
b318e8de | 6743 | struct kvm_x86_msr_filter *new_filter, *old_filter; |
1a155254 | 6744 | bool default_allow; |
043248b3 | 6745 | bool empty = true; |
4559e6cf | 6746 | int r; |
1a155254 AG |
6747 | u32 i; |
6748 | ||
c1340fe3 | 6749 | if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK) |
cf5029d5 AL |
6750 | return -EINVAL; |
6751 | ||
2e3272bc AG |
6752 | for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) |
6753 | empty &= !filter->ranges[i].nmsrs; | |
1a155254 | 6754 | |
2e3272bc | 6755 | default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY); |
043248b3 PB |
6756 | if (empty && !default_allow) |
6757 | return -EINVAL; | |
6758 | ||
b318e8de SC |
6759 | new_filter = kvm_alloc_msr_filter(default_allow); |
6760 | if (!new_filter) | |
6761 | return -ENOMEM; | |
1a155254 | 6762 | |
2e3272bc AG |
6763 | for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) { |
6764 | r = kvm_add_msr_filter(new_filter, &filter->ranges[i]); | |
b318e8de SC |
6765 | if (r) { |
6766 | kvm_free_msr_filter(new_filter); | |
6767 | return r; | |
6768 | } | |
1a155254 AG |
6769 | } |
6770 | ||
b318e8de | 6771 | mutex_lock(&kvm->lock); |
1fdefb8b ML |
6772 | old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter, |
6773 | mutex_is_locked(&kvm->lock)); | |
708f799d | 6774 | mutex_unlock(&kvm->lock); |
b318e8de SC |
6775 | synchronize_srcu(&kvm->srcu); |
6776 | ||
6777 | kvm_free_msr_filter(old_filter); | |
6778 | ||
1a155254 | 6779 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); |
1a155254 | 6780 | |
b318e8de | 6781 | return 0; |
1a155254 AG |
6782 | } |
6783 | ||
1739c701 AG |
6784 | #ifdef CONFIG_KVM_COMPAT |
6785 | /* for KVM_X86_SET_MSR_FILTER */ | |
6786 | struct kvm_msr_filter_range_compat { | |
6787 | __u32 flags; | |
6788 | __u32 nmsrs; | |
6789 | __u32 base; | |
6790 | __u32 bitmap; | |
6791 | }; | |
6792 | ||
6793 | struct kvm_msr_filter_compat { | |
6794 | __u32 flags; | |
6795 | struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES]; | |
6796 | }; | |
6797 | ||
6798 | #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat) | |
6799 | ||
6800 | long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl, | |
6801 | unsigned long arg) | |
6802 | { | |
6803 | void __user *argp = (void __user *)arg; | |
6804 | struct kvm *kvm = filp->private_data; | |
6805 | long r = -ENOTTY; | |
6806 | ||
6807 | switch (ioctl) { | |
6808 | case KVM_X86_SET_MSR_FILTER_COMPAT: { | |
6809 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
6810 | struct kvm_msr_filter_compat filter_compat; | |
6811 | struct kvm_msr_filter filter; | |
6812 | int i; | |
6813 | ||
6814 | if (copy_from_user(&filter_compat, user_msr_filter, | |
6815 | sizeof(filter_compat))) | |
6816 | return -EFAULT; | |
6817 | ||
6818 | filter.flags = filter_compat.flags; | |
6819 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { | |
6820 | struct kvm_msr_filter_range_compat *cr; | |
6821 | ||
6822 | cr = &filter_compat.ranges[i]; | |
6823 | filter.ranges[i] = (struct kvm_msr_filter_range) { | |
6824 | .flags = cr->flags, | |
6825 | .nmsrs = cr->nmsrs, | |
6826 | .base = cr->base, | |
6827 | .bitmap = (__u8 *)(ulong)cr->bitmap, | |
6828 | }; | |
6829 | } | |
6830 | ||
6831 | r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); | |
6832 | break; | |
6833 | } | |
6834 | } | |
6835 | ||
6836 | return r; | |
6837 | } | |
6838 | #endif | |
6839 | ||
7d62874f SS |
6840 | #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER |
6841 | static int kvm_arch_suspend_notifier(struct kvm *kvm) | |
6842 | { | |
6843 | struct kvm_vcpu *vcpu; | |
46808a4c MZ |
6844 | unsigned long i; |
6845 | int ret = 0; | |
7d62874f SS |
6846 | |
6847 | mutex_lock(&kvm->lock); | |
6848 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
916d3608 | 6849 | if (!vcpu->arch.pv_time.active) |
7d62874f SS |
6850 | continue; |
6851 | ||
6852 | ret = kvm_set_guest_paused(vcpu); | |
6853 | if (ret) { | |
6854 | kvm_err("Failed to pause guest VCPU%d: %d\n", | |
6855 | vcpu->vcpu_id, ret); | |
6856 | break; | |
6857 | } | |
6858 | } | |
6859 | mutex_unlock(&kvm->lock); | |
6860 | ||
6861 | return ret ? NOTIFY_BAD : NOTIFY_DONE; | |
6862 | } | |
6863 | ||
6864 | int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) | |
6865 | { | |
6866 | switch (state) { | |
6867 | case PM_HIBERNATION_PREPARE: | |
6868 | case PM_SUSPEND_PREPARE: | |
6869 | return kvm_arch_suspend_notifier(kvm); | |
6870 | } | |
6871 | ||
6872 | return NOTIFY_DONE; | |
6873 | } | |
6874 | #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ | |
6875 | ||
45e6c2fa PB |
6876 | static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) |
6877 | { | |
869b4421 | 6878 | struct kvm_clock_data data = { 0 }; |
45e6c2fa | 6879 | |
55c0cefb | 6880 | get_kvmclock(kvm, &data); |
45e6c2fa PB |
6881 | if (copy_to_user(argp, &data, sizeof(data))) |
6882 | return -EFAULT; | |
6883 | ||
6884 | return 0; | |
6885 | } | |
6886 | ||
6887 | static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) | |
6888 | { | |
6889 | struct kvm_arch *ka = &kvm->arch; | |
6890 | struct kvm_clock_data data; | |
c68dc1b5 | 6891 | u64 now_raw_ns; |
45e6c2fa PB |
6892 | |
6893 | if (copy_from_user(&data, argp, sizeof(data))) | |
6894 | return -EFAULT; | |
6895 | ||
c68dc1b5 OU |
6896 | /* |
6897 | * Only KVM_CLOCK_REALTIME is used, but allow passing the | |
6898 | * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. | |
6899 | */ | |
6900 | if (data.flags & ~KVM_CLOCK_VALID_FLAGS) | |
45e6c2fa PB |
6901 | return -EINVAL; |
6902 | ||
42dcbe7d | 6903 | kvm_hv_request_tsc_page_update(kvm); |
45e6c2fa PB |
6904 | kvm_start_pvclock_update(kvm); |
6905 | pvclock_update_vm_gtod_copy(kvm); | |
6906 | ||
6907 | /* | |
6908 | * This pairs with kvm_guest_time_update(): when masterclock is | |
6909 | * in use, we use master_kernel_ns + kvmclock_offset to set | |
6910 | * unsigned 'system_time' so if we use get_kvmclock_ns() (which | |
6911 | * is slightly ahead) here we risk going negative on unsigned | |
6912 | * 'system_time' when 'data.clock' is very small. | |
6913 | */ | |
c68dc1b5 OU |
6914 | if (data.flags & KVM_CLOCK_REALTIME) { |
6915 | u64 now_real_ns = ktime_get_real_ns(); | |
6916 | ||
6917 | /* | |
6918 | * Avoid stepping the kvmclock backwards. | |
6919 | */ | |
6920 | if (now_real_ns > data.realtime) | |
6921 | data.clock += now_real_ns - data.realtime; | |
6922 | } | |
6923 | ||
6924 | if (ka->use_master_clock) | |
6925 | now_raw_ns = ka->master_kernel_ns; | |
45e6c2fa | 6926 | else |
c68dc1b5 OU |
6927 | now_raw_ns = get_kvmclock_base_ns(); |
6928 | ka->kvmclock_offset = data.clock - now_raw_ns; | |
45e6c2fa PB |
6929 | kvm_end_pvclock_update(kvm); |
6930 | return 0; | |
6931 | } | |
6932 | ||
d8708b80 | 6933 | int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) |
1fe779f8 CO |
6934 | { |
6935 | struct kvm *kvm = filp->private_data; | |
6936 | void __user *argp = (void __user *)arg; | |
367e1319 | 6937 | int r = -ENOTTY; |
f0d66275 DH |
6938 | /* |
6939 | * This union makes it completely explicit to gcc-3.x | |
6940 | * that these two variables' stack usage should be | |
6941 | * combined, not added together. | |
6942 | */ | |
6943 | union { | |
6944 | struct kvm_pit_state ps; | |
e9f42757 | 6945 | struct kvm_pit_state2 ps2; |
c5ff41ce | 6946 | struct kvm_pit_config pit_config; |
f0d66275 | 6947 | } u; |
1fe779f8 CO |
6948 | |
6949 | switch (ioctl) { | |
6950 | case KVM_SET_TSS_ADDR: | |
6951 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 6952 | break; |
b927a3ce SY |
6953 | case KVM_SET_IDENTITY_MAP_ADDR: { |
6954 | u64 ident_addr; | |
6955 | ||
1af1ac91 DH |
6956 | mutex_lock(&kvm->lock); |
6957 | r = -EINVAL; | |
6958 | if (kvm->created_vcpus) | |
6959 | goto set_identity_unlock; | |
b927a3ce | 6960 | r = -EFAULT; |
0e96f31e | 6961 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 6962 | goto set_identity_unlock; |
b927a3ce | 6963 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
6964 | set_identity_unlock: |
6965 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
6966 | break; |
6967 | } | |
1fe779f8 CO |
6968 | case KVM_SET_NR_MMU_PAGES: |
6969 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 | 6970 | break; |
3ddea128 | 6971 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 6972 | mutex_lock(&kvm->lock); |
09941366 | 6973 | |
3ddea128 | 6974 | r = -EEXIST; |
35e6eaa3 | 6975 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 6976 | goto create_irqchip_unlock; |
09941366 | 6977 | |
3e515705 | 6978 | r = -EINVAL; |
557abc40 | 6979 | if (kvm->created_vcpus) |
3e515705 | 6980 | goto create_irqchip_unlock; |
09941366 RK |
6981 | |
6982 | r = kvm_pic_init(kvm); | |
6983 | if (r) | |
3ddea128 | 6984 | goto create_irqchip_unlock; |
09941366 RK |
6985 | |
6986 | r = kvm_ioapic_init(kvm); | |
6987 | if (r) { | |
09941366 | 6988 | kvm_pic_destroy(kvm); |
3ddea128 | 6989 | goto create_irqchip_unlock; |
09941366 RK |
6990 | } |
6991 | ||
399ec807 AK |
6992 | r = kvm_setup_default_irq_routing(kvm); |
6993 | if (r) { | |
72bb2fcd | 6994 | kvm_ioapic_destroy(kvm); |
09941366 | 6995 | kvm_pic_destroy(kvm); |
71ba994c | 6996 | goto create_irqchip_unlock; |
399ec807 | 6997 | } |
49776faf | 6998 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 6999 | smp_wmb(); |
49776faf | 7000 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
320af55a | 7001 | kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); |
3ddea128 MT |
7002 | create_irqchip_unlock: |
7003 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 7004 | break; |
3ddea128 | 7005 | } |
7837699f | 7006 | case KVM_CREATE_PIT: |
c5ff41ce JK |
7007 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
7008 | goto create_pit; | |
7009 | case KVM_CREATE_PIT2: | |
7010 | r = -EFAULT; | |
7011 | if (copy_from_user(&u.pit_config, argp, | |
7012 | sizeof(struct kvm_pit_config))) | |
7013 | goto out; | |
7014 | create_pit: | |
250715a6 | 7015 | mutex_lock(&kvm->lock); |
269e05e4 AK |
7016 | r = -EEXIST; |
7017 | if (kvm->arch.vpit) | |
7018 | goto create_pit_unlock; | |
7837699f | 7019 | r = -ENOMEM; |
c5ff41ce | 7020 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
7021 | if (kvm->arch.vpit) |
7022 | r = 0; | |
269e05e4 | 7023 | create_pit_unlock: |
250715a6 | 7024 | mutex_unlock(&kvm->lock); |
7837699f | 7025 | break; |
1fe779f8 CO |
7026 | case KVM_GET_IRQCHIP: { |
7027 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 7028 | struct kvm_irqchip *chip; |
1fe779f8 | 7029 | |
ff5c2c03 SL |
7030 | chip = memdup_user(argp, sizeof(*chip)); |
7031 | if (IS_ERR(chip)) { | |
7032 | r = PTR_ERR(chip); | |
1fe779f8 | 7033 | goto out; |
ff5c2c03 SL |
7034 | } |
7035 | ||
1fe779f8 | 7036 | r = -ENXIO; |
826da321 | 7037 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
7038 | goto get_irqchip_out; |
7039 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 7040 | if (r) |
f0d66275 | 7041 | goto get_irqchip_out; |
1fe779f8 | 7042 | r = -EFAULT; |
0e96f31e | 7043 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 7044 | goto get_irqchip_out; |
1fe779f8 | 7045 | r = 0; |
f0d66275 DH |
7046 | get_irqchip_out: |
7047 | kfree(chip); | |
1fe779f8 CO |
7048 | break; |
7049 | } | |
7050 | case KVM_SET_IRQCHIP: { | |
7051 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 7052 | struct kvm_irqchip *chip; |
1fe779f8 | 7053 | |
ff5c2c03 SL |
7054 | chip = memdup_user(argp, sizeof(*chip)); |
7055 | if (IS_ERR(chip)) { | |
7056 | r = PTR_ERR(chip); | |
1fe779f8 | 7057 | goto out; |
ff5c2c03 SL |
7058 | } |
7059 | ||
1fe779f8 | 7060 | r = -ENXIO; |
826da321 | 7061 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
7062 | goto set_irqchip_out; |
7063 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
7064 | set_irqchip_out: |
7065 | kfree(chip); | |
1fe779f8 CO |
7066 | break; |
7067 | } | |
e0f63cb9 | 7068 | case KVM_GET_PIT: { |
e0f63cb9 | 7069 | r = -EFAULT; |
f0d66275 | 7070 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
7071 | goto out; |
7072 | r = -ENXIO; | |
7073 | if (!kvm->arch.vpit) | |
7074 | goto out; | |
f0d66275 | 7075 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
7076 | if (r) |
7077 | goto out; | |
7078 | r = -EFAULT; | |
f0d66275 | 7079 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
7080 | goto out; |
7081 | r = 0; | |
7082 | break; | |
7083 | } | |
7084 | case KVM_SET_PIT: { | |
e0f63cb9 | 7085 | r = -EFAULT; |
0e96f31e | 7086 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 7087 | goto out; |
7289fdb5 | 7088 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
7089 | r = -ENXIO; |
7090 | if (!kvm->arch.vpit) | |
7289fdb5 | 7091 | goto set_pit_out; |
f0d66275 | 7092 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
7093 | set_pit_out: |
7094 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
7095 | break; |
7096 | } | |
e9f42757 BK |
7097 | case KVM_GET_PIT2: { |
7098 | r = -ENXIO; | |
7099 | if (!kvm->arch.vpit) | |
7100 | goto out; | |
7101 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
7102 | if (r) | |
7103 | goto out; | |
7104 | r = -EFAULT; | |
7105 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
7106 | goto out; | |
7107 | r = 0; | |
7108 | break; | |
7109 | } | |
7110 | case KVM_SET_PIT2: { | |
7111 | r = -EFAULT; | |
7112 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
7113 | goto out; | |
7289fdb5 | 7114 | mutex_lock(&kvm->lock); |
e9f42757 BK |
7115 | r = -ENXIO; |
7116 | if (!kvm->arch.vpit) | |
7289fdb5 | 7117 | goto set_pit2_out; |
e9f42757 | 7118 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
7119 | set_pit2_out: |
7120 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
7121 | break; |
7122 | } | |
52d939a0 MT |
7123 | case KVM_REINJECT_CONTROL: { |
7124 | struct kvm_reinject_control control; | |
7125 | r = -EFAULT; | |
7126 | if (copy_from_user(&control, argp, sizeof(control))) | |
7127 | goto out; | |
cad23e72 ML |
7128 | r = -ENXIO; |
7129 | if (!kvm->arch.vpit) | |
7130 | goto out; | |
52d939a0 | 7131 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
7132 | break; |
7133 | } | |
d71ba788 PB |
7134 | case KVM_SET_BOOT_CPU_ID: |
7135 | r = 0; | |
7136 | mutex_lock(&kvm->lock); | |
557abc40 | 7137 | if (kvm->created_vcpus) |
d71ba788 PB |
7138 | r = -EBUSY; |
7139 | else | |
7140 | kvm->arch.bsp_vcpu_id = arg; | |
7141 | mutex_unlock(&kvm->lock); | |
7142 | break; | |
b59b153d | 7143 | #ifdef CONFIG_KVM_XEN |
ffde22ac | 7144 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 7145 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 7146 | r = -EFAULT; |
51776043 | 7147 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac | 7148 | goto out; |
78e9878c | 7149 | r = kvm_xen_hvm_config(kvm, &xhc); |
ffde22ac ES |
7150 | break; |
7151 | } | |
a76b9641 JM |
7152 | case KVM_XEN_HVM_GET_ATTR: { |
7153 | struct kvm_xen_hvm_attr xha; | |
7154 | ||
7155 | r = -EFAULT; | |
7156 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
ffde22ac | 7157 | goto out; |
a76b9641 JM |
7158 | r = kvm_xen_hvm_get_attr(kvm, &xha); |
7159 | if (!r && copy_to_user(argp, &xha, sizeof(xha))) | |
7160 | r = -EFAULT; | |
7161 | break; | |
7162 | } | |
7163 | case KVM_XEN_HVM_SET_ATTR: { | |
7164 | struct kvm_xen_hvm_attr xha; | |
7165 | ||
7166 | r = -EFAULT; | |
7167 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
7168 | goto out; | |
7169 | r = kvm_xen_hvm_set_attr(kvm, &xha); | |
ffde22ac ES |
7170 | break; |
7171 | } | |
35025735 DW |
7172 | case KVM_XEN_HVM_EVTCHN_SEND: { |
7173 | struct kvm_irq_routing_xen_evtchn uxe; | |
7174 | ||
7175 | r = -EFAULT; | |
7176 | if (copy_from_user(&uxe, argp, sizeof(uxe))) | |
7177 | goto out; | |
7178 | r = kvm_xen_hvm_evtchn_send(kvm, &uxe); | |
7179 | break; | |
7180 | } | |
b59b153d | 7181 | #endif |
45e6c2fa PB |
7182 | case KVM_SET_CLOCK: |
7183 | r = kvm_vm_ioctl_set_clock(kvm, argp); | |
afbcf7ab | 7184 | break; |
45e6c2fa PB |
7185 | case KVM_GET_CLOCK: |
7186 | r = kvm_vm_ioctl_get_clock(kvm, argp); | |
afbcf7ab | 7187 | break; |
ffbb61d0 DW |
7188 | case KVM_SET_TSC_KHZ: { |
7189 | u32 user_tsc_khz; | |
7190 | ||
7191 | r = -EINVAL; | |
7192 | user_tsc_khz = (u32)arg; | |
7193 | ||
938c8745 SC |
7194 | if (kvm_caps.has_tsc_control && |
7195 | user_tsc_khz >= kvm_caps.max_guest_tsc_khz) | |
ffbb61d0 DW |
7196 | goto out; |
7197 | ||
7198 | if (user_tsc_khz == 0) | |
7199 | user_tsc_khz = tsc_khz; | |
7200 | ||
7201 | WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz); | |
7202 | r = 0; | |
7203 | ||
7204 | goto out; | |
7205 | } | |
7206 | case KVM_GET_TSC_KHZ: { | |
7207 | r = READ_ONCE(kvm->arch.default_tsc_khz); | |
7208 | goto out; | |
7209 | } | |
5acc5c06 BS |
7210 | case KVM_MEMORY_ENCRYPT_OP: { |
7211 | r = -ENOTTY; | |
03d004cd SC |
7212 | if (!kvm_x86_ops.mem_enc_ioctl) |
7213 | goto out; | |
7214 | ||
7215 | r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp); | |
5acc5c06 BS |
7216 | break; |
7217 | } | |
69eaedee BS |
7218 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
7219 | struct kvm_enc_region region; | |
7220 | ||
7221 | r = -EFAULT; | |
7222 | if (copy_from_user(®ion, argp, sizeof(region))) | |
7223 | goto out; | |
7224 | ||
7225 | r = -ENOTTY; | |
03d004cd SC |
7226 | if (!kvm_x86_ops.mem_enc_register_region) |
7227 | goto out; | |
7228 | ||
7229 | r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion); | |
69eaedee BS |
7230 | break; |
7231 | } | |
7232 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
7233 | struct kvm_enc_region region; | |
7234 | ||
7235 | r = -EFAULT; | |
7236 | if (copy_from_user(®ion, argp, sizeof(region))) | |
7237 | goto out; | |
7238 | ||
7239 | r = -ENOTTY; | |
03d004cd SC |
7240 | if (!kvm_x86_ops.mem_enc_unregister_region) |
7241 | goto out; | |
7242 | ||
7243 | r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion); | |
69eaedee BS |
7244 | break; |
7245 | } | |
b4f69df0 | 7246 | #ifdef CONFIG_KVM_HYPERV |
faeb7833 RK |
7247 | case KVM_HYPERV_EVENTFD: { |
7248 | struct kvm_hyperv_eventfd hvevfd; | |
7249 | ||
7250 | r = -EFAULT; | |
7251 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
7252 | goto out; | |
7253 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
7254 | break; | |
7255 | } | |
b4f69df0 | 7256 | #endif |
66bb8a06 EH |
7257 | case KVM_SET_PMU_EVENT_FILTER: |
7258 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
7259 | break; | |
2e3272bc AG |
7260 | case KVM_X86_SET_MSR_FILTER: { |
7261 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
7262 | struct kvm_msr_filter filter; | |
7263 | ||
7264 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
7265 | return -EFAULT; | |
7266 | ||
7267 | r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); | |
1a155254 | 7268 | break; |
2e3272bc | 7269 | } |
1fe779f8 | 7270 | default: |
ad6260da | 7271 | r = -ENOTTY; |
1fe779f8 CO |
7272 | } |
7273 | out: | |
7274 | return r; | |
7275 | } | |
7276 | ||
9eb6ba31 SC |
7277 | static void kvm_probe_feature_msr(u32 msr_index) |
7278 | { | |
7279 | struct kvm_msr_entry msr = { | |
7280 | .index = msr_index, | |
7281 | }; | |
7282 | ||
7283 | if (kvm_get_msr_feature(&msr)) | |
7284 | return; | |
7285 | ||
7286 | msr_based_features[num_msr_based_features++] = msr_index; | |
7287 | } | |
7288 | ||
2374b731 | 7289 | static void kvm_probe_msr_to_save(u32 msr_index) |
043405e1 CO |
7290 | { |
7291 | u32 dummy[2]; | |
2374b731 SC |
7292 | |
7293 | if (rdmsr_safe(msr_index, &dummy[0], &dummy[1])) | |
7294 | return; | |
7295 | ||
7296 | /* | |
7297 | * Even MSRs that are valid in the host may not be exposed to guests in | |
7298 | * some cases. | |
7299 | */ | |
7300 | switch (msr_index) { | |
7301 | case MSR_IA32_BNDCFGS: | |
7302 | if (!kvm_mpx_supported()) | |
7303 | return; | |
7304 | break; | |
7305 | case MSR_TSC_AUX: | |
7306 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && | |
7307 | !kvm_cpu_cap_has(X86_FEATURE_RDPID)) | |
7308 | return; | |
7309 | break; | |
7310 | case MSR_IA32_UMWAIT_CONTROL: | |
7311 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
7312 | return; | |
7313 | break; | |
7314 | case MSR_IA32_RTIT_CTL: | |
7315 | case MSR_IA32_RTIT_STATUS: | |
7316 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) | |
7317 | return; | |
7318 | break; | |
7319 | case MSR_IA32_RTIT_CR3_MATCH: | |
7320 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || | |
7321 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) | |
7322 | return; | |
7323 | break; | |
7324 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
7325 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7326 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || | |
7327 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && | |
7328 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
7329 | return; | |
7330 | break; | |
7331 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: | |
7332 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || | |
7333 | (msr_index - MSR_IA32_RTIT_ADDR0_A >= | |
7334 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)) | |
7335 | return; | |
7336 | break; | |
7337 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX: | |
7338 | if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >= | |
7339 | kvm_pmu_cap.num_counters_gp) | |
7340 | return; | |
7341 | break; | |
7342 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX: | |
7343 | if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >= | |
7344 | kvm_pmu_cap.num_counters_gp) | |
7345 | return; | |
7346 | break; | |
e33b6d79 LX |
7347 | case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX: |
7348 | if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >= | |
7349 | kvm_pmu_cap.num_counters_fixed) | |
7350 | return; | |
7351 | break; | |
4a277189 LX |
7352 | case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: |
7353 | case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: | |
7354 | case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: | |
7355 | if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) | |
7356 | return; | |
7357 | break; | |
2374b731 SC |
7358 | case MSR_IA32_XFD: |
7359 | case MSR_IA32_XFD_ERR: | |
7360 | if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) | |
7361 | return; | |
7362 | break; | |
b9846a69 MZ |
7363 | case MSR_IA32_TSX_CTRL: |
7364 | if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR)) | |
7365 | return; | |
7366 | break; | |
2374b731 SC |
7367 | default: |
7368 | break; | |
7369 | } | |
7370 | ||
7371 | msrs_to_save[num_msrs_to_save++] = msr_index; | |
7372 | } | |
7373 | ||
b1932c5c | 7374 | static void kvm_init_msr_lists(void) |
2374b731 | 7375 | { |
7a5ee6ed | 7376 | unsigned i; |
043405e1 | 7377 | |
0144ba0c | 7378 | BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3, |
2374b731 | 7379 | "Please update the fixed PMCs in msrs_to_save_pmu[]"); |
24c29b7a | 7380 | |
6cbee2b9 XL |
7381 | num_msrs_to_save = 0; |
7382 | num_emulated_msrs = 0; | |
7383 | num_msr_based_features = 0; | |
7384 | ||
2374b731 SC |
7385 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++) |
7386 | kvm_probe_msr_to_save(msrs_to_save_base[i]); | |
93c4adc7 | 7387 | |
c3531edc SC |
7388 | if (enable_pmu) { |
7389 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++) | |
7390 | kvm_probe_msr_to_save(msrs_to_save_pmu[i]); | |
043405e1 | 7391 | } |
62ef68bb | 7392 | |
7a5ee6ed | 7393 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
b3646477 | 7394 | if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) |
bc226f07 | 7395 | continue; |
62ef68bb | 7396 | |
7a5ee6ed | 7397 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 7398 | } |
801e459a | 7399 | |
9eb6ba31 SC |
7400 | for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++) |
7401 | kvm_probe_feature_msr(i); | |
801e459a | 7402 | |
9eb6ba31 SC |
7403 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) |
7404 | kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]); | |
043405e1 CO |
7405 | } |
7406 | ||
bda9020e MT |
7407 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
7408 | const void *v) | |
bbd9b64e | 7409 | { |
70252a10 AK |
7410 | int handled = 0; |
7411 | int n; | |
7412 | ||
7413 | do { | |
7414 | n = min(len, 8); | |
bce87cce | 7415 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
7416 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
7417 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
7418 | break; |
7419 | handled += n; | |
7420 | addr += n; | |
7421 | len -= n; | |
7422 | v += n; | |
7423 | } while (len); | |
bbd9b64e | 7424 | |
70252a10 | 7425 | return handled; |
bbd9b64e CO |
7426 | } |
7427 | ||
bda9020e | 7428 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 7429 | { |
70252a10 AK |
7430 | int handled = 0; |
7431 | int n; | |
7432 | ||
7433 | do { | |
7434 | n = min(len, 8); | |
bce87cce | 7435 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
7436 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
7437 | addr, n, v)) | |
7438 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 7439 | break; |
e39d200f | 7440 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
7441 | handled += n; |
7442 | addr += n; | |
7443 | len -= n; | |
7444 | v += n; | |
7445 | } while (len); | |
bbd9b64e | 7446 | |
70252a10 | 7447 | return handled; |
bbd9b64e CO |
7448 | } |
7449 | ||
c53da4f3 PB |
7450 | void kvm_set_segment(struct kvm_vcpu *vcpu, |
7451 | struct kvm_segment *var, int seg) | |
2dafc6c2 | 7452 | { |
b3646477 | 7453 | static_call(kvm_x86_set_segment)(vcpu, var, seg); |
2dafc6c2 GN |
7454 | } |
7455 | ||
7456 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
7457 | struct kvm_segment *var, int seg) | |
7458 | { | |
b3646477 | 7459 | static_call(kvm_x86_get_segment)(vcpu, var, seg); |
2dafc6c2 GN |
7460 | } |
7461 | ||
5b22bbe7 | 7462 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, |
54987b7a | 7463 | struct x86_exception *exception) |
02f59dc9 | 7464 | { |
1f5a21ee | 7465 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
02f59dc9 | 7466 | gpa_t t_gpa; |
02f59dc9 JR |
7467 | |
7468 | BUG_ON(!mmu_is_nested(vcpu)); | |
7469 | ||
7470 | /* NPT walks are always user-walks */ | |
7471 | access |= PFERR_USER_MASK; | |
1f5a21ee | 7472 | t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); |
02f59dc9 JR |
7473 | |
7474 | return t_gpa; | |
7475 | } | |
7476 | ||
ab9ae313 AK |
7477 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
7478 | struct x86_exception *exception) | |
1871c602 | 7479 | { |
1f5a21ee LJ |
7480 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7481 | ||
5b22bbe7 | 7482 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1f5a21ee | 7483 | return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
1871c602 | 7484 | } |
54f958cd | 7485 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); |
1871c602 | 7486 | |
ab9ae313 AK |
7487 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
7488 | struct x86_exception *exception) | |
1871c602 | 7489 | { |
1f5a21ee LJ |
7490 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7491 | ||
5b22bbe7 | 7492 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 7493 | access |= PFERR_WRITE_MASK; |
1f5a21ee | 7494 | return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
1871c602 | 7495 | } |
54f958cd | 7496 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); |
1871c602 GN |
7497 | |
7498 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
7499 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
7500 | struct x86_exception *exception) | |
1871c602 | 7501 | { |
1f5a21ee LJ |
7502 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7503 | ||
7504 | return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); | |
1871c602 GN |
7505 | } |
7506 | ||
7507 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5b22bbe7 | 7508 | struct kvm_vcpu *vcpu, u64 access, |
bcc55cba | 7509 | struct x86_exception *exception) |
bbd9b64e | 7510 | { |
1f5a21ee | 7511 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
bbd9b64e | 7512 | void *data = val; |
10589a46 | 7513 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
7514 | |
7515 | while (bytes) { | |
1f5a21ee | 7516 | gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); |
bbd9b64e | 7517 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 7518 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
7519 | int ret; |
7520 | ||
6e1d2a3f | 7521 | if (gpa == INVALID_GPA) |
ab9ae313 | 7522 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
7523 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
7524 | offset, toread); | |
10589a46 | 7525 | if (ret < 0) { |
c3cd7ffa | 7526 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
7527 | goto out; |
7528 | } | |
bbd9b64e | 7529 | |
77c2002e IE |
7530 | bytes -= toread; |
7531 | data += toread; | |
7532 | addr += toread; | |
bbd9b64e | 7533 | } |
10589a46 | 7534 | out: |
10589a46 | 7535 | return r; |
bbd9b64e | 7536 | } |
77c2002e | 7537 | |
1871c602 | 7538 | /* used for instruction fetching */ |
0f65dd70 AK |
7539 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
7540 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 7541 | struct x86_exception *exception) |
1871c602 | 7542 | { |
0f65dd70 | 7543 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1f5a21ee | 7544 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
5b22bbe7 | 7545 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
7546 | unsigned offset; |
7547 | int ret; | |
0f65dd70 | 7548 | |
44583cba | 7549 | /* Inline kvm_read_guest_virt_helper for speed. */ |
1f5a21ee LJ |
7550 | gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, |
7551 | exception); | |
6e1d2a3f | 7552 | if (unlikely(gpa == INVALID_GPA)) |
44583cba PB |
7553 | return X86EMUL_PROPAGATE_FAULT; |
7554 | ||
7555 | offset = addr & (PAGE_SIZE-1); | |
7556 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
7557 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
7558 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
7559 | offset, bytes); | |
44583cba PB |
7560 | if (unlikely(ret < 0)) |
7561 | return X86EMUL_IO_NEEDED; | |
7562 | ||
7563 | return X86EMUL_CONTINUE; | |
1871c602 GN |
7564 | } |
7565 | ||
ce14e868 | 7566 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 7567 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 7568 | struct x86_exception *exception) |
1871c602 | 7569 | { |
5b22bbe7 | 7570 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 7571 | |
353c0956 PB |
7572 | /* |
7573 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
7574 | * is returned, but our callers are not ready for that and they blindly | |
7575 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
7576 | * uninitialized kernel stack memory into cr2 and error code. | |
7577 | */ | |
7578 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 7579 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 7580 | exception); |
1871c602 | 7581 | } |
064aea77 | 7582 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 7583 | |
ce14e868 PB |
7584 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
7585 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 7586 | struct x86_exception *exception, bool system) |
1871c602 | 7587 | { |
0f65dd70 | 7588 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
5b22bbe7 | 7589 | u64 access = 0; |
3c9fa24c | 7590 | |
4f4aa80e LJ |
7591 | if (system) |
7592 | access |= PFERR_IMPLICIT_ACCESS; | |
7593 | else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) | |
3c9fa24c PB |
7594 | access |= PFERR_USER_MASK; |
7595 | ||
7596 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
7597 | } |
7598 | ||
ce14e868 | 7599 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
5b22bbe7 | 7600 | struct kvm_vcpu *vcpu, u64 access, |
ce14e868 | 7601 | struct x86_exception *exception) |
77c2002e | 7602 | { |
1f5a21ee | 7603 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
77c2002e IE |
7604 | void *data = val; |
7605 | int r = X86EMUL_CONTINUE; | |
7606 | ||
7607 | while (bytes) { | |
1f5a21ee | 7608 | gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); |
77c2002e IE |
7609 | unsigned offset = addr & (PAGE_SIZE-1); |
7610 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
7611 | int ret; | |
7612 | ||
6e1d2a3f | 7613 | if (gpa == INVALID_GPA) |
ab9ae313 | 7614 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 7615 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 7616 | if (ret < 0) { |
c3cd7ffa | 7617 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
7618 | goto out; |
7619 | } | |
7620 | ||
7621 | bytes -= towrite; | |
7622 | data += towrite; | |
7623 | addr += towrite; | |
7624 | } | |
7625 | out: | |
7626 | return r; | |
7627 | } | |
ce14e868 PB |
7628 | |
7629 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
7630 | unsigned int bytes, struct x86_exception *exception, |
7631 | bool system) | |
ce14e868 PB |
7632 | { |
7633 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5b22bbe7 | 7634 | u64 access = PFERR_WRITE_MASK; |
3c9fa24c | 7635 | |
4f4aa80e LJ |
7636 | if (system) |
7637 | access |= PFERR_IMPLICIT_ACCESS; | |
7638 | else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) | |
3c9fa24c | 7639 | access |= PFERR_USER_MASK; |
ce14e868 PB |
7640 | |
7641 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 7642 | access, exception); |
ce14e868 PB |
7643 | } |
7644 | ||
7645 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
7646 | unsigned int bytes, struct x86_exception *exception) | |
7647 | { | |
c595ceee PB |
7648 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
7649 | vcpu->arch.l1tf_flush_l1d = true; | |
7650 | ||
ce14e868 PB |
7651 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
7652 | PFERR_WRITE_MASK, exception); | |
7653 | } | |
6a4d7550 | 7654 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 7655 | |
aeb904f6 SC |
7656 | static int kvm_check_emulate_insn(struct kvm_vcpu *vcpu, int emul_type, |
7657 | void *insn, int insn_len) | |
4d31d9ef | 7658 | { |
aeb904f6 SC |
7659 | return static_call(kvm_x86_check_emulate_instruction)(vcpu, emul_type, |
7660 | insn, insn_len); | |
4d31d9ef SC |
7661 | } |
7662 | ||
082d06ed WL |
7663 | int handle_ud(struct kvm_vcpu *vcpu) |
7664 | { | |
b3dc0695 | 7665 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
40aaa5b6 | 7666 | int fep_flags = READ_ONCE(force_emulation_prefix); |
6c86eedc | 7667 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
7668 | char sig[5]; /* ud2; .ascii "kvm" */ |
7669 | struct x86_exception e; | |
aeb904f6 | 7670 | int r; |
6c86eedc | 7671 | |
aeb904f6 SC |
7672 | r = kvm_check_emulate_insn(vcpu, emul_type, NULL, 0); |
7673 | if (r != X86EMUL_CONTINUE) | |
09e3e2a1 SC |
7674 | return 1; |
7675 | ||
40aaa5b6 | 7676 | if (fep_flags && |
3c9fa24c PB |
7677 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
7678 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 7679 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
40aaa5b6 | 7680 | if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF) |
d500e1ed | 7681 | kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF); |
6c86eedc | 7682 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 7683 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 7684 | } |
082d06ed | 7685 | |
60fc3d02 | 7686 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
7687 | } |
7688 | EXPORT_SYMBOL_GPL(handle_ud); | |
7689 | ||
0f89b207 TL |
7690 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
7691 | gpa_t gpa, bool write) | |
7692 | { | |
7693 | /* For APIC access vmexit */ | |
7694 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
7695 | return 1; | |
7696 | ||
7697 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
7698 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
7699 | return 1; | |
7700 | } | |
7701 | ||
7702 | return 0; | |
7703 | } | |
7704 | ||
af7cc7d1 XG |
7705 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
7706 | gpa_t *gpa, struct x86_exception *exception, | |
7707 | bool write) | |
7708 | { | |
1f5a21ee | 7709 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
5b22bbe7 | 7710 | u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 7711 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 7712 | |
be94f6b7 HH |
7713 | /* |
7714 | * currently PKRU is only applied to ept enabled guest so | |
7715 | * there is no pkey in EPT page table for L1 guest or EPT | |
7716 | * shadow page table for L2 guest. | |
7717 | */ | |
908b7d43 SC |
7718 | if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || |
7719 | !permission_fault(vcpu, vcpu->arch.walk_mmu, | |
7720 | vcpu->arch.mmio_access, 0, access))) { | |
bebb106a XG |
7721 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
7722 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 7723 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
7724 | return 1; |
7725 | } | |
7726 | ||
1f5a21ee | 7727 | *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
af7cc7d1 | 7728 | |
6e1d2a3f | 7729 | if (*gpa == INVALID_GPA) |
af7cc7d1 XG |
7730 | return -1; |
7731 | ||
0f89b207 | 7732 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
7733 | } |
7734 | ||
3200f405 | 7735 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 7736 | const void *val, int bytes) |
bbd9b64e CO |
7737 | { |
7738 | int ret; | |
7739 | ||
54bf36aa | 7740 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 7741 | if (ret < 0) |
bbd9b64e | 7742 | return 0; |
0eb05bf2 | 7743 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
7744 | return 1; |
7745 | } | |
7746 | ||
77d197b2 XG |
7747 | struct read_write_emulator_ops { |
7748 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
7749 | int bytes); | |
7750 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7751 | void *val, int bytes); | |
7752 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7753 | int bytes, void *val); | |
7754 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7755 | void *val, int bytes); | |
7756 | bool write; | |
7757 | }; | |
7758 | ||
7759 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
7760 | { | |
7761 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 7762 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 7763 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
7764 | vcpu->mmio_read_completed = 0; |
7765 | return 1; | |
7766 | } | |
7767 | ||
7768 | return 0; | |
7769 | } | |
7770 | ||
7771 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7772 | void *val, int bytes) | |
7773 | { | |
54bf36aa | 7774 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
7775 | } |
7776 | ||
7777 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7778 | void *val, int bytes) | |
7779 | { | |
7780 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
7781 | } | |
7782 | ||
7783 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
7784 | { | |
e39d200f | 7785 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
7786 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
7787 | } | |
7788 | ||
7789 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7790 | void *val, int bytes) | |
7791 | { | |
e39d200f | 7792 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
7793 | return X86EMUL_IO_NEEDED; |
7794 | } | |
7795 | ||
7796 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7797 | void *val, int bytes) | |
7798 | { | |
f78146b0 AK |
7799 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
7800 | ||
87da7e66 | 7801 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
7802 | return X86EMUL_CONTINUE; |
7803 | } | |
7804 | ||
0fbe9b0b | 7805 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
7806 | .read_write_prepare = read_prepare, |
7807 | .read_write_emulate = read_emulate, | |
7808 | .read_write_mmio = vcpu_mmio_read, | |
7809 | .read_write_exit_mmio = read_exit_mmio, | |
7810 | }; | |
7811 | ||
0fbe9b0b | 7812 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
7813 | .read_write_emulate = write_emulate, |
7814 | .read_write_mmio = write_mmio, | |
7815 | .read_write_exit_mmio = write_exit_mmio, | |
7816 | .write = true, | |
7817 | }; | |
7818 | ||
22388a3c XG |
7819 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
7820 | unsigned int bytes, | |
7821 | struct x86_exception *exception, | |
7822 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 7823 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 7824 | { |
af7cc7d1 XG |
7825 | gpa_t gpa; |
7826 | int handled, ret; | |
22388a3c | 7827 | bool write = ops->write; |
f78146b0 | 7828 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 7829 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
7830 | |
7831 | /* | |
7832 | * If the exit was due to a NPF we may already have a GPA. | |
7833 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
7834 | * Note, this cannot be used on string operations since string | |
7835 | * operation using rep will only have the initial GPA from the NPF | |
7836 | * occurred. | |
7837 | */ | |
744e699c SC |
7838 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
7839 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
7840 | gpa = ctxt->gpa_val; | |
618232e2 BS |
7841 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
7842 | } else { | |
7843 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
7844 | if (ret < 0) | |
7845 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 7846 | } |
10589a46 | 7847 | |
618232e2 | 7848 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
7849 | return X86EMUL_CONTINUE; |
7850 | ||
bbd9b64e CO |
7851 | /* |
7852 | * Is this MMIO handled locally? | |
7853 | */ | |
22388a3c | 7854 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 7855 | if (handled == bytes) |
bbd9b64e | 7856 | return X86EMUL_CONTINUE; |
bbd9b64e | 7857 | |
70252a10 AK |
7858 | gpa += handled; |
7859 | bytes -= handled; | |
7860 | val += handled; | |
7861 | ||
87da7e66 XG |
7862 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
7863 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
7864 | frag->gpa = gpa; | |
7865 | frag->data = val; | |
7866 | frag->len = bytes; | |
f78146b0 | 7867 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
7868 | } |
7869 | ||
52eb5a6d XL |
7870 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
7871 | unsigned long addr, | |
22388a3c XG |
7872 | void *val, unsigned int bytes, |
7873 | struct x86_exception *exception, | |
0fbe9b0b | 7874 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 7875 | { |
0f65dd70 | 7876 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
7877 | gpa_t gpa; |
7878 | int rc; | |
7879 | ||
7880 | if (ops->read_write_prepare && | |
7881 | ops->read_write_prepare(vcpu, val, bytes)) | |
7882 | return X86EMUL_CONTINUE; | |
7883 | ||
7884 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 7885 | |
bbd9b64e CO |
7886 | /* Crossing a page boundary? */ |
7887 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 7888 | int now; |
bbd9b64e CO |
7889 | |
7890 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
7891 | rc = emulator_read_write_onepage(addr, val, now, exception, |
7892 | vcpu, ops); | |
7893 | ||
bbd9b64e CO |
7894 | if (rc != X86EMUL_CONTINUE) |
7895 | return rc; | |
7896 | addr += now; | |
bac15531 NA |
7897 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
7898 | addr = (u32)addr; | |
bbd9b64e CO |
7899 | val += now; |
7900 | bytes -= now; | |
7901 | } | |
22388a3c | 7902 | |
f78146b0 AK |
7903 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
7904 | vcpu, ops); | |
7905 | if (rc != X86EMUL_CONTINUE) | |
7906 | return rc; | |
7907 | ||
7908 | if (!vcpu->mmio_nr_fragments) | |
7909 | return rc; | |
7910 | ||
7911 | gpa = vcpu->mmio_fragments[0].gpa; | |
7912 | ||
7913 | vcpu->mmio_needed = 1; | |
7914 | vcpu->mmio_cur_fragment = 0; | |
7915 | ||
87da7e66 | 7916 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
7917 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
7918 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
7919 | vcpu->run->mmio.phys_addr = gpa; | |
7920 | ||
7921 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
7922 | } |
7923 | ||
7924 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
7925 | unsigned long addr, | |
7926 | void *val, | |
7927 | unsigned int bytes, | |
7928 | struct x86_exception *exception) | |
7929 | { | |
7930 | return emulator_read_write(ctxt, addr, val, bytes, | |
7931 | exception, &read_emultor); | |
7932 | } | |
7933 | ||
52eb5a6d | 7934 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
7935 | unsigned long addr, |
7936 | const void *val, | |
7937 | unsigned int bytes, | |
7938 | struct x86_exception *exception) | |
7939 | { | |
7940 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
7941 | exception, &write_emultor); | |
bbd9b64e | 7942 | } |
bbd9b64e | 7943 | |
1c2361f6 SC |
7944 | #define emulator_try_cmpxchg_user(t, ptr, old, new) \ |
7945 | (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t)) | |
daea3e73 | 7946 | |
0f65dd70 AK |
7947 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
7948 | unsigned long addr, | |
bbd9b64e CO |
7949 | const void *old, |
7950 | const void *new, | |
7951 | unsigned int bytes, | |
0f65dd70 | 7952 | struct x86_exception *exception) |
bbd9b64e | 7953 | { |
0f65dd70 | 7954 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 7955 | u64 page_line_mask; |
1c2361f6 | 7956 | unsigned long hva; |
daea3e73 | 7957 | gpa_t gpa; |
1c2361f6 | 7958 | int r; |
2bacc55c | 7959 | |
daea3e73 AK |
7960 | /* guests cmpxchg8b have to be emulated atomically */ |
7961 | if (bytes > 8 || (bytes & (bytes - 1))) | |
7962 | goto emul_write; | |
10589a46 | 7963 | |
daea3e73 | 7964 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 7965 | |
6e1d2a3f | 7966 | if (gpa == INVALID_GPA || |
daea3e73 AK |
7967 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) |
7968 | goto emul_write; | |
2bacc55c | 7969 | |
9de6fe3c XL |
7970 | /* |
7971 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
7972 | * enabled in the host and the access splits a cache line. | |
7973 | */ | |
7974 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
7975 | page_line_mask = ~(cache_line_size() - 1); | |
7976 | else | |
7977 | page_line_mask = PAGE_MASK; | |
7978 | ||
7979 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 7980 | goto emul_write; |
72dc67a6 | 7981 | |
1c2361f6 | 7982 | hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa)); |
33fbe6be | 7983 | if (kvm_is_error_hva(hva)) |
c19b8bd6 | 7984 | goto emul_write; |
72dc67a6 | 7985 | |
1c2361f6 | 7986 | hva += offset_in_page(gpa); |
42e35f80 | 7987 | |
daea3e73 AK |
7988 | switch (bytes) { |
7989 | case 1: | |
1c2361f6 | 7990 | r = emulator_try_cmpxchg_user(u8, hva, old, new); |
daea3e73 AK |
7991 | break; |
7992 | case 2: | |
1c2361f6 | 7993 | r = emulator_try_cmpxchg_user(u16, hva, old, new); |
daea3e73 AK |
7994 | break; |
7995 | case 4: | |
1c2361f6 | 7996 | r = emulator_try_cmpxchg_user(u32, hva, old, new); |
daea3e73 AK |
7997 | break; |
7998 | case 8: | |
1c2361f6 | 7999 | r = emulator_try_cmpxchg_user(u64, hva, old, new); |
daea3e73 AK |
8000 | break; |
8001 | default: | |
8002 | BUG(); | |
2bacc55c | 8003 | } |
42e35f80 | 8004 | |
1c2361f6 | 8005 | if (r < 0) |
5d6c7de6 | 8006 | return X86EMUL_UNHANDLEABLE; |
1c2361f6 | 8007 | if (r) |
daea3e73 AK |
8008 | return X86EMUL_CMPXCHG_FAILED; |
8009 | ||
0eb05bf2 | 8010 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
8011 | |
8012 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 8013 | |
3200f405 | 8014 | emul_write: |
8d20bd63 | 8015 | pr_warn_once("emulating exchange as write\n"); |
2bacc55c | 8016 | |
0f65dd70 | 8017 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
8018 | } |
8019 | ||
6f6fbe98 | 8020 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
30d583fd | 8021 | unsigned short port, void *data, |
6f6fbe98 | 8022 | unsigned int count, bool in) |
cf8f70bf | 8023 | { |
0f87ac23 PB |
8024 | unsigned i; |
8025 | int r; | |
cf8f70bf | 8026 | |
30d583fd | 8027 | WARN_ON_ONCE(vcpu->arch.pio.count); |
0f87ac23 PB |
8028 | for (i = 0; i < count; i++) { |
8029 | if (in) | |
8030 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data); | |
cbfc6c91 | 8031 | else |
0f87ac23 | 8032 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data); |
35ab3b77 PB |
8033 | |
8034 | if (r) { | |
8035 | if (i == 0) | |
8036 | goto userspace_io; | |
8037 | ||
8038 | /* | |
8039 | * Userspace must have unregistered the device while PIO | |
0c05e10b | 8040 | * was running. Drop writes / read as 0. |
35ab3b77 | 8041 | */ |
0c05e10b PB |
8042 | if (in) |
8043 | memset(data, 0, size * (count - i)); | |
cbfc6c91 | 8044 | break; |
35ab3b77 PB |
8045 | } |
8046 | ||
0f87ac23 | 8047 | data += size; |
cbfc6c91 | 8048 | } |
0f87ac23 | 8049 | return 1; |
cf8f70bf | 8050 | |
0f87ac23 | 8051 | userspace_io: |
cf8f70bf | 8052 | vcpu->arch.pio.port = port; |
6f6fbe98 | 8053 | vcpu->arch.pio.in = in; |
0c05e10b | 8054 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
8055 | vcpu->arch.pio.size = size; |
8056 | ||
0c05e10b PB |
8057 | if (in) |
8058 | memset(vcpu->arch.pio_data, 0, size * count); | |
8059 | else | |
8060 | memcpy(vcpu->arch.pio_data, data, size * count); | |
cf8f70bf GN |
8061 | |
8062 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 8063 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
8064 | vcpu->run->io.size = size; |
8065 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
8066 | vcpu->run->io.count = count; | |
8067 | vcpu->run->io.port = port; | |
cf8f70bf GN |
8068 | return 0; |
8069 | } | |
8070 | ||
f35cee4a PB |
8071 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
8072 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 8073 | { |
0c05e10b PB |
8074 | int r = emulator_pio_in_out(vcpu, size, port, val, count, true); |
8075 | if (r) | |
8076 | trace_kvm_pio(KVM_PIO_IN, port, size, count, val); | |
8077 | ||
8078 | return r; | |
3b27de27 | 8079 | } |
ca1d4a9e | 8080 | |
6b5efc93 | 8081 | static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) |
3b27de27 | 8082 | { |
6b5efc93 | 8083 | int size = vcpu->arch.pio.size; |
0c05e10b | 8084 | unsigned int count = vcpu->arch.pio.count; |
6b5efc93 PB |
8085 | memcpy(val, vcpu->arch.pio_data, size * count); |
8086 | trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); | |
3b27de27 PB |
8087 | vcpu->arch.pio.count = 0; |
8088 | } | |
cf8f70bf | 8089 | |
f35cee4a PB |
8090 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
8091 | int size, unsigned short port, void *val, | |
8092 | unsigned int count) | |
3b27de27 | 8093 | { |
f35cee4a | 8094 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3b27de27 | 8095 | if (vcpu->arch.pio.count) { |
d07898ea SC |
8096 | /* |
8097 | * Complete a previous iteration that required userspace I/O. | |
8098 | * Note, @count isn't guaranteed to match pio.count as userspace | |
8099 | * can modify ECX before rerunning the vCPU. Ignore any such | |
8100 | * shenanigans as KVM doesn't support modifying the rep count, | |
8101 | * and the emulator ensures @count doesn't overflow the buffer. | |
8102 | */ | |
0c05e10b PB |
8103 | complete_emulator_pio_in(vcpu, val); |
8104 | return 1; | |
cf8f70bf GN |
8105 | } |
8106 | ||
f35cee4a | 8107 | return emulator_pio_in(vcpu, size, port, val, count); |
2e3bb4d8 | 8108 | } |
6f6fbe98 | 8109 | |
2e3bb4d8 SC |
8110 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
8111 | unsigned short port, const void *val, | |
8112 | unsigned int count) | |
8113 | { | |
30d583fd | 8114 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, val); |
0c05e10b | 8115 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6f6fbe98 XG |
8116 | } |
8117 | ||
2e3bb4d8 SC |
8118 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
8119 | int size, unsigned short port, | |
8120 | const void *val, unsigned int count) | |
8121 | { | |
8122 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
8123 | } | |
8124 | ||
bbd9b64e CO |
8125 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
8126 | { | |
b3646477 | 8127 | return static_call(kvm_x86_get_segment_base)(vcpu, seg); |
bbd9b64e CO |
8128 | } |
8129 | ||
3cb16fe7 | 8130 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 8131 | { |
3cb16fe7 | 8132 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
8133 | } |
8134 | ||
ae6a2375 | 8135 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
8136 | { |
8137 | if (!need_emulate_wbinvd(vcpu)) | |
8138 | return X86EMUL_CONTINUE; | |
8139 | ||
b3646477 | 8140 | if (static_call(kvm_x86_has_wbinvd_exit)()) { |
2eec7343 JK |
8141 | int cpu = get_cpu(); |
8142 | ||
8143 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
c2162e13 | 8144 | on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, |
f5f48ee1 | 8145 | wbinvd_ipi, NULL, 1); |
2eec7343 | 8146 | put_cpu(); |
f5f48ee1 | 8147 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
8148 | } else |
8149 | wbinvd(); | |
f5f48ee1 SY |
8150 | return X86EMUL_CONTINUE; |
8151 | } | |
5cb56059 JS |
8152 | |
8153 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
8154 | { | |
6affcbed KH |
8155 | kvm_emulate_wbinvd_noskip(vcpu); |
8156 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 8157 | } |
f5f48ee1 SY |
8158 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
8159 | ||
5cb56059 JS |
8160 | |
8161 | ||
bcaf5cc5 AK |
8162 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
8163 | { | |
5cb56059 | 8164 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
8165 | } |
8166 | ||
29d6ca41 PB |
8167 | static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
8168 | unsigned long *dest) | |
bbd9b64e | 8169 | { |
29d6ca41 | 8170 | kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
8171 | } |
8172 | ||
52eb5a6d XL |
8173 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
8174 | unsigned long value) | |
bbd9b64e | 8175 | { |
338dbc97 | 8176 | |
996ff542 | 8177 | return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
8178 | } |
8179 | ||
52a46617 | 8180 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 8181 | { |
52a46617 | 8182 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
8183 | } |
8184 | ||
717746e3 | 8185 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 8186 | { |
717746e3 | 8187 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
8188 | unsigned long value; |
8189 | ||
8190 | switch (cr) { | |
8191 | case 0: | |
8192 | value = kvm_read_cr0(vcpu); | |
8193 | break; | |
8194 | case 2: | |
8195 | value = vcpu->arch.cr2; | |
8196 | break; | |
8197 | case 3: | |
9f8fe504 | 8198 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
8199 | break; |
8200 | case 4: | |
8201 | value = kvm_read_cr4(vcpu); | |
8202 | break; | |
8203 | case 8: | |
8204 | value = kvm_get_cr8(vcpu); | |
8205 | break; | |
8206 | default: | |
a737f256 | 8207 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
8208 | return 0; |
8209 | } | |
8210 | ||
8211 | return value; | |
8212 | } | |
8213 | ||
717746e3 | 8214 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 8215 | { |
717746e3 | 8216 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
8217 | int res = 0; |
8218 | ||
52a46617 GN |
8219 | switch (cr) { |
8220 | case 0: | |
49a9b07e | 8221 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
8222 | break; |
8223 | case 2: | |
8224 | vcpu->arch.cr2 = val; | |
8225 | break; | |
8226 | case 3: | |
2390218b | 8227 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
8228 | break; |
8229 | case 4: | |
a83b29c6 | 8230 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
8231 | break; |
8232 | case 8: | |
eea1cff9 | 8233 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
8234 | break; |
8235 | default: | |
a737f256 | 8236 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 8237 | res = -1; |
52a46617 | 8238 | } |
0f12244f GN |
8239 | |
8240 | return res; | |
52a46617 GN |
8241 | } |
8242 | ||
717746e3 | 8243 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 8244 | { |
b3646477 | 8245 | return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); |
9c537244 GN |
8246 | } |
8247 | ||
4bff1e86 | 8248 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 8249 | { |
b3646477 | 8250 | static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
8251 | } |
8252 | ||
4bff1e86 | 8253 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 8254 | { |
b3646477 | 8255 | static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
8256 | } |
8257 | ||
1ac9d0cf AK |
8258 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
8259 | { | |
b3646477 | 8260 | static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
8261 | } |
8262 | ||
8263 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
8264 | { | |
b3646477 | 8265 | static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
8266 | } |
8267 | ||
4bff1e86 AK |
8268 | static unsigned long emulator_get_cached_segment_base( |
8269 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 8270 | { |
4bff1e86 | 8271 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
8272 | } |
8273 | ||
1aa36616 AK |
8274 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
8275 | struct desc_struct *desc, u32 *base3, | |
8276 | int seg) | |
2dafc6c2 GN |
8277 | { |
8278 | struct kvm_segment var; | |
8279 | ||
4bff1e86 | 8280 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 8281 | *selector = var.selector; |
2dafc6c2 | 8282 | |
378a8b09 GN |
8283 | if (var.unusable) { |
8284 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
8285 | if (base3) |
8286 | *base3 = 0; | |
2dafc6c2 | 8287 | return false; |
378a8b09 | 8288 | } |
2dafc6c2 GN |
8289 | |
8290 | if (var.g) | |
8291 | var.limit >>= 12; | |
8292 | set_desc_limit(desc, var.limit); | |
8293 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
8294 | #ifdef CONFIG_X86_64 |
8295 | if (base3) | |
8296 | *base3 = var.base >> 32; | |
8297 | #endif | |
2dafc6c2 GN |
8298 | desc->type = var.type; |
8299 | desc->s = var.s; | |
8300 | desc->dpl = var.dpl; | |
8301 | desc->p = var.present; | |
8302 | desc->avl = var.avl; | |
8303 | desc->l = var.l; | |
8304 | desc->d = var.db; | |
8305 | desc->g = var.g; | |
8306 | ||
8307 | return true; | |
8308 | } | |
8309 | ||
1aa36616 AK |
8310 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
8311 | struct desc_struct *desc, u32 base3, | |
8312 | int seg) | |
2dafc6c2 | 8313 | { |
4bff1e86 | 8314 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
8315 | struct kvm_segment var; |
8316 | ||
1aa36616 | 8317 | var.selector = selector; |
2dafc6c2 | 8318 | var.base = get_desc_base(desc); |
5601d05b GN |
8319 | #ifdef CONFIG_X86_64 |
8320 | var.base |= ((u64)base3) << 32; | |
8321 | #endif | |
2dafc6c2 GN |
8322 | var.limit = get_desc_limit(desc); |
8323 | if (desc->g) | |
8324 | var.limit = (var.limit << 12) | 0xfff; | |
8325 | var.type = desc->type; | |
2dafc6c2 GN |
8326 | var.dpl = desc->dpl; |
8327 | var.db = desc->d; | |
8328 | var.s = desc->s; | |
8329 | var.l = desc->l; | |
8330 | var.g = desc->g; | |
8331 | var.avl = desc->avl; | |
8332 | var.present = desc->p; | |
8333 | var.unusable = !var.present; | |
8334 | var.padding = 0; | |
8335 | ||
8336 | kvm_set_segment(vcpu, &var, seg); | |
8337 | return; | |
8338 | } | |
8339 | ||
ac8d6cad HW |
8340 | static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt, |
8341 | u32 msr_index, u64 *pdata) | |
717746e3 | 8342 | { |
1ae09954 AG |
8343 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8344 | int r; | |
8345 | ||
ac8d6cad | 8346 | r = kvm_get_msr_with_filter(vcpu, msr_index, pdata); |
36d546d5 HW |
8347 | if (r < 0) |
8348 | return X86EMUL_UNHANDLEABLE; | |
1ae09954 | 8349 | |
36d546d5 HW |
8350 | if (r) { |
8351 | if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, | |
8352 | complete_emulated_rdmsr, r)) | |
8353 | return X86EMUL_IO_NEEDED; | |
794663e1 HW |
8354 | |
8355 | trace_kvm_msr_read_ex(msr_index); | |
36d546d5 | 8356 | return X86EMUL_PROPAGATE_FAULT; |
1ae09954 AG |
8357 | } |
8358 | ||
794663e1 | 8359 | trace_kvm_msr_read(msr_index, *pdata); |
36d546d5 | 8360 | return X86EMUL_CONTINUE; |
717746e3 AK |
8361 | } |
8362 | ||
ac8d6cad HW |
8363 | static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt, |
8364 | u32 msr_index, u64 data) | |
717746e3 | 8365 | { |
1ae09954 AG |
8366 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8367 | int r; | |
8368 | ||
ac8d6cad | 8369 | r = kvm_set_msr_with_filter(vcpu, msr_index, data); |
36d546d5 HW |
8370 | if (r < 0) |
8371 | return X86EMUL_UNHANDLEABLE; | |
1ae09954 | 8372 | |
36d546d5 HW |
8373 | if (r) { |
8374 | if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, | |
8375 | complete_emulated_msr_access, r)) | |
8376 | return X86EMUL_IO_NEEDED; | |
794663e1 HW |
8377 | |
8378 | trace_kvm_msr_write_ex(msr_index, data); | |
36d546d5 | 8379 | return X86EMUL_PROPAGATE_FAULT; |
1ae09954 AG |
8380 | } |
8381 | ||
794663e1 | 8382 | trace_kvm_msr_write(msr_index, data); |
36d546d5 | 8383 | return X86EMUL_CONTINUE; |
717746e3 AK |
8384 | } |
8385 | ||
ac8d6cad HW |
8386 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
8387 | u32 msr_index, u64 *pdata) | |
8388 | { | |
8389 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
8390 | } | |
8391 | ||
7bb7fce1 | 8392 | static int emulator_check_rdpmc_early(struct x86_emulate_ctxt *ctxt, u32 pmc) |
67f4d428 | 8393 | { |
7bb7fce1 | 8394 | return kvm_pmu_check_rdpmc_early(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
8395 | } |
8396 | ||
222d21aa AK |
8397 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
8398 | u32 pmc, u64 *pdata) | |
8399 | { | |
c6702c9d | 8400 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
8401 | } |
8402 | ||
6c3287f7 AK |
8403 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
8404 | { | |
8405 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
8406 | } | |
8407 | ||
2953538e | 8408 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 8409 | struct x86_instruction_info *info, |
c4f035c6 AK |
8410 | enum x86_intercept_stage stage) |
8411 | { | |
b3646477 | 8412 | return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 8413 | &ctxt->exception); |
c4f035c6 AK |
8414 | } |
8415 | ||
e911eb3b | 8416 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
8417 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
8418 | bool exact_only) | |
bdb42f5a | 8419 | { |
f91af517 | 8420 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
8421 | } |
8422 | ||
5ae78e95 SC |
8423 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) |
8424 | { | |
8425 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
8426 | } | |
8427 | ||
8428 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
8429 | { | |
8430 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
8431 | } | |
8432 | ||
a836839c HW |
8433 | static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt) |
8434 | { | |
8435 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID); | |
8436 | } | |
8437 | ||
dd856efa AK |
8438 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
8439 | { | |
27b4a9c4 | 8440 | return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); |
dd856efa AK |
8441 | } |
8442 | ||
8443 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
8444 | { | |
27b4a9c4 | 8445 | kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); |
dd856efa AK |
8446 | } |
8447 | ||
801806d9 NA |
8448 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
8449 | { | |
b3646477 | 8450 | static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
8451 | } |
8452 | ||
32e69f23 | 8453 | static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt) |
6ed071f0 | 8454 | { |
32e69f23 ML |
8455 | return is_smm(emul_to_vcpu(ctxt)); |
8456 | } | |
8457 | ||
8458 | static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt) | |
6ed071f0 | 8459 | { |
32e69f23 | 8460 | return is_guest_mode(emul_to_vcpu(ctxt)); |
6ed071f0 LP |
8461 | } |
8462 | ||
4b8e1b32 PB |
8463 | #ifndef CONFIG_KVM_SMM |
8464 | static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt) | |
6ed071f0 | 8465 | { |
4b8e1b32 PB |
8466 | WARN_ON_ONCE(1); |
8467 | return X86EMUL_UNHANDLEABLE; | |
0234bf88 | 8468 | } |
4b8e1b32 | 8469 | #endif |
0234bf88 | 8470 | |
25b17226 SC |
8471 | static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) |
8472 | { | |
8473 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); | |
8474 | } | |
8475 | ||
02d4160f VK |
8476 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
8477 | { | |
8478 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
8479 | } | |
8480 | ||
1cca2f8c SC |
8481 | static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt) |
8482 | { | |
8483 | struct kvm *kvm = emul_to_vcpu(ctxt)->kvm; | |
8484 | ||
8485 | if (!kvm->vm_bugged) | |
8486 | kvm_vm_bugged(kvm); | |
8487 | } | |
8488 | ||
37a41847 BW |
8489 | static gva_t emulator_get_untagged_addr(struct x86_emulate_ctxt *ctxt, |
8490 | gva_t addr, unsigned int flags) | |
8491 | { | |
8492 | if (!kvm_x86_ops.get_untagged_addr) | |
8493 | return addr; | |
8494 | ||
8495 | return static_call(kvm_x86_get_untagged_addr)(emul_to_vcpu(ctxt), addr, flags); | |
8496 | } | |
8497 | ||
0225fb50 | 8498 | static const struct x86_emulate_ops emulate_ops = { |
1cca2f8c | 8499 | .vm_bugged = emulator_vm_bugged, |
dd856efa AK |
8500 | .read_gpr = emulator_read_gpr, |
8501 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
8502 | .read_std = emulator_read_std, |
8503 | .write_std = emulator_write_std, | |
1871c602 | 8504 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
8505 | .read_emulated = emulator_read_emulated, |
8506 | .write_emulated = emulator_write_emulated, | |
8507 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 8508 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
8509 | .pio_in_emulated = emulator_pio_in_emulated, |
8510 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
8511 | .get_segment = emulator_get_segment, |
8512 | .set_segment = emulator_set_segment, | |
5951c442 | 8513 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 8514 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 8515 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
8516 | .set_gdt = emulator_set_gdt, |
8517 | .set_idt = emulator_set_idt, | |
52a46617 GN |
8518 | .get_cr = emulator_get_cr, |
8519 | .set_cr = emulator_set_cr, | |
9c537244 | 8520 | .cpl = emulator_get_cpl, |
35aa5375 GN |
8521 | .get_dr = emulator_get_dr, |
8522 | .set_dr = emulator_set_dr, | |
ac8d6cad HW |
8523 | .set_msr_with_filter = emulator_set_msr_with_filter, |
8524 | .get_msr_with_filter = emulator_get_msr_with_filter, | |
717746e3 | 8525 | .get_msr = emulator_get_msr, |
7bb7fce1 | 8526 | .check_rdpmc_early = emulator_check_rdpmc_early, |
222d21aa | 8527 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 8528 | .halt = emulator_halt, |
bcaf5cc5 | 8529 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 8530 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 8531 | .intercept = emulator_intercept, |
bdb42f5a | 8532 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
8533 | .guest_has_movbe = emulator_guest_has_movbe, |
8534 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
a836839c | 8535 | .guest_has_rdpid = emulator_guest_has_rdpid, |
801806d9 | 8536 | .set_nmi_mask = emulator_set_nmi_mask, |
32e69f23 ML |
8537 | .is_smm = emulator_is_smm, |
8538 | .is_guest_mode = emulator_is_guest_mode, | |
ecc513e5 | 8539 | .leave_smm = emulator_leave_smm, |
25b17226 | 8540 | .triple_fault = emulator_triple_fault, |
02d4160f | 8541 | .set_xcr = emulator_set_xcr, |
37a41847 | 8542 | .get_untagged_addr = emulator_get_untagged_addr, |
bbd9b64e CO |
8543 | }; |
8544 | ||
95cb2295 GN |
8545 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
8546 | { | |
b3646477 | 8547 | u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
95cb2295 GN |
8548 | /* |
8549 | * an sti; sti; sequence only disable interrupts for the first | |
8550 | * instruction. So, if the last instruction, be it emulated or | |
8551 | * not, left the system with the INT_STI flag enabled, it | |
8552 | * means that the last instruction is an sti. We should not | |
8553 | * leave the flag on in this case. The same goes for mov ss | |
8554 | */ | |
37ccdcbe PB |
8555 | if (int_shadow & mask) |
8556 | mask = 0; | |
6addfc42 | 8557 | if (unlikely(int_shadow || mask)) { |
b3646477 | 8558 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); |
6addfc42 PB |
8559 | if (!mask) |
8560 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8561 | } | |
95cb2295 GN |
8562 | } |
8563 | ||
7709aba8 | 8564 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 8565 | { |
c9b8b07c | 8566 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
ef54bcfe | 8567 | |
7709aba8 SC |
8568 | if (ctxt->exception.vector == PF_VECTOR) |
8569 | kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); | |
8570 | else if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
8571 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
8572 | ctxt->exception.error_code); | |
54b8486f | 8573 | else |
da9cb575 | 8574 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
54b8486f GN |
8575 | } |
8576 | ||
c9b8b07c SC |
8577 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
8578 | { | |
8579 | struct x86_emulate_ctxt *ctxt; | |
8580 | ||
8581 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
8582 | if (!ctxt) { | |
8d20bd63 | 8583 | pr_err("failed to allocate vcpu's emulator\n"); |
c9b8b07c SC |
8584 | return NULL; |
8585 | } | |
8586 | ||
8587 | ctxt->vcpu = vcpu; | |
8588 | ctxt->ops = &emulate_ops; | |
8589 | vcpu->arch.emulate_ctxt = ctxt; | |
8590 | ||
8591 | return ctxt; | |
8592 | } | |
8593 | ||
8ec4722d MG |
8594 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
8595 | { | |
c9b8b07c | 8596 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
8597 | int cs_db, cs_l; |
8598 | ||
b3646477 | 8599 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
8ec4722d | 8600 | |
744e699c | 8601 | ctxt->gpa_available = false; |
adf52235 | 8602 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
8603 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
8604 | ||
adf52235 TY |
8605 | ctxt->eip = kvm_rip_read(vcpu); |
8606 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
8607 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 8608 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
8609 | cs_db ? X86EMUL_MODE_PROT32 : |
8610 | X86EMUL_MODE_PROT16; | |
da6393cd WL |
8611 | ctxt->interruptibility = 0; |
8612 | ctxt->have_exception = false; | |
8613 | ctxt->exception.vector = -1; | |
8614 | ctxt->perm_ok = false; | |
8615 | ||
dd856efa | 8616 | init_decode_cache(ctxt); |
7ae441ea | 8617 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
8618 | } |
8619 | ||
9497e1f2 | 8620 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 8621 | { |
c9b8b07c | 8622 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
8623 | int ret; |
8624 | ||
8625 | init_emulate_ctxt(vcpu); | |
8626 | ||
9dac77fa AK |
8627 | ctxt->op_bytes = 2; |
8628 | ctxt->ad_bytes = 2; | |
8629 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 8630 | ret = emulate_int_real(ctxt, irq); |
63995653 | 8631 | |
9497e1f2 SC |
8632 | if (ret != X86EMUL_CONTINUE) { |
8633 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
8634 | } else { | |
8635 | ctxt->eip = ctxt->_eip; | |
8636 | kvm_rip_write(vcpu, ctxt->eip); | |
8637 | kvm_set_rflags(vcpu, ctxt->eflags); | |
8638 | } | |
63995653 MG |
8639 | } |
8640 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
8641 | ||
e615e355 DE |
8642 | static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, |
8643 | u8 ndata, u8 *insn_bytes, u8 insn_size) | |
19238e75 | 8644 | { |
19238e75 | 8645 | struct kvm_run *run = vcpu->run; |
e615e355 DE |
8646 | u64 info[5]; |
8647 | u8 info_start; | |
8648 | ||
8649 | /* | |
8650 | * Zero the whole array used to retrieve the exit info, as casting to | |
8651 | * u32 for select entries will leave some chunks uninitialized. | |
8652 | */ | |
8653 | memset(&info, 0, sizeof(info)); | |
8654 | ||
8655 | static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], | |
8656 | &info[2], (u32 *)&info[3], | |
8657 | (u32 *)&info[4]); | |
19238e75 AL |
8658 | |
8659 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8660 | run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
e615e355 DE |
8661 | |
8662 | /* | |
8663 | * There's currently space for 13 entries, but 5 are used for the exit | |
8664 | * reason and info. Restrict to 4 to reduce the maintenance burden | |
8665 | * when expanding kvm_run.emulation_failure in the future. | |
8666 | */ | |
8667 | if (WARN_ON_ONCE(ndata > 4)) | |
8668 | ndata = 4; | |
8669 | ||
8670 | /* Always include the flags as a 'data' entry. */ | |
8671 | info_start = 1; | |
19238e75 AL |
8672 | run->emulation_failure.flags = 0; |
8673 | ||
8674 | if (insn_size) { | |
e615e355 DE |
8675 | BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + |
8676 | sizeof(run->emulation_failure.insn_bytes) != 16)); | |
8677 | info_start += 2; | |
19238e75 AL |
8678 | run->emulation_failure.flags |= |
8679 | KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; | |
8680 | run->emulation_failure.insn_size = insn_size; | |
8681 | memset(run->emulation_failure.insn_bytes, 0x90, | |
8682 | sizeof(run->emulation_failure.insn_bytes)); | |
e615e355 | 8683 | memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); |
19238e75 | 8684 | } |
e615e355 DE |
8685 | |
8686 | memcpy(&run->internal.data[info_start], info, sizeof(info)); | |
8687 | memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, | |
8688 | ndata * sizeof(data[0])); | |
8689 | ||
8690 | run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; | |
19238e75 AL |
8691 | } |
8692 | ||
e615e355 DE |
8693 | static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) |
8694 | { | |
8695 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
8696 | ||
8697 | prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, | |
8698 | ctxt->fetch.end - ctxt->fetch.data); | |
8699 | } | |
8700 | ||
8701 | void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, | |
8702 | u8 ndata) | |
8703 | { | |
8704 | prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); | |
19238e75 | 8705 | } |
e615e355 DE |
8706 | EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); |
8707 | ||
8708 | void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) | |
8709 | { | |
8710 | __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); | |
8711 | } | |
8712 | EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); | |
19238e75 | 8713 | |
e2366171 | 8714 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 8715 | { |
19238e75 AL |
8716 | struct kvm *kvm = vcpu->kvm; |
8717 | ||
6d77dbfc GN |
8718 | ++vcpu->stat.insn_emulation_fail; |
8719 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 8720 | |
42cbf068 SC |
8721 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
8722 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 8723 | return 1; |
42cbf068 | 8724 | } |
e2366171 | 8725 | |
19238e75 AL |
8726 | if (kvm->arch.exit_on_emulation_error || |
8727 | (emulation_type & EMULTYPE_SKIP)) { | |
e615e355 | 8728 | prepare_emulation_ctxt_failure_exit(vcpu); |
60fc3d02 | 8729 | return 0; |
738fece4 SC |
8730 | } |
8731 | ||
22da61c9 SC |
8732 | kvm_queue_exception(vcpu, UD_VECTOR); |
8733 | ||
b3646477 | 8734 | if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { |
e615e355 | 8735 | prepare_emulation_ctxt_failure_exit(vcpu); |
60fc3d02 | 8736 | return 0; |
fc3a9157 | 8737 | } |
e2366171 | 8738 | |
60fc3d02 | 8739 | return 1; |
6d77dbfc GN |
8740 | } |
8741 | ||
736c291c | 8742 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 | 8743 | int emulation_type) |
a6f177ef | 8744 | { |
736c291c | 8745 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 8746 | kvm_pfn_t pfn; |
a6f177ef | 8747 | |
92daa48b | 8748 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
8749 | return false; |
8750 | ||
92daa48b SC |
8751 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
8752 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
8753 | return false; |
8754 | ||
347a0d0d | 8755 | if (!vcpu->arch.mmu->root_role.direct) { |
95b3cf69 XG |
8756 | /* |
8757 | * Write permission should be allowed since only | |
8758 | * write access need to be emulated. | |
8759 | */ | |
736c291c | 8760 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 8761 | |
95b3cf69 XG |
8762 | /* |
8763 | * If the mapping is invalid in guest, let cpu retry | |
8764 | * it to generate fault. | |
8765 | */ | |
6e1d2a3f | 8766 | if (gpa == INVALID_GPA) |
95b3cf69 XG |
8767 | return true; |
8768 | } | |
a6f177ef | 8769 | |
8e3d9d06 XG |
8770 | /* |
8771 | * Do not retry the unhandleable instruction if it faults on the | |
8772 | * readonly host memory, otherwise it will goto a infinite loop: | |
8773 | * retry instruction -> write #PF -> emulation fail -> retry | |
8774 | * instruction -> ... | |
8775 | */ | |
8776 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
8777 | |
8778 | /* | |
8779 | * If the instruction failed on the error pfn, it can not be fixed, | |
8780 | * report the error to userspace. | |
8781 | */ | |
8782 | if (is_error_noslot_pfn(pfn)) | |
8783 | return false; | |
8784 | ||
8785 | kvm_release_pfn_clean(pfn); | |
8786 | ||
8787 | /* The instructions are well-emulated on direct mmu. */ | |
347a0d0d | 8788 | if (vcpu->arch.mmu->root_role.direct) { |
95b3cf69 XG |
8789 | unsigned int indirect_shadow_pages; |
8790 | ||
531810ca | 8791 | write_lock(&vcpu->kvm->mmu_lock); |
95b3cf69 | 8792 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; |
531810ca | 8793 | write_unlock(&vcpu->kvm->mmu_lock); |
95b3cf69 XG |
8794 | |
8795 | if (indirect_shadow_pages) | |
8796 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
8797 | ||
a6f177ef | 8798 | return true; |
8e3d9d06 | 8799 | } |
a6f177ef | 8800 | |
95b3cf69 XG |
8801 | /* |
8802 | * if emulation was due to access to shadowed page table | |
8803 | * and it failed try to unshadow page and re-enter the | |
8804 | * guest to let CPU execute the instruction. | |
8805 | */ | |
8806 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
8807 | |
8808 | /* | |
8809 | * If the access faults on its page table, it can not | |
8810 | * be fixed by unprotecting shadow page and it should | |
8811 | * be reported to userspace. | |
8812 | */ | |
258d985f | 8813 | return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP); |
a6f177ef GN |
8814 | } |
8815 | ||
1cb3f3ae | 8816 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 8817 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
8818 | { |
8819 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 8820 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
8821 | |
8822 | last_retry_eip = vcpu->arch.last_retry_eip; | |
8823 | last_retry_addr = vcpu->arch.last_retry_addr; | |
8824 | ||
8825 | /* | |
8826 | * If the emulation is caused by #PF and it is non-page_table | |
8827 | * writing instruction, it means the VM-EXIT is caused by shadow | |
8828 | * page protected, we can zap the shadow page and retry this | |
8829 | * instruction directly. | |
8830 | * | |
8831 | * Note: if the guest uses a non-page-table modifying instruction | |
8832 | * on the PDE that points to the instruction, then we will unmap | |
8833 | * the instruction and go to an infinite loop. So, we cache the | |
8834 | * last retried eip and the last fault address, if we meet the eip | |
8835 | * and the address again, we can break out of the potential infinite | |
8836 | * loop. | |
8837 | */ | |
8838 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
8839 | ||
92daa48b | 8840 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
8841 | return false; |
8842 | ||
92daa48b SC |
8843 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
8844 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
8845 | return false; |
8846 | ||
1cb3f3ae XG |
8847 | if (x86_page_table_writing_insn(ctxt)) |
8848 | return false; | |
8849 | ||
736c291c | 8850 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
8851 | return false; |
8852 | ||
8853 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 8854 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 8855 | |
347a0d0d | 8856 | if (!vcpu->arch.mmu->root_role.direct) |
736c291c | 8857 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 8858 | |
22368028 | 8859 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
8860 | |
8861 | return true; | |
8862 | } | |
8863 | ||
716d51ab GN |
8864 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
8865 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
8866 | ||
4a1e10d5 PB |
8867 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
8868 | unsigned long *db) | |
8869 | { | |
8870 | u32 dr6 = 0; | |
8871 | int i; | |
8872 | u32 enable, rwlen; | |
8873 | ||
8874 | enable = dr7; | |
8875 | rwlen = dr7 >> 16; | |
8876 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
8877 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
8878 | dr6 |= (1 << i); | |
8879 | return dr6; | |
8880 | } | |
8881 | ||
120c2c4f | 8882 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
8883 | { |
8884 | struct kvm_run *kvm_run = vcpu->run; | |
8885 | ||
c8401dda | 8886 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 8887 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 8888 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
8889 | kvm_run->debug.arch.exception = DB_VECTOR; |
8890 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 8891 | return 0; |
663f4c61 | 8892 | } |
120c2c4f | 8893 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 8894 | return 1; |
663f4c61 PB |
8895 | } |
8896 | ||
6affcbed KH |
8897 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
8898 | { | |
b3646477 | 8899 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
f8ea7c60 | 8900 | int r; |
6affcbed | 8901 | |
b3646477 | 8902 | r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); |
60fc3d02 | 8903 | if (unlikely(!r)) |
f8ea7c60 | 8904 | return 0; |
c8401dda | 8905 | |
f19063b1 | 8906 | kvm_pmu_trigger_event(vcpu, kvm_pmu_eventsel.INSTRUCTIONS_RETIRED); |
9cd803d4 | 8907 | |
c8401dda PB |
8908 | /* |
8909 | * rflags is the old, "raw" value of the flags. The new value has | |
8910 | * not been saved yet. | |
8911 | * | |
8912 | * This is correct even for TF set by the guest, because "the | |
8913 | * processor will not generate this exception after the instruction | |
8914 | * that sets the TF flag". | |
8915 | */ | |
8916 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 8917 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 8918 | return r; |
6affcbed KH |
8919 | } |
8920 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
8921 | ||
baf67ca8 | 8922 | static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu) |
4a1e10d5 | 8923 | { |
baf67ca8 SC |
8924 | u32 shadow; |
8925 | ||
8926 | if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF) | |
8927 | return true; | |
8928 | ||
8929 | /* | |
8930 | * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active, | |
8931 | * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first | |
8932 | * to avoid the relatively expensive CPUID lookup. | |
8933 | */ | |
8934 | shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); | |
8935 | return (shadow & KVM_X86_SHADOW_INT_MOV_SS) && | |
8936 | guest_cpuid_is_intel(vcpu); | |
8937 | } | |
8938 | ||
750f8fcb SC |
8939 | static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, |
8940 | int emulation_type, int *r) | |
4a1e10d5 | 8941 | { |
750f8fcb SC |
8942 | WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE); |
8943 | ||
8944 | /* | |
8945 | * Do not check for code breakpoints if hardware has already done the | |
8946 | * checks, as inferred from the emulation type. On NO_DECODE and SKIP, | |
8947 | * the instruction has passed all exception checks, and all intercepted | |
8948 | * exceptions that trigger emulation have lower priority than code | |
8949 | * breakpoints, i.e. the fact that the intercepted exception occurred | |
8950 | * means any code breakpoints have already been serviced. | |
8951 | * | |
8952 | * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as | |
8953 | * hardware has checked the RIP of the magic prefix, but not the RIP of | |
8954 | * the instruction being emulated. The intent of forced emulation is | |
8955 | * to behave as if KVM intercepted the instruction without an exception | |
8956 | * and without a prefix. | |
8957 | */ | |
8958 | if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP | | |
8959 | EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF)) | |
8960 | return false; | |
8961 | ||
4a1e10d5 PB |
8962 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
8963 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
8964 | struct kvm_run *kvm_run = vcpu->run; |
8965 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
8966 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
8967 | vcpu->arch.guest_debug_dr7, |
8968 | vcpu->arch.eff_db); | |
8969 | ||
8970 | if (dr6 != 0) { | |
9a3ecd5e | 8971 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 8972 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
8973 | kvm_run->debug.arch.exception = DB_VECTOR; |
8974 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 8975 | *r = 0; |
4a1e10d5 PB |
8976 | return true; |
8977 | } | |
8978 | } | |
8979 | ||
4161a569 | 8980 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
baf67ca8 | 8981 | !kvm_is_code_breakpoint_inhibited(vcpu)) { |
82b32774 NA |
8982 | unsigned long eip = kvm_get_linear_rip(vcpu); |
8983 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
8984 | vcpu->arch.dr7, |
8985 | vcpu->arch.db); | |
8986 | ||
8987 | if (dr6 != 0) { | |
4d5523cf | 8988 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 8989 | *r = 1; |
4a1e10d5 PB |
8990 | return true; |
8991 | } | |
8992 | } | |
8993 | ||
8994 | return false; | |
8995 | } | |
8996 | ||
04789b66 LA |
8997 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
8998 | { | |
2d7921c4 AM |
8999 | switch (ctxt->opcode_len) { |
9000 | case 1: | |
9001 | switch (ctxt->b) { | |
9002 | case 0xe4: /* IN */ | |
9003 | case 0xe5: | |
9004 | case 0xec: | |
9005 | case 0xed: | |
9006 | case 0xe6: /* OUT */ | |
9007 | case 0xe7: | |
9008 | case 0xee: | |
9009 | case 0xef: | |
9010 | case 0x6c: /* INS */ | |
9011 | case 0x6d: | |
9012 | case 0x6e: /* OUTS */ | |
9013 | case 0x6f: | |
9014 | return true; | |
9015 | } | |
9016 | break; | |
9017 | case 2: | |
9018 | switch (ctxt->b) { | |
9019 | case 0x33: /* RDPMC */ | |
9020 | return true; | |
9021 | } | |
9022 | break; | |
04789b66 LA |
9023 | } |
9024 | ||
9025 | return false; | |
9026 | } | |
9027 | ||
4aa2691d | 9028 | /* |
fee060cd SC |
9029 | * Decode an instruction for emulation. The caller is responsible for handling |
9030 | * code breakpoints. Note, manually detecting code breakpoints is unnecessary | |
9031 | * (and wrong) when emulating on an intercepted fault-like exception[*], as | |
9032 | * code breakpoints have higher priority and thus have already been done by | |
9033 | * hardware. | |
9034 | * | |
9035 | * [*] Except #MC, which is higher priority, but KVM should never emulate in | |
9036 | * response to a machine check. | |
4aa2691d WH |
9037 | */ |
9038 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
9039 | void *insn, int insn_len) | |
9040 | { | |
4aa2691d | 9041 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
fee060cd | 9042 | int r; |
4aa2691d WH |
9043 | |
9044 | init_emulate_ctxt(vcpu); | |
9045 | ||
b35491e6 | 9046 | r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); |
4aa2691d WH |
9047 | |
9048 | trace_kvm_emulate_insn_start(vcpu); | |
9049 | ++vcpu->stat.insn_emulation; | |
9050 | ||
9051 | return r; | |
9052 | } | |
9053 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
9054 | ||
736c291c SC |
9055 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
9056 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 9057 | { |
95cb2295 | 9058 | int r; |
c9b8b07c | 9059 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 9060 | bool writeback = true; |
09e3e2a1 | 9061 | |
aeb904f6 | 9062 | r = kvm_check_emulate_insn(vcpu, emulation_type, insn, insn_len); |
00682995 SC |
9063 | if (r != X86EMUL_CONTINUE) { |
9064 | if (r == X86EMUL_RETRY_INSTR || r == X86EMUL_PROPAGATE_FAULT) | |
9065 | return 1; | |
9066 | ||
9067 | WARN_ON_ONCE(r != X86EMUL_UNHANDLEABLE); | |
9068 | return handle_emulation_failure(vcpu, emulation_type); | |
9069 | } | |
bbd9b64e | 9070 | |
c595ceee PB |
9071 | vcpu->arch.l1tf_flush_l1d = true; |
9072 | ||
571008da | 9073 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 9074 | kvm_clear_exception_queue(vcpu); |
4a1e10d5 | 9075 | |
fee060cd SC |
9076 | /* |
9077 | * Return immediately if RIP hits a code breakpoint, such #DBs | |
9078 | * are fault-like and are higher priority than any faults on | |
9079 | * the code fetch itself. | |
9080 | */ | |
750f8fcb | 9081 | if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r)) |
fee060cd SC |
9082 | return r; |
9083 | ||
4aa2691d WH |
9084 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
9085 | insn, insn_len); | |
1d2887e2 | 9086 | if (r != EMULATION_OK) { |
b4000606 | 9087 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
9088 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
9089 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 9090 | return 1; |
c83fad65 | 9091 | } |
736c291c | 9092 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
736c291c | 9093 | emulation_type)) |
60fc3d02 | 9094 | return 1; |
17122c06 SC |
9095 | |
9096 | if (ctxt->have_exception && | |
9097 | !(emulation_type & EMULTYPE_SKIP)) { | |
c8848cee JD |
9098 | /* |
9099 | * #UD should result in just EMULATION_FAILED, and trap-like | |
9100 | * exception should not be encountered during decode. | |
9101 | */ | |
9102 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
9103 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 9104 | inject_emulated_exception(vcpu); |
60fc3d02 | 9105 | return 1; |
8530a79c | 9106 | } |
e2366171 | 9107 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
9108 | } |
9109 | } | |
9110 | ||
42cbf068 SC |
9111 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
9112 | !is_vmware_backdoor_opcode(ctxt)) { | |
9113 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 9114 | return 1; |
42cbf068 | 9115 | } |
04789b66 | 9116 | |
1957aa63 | 9117 | /* |
906fa904 HW |
9118 | * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for |
9119 | * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). | |
9120 | * The caller is responsible for updating interruptibility state and | |
9121 | * injecting single-step #DBs. | |
1957aa63 | 9122 | */ |
ba8afb6b | 9123 | if (emulation_type & EMULTYPE_SKIP) { |
5e854864 SC |
9124 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
9125 | ctxt->eip = (u32)ctxt->_eip; | |
9126 | else | |
9127 | ctxt->eip = ctxt->_eip; | |
9128 | ||
906fa904 HW |
9129 | if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { |
9130 | r = 1; | |
9131 | goto writeback; | |
9132 | } | |
9133 | ||
5e854864 | 9134 | kvm_rip_write(vcpu, ctxt->eip); |
bb663c7a NA |
9135 | if (ctxt->eflags & X86_EFLAGS_RF) |
9136 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 9137 | return 1; |
ba8afb6b GN |
9138 | } |
9139 | ||
736c291c | 9140 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 9141 | return 1; |
1cb3f3ae | 9142 | |
7ae441ea | 9143 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 9144 | changes registers values during IO operation */ |
7ae441ea GN |
9145 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
9146 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 9147 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 9148 | } |
4d2179e1 | 9149 | |
5cd21917 | 9150 | restart: |
92daa48b SC |
9151 | if (emulation_type & EMULTYPE_PF) { |
9152 | /* Save the faulting GPA (cr2) in the address field */ | |
9153 | ctxt->exception.address = cr2_or_gpa; | |
9154 | ||
9155 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
347a0d0d | 9156 | if (vcpu->arch.mmu->root_role.direct) { |
744e699c SC |
9157 | ctxt->gpa_available = true; |
9158 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
9159 | } |
9160 | } else { | |
9161 | /* Sanitize the address out of an abundance of paranoia. */ | |
9162 | ctxt->exception.address = 0; | |
9163 | } | |
0f89b207 | 9164 | |
9d74191a | 9165 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 9166 | |
775fde86 | 9167 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 9168 | return 1; |
775fde86 | 9169 | |
d2ddd1c4 | 9170 | if (r == EMULATION_FAILED) { |
258d985f | 9171 | if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type)) |
60fc3d02 | 9172 | return 1; |
c3cd7ffa | 9173 | |
e2366171 | 9174 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
9175 | } |
9176 | ||
9d74191a | 9177 | if (ctxt->have_exception) { |
0dc90226 SC |
9178 | WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write); |
9179 | vcpu->mmio_needed = false; | |
60fc3d02 | 9180 | r = 1; |
7709aba8 | 9181 | inject_emulated_exception(vcpu); |
d2ddd1c4 | 9182 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
9183 | if (!vcpu->arch.pio.in) { |
9184 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 9185 | vcpu->arch.pio.count = 0; |
0912c977 | 9186 | } else { |
7ae441ea | 9187 | writeback = false; |
716d51ab GN |
9188 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
9189 | } | |
60fc3d02 | 9190 | r = 0; |
7ae441ea | 9191 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
9192 | ++vcpu->stat.mmio_exits; |
9193 | ||
7ae441ea GN |
9194 | if (!vcpu->mmio_is_write) |
9195 | writeback = false; | |
60fc3d02 | 9196 | r = 0; |
716d51ab | 9197 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
adbfb12d HW |
9198 | } else if (vcpu->arch.complete_userspace_io) { |
9199 | writeback = false; | |
9200 | r = 0; | |
7ae441ea | 9201 | } else if (r == EMULATION_RESTART) |
5cd21917 | 9202 | goto restart; |
d2ddd1c4 | 9203 | else |
60fc3d02 | 9204 | r = 1; |
f850e2e6 | 9205 | |
906fa904 | 9206 | writeback: |
7ae441ea | 9207 | if (writeback) { |
b3646477 | 9208 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
9d74191a | 9209 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 9210 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
5623f751 SC |
9211 | |
9212 | /* | |
9213 | * Note, EXCPT_DB is assumed to be fault-like as the emulator | |
9214 | * only supports code breakpoints and general detect #DB, both | |
9215 | * of which are fault-like. | |
9216 | */ | |
38827dbd | 9217 | if (!ctxt->have_exception || |
75ee23b3 | 9218 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
f19063b1 | 9219 | kvm_pmu_trigger_event(vcpu, kvm_pmu_eventsel.INSTRUCTIONS_RETIRED); |
018d70ff | 9220 | if (ctxt->is_branch) |
f19063b1 | 9221 | kvm_pmu_trigger_event(vcpu, kvm_pmu_eventsel.BRANCH_INSTRUCTIONS_RETIRED); |
75ee23b3 | 9222 | kvm_rip_write(vcpu, ctxt->eip); |
384dea1c | 9223 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 9224 | r = kvm_vcpu_do_singlestep(vcpu); |
2a890614 | 9225 | static_call_cond(kvm_x86_update_emulated_instruction)(vcpu); |
38827dbd | 9226 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 9227 | } |
6addfc42 PB |
9228 | |
9229 | /* | |
9230 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
9231 | * do nothing, and it will be requested again as soon as | |
9232 | * the shadow expires. But we still need to check here, | |
9233 | * because POPF has no interrupt shadow. | |
9234 | */ | |
9235 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
9236 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
9237 | } else |
9238 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
9239 | |
9240 | return r; | |
de7d789a | 9241 | } |
c60658d1 SC |
9242 | |
9243 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
9244 | { | |
9245 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
9246 | } | |
9247 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
9248 | ||
9249 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
9250 | void *insn, int insn_len) | |
9251 | { | |
9252 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
9253 | } | |
9254 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 9255 | |
8764ed55 SC |
9256 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
9257 | { | |
9258 | vcpu->arch.pio.count = 0; | |
9259 | return 1; | |
9260 | } | |
9261 | ||
45def77e SC |
9262 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
9263 | { | |
9264 | vcpu->arch.pio.count = 0; | |
9265 | ||
9266 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
9267 | return 1; | |
9268 | ||
9269 | return kvm_skip_emulated_instruction(vcpu); | |
9270 | } | |
9271 | ||
dca7f128 SC |
9272 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
9273 | unsigned short port) | |
de7d789a | 9274 | { |
de3cd117 | 9275 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
9276 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
9277 | ||
8764ed55 SC |
9278 | if (ret) |
9279 | return ret; | |
45def77e | 9280 | |
8764ed55 SC |
9281 | /* |
9282 | * Workaround userspace that relies on old KVM behavior of %rip being | |
9283 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
9284 | */ | |
9285 | if (port == 0x7e && | |
9286 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
9287 | vcpu->arch.complete_userspace_io = | |
9288 | complete_fast_pio_out_port_0x7e; | |
9289 | kvm_skip_emulated_instruction(vcpu); | |
9290 | } else { | |
45def77e SC |
9291 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
9292 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
9293 | } | |
8764ed55 | 9294 | return 0; |
de7d789a | 9295 | } |
de7d789a | 9296 | |
8370c3d0 TL |
9297 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
9298 | { | |
9299 | unsigned long val; | |
9300 | ||
9301 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
9302 | BUG_ON(vcpu->arch.pio.count != 1); | |
9303 | ||
45def77e SC |
9304 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
9305 | vcpu->arch.pio.count = 0; | |
9306 | return 1; | |
9307 | } | |
9308 | ||
8370c3d0 | 9309 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 9310 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 9311 | |
7a6177d6 | 9312 | complete_emulator_pio_in(vcpu, &val); |
de3cd117 | 9313 | kvm_rax_write(vcpu, val); |
8370c3d0 | 9314 | |
45def77e | 9315 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
9316 | } |
9317 | ||
dca7f128 SC |
9318 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
9319 | unsigned short port) | |
8370c3d0 TL |
9320 | { |
9321 | unsigned long val; | |
9322 | int ret; | |
9323 | ||
9324 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 9325 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 9326 | |
2e3bb4d8 | 9327 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 9328 | if (ret) { |
de3cd117 | 9329 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
9330 | return ret; |
9331 | } | |
9332 | ||
45def77e | 9333 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
9334 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
9335 | ||
9336 | return 0; | |
9337 | } | |
dca7f128 SC |
9338 | |
9339 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
9340 | { | |
45def77e | 9341 | int ret; |
dca7f128 | 9342 | |
dca7f128 | 9343 | if (in) |
45def77e | 9344 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 9345 | else |
45def77e SC |
9346 | ret = kvm_fast_pio_out(vcpu, size, port); |
9347 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
9348 | } |
9349 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 9350 | |
251a5fd6 | 9351 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 9352 | { |
0a3aee0d | 9353 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 9354 | return 0; |
8cfdc000 ZA |
9355 | } |
9356 | ||
9357 | static void tsc_khz_changed(void *data) | |
c8076604 | 9358 | { |
8cfdc000 | 9359 | struct cpufreq_freqs *freq = data; |
392a5324 | 9360 | unsigned long khz; |
8cfdc000 | 9361 | |
3ebcbd22 AR |
9362 | WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC)); |
9363 | ||
8cfdc000 ZA |
9364 | if (data) |
9365 | khz = freq->new; | |
3ebcbd22 | 9366 | else |
8cfdc000 ZA |
9367 | khz = cpufreq_quick_get(raw_smp_processor_id()); |
9368 | if (!khz) | |
9369 | khz = tsc_khz; | |
0a3aee0d | 9370 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
9371 | } |
9372 | ||
5fa4ec9c | 9373 | #ifdef CONFIG_X86_64 |
0092e434 VK |
9374 | static void kvm_hyperv_tsc_notifier(void) |
9375 | { | |
0092e434 | 9376 | struct kvm *kvm; |
0092e434 VK |
9377 | int cpu; |
9378 | ||
0d9ce162 | 9379 | mutex_lock(&kvm_lock); |
0092e434 VK |
9380 | list_for_each_entry(kvm, &vm_list, vm_list) |
9381 | kvm_make_mclock_inprogress_request(kvm); | |
9382 | ||
6b6fcd28 | 9383 | /* no guest entries from this point */ |
0092e434 VK |
9384 | hyperv_stop_tsc_emulation(); |
9385 | ||
9386 | /* TSC frequency always matches when on Hyper-V */ | |
3ebcbd22 AR |
9387 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
9388 | for_each_present_cpu(cpu) | |
9389 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
9390 | } | |
938c8745 | 9391 | kvm_caps.max_guest_tsc_khz = tsc_khz; |
0092e434 VK |
9392 | |
9393 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
869b4421 | 9394 | __kvm_start_pvclock_update(kvm); |
0092e434 | 9395 | pvclock_update_vm_gtod_copy(kvm); |
6b6fcd28 | 9396 | kvm_end_pvclock_update(kvm); |
0092e434 | 9397 | } |
6b6fcd28 | 9398 | |
0d9ce162 | 9399 | mutex_unlock(&kvm_lock); |
0092e434 | 9400 | } |
5fa4ec9c | 9401 | #endif |
0092e434 | 9402 | |
df24014a | 9403 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 9404 | { |
c8076604 GH |
9405 | struct kvm *kvm; |
9406 | struct kvm_vcpu *vcpu; | |
46808a4c MZ |
9407 | int send_ipi = 0; |
9408 | unsigned long i; | |
c8076604 | 9409 | |
8cfdc000 ZA |
9410 | /* |
9411 | * We allow guests to temporarily run on slowing clocks, | |
9412 | * provided we notify them after, or to run on accelerating | |
9413 | * clocks, provided we notify them before. Thus time never | |
9414 | * goes backwards. | |
9415 | * | |
9416 | * However, we have a problem. We can't atomically update | |
9417 | * the frequency of a given CPU from this function; it is | |
9418 | * merely a notifier, which can be called from any CPU. | |
9419 | * Changing the TSC frequency at arbitrary points in time | |
9420 | * requires a recomputation of local variables related to | |
9421 | * the TSC for each VCPU. We must flag these local variables | |
9422 | * to be updated and be sure the update takes place with the | |
9423 | * new frequency before any guests proceed. | |
9424 | * | |
9425 | * Unfortunately, the combination of hotplug CPU and frequency | |
9426 | * change creates an intractable locking scenario; the order | |
9427 | * of when these callouts happen is undefined with respect to | |
9428 | * CPU hotplug, and they can race with each other. As such, | |
9429 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
9430 | * undefined; you can actually have a CPU frequency change take | |
9431 | * place in between the computation of X and the setting of the | |
9432 | * variable. To protect against this problem, all updates of | |
9433 | * the per_cpu tsc_khz variable are done in an interrupt | |
9434 | * protected IPI, and all callers wishing to update the value | |
9435 | * must wait for a synchronous IPI to complete (which is trivial | |
9436 | * if the caller is on the CPU already). This establishes the | |
9437 | * necessary total order on variable updates. | |
9438 | * | |
9439 | * Note that because a guest time update may take place | |
9440 | * anytime after the setting of the VCPU's request bit, the | |
9441 | * correct TSC value must be set before the request. However, | |
9442 | * to ensure the update actually makes it to any guest which | |
9443 | * starts running in hardware virtualization between the set | |
9444 | * and the acquisition of the spinlock, we must also ping the | |
9445 | * CPU after setting the request bit. | |
9446 | * | |
9447 | */ | |
9448 | ||
df24014a | 9449 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 9450 | |
0d9ce162 | 9451 | mutex_lock(&kvm_lock); |
c8076604 | 9452 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 9453 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 9454 | if (vcpu->cpu != cpu) |
c8076604 | 9455 | continue; |
c285545f | 9456 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 9457 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 9458 | send_ipi = 1; |
c8076604 GH |
9459 | } |
9460 | } | |
0d9ce162 | 9461 | mutex_unlock(&kvm_lock); |
c8076604 GH |
9462 | |
9463 | if (freq->old < freq->new && send_ipi) { | |
9464 | /* | |
9465 | * We upscale the frequency. Must make the guest | |
9466 | * doesn't see old kvmclock values while running with | |
9467 | * the new frequency, otherwise we risk the guest sees | |
9468 | * time go backwards. | |
9469 | * | |
9470 | * In case we update the frequency for another cpu | |
9471 | * (which might be in guest context) send an interrupt | |
9472 | * to kick the cpu out of guest context. Next time | |
9473 | * guest context is entered kvmclock will be updated, | |
9474 | * so the guest will not see stale values. | |
9475 | */ | |
df24014a | 9476 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 9477 | } |
df24014a VK |
9478 | } |
9479 | ||
9480 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
9481 | void *data) | |
9482 | { | |
9483 | struct cpufreq_freqs *freq = data; | |
9484 | int cpu; | |
9485 | ||
9486 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
9487 | return 0; | |
9488 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
9489 | return 0; | |
9490 | ||
9491 | for_each_cpu(cpu, freq->policy->cpus) | |
9492 | __kvmclock_cpufreq_notifier(freq, cpu); | |
9493 | ||
c8076604 GH |
9494 | return 0; |
9495 | } | |
9496 | ||
9497 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
9498 | .notifier_call = kvmclock_cpufreq_notifier |
9499 | }; | |
9500 | ||
251a5fd6 | 9501 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 9502 | { |
251a5fd6 SAS |
9503 | tsc_khz_changed(NULL); |
9504 | return 0; | |
8cfdc000 ZA |
9505 | } |
9506 | ||
b820cc0c ZA |
9507 | static void kvm_timer_init(void) |
9508 | { | |
b820cc0c | 9509 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
741e511b SC |
9510 | max_tsc_khz = tsc_khz; |
9511 | ||
9512 | if (IS_ENABLED(CONFIG_CPU_FREQ)) { | |
9513 | struct cpufreq_policy *policy; | |
9514 | int cpu; | |
9515 | ||
9516 | cpu = get_cpu(); | |
9517 | policy = cpufreq_cpu_get(cpu); | |
9518 | if (policy) { | |
9519 | if (policy->cpuinfo.max_freq) | |
9520 | max_tsc_khz = policy->cpuinfo.max_freq; | |
9521 | cpufreq_cpu_put(policy); | |
9522 | } | |
9523 | put_cpu(); | |
9a11997e | 9524 | } |
b820cc0c ZA |
9525 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
9526 | CPUFREQ_TRANSITION_NOTIFIER); | |
460dd42e | 9527 | |
3ebcbd22 AR |
9528 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
9529 | kvmclock_cpu_online, kvmclock_cpu_down_prep); | |
9530 | } | |
b820cc0c ZA |
9531 | } |
9532 | ||
16e8d74d MT |
9533 | #ifdef CONFIG_X86_64 |
9534 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
9535 | { | |
d828199e | 9536 | struct kvm *kvm; |
d828199e | 9537 | struct kvm_vcpu *vcpu; |
46808a4c | 9538 | unsigned long i; |
d828199e | 9539 | |
0d9ce162 | 9540 | mutex_lock(&kvm_lock); |
d828199e MT |
9541 | list_for_each_entry(kvm, &vm_list, vm_list) |
9542 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 9543 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 9544 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 9545 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
9546 | } |
9547 | ||
9548 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
9549 | ||
3f804f6d TG |
9550 | /* |
9551 | * Indirection to move queue_work() out of the tk_core.seq write held | |
9552 | * region to prevent possible deadlocks against time accessors which | |
9553 | * are invoked with work related locks held. | |
9554 | */ | |
9555 | static void pvclock_irq_work_fn(struct irq_work *w) | |
9556 | { | |
9557 | queue_work(system_long_wq, &pvclock_gtod_work); | |
9558 | } | |
9559 | ||
9560 | static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); | |
9561 | ||
16e8d74d MT |
9562 | /* |
9563 | * Notification about pvclock gtod data update. | |
9564 | */ | |
9565 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
9566 | void *priv) | |
9567 | { | |
9568 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
9569 | struct timekeeper *tk = priv; | |
9570 | ||
9571 | update_pvclock_gtod(tk); | |
9572 | ||
3f804f6d TG |
9573 | /* |
9574 | * Disable master clock if host does not trust, or does not use, | |
9575 | * TSC based clocksource. Delegate queue_work() to irq_work as | |
9576 | * this is invoked with tk_core.seq write held. | |
16e8d74d | 9577 | */ |
b0c39dc6 | 9578 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d | 9579 | atomic_read(&kvm_guest_has_master_clock) != 0) |
3f804f6d | 9580 | irq_work_queue(&pvclock_irq_work); |
16e8d74d MT |
9581 | return 0; |
9582 | } | |
9583 | ||
9584 | static struct notifier_block pvclock_gtod_notifier = { | |
9585 | .notifier_call = pvclock_gtod_notify, | |
9586 | }; | |
9587 | #endif | |
9588 | ||
b7483387 SC |
9589 | static inline void kvm_ops_update(struct kvm_x86_init_ops *ops) |
9590 | { | |
9591 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); | |
9592 | ||
9593 | #define __KVM_X86_OP(func) \ | |
9594 | static_call_update(kvm_x86_##func, kvm_x86_ops.func); | |
9595 | #define KVM_X86_OP(func) \ | |
9596 | WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func) | |
9597 | #define KVM_X86_OP_OPTIONAL __KVM_X86_OP | |
9598 | #define KVM_X86_OP_OPTIONAL_RET0(func) \ | |
9599 | static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \ | |
9600 | (void *)__static_call_return0); | |
9601 | #include <asm/kvm-x86-ops.h> | |
9602 | #undef __KVM_X86_OP | |
9603 | ||
9604 | kvm_pmu_ops_update(ops->pmu_ops); | |
9605 | } | |
9606 | ||
d83420c2 | 9607 | static int kvm_x86_check_processor_compatibility(void) |
3045c483 | 9608 | { |
e4aa7f88 CG |
9609 | int cpu = smp_processor_id(); |
9610 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
9611 | ||
9612 | /* | |
9613 | * Compatibility checks are done when loading KVM and when enabling | |
9614 | * hardware, e.g. during CPU hotplug, to ensure all online CPUs are | |
9615 | * compatible, i.e. KVM should never perform a compatibility check on | |
9616 | * an offline CPU. | |
9617 | */ | |
9618 | WARN_ON(!cpu_online(cpu)); | |
3045c483 | 9619 | |
3045c483 SC |
9620 | if (__cr4_reserved_bits(cpu_has, c) != |
9621 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
9622 | return -EIO; | |
9623 | ||
d83420c2 | 9624 | return static_call(kvm_x86_check_processor_compatibility)(); |
3045c483 SC |
9625 | } |
9626 | ||
d83420c2 | 9627 | static void kvm_x86_check_cpu_compat(void *ret) |
3045c483 | 9628 | { |
d83420c2 | 9629 | *(int *)ret = kvm_x86_check_processor_compatibility(); |
3045c483 SC |
9630 | } |
9631 | ||
3af4a9e6 | 9632 | static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops) |
043405e1 | 9633 | { |
94bda2f4 | 9634 | u64 host_pat; |
3045c483 | 9635 | int r, cpu; |
f8c16bba | 9636 | |
afaf0b2f | 9637 | if (kvm_x86_ops.hardware_enable) { |
8d20bd63 | 9638 | pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name); |
82ffad2d | 9639 | return -EEXIST; |
f8c16bba ZX |
9640 | } |
9641 | ||
b666a4b6 MO |
9642 | /* |
9643 | * KVM explicitly assumes that the guest has an FPU and | |
9644 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
9645 | * vCPU's FPU state as a fxregs_state struct. | |
9646 | */ | |
9647 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
8d20bd63 | 9648 | pr_err("inadequate fpu\n"); |
82ffad2d | 9649 | return -EOPNOTSUPP; |
b666a4b6 MO |
9650 | } |
9651 | ||
5e17b2ee TG |
9652 | if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
9653 | pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n"); | |
82ffad2d | 9654 | return -EOPNOTSUPP; |
b666a4b6 MO |
9655 | } |
9656 | ||
94bda2f4 SC |
9657 | /* |
9658 | * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes | |
9659 | * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something | |
9660 | * other than WB. Note, EPT doesn't utilize the PAT, but don't bother | |
9661 | * with an exception. PAT[0] is set to WB on RESET and also by the | |
9662 | * kernel, i.e. failure indicates a kernel bug or broken firmware. | |
9663 | */ | |
9664 | if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) || | |
9665 | (host_pat & GENMASK(2, 0)) != 6) { | |
8d20bd63 | 9666 | pr_err("host PAT[0] is not WB\n"); |
82ffad2d | 9667 | return -EIO; |
94bda2f4 | 9668 | } |
b666a4b6 | 9669 | |
c9b8b07c SC |
9670 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
9671 | if (!x86_emulator_cache) { | |
8d20bd63 | 9672 | pr_err("failed to allocate cache for x86 emulator\n"); |
82ffad2d | 9673 | return -ENOMEM; |
c9b8b07c SC |
9674 | } |
9675 | ||
7e34fbd0 SC |
9676 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
9677 | if (!user_return_msrs) { | |
8d20bd63 | 9678 | pr_err("failed to allocate percpu kvm_user_return_msrs\n"); |
82ffad2d | 9679 | r = -ENOMEM; |
c9b8b07c | 9680 | goto out_free_x86_emulator_cache; |
013f6a5d | 9681 | } |
e5fda4bb | 9682 | kvm_nr_uret_msrs = 0; |
013f6a5d | 9683 | |
1d0e8480 | 9684 | r = kvm_mmu_vendor_module_init(); |
97db56ce | 9685 | if (r) |
013f6a5d | 9686 | goto out_free_percpu; |
97db56ce | 9687 | |
cfc48181 | 9688 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 9689 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
938c8745 | 9690 | kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
cfc48181 | 9691 | } |
2acf923e | 9692 | |
b7483387 SC |
9693 | rdmsrl_safe(MSR_EFER, &host_efer); |
9694 | ||
9695 | if (boot_cpu_has(X86_FEATURE_XSAVES)) | |
9696 | rdmsrl(MSR_IA32_XSS, host_xss); | |
9697 | ||
8911ce66 | 9698 | kvm_init_pmu_capability(ops->pmu_ops); |
b7483387 | 9699 | |
a2fd5d02 SC |
9700 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
9701 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, host_arch_capabilities); | |
9702 | ||
b7483387 SC |
9703 | r = ops->hardware_setup(); |
9704 | if (r != 0) | |
9705 | goto out_mmu_exit; | |
9706 | ||
d83420c2 SC |
9707 | kvm_ops_update(ops); |
9708 | ||
3045c483 | 9709 | for_each_online_cpu(cpu) { |
d83420c2 | 9710 | smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1); |
3045c483 | 9711 | if (r < 0) |
d83420c2 | 9712 | goto out_unwind_ops; |
3045c483 SC |
9713 | } |
9714 | ||
b7483387 SC |
9715 | /* |
9716 | * Point of no return! DO NOT add error paths below this point unless | |
9717 | * absolutely necessary, as most operations from this point forward | |
9718 | * require unwinding. | |
9719 | */ | |
1935542a SC |
9720 | kvm_timer_init(); |
9721 | ||
0c5f81da | 9722 | if (pi_inject_timer == -1) |
04d4e665 | 9723 | pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER); |
16e8d74d MT |
9724 | #ifdef CONFIG_X86_64 |
9725 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 9726 | |
5fa4ec9c | 9727 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 9728 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
9729 | #endif |
9730 | ||
b7483387 SC |
9731 | kvm_register_perf_callbacks(ops->handle_intel_pt_intr); |
9732 | ||
9733 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) | |
9734 | kvm_caps.supported_xss = 0; | |
9735 | ||
9736 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) | |
9737 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
9738 | #undef __kvm_cpu_cap_has | |
9739 | ||
9740 | if (kvm_caps.has_tsc_control) { | |
9741 | /* | |
9742 | * Make sure the user can only configure tsc_khz values that | |
9743 | * fit into a signed integer. | |
9744 | * A min value is not calculated because it will always | |
9745 | * be 1 on all machines. | |
9746 | */ | |
9747 | u64 max = min(0x7fffffffULL, | |
9748 | __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz)); | |
9749 | kvm_caps.max_guest_tsc_khz = max; | |
9750 | } | |
9751 | kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits; | |
b1932c5c | 9752 | kvm_init_msr_lists(); |
f8c16bba | 9753 | return 0; |
56c6d28a | 9754 | |
d83420c2 SC |
9755 | out_unwind_ops: |
9756 | kvm_x86_ops.hardware_enable = NULL; | |
9757 | static_call(kvm_x86_hardware_unsetup)(); | |
b7483387 SC |
9758 | out_mmu_exit: |
9759 | kvm_mmu_vendor_module_exit(); | |
013f6a5d | 9760 | out_free_percpu: |
7e34fbd0 | 9761 | free_percpu(user_return_msrs); |
c9b8b07c SC |
9762 | out_free_x86_emulator_cache: |
9763 | kmem_cache_destroy(x86_emulator_cache); | |
56c6d28a | 9764 | return r; |
043405e1 | 9765 | } |
8776e519 | 9766 | |
3af4a9e6 SC |
9767 | int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops) |
9768 | { | |
9769 | int r; | |
9770 | ||
9771 | mutex_lock(&vendor_module_lock); | |
9772 | r = __kvm_x86_vendor_init(ops); | |
9773 | mutex_unlock(&vendor_module_lock); | |
9774 | ||
9775 | return r; | |
9776 | } | |
4f8396b9 | 9777 | EXPORT_SYMBOL_GPL(kvm_x86_vendor_init); |
8776e519 | 9778 | |
4f8396b9 | 9779 | void kvm_x86_vendor_exit(void) |
f8c16bba | 9780 | { |
b7483387 SC |
9781 | kvm_unregister_perf_callbacks(); |
9782 | ||
0092e434 | 9783 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 9784 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
9785 | clear_hv_tscchange_cb(); |
9786 | #endif | |
cef84c30 | 9787 | kvm_lapic_exit(); |
ff9d07a0 | 9788 | |
3ebcbd22 | 9789 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
888d256e JK |
9790 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, |
9791 | CPUFREQ_TRANSITION_NOTIFIER); | |
3ebcbd22 AR |
9792 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
9793 | } | |
16e8d74d MT |
9794 | #ifdef CONFIG_X86_64 |
9795 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
3f804f6d | 9796 | irq_work_sync(&pvclock_irq_work); |
594b27e6 | 9797 | cancel_work_sync(&pvclock_gtod_work); |
16e8d74d | 9798 | #endif |
b7483387 | 9799 | static_call(kvm_x86_hardware_unsetup)(); |
1d0e8480 | 9800 | kvm_mmu_vendor_module_exit(); |
7e34fbd0 | 9801 | free_percpu(user_return_msrs); |
dfdc0a71 | 9802 | kmem_cache_destroy(x86_emulator_cache); |
b59b153d | 9803 | #ifdef CONFIG_KVM_XEN |
c462f859 | 9804 | static_key_deferred_flush(&kvm_xen_enabled); |
7d6bbebb | 9805 | WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); |
b59b153d | 9806 | #endif |
3af4a9e6 SC |
9807 | mutex_lock(&vendor_module_lock); |
9808 | kvm_x86_ops.hardware_enable = NULL; | |
9809 | mutex_unlock(&vendor_module_lock); | |
56c6d28a | 9810 | } |
4f8396b9 | 9811 | EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit); |
f8c16bba | 9812 | |
1460179d | 9813 | static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 | 9814 | { |
91b99ea7 SC |
9815 | /* |
9816 | * The vCPU has halted, e.g. executed HLT. Update the run state if the | |
9817 | * local APIC is in-kernel, the run loop will detect the non-runnable | |
9818 | * state and halt the vCPU. Exit to userspace if the local APIC is | |
9819 | * managed by userspace, in which case userspace is responsible for | |
9820 | * handling wake events. | |
9821 | */ | |
8776e519 | 9822 | ++vcpu->stat.halt_exits; |
35754c98 | 9823 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 9824 | vcpu->arch.mp_state = state; |
8776e519 HB |
9825 | return 1; |
9826 | } else { | |
647daca2 | 9827 | vcpu->run->exit_reason = reason; |
8776e519 HB |
9828 | return 0; |
9829 | } | |
9830 | } | |
647daca2 | 9831 | |
1460179d | 9832 | int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) |
647daca2 | 9833 | { |
1460179d | 9834 | return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); |
647daca2 | 9835 | } |
1460179d | 9836 | EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); |
5cb56059 JS |
9837 | |
9838 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
9839 | { | |
6affcbed KH |
9840 | int ret = kvm_skip_emulated_instruction(vcpu); |
9841 | /* | |
9842 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
9843 | * KVM_EXIT_DEBUG here. | |
9844 | */ | |
1460179d | 9845 | return kvm_emulate_halt_noskip(vcpu) && ret; |
5cb56059 | 9846 | } |
8776e519 HB |
9847 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
9848 | ||
647daca2 TL |
9849 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
9850 | { | |
9851 | int ret = kvm_skip_emulated_instruction(vcpu); | |
9852 | ||
1460179d SC |
9853 | return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, |
9854 | KVM_EXIT_AP_RESET_HOLD) && ret; | |
647daca2 TL |
9855 | } |
9856 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
9857 | ||
8ef81a9a | 9858 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
9859 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
9860 | unsigned long clock_type) | |
9861 | { | |
9862 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 9863 | struct timespec64 ts; |
80fbd89c | 9864 | u64 cycle; |
55dd00a7 MT |
9865 | int ret; |
9866 | ||
9867 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
9868 | return -KVM_EOPNOTSUPP; | |
9869 | ||
3a55f729 AR |
9870 | /* |
9871 | * When tsc is in permanent catchup mode guests won't be able to use | |
9872 | * pvclock_read_retry loop to get consistent view of pvclock | |
9873 | */ | |
9874 | if (vcpu->arch.tsc_always_catchup) | |
9875 | return -KVM_EOPNOTSUPP; | |
9876 | ||
7ca7f3b9 | 9877 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
9878 | return -KVM_EOPNOTSUPP; |
9879 | ||
9880 | clock_pairing.sec = ts.tv_sec; | |
9881 | clock_pairing.nsec = ts.tv_nsec; | |
9882 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
9883 | clock_pairing.flags = 0; | |
bcbfbd8e | 9884 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
9885 | |
9886 | ret = 0; | |
9887 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
9888 | sizeof(struct kvm_clock_pairing))) | |
9889 | ret = -KVM_EFAULT; | |
9890 | ||
9891 | return ret; | |
9892 | } | |
8ef81a9a | 9893 | #endif |
55dd00a7 | 9894 | |
6aef266c SV |
9895 | /* |
9896 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
9897 | * | |
9898 | * @apicid - apicid of vcpu to be kicked. | |
9899 | */ | |
9d68c6f6 | 9900 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid) |
6aef266c | 9901 | { |
8a414f94 VK |
9902 | /* |
9903 | * All other fields are unused for APIC_DM_REMRD, but may be consumed by | |
9904 | * common code, e.g. for tracing. Defer initialization to the compiler. | |
9905 | */ | |
9906 | struct kvm_lapic_irq lapic_irq = { | |
9907 | .delivery_mode = APIC_DM_REMRD, | |
9908 | .dest_mode = APIC_DEST_PHYSICAL, | |
9909 | .shorthand = APIC_DEST_NOSHORT, | |
9910 | .dest_id = apicid, | |
9911 | }; | |
6aef266c | 9912 | |
795a149e | 9913 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
9914 | } |
9915 | ||
4e19c36f SS |
9916 | bool kvm_apicv_activated(struct kvm *kvm) |
9917 | { | |
9918 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
9919 | } | |
9920 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
9921 | ||
d5fa597e ML |
9922 | bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu) |
9923 | { | |
9924 | ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons); | |
9925 | ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu); | |
9926 | ||
9927 | return (vm_reasons | vcpu_reasons) == 0; | |
9928 | } | |
9929 | EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated); | |
4f4c4a3e SC |
9930 | |
9931 | static void set_or_clear_apicv_inhibit(unsigned long *inhibits, | |
9932 | enum kvm_apicv_inhibit reason, bool set) | |
9933 | { | |
9934 | if (set) | |
9935 | __set_bit(reason, inhibits); | |
9936 | else | |
9937 | __clear_bit(reason, inhibits); | |
9938 | ||
9939 | trace_kvm_apicv_inhibit_changed(reason, set, *inhibits); | |
9940 | } | |
9941 | ||
4651fc56 | 9942 | static void kvm_apicv_init(struct kvm *kvm) |
4e19c36f | 9943 | { |
4f4c4a3e SC |
9944 | unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons; |
9945 | ||
187c8833 | 9946 | init_rwsem(&kvm->arch.apicv_update_lock); |
b0a1637f | 9947 | |
4f4c4a3e SC |
9948 | set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true); |
9949 | ||
ef8b4b72 | 9950 | if (!enable_apicv) |
4f4c4a3e | 9951 | set_or_clear_apicv_inhibit(inhibits, |
80f0497c | 9952 | APICV_INHIBIT_REASON_DISABLE, true); |
4e19c36f | 9953 | } |
4e19c36f | 9954 | |
4a7132ef | 9955 | static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) |
71506297 WL |
9956 | { |
9957 | struct kvm_vcpu *target = NULL; | |
9958 | struct kvm_apic_map *map; | |
9959 | ||
4a7132ef WL |
9960 | vcpu->stat.directed_yield_attempted++; |
9961 | ||
72b268a8 WL |
9962 | if (single_task_running()) |
9963 | goto no_yield; | |
9964 | ||
71506297 | 9965 | rcu_read_lock(); |
4a7132ef | 9966 | map = rcu_dereference(vcpu->kvm->arch.apic_map); |
71506297 WL |
9967 | |
9968 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
9969 | target = map->phys_map[dest_id]->vcpu; | |
9970 | ||
9971 | rcu_read_unlock(); | |
9972 | ||
4a7132ef WL |
9973 | if (!target || !READ_ONCE(target->ready)) |
9974 | goto no_yield; | |
9975 | ||
a1fa4cbd WL |
9976 | /* Ignore requests to yield to self */ |
9977 | if (vcpu == target) | |
9978 | goto no_yield; | |
9979 | ||
4a7132ef WL |
9980 | if (kvm_vcpu_yield_to(target) <= 0) |
9981 | goto no_yield; | |
9982 | ||
9983 | vcpu->stat.directed_yield_successful++; | |
9984 | ||
9985 | no_yield: | |
9986 | return; | |
71506297 WL |
9987 | } |
9988 | ||
0dbb1123 AK |
9989 | static int complete_hypercall_exit(struct kvm_vcpu *vcpu) |
9990 | { | |
9991 | u64 ret = vcpu->run->hypercall.ret; | |
9992 | ||
9993 | if (!is_64_bit_mode(vcpu)) | |
9994 | ret = (u32)ret; | |
9995 | kvm_rax_write(vcpu, ret); | |
9996 | ++vcpu->stat.hypercalls; | |
9997 | return kvm_skip_emulated_instruction(vcpu); | |
9998 | } | |
9999 | ||
8776e519 HB |
10000 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
10001 | { | |
10002 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 10003 | int op_64_bit; |
8776e519 | 10004 | |
23200b7a JM |
10005 | if (kvm_xen_hypercall_enabled(vcpu->kvm)) |
10006 | return kvm_xen_hypercall(vcpu); | |
10007 | ||
8f014550 | 10008 | if (kvm_hv_hypercall_enabled(vcpu)) |
696ca779 | 10009 | return kvm_hv_hypercall(vcpu); |
55cd8e5a | 10010 | |
de3cd117 SC |
10011 | nr = kvm_rax_read(vcpu); |
10012 | a0 = kvm_rbx_read(vcpu); | |
10013 | a1 = kvm_rcx_read(vcpu); | |
10014 | a2 = kvm_rdx_read(vcpu); | |
10015 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 10016 | |
229456fc | 10017 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 10018 | |
b5aead00 | 10019 | op_64_bit = is_64_bit_hypercall(vcpu); |
a449c7aa | 10020 | if (!op_64_bit) { |
8776e519 HB |
10021 | nr &= 0xFFFFFFFF; |
10022 | a0 &= 0xFFFFFFFF; | |
10023 | a1 &= 0xFFFFFFFF; | |
10024 | a2 &= 0xFFFFFFFF; | |
10025 | a3 &= 0xFFFFFFFF; | |
10026 | } | |
10027 | ||
b3646477 | 10028 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { |
07708c4a | 10029 | ret = -KVM_EPERM; |
696ca779 | 10030 | goto out; |
07708c4a JK |
10031 | } |
10032 | ||
66570e96 OU |
10033 | ret = -KVM_ENOSYS; |
10034 | ||
8776e519 | 10035 | switch (nr) { |
b93463aa AK |
10036 | case KVM_HC_VAPIC_POLL_IRQ: |
10037 | ret = 0; | |
10038 | break; | |
6aef266c | 10039 | case KVM_HC_KICK_CPU: |
66570e96 OU |
10040 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
10041 | break; | |
10042 | ||
9d68c6f6 | 10043 | kvm_pv_kick_cpu_op(vcpu->kvm, a1); |
4a7132ef | 10044 | kvm_sched_yield(vcpu, a1); |
6aef266c SV |
10045 | ret = 0; |
10046 | break; | |
8ef81a9a | 10047 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
10048 | case KVM_HC_CLOCK_PAIRING: |
10049 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
10050 | break; | |
1ed199a4 | 10051 | #endif |
4180bf1b | 10052 | case KVM_HC_SEND_IPI: |
66570e96 OU |
10053 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
10054 | break; | |
10055 | ||
4180bf1b WL |
10056 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
10057 | break; | |
71506297 | 10058 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
10059 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
10060 | break; | |
10061 | ||
4a7132ef | 10062 | kvm_sched_yield(vcpu, a0); |
71506297 WL |
10063 | ret = 0; |
10064 | break; | |
0dbb1123 AK |
10065 | case KVM_HC_MAP_GPA_RANGE: { |
10066 | u64 gpa = a0, npages = a1, attrs = a2; | |
10067 | ||
10068 | ret = -KVM_ENOSYS; | |
10069 | if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) | |
10070 | break; | |
10071 | ||
10072 | if (!PAGE_ALIGNED(gpa) || !npages || | |
10073 | gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { | |
10074 | ret = -KVM_EINVAL; | |
10075 | break; | |
10076 | } | |
10077 | ||
10078 | vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; | |
10079 | vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; | |
10080 | vcpu->run->hypercall.args[0] = gpa; | |
10081 | vcpu->run->hypercall.args[1] = npages; | |
10082 | vcpu->run->hypercall.args[2] = attrs; | |
e65733b5 OU |
10083 | vcpu->run->hypercall.flags = 0; |
10084 | if (op_64_bit) | |
10085 | vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE; | |
10086 | ||
10087 | WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ); | |
0dbb1123 AK |
10088 | vcpu->arch.complete_userspace_io = complete_hypercall_exit; |
10089 | return 0; | |
10090 | } | |
8776e519 HB |
10091 | default: |
10092 | ret = -KVM_ENOSYS; | |
10093 | break; | |
10094 | } | |
696ca779 | 10095 | out: |
a449c7aa NA |
10096 | if (!op_64_bit) |
10097 | ret = (u32)ret; | |
de3cd117 | 10098 | kvm_rax_write(vcpu, ret); |
6356ee0c | 10099 | |
f11c3a8d | 10100 | ++vcpu->stat.hypercalls; |
6356ee0c | 10101 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
10102 | } |
10103 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
10104 | ||
b6785def | 10105 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 10106 | { |
d6aa1000 | 10107 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 10108 | char instruction[3]; |
5fdbf976 | 10109 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 10110 | |
f1a9761f OU |
10111 | /* |
10112 | * If the quirk is disabled, synthesize a #UD and let the guest pick up | |
10113 | * the pieces. | |
10114 | */ | |
10115 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) { | |
10116 | ctxt->exception.error_code_valid = false; | |
10117 | ctxt->exception.vector = UD_VECTOR; | |
10118 | ctxt->have_exception = true; | |
10119 | return X86EMUL_PROPAGATE_FAULT; | |
10120 | } | |
10121 | ||
b3646477 | 10122 | static_call(kvm_x86_patch_hypercall)(vcpu, instruction); |
8776e519 | 10123 | |
ce2e852e DV |
10124 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
10125 | &ctxt->exception); | |
8776e519 HB |
10126 | } |
10127 | ||
851ba692 | 10128 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 10129 | { |
782d422b MG |
10130 | return vcpu->run->request_interrupt_window && |
10131 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
10132 | } |
10133 | ||
8d25b7be | 10134 | /* Called within kvm->srcu read side. */ |
851ba692 | 10135 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 10136 | { |
851ba692 AK |
10137 | struct kvm_run *kvm_run = vcpu->run; |
10138 | ||
c5063551 | 10139 | kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); |
2d3ad1f4 | 10140 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 10141 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
f3d1436d | 10142 | |
127a457a MG |
10143 | kvm_run->ready_for_interrupt_injection = |
10144 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 10145 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
15aad3be CQ |
10146 | |
10147 | if (is_smm(vcpu)) | |
10148 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
10149 | } |
10150 | ||
95ba8273 GN |
10151 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
10152 | { | |
10153 | int max_irr, tpr; | |
10154 | ||
afaf0b2f | 10155 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
10156 | return; |
10157 | ||
bce87cce | 10158 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
10159 | return; |
10160 | ||
ce0a58f4 | 10161 | if (vcpu->arch.apic->apicv_active) |
d62caabb AS |
10162 | return; |
10163 | ||
8db3baa2 GN |
10164 | if (!vcpu->arch.apic->vapic_addr) |
10165 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
10166 | else | |
10167 | max_irr = -1; | |
95ba8273 GN |
10168 | |
10169 | if (max_irr != -1) | |
10170 | max_irr >>= 4; | |
10171 | ||
10172 | tpr = kvm_lapic_get_cr8(vcpu); | |
10173 | ||
b3646477 | 10174 | static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); |
95ba8273 GN |
10175 | } |
10176 | ||
b97f0745 | 10177 | |
cb6a32c2 SC |
10178 | int kvm_check_nested_events(struct kvm_vcpu *vcpu) |
10179 | { | |
92e7d5c8 | 10180 | if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
cb6a32c2 SC |
10181 | kvm_x86_ops.nested_ops->triple_fault(vcpu); |
10182 | return 1; | |
10183 | } | |
10184 | ||
10185 | return kvm_x86_ops.nested_ops->check_events(vcpu); | |
10186 | } | |
10187 | ||
b97f0745 ML |
10188 | static void kvm_inject_exception(struct kvm_vcpu *vcpu) |
10189 | { | |
6c41468c SC |
10190 | /* |
10191 | * Suppress the error code if the vCPU is in Real Mode, as Real Mode | |
10192 | * exceptions don't report error codes. The presence of an error code | |
10193 | * is carried with the exception and only stripped when the exception | |
10194 | * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do | |
10195 | * report an error code despite the CPU being in Real Mode. | |
10196 | */ | |
10197 | vcpu->arch.exception.has_error_code &= is_protmode(vcpu); | |
10198 | ||
d4963e31 | 10199 | trace_kvm_inj_exception(vcpu->arch.exception.vector, |
a61d7c54 SC |
10200 | vcpu->arch.exception.has_error_code, |
10201 | vcpu->arch.exception.error_code, | |
10202 | vcpu->arch.exception.injected); | |
10203 | ||
6ad75c5c | 10204 | static_call(kvm_x86_inject_exception)(vcpu); |
b97f0745 ML |
10205 | } |
10206 | ||
e746c1f1 SC |
10207 | /* |
10208 | * Check for any event (interrupt or exception) that is ready to be injected, | |
10209 | * and if there is at least one event, inject the event with the highest | |
10210 | * priority. This handles both "pending" events, i.e. events that have never | |
10211 | * been injected into the guest, and "injected" events, i.e. events that were | |
10212 | * injected as part of a previous VM-Enter, but weren't successfully delivered | |
10213 | * and need to be re-injected. | |
10214 | * | |
10215 | * Note, this is not guaranteed to be invoked on a guest instruction boundary, | |
10216 | * i.e. doesn't guarantee that there's an event window in the guest. KVM must | |
10217 | * be able to inject exceptions in the "middle" of an instruction, and so must | |
10218 | * also be able to re-inject NMIs and IRQs in the middle of an instruction. | |
10219 | * I.e. for exceptions and re-injected events, NOT invoking this on instruction | |
10220 | * boundaries is necessary and correct. | |
10221 | * | |
10222 | * For simplicity, KVM uses a single path to inject all events (except events | |
10223 | * that are injected directly from L1 to L2) and doesn't explicitly track | |
10224 | * instruction boundaries for asynchronous events. However, because VM-Exits | |
10225 | * that can occur during instruction execution typically result in KVM skipping | |
10226 | * the instruction or injecting an exception, e.g. instruction and exception | |
10227 | * intercepts, and because pending exceptions have higher priority than pending | |
10228 | * interrupts, KVM still honors instruction boundaries in most scenarios. | |
10229 | * | |
10230 | * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip | |
10231 | * the instruction or inject an exception, then KVM can incorrecty inject a new | |
54aa699e | 10232 | * asynchronous event if the event became pending after the CPU fetched the |
e746c1f1 SC |
10233 | * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation) |
10234 | * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be | |
10235 | * injected on the restarted instruction instead of being deferred until the | |
10236 | * instruction completes. | |
10237 | * | |
10238 | * In practice, this virtualization hole is unlikely to be observed by the | |
10239 | * guest, and even less likely to cause functional problems. To detect the | |
10240 | * hole, the guest would have to trigger an event on a side effect of an early | |
10241 | * phase of instruction execution, e.g. on the instruction fetch from memory. | |
10242 | * And for it to be a functional problem, the guest would need to depend on the | |
10243 | * ordering between that side effect, the instruction completing, _and_ the | |
10244 | * delivery of the asynchronous event. | |
10245 | */ | |
10246 | static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu, | |
10247 | bool *req_immediate_exit) | |
95ba8273 | 10248 | { |
28360f88 | 10249 | bool can_inject; |
b6b8a145 JK |
10250 | int r; |
10251 | ||
6c593b52 | 10252 | /* |
54aa699e | 10253 | * Process nested events first, as nested VM-Exit supersedes event |
6c593b52 SC |
10254 | * re-injection. If there's an event queued for re-injection, it will |
10255 | * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit. | |
10256 | */ | |
10257 | if (is_guest_mode(vcpu)) | |
10258 | r = kvm_check_nested_events(vcpu); | |
10259 | else | |
10260 | r = 0; | |
664f8e26 WL |
10261 | |
10262 | /* | |
6c593b52 SC |
10263 | * Re-inject exceptions and events *especially* if immediate entry+exit |
10264 | * to/from L2 is needed, as any event that has already been injected | |
10265 | * into L2 needs to complete its lifecycle before injecting a new event. | |
10266 | * | |
10267 | * Don't re-inject an NMI or interrupt if there is a pending exception. | |
10268 | * This collision arises if an exception occurred while vectoring the | |
10269 | * injected event, KVM intercepted said exception, and KVM ultimately | |
10270 | * determined the fault belongs to the guest and queues the exception | |
10271 | * for injection back into the guest. | |
10272 | * | |
10273 | * "Injected" interrupts can also collide with pending exceptions if | |
10274 | * userspace ignores the "ready for injection" flag and blindly queues | |
10275 | * an interrupt. In that case, prioritizing the exception is correct, | |
10276 | * as the exception "occurred" before the exit to userspace. Trap-like | |
10277 | * exceptions, e.g. most #DBs, have higher priority than interrupts. | |
10278 | * And while fault-like exceptions, e.g. #GP and #PF, are the lowest | |
10279 | * priority, they're only generated (pended) during instruction | |
10280 | * execution, and interrupts are recognized at instruction boundaries. | |
10281 | * Thus a pending fault-like exception means the fault occurred on the | |
10282 | * *previous* instruction and must be serviced prior to recognizing any | |
10283 | * new events in order to fully complete the previous instruction. | |
664f8e26 | 10284 | */ |
6c593b52 SC |
10285 | if (vcpu->arch.exception.injected) |
10286 | kvm_inject_exception(vcpu); | |
7709aba8 | 10287 | else if (kvm_is_exception_pending(vcpu)) |
6c593b52 SC |
10288 | ; /* see above */ |
10289 | else if (vcpu->arch.nmi_injected) | |
10290 | static_call(kvm_x86_inject_nmi)(vcpu); | |
10291 | else if (vcpu->arch.interrupt.injected) | |
10292 | static_call(kvm_x86_inject_irq)(vcpu, true); | |
664f8e26 | 10293 | |
6c593b52 SC |
10294 | /* |
10295 | * Exceptions that morph to VM-Exits are handled above, and pending | |
10296 | * exceptions on top of injected exceptions that do not VM-Exit should | |
10297 | * either morph to #DF or, sadly, override the injected exception. | |
10298 | */ | |
3b82b8d7 SC |
10299 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
10300 | vcpu->arch.exception.pending); | |
10301 | ||
1a680e35 | 10302 | /* |
6c593b52 SC |
10303 | * Bail if immediate entry+exit to/from the guest is needed to complete |
10304 | * nested VM-Enter or event re-injection so that a different pending | |
10305 | * event can be serviced (or if KVM needs to exit to userspace). | |
10306 | * | |
10307 | * Otherwise, continue processing events even if VM-Exit occurred. The | |
10308 | * VM-Exit will have cleared exceptions that were meant for L2, but | |
10309 | * there may now be events that can be injected into L1. | |
1a680e35 | 10310 | */ |
6c593b52 SC |
10311 | if (r < 0) |
10312 | goto out; | |
664f8e26 | 10313 | |
7709aba8 SC |
10314 | /* |
10315 | * A pending exception VM-Exit should either result in nested VM-Exit | |
10316 | * or force an immediate re-entry and exit to/from L2, and exception | |
10317 | * VM-Exits cannot be injected (flag should _never_ be set). | |
10318 | */ | |
10319 | WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected || | |
10320 | vcpu->arch.exception_vmexit.pending); | |
10321 | ||
28360f88 SC |
10322 | /* |
10323 | * New events, other than exceptions, cannot be injected if KVM needs | |
10324 | * to re-inject a previous event. See above comments on re-injecting | |
10325 | * for why pending exceptions get priority. | |
10326 | */ | |
10327 | can_inject = !kvm_event_needs_reinjection(vcpu); | |
664f8e26 | 10328 | |
b59bb7bd | 10329 | if (vcpu->arch.exception.pending) { |
5623f751 SC |
10330 | /* |
10331 | * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS | |
10332 | * value pushed on the stack. Trap-like exception and all #DBs | |
10333 | * leave RF as-is (KVM follows Intel's behavior in this regard; | |
10334 | * AMD states that code breakpoint #DBs excplitly clear RF=0). | |
10335 | * | |
10336 | * Note, most versions of Intel's SDM and AMD's APM incorrectly | |
10337 | * describe the behavior of General Detect #DBs, which are | |
10338 | * fault-like. They do _not_ set RF, a la code breakpoints. | |
10339 | */ | |
d4963e31 | 10340 | if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT) |
d6e8c854 NA |
10341 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | |
10342 | X86_EFLAGS_RF); | |
10343 | ||
d4963e31 SC |
10344 | if (vcpu->arch.exception.vector == DB_VECTOR) { |
10345 | kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception); | |
f10c729f JM |
10346 | if (vcpu->arch.dr7 & DR7_GD) { |
10347 | vcpu->arch.dr7 &= ~DR7_GD; | |
10348 | kvm_update_dr7(vcpu); | |
10349 | } | |
6bdf0662 NA |
10350 | } |
10351 | ||
b97f0745 | 10352 | kvm_inject_exception(vcpu); |
a61d7c54 SC |
10353 | |
10354 | vcpu->arch.exception.pending = false; | |
10355 | vcpu->arch.exception.injected = true; | |
10356 | ||
c6b22f59 | 10357 | can_inject = false; |
1a680e35 LA |
10358 | } |
10359 | ||
61e5f69e ML |
10360 | /* Don't inject interrupts if the user asked to avoid doing so */ |
10361 | if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) | |
10362 | return 0; | |
10363 | ||
c9d40913 PB |
10364 | /* |
10365 | * Finally, inject interrupt events. If an event cannot be injected | |
10366 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
10367 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
10368 | * and can architecturally be injected, but we cannot do it right now: | |
10369 | * an interrupt could have arrived just now and we have to inject it | |
10370 | * as a vmexit, or there could already an event in the queue, which is | |
10371 | * indicated by can_inject. In that case we request an immediate exit | |
10372 | * in order to make progress and get back here for another iteration. | |
10373 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
10374 | */ | |
31e83e21 | 10375 | #ifdef CONFIG_KVM_SMM |
c9d40913 | 10376 | if (vcpu->arch.smi_pending) { |
b3646477 | 10377 | r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 10378 | if (r < 0) |
a5f6909a | 10379 | goto out; |
c9d40913 PB |
10380 | if (r) { |
10381 | vcpu->arch.smi_pending = false; | |
10382 | ++vcpu->arch.smi_count; | |
10383 | enter_smm(vcpu); | |
10384 | can_inject = false; | |
10385 | } else | |
b3646477 | 10386 | static_call(kvm_x86_enable_smi_window)(vcpu); |
c9d40913 | 10387 | } |
31e83e21 | 10388 | #endif |
c9d40913 PB |
10389 | |
10390 | if (vcpu->arch.nmi_pending) { | |
b3646477 | 10391 | r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 10392 | if (r < 0) |
a5f6909a | 10393 | goto out; |
c9d40913 PB |
10394 | if (r) { |
10395 | --vcpu->arch.nmi_pending; | |
10396 | vcpu->arch.nmi_injected = true; | |
e27bc044 | 10397 | static_call(kvm_x86_inject_nmi)(vcpu); |
c9d40913 | 10398 | can_inject = false; |
b3646477 | 10399 | WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); |
c9d40913 PB |
10400 | } |
10401 | if (vcpu->arch.nmi_pending) | |
b3646477 | 10402 | static_call(kvm_x86_enable_nmi_window)(vcpu); |
c9d40913 | 10403 | } |
1a680e35 | 10404 | |
c9d40913 | 10405 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
b3646477 | 10406 | r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 10407 | if (r < 0) |
a5f6909a | 10408 | goto out; |
c9d40913 | 10409 | if (r) { |
bf672720 ML |
10410 | int irq = kvm_cpu_get_interrupt(vcpu); |
10411 | ||
10412 | if (!WARN_ON_ONCE(irq == -1)) { | |
10413 | kvm_queue_interrupt(vcpu, irq, false); | |
10414 | static_call(kvm_x86_inject_irq)(vcpu, false); | |
10415 | WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); | |
10416 | } | |
c9d40913 PB |
10417 | } |
10418 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
b3646477 | 10419 | static_call(kvm_x86_enable_irq_window)(vcpu); |
95ba8273 | 10420 | } |
ee2cd4b7 | 10421 | |
c9d40913 | 10422 | if (is_guest_mode(vcpu) && |
5b4ac1a1 PB |
10423 | kvm_x86_ops.nested_ops->has_events && |
10424 | kvm_x86_ops.nested_ops->has_events(vcpu)) | |
c9d40913 PB |
10425 | *req_immediate_exit = true; |
10426 | ||
dea0d5a2 SC |
10427 | /* |
10428 | * KVM must never queue a new exception while injecting an event; KVM | |
10429 | * is done emulating and should only propagate the to-be-injected event | |
10430 | * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an | |
10431 | * infinite loop as KVM will bail from VM-Enter to inject the pending | |
10432 | * exception and start the cycle all over. | |
10433 | * | |
10434 | * Exempt triple faults as they have special handling and won't put the | |
10435 | * vCPU into an infinite loop. Triple fault can be queued when running | |
10436 | * VMX without unrestricted guest, as that requires KVM to emulate Real | |
10437 | * Mode events (see kvm_inject_realmode_interrupt()). | |
10438 | */ | |
10439 | WARN_ON_ONCE(vcpu->arch.exception.pending || | |
10440 | vcpu->arch.exception_vmexit.pending); | |
a5f6909a | 10441 | return 0; |
c9d40913 | 10442 | |
a5f6909a JM |
10443 | out: |
10444 | if (r == -EBUSY) { | |
10445 | *req_immediate_exit = true; | |
10446 | r = 0; | |
10447 | } | |
10448 | return r; | |
95ba8273 GN |
10449 | } |
10450 | ||
7460fb4a AK |
10451 | static void process_nmi(struct kvm_vcpu *vcpu) |
10452 | { | |
400fee8c | 10453 | unsigned int limit; |
7460fb4a AK |
10454 | |
10455 | /* | |
400fee8c SC |
10456 | * x86 is limited to one NMI pending, but because KVM can't react to |
10457 | * incoming NMIs as quickly as bare metal, e.g. if the vCPU is | |
10458 | * scheduled out, KVM needs to play nice with two queued NMIs showing | |
10459 | * up at the same time. To handle this scenario, allow two NMIs to be | |
10460 | * (temporarily) pending so long as NMIs are not blocked and KVM is not | |
10461 | * waiting for a previous NMI injection to complete (which effectively | |
10462 | * blocks NMIs). KVM will immediately inject one of the two NMIs, and | |
10463 | * will request an NMI window to handle the second NMI. | |
7460fb4a | 10464 | */ |
b3646477 | 10465 | if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a | 10466 | limit = 1; |
400fee8c SC |
10467 | else |
10468 | limit = 2; | |
7460fb4a | 10469 | |
fa4c027a SS |
10470 | /* |
10471 | * Adjust the limit to account for pending virtual NMIs, which aren't | |
10472 | * tracked in vcpu->arch.nmi_pending. | |
10473 | */ | |
10474 | if (static_call(kvm_x86_is_vnmi_pending)(vcpu)) | |
10475 | limit--; | |
7460fb4a AK |
10476 | |
10477 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
10478 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
2cb93173 | 10479 | |
fa4c027a SS |
10480 | if (vcpu->arch.nmi_pending && |
10481 | (static_call(kvm_x86_set_vnmi_pending)(vcpu))) | |
10482 | vcpu->arch.nmi_pending--; | |
10483 | ||
2cb93173 SC |
10484 | if (vcpu->arch.nmi_pending) |
10485 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7460fb4a AK |
10486 | } |
10487 | ||
fa4c027a SS |
10488 | /* Return total number of NMIs pending injection to the VM */ |
10489 | int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu) | |
10490 | { | |
10491 | return vcpu->arch.nmi_pending + | |
10492 | static_call(kvm_x86_is_vnmi_pending)(vcpu); | |
7460fb4a AK |
10493 | } |
10494 | ||
7ee30bc1 NNL |
10495 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
10496 | unsigned long *vcpu_bitmap) | |
10497 | { | |
620b2438 | 10498 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); |
7ee30bc1 NNL |
10499 | } |
10500 | ||
2860c4b1 PB |
10501 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
10502 | { | |
10503 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
10504 | } | |
10505 | ||
2008fab3 | 10506 | void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
8df14af4 | 10507 | { |
ce0a58f4 | 10508 | struct kvm_lapic *apic = vcpu->arch.apic; |
06ef8134 ML |
10509 | bool activate; |
10510 | ||
8df14af4 SS |
10511 | if (!lapic_in_kernel(vcpu)) |
10512 | return; | |
10513 | ||
187c8833 | 10514 | down_read(&vcpu->kvm->arch.apicv_update_lock); |
66c768d3 | 10515 | preempt_disable(); |
b0a1637f | 10516 | |
8fc9c7a3 SS |
10517 | /* Do not activate APICV when APIC is disabled */ |
10518 | activate = kvm_vcpu_apicv_activated(vcpu) && | |
10519 | (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED); | |
d5fa597e | 10520 | |
ce0a58f4 | 10521 | if (apic->apicv_active == activate) |
06ef8134 ML |
10522 | goto out; |
10523 | ||
ce0a58f4 | 10524 | apic->apicv_active = activate; |
8df14af4 | 10525 | kvm_apic_update_apicv(vcpu); |
b3646477 | 10526 | static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); |
bca66dbc VK |
10527 | |
10528 | /* | |
10529 | * When APICv gets disabled, we may still have injected interrupts | |
10530 | * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was | |
10531 | * still active when the interrupt got accepted. Make sure | |
e746c1f1 | 10532 | * kvm_check_and_inject_events() is called to check for that. |
bca66dbc | 10533 | */ |
ce0a58f4 | 10534 | if (!apic->apicv_active) |
bca66dbc | 10535 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
b0a1637f | 10536 | |
06ef8134 | 10537 | out: |
66c768d3 | 10538 | preempt_enable(); |
187c8833 | 10539 | up_read(&vcpu->kvm->arch.apicv_update_lock); |
8df14af4 | 10540 | } |
2008fab3 SC |
10541 | EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv); |
10542 | ||
10543 | static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) | |
10544 | { | |
10545 | if (!lapic_in_kernel(vcpu)) | |
10546 | return; | |
10547 | ||
10548 | /* | |
10549 | * Due to sharing page tables across vCPUs, the xAPIC memslot must be | |
10550 | * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but | |
10551 | * and hardware doesn't support x2APIC virtualization. E.g. some AMD | |
10552 | * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in | |
10553 | * this case so that KVM can the AVIC doorbell to inject interrupts to | |
10554 | * running vCPUs, but KVM must not create SPTEs for the APIC base as | |
10555 | * the vCPU would incorrectly be able to access the vAPIC page via MMIO | |
10556 | * despite being in x2APIC mode. For simplicity, inhibiting the APIC | |
10557 | * access page is sticky. | |
10558 | */ | |
10559 | if (apic_x2apic_mode(vcpu->arch.apic) && | |
10560 | kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization) | |
10561 | kvm_inhibit_apic_access_page(vcpu); | |
10562 | ||
10563 | __kvm_vcpu_update_apicv(vcpu); | |
10564 | } | |
8df14af4 | 10565 | |
320af55a SC |
10566 | void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, |
10567 | enum kvm_apicv_inhibit reason, bool set) | |
8df14af4 | 10568 | { |
b0a1637f | 10569 | unsigned long old, new; |
8e205a6b | 10570 | |
187c8833 SC |
10571 | lockdep_assert_held_write(&kvm->arch.apicv_update_lock); |
10572 | ||
b3f257a8 | 10573 | if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason))) |
ef8efd7a SS |
10574 | return; |
10575 | ||
b0a1637f ML |
10576 | old = new = kvm->arch.apicv_inhibit_reasons; |
10577 | ||
4f4c4a3e | 10578 | set_or_clear_apicv_inhibit(&new, reason, set); |
8e205a6b | 10579 | |
36222b11 | 10580 | if (!!old != !!new) { |
ee49a893 SC |
10581 | /* |
10582 | * Kick all vCPUs before setting apicv_inhibit_reasons to avoid | |
10583 | * false positives in the sanity check WARN in svm_vcpu_run(). | |
10584 | * This task will wait for all vCPUs to ack the kick IRQ before | |
10585 | * updating apicv_inhibit_reasons, and all other vCPUs will | |
10586 | * block on acquiring apicv_update_lock so that vCPUs can't | |
10587 | * redo svm_vcpu_run() without seeing the new inhibit state. | |
10588 | * | |
10589 | * Note, holding apicv_update_lock and taking it in the read | |
10590 | * side (handling the request) also prevents other vCPUs from | |
10591 | * servicing the request with a stale apicv_inhibit_reasons. | |
10592 | */ | |
36222b11 | 10593 | kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); |
b0a1637f | 10594 | kvm->arch.apicv_inhibit_reasons = new; |
36222b11 ML |
10595 | if (new) { |
10596 | unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); | |
074c0080 BG |
10597 | int idx = srcu_read_lock(&kvm->srcu); |
10598 | ||
36222b11 | 10599 | kvm_zap_gfn_range(kvm, gfn, gfn+1); |
074c0080 | 10600 | srcu_read_unlock(&kvm->srcu, idx); |
36222b11 | 10601 | } |
7491b7b2 | 10602 | } else { |
b0a1637f | 10603 | kvm->arch.apicv_inhibit_reasons = new; |
7491b7b2 | 10604 | } |
b0a1637f | 10605 | } |
7d611233 | 10606 | |
320af55a SC |
10607 | void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, |
10608 | enum kvm_apicv_inhibit reason, bool set) | |
b0a1637f | 10609 | { |
f1575642 SC |
10610 | if (!enable_apicv) |
10611 | return; | |
10612 | ||
187c8833 | 10613 | down_write(&kvm->arch.apicv_update_lock); |
320af55a | 10614 | __kvm_set_or_clear_apicv_inhibit(kvm, reason, set); |
187c8833 | 10615 | up_write(&kvm->arch.apicv_update_lock); |
8df14af4 | 10616 | } |
320af55a | 10617 | EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit); |
8df14af4 | 10618 | |
3d81bc7e | 10619 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 10620 | { |
dcbd3e49 | 10621 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 10622 | return; |
c7c9c56c | 10623 | |
6308630b | 10624 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 10625 | |
b053b2ae | 10626 | if (irqchip_split(vcpu->kvm)) |
6308630b | 10627 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 10628 | else { |
37c4dbf3 | 10629 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); |
e97f852f WL |
10630 | if (ioapic_in_kernel(vcpu->kvm)) |
10631 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 10632 | } |
e40ff1d6 LA |
10633 | |
10634 | if (is_guest_mode(vcpu)) | |
10635 | vcpu->arch.load_eoi_exitmap_pending = true; | |
10636 | else | |
10637 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
10638 | } | |
10639 | ||
10640 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
10641 | { | |
e40ff1d6 LA |
10642 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
10643 | return; | |
10644 | ||
b4f69df0 | 10645 | #ifdef CONFIG_KVM_HYPERV |
c5adbb3a | 10646 | if (to_hv_vcpu(vcpu)) { |
b4f69df0 VK |
10647 | u64 eoi_exit_bitmap[4]; |
10648 | ||
f2bc14b6 VK |
10649 | bitmap_or((ulong *)eoi_exit_bitmap, |
10650 | vcpu->arch.ioapic_handled_vectors, | |
10651 | to_hv_synic(vcpu)->vec_bitmap, 256); | |
abb6d479 | 10652 | static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); |
c5adbb3a | 10653 | return; |
10654 | } | |
b4f69df0 | 10655 | #endif |
abb6d479 | 10656 | static_call_cond(kvm_x86_load_eoi_exitmap)( |
c5adbb3a | 10657 | vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); |
c7c9c56c YZ |
10658 | } |
10659 | ||
683412cc MZ |
10660 | void kvm_arch_guest_memory_reclaimed(struct kvm *kvm) |
10661 | { | |
10662 | static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm); | |
10663 | } | |
10664 | ||
d081a343 | 10665 | static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
4256f43f | 10666 | { |
35754c98 | 10667 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
10668 | return; |
10669 | ||
2a890614 | 10670 | static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu); |
4256f43f | 10671 | } |
4256f43f | 10672 | |
d264ee0c SC |
10673 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
10674 | { | |
10675 | smp_send_reschedule(vcpu->cpu); | |
10676 | } | |
10677 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
10678 | ||
9357d939 | 10679 | /* |
8d25b7be | 10680 | * Called within kvm->srcu read side. |
362c698f | 10681 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
10682 | * exiting to the userspace. Otherwise, the value will be returned to the |
10683 | * userspace. | |
10684 | */ | |
851ba692 | 10685 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
10686 | { |
10687 | int r; | |
62a193ed MG |
10688 | bool req_int_win = |
10689 | dm_request_for_irq_injection(vcpu) && | |
10690 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 10691 | fastpath_t exit_fastpath; |
62a193ed | 10692 | |
730dca42 | 10693 | bool req_immediate_exit = false; |
b6c7a5dc | 10694 | |
2fa6e1e1 | 10695 | if (kvm_request_pending(vcpu)) { |
f4d31653 | 10696 | if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { |
67369273 SC |
10697 | r = -EIO; |
10698 | goto out; | |
10699 | } | |
cf87ac73 GS |
10700 | |
10701 | if (kvm_dirty_ring_check_request(vcpu)) { | |
10702 | r = 0; | |
10703 | goto out; | |
10704 | } | |
10705 | ||
729c15c2 | 10706 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 10707 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
10708 | r = 0; |
10709 | goto out; | |
10710 | } | |
10711 | } | |
527d5cd7 SC |
10712 | if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu)) |
10713 | kvm_mmu_free_obsolete_roots(vcpu); | |
a8eeb04a | 10714 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 10715 | __kvm_migrate_timers(vcpu); |
d828199e | 10716 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6b6fcd28 | 10717 | kvm_update_masterclock(vcpu->kvm); |
0061d53d MT |
10718 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
10719 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
10720 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
10721 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
10722 | if (unlikely(r)) |
10723 | goto out; | |
10724 | } | |
a8eeb04a | 10725 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 10726 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
10727 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
10728 | kvm_mmu_load_pgd(vcpu); | |
e94cea09 SC |
10729 | |
10730 | /* | |
10731 | * Note, the order matters here, as flushing "all" TLB entries | |
10732 | * also flushes the "current" TLB entries, i.e. servicing the | |
10733 | * flush "all" will clear any request to flush "current". | |
10734 | */ | |
10735 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) | |
7780938c | 10736 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 | 10737 | |
40e5f908 | 10738 | kvm_service_local_tlb_flush_requests(vcpu); |
eeeb4f67 | 10739 | |
0823570f VK |
10740 | /* |
10741 | * Fall back to a "full" guest flush if Hyper-V's precise | |
10742 | * flushing fails. Note, Hyper-V's flushing is per-vCPU, but | |
10743 | * the flushes are considered "remote" and not "local" because | |
10744 | * the requests can be initiated from other vCPUs. | |
10745 | */ | |
b4f69df0 | 10746 | #ifdef CONFIG_KVM_HYPERV |
0823570f VK |
10747 | if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) && |
10748 | kvm_hv_vcpu_flush_tlb(vcpu)) | |
adc43caa | 10749 | kvm_vcpu_flush_tlb_guest(vcpu); |
b4f69df0 | 10750 | #endif |
adc43caa | 10751 | |
a8eeb04a | 10752 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 10753 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
10754 | r = 0; |
10755 | goto out; | |
10756 | } | |
92e7d5c8 ML |
10757 | if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
10758 | if (is_guest_mode(vcpu)) | |
cb6a32c2 | 10759 | kvm_x86_ops.nested_ops->triple_fault(vcpu); |
92e7d5c8 ML |
10760 | |
10761 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { | |
cb6a32c2 SC |
10762 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
10763 | vcpu->mmio_needed = 0; | |
10764 | r = 0; | |
e542baf3 | 10765 | goto out; |
cb6a32c2 | 10766 | } |
71c4dfaf | 10767 | } |
af585b92 GN |
10768 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
10769 | /* Page is swapped out. Do synthetic halt */ | |
10770 | vcpu->arch.apf.halted = true; | |
10771 | r = 1; | |
10772 | goto out; | |
10773 | } | |
c9aaa895 GC |
10774 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
10775 | record_steal_time(vcpu); | |
fad505b2 MZ |
10776 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
10777 | kvm_pmu_handle_event(vcpu); | |
10778 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
10779 | kvm_pmu_deliver_pmi(vcpu); | |
cf7316d0 | 10780 | #ifdef CONFIG_KVM_SMM |
64d60670 PB |
10781 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
10782 | process_smi(vcpu); | |
cf7316d0 | 10783 | #endif |
7460fb4a AK |
10784 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
10785 | process_nmi(vcpu); | |
7543a635 SR |
10786 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
10787 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
10788 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 10789 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
10790 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
10791 | vcpu->run->eoi.vector = | |
10792 | vcpu->arch.pending_ioapic_eoi; | |
10793 | r = 0; | |
10794 | goto out; | |
10795 | } | |
10796 | } | |
3d81bc7e YZ |
10797 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
10798 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
10799 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
10800 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
10801 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
10802 | kvm_vcpu_reload_apic_access_page(vcpu); | |
b4f69df0 | 10803 | #ifdef CONFIG_KVM_HYPERV |
2ce79189 AS |
10804 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
10805 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
10806 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
d495f942 | 10807 | vcpu->run->system_event.ndata = 0; |
2ce79189 AS |
10808 | r = 0; |
10809 | goto out; | |
10810 | } | |
e516cebb AS |
10811 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
10812 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
10813 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
d495f942 | 10814 | vcpu->run->system_event.ndata = 0; |
e516cebb AS |
10815 | r = 0; |
10816 | goto out; | |
10817 | } | |
db397571 | 10818 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
9ff5e030 VK |
10819 | struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); |
10820 | ||
db397571 | 10821 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; |
9ff5e030 | 10822 | vcpu->run->hyperv = hv_vcpu->exit; |
db397571 AS |
10823 | r = 0; |
10824 | goto out; | |
10825 | } | |
f3b138c5 AS |
10826 | |
10827 | /* | |
10828 | * KVM_REQ_HV_STIMER has to be processed after | |
10829 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
10830 | * depend on the guest clock being up-to-date | |
10831 | */ | |
1f4b34f8 AS |
10832 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
10833 | kvm_hv_process_stimers(vcpu); | |
b4f69df0 | 10834 | #endif |
8df14af4 SS |
10835 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
10836 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
10837 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
10838 | kvm_check_async_pf_completion(vcpu); | |
1a155254 | 10839 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
b3646477 | 10840 | static_call(kvm_x86_msr_filter_changed)(vcpu); |
a85863c2 MS |
10841 | |
10842 | if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) | |
10843 | static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); | |
2f52d58c | 10844 | } |
b93463aa | 10845 | |
40da8ccd DW |
10846 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || |
10847 | kvm_xen_has_interrupt(vcpu)) { | |
0f1e261e | 10848 | ++vcpu->stat.req_event; |
4fe09bcf JM |
10849 | r = kvm_apic_accept_events(vcpu); |
10850 | if (r < 0) { | |
10851 | r = 0; | |
10852 | goto out; | |
10853 | } | |
66450a21 JK |
10854 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
10855 | r = 1; | |
10856 | goto out; | |
10857 | } | |
10858 | ||
e746c1f1 | 10859 | r = kvm_check_and_inject_events(vcpu, &req_immediate_exit); |
a5f6909a JM |
10860 | if (r < 0) { |
10861 | r = 0; | |
10862 | goto out; | |
10863 | } | |
c9d40913 | 10864 | if (req_int_win) |
b3646477 | 10865 | static_call(kvm_x86_enable_irq_window)(vcpu); |
b463a6f7 AK |
10866 | |
10867 | if (kvm_lapic_enabled(vcpu)) { | |
10868 | update_cr8_intercept(vcpu); | |
10869 | kvm_lapic_sync_to_vapic(vcpu); | |
10870 | } | |
10871 | } | |
10872 | ||
d8368af8 AK |
10873 | r = kvm_mmu_reload(vcpu); |
10874 | if (unlikely(r)) { | |
d905c069 | 10875 | goto cancel_injection; |
d8368af8 AK |
10876 | } |
10877 | ||
b6c7a5dc HB |
10878 | preempt_disable(); |
10879 | ||
e27bc044 | 10880 | static_call(kvm_x86_prepare_switch_to_guest)(vcpu); |
b95234c8 PB |
10881 | |
10882 | /* | |
10883 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
10884 | * IPI are then delayed after guest entry, which ensures that they | |
10885 | * result in virtual interrupt delivery. | |
10886 | */ | |
10887 | local_irq_disable(); | |
66fa226c ML |
10888 | |
10889 | /* Store vcpu->apicv_active before vcpu->mode. */ | |
10890 | smp_store_release(&vcpu->mode, IN_GUEST_MODE); | |
6b7e2d09 | 10891 | |
2031f287 | 10892 | kvm_vcpu_srcu_read_unlock(vcpu); |
01b71917 | 10893 | |
0f127d12 | 10894 | /* |
b95234c8 | 10895 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 10896 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 10897 | * |
81b01667 | 10898 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
10899 | * pairs with the memory barrier implicit in pi_test_and_set_on |
10900 | * (see vmx_deliver_posted_interrupt). | |
10901 | * | |
10902 | * 3) This also orders the write to mode from any reads to the page | |
10903 | * tables done while the VCPU is running. Please see the comment | |
10904 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 10905 | */ |
01b71917 | 10906 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 10907 | |
b95234c8 | 10908 | /* |
0f65a9d3 SC |
10909 | * Process pending posted interrupts to handle the case where the |
10910 | * notification IRQ arrived in the host, or was never sent (because the | |
10911 | * target vCPU wasn't running). Do this regardless of the vCPU's APICv | |
10912 | * status, KVM doesn't update assigned devices when APICv is inhibited, | |
10913 | * i.e. they can post interrupts even if APICv is temporarily disabled. | |
b95234c8 | 10914 | */ |
37c4dbf3 PB |
10915 | if (kvm_lapic_enabled(vcpu)) |
10916 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); | |
32f88400 | 10917 | |
5a9f5443 | 10918 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 10919 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 10920 | smp_wmb(); |
6c142801 AK |
10921 | local_irq_enable(); |
10922 | preempt_enable(); | |
2031f287 | 10923 | kvm_vcpu_srcu_read_lock(vcpu); |
6c142801 | 10924 | r = 1; |
d905c069 | 10925 | goto cancel_injection; |
6c142801 AK |
10926 | } |
10927 | ||
c43203ca PB |
10928 | if (req_immediate_exit) { |
10929 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 10930 | static_call(kvm_x86_request_immediate_exit)(vcpu); |
c43203ca | 10931 | } |
d6185f20 | 10932 | |
2620fe26 SC |
10933 | fpregs_assert_state_consistent(); |
10934 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
10935 | switch_fpu_return(); | |
5f409e20 | 10936 | |
ec5be88a JL |
10937 | if (vcpu->arch.guest_fpu.xfd_err) |
10938 | wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); | |
10939 | ||
42dbaa5a | 10940 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
10941 | set_debugreg(0, 7); |
10942 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
10943 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
10944 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
10945 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
f85d4016 LJ |
10946 | } else if (unlikely(hw_breakpoint_active())) { |
10947 | set_debugreg(0, 7); | |
42dbaa5a | 10948 | } |
b6c7a5dc | 10949 | |
b2d2af7e MR |
10950 | guest_timing_enter_irqoff(); |
10951 | ||
d89d04ab | 10952 | for (;;) { |
ee49a893 SC |
10953 | /* |
10954 | * Assert that vCPU vs. VM APICv state is consistent. An APICv | |
10955 | * update must kick and wait for all vCPUs before toggling the | |
54aa699e | 10956 | * per-VM state, and responding vCPUs must wait for the update |
ee49a893 SC |
10957 | * to complete before servicing KVM_REQ_APICV_UPDATE. |
10958 | */ | |
f8d8ac21 SS |
10959 | WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) && |
10960 | (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED)); | |
ee49a893 | 10961 | |
e27bc044 | 10962 | exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu); |
d89d04ab PB |
10963 | if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) |
10964 | break; | |
10965 | ||
37c4dbf3 PB |
10966 | if (kvm_lapic_enabled(vcpu)) |
10967 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); | |
de7cd3f6 PB |
10968 | |
10969 | if (unlikely(kvm_vcpu_exit_request(vcpu))) { | |
d89d04ab PB |
10970 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; |
10971 | break; | |
10972 | } | |
8b703a49 SC |
10973 | |
10974 | /* Note, VM-Exits that go down the "slow" path are accounted below. */ | |
10975 | ++vcpu->stat.exits; | |
de7cd3f6 | 10976 | } |
b6c7a5dc | 10977 | |
c77fb5fe PB |
10978 | /* |
10979 | * Do this here before restoring debug registers on the host. And | |
10980 | * since we do this before handling the vmexit, a DR access vmexit | |
10981 | * can (a) read the correct value of the debug registers, (b) set | |
10982 | * KVM_DEBUGREG_WONT_EXIT again. | |
10983 | */ | |
10984 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 10985 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
b3646477 | 10986 | static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); |
70e4da7a | 10987 | kvm_update_dr0123(vcpu); |
70e4da7a | 10988 | kvm_update_dr7(vcpu); |
c77fb5fe PB |
10989 | } |
10990 | ||
24f1e32c FW |
10991 | /* |
10992 | * If the guest has used debug registers, at least dr7 | |
10993 | * will be disabled while returning to the host. | |
10994 | * If we don't have active breakpoints in the host, we don't | |
10995 | * care about the messed up debug address registers. But if | |
10996 | * we have some of them active, restore the old state. | |
10997 | */ | |
59d8eb53 | 10998 | if (hw_breakpoint_active()) |
24f1e32c | 10999 | hw_breakpoint_restore(); |
42dbaa5a | 11000 | |
c967118d | 11001 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 11002 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 11003 | |
6b7e2d09 | 11004 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 11005 | smp_wmb(); |
a547c6db | 11006 | |
b5274b1b KT |
11007 | /* |
11008 | * Sync xfd before calling handle_exit_irqoff() which may | |
11009 | * rely on the fact that guest_fpu::xfd is up-to-date (e.g. | |
11010 | * in #NM irqoff handler). | |
11011 | */ | |
11012 | if (vcpu->arch.xfd_no_write_intercept) | |
11013 | fpu_sync_guest_vmexit_xfd_state(); | |
11014 | ||
b3646477 | 11015 | static_call(kvm_x86_handle_exit_irqoff)(vcpu); |
b6c7a5dc | 11016 | |
ec5be88a JL |
11017 | if (vcpu->arch.guest_fpu.xfd_err) |
11018 | wrmsrl(MSR_IA32_XFD_ERR, 0); | |
11019 | ||
d7a08882 SC |
11020 | /* |
11021 | * Consume any pending interrupts, including the possible source of | |
11022 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
11023 | * An instruction is required after local_irq_enable() to fully unblock | |
11024 | * interrupts on processors that implement an interrupt shadow, the | |
11025 | * stat.exits increment will do nicely. | |
11026 | */ | |
db215756 | 11027 | kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); |
d7a08882 | 11028 | local_irq_enable(); |
b6c7a5dc | 11029 | ++vcpu->stat.exits; |
d7a08882 SC |
11030 | local_irq_disable(); |
11031 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 11032 | |
16045714 WL |
11033 | /* |
11034 | * Wait until after servicing IRQs to account guest time so that any | |
11035 | * ticks that occurred while running the guest are properly accounted | |
11036 | * to the guest. Waiting until IRQs are enabled degrades the accuracy | |
11037 | * of accounting via context tracking, but the loss of accuracy is | |
11038 | * acceptable for all known use cases. | |
11039 | */ | |
b2d2af7e | 11040 | guest_timing_exit_irqoff(); |
16045714 | 11041 | |
f2485b3e | 11042 | local_irq_enable(); |
b6c7a5dc HB |
11043 | preempt_enable(); |
11044 | ||
2031f287 | 11045 | kvm_vcpu_srcu_read_lock(vcpu); |
3200f405 | 11046 | |
b6c7a5dc HB |
11047 | /* |
11048 | * Profile KVM exit RIPs: | |
11049 | */ | |
11050 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
11051 | unsigned long rip = kvm_rip_read(vcpu); |
11052 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
11053 | } |
11054 | ||
cc578287 ZA |
11055 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
11056 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 11057 | |
5cfb1d5a MT |
11058 | if (vcpu->arch.apic_attention) |
11059 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 11060 | |
b3646477 | 11061 | r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); |
d905c069 MT |
11062 | return r; |
11063 | ||
11064 | cancel_injection: | |
8081ad06 SC |
11065 | if (req_immediate_exit) |
11066 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 11067 | static_call(kvm_x86_cancel_injection)(vcpu); |
ae7a2a3f MT |
11068 | if (unlikely(vcpu->arch.apic_attention)) |
11069 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
11070 | out: |
11071 | return r; | |
11072 | } | |
b6c7a5dc | 11073 | |
8d25b7be | 11074 | /* Called within kvm->srcu read side. */ |
2031f287 | 11075 | static inline int vcpu_block(struct kvm_vcpu *vcpu) |
362c698f | 11076 | { |
98c25ead SC |
11077 | bool hv_timer; |
11078 | ||
c3e8abf0 | 11079 | if (!kvm_arch_vcpu_runnable(vcpu)) { |
98c25ead SC |
11080 | /* |
11081 | * Switch to the software timer before halt-polling/blocking as | |
11082 | * the guest's timer may be a break event for the vCPU, and the | |
11083 | * hypervisor timer runs only when the CPU is in guest mode. | |
11084 | * Switch before halt-polling so that KVM recognizes an expired | |
11085 | * timer before blocking. | |
11086 | */ | |
11087 | hv_timer = kvm_lapic_hv_timer_in_use(vcpu); | |
11088 | if (hv_timer) | |
11089 | kvm_lapic_switch_to_sw_timer(vcpu); | |
11090 | ||
2031f287 | 11091 | kvm_vcpu_srcu_read_unlock(vcpu); |
cdafece4 SC |
11092 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
11093 | kvm_vcpu_halt(vcpu); | |
11094 | else | |
11095 | kvm_vcpu_block(vcpu); | |
2031f287 | 11096 | kvm_vcpu_srcu_read_lock(vcpu); |
bf9f6ac8 | 11097 | |
98c25ead SC |
11098 | if (hv_timer) |
11099 | kvm_lapic_switch_to_hv_timer(vcpu); | |
11100 | ||
599275c0 PB |
11101 | /* |
11102 | * If the vCPU is not runnable, a signal or another host event | |
11103 | * of some kind is pending; service it without changing the | |
11104 | * vCPU's activity state. | |
11105 | */ | |
11106 | if (!kvm_arch_vcpu_runnable(vcpu)) | |
9c8fd1ba PB |
11107 | return 1; |
11108 | } | |
362c698f | 11109 | |
26844fee PB |
11110 | /* |
11111 | * Evaluate nested events before exiting the halted state. This allows | |
11112 | * the halt state to be recorded properly in the VMCS12's activity | |
11113 | * state field (AMD does not have a similar field and a VM-Exit always | |
11114 | * causes a spurious wakeup from HLT). | |
11115 | */ | |
11116 | if (is_guest_mode(vcpu)) { | |
11117 | if (kvm_check_nested_events(vcpu) < 0) | |
11118 | return 0; | |
11119 | } | |
11120 | ||
4fe09bcf JM |
11121 | if (kvm_apic_accept_events(vcpu) < 0) |
11122 | return 0; | |
362c698f PB |
11123 | switch(vcpu->arch.mp_state) { |
11124 | case KVM_MP_STATE_HALTED: | |
647daca2 | 11125 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
11126 | vcpu->arch.pv.pv_unhalted = false; |
11127 | vcpu->arch.mp_state = | |
11128 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 11129 | fallthrough; |
362c698f PB |
11130 | case KVM_MP_STATE_RUNNABLE: |
11131 | vcpu->arch.apf.halted = false; | |
11132 | break; | |
11133 | case KVM_MP_STATE_INIT_RECEIVED: | |
11134 | break; | |
11135 | default: | |
22c6a0ef PB |
11136 | WARN_ON_ONCE(1); |
11137 | break; | |
362c698f PB |
11138 | } |
11139 | return 1; | |
11140 | } | |
09cec754 | 11141 | |
5d9bc648 PB |
11142 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
11143 | { | |
11144 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && | |
11145 | !vcpu->arch.apf.halted); | |
11146 | } | |
11147 | ||
8d25b7be | 11148 | /* Called within kvm->srcu read side. */ |
362c698f | 11149 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
11150 | { |
11151 | int r; | |
11152 | ||
ee605e31 | 11153 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
c595ceee | 11154 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 11155 | |
362c698f | 11156 | for (;;) { |
6cd88243 PB |
11157 | /* |
11158 | * If another guest vCPU requests a PV TLB flush in the middle | |
11159 | * of instruction emulation, the rest of the emulation could | |
11160 | * use a stale page translation. Assume that any code after | |
11161 | * this point can start executing an instruction. | |
11162 | */ | |
11163 | vcpu->arch.at_instruction_boundary = false; | |
58f800d5 | 11164 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 11165 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 11166 | } else { |
2031f287 | 11167 | r = vcpu_block(vcpu); |
bf9f6ac8 FW |
11168 | } |
11169 | ||
09cec754 GN |
11170 | if (r <= 0) |
11171 | break; | |
11172 | ||
084071d5 | 11173 | kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); |
7caf9571 DW |
11174 | if (kvm_xen_has_pending_events(vcpu)) |
11175 | kvm_xen_inject_pending_events(vcpu); | |
11176 | ||
09cec754 GN |
11177 | if (kvm_cpu_has_pending_timer(vcpu)) |
11178 | kvm_inject_pending_timer_irqs(vcpu); | |
11179 | ||
782d422b MG |
11180 | if (dm_request_for_irq_injection(vcpu) && |
11181 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
11182 | r = 0; |
11183 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 11184 | ++vcpu->stat.request_irq_exits; |
362c698f | 11185 | break; |
09cec754 | 11186 | } |
af585b92 | 11187 | |
f3020b88 | 11188 | if (__xfer_to_guest_mode_work_pending()) { |
2031f287 | 11189 | kvm_vcpu_srcu_read_unlock(vcpu); |
72c3c0fe | 11190 | r = xfer_to_guest_mode_handle_work(vcpu); |
2031f287 | 11191 | kvm_vcpu_srcu_read_lock(vcpu); |
72c3c0fe TG |
11192 | if (r) |
11193 | return r; | |
d7690175 | 11194 | } |
b6c7a5dc HB |
11195 | } |
11196 | ||
b6c7a5dc HB |
11197 | return r; |
11198 | } | |
11199 | ||
716d51ab GN |
11200 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
11201 | { | |
2d089356 | 11202 | return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab GN |
11203 | } |
11204 | ||
11205 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
11206 | { | |
11207 | BUG_ON(!vcpu->arch.pio.count); | |
11208 | ||
11209 | return complete_emulated_io(vcpu); | |
11210 | } | |
11211 | ||
f78146b0 AK |
11212 | /* |
11213 | * Implements the following, as a state machine: | |
11214 | * | |
11215 | * read: | |
11216 | * for each fragment | |
87da7e66 XG |
11217 | * for each mmio piece in the fragment |
11218 | * write gpa, len | |
11219 | * exit | |
11220 | * copy data | |
f78146b0 AK |
11221 | * execute insn |
11222 | * | |
11223 | * write: | |
11224 | * for each fragment | |
87da7e66 XG |
11225 | * for each mmio piece in the fragment |
11226 | * write gpa, len | |
11227 | * copy data | |
11228 | * exit | |
f78146b0 | 11229 | */ |
716d51ab | 11230 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
11231 | { |
11232 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 11233 | struct kvm_mmio_fragment *frag; |
87da7e66 | 11234 | unsigned len; |
5287f194 | 11235 | |
716d51ab | 11236 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 11237 | |
716d51ab | 11238 | /* Complete previous fragment */ |
87da7e66 XG |
11239 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
11240 | len = min(8u, frag->len); | |
716d51ab | 11241 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
11242 | memcpy(frag->data, run->mmio.data, len); |
11243 | ||
11244 | if (frag->len <= 8) { | |
11245 | /* Switch to the next fragment. */ | |
11246 | frag++; | |
11247 | vcpu->mmio_cur_fragment++; | |
11248 | } else { | |
11249 | /* Go forward to the next mmio piece. */ | |
11250 | frag->data += len; | |
11251 | frag->gpa += len; | |
11252 | frag->len -= len; | |
11253 | } | |
11254 | ||
a08d3b3b | 11255 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 11256 | vcpu->mmio_needed = 0; |
0912c977 PB |
11257 | |
11258 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 11259 | if (vcpu->mmio_is_write) |
716d51ab GN |
11260 | return 1; |
11261 | vcpu->mmio_read_completed = 1; | |
11262 | return complete_emulated_io(vcpu); | |
11263 | } | |
87da7e66 | 11264 | |
716d51ab GN |
11265 | run->exit_reason = KVM_EXIT_MMIO; |
11266 | run->mmio.phys_addr = frag->gpa; | |
11267 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
11268 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
11269 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
11270 | run->mmio.is_write = vcpu->mmio_is_write; |
11271 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
11272 | return 0; | |
5287f194 AK |
11273 | } |
11274 | ||
822f312d SAS |
11275 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
11276 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
11277 | { | |
e27bc044 | 11278 | /* Exclude PKRU, it's restored separately immediately after VM-Exit. */ |
d69c1382 | 11279 | fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); |
822f312d SAS |
11280 | trace_kvm_fpu(1); |
11281 | } | |
11282 | ||
11283 | /* When vcpu_run ends, restore user space FPU context. */ | |
11284 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
11285 | { | |
d69c1382 | 11286 | fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); |
822f312d SAS |
11287 | ++vcpu->stat.fpu_reload; |
11288 | trace_kvm_fpu(0); | |
11289 | } | |
11290 | ||
1b94f6f8 | 11291 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 11292 | { |
7709aba8 | 11293 | struct kvm_queued_exception *ex = &vcpu->arch.exception; |
1b94f6f8 | 11294 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 11295 | int r; |
b6c7a5dc | 11296 | |
accb757d | 11297 | vcpu_load(vcpu); |
20b7035c | 11298 | kvm_sigset_activate(vcpu); |
15aad3be | 11299 | kvm_run->flags = 0; |
5663d8f9 PX |
11300 | kvm_load_guest_fpu(vcpu); |
11301 | ||
2031f287 | 11302 | kvm_vcpu_srcu_read_lock(vcpu); |
a4535290 | 11303 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
11304 | if (kvm_run->immediate_exit) { |
11305 | r = -EINTR; | |
11306 | goto out; | |
11307 | } | |
7b0151ca | 11308 | |
98c25ead | 11309 | /* |
7b0151ca SC |
11310 | * Don't bother switching APIC timer emulation from the |
11311 | * hypervisor timer to the software timer, the only way for the | |
11312 | * APIC timer to be active is if userspace stuffed vCPU state, | |
11313 | * i.e. put the vCPU into a nonsensical state. Only an INIT | |
11314 | * will transition the vCPU out of UNINITIALIZED (without more | |
11315 | * state stuffing from userspace), which will reset the local | |
11316 | * APIC and thus cancel the timer or drop the IRQ (if the timer | |
11317 | * already expired). | |
98c25ead | 11318 | */ |
2031f287 | 11319 | kvm_vcpu_srcu_read_unlock(vcpu); |
c91d4497 | 11320 | kvm_vcpu_block(vcpu); |
2031f287 | 11321 | kvm_vcpu_srcu_read_lock(vcpu); |
8d25b7be | 11322 | |
4fe09bcf JM |
11323 | if (kvm_apic_accept_events(vcpu) < 0) { |
11324 | r = 0; | |
11325 | goto out; | |
11326 | } | |
ac9f6dc0 | 11327 | r = -EAGAIN; |
a0595000 JS |
11328 | if (signal_pending(current)) { |
11329 | r = -EINTR; | |
1b94f6f8 | 11330 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
11331 | ++vcpu->stat.signal_exits; |
11332 | } | |
ac9f6dc0 | 11333 | goto out; |
b6c7a5dc HB |
11334 | } |
11335 | ||
e489a4a6 SC |
11336 | if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || |
11337 | (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { | |
01643c51 KH |
11338 | r = -EINVAL; |
11339 | goto out; | |
11340 | } | |
11341 | ||
1b94f6f8 | 11342 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
11343 | r = sync_regs(vcpu); |
11344 | if (r != 0) | |
11345 | goto out; | |
11346 | } | |
11347 | ||
b6c7a5dc | 11348 | /* re-sync apic's tpr */ |
35754c98 | 11349 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
11350 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
11351 | r = -EINVAL; | |
11352 | goto out; | |
11353 | } | |
11354 | } | |
b6c7a5dc | 11355 | |
7709aba8 SC |
11356 | /* |
11357 | * If userspace set a pending exception and L2 is active, convert it to | |
11358 | * a pending VM-Exit if L1 wants to intercept the exception. | |
11359 | */ | |
11360 | if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) && | |
11361 | kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector, | |
11362 | ex->error_code)) { | |
11363 | kvm_queue_exception_vmexit(vcpu, ex->vector, | |
11364 | ex->has_error_code, ex->error_code, | |
11365 | ex->has_payload, ex->payload); | |
11366 | ex->injected = false; | |
11367 | ex->pending = false; | |
11368 | } | |
11369 | vcpu->arch.exception_from_userspace = false; | |
11370 | ||
716d51ab GN |
11371 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
11372 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
11373 | vcpu->arch.complete_userspace_io = NULL; | |
11374 | r = cui(vcpu); | |
11375 | if (r <= 0) | |
5663d8f9 | 11376 | goto out; |
0bc27326 SC |
11377 | } else { |
11378 | WARN_ON_ONCE(vcpu->arch.pio.count); | |
11379 | WARN_ON_ONCE(vcpu->mmio_needed); | |
11380 | } | |
5287f194 | 11381 | |
fc4fad79 | 11382 | if (kvm_run->immediate_exit) { |
460df4c1 | 11383 | r = -EINTR; |
fc4fad79 SC |
11384 | goto out; |
11385 | } | |
11386 | ||
11387 | r = static_call(kvm_x86_vcpu_pre_run)(vcpu); | |
11388 | if (r <= 0) | |
11389 | goto out; | |
11390 | ||
11391 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
11392 | |
11393 | out: | |
5663d8f9 | 11394 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 11395 | if (kvm_run->kvm_valid_regs) |
01643c51 | 11396 | store_regs(vcpu); |
f1d86e46 | 11397 | post_kvm_run_save(vcpu); |
2031f287 | 11398 | kvm_vcpu_srcu_read_unlock(vcpu); |
b6c7a5dc | 11399 | |
8d25b7be | 11400 | kvm_sigset_deactivate(vcpu); |
accb757d | 11401 | vcpu_put(vcpu); |
b6c7a5dc HB |
11402 | return r; |
11403 | } | |
11404 | ||
01643c51 | 11405 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 11406 | { |
7ae441ea GN |
11407 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
11408 | /* | |
11409 | * We are here if userspace calls get_regs() in the middle of | |
11410 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 11411 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
11412 | * that usually, but some bad designed PV devices (vmware |
11413 | * backdoor interface) need this to work | |
11414 | */ | |
c9b8b07c | 11415 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
11416 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
11417 | } | |
de3cd117 SC |
11418 | regs->rax = kvm_rax_read(vcpu); |
11419 | regs->rbx = kvm_rbx_read(vcpu); | |
11420 | regs->rcx = kvm_rcx_read(vcpu); | |
11421 | regs->rdx = kvm_rdx_read(vcpu); | |
11422 | regs->rsi = kvm_rsi_read(vcpu); | |
11423 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 11424 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 11425 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 11426 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
11427 | regs->r8 = kvm_r8_read(vcpu); |
11428 | regs->r9 = kvm_r9_read(vcpu); | |
11429 | regs->r10 = kvm_r10_read(vcpu); | |
11430 | regs->r11 = kvm_r11_read(vcpu); | |
11431 | regs->r12 = kvm_r12_read(vcpu); | |
11432 | regs->r13 = kvm_r13_read(vcpu); | |
11433 | regs->r14 = kvm_r14_read(vcpu); | |
11434 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
11435 | #endif |
11436 | ||
5fdbf976 | 11437 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 11438 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 11439 | } |
b6c7a5dc | 11440 | |
01643c51 KH |
11441 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
11442 | { | |
11443 | vcpu_load(vcpu); | |
11444 | __get_regs(vcpu, regs); | |
1fc9b76b | 11445 | vcpu_put(vcpu); |
b6c7a5dc HB |
11446 | return 0; |
11447 | } | |
11448 | ||
01643c51 | 11449 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 11450 | { |
7ae441ea GN |
11451 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
11452 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
11453 | ||
de3cd117 SC |
11454 | kvm_rax_write(vcpu, regs->rax); |
11455 | kvm_rbx_write(vcpu, regs->rbx); | |
11456 | kvm_rcx_write(vcpu, regs->rcx); | |
11457 | kvm_rdx_write(vcpu, regs->rdx); | |
11458 | kvm_rsi_write(vcpu, regs->rsi); | |
11459 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 11460 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 11461 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 11462 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
11463 | kvm_r8_write(vcpu, regs->r8); |
11464 | kvm_r9_write(vcpu, regs->r9); | |
11465 | kvm_r10_write(vcpu, regs->r10); | |
11466 | kvm_r11_write(vcpu, regs->r11); | |
11467 | kvm_r12_write(vcpu, regs->r12); | |
11468 | kvm_r13_write(vcpu, regs->r13); | |
11469 | kvm_r14_write(vcpu, regs->r14); | |
11470 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
11471 | #endif |
11472 | ||
5fdbf976 | 11473 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 11474 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 11475 | |
b4f14abd | 11476 | vcpu->arch.exception.pending = false; |
7709aba8 | 11477 | vcpu->arch.exception_vmexit.pending = false; |
b4f14abd | 11478 | |
3842d135 | 11479 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 11480 | } |
3842d135 | 11481 | |
01643c51 KH |
11482 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
11483 | { | |
11484 | vcpu_load(vcpu); | |
11485 | __set_regs(vcpu, regs); | |
875656fe | 11486 | vcpu_put(vcpu); |
b6c7a5dc HB |
11487 | return 0; |
11488 | } | |
11489 | ||
6dba9403 | 11490 | static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 11491 | { |
89a27f4d | 11492 | struct desc_ptr dt; |
b6c7a5dc | 11493 | |
5265713a TL |
11494 | if (vcpu->arch.guest_state_protected) |
11495 | goto skip_protected_regs; | |
11496 | ||
3e6e0aab GT |
11497 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
11498 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
11499 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
11500 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
11501 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
11502 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 11503 | |
3e6e0aab GT |
11504 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
11505 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 11506 | |
b3646477 | 11507 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
89a27f4d GN |
11508 | sregs->idt.limit = dt.size; |
11509 | sregs->idt.base = dt.address; | |
b3646477 | 11510 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
89a27f4d GN |
11511 | sregs->gdt.limit = dt.size; |
11512 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 11513 | |
ad312c7c | 11514 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 11515 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
11516 | |
11517 | skip_protected_regs: | |
11518 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 11519 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 11520 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 11521 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc | 11522 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6dba9403 | 11523 | } |
b6c7a5dc | 11524 | |
6dba9403 ML |
11525 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
11526 | { | |
11527 | __get_sregs_common(vcpu, sregs); | |
11528 | ||
11529 | if (vcpu->arch.guest_state_protected) | |
11530 | return; | |
b6c7a5dc | 11531 | |
04140b41 | 11532 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
11533 | set_bit(vcpu->arch.interrupt.nr, |
11534 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 11535 | } |
16d7a191 | 11536 | |
6dba9403 ML |
11537 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
11538 | { | |
11539 | int i; | |
11540 | ||
11541 | __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); | |
11542 | ||
11543 | if (vcpu->arch.guest_state_protected) | |
11544 | return; | |
11545 | ||
11546 | if (is_pae_paging(vcpu)) { | |
11547 | for (i = 0 ; i < 4 ; i++) | |
11548 | sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); | |
11549 | sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
11550 | } | |
11551 | } | |
11552 | ||
01643c51 KH |
11553 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
11554 | struct kvm_sregs *sregs) | |
11555 | { | |
11556 | vcpu_load(vcpu); | |
11557 | __get_sregs(vcpu, sregs); | |
bcdec41c | 11558 | vcpu_put(vcpu); |
b6c7a5dc HB |
11559 | return 0; |
11560 | } | |
11561 | ||
62d9f0db MT |
11562 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
11563 | struct kvm_mp_state *mp_state) | |
11564 | { | |
4fe09bcf JM |
11565 | int r; |
11566 | ||
fd232561 | 11567 | vcpu_load(vcpu); |
f958bd23 SC |
11568 | if (kvm_mpx_supported()) |
11569 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 11570 | |
4fe09bcf JM |
11571 | r = kvm_apic_accept_events(vcpu); |
11572 | if (r < 0) | |
11573 | goto out; | |
11574 | r = 0; | |
11575 | ||
647daca2 TL |
11576 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
11577 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
11578 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
11579 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
11580 | else | |
11581 | mp_state->mp_state = vcpu->arch.mp_state; | |
11582 | ||
4fe09bcf | 11583 | out: |
f958bd23 SC |
11584 | if (kvm_mpx_supported()) |
11585 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 11586 | vcpu_put(vcpu); |
4fe09bcf | 11587 | return r; |
62d9f0db MT |
11588 | } |
11589 | ||
11590 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
11591 | struct kvm_mp_state *mp_state) | |
11592 | { | |
e83dff5e CD |
11593 | int ret = -EINVAL; |
11594 | ||
11595 | vcpu_load(vcpu); | |
11596 | ||
22c6a0ef PB |
11597 | switch (mp_state->mp_state) { |
11598 | case KVM_MP_STATE_UNINITIALIZED: | |
11599 | case KVM_MP_STATE_HALTED: | |
11600 | case KVM_MP_STATE_AP_RESET_HOLD: | |
11601 | case KVM_MP_STATE_INIT_RECEIVED: | |
11602 | case KVM_MP_STATE_SIPI_RECEIVED: | |
11603 | if (!lapic_in_kernel(vcpu)) | |
11604 | goto out; | |
11605 | break; | |
11606 | ||
11607 | case KVM_MP_STATE_RUNNABLE: | |
11608 | break; | |
11609 | ||
11610 | default: | |
e83dff5e | 11611 | goto out; |
22c6a0ef | 11612 | } |
66450a21 | 11613 | |
27cbe7d6 | 11614 | /* |
1b7a1b78 SC |
11615 | * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow |
11616 | * forcing the guest into INIT/SIPI if those events are supposed to be | |
11617 | * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state | |
11618 | * if an SMI is pending as well. | |
27cbe7d6 | 11619 | */ |
1b7a1b78 | 11620 | if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) && |
28bf2888 DH |
11621 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
11622 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 11623 | goto out; |
28bf2888 | 11624 | |
66450a21 JK |
11625 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
11626 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
11627 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
11628 | } else | |
11629 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 11630 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
11631 | |
11632 | ret = 0; | |
11633 | out: | |
11634 | vcpu_put(vcpu); | |
11635 | return ret; | |
62d9f0db MT |
11636 | } |
11637 | ||
7f3d35fd KW |
11638 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
11639 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 11640 | { |
c9b8b07c | 11641 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 11642 | int ret; |
e01c2426 | 11643 | |
8ec4722d | 11644 | init_emulate_ctxt(vcpu); |
c697518a | 11645 | |
7f3d35fd | 11646 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 11647 | has_error_code, error_code); |
1051778f SC |
11648 | if (ret) { |
11649 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
11650 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
11651 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 11652 | return 0; |
1051778f | 11653 | } |
37817f29 | 11654 | |
9d74191a TY |
11655 | kvm_rip_write(vcpu, ctxt->eip); |
11656 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 11657 | return 1; |
37817f29 IE |
11658 | } |
11659 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
11660 | ||
ee69c92b | 11661 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 11662 | { |
37b95951 | 11663 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
11664 | /* |
11665 | * When EFER.LME and CR0.PG are set, the processor is in | |
11666 | * 64-bit mode (though maybe in a 32-bit code segment). | |
11667 | * CR4.PAE and EFER.LMA must be set. | |
11668 | */ | |
ee69c92b SC |
11669 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
11670 | return false; | |
2c49db45 | 11671 | if (!kvm_vcpu_is_legal_cr3(vcpu, sregs->cr3)) |
c1c35cf7 | 11672 | return false; |
f2981033 LT |
11673 | } else { |
11674 | /* | |
11675 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
11676 | * segment cannot be 64-bit. | |
11677 | */ | |
11678 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 11679 | return false; |
f2981033 LT |
11680 | } |
11681 | ||
26a0652c SC |
11682 | return kvm_is_valid_cr4(vcpu, sregs->cr4) && |
11683 | kvm_is_valid_cr0(vcpu, sregs->cr0); | |
f2981033 LT |
11684 | } |
11685 | ||
6dba9403 ML |
11686 | static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, |
11687 | int *mmu_reset_needed, bool update_pdptrs) | |
b6c7a5dc | 11688 | { |
58cb628d | 11689 | struct msr_data apic_base_msr; |
6dba9403 | 11690 | int idx; |
89a27f4d | 11691 | struct desc_ptr dt; |
b4ef9d4e | 11692 | |
ee69c92b | 11693 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
6dba9403 | 11694 | return -EINVAL; |
f2981033 | 11695 | |
d3802286 JM |
11696 | apic_base_msr.data = sregs->apic_base; |
11697 | apic_base_msr.host_initiated = true; | |
11698 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
6dba9403 | 11699 | return -EINVAL; |
6d1068b3 | 11700 | |
5265713a | 11701 | if (vcpu->arch.guest_state_protected) |
6dba9403 | 11702 | return 0; |
5265713a | 11703 | |
89a27f4d GN |
11704 | dt.size = sregs->idt.limit; |
11705 | dt.address = sregs->idt.base; | |
b3646477 | 11706 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
89a27f4d GN |
11707 | dt.size = sregs->gdt.limit; |
11708 | dt.address = sregs->gdt.base; | |
b3646477 | 11709 | static_call(kvm_x86_set_gdt)(vcpu, &dt); |
b6c7a5dc | 11710 | |
ad312c7c | 11711 | vcpu->arch.cr2 = sregs->cr2; |
6dba9403 | 11712 | *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 11713 | vcpu->arch.cr3 = sregs->cr3; |
3883bc9d | 11714 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); |
405329fc | 11715 | static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3); |
b6c7a5dc | 11716 | |
2d3ad1f4 | 11717 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 11718 | |
6dba9403 | 11719 | *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b3646477 | 11720 | static_call(kvm_x86_set_efer)(vcpu, sregs->efer); |
b6c7a5dc | 11721 | |
6dba9403 | 11722 | *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b3646477 | 11723 | static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); |
b6c7a5dc | 11724 | |
6dba9403 | 11725 | *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b3646477 | 11726 | static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); |
63f42e02 | 11727 | |
6dba9403 ML |
11728 | if (update_pdptrs) { |
11729 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
11730 | if (is_pae_paging(vcpu)) { | |
2df4a5eb | 11731 | load_pdptrs(vcpu, kvm_read_cr3(vcpu)); |
6dba9403 ML |
11732 | *mmu_reset_needed = 1; |
11733 | } | |
11734 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
7c93be44 | 11735 | } |
b6c7a5dc | 11736 | |
3e6e0aab GT |
11737 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
11738 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
11739 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
11740 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
11741 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
11742 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 11743 | |
3e6e0aab GT |
11744 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
11745 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 11746 | |
5f0269f5 ME |
11747 | update_cr8_intercept(vcpu); |
11748 | ||
9c3e4aab | 11749 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 11750 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 11751 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 11752 | !is_protmode(vcpu)) |
9c3e4aab MT |
11753 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
11754 | ||
6dba9403 ML |
11755 | return 0; |
11756 | } | |
11757 | ||
11758 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
11759 | { | |
11760 | int pending_vec, max_bits; | |
11761 | int mmu_reset_needed = 0; | |
11762 | int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); | |
11763 | ||
11764 | if (ret) | |
11765 | return ret; | |
11766 | ||
4346db6e | 11767 | if (mmu_reset_needed) { |
6dba9403 | 11768 | kvm_mmu_reset_context(vcpu); |
4346db6e ML |
11769 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
11770 | } | |
6dba9403 | 11771 | |
5265713a TL |
11772 | max_bits = KVM_NR_INTERRUPTS; |
11773 | pending_vec = find_first_bit( | |
11774 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6dba9403 | 11775 | |
5265713a TL |
11776 | if (pending_vec < max_bits) { |
11777 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
11778 | pr_debug("Set back pending irq %d\n", pending_vec); | |
6dba9403 | 11779 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5265713a | 11780 | } |
6dba9403 ML |
11781 | return 0; |
11782 | } | |
5265713a | 11783 | |
6dba9403 ML |
11784 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
11785 | { | |
11786 | int mmu_reset_needed = 0; | |
11787 | bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
11788 | bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && | |
11789 | !(sregs2->efer & EFER_LMA); | |
11790 | int i, ret; | |
3842d135 | 11791 | |
6dba9403 ML |
11792 | if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) |
11793 | return -EINVAL; | |
11794 | ||
11795 | if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) | |
11796 | return -EINVAL; | |
11797 | ||
11798 | ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, | |
11799 | &mmu_reset_needed, !valid_pdptrs); | |
11800 | if (ret) | |
11801 | return ret; | |
11802 | ||
11803 | if (valid_pdptrs) { | |
11804 | for (i = 0; i < 4 ; i++) | |
11805 | kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); | |
11806 | ||
11807 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
11808 | mmu_reset_needed = 1; | |
158a48ec | 11809 | vcpu->arch.pdptrs_from_userspace = true; |
6dba9403 | 11810 | } |
4346db6e | 11811 | if (mmu_reset_needed) { |
6dba9403 | 11812 | kvm_mmu_reset_context(vcpu); |
4346db6e ML |
11813 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
11814 | } | |
6dba9403 | 11815 | return 0; |
01643c51 KH |
11816 | } |
11817 | ||
11818 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
11819 | struct kvm_sregs *sregs) | |
11820 | { | |
11821 | int ret; | |
11822 | ||
11823 | vcpu_load(vcpu); | |
11824 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
11825 | vcpu_put(vcpu); |
11826 | return ret; | |
b6c7a5dc HB |
11827 | } |
11828 | ||
cae72dcc ML |
11829 | static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) |
11830 | { | |
320af55a | 11831 | bool set = false; |
cae72dcc | 11832 | struct kvm_vcpu *vcpu; |
46808a4c | 11833 | unsigned long i; |
cae72dcc | 11834 | |
0047fb33 SC |
11835 | if (!enable_apicv) |
11836 | return; | |
11837 | ||
cae72dcc ML |
11838 | down_write(&kvm->arch.apicv_update_lock); |
11839 | ||
11840 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
11841 | if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { | |
320af55a | 11842 | set = true; |
cae72dcc ML |
11843 | break; |
11844 | } | |
11845 | } | |
320af55a | 11846 | __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set); |
cae72dcc ML |
11847 | up_write(&kvm->arch.apicv_update_lock); |
11848 | } | |
11849 | ||
d0bfb940 JK |
11850 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
11851 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 11852 | { |
355be0b9 | 11853 | unsigned long rflags; |
ae675ef0 | 11854 | int i, r; |
b6c7a5dc | 11855 | |
8d4846b9 TL |
11856 | if (vcpu->arch.guest_state_protected) |
11857 | return -EINVAL; | |
11858 | ||
66b56562 CD |
11859 | vcpu_load(vcpu); |
11860 | ||
4f926bf2 JK |
11861 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
11862 | r = -EBUSY; | |
7709aba8 | 11863 | if (kvm_is_exception_pending(vcpu)) |
2122ff5e | 11864 | goto out; |
4f926bf2 JK |
11865 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
11866 | kvm_queue_exception(vcpu, DB_VECTOR); | |
11867 | else | |
11868 | kvm_queue_exception(vcpu, BP_VECTOR); | |
11869 | } | |
11870 | ||
91586a3b JK |
11871 | /* |
11872 | * Read rflags as long as potentially injected trace flags are still | |
11873 | * filtered out. | |
11874 | */ | |
11875 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
11876 | |
11877 | vcpu->guest_debug = dbg->control; | |
11878 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
11879 | vcpu->guest_debug = 0; | |
11880 | ||
11881 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
11882 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
11883 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 11884 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
11885 | } else { |
11886 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
11887 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 11888 | } |
c8639010 | 11889 | kvm_update_dr7(vcpu); |
ae675ef0 | 11890 | |
f92653ee | 11891 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
e87e46d5 | 11892 | vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); |
94fe45da | 11893 | |
91586a3b JK |
11894 | /* |
11895 | * Trigger an rflags update that will inject or remove the trace | |
11896 | * flags. | |
11897 | */ | |
11898 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 11899 | |
b3646477 | 11900 | static_call(kvm_x86_update_exception_bitmap)(vcpu); |
b6c7a5dc | 11901 | |
cae72dcc ML |
11902 | kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); |
11903 | ||
4f926bf2 | 11904 | r = 0; |
d0bfb940 | 11905 | |
2122ff5e | 11906 | out: |
66b56562 | 11907 | vcpu_put(vcpu); |
b6c7a5dc HB |
11908 | return r; |
11909 | } | |
11910 | ||
8b006791 ZX |
11911 | /* |
11912 | * Translate a guest virtual address to a guest physical address. | |
11913 | */ | |
11914 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
11915 | struct kvm_translation *tr) | |
11916 | { | |
11917 | unsigned long vaddr = tr->linear_address; | |
11918 | gpa_t gpa; | |
f656ce01 | 11919 | int idx; |
8b006791 | 11920 | |
1da5b61d CD |
11921 | vcpu_load(vcpu); |
11922 | ||
f656ce01 | 11923 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 11924 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 11925 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 | 11926 | tr->physical_address = gpa; |
6e1d2a3f | 11927 | tr->valid = gpa != INVALID_GPA; |
8b006791 ZX |
11928 | tr->writeable = 1; |
11929 | tr->usermode = 0; | |
8b006791 | 11930 | |
1da5b61d | 11931 | vcpu_put(vcpu); |
8b006791 ZX |
11932 | return 0; |
11933 | } | |
11934 | ||
d0752060 HB |
11935 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
11936 | { | |
1393123e | 11937 | struct fxregs_state *fxsave; |
d0752060 | 11938 | |
d69c1382 | 11939 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
11940 | return 0; |
11941 | ||
1393123e | 11942 | vcpu_load(vcpu); |
d0752060 | 11943 | |
d69c1382 | 11944 | fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; |
d0752060 HB |
11945 | memcpy(fpu->fpr, fxsave->st_space, 128); |
11946 | fpu->fcw = fxsave->cwd; | |
11947 | fpu->fsw = fxsave->swd; | |
11948 | fpu->ftwx = fxsave->twd; | |
11949 | fpu->last_opcode = fxsave->fop; | |
11950 | fpu->last_ip = fxsave->rip; | |
11951 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 11952 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 11953 | |
1393123e | 11954 | vcpu_put(vcpu); |
d0752060 HB |
11955 | return 0; |
11956 | } | |
11957 | ||
11958 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
11959 | { | |
6a96bc7f CD |
11960 | struct fxregs_state *fxsave; |
11961 | ||
d69c1382 | 11962 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
11963 | return 0; |
11964 | ||
6a96bc7f CD |
11965 | vcpu_load(vcpu); |
11966 | ||
d69c1382 | 11967 | fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; |
d0752060 | 11968 | |
d0752060 HB |
11969 | memcpy(fxsave->st_space, fpu->fpr, 128); |
11970 | fxsave->cwd = fpu->fcw; | |
11971 | fxsave->swd = fpu->fsw; | |
11972 | fxsave->twd = fpu->ftwx; | |
11973 | fxsave->fop = fpu->last_opcode; | |
11974 | fxsave->rip = fpu->last_ip; | |
11975 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 11976 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 11977 | |
6a96bc7f | 11978 | vcpu_put(vcpu); |
d0752060 HB |
11979 | return 0; |
11980 | } | |
11981 | ||
01643c51 KH |
11982 | static void store_regs(struct kvm_vcpu *vcpu) |
11983 | { | |
11984 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
11985 | ||
11986 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
11987 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
11988 | ||
11989 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
11990 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
11991 | ||
11992 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
11993 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
11994 | vcpu, &vcpu->run->s.regs.events); | |
11995 | } | |
11996 | ||
11997 | static int sync_regs(struct kvm_vcpu *vcpu) | |
11998 | { | |
01643c51 KH |
11999 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { |
12000 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
12001 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
12002 | } | |
0d033770 | 12003 | |
01643c51 | 12004 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { |
0d033770 ML |
12005 | struct kvm_sregs sregs = vcpu->run->s.regs.sregs; |
12006 | ||
12007 | if (__set_sregs(vcpu, &sregs)) | |
01643c51 | 12008 | return -EINVAL; |
0d033770 | 12009 | |
01643c51 KH |
12010 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; |
12011 | } | |
0d033770 | 12012 | |
01643c51 | 12013 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { |
0d033770 ML |
12014 | struct kvm_vcpu_events events = vcpu->run->s.regs.events; |
12015 | ||
12016 | if (kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events)) | |
01643c51 | 12017 | return -EINVAL; |
0d033770 | 12018 | |
01643c51 KH |
12019 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; |
12020 | } | |
12021 | ||
12022 | return 0; | |
12023 | } | |
12024 | ||
897cc38e | 12025 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 12026 | { |
1d5e740d | 12027 | if (kvm_check_tsc_unstable() && kvm->created_vcpus) |
8d20bd63 | 12028 | pr_warn_once("SMP vm created on host with unstable TSC; " |
897cc38e | 12029 | "guest TSC will not be reliable\n"); |
7f1ea208 | 12030 | |
35875316 ZG |
12031 | if (!kvm->arch.max_vcpu_ids) |
12032 | kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS; | |
12033 | ||
12034 | if (id >= kvm->arch.max_vcpu_ids) | |
12035 | return -EINVAL; | |
12036 | ||
d588bb9b | 12037 | return static_call(kvm_x86_vcpu_precreate)(kvm); |
e9b11c17 ZX |
12038 | } |
12039 | ||
e529ef66 | 12040 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 12041 | { |
95a0d01e SC |
12042 | struct page *page; |
12043 | int r; | |
c447e76b | 12044 | |
63f5a190 | 12045 | vcpu->arch.last_vmentry_cpu = -1; |
7117003f SC |
12046 | vcpu->arch.regs_avail = ~0; |
12047 | vcpu->arch.regs_dirty = ~0; | |
63f5a190 | 12048 | |
8c82a0b3 | 12049 | kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN); |
52491a38 | 12050 | |
95a0d01e SC |
12051 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
12052 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
12053 | else | |
12054 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 12055 | |
95a0d01e SC |
12056 | r = kvm_mmu_create(vcpu); |
12057 | if (r < 0) | |
12058 | return r; | |
12059 | ||
12060 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
12061 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
12062 | if (r < 0) | |
12063 | goto fail_mmu_destroy; | |
423ecfea SC |
12064 | |
12065 | /* | |
12066 | * Defer evaluating inhibits until the vCPU is first run, as | |
12067 | * this vCPU will not get notified of any changes until this | |
12068 | * vCPU is visible to other vCPUs (marked online and added to | |
12069 | * the set of vCPUs). Opportunistically mark APICv active as | |
12070 | * VMX in particularly is highly unlikely to have inhibits. | |
12071 | * Ignore the current per-VM APICv state so that vCPU creation | |
12072 | * is guaranteed to run with a deterministic value, the request | |
12073 | * will ensure the vCPU gets the correct state before VM-Entry. | |
12074 | */ | |
12075 | if (enable_apicv) { | |
ce0a58f4 | 12076 | vcpu->arch.apic->apicv_active = true; |
423ecfea SC |
12077 | kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); |
12078 | } | |
95a0d01e | 12079 | } else |
6e4e3b4d | 12080 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
12081 | |
12082 | r = -ENOMEM; | |
12083 | ||
93bb59ca | 12084 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
12085 | if (!page) |
12086 | goto fail_free_lapic; | |
12087 | vcpu->arch.pio_data = page_address(page); | |
12088 | ||
087acc4e | 12089 | vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64), |
95a0d01e | 12090 | GFP_KERNEL_ACCOUNT); |
281b5278 JW |
12091 | vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64), |
12092 | GFP_KERNEL_ACCOUNT); | |
12093 | if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks) | |
3c0ba05c | 12094 | goto fail_free_mce_banks; |
95a0d01e SC |
12095 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; |
12096 | ||
12097 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
12098 | GFP_KERNEL_ACCOUNT)) | |
12099 | goto fail_free_mce_banks; | |
12100 | ||
c9b8b07c SC |
12101 | if (!alloc_emulate_ctxt(vcpu)) |
12102 | goto free_wbinvd_dirty_mask; | |
12103 | ||
d69c1382 | 12104 | if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { |
8d20bd63 | 12105 | pr_err("failed to allocate vcpu's fpu\n"); |
c9b8b07c | 12106 | goto free_emulate_ctxt; |
95a0d01e SC |
12107 | } |
12108 | ||
95a0d01e | 12109 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 12110 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
95a0d01e SC |
12111 | |
12112 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
12113 | ||
12114 | kvm_async_pf_hash_reset(vcpu); | |
6c6f82be SC |
12115 | |
12116 | vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap; | |
95a0d01e SC |
12117 | kvm_pmu_init(vcpu); |
12118 | ||
12119 | vcpu->arch.pending_external_vector = -1; | |
12120 | vcpu->arch.preempted_in_kernel = false; | |
12121 | ||
3c86c0d3 VP |
12122 | #if IS_ENABLED(CONFIG_HYPERV) |
12123 | vcpu->arch.hv_root_tdp = INVALID_PAGE; | |
12124 | #endif | |
12125 | ||
b3646477 | 12126 | r = static_call(kvm_x86_vcpu_create)(vcpu); |
95a0d01e SC |
12127 | if (r) |
12128 | goto free_guest_fpu; | |
e9b11c17 | 12129 | |
0cf9135b | 12130 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 12131 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
942c2490 | 12132 | kvm_xen_init_vcpu(vcpu); |
19efffa2 | 12133 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 12134 | vcpu_load(vcpu); |
ffbb61d0 | 12135 | kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz); |
d28bc9dd | 12136 | kvm_vcpu_reset(vcpu, false); |
c9060662 | 12137 | kvm_init_mmu(vcpu); |
e9b11c17 | 12138 | vcpu_put(vcpu); |
ec7660cc | 12139 | return 0; |
95a0d01e SC |
12140 | |
12141 | free_guest_fpu: | |
d69c1382 | 12142 | fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); |
c9b8b07c SC |
12143 | free_emulate_ctxt: |
12144 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
12145 | free_wbinvd_dirty_mask: |
12146 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
12147 | fail_free_mce_banks: | |
12148 | kfree(vcpu->arch.mce_banks); | |
281b5278 | 12149 | kfree(vcpu->arch.mci_ctl2_banks); |
95a0d01e SC |
12150 | free_page((unsigned long)vcpu->arch.pio_data); |
12151 | fail_free_lapic: | |
12152 | kvm_free_lapic(vcpu); | |
12153 | fail_mmu_destroy: | |
12154 | kvm_mmu_destroy(vcpu); | |
12155 | return r; | |
e9b11c17 ZX |
12156 | } |
12157 | ||
31928aa5 | 12158 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 12159 | { |
332967a3 | 12160 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 12161 | |
ec7660cc | 12162 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 12163 | return; |
ec7660cc | 12164 | vcpu_load(vcpu); |
bf328e22 | 12165 | kvm_synchronize_tsc(vcpu, NULL); |
42897d86 | 12166 | vcpu_put(vcpu); |
2d5ba19b MT |
12167 | |
12168 | /* poll control enabled by default */ | |
12169 | vcpu->arch.msr_kvm_poll_control = 1; | |
12170 | ||
ec7660cc | 12171 | mutex_unlock(&vcpu->mutex); |
42897d86 | 12172 | |
b34de572 WL |
12173 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
12174 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
12175 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
12176 | } |
12177 | ||
d40ccc62 | 12178 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 12179 | { |
95a0d01e | 12180 | int idx; |
344d9588 | 12181 | |
50b143e1 | 12182 | kvmclock_reset(vcpu); |
e9b11c17 | 12183 | |
b3646477 | 12184 | static_call(kvm_x86_vcpu_free)(vcpu); |
50b143e1 | 12185 | |
c9b8b07c | 12186 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 | 12187 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
d69c1382 | 12188 | fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); |
95a0d01e | 12189 | |
a795cd43 | 12190 | kvm_xen_destroy_vcpu(vcpu); |
95a0d01e SC |
12191 | kvm_hv_vcpu_uninit(vcpu); |
12192 | kvm_pmu_destroy(vcpu); | |
12193 | kfree(vcpu->arch.mce_banks); | |
281b5278 | 12194 | kfree(vcpu->arch.mci_ctl2_banks); |
95a0d01e SC |
12195 | kvm_free_lapic(vcpu); |
12196 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
12197 | kvm_mmu_destroy(vcpu); | |
12198 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
12199 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 12200 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 12201 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 12202 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
12203 | } |
12204 | ||
d28bc9dd | 12205 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 12206 | { |
25b97845 | 12207 | struct kvm_cpuid_entry2 *cpuid_0x1; |
0aa18375 | 12208 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
4c72ab5a | 12209 | unsigned long new_cr0; |
0aa18375 | 12210 | |
62dd57dd SC |
12211 | /* |
12212 | * Several of the "set" flows, e.g. ->set_cr0(), read other registers | |
12213 | * to handle side effects. RESET emulation hits those flows and relies | |
12214 | * on emulated/virtualized registers, including those that are loaded | |
12215 | * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel | |
12216 | * to detect improper or missing initialization. | |
12217 | */ | |
12218 | WARN_ON_ONCE(!init_event && | |
12219 | (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); | |
0aa18375 | 12220 | |
ed129ec9 ML |
12221 | /* |
12222 | * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's | |
12223 | * possible to INIT the vCPU while L2 is active. Force the vCPU back | |
12224 | * into L1 as EFER.SVME is cleared on INIT (along with all other EFER | |
12225 | * bits), i.e. virtualization is disabled. | |
12226 | */ | |
12227 | if (is_guest_mode(vcpu)) | |
12228 | kvm_leave_nested(vcpu); | |
12229 | ||
b7e31be3 RK |
12230 | kvm_lapic_reset(vcpu, init_event); |
12231 | ||
ed129ec9 | 12232 | WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu)); |
e69fab5d PB |
12233 | vcpu->arch.hflags = 0; |
12234 | ||
c43203ca | 12235 | vcpu->arch.smi_pending = 0; |
52797bf9 | 12236 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
12237 | atomic_set(&vcpu->arch.nmi_queued, 0); |
12238 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 12239 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
12240 | kvm_clear_interrupt_queue(vcpu); |
12241 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 12242 | |
42dbaa5a | 12243 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 12244 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 12245 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 12246 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 12247 | kvm_update_dr7(vcpu); |
42dbaa5a | 12248 | |
1119022c NA |
12249 | vcpu->arch.cr2 = 0; |
12250 | ||
3842d135 | 12251 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
12252 | vcpu->arch.apf.msr_en_val = 0; |
12253 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 12254 | vcpu->arch.st.msr_val = 0; |
3842d135 | 12255 | |
12f9a48f GC |
12256 | kvmclock_reset(vcpu); |
12257 | ||
af585b92 GN |
12258 | kvm_clear_async_pf_completion_queue(vcpu); |
12259 | kvm_async_pf_hash_reset(vcpu); | |
12260 | vcpu->arch.apf.halted = false; | |
3842d135 | 12261 | |
d69c1382 TG |
12262 | if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { |
12263 | struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; | |
a554d207 WL |
12264 | |
12265 | /* | |
a61353ac SC |
12266 | * All paths that lead to INIT are required to load the guest's |
12267 | * FPU state (because most paths are buried in KVM_RUN). | |
a554d207 | 12268 | */ |
f775b13e RR |
12269 | if (init_event) |
12270 | kvm_put_guest_fpu(vcpu); | |
087df48c TG |
12271 | |
12272 | fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); | |
12273 | fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); | |
12274 | ||
f775b13e RR |
12275 | if (init_event) |
12276 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
12277 | } |
12278 | ||
64d60670 | 12279 | if (!init_event) { |
64d60670 | 12280 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 12281 | |
db2336a8 | 12282 | vcpu->arch.msr_misc_features_enables = 0; |
9fc22296 SC |
12283 | vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | |
12284 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL; | |
a554d207 | 12285 | |
05a9e065 LX |
12286 | __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); |
12287 | __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); | |
64d60670 | 12288 | } |
f5132b01 | 12289 | |
ff8828c8 | 12290 | /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ |
66f7b72e | 12291 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
ff8828c8 | 12292 | kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); |
66f7b72e | 12293 | |
49d8665c SC |
12294 | /* |
12295 | * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) | |
12296 | * if no CPUID match is found. Note, it's impossible to get a match at | |
12297 | * RESET since KVM emulates RESET before exposing the vCPU to userspace, | |
25b97845 SC |
12298 | * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry |
12299 | * on RESET. But, go through the motions in case that's ever remedied. | |
49d8665c | 12300 | */ |
277ad7d5 | 12301 | cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1); |
25b97845 | 12302 | kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); |
49d8665c | 12303 | |
b3646477 | 12304 | static_call(kvm_x86_vcpu_reset)(vcpu, init_event); |
0aa18375 | 12305 | |
f39e805e SC |
12306 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
12307 | kvm_rip_write(vcpu, 0xfff0); | |
12308 | ||
03a6e840 SC |
12309 | vcpu->arch.cr3 = 0; |
12310 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); | |
12311 | ||
4c72ab5a SC |
12312 | /* |
12313 | * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions | |
12314 | * of Intel's SDM list CD/NW as being set on INIT, but they contradict | |
12315 | * (or qualify) that with a footnote stating that CD/NW are preserved. | |
12316 | */ | |
12317 | new_cr0 = X86_CR0_ET; | |
12318 | if (init_event) | |
12319 | new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); | |
12320 | else | |
12321 | new_cr0 |= X86_CR0_NW | X86_CR0_CD; | |
12322 | ||
12323 | static_call(kvm_x86_set_cr0)(vcpu, new_cr0); | |
f39e805e SC |
12324 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
12325 | static_call(kvm_x86_set_efer)(vcpu, 0); | |
12326 | static_call(kvm_x86_update_exception_bitmap)(vcpu); | |
12327 | ||
0aa18375 | 12328 | /* |
b5f61c03 PB |
12329 | * On the standard CR0/CR4/EFER modification paths, there are several |
12330 | * complex conditions determining whether the MMU has to be reset and/or | |
12331 | * which PCIDs have to be flushed. However, CR0.WP and the paging-related | |
12332 | * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush | |
12333 | * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as | |
12334 | * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here. | |
0aa18375 | 12335 | */ |
b5f61c03 PB |
12336 | if (old_cr0 & X86_CR0_PG) { |
12337 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
0aa18375 | 12338 | kvm_mmu_reset_context(vcpu); |
b5f61c03 | 12339 | } |
df37ed38 SC |
12340 | |
12341 | /* | |
12342 | * Intel's SDM states that all TLB entries are flushed on INIT. AMD's | |
12343 | * APM states the TLBs are untouched by INIT, but it also states that | |
12344 | * the TLBs are flushed on "External initialization of the processor." | |
12345 | * Flush the guest TLB regardless of vendor, there is no meaningful | |
12346 | * benefit in relying on the guest to flush the TLB immediately after | |
12347 | * INIT. A spurious TLB flush is benign and likely negligible from a | |
12348 | * performance perspective. | |
12349 | */ | |
12350 | if (init_event) | |
12351 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
e9b11c17 | 12352 | } |
265e4353 | 12353 | EXPORT_SYMBOL_GPL(kvm_vcpu_reset); |
e9b11c17 | 12354 | |
2b4a273b | 12355 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
12356 | { |
12357 | struct kvm_segment cs; | |
12358 | ||
12359 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
12360 | cs.selector = vector << 8; | |
12361 | cs.base = vector << 12; | |
12362 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
12363 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 12364 | } |
647daca2 | 12365 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 12366 | |
13a34e06 | 12367 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 12368 | { |
ca84d1a2 ZA |
12369 | struct kvm *kvm; |
12370 | struct kvm_vcpu *vcpu; | |
46808a4c | 12371 | unsigned long i; |
0dd6a6ed ZA |
12372 | int ret; |
12373 | u64 local_tsc; | |
12374 | u64 max_tsc = 0; | |
12375 | bool stable, backwards_tsc = false; | |
18863bdd | 12376 | |
7e34fbd0 | 12377 | kvm_user_return_msr_cpu_online(); |
c82a5c5c CG |
12378 | |
12379 | ret = kvm_x86_check_processor_compatibility(); | |
12380 | if (ret) | |
12381 | return ret; | |
12382 | ||
b3646477 | 12383 | ret = static_call(kvm_x86_hardware_enable)(); |
0dd6a6ed ZA |
12384 | if (ret != 0) |
12385 | return ret; | |
12386 | ||
4ea1636b | 12387 | local_tsc = rdtsc(); |
b0c39dc6 | 12388 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
12389 | list_for_each_entry(kvm, &vm_list, vm_list) { |
12390 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
12391 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 12392 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
12393 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
12394 | backwards_tsc = true; | |
12395 | if (vcpu->arch.last_host_tsc > max_tsc) | |
12396 | max_tsc = vcpu->arch.last_host_tsc; | |
12397 | } | |
12398 | } | |
12399 | } | |
12400 | ||
12401 | /* | |
12402 | * Sometimes, even reliable TSCs go backwards. This happens on | |
12403 | * platforms that reset TSC during suspend or hibernate actions, but | |
12404 | * maintain synchronization. We must compensate. Fortunately, we can | |
12405 | * detect that condition here, which happens early in CPU bringup, | |
12406 | * before any KVM threads can be running. Unfortunately, we can't | |
12407 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
12408 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 12409 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
12410 | * variables that haven't been updated yet. |
12411 | * | |
12412 | * So we simply find the maximum observed TSC above, then record the | |
12413 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
12414 | * the adjustment will be applied. Note that we accumulate | |
12415 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
12416 | * gets a chance to run again. In the event that no KVM threads get a | |
12417 | * chance to run, we will miss the entire elapsed period, as we'll have | |
12418 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
12419 | * loose cycle time. This isn't too big a deal, since the loss will be | |
12420 | * uniform across all VCPUs (not to mention the scenario is extremely | |
12421 | * unlikely). It is possible that a second hibernate recovery happens | |
12422 | * much faster than a first, causing the observed TSC here to be | |
12423 | * smaller; this would require additional padding adjustment, which is | |
12424 | * why we set last_host_tsc to the local tsc observed here. | |
12425 | * | |
12426 | * N.B. - this code below runs only on platforms with reliable TSC, | |
12427 | * as that is the only way backwards_tsc is set above. Also note | |
12428 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
12429 | * have the same delta_cyc adjustment applied if backwards_tsc | |
12430 | * is detected. Note further, this adjustment is only done once, | |
12431 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
12432 | * called multiple times (one for each physical CPU bringup). | |
12433 | * | |
4a969980 | 12434 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
12435 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
12436 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
12437 | * guarantee that they stay in perfect synchronization. | |
12438 | */ | |
12439 | if (backwards_tsc) { | |
12440 | u64 delta_cyc = max_tsc - local_tsc; | |
12441 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 12442 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
12443 | kvm_for_each_vcpu(i, vcpu, kvm) { |
12444 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
12445 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 12446 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
12447 | } |
12448 | ||
12449 | /* | |
12450 | * We have to disable TSC offset matching.. if you were | |
12451 | * booting a VM while issuing an S4 host suspend.... | |
12452 | * you may have some problem. Solving this issue is | |
12453 | * left as an exercise to the reader. | |
12454 | */ | |
12455 | kvm->arch.last_tsc_nsec = 0; | |
12456 | kvm->arch.last_tsc_write = 0; | |
12457 | } | |
12458 | ||
12459 | } | |
12460 | return 0; | |
e9b11c17 ZX |
12461 | } |
12462 | ||
13a34e06 | 12463 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 12464 | { |
b3646477 | 12465 | static_call(kvm_x86_hardware_disable)(); |
13a34e06 | 12466 | drop_user_return_notifiers(); |
e9b11c17 ZX |
12467 | } |
12468 | ||
d71ba788 PB |
12469 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) |
12470 | { | |
12471 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
12472 | } | |
d71ba788 PB |
12473 | |
12474 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
12475 | { | |
12476 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
12477 | } |
12478 | ||
6e4e3b4d CL |
12479 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
12480 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 12481 | |
e790d9ef RK |
12482 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
12483 | { | |
b35e5548 LX |
12484 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
12485 | ||
c595ceee | 12486 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
12487 | if (pmu->version && unlikely(pmu->event_count)) { |
12488 | pmu->need_cleanup = true; | |
12489 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
12490 | } | |
b3646477 | 12491 | static_call(kvm_x86_sched_in)(vcpu, cpu); |
e790d9ef RK |
12492 | } |
12493 | ||
562b6b08 SC |
12494 | void kvm_arch_free_vm(struct kvm *kvm) |
12495 | { | |
cfef5af3 VK |
12496 | #if IS_ENABLED(CONFIG_HYPERV) |
12497 | kfree(kvm->arch.hv_pa_pg); | |
12498 | #endif | |
78b497f2 | 12499 | __kvm_arch_free_vm(kvm); |
e790d9ef RK |
12500 | } |
12501 | ||
562b6b08 | 12502 | |
e08b9637 | 12503 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 12504 | { |
eb7511bf | 12505 | int ret; |
869b4421 | 12506 | unsigned long flags; |
eb7511bf | 12507 | |
89ea60c2 | 12508 | if (!kvm_is_vm_type_supported(type)) |
e08b9637 CO |
12509 | return -EINVAL; |
12510 | ||
89ea60c2 SC |
12511 | kvm->arch.vm_type = type; |
12512 | ||
eb7511bf HZ |
12513 | ret = kvm_page_track_init(kvm); |
12514 | if (ret) | |
a1a39128 PB |
12515 | goto out; |
12516 | ||
0df9dab8 | 12517 | kvm_mmu_init_vm(kvm); |
eb7511bf | 12518 | |
b24ede22 JS |
12519 | ret = static_call(kvm_x86_vm_init)(kvm); |
12520 | if (ret) | |
12521 | goto out_uninit_mmu; | |
12522 | ||
6ef768fa | 12523 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
e0f0bbc5 | 12524 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 12525 | |
5550af4d SY |
12526 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
12527 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
12528 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
12529 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
12530 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 12531 | |
038f8c11 | 12532 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 12533 | mutex_init(&kvm->arch.apic_map_lock); |
869b4421 | 12534 | seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); |
8171cd68 | 12535 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
869b4421 PB |
12536 | |
12537 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
d828199e | 12538 | pvclock_update_vm_gtod_copy(kvm); |
869b4421 | 12539 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
53f658b3 | 12540 | |
741e511b | 12541 | kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz; |
6fbbde9a | 12542 | kvm->arch.guest_can_read_msr_platform_info = true; |
ba7bb663 | 12543 | kvm->arch.enable_pmu = enable_pmu; |
6fbbde9a | 12544 | |
3c86c0d3 VP |
12545 | #if IS_ENABLED(CONFIG_HYPERV) |
12546 | spin_lock_init(&kvm->arch.hv_root_tdp_lock); | |
12547 | kvm->arch.hv_root_tdp = INVALID_PAGE; | |
12548 | #endif | |
12549 | ||
7e44e449 | 12550 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 12551 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 12552 | |
4651fc56 | 12553 | kvm_apicv_init(kvm); |
cbc0236a | 12554 | kvm_hv_init_vm(kvm); |
319afe68 | 12555 | kvm_xen_init_vm(kvm); |
0eb05bf2 | 12556 | |
b24ede22 | 12557 | return 0; |
a1a39128 | 12558 | |
b24ede22 JS |
12559 | out_uninit_mmu: |
12560 | kvm_mmu_uninit_vm(kvm); | |
a1a39128 PB |
12561 | kvm_page_track_cleanup(kvm); |
12562 | out: | |
12563 | return ret; | |
d19a9cd2 ZX |
12564 | } |
12565 | ||
1aa9b957 JS |
12566 | int kvm_arch_post_init_vm(struct kvm *kvm) |
12567 | { | |
12568 | return kvm_mmu_post_init_vm(kvm); | |
12569 | } | |
12570 | ||
d19a9cd2 ZX |
12571 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
12572 | { | |
ec7660cc | 12573 | vcpu_load(vcpu); |
d19a9cd2 ZX |
12574 | kvm_mmu_unload(vcpu); |
12575 | vcpu_put(vcpu); | |
12576 | } | |
12577 | ||
6fcee03d | 12578 | static void kvm_unload_vcpu_mmus(struct kvm *kvm) |
d19a9cd2 | 12579 | { |
46808a4c | 12580 | unsigned long i; |
988a2cae | 12581 | struct kvm_vcpu *vcpu; |
d19a9cd2 | 12582 | |
af585b92 GN |
12583 | kvm_for_each_vcpu(i, vcpu, kvm) { |
12584 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 12585 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 12586 | } |
d19a9cd2 ZX |
12587 | } |
12588 | ||
ad8ba2cd SY |
12589 | void kvm_arch_sync_events(struct kvm *kvm) |
12590 | { | |
332967a3 | 12591 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 12592 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 12593 | kvm_free_pit(kvm); |
ad8ba2cd SY |
12594 | } |
12595 | ||
ff5a983c PX |
12596 | /** |
12597 | * __x86_set_memory_region: Setup KVM internal memory slot | |
12598 | * | |
12599 | * @kvm: the kvm pointer to the VM. | |
12600 | * @id: the slot ID to setup. | |
12601 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
12602 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
12603 | * | |
12604 | * This function helps to setup a KVM internal memory slot. Specify | |
12605 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
12606 | * slot. The return code can be one of the following: | |
12607 | * | |
12608 | * HVA: on success (uninstall will return a bogus HVA) | |
12609 | * -errno: on error | |
12610 | * | |
12611 | * The caller should always use IS_ERR() to check the return value | |
12612 | * before use. Note, the KVM internal memory slots are guaranteed to | |
12613 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
12614 | * GPA->HVA translation will not change. However, the HVA is a user | |
12615 | * address, i.e. its accessibility is not guaranteed, and must be | |
12616 | * accessed via __copy_{to,from}_user(). | |
12617 | */ | |
12618 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
12619 | u32 size) | |
9da0e4d5 PB |
12620 | { |
12621 | int i, r; | |
3f649ab7 | 12622 | unsigned long hva, old_npages; |
f0d648bd | 12623 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 12624 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
12625 | |
12626 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 12627 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 12628 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 12629 | |
f0d648bd PB |
12630 | slot = id_to_memslot(slots, id); |
12631 | if (size) { | |
0577d1ab | 12632 | if (slot && slot->npages) |
ff5a983c | 12633 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
12634 | |
12635 | /* | |
12636 | * MAP_SHARED to prevent internal slot pages from being moved | |
12637 | * by fork()/COW. | |
12638 | */ | |
12639 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
12640 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
2eb398df | 12641 | if (IS_ERR_VALUE(hva)) |
ff5a983c | 12642 | return (void __user *)hva; |
f0d648bd | 12643 | } else { |
0577d1ab | 12644 | if (!slot || !slot->npages) |
46914534 | 12645 | return NULL; |
f0d648bd | 12646 | |
0577d1ab | 12647 | old_npages = slot->npages; |
b66f9bab | 12648 | hva = slot->userspace_addr; |
f0d648bd PB |
12649 | } |
12650 | ||
eed52e43 | 12651 | for (i = 0; i < kvm_arch_nr_memslot_as_ids(kvm); i++) { |
bb58b90b | 12652 | struct kvm_userspace_memory_region2 m; |
9da0e4d5 | 12653 | |
1d8007bd PB |
12654 | m.slot = id | (i << 16); |
12655 | m.flags = 0; | |
12656 | m.guest_phys_addr = gpa; | |
f0d648bd | 12657 | m.userspace_addr = hva; |
1d8007bd | 12658 | m.memory_size = size; |
9da0e4d5 PB |
12659 | r = __kvm_set_memory_region(kvm, &m); |
12660 | if (r < 0) | |
ff5a983c | 12661 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
12662 | } |
12663 | ||
103c763c | 12664 | if (!size) |
0577d1ab | 12665 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 12666 | |
ff5a983c | 12667 | return (void __user *)hva; |
9da0e4d5 PB |
12668 | } |
12669 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
12670 | ||
1aa9b957 JS |
12671 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
12672 | { | |
12673 | kvm_mmu_pre_destroy_vm(kvm); | |
12674 | } | |
12675 | ||
d19a9cd2 ZX |
12676 | void kvm_arch_destroy_vm(struct kvm *kvm) |
12677 | { | |
27469d29 AH |
12678 | if (current->mm == kvm->mm) { |
12679 | /* | |
12680 | * Free memory regions allocated on behalf of userspace, | |
f7081834 | 12681 | * unless the memory map has changed due to process exit |
27469d29 AH |
12682 | * or fd copying. |
12683 | */ | |
6a3c623b PX |
12684 | mutex_lock(&kvm->slots_lock); |
12685 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
12686 | 0, 0); | |
12687 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
12688 | 0, 0); | |
12689 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
12690 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 12691 | } |
6fcee03d | 12692 | kvm_unload_vcpu_mmus(kvm); |
b3646477 | 12693 | static_call_cond(kvm_x86_vm_destroy)(kvm); |
b318e8de | 12694 | kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); |
c761159c PX |
12695 | kvm_pic_destroy(kvm); |
12696 | kvm_ioapic_destroy(kvm); | |
6fcee03d | 12697 | kvm_destroy_vcpus(kvm); |
af1bae54 | 12698 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 12699 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 12700 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 12701 | kvm_page_track_cleanup(kvm); |
7d6bbebb | 12702 | kvm_xen_destroy_vm(kvm); |
cbc0236a | 12703 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 12704 | } |
0de10343 | 12705 | |
c9b929b3 | 12706 | static void memslot_rmap_free(struct kvm_memory_slot *slot) |
db3fe4eb TY |
12707 | { |
12708 | int i; | |
12709 | ||
d89cc617 | 12710 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
12711 | kvfree(slot->arch.rmap[i]); |
12712 | slot->arch.rmap[i] = NULL; | |
c9b929b3 BG |
12713 | } |
12714 | } | |
e96c81ee | 12715 | |
c9b929b3 BG |
12716 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
12717 | { | |
12718 | int i; | |
12719 | ||
12720 | memslot_rmap_free(slot); | |
d89cc617 | 12721 | |
c9b929b3 | 12722 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
12723 | kvfree(slot->arch.lpage_info[i - 1]); |
12724 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 12725 | } |
21ebbeda | 12726 | |
e96c81ee | 12727 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
12728 | } |
12729 | ||
1e76a3ce | 12730 | int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) |
56dd1019 BG |
12731 | { |
12732 | const int sz = sizeof(*slot->arch.rmap[0]); | |
12733 | int i; | |
12734 | ||
12735 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
12736 | int level = i + 1; | |
4139b197 | 12737 | int lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
56dd1019 | 12738 | |
fa13843d PB |
12739 | if (slot->arch.rmap[i]) |
12740 | continue; | |
d501f747 | 12741 | |
37b2a651 | 12742 | slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); |
56dd1019 BG |
12743 | if (!slot->arch.rmap[i]) { |
12744 | memslot_rmap_free(slot); | |
12745 | return -ENOMEM; | |
12746 | } | |
12747 | } | |
12748 | ||
12749 | return 0; | |
12750 | } | |
12751 | ||
a2557408 | 12752 | static int kvm_alloc_memslot_metadata(struct kvm *kvm, |
9d7d18ee | 12753 | struct kvm_memory_slot *slot) |
db3fe4eb | 12754 | { |
9d7d18ee | 12755 | unsigned long npages = slot->npages; |
56dd1019 | 12756 | int i, r; |
db3fe4eb | 12757 | |
edd4fa37 SC |
12758 | /* |
12759 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
12760 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
12761 | * the new memslot is successful. | |
12762 | */ | |
12763 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
12764 | ||
e2209710 | 12765 | if (kvm_memslots_have_rmaps(kvm)) { |
a2557408 BG |
12766 | r = memslot_rmap_alloc(slot, npages); |
12767 | if (r) | |
12768 | return r; | |
12769 | } | |
56dd1019 BG |
12770 | |
12771 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { | |
92f94f1e | 12772 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
12773 | unsigned long ugfn; |
12774 | int lpages; | |
d89cc617 | 12775 | int level = i + 1; |
db3fe4eb | 12776 | |
4139b197 | 12777 | lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
db3fe4eb | 12778 | |
37b2a651 | 12779 | linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 12780 | if (!linfo) |
db3fe4eb TY |
12781 | goto out_free; |
12782 | ||
92f94f1e XG |
12783 | slot->arch.lpage_info[i - 1] = linfo; |
12784 | ||
db3fe4eb | 12785 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 12786 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 12787 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 12788 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
12789 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
12790 | /* | |
12791 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 12792 | * other, disable large page support for this slot. |
db3fe4eb | 12793 | */ |
600087b6 | 12794 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
12795 | unsigned long j; |
12796 | ||
12797 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 12798 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
12799 | } |
12800 | } | |
12801 | ||
90b4fe17 CP |
12802 | #ifdef CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES |
12803 | kvm_mmu_init_memslot_memory_attributes(kvm, slot); | |
12804 | #endif | |
12805 | ||
deae4a10 | 12806 | if (kvm_page_track_create_memslot(kvm, slot, npages)) |
21ebbeda XG |
12807 | goto out_free; |
12808 | ||
db3fe4eb TY |
12809 | return 0; |
12810 | ||
12811 | out_free: | |
c9b929b3 | 12812 | memslot_rmap_free(slot); |
d89cc617 | 12813 | |
c9b929b3 | 12814 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 12815 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 12816 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
12817 | } |
12818 | return -ENOMEM; | |
12819 | } | |
12820 | ||
15248258 | 12821 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 12822 | { |
91724814 | 12823 | struct kvm_vcpu *vcpu; |
46808a4c | 12824 | unsigned long i; |
91724814 | 12825 | |
e6dff7d1 TY |
12826 | /* |
12827 | * memslots->generation has been incremented. | |
12828 | * mmio generation may have reached its maximum value. | |
12829 | */ | |
15248258 | 12830 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
12831 | |
12832 | /* Force re-initialization of steal_time cache */ | |
12833 | kvm_for_each_vcpu(i, vcpu, kvm) | |
12834 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
12835 | } |
12836 | ||
f7784b8e | 12837 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
537a17b3 SC |
12838 | const struct kvm_memory_slot *old, |
12839 | struct kvm_memory_slot *new, | |
12840 | enum kvm_mr_change change) | |
0de10343 | 12841 | { |
c70934e0 SC |
12842 | /* |
12843 | * KVM doesn't support moving memslots when there are external page | |
12844 | * trackers attached to the VM, i.e. if KVMGT is in use. | |
12845 | */ | |
12846 | if (change == KVM_MR_MOVE && kvm_page_track_has_external_user(kvm)) | |
12847 | return -EINVAL; | |
12848 | ||
86931ff7 SC |
12849 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) { |
12850 | if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn()) | |
12851 | return -EINVAL; | |
12852 | ||
9d7d18ee | 12853 | return kvm_alloc_memslot_metadata(kvm, new); |
86931ff7 | 12854 | } |
537a17b3 SC |
12855 | |
12856 | if (change == KVM_MR_FLAGS_ONLY) | |
12857 | memcpy(&new->arch, &old->arch, sizeof(old->arch)); | |
12858 | else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) | |
12859 | return -EIO; | |
12860 | ||
f7784b8e MT |
12861 | return 0; |
12862 | } | |
12863 | ||
a85863c2 MS |
12864 | |
12865 | static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) | |
12866 | { | |
ee661d8e | 12867 | int nr_slots; |
a85863c2 MS |
12868 | |
12869 | if (!kvm_x86_ops.cpu_dirty_log_size) | |
12870 | return; | |
12871 | ||
ee661d8e DM |
12872 | nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging); |
12873 | if ((enable && nr_slots == 1) || !nr_slots) | |
a85863c2 | 12874 | kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); |
a85863c2 MS |
12875 | } |
12876 | ||
88178fd4 | 12877 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b | 12878 | struct kvm_memory_slot *old, |
269e9552 | 12879 | const struct kvm_memory_slot *new, |
3741679b | 12880 | enum kvm_mr_change change) |
88178fd4 | 12881 | { |
77aedf26 SC |
12882 | u32 old_flags = old ? old->flags : 0; |
12883 | u32 new_flags = new ? new->flags : 0; | |
12884 | bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; | |
a85863c2 | 12885 | |
3741679b | 12886 | /* |
a85863c2 MS |
12887 | * Update CPU dirty logging if dirty logging is being toggled. This |
12888 | * applies to all operations. | |
3741679b | 12889 | */ |
77aedf26 | 12890 | if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) |
a85863c2 | 12891 | kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); |
88178fd4 KH |
12892 | |
12893 | /* | |
a85863c2 | 12894 | * Nothing more to do for RO slots (which can't be dirtied and can't be |
b6e16ae5 | 12895 | * made writable) or CREATE/MOVE/DELETE of a slot. |
88178fd4 | 12896 | * |
b6e16ae5 | 12897 | * For a memslot with dirty logging disabled: |
3741679b AY |
12898 | * CREATE: No dirty mappings will already exist. |
12899 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
12900 | * kvm_arch_flush_shadow_memslot() | |
b6e16ae5 SC |
12901 | * |
12902 | * For a memslot with dirty logging enabled: | |
12903 | * CREATE: No shadow pages exist, thus nothing to write-protect | |
12904 | * and no dirty bits to clear. | |
12905 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
12906 | * kvm_arch_flush_shadow_memslot(). | |
3741679b | 12907 | */ |
77aedf26 | 12908 | if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) |
88178fd4 | 12909 | return; |
3741679b AY |
12910 | |
12911 | /* | |
52f46079 SC |
12912 | * READONLY and non-flags changes were filtered out above, and the only |
12913 | * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty | |
12914 | * logging isn't being toggled on or off. | |
88178fd4 | 12915 | */ |
77aedf26 | 12916 | if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) |
52f46079 SC |
12917 | return; |
12918 | ||
b6e16ae5 SC |
12919 | if (!log_dirty_pages) { |
12920 | /* | |
12921 | * Dirty logging tracks sptes in 4k granularity, meaning that | |
12922 | * large sptes have to be split. If live migration succeeds, | |
12923 | * the guest in the source machine will be destroyed and large | |
12924 | * sptes will be created in the destination. However, if the | |
12925 | * guest continues to run in the source machine (for example if | |
12926 | * live migration fails), small sptes will remain around and | |
12927 | * cause bad performance. | |
12928 | * | |
12929 | * Scan sptes if dirty logging has been stopped, dropping those | |
12930 | * which can be collapsed into a single large-page spte. Later | |
12931 | * page faults will create the large-page sptes. | |
12932 | */ | |
3741679b | 12933 | kvm_mmu_zap_collapsible_sptes(kvm, new); |
b6e16ae5 | 12934 | } else { |
89212919 KZ |
12935 | /* |
12936 | * Initially-all-set does not require write protecting any page, | |
12937 | * because they're all assumed to be dirty. | |
12938 | */ | |
12939 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) | |
12940 | return; | |
a1419f8b | 12941 | |
a3fe5dbd DM |
12942 | if (READ_ONCE(eager_page_split)) |
12943 | kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K); | |
12944 | ||
a018eba5 | 12945 | if (kvm_x86_ops.cpu_dirty_log_size) { |
89212919 KZ |
12946 | kvm_mmu_slot_leaf_clear_dirty(kvm, new); |
12947 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); | |
12948 | } else { | |
12949 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); | |
3c9bd400 | 12950 | } |
b64d740e JS |
12951 | |
12952 | /* | |
12953 | * Unconditionally flush the TLBs after enabling dirty logging. | |
12954 | * A flush is almost always going to be necessary (see below), | |
12955 | * and unconditionally flushing allows the helpers to omit | |
12956 | * the subtly complex checks when removing write access. | |
12957 | * | |
12958 | * Do the flush outside of mmu_lock to reduce the amount of | |
12959 | * time mmu_lock is held. Flushing after dropping mmu_lock is | |
12960 | * safe as KVM only needs to guarantee the slot is fully | |
12961 | * write-protected before returning to userspace, i.e. before | |
12962 | * userspace can consume the dirty status. | |
12963 | * | |
12964 | * Flushing outside of mmu_lock requires KVM to be careful when | |
12965 | * making decisions based on writable status of an SPTE, e.g. a | |
12966 | * !writable SPTE doesn't guarantee a CPU can't perform writes. | |
12967 | * | |
12968 | * Specifically, KVM also write-protects guest page tables to | |
12969 | * monitor changes when using shadow paging, and must guarantee | |
12970 | * no CPUs can write to those page before mmu_lock is dropped. | |
12971 | * Because CPUs may have stale TLB entries at this point, a | |
12972 | * !writable SPTE doesn't guarantee CPUs can't perform writes. | |
12973 | * | |
12974 | * KVM also allows making SPTES writable outside of mmu_lock, | |
12975 | * e.g. to allow dirty logging without taking mmu_lock. | |
12976 | * | |
12977 | * To handle these scenarios, KVM uses a separate software-only | |
12978 | * bit (MMU-writable) to track if a SPTE is !writable due to | |
12979 | * a guest page table being write-protected (KVM clears the | |
12980 | * MMU-writable flag when write-protecting for shadow paging). | |
12981 | * | |
12982 | * The use of MMU-writable is also the primary motivation for | |
12983 | * the unconditional flush. Because KVM must guarantee that a | |
12984 | * CPU doesn't contain stale, writable TLB entries for a | |
12985 | * !MMU-writable SPTE, KVM must flush if it encounters any | |
12986 | * MMU-writable SPTE regardless of whether the actual hardware | |
12987 | * writable bit was set. I.e. KVM is almost guaranteed to need | |
12988 | * to flush, while unconditionally flushing allows the "remove | |
12989 | * write access" helpers to ignore MMU-writable entirely. | |
12990 | * | |
12991 | * See is_writable_pte() for more details (the case involving | |
12992 | * access-tracked SPTEs is particularly relevant). | |
12993 | */ | |
619b5072 | 12994 | kvm_flush_remote_tlbs_memslot(kvm, new); |
88178fd4 KH |
12995 | } |
12996 | } | |
12997 | ||
f7784b8e | 12998 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
9d4c197c | 12999 | struct kvm_memory_slot *old, |
f36f3f28 | 13000 | const struct kvm_memory_slot *new, |
8482644a | 13001 | enum kvm_mr_change change) |
f7784b8e | 13002 | { |
b83ab124 YZ |
13003 | if (change == KVM_MR_DELETE) |
13004 | kvm_page_track_delete_slot(kvm, old); | |
13005 | ||
e0c2b633 | 13006 | if (!kvm->arch.n_requested_mmu_pages && |
f5756029 MS |
13007 | (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { |
13008 | unsigned long nr_mmu_pages; | |
13009 | ||
13010 | nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; | |
13011 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); | |
13012 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
13013 | } | |
1c91cad4 | 13014 | |
269e9552 | 13015 | kvm_mmu_slot_apply_flags(kvm, old, new, change); |
21198846 SC |
13016 | |
13017 | /* Free the arrays associated with the old memslot. */ | |
13018 | if (change == KVM_MR_MOVE) | |
e96c81ee | 13019 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 13020 | } |
1d737c8a | 13021 | |
e6c67d8c LA |
13022 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
13023 | { | |
13024 | return (is_guest_mode(vcpu) && | |
5be2226f | 13025 | static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); |
e6c67d8c LA |
13026 | } |
13027 | ||
5d9bc648 PB |
13028 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
13029 | { | |
13030 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
13031 | return true; | |
13032 | ||
bf7f9352 PB |
13033 | if (kvm_apic_has_pending_init_or_sipi(vcpu) && |
13034 | kvm_apic_init_sipi_allowed(vcpu)) | |
5d9bc648 PB |
13035 | return true; |
13036 | ||
13037 | if (vcpu->arch.pv.pv_unhalted) | |
13038 | return true; | |
13039 | ||
7709aba8 | 13040 | if (kvm_is_exception_pending(vcpu)) |
a5f01f8e WL |
13041 | return true; |
13042 | ||
47a66eed Z |
13043 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
13044 | (vcpu->arch.nmi_pending && | |
b3646477 | 13045 | static_call(kvm_x86_nmi_allowed)(vcpu, false))) |
5d9bc648 PB |
13046 | return true; |
13047 | ||
31e83e21 | 13048 | #ifdef CONFIG_KVM_SMM |
47a66eed | 13049 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 13050 | (vcpu->arch.smi_pending && |
b3646477 | 13051 | static_call(kvm_x86_smi_allowed)(vcpu, false))) |
73917739 | 13052 | return true; |
31e83e21 | 13053 | #endif |
73917739 | 13054 | |
73554b29 JM |
13055 | if (kvm_test_request(KVM_REQ_PMI, vcpu)) |
13056 | return true; | |
13057 | ||
5d9bc648 | 13058 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
13059 | (kvm_cpu_has_interrupt(vcpu) || |
13060 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
13061 | return true; |
13062 | ||
1f4b34f8 AS |
13063 | if (kvm_hv_has_stimer_pending(vcpu)) |
13064 | return true; | |
13065 | ||
d2060bd4 | 13066 | if (is_guest_mode(vcpu) && |
5b4ac1a1 PB |
13067 | kvm_x86_ops.nested_ops->has_events && |
13068 | kvm_x86_ops.nested_ops->has_events(vcpu)) | |
d2060bd4 SC |
13069 | return true; |
13070 | ||
7caf9571 DW |
13071 | if (kvm_xen_has_pending_events(vcpu)) |
13072 | return true; | |
13073 | ||
5d9bc648 PB |
13074 | return false; |
13075 | } | |
13076 | ||
1d737c8a ZX |
13077 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
13078 | { | |
5d9bc648 | 13079 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 13080 | } |
5736199a | 13081 | |
10dbdf98 | 13082 | bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) |
17e433b5 | 13083 | { |
ae801e13 SC |
13084 | if (kvm_vcpu_apicv_active(vcpu) && |
13085 | static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) | |
52acd22f WL |
13086 | return true; |
13087 | ||
13088 | return false; | |
13089 | } | |
13090 | ||
17e433b5 WL |
13091 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
13092 | { | |
13093 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
13094 | return true; | |
13095 | ||
13096 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
cf7316d0 | 13097 | #ifdef CONFIG_KVM_SMM |
17e433b5 | 13098 | kvm_test_request(KVM_REQ_SMI, vcpu) || |
cf7316d0 | 13099 | #endif |
17e433b5 WL |
13100 | kvm_test_request(KVM_REQ_EVENT, vcpu)) |
13101 | return true; | |
13102 | ||
10dbdf98 | 13103 | return kvm_arch_dy_has_pending_interrupt(vcpu); |
17e433b5 WL |
13104 | } |
13105 | ||
199b5763 LM |
13106 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
13107 | { | |
b86bb11e WL |
13108 | if (vcpu->arch.guest_state_protected) |
13109 | return true; | |
13110 | ||
547c9192 LX |
13111 | if (vcpu != kvm_get_running_vcpu()) |
13112 | return vcpu->arch.preempted_in_kernel; | |
13113 | ||
13114 | return static_call(kvm_x86_get_cpl)(vcpu) == 0; | |
199b5763 LM |
13115 | } |
13116 | ||
e1bfc245 SC |
13117 | unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) |
13118 | { | |
13119 | return kvm_rip_read(vcpu); | |
13120 | } | |
13121 | ||
b6d33834 | 13122 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 13123 | { |
b6d33834 | 13124 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 13125 | } |
78646121 GN |
13126 | |
13127 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
13128 | { | |
b3646477 | 13129 | return static_call(kvm_x86_interrupt_allowed)(vcpu, false); |
78646121 | 13130 | } |
229456fc | 13131 | |
82b32774 | 13132 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 13133 | { |
7ed9abfe TL |
13134 | /* Can't read the RIP when guest state is protected, just return 0 */ |
13135 | if (vcpu->arch.guest_state_protected) | |
13136 | return 0; | |
13137 | ||
82b32774 NA |
13138 | if (is_64_bit_mode(vcpu)) |
13139 | return kvm_rip_read(vcpu); | |
13140 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
13141 | kvm_rip_read(vcpu)); | |
13142 | } | |
13143 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 13144 | |
82b32774 NA |
13145 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
13146 | { | |
13147 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
13148 | } |
13149 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
13150 | ||
94fe45da JK |
13151 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
13152 | { | |
13153 | unsigned long rflags; | |
13154 | ||
b3646477 | 13155 | rflags = static_call(kvm_x86_get_rflags)(vcpu); |
94fe45da | 13156 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 13157 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
13158 | return rflags; |
13159 | } | |
13160 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
13161 | ||
6addfc42 | 13162 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
13163 | { |
13164 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 13165 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 13166 | rflags |= X86_EFLAGS_TF; |
b3646477 | 13167 | static_call(kvm_x86_set_rflags)(vcpu, rflags); |
6addfc42 PB |
13168 | } |
13169 | ||
13170 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
13171 | { | |
13172 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 13173 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
13174 | } |
13175 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
13176 | ||
af585b92 GN |
13177 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
13178 | { | |
dd03bcaa PX |
13179 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
13180 | ||
af585b92 GN |
13181 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
13182 | } | |
13183 | ||
13184 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
13185 | { | |
dd03bcaa | 13186 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
13187 | } |
13188 | ||
13189 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
13190 | { | |
13191 | u32 key = kvm_async_pf_hash_fn(gfn); | |
13192 | ||
13193 | while (vcpu->arch.apf.gfns[key] != ~0) | |
13194 | key = kvm_async_pf_next_probe(key); | |
13195 | ||
13196 | vcpu->arch.apf.gfns[key] = gfn; | |
13197 | } | |
13198 | ||
13199 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
13200 | { | |
13201 | int i; | |
13202 | u32 key = kvm_async_pf_hash_fn(gfn); | |
13203 | ||
dd03bcaa | 13204 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
13205 | (vcpu->arch.apf.gfns[key] != gfn && |
13206 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
13207 | key = kvm_async_pf_next_probe(key); |
13208 | ||
13209 | return key; | |
13210 | } | |
13211 | ||
13212 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
13213 | { | |
13214 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
13215 | } | |
13216 | ||
13217 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
13218 | { | |
13219 | u32 i, j, k; | |
13220 | ||
13221 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
13222 | |
13223 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
13224 | return; | |
13225 | ||
af585b92 GN |
13226 | while (true) { |
13227 | vcpu->arch.apf.gfns[i] = ~0; | |
13228 | do { | |
13229 | j = kvm_async_pf_next_probe(j); | |
13230 | if (vcpu->arch.apf.gfns[j] == ~0) | |
13231 | return; | |
13232 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
13233 | /* | |
13234 | * k lies cyclically in ]i,j] | |
13235 | * | i.k.j | | |
13236 | * |....j i.k.| or |.k..j i...| | |
13237 | */ | |
13238 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
13239 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
13240 | i = j; | |
13241 | } | |
13242 | } | |
13243 | ||
68fd66f1 | 13244 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 13245 | { |
68fd66f1 VK |
13246 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
13247 | ||
13248 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
13249 | sizeof(reason)); | |
13250 | } | |
13251 | ||
13252 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
13253 | { | |
2635b5c4 | 13254 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 13255 | |
2635b5c4 VK |
13256 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
13257 | &token, offset, sizeof(token)); | |
13258 | } | |
13259 | ||
13260 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
13261 | { | |
13262 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
13263 | u32 val; | |
13264 | ||
13265 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
13266 | &val, offset, sizeof(val))) | |
13267 | return false; | |
13268 | ||
13269 | return !val; | |
7c90705b GN |
13270 | } |
13271 | ||
1dfdb45e PB |
13272 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
13273 | { | |
57cb3bb0 PB |
13274 | |
13275 | if (!kvm_pv_async_pf_enabled(vcpu)) | |
1dfdb45e PB |
13276 | return false; |
13277 | ||
57cb3bb0 PB |
13278 | if (vcpu->arch.apf.send_user_only && |
13279 | static_call(kvm_x86_get_cpl)(vcpu) == 0) | |
1dfdb45e PB |
13280 | return false; |
13281 | ||
57cb3bb0 PB |
13282 | if (is_guest_mode(vcpu)) { |
13283 | /* | |
13284 | * L1 needs to opt into the special #PF vmexits that are | |
13285 | * used to deliver async page faults. | |
13286 | */ | |
13287 | return vcpu->arch.apf.delivery_as_pf_vmexit; | |
13288 | } else { | |
13289 | /* | |
13290 | * Play it safe in case the guest temporarily disables paging. | |
13291 | * The real mode IDT in particular is unlikely to have a #PF | |
13292 | * exception setup. | |
13293 | */ | |
13294 | return is_paging(vcpu); | |
13295 | } | |
1dfdb45e PB |
13296 | } |
13297 | ||
13298 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
13299 | { | |
13300 | if (unlikely(!lapic_in_kernel(vcpu) || | |
13301 | kvm_event_needs_reinjection(vcpu) || | |
7709aba8 | 13302 | kvm_is_exception_pending(vcpu))) |
1dfdb45e PB |
13303 | return false; |
13304 | ||
13305 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
13306 | return false; | |
13307 | ||
13308 | /* | |
13309 | * If interrupts are off we cannot even use an artificial | |
13310 | * halt state. | |
13311 | */ | |
c300ab9f | 13312 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
13313 | } |
13314 | ||
2a18b7e7 | 13315 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
13316 | struct kvm_async_pf *work) |
13317 | { | |
6389ee94 AK |
13318 | struct x86_exception fault; |
13319 | ||
736c291c | 13320 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 13321 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 13322 | |
1dfdb45e | 13323 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 13324 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
13325 | fault.vector = PF_VECTOR; |
13326 | fault.error_code_valid = true; | |
13327 | fault.error_code = 0; | |
13328 | fault.nested_page_fault = false; | |
13329 | fault.address = work->arch.token; | |
adfe20fb | 13330 | fault.async_page_fault = true; |
6389ee94 | 13331 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 13332 | return true; |
1dfdb45e PB |
13333 | } else { |
13334 | /* | |
13335 | * It is not possible to deliver a paravirtualized asynchronous | |
13336 | * page fault, but putting the guest in an artificial halt state | |
13337 | * can be beneficial nevertheless: if an interrupt arrives, we | |
13338 | * can deliver it timely and perhaps the guest will schedule | |
13339 | * another process. When the instruction that triggered a page | |
13340 | * fault is retried, hopefully the page will be ready in the host. | |
13341 | */ | |
13342 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 13343 | return false; |
7c90705b | 13344 | } |
af585b92 GN |
13345 | } |
13346 | ||
13347 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
13348 | struct kvm_async_pf *work) | |
13349 | { | |
2635b5c4 VK |
13350 | struct kvm_lapic_irq irq = { |
13351 | .delivery_mode = APIC_DM_FIXED, | |
13352 | .vector = vcpu->arch.apf.vec | |
13353 | }; | |
6389ee94 | 13354 | |
f2e10669 | 13355 | if (work->wakeup_all) |
7c90705b GN |
13356 | work->arch.token = ~0; /* broadcast wakeup */ |
13357 | else | |
13358 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 13359 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 13360 | |
2a18b7e7 VK |
13361 | if ((work->wakeup_all || work->notpresent_injected) && |
13362 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
13363 | !apf_put_user_ready(vcpu, work->arch.token)) { |
13364 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 13365 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 13366 | } |
2635b5c4 | 13367 | |
e6d53e3b | 13368 | vcpu->arch.apf.halted = false; |
a4fa1635 | 13369 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
13370 | } |
13371 | ||
557a961a VK |
13372 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
13373 | { | |
13374 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
13375 | if (!vcpu->arch.apf.pageready_pending) | |
13376 | kvm_vcpu_kick(vcpu); | |
13377 | } | |
13378 | ||
7c0ade6c | 13379 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 13380 | { |
2635b5c4 | 13381 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
13382 | return true; |
13383 | else | |
2f15d027 | 13384 | return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); |
af585b92 GN |
13385 | } |
13386 | ||
5544eb9b PB |
13387 | void kvm_arch_start_assignment(struct kvm *kvm) |
13388 | { | |
57ab8794 | 13389 | if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) |
e27bc044 | 13390 | static_call_cond(kvm_x86_pi_start_assignment)(kvm); |
5544eb9b PB |
13391 | } |
13392 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
13393 | ||
13394 | void kvm_arch_end_assignment(struct kvm *kvm) | |
13395 | { | |
13396 | atomic_dec(&kvm->arch.assigned_device_count); | |
13397 | } | |
13398 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
13399 | ||
742ab6df | 13400 | bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) |
5544eb9b | 13401 | { |
0f613bfa | 13402 | return raw_atomic_read(&kvm->arch.assigned_device_count); |
5544eb9b PB |
13403 | } |
13404 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
13405 | ||
362ff6dc YZ |
13406 | static void kvm_noncoherent_dma_assignment_start_or_stop(struct kvm *kvm) |
13407 | { | |
13408 | /* | |
13409 | * Non-coherent DMA assignment and de-assignment will affect | |
13410 | * whether KVM honors guest MTRRs and cause changes in memtypes | |
13411 | * in TDP. | |
13412 | * So, pass %true unconditionally to indicate non-coherent DMA was, | |
13413 | * or will be involved, and that zapping SPTEs might be necessary. | |
13414 | */ | |
13415 | if (__kvm_mmu_honors_guest_mtrrs(true)) | |
13416 | kvm_zap_gfn_range(kvm, gpa_to_gfn(0), gpa_to_gfn(~0ULL)); | |
13417 | } | |
13418 | ||
e0f0bbc5 AW |
13419 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
13420 | { | |
362ff6dc YZ |
13421 | if (atomic_inc_return(&kvm->arch.noncoherent_dma_count) == 1) |
13422 | kvm_noncoherent_dma_assignment_start_or_stop(kvm); | |
e0f0bbc5 AW |
13423 | } |
13424 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
13425 | ||
13426 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
13427 | { | |
362ff6dc YZ |
13428 | if (!atomic_dec_return(&kvm->arch.noncoherent_dma_count)) |
13429 | kvm_noncoherent_dma_assignment_start_or_stop(kvm); | |
e0f0bbc5 AW |
13430 | } |
13431 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
13432 | ||
13433 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
13434 | { | |
13435 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
13436 | } | |
13437 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
13438 | ||
14717e20 AW |
13439 | bool kvm_arch_has_irq_bypass(void) |
13440 | { | |
5e1fe4a2 | 13441 | return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP); |
14717e20 AW |
13442 | } |
13443 | ||
87276880 FW |
13444 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
13445 | struct irq_bypass_producer *prod) | |
13446 | { | |
13447 | struct kvm_kernel_irqfd *irqfd = | |
13448 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 13449 | int ret; |
87276880 | 13450 | |
14717e20 | 13451 | irqfd->producer = prod; |
2edd9cb7 | 13452 | kvm_arch_start_assignment(irqfd->kvm); |
e27bc044 | 13453 | ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, |
2edd9cb7 ZL |
13454 | prod->irq, irqfd->gsi, 1); |
13455 | ||
13456 | if (ret) | |
13457 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 13458 | |
2edd9cb7 | 13459 | return ret; |
87276880 FW |
13460 | } |
13461 | ||
13462 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
13463 | struct irq_bypass_producer *prod) | |
13464 | { | |
13465 | int ret; | |
13466 | struct kvm_kernel_irqfd *irqfd = | |
13467 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
13468 | ||
87276880 FW |
13469 | WARN_ON(irqfd->producer != prod); |
13470 | irqfd->producer = NULL; | |
13471 | ||
13472 | /* | |
13473 | * When producer of consumer is unregistered, we change back to | |
13474 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 13475 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
13476 | * int this case doesn't want to receive the interrupts. |
13477 | */ | |
e27bc044 | 13478 | ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
13479 | if (ret) |
13480 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
13481 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
13482 | |
13483 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
13484 | } |
13485 | ||
13486 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
13487 | uint32_t guest_irq, bool set) | |
13488 | { | |
e27bc044 | 13489 | return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set); |
87276880 FW |
13490 | } |
13491 | ||
515a0c79 LM |
13492 | bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, |
13493 | struct kvm_kernel_irq_routing_entry *new) | |
13494 | { | |
13495 | if (new->type != KVM_IRQ_ROUTING_MSI) | |
13496 | return true; | |
13497 | ||
13498 | return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); | |
13499 | } | |
13500 | ||
52004014 FW |
13501 | bool kvm_vector_hashing_enabled(void) |
13502 | { | |
13503 | return vector_hashing; | |
13504 | } | |
52004014 | 13505 | |
2d5ba19b MT |
13506 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
13507 | { | |
13508 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
13509 | } | |
13510 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
13511 | ||
841c2be0 ML |
13512 | |
13513 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 13514 | { |
841c2be0 ML |
13515 | /* |
13516 | * test that setting IA32_SPEC_CTRL to given value | |
13517 | * is allowed by the host processor | |
13518 | */ | |
6441fa61 | 13519 | |
841c2be0 ML |
13520 | u64 saved_value; |
13521 | unsigned long flags; | |
13522 | int ret = 0; | |
6441fa61 | 13523 | |
841c2be0 | 13524 | local_irq_save(flags); |
6441fa61 | 13525 | |
841c2be0 ML |
13526 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
13527 | ret = 1; | |
13528 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
13529 | ret = 1; | |
13530 | else | |
13531 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 13532 | |
841c2be0 | 13533 | local_irq_restore(flags); |
6441fa61 | 13534 | |
841c2be0 | 13535 | return ret; |
6441fa61 | 13536 | } |
841c2be0 | 13537 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 13538 | |
89786147 MG |
13539 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
13540 | { | |
1f5a21ee | 13541 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
89786147 | 13542 | struct x86_exception fault; |
5b22bbe7 | 13543 | u64 access = error_code & |
19cf4b7e | 13544 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); |
89786147 MG |
13545 | |
13546 | if (!(error_code & PFERR_PRESENT_MASK) || | |
6e1d2a3f | 13547 | mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) { |
89786147 MG |
13548 | /* |
13549 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
13550 | * tables probably do not match the TLB. Just proceed | |
13551 | * with the error code that the processor gave. | |
13552 | */ | |
13553 | fault.vector = PF_VECTOR; | |
13554 | fault.error_code_valid = true; | |
13555 | fault.error_code = error_code; | |
13556 | fault.nested_page_fault = false; | |
13557 | fault.address = gva; | |
2bc685e6 | 13558 | fault.async_page_fault = false; |
89786147 MG |
13559 | } |
13560 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 13561 | } |
89786147 | 13562 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 13563 | |
3f3393b3 BM |
13564 | /* |
13565 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
13566 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
13567 | * indicates whether exit to userspace is needed. | |
13568 | */ | |
13569 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
13570 | struct x86_exception *e) | |
13571 | { | |
13572 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
77b1908e SC |
13573 | if (KVM_BUG_ON(!e, vcpu->kvm)) |
13574 | return -EIO; | |
13575 | ||
3f3393b3 BM |
13576 | kvm_inject_emulated_page_fault(vcpu, e); |
13577 | return 1; | |
13578 | } | |
13579 | ||
13580 | /* | |
13581 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
13582 | * while handling a VMX instruction KVM could've handled the request | |
13583 | * correctly by exiting to userspace and performing I/O but there | |
13584 | * doesn't seem to be a real use-case behind such requests, just return | |
13585 | * KVM_EXIT_INTERNAL_ERROR for now. | |
13586 | */ | |
e615e355 | 13587 | kvm_prepare_emulation_failure_exit(vcpu); |
3f3393b3 BM |
13588 | |
13589 | return 0; | |
13590 | } | |
13591 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
13592 | ||
9715092f BM |
13593 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
13594 | { | |
13595 | bool pcid_enabled; | |
13596 | struct x86_exception e; | |
9715092f BM |
13597 | struct { |
13598 | u64 pcid; | |
13599 | u64 gla; | |
13600 | } operand; | |
13601 | int r; | |
13602 | ||
13603 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
13604 | if (r != X86EMUL_CONTINUE) | |
13605 | return kvm_handle_memory_failure(vcpu, r, &e); | |
13606 | ||
13607 | if (operand.pcid >> 12 != 0) { | |
13608 | kvm_inject_gp(vcpu, 0); | |
13609 | return 1; | |
13610 | } | |
13611 | ||
607475cf | 13612 | pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE); |
9715092f BM |
13613 | |
13614 | switch (type) { | |
13615 | case INVPCID_TYPE_INDIV_ADDR: | |
b39bd520 BW |
13616 | /* |
13617 | * LAM doesn't apply to addresses that are inputs to TLB | |
13618 | * invalidation. | |
13619 | */ | |
9715092f BM |
13620 | if ((!pcid_enabled && (operand.pcid != 0)) || |
13621 | is_noncanonical_address(operand.gla, vcpu)) { | |
13622 | kvm_inject_gp(vcpu, 0); | |
13623 | return 1; | |
13624 | } | |
13625 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
13626 | return kvm_skip_emulated_instruction(vcpu); | |
13627 | ||
13628 | case INVPCID_TYPE_SINGLE_CTXT: | |
13629 | if (!pcid_enabled && (operand.pcid != 0)) { | |
13630 | kvm_inject_gp(vcpu, 0); | |
13631 | return 1; | |
13632 | } | |
13633 | ||
21823fbd | 13634 | kvm_invalidate_pcid(vcpu, operand.pcid); |
9715092f BM |
13635 | return kvm_skip_emulated_instruction(vcpu); |
13636 | ||
13637 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
13638 | /* | |
13639 | * Currently, KVM doesn't mark global entries in the shadow | |
13640 | * page tables, so a non-global flush just degenerates to a | |
13641 | * global flush. If needed, we could optimize this later by | |
13642 | * keeping track of global entries in shadow page tables. | |
13643 | */ | |
13644 | ||
13645 | fallthrough; | |
13646 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
28f28d45 | 13647 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
9715092f BM |
13648 | return kvm_skip_emulated_instruction(vcpu); |
13649 | ||
13650 | default: | |
796c83c5 VS |
13651 | kvm_inject_gp(vcpu, 0); |
13652 | return 1; | |
9715092f BM |
13653 | } |
13654 | } | |
13655 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
13656 | ||
8f423a80 TL |
13657 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
13658 | { | |
13659 | struct kvm_run *run = vcpu->run; | |
13660 | struct kvm_mmio_fragment *frag; | |
13661 | unsigned int len; | |
13662 | ||
13663 | BUG_ON(!vcpu->mmio_needed); | |
13664 | ||
13665 | /* Complete previous fragment */ | |
13666 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
13667 | len = min(8u, frag->len); | |
13668 | if (!vcpu->mmio_is_write) | |
13669 | memcpy(frag->data, run->mmio.data, len); | |
13670 | ||
13671 | if (frag->len <= 8) { | |
13672 | /* Switch to the next fragment. */ | |
13673 | frag++; | |
13674 | vcpu->mmio_cur_fragment++; | |
13675 | } else { | |
13676 | /* Go forward to the next mmio piece. */ | |
13677 | frag->data += len; | |
13678 | frag->gpa += len; | |
13679 | frag->len -= len; | |
13680 | } | |
13681 | ||
13682 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
13683 | vcpu->mmio_needed = 0; | |
13684 | ||
13685 | // VMG change, at this point, we're always done | |
13686 | // RIP has already been advanced | |
13687 | return 1; | |
13688 | } | |
13689 | ||
13690 | // More MMIO is needed | |
13691 | run->mmio.phys_addr = frag->gpa; | |
13692 | run->mmio.len = min(8u, frag->len); | |
13693 | run->mmio.is_write = vcpu->mmio_is_write; | |
13694 | if (run->mmio.is_write) | |
13695 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
13696 | run->exit_reason = KVM_EXIT_MMIO; | |
13697 | ||
13698 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
13699 | ||
13700 | return 0; | |
13701 | } | |
13702 | ||
13703 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
13704 | void *data) | |
13705 | { | |
13706 | int handled; | |
13707 | struct kvm_mmio_fragment *frag; | |
13708 | ||
13709 | if (!data) | |
13710 | return -EINVAL; | |
13711 | ||
13712 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
13713 | if (handled == bytes) | |
13714 | return 1; | |
13715 | ||
13716 | bytes -= handled; | |
13717 | gpa += handled; | |
13718 | data += handled; | |
13719 | ||
13720 | /*TODO: Check if need to increment number of frags */ | |
13721 | frag = vcpu->mmio_fragments; | |
13722 | vcpu->mmio_nr_fragments = 1; | |
13723 | frag->len = bytes; | |
13724 | frag->gpa = gpa; | |
13725 | frag->data = data; | |
13726 | ||
13727 | vcpu->mmio_needed = 1; | |
13728 | vcpu->mmio_cur_fragment = 0; | |
13729 | ||
13730 | vcpu->run->mmio.phys_addr = gpa; | |
13731 | vcpu->run->mmio.len = min(8u, frag->len); | |
13732 | vcpu->run->mmio.is_write = 1; | |
13733 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
13734 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
13735 | ||
13736 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
13737 | ||
13738 | return 0; | |
13739 | } | |
13740 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
13741 | ||
13742 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
13743 | void *data) | |
13744 | { | |
13745 | int handled; | |
13746 | struct kvm_mmio_fragment *frag; | |
13747 | ||
13748 | if (!data) | |
13749 | return -EINVAL; | |
13750 | ||
13751 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
13752 | if (handled == bytes) | |
13753 | return 1; | |
13754 | ||
13755 | bytes -= handled; | |
13756 | gpa += handled; | |
13757 | data += handled; | |
13758 | ||
13759 | /*TODO: Check if need to increment number of frags */ | |
13760 | frag = vcpu->mmio_fragments; | |
13761 | vcpu->mmio_nr_fragments = 1; | |
13762 | frag->len = bytes; | |
13763 | frag->gpa = gpa; | |
13764 | frag->data = data; | |
13765 | ||
13766 | vcpu->mmio_needed = 1; | |
13767 | vcpu->mmio_cur_fragment = 0; | |
13768 | ||
13769 | vcpu->run->mmio.phys_addr = gpa; | |
13770 | vcpu->run->mmio.len = min(8u, frag->len); | |
13771 | vcpu->run->mmio.is_write = 0; | |
13772 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
13773 | ||
13774 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
13775 | ||
13776 | return 0; | |
13777 | } | |
13778 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
13779 | ||
db209369 PB |
13780 | static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size) |
13781 | { | |
13782 | vcpu->arch.sev_pio_count -= count; | |
13783 | vcpu->arch.sev_pio_data += count * size; | |
13784 | } | |
13785 | ||
7ed9abfe | 13786 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, |
95e16b47 PB |
13787 | unsigned int port); |
13788 | ||
13789 | static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) | |
7ed9abfe | 13790 | { |
95e16b47 PB |
13791 | int size = vcpu->arch.pio.size; |
13792 | int port = vcpu->arch.pio.port; | |
13793 | ||
13794 | vcpu->arch.pio.count = 0; | |
13795 | if (vcpu->arch.sev_pio_count) | |
13796 | return kvm_sev_es_outs(vcpu, size, port); | |
13797 | return 1; | |
13798 | } | |
13799 | ||
13800 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
13801 | unsigned int port) | |
13802 | { | |
13803 | for (;;) { | |
13804 | unsigned int count = | |
13805 | min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); | |
13806 | int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); | |
13807 | ||
13808 | /* memcpy done already by emulator_pio_out. */ | |
db209369 | 13809 | advance_sev_es_emulated_pio(vcpu, count, size); |
95e16b47 PB |
13810 | if (!ret) |
13811 | break; | |
7ed9abfe | 13812 | |
ea724ea4 | 13813 | /* Emulation done by the kernel. */ |
95e16b47 PB |
13814 | if (!vcpu->arch.sev_pio_count) |
13815 | return 1; | |
ea724ea4 | 13816 | } |
7ed9abfe | 13817 | |
95e16b47 | 13818 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; |
7ed9abfe TL |
13819 | return 0; |
13820 | } | |
13821 | ||
95e16b47 PB |
13822 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, |
13823 | unsigned int port); | |
13824 | ||
4fa4b38d PB |
13825 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
13826 | { | |
0c05e10b | 13827 | unsigned count = vcpu->arch.pio.count; |
95e16b47 PB |
13828 | int size = vcpu->arch.pio.size; |
13829 | int port = vcpu->arch.pio.port; | |
4fa4b38d | 13830 | |
0c05e10b | 13831 | complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); |
db209369 | 13832 | advance_sev_es_emulated_pio(vcpu, count, size); |
95e16b47 PB |
13833 | if (vcpu->arch.sev_pio_count) |
13834 | return kvm_sev_es_ins(vcpu, size, port); | |
4fa4b38d PB |
13835 | return 1; |
13836 | } | |
13837 | ||
7ed9abfe | 13838 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, |
95e16b47 | 13839 | unsigned int port) |
7ed9abfe | 13840 | { |
95e16b47 PB |
13841 | for (;;) { |
13842 | unsigned int count = | |
13843 | min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); | |
f35cee4a | 13844 | if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count)) |
95e16b47 | 13845 | break; |
7ed9abfe | 13846 | |
ea724ea4 | 13847 | /* Emulation done by the kernel. */ |
db209369 | 13848 | advance_sev_es_emulated_pio(vcpu, count, size); |
95e16b47 PB |
13849 | if (!vcpu->arch.sev_pio_count) |
13850 | return 1; | |
7ed9abfe TL |
13851 | } |
13852 | ||
ea724ea4 | 13853 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; |
7ed9abfe TL |
13854 | return 0; |
13855 | } | |
13856 | ||
13857 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
13858 | unsigned int port, void *data, unsigned int count, | |
13859 | int in) | |
13860 | { | |
ea724ea4 | 13861 | vcpu->arch.sev_pio_data = data; |
95e16b47 PB |
13862 | vcpu->arch.sev_pio_count = count; |
13863 | return in ? kvm_sev_es_ins(vcpu, size, port) | |
13864 | : kvm_sev_es_outs(vcpu, size, port); | |
7ed9abfe TL |
13865 | } |
13866 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
13867 | ||
d95df951 | 13868 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 13869 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 13870 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
13871 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
13872 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
13873 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
13874 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
89e54ec5 | 13875 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter); |
d8cabddf | 13876 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 13877 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 13878 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 13879 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 13880 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 13881 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 13882 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 13883 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 13884 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 13885 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 13886 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
13887 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
13888 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 13889 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
9f084f7c | 13890 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath); |
39b6b8c3 | 13891 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell); |
8e819d75 | 13892 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); |
d523ab6b TL |
13893 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
13894 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
13895 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
13896 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); | |
1d0e8480 SC |
13897 | |
13898 | static int __init kvm_x86_init(void) | |
13899 | { | |
13900 | kvm_mmu_x86_module_init(); | |
6f0f2d5e | 13901 | mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible(); |
1d0e8480 SC |
13902 | return 0; |
13903 | } | |
13904 | module_init(kvm_x86_init); | |
13905 | ||
13906 | static void __exit kvm_x86_exit(void) | |
13907 | { | |
13908 | /* | |
13909 | * If module_init() is implemented, module_exit() must also be | |
13910 | * implemented to allow module unload. | |
13911 | */ | |
13912 | } | |
13913 | module_exit(kvm_x86_exit); |