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KVM: MMU: do not free active mmu pages in free_mmu_pages()
[linux-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
043405e1
CO		 40
41#include <asm/uaccess.h>
d825ed0a 42#include <asm/msr.h>
a5f61300 43#include <asm/desc.h>
0bed3b56 44#include <asm/mtrr.h>
043405e1 45
313a3dc7 46#define MAX_IO_MSRS 256
a03490ed
CO		 47#define CR0_RESERVED_BITS \
48 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
49 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
50 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
51#define CR4_RESERVED_BITS \
52 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
53 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
54 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
55 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
56
57#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 58/* EFER defaults:
59 * - enable syscall per default because its emulated by KVM
60 * - enable LME and LMA per default on 64 bit KVM
61 */
62#ifdef CONFIG_X86_64
63static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
64#else
65static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
66#endif
313a3dc7 67
ba1389b7
AK		 68#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
69#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 70
674eea0f
AK		 71static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
72 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 73struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
74 u32 function, u32 index);
674eea0f 75
97896d04 76struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 77EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 78
417bc304 79struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 80 { "pf_fixed", VCPU_STAT(pf_fixed) },
81 { "pf_guest", VCPU_STAT(pf_guest) },
82 { "tlb_flush", VCPU_STAT(tlb_flush) },
83 { "invlpg", VCPU_STAT(invlpg) },
84 { "exits", VCPU_STAT(exits) },
85 { "io_exits", VCPU_STAT(io_exits) },
86 { "mmio_exits", VCPU_STAT(mmio_exits) },
87 { "signal_exits", VCPU_STAT(signal_exits) },
88 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 89 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 90 { "halt_exits", VCPU_STAT(halt_exits) },
91 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 92 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 93 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 94 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 95 { "irq_exits", VCPU_STAT(irq_exits) },
96 { "host_state_reload", VCPU_STAT(host_state_reload) },
97 { "efer_reload", VCPU_STAT(efer_reload) },
98 { "fpu_reload", VCPU_STAT(fpu_reload) },
99 { "insn_emulation", VCPU_STAT(insn_emulation) },
100 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 101 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 102 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 103 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
104 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
105 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
106 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
107 { "mmu_flooded", VM_STAT(mmu_flooded) },
108 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 109 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 110 { "mmu_unsync", VM_STAT(mmu_unsync) },
6cffe8ca 111 { "mmu_unsync_global", VM_STAT(mmu_unsync_global) },
0f74a24c 112 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 113 { "largepages", VM_STAT(lpages) },
417bc304
HB		 114 { NULL }
115};
116
5fb76f9b
CO		 117unsigned long segment_base(u16 selector)
118{
119 struct descriptor_table gdt;
a5f61300 120 struct desc_struct *d;
5fb76f9b
CO		 121 unsigned long table_base;
122 unsigned long v;
123
124 if (selector == 0)
125 return 0;
126
127 asm("sgdt %0" : "=m"(gdt));
128 table_base = gdt.base;
129
130 if (selector & 4) { /* from ldt */
131 u16 ldt_selector;
132
133 asm("sldt %0" : "=g"(ldt_selector));
134 table_base = segment_base(ldt_selector);
135 }
a5f61300
AK		 136 d = (struct desc_struct *)(table_base + (selector & ~7));
137 v = d->base0 | ((unsigned long)d->base1 << 16) |
138 ((unsigned long)d->base2 << 24);
5fb76f9b 139#ifdef CONFIG_X86_64
a5f61300
AK		 140 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
141 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 142#endif
143 return v;
144}
145EXPORT_SYMBOL_GPL(segment_base);
146
6866b83e
CO		 147u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
148{
149 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 150 return vcpu->arch.apic_base;
6866b83e 151 else
ad312c7c 152 return vcpu->arch.apic_base;
6866b83e
CO		 153}
154EXPORT_SYMBOL_GPL(kvm_get_apic_base);
155
156void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
157{
158 /* TODO: reserve bits check */
159 if (irqchip_in_kernel(vcpu->kvm))
160 kvm_lapic_set_base(vcpu, data);
161 else
ad312c7c 162 vcpu->arch.apic_base = data;
6866b83e
CO		 163}
164EXPORT_SYMBOL_GPL(kvm_set_apic_base);
165
298101da
AK		 166void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
167{
ad312c7c
ZX		 168 WARN_ON(vcpu->arch.exception.pending);
169 vcpu->arch.exception.pending = true;
170 vcpu->arch.exception.has_error_code = false;
171 vcpu->arch.exception.nr = nr;
298101da
AK		 172}
173EXPORT_SYMBOL_GPL(kvm_queue_exception);
174
c3c91fee
AK		 175void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
176 u32 error_code)
177{
178 ++vcpu->stat.pf_guest;
d8017474 179
71c4dfaf
JR		 180 if (vcpu->arch.exception.pending) {
181 if (vcpu->arch.exception.nr == PF_VECTOR) {
182 printk(KERN_DEBUG "kvm: inject_page_fault:"
183 " double fault 0x%lx\n", addr);
184 vcpu->arch.exception.nr = DF_VECTOR;
185 vcpu->arch.exception.error_code = 0;
186 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
187 /* triple fault -> shutdown */
188 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
189 }
c3c91fee
AK		 190 return;
191 }
ad312c7c 192 vcpu->arch.cr2 = addr;
c3c91fee
AK		 193 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
194}
195
3419ffc8
SY		 196void kvm_inject_nmi(struct kvm_vcpu *vcpu)
197{
198 vcpu->arch.nmi_pending = 1;
199}
200EXPORT_SYMBOL_GPL(kvm_inject_nmi);
201
298101da
AK		 202void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
203{
ad312c7c
ZX		 204 WARN_ON(vcpu->arch.exception.pending);
205 vcpu->arch.exception.pending = true;
206 vcpu->arch.exception.has_error_code = true;
207 vcpu->arch.exception.nr = nr;
208 vcpu->arch.exception.error_code = error_code;
298101da
AK		 209}
210EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
211
212static void __queue_exception(struct kvm_vcpu *vcpu)
213{
ad312c7c
ZX		 214 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
215 vcpu->arch.exception.has_error_code,
216 vcpu->arch.exception.error_code);
298101da
AK		 217}
218
a03490ed
CO		 219/*
220 * Load the pae pdptrs. Return true is they are all valid.
221 */
222int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
223{
224 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
225 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
226 int i;
227 int ret;
ad312c7c 228 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 229
a03490ed
CO		 230 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
231 offset * sizeof(u64), sizeof(pdpte));
232 if (ret < 0) {
233 ret = 0;
234 goto out;
235 }
236 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
237 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
238 ret = 0;
239 goto out;
240 }
241 }
242 ret = 1;
243
ad312c7c 244 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 245out:
a03490ed
CO		 246
247 return ret;
248}
cc4b6871 249EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 250
d835dfec
AK		 251static bool pdptrs_changed(struct kvm_vcpu *vcpu)
252{
ad312c7c 253 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 254 bool changed = true;
255 int r;
256
257 if (is_long_mode(vcpu) || !is_pae(vcpu))
258 return false;
259
ad312c7c 260 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 261 if (r < 0)
262 goto out;
ad312c7c 263 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 264out:
d835dfec
AK		 265
266 return changed;
267}
268
2d3ad1f4 269void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 270{
271 if (cr0 & CR0_RESERVED_BITS) {
272 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 273 cr0, vcpu->arch.cr0);
c1a5d4f9 274 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 275 return;
276 }
277
278 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
279 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 280 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 281 return;
282 }
283
284 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
285 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
286 "and a clear PE flag\n");
c1a5d4f9 287 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 288 return;
289 }
290
291 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
292#ifdef CONFIG_X86_64
ad312c7c 293 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 294 int cs_db, cs_l;
295
296 if (!is_pae(vcpu)) {
297 printk(KERN_DEBUG "set_cr0: #GP, start paging "
298 "in long mode while PAE is disabled\n");
c1a5d4f9 299 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 300 return;
301 }
302 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
303 if (cs_l) {
304 printk(KERN_DEBUG "set_cr0: #GP, start paging "
305 "in long mode while CS.L == 1\n");
c1a5d4f9 306 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 307 return;
308
309 }
310 } else
311#endif
ad312c7c 312 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 313 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
314 "reserved bits\n");
c1a5d4f9 315 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 316 return;
317 }
318
319 }
320
321 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 322 vcpu->arch.cr0 = cr0;
a03490ed 323
6cffe8ca 324 kvm_mmu_sync_global(vcpu);
a03490ed 325 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 326 return;
327}
2d3ad1f4 328EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 329
2d3ad1f4 330void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 331{
2d3ad1f4 332 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 333 KVMTRACE_1D(LMSW, vcpu,
334 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
335 handler);
a03490ed 336}
2d3ad1f4 337EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 338
2d3ad1f4 339void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 340{
a2edf57f
AK		 341 unsigned long old_cr4 = vcpu->arch.cr4;
342 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
343
a03490ed
CO		 344 if (cr4 & CR4_RESERVED_BITS) {
345 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 346 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 347 return;
348 }
349
350 if (is_long_mode(vcpu)) {
351 if (!(cr4 & X86_CR4_PAE)) {
352 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
353 "in long mode\n");
c1a5d4f9 354 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 355 return;
356 }
a2edf57f
AK		 357 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
358 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 359 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 360 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 361 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 362 return;
363 }
364
365 if (cr4 & X86_CR4_VMXE) {
366 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 367 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 368 return;
369 }
370 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 371 vcpu->arch.cr4 = cr4;
5a41accd 372 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
6cffe8ca 373 kvm_mmu_sync_global(vcpu);
a03490ed 374 kvm_mmu_reset_context(vcpu);
a03490ed 375}
2d3ad1f4 376EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 377
2d3ad1f4 378void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 379{
ad312c7c 380 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 381 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 382 kvm_mmu_flush_tlb(vcpu);
383 return;
384 }
385
a03490ed
CO		 386 if (is_long_mode(vcpu)) {
387 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
388 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 389 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 390 return;
391 }
392 } else {
393 if (is_pae(vcpu)) {
394 if (cr3 & CR3_PAE_RESERVED_BITS) {
395 printk(KERN_DEBUG
396 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 397 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 398 return;
399 }
400 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
401 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
402 "reserved bits\n");
c1a5d4f9 403 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 404 return;
405 }
406 }
407 /*
408 * We don't check reserved bits in nonpae mode, because
409 * this isn't enforced, and VMware depends on this.
410 */
411 }
412
a03490ed
CO		 413 /*
414 * Does the new cr3 value map to physical memory? (Note, we
415 * catch an invalid cr3 even in real-mode, because it would
416 * cause trouble later on when we turn on paging anyway.)
417 *
418 * A real CPU would silently accept an invalid cr3 and would
419 * attempt to use it - with largely undefined (and often hard
420 * to debug) behavior on the guest side.
421 */
422 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 423 kvm_inject_gp(vcpu, 0);
a03490ed 424 else {
ad312c7c
ZX		 425 vcpu->arch.cr3 = cr3;
426 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 427 }
a03490ed 428}
2d3ad1f4 429EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 430
2d3ad1f4 431void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 432{
433 if (cr8 & CR8_RESERVED_BITS) {
434 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 435 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 436 return;
437 }
438 if (irqchip_in_kernel(vcpu->kvm))
439 kvm_lapic_set_tpr(vcpu, cr8);
440 else
ad312c7c 441 vcpu->arch.cr8 = cr8;
a03490ed 442}
2d3ad1f4 443EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 444
2d3ad1f4 445unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 446{
447 if (irqchip_in_kernel(vcpu->kvm))
448 return kvm_lapic_get_cr8(vcpu);
449 else
ad312c7c 450 return vcpu->arch.cr8;
a03490ed 451}
2d3ad1f4 452EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 453
d8017474
AG		 454static inline u32 bit(int bitno)
455{
456 return 1 << (bitno & 31);
457}
458
043405e1
CO		 459/*
460 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
461 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
462 *
463 * This list is modified at module load time to reflect the
464 * capabilities of the host cpu.
465 */
466static u32 msrs_to_save[] = {
467 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
468 MSR_K6_STAR,
469#ifdef CONFIG_X86_64
470 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
471#endif
18068523 472 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 473 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 474};
475
476static unsigned num_msrs_to_save;
477
478static u32 emulated_msrs[] = {
479 MSR_IA32_MISC_ENABLE,
480};
481
15c4a640
CO		 482static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
483{
f2b4b7dd 484 if (efer & efer_reserved_bits) {
15c4a640
CO		 485 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
486 efer);
c1a5d4f9 487 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 488 return;
489 }
490
491 if (is_paging(vcpu)
ad312c7c 492 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 493 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 494 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 495 return;
496 }
497
1b2fd70c
AG		 498 if (efer & EFER_FFXSR) {
499 struct kvm_cpuid_entry2 *feat;
500
501 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
502 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
503 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
504 kvm_inject_gp(vcpu, 0);
505 return;
506 }
507 }
508
d8017474
AG		 509 if (efer & EFER_SVME) {
510 struct kvm_cpuid_entry2 *feat;
511
512 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
513 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
514 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
515 kvm_inject_gp(vcpu, 0);
516 return;
517 }
518 }
519
15c4a640
CO		 520 kvm_x86_ops->set_efer(vcpu, efer);
521
522 efer &= ~EFER_LMA;
ad312c7c 523 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 524
ad312c7c 525 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 526}
527
f2b4b7dd
JR		 528void kvm_enable_efer_bits(u64 mask)
529{
530 efer_reserved_bits &= ~mask;
531}
532EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
533
534
15c4a640
CO		 535/*
536 * Writes msr value into into the appropriate "register".
537 * Returns 0 on success, non-0 otherwise.
538 * Assumes vcpu_load() was already called.
539 */
540int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
541{
542 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
543}
544
313a3dc7
CO		 545/*
546 * Adapt set_msr() to msr_io()'s calling convention
547 */
548static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
549{
550 return kvm_set_msr(vcpu, index, *data);
551}
552
18068523
GOC		 553static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
554{
555 static int version;
50d0a0f9
GH		 556 struct pvclock_wall_clock wc;
557 struct timespec now, sys, boot;
18068523
GOC		 558
559 if (!wall_clock)
560 return;
561
562 version++;
563
18068523
GOC		 564 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
565
50d0a0f9
GH		 566 /*
567 * The guest calculates current wall clock time by adding
568 * system time (updated by kvm_write_guest_time below) to the
569 * wall clock specified here. guest system time equals host
570 * system time for us, thus we must fill in host boot time here.
571 */
572 now = current_kernel_time();
573 ktime_get_ts(&sys);
574 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
575
576 wc.sec = boot.tv_sec;
577 wc.nsec = boot.tv_nsec;
578 wc.version = version;
18068523
GOC		 579
580 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
581
582 version++;
583 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 584}
585
50d0a0f9
GH		 586static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
587{
588 uint32_t quotient, remainder;
589
590 /* Don't try to replace with do_div(), this one calculates
591 * "(dividend << 32) / divisor" */
592 __asm__ ( "divl %4"
593 : "=a" (quotient), "=d" (remainder)
594 : "0" (0), "1" (dividend), "r" (divisor) );
595 return quotient;
596}
597
598static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
599{
600 uint64_t nsecs = 1000000000LL;
601 int32_t shift = 0;
602 uint64_t tps64;
603 uint32_t tps32;
604
605 tps64 = tsc_khz * 1000LL;
606 while (tps64 > nsecs*2) {
607 tps64 >>= 1;
608 shift--;
609 }
610
611 tps32 = (uint32_t)tps64;
612 while (tps32 <= (uint32_t)nsecs) {
613 tps32 <<= 1;
614 shift++;
615 }
616
617 hv_clock->tsc_shift = shift;
618 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
619
620 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 621 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 622 hv_clock->tsc_to_system_mul);
623}
624
c8076604
GH		 625static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
626
18068523
GOC		 627static void kvm_write_guest_time(struct kvm_vcpu *v)
628{
629 struct timespec ts;
630 unsigned long flags;
631 struct kvm_vcpu_arch *vcpu = &v->arch;
632 void *shared_kaddr;
633
634 if ((!vcpu->time_page))
635 return;
636
2dea4c84 637 preempt_disable();
c8076604
GH		 638 if (unlikely(vcpu->hv_clock_tsc_khz != __get_cpu_var(cpu_tsc_khz))) {
639 kvm_set_time_scale(__get_cpu_var(cpu_tsc_khz), &vcpu->hv_clock);
640 vcpu->hv_clock_tsc_khz = __get_cpu_var(cpu_tsc_khz);
50d0a0f9 641 }
2dea4c84 642 preempt_enable();
50d0a0f9 643
18068523
GOC		 644 /* Keep irq disabled to prevent changes to the clock */
645 local_irq_save(flags);
646 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
647 &vcpu->hv_clock.tsc_timestamp);
648 ktime_get_ts(&ts);
649 local_irq_restore(flags);
650
651 /* With all the info we got, fill in the values */
652
653 vcpu->hv_clock.system_time = ts.tv_nsec +
654 (NSEC_PER_SEC * (u64)ts.tv_sec);
655 /*
656 * The interface expects us to write an even number signaling that the
657 * update is finished. Since the guest won't see the intermediate
50d0a0f9 658 * state, we just increase by 2 at the end.
18068523 659 */
50d0a0f9 660 vcpu->hv_clock.version += 2;
18068523
GOC		 661
662 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
663
664 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 665 sizeof(vcpu->hv_clock));
18068523
GOC		 666
667 kunmap_atomic(shared_kaddr, KM_USER0);
668
669 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
670}
671
c8076604
GH		 672static int kvm_request_guest_time_update(struct kvm_vcpu *v)
673{
674 struct kvm_vcpu_arch *vcpu = &v->arch;
675
676 if (!vcpu->time_page)
677 return 0;
678 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
679 return 1;
680}
681
9ba075a6
AK		 682static bool msr_mtrr_valid(unsigned msr)
683{
684 switch (msr) {
685 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
686 case MSR_MTRRfix64K_00000:
687 case MSR_MTRRfix16K_80000:
688 case MSR_MTRRfix16K_A0000:
689 case MSR_MTRRfix4K_C0000:
690 case MSR_MTRRfix4K_C8000:
691 case MSR_MTRRfix4K_D0000:
692 case MSR_MTRRfix4K_D8000:
693 case MSR_MTRRfix4K_E0000:
694 case MSR_MTRRfix4K_E8000:
695 case MSR_MTRRfix4K_F0000:
696 case MSR_MTRRfix4K_F8000:
697 case MSR_MTRRdefType:
698 case MSR_IA32_CR_PAT:
699 return true;
700 case 0x2f8:
701 return true;
702 }
703 return false;
704}
705
706static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
707{
0bed3b56
SY		 708 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
709
9ba075a6
AK		 710 if (!msr_mtrr_valid(msr))
711 return 1;
712
0bed3b56
SY		 713 if (msr == MSR_MTRRdefType) {
714 vcpu->arch.mtrr_state.def_type = data;
715 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
716 } else if (msr == MSR_MTRRfix64K_00000)
717 p[0] = data;
718 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
719 p[1 + msr - MSR_MTRRfix16K_80000] = data;
720 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
721 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
722 else if (msr == MSR_IA32_CR_PAT)
723 vcpu->arch.pat = data;
724 else { /* Variable MTRRs */
725 int idx, is_mtrr_mask;
726 u64 *pt;
727
728 idx = (msr - 0x200) / 2;
729 is_mtrr_mask = msr - 0x200 - 2 * idx;
730 if (!is_mtrr_mask)
731 pt =
732 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
733 else
734 pt =
735 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
736 *pt = data;
737 }
738
739 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 740 return 0;
741}
15c4a640
CO		 742
743int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
744{
745 switch (msr) {
15c4a640
CO		 746 case MSR_EFER:
747 set_efer(vcpu, data);
748 break;
15c4a640
CO		 749 case MSR_IA32_MC0_STATUS:
750 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 751 __func__, data);
15c4a640
CO		 752 break;
753 case MSR_IA32_MCG_STATUS:
754 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 755 __func__, data);
15c4a640 756 break;
c7ac679c
JR		 757 case MSR_IA32_MCG_CTL:
758 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 759 __func__, data);
c7ac679c 760 break;
b5e2fec0
AG		 761 case MSR_IA32_DEBUGCTLMSR:
762 if (!data) {
763 /* We support the non-activated case already */
764 break;
765 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
766 /* Values other than LBR and BTF are vendor-specific,
767 thus reserved and should throw a #GP */
768 return 1;
769 }
770 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
771 __func__, data);
772 break;
15c4a640
CO		 773 case MSR_IA32_UCODE_REV:
774 case MSR_IA32_UCODE_WRITE:
61a6bd67 775 case MSR_VM_HSAVE_PA:
15c4a640 776 break;
9ba075a6
AK		 777 case 0x200 ... 0x2ff:
778 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 779 case MSR_IA32_APICBASE:
780 kvm_set_apic_base(vcpu, data);
781 break;
782 case MSR_IA32_MISC_ENABLE:
ad312c7c 783 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 784 break;
18068523
GOC		 785 case MSR_KVM_WALL_CLOCK:
786 vcpu->kvm->arch.wall_clock = data;
787 kvm_write_wall_clock(vcpu->kvm, data);
788 break;
789 case MSR_KVM_SYSTEM_TIME: {
790 if (vcpu->arch.time_page) {
791 kvm_release_page_dirty(vcpu->arch.time_page);
792 vcpu->arch.time_page = NULL;
793 }
794
795 vcpu->arch.time = data;
796
797 /* we verify if the enable bit is set... */
798 if (!(data & 1))
799 break;
800
801 /* ...but clean it before doing the actual write */
802 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
803
18068523
GOC		 804 vcpu->arch.time_page =
805 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 806
807 if (is_error_page(vcpu->arch.time_page)) {
808 kvm_release_page_clean(vcpu->arch.time_page);
809 vcpu->arch.time_page = NULL;
810 }
811
c8076604 812 kvm_request_guest_time_update(vcpu);
18068523
GOC		 813 break;
814 }
15c4a640 815 default:
565f1fbd 816 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 817 return 1;
818 }
819 return 0;
820}
821EXPORT_SYMBOL_GPL(kvm_set_msr_common);
822
823
824/*
825 * Reads an msr value (of 'msr_index') into 'pdata'.
826 * Returns 0 on success, non-0 otherwise.
827 * Assumes vcpu_load() was already called.
828 */
829int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
830{
831 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
832}
833
9ba075a6
AK		 834static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
835{
0bed3b56
SY		 836 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
837
9ba075a6
AK		 838 if (!msr_mtrr_valid(msr))
839 return 1;
840
0bed3b56
SY		 841 if (msr == MSR_MTRRdefType)
842 *pdata = vcpu->arch.mtrr_state.def_type +
843 (vcpu->arch.mtrr_state.enabled << 10);
844 else if (msr == MSR_MTRRfix64K_00000)
845 *pdata = p[0];
846 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
847 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
848 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
849 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
850 else if (msr == MSR_IA32_CR_PAT)
851 *pdata = vcpu->arch.pat;
852 else { /* Variable MTRRs */
853 int idx, is_mtrr_mask;
854 u64 *pt;
855
856 idx = (msr - 0x200) / 2;
857 is_mtrr_mask = msr - 0x200 - 2 * idx;
858 if (!is_mtrr_mask)
859 pt =
860 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
861 else
862 pt =
863 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
864 *pdata = *pt;
865 }
866
9ba075a6
AK		 867 return 0;
868}
869
15c4a640
CO		 870int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
871{
872 u64 data;
873
874 switch (msr) {
875 case 0xc0010010: /* SYSCFG */
876 case 0xc0010015: /* HWCR */
877 case MSR_IA32_PLATFORM_ID:
878 case MSR_IA32_P5_MC_ADDR:
879 case MSR_IA32_P5_MC_TYPE:
880 case MSR_IA32_MC0_CTL:
881 case MSR_IA32_MCG_STATUS:
882 case MSR_IA32_MCG_CAP:
c7ac679c 883 case MSR_IA32_MCG_CTL:
15c4a640
CO		 884 case MSR_IA32_MC0_MISC:
885 case MSR_IA32_MC0_MISC+4:
886 case MSR_IA32_MC0_MISC+8:
887 case MSR_IA32_MC0_MISC+12:
888 case MSR_IA32_MC0_MISC+16:
a89c1ad2 889 case MSR_IA32_MC0_MISC+20:
15c4a640 890 case MSR_IA32_UCODE_REV:
15c4a640 891 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 892 case MSR_IA32_DEBUGCTLMSR:
893 case MSR_IA32_LASTBRANCHFROMIP:
894 case MSR_IA32_LASTBRANCHTOIP:
895 case MSR_IA32_LASTINTFROMIP:
896 case MSR_IA32_LASTINTTOIP:
61a6bd67 897 case MSR_VM_HSAVE_PA:
15c4a640
CO		 898 data = 0;
899 break;
9ba075a6
AK		 900 case MSR_MTRRcap:
901 data = 0x500 | KVM_NR_VAR_MTRR;
902 break;
903 case 0x200 ... 0x2ff:
904 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 905 case 0xcd: /* fsb frequency */
906 data = 3;
907 break;
908 case MSR_IA32_APICBASE:
909 data = kvm_get_apic_base(vcpu);
910 break;
911 case MSR_IA32_MISC_ENABLE:
ad312c7c 912 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 913 break;
847f0ad8
AG		 914 case MSR_IA32_PERF_STATUS:
915 /* TSC increment by tick */
916 data = 1000ULL;
917 /* CPU multiplier */
918 data |= (((uint64_t)4ULL) << 40);
919 break;
15c4a640 920 case MSR_EFER:
ad312c7c 921 data = vcpu->arch.shadow_efer;
15c4a640 922 break;
18068523
GOC		 923 case MSR_KVM_WALL_CLOCK:
924 data = vcpu->kvm->arch.wall_clock;
925 break;
926 case MSR_KVM_SYSTEM_TIME:
927 data = vcpu->arch.time;
928 break;
15c4a640
CO		 929 default:
930 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
931 return 1;
932 }
933 *pdata = data;
934 return 0;
935}
936EXPORT_SYMBOL_GPL(kvm_get_msr_common);
937
313a3dc7
CO		 938/*
939 * Read or write a bunch of msrs. All parameters are kernel addresses.
940 *
941 * @return number of msrs set successfully.
942 */
943static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
944 struct kvm_msr_entry *entries,
945 int (*do_msr)(struct kvm_vcpu *vcpu,
946 unsigned index, u64 *data))
947{
948 int i;
949
950 vcpu_load(vcpu);
951
3200f405 952 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 953 for (i = 0; i < msrs->nmsrs; ++i)
954 if (do_msr(vcpu, entries[i].index, &entries[i].data))
955 break;
3200f405 956 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 957
958 vcpu_put(vcpu);
959
960 return i;
961}
962
963/*
964 * Read or write a bunch of msrs. Parameters are user addresses.
965 *
966 * @return number of msrs set successfully.
967 */
968static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
969 int (*do_msr)(struct kvm_vcpu *vcpu,
970 unsigned index, u64 *data),
971 int writeback)
972{
973 struct kvm_msrs msrs;
974 struct kvm_msr_entry *entries;
975 int r, n;
976 unsigned size;
977
978 r = -EFAULT;
979 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
980 goto out;
981
982 r = -E2BIG;
983 if (msrs.nmsrs >= MAX_IO_MSRS)
984 goto out;
985
986 r = -ENOMEM;
987 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
988 entries = vmalloc(size);
989 if (!entries)
990 goto out;
991
992 r = -EFAULT;
993 if (copy_from_user(entries, user_msrs->entries, size))
994 goto out_free;
995
996 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
997 if (r < 0)
998 goto out_free;
999
1000 r = -EFAULT;
1001 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1002 goto out_free;
1003
1004 r = n;
1005
1006out_free:
1007 vfree(entries);
1008out:
1009 return r;
1010}
1011
018d00d2
ZX		 1012int kvm_dev_ioctl_check_extension(long ext)
1013{
1014 int r;
1015
1016 switch (ext) {
1017 case KVM_CAP_IRQCHIP:
1018 case KVM_CAP_HLT:
1019 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1020 case KVM_CAP_SET_TSS_ADDR:
07716717 1021 case KVM_CAP_EXT_CPUID:
c8076604 1022 case KVM_CAP_CLOCKSOURCE:
7837699f 1023 case KVM_CAP_PIT:
a28e4f5a 1024 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1025 case KVM_CAP_MP_STATE:
ed848624 1026 case KVM_CAP_SYNC_MMU:
52d939a0 1027 case KVM_CAP_REINJECT_CONTROL:
4925663a 1028 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1029 case KVM_CAP_ASSIGN_DEV_IRQ:
018d00d2
ZX		 1030 r = 1;
1031 break;
542472b5
LV		 1032 case KVM_CAP_COALESCED_MMIO:
1033 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1034 break;
774ead3a
AK		 1035 case KVM_CAP_VAPIC:
1036 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1037 break;
f725230a
AK		 1038 case KVM_CAP_NR_VCPUS:
1039 r = KVM_MAX_VCPUS;
1040 break;
a988b910
AK		 1041 case KVM_CAP_NR_MEMSLOTS:
1042 r = KVM_MEMORY_SLOTS;
1043 break;
2f333bcb
MT		 1044 case KVM_CAP_PV_MMU:
1045 r = !tdp_enabled;
1046 break;
62c476c7 1047 case KVM_CAP_IOMMU:
19de40a8 1048 r = iommu_found();
62c476c7 1049 break;
018d00d2
ZX		 1050 default:
1051 r = 0;
1052 break;
1053 }
1054 return r;
1055
1056}
1057
043405e1
CO		 1058long kvm_arch_dev_ioctl(struct file *filp,
1059 unsigned int ioctl, unsigned long arg)
1060{
1061 void __user *argp = (void __user *)arg;
1062 long r;
1063
1064 switch (ioctl) {
1065 case KVM_GET_MSR_INDEX_LIST: {
1066 struct kvm_msr_list __user *user_msr_list = argp;
1067 struct kvm_msr_list msr_list;
1068 unsigned n;
1069
1070 r = -EFAULT;
1071 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1072 goto out;
1073 n = msr_list.nmsrs;
1074 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1075 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1076 goto out;
1077 r = -E2BIG;
1078 if (n < num_msrs_to_save)
1079 goto out;
1080 r = -EFAULT;
1081 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1082 num_msrs_to_save * sizeof(u32)))
1083 goto out;
1084 if (copy_to_user(user_msr_list->indices
1085 + num_msrs_to_save * sizeof(u32),
1086 &emulated_msrs,
1087 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1088 goto out;
1089 r = 0;
1090 break;
1091 }
674eea0f
AK		 1092 case KVM_GET_SUPPORTED_CPUID: {
1093 struct kvm_cpuid2 __user *cpuid_arg = argp;
1094 struct kvm_cpuid2 cpuid;
1095
1096 r = -EFAULT;
1097 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1098 goto out;
1099 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1100 cpuid_arg->entries);
674eea0f
AK		 1101 if (r)
1102 goto out;
1103
1104 r = -EFAULT;
1105 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1106 goto out;
1107 r = 0;
1108 break;
1109 }
043405e1
CO		 1110 default:
1111 r = -EINVAL;
1112 }
1113out:
1114 return r;
1115}
1116
313a3dc7
CO		 1117void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1118{
1119 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1120 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1121}
1122
1123void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1124{
1125 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1126 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1127}
1128
07716717 1129static int is_efer_nx(void)
313a3dc7 1130{
e286e86e 1131 unsigned long long efer = 0;
313a3dc7 1132
e286e86e 1133 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1134 return efer & EFER_NX;
1135}
1136
1137static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1138{
1139 int i;
1140 struct kvm_cpuid_entry2 *e, *entry;
1141
313a3dc7 1142 entry = NULL;
ad312c7c
ZX		 1143 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1144 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1145 if (e->function == 0x80000001) {
1146 entry = e;
1147 break;
1148 }
1149 }
07716717 1150 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1151 entry->edx &= ~(1 << 20);
1152 printk(KERN_INFO "kvm: guest NX capability removed\n");
1153 }
1154}
1155
07716717 1156/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1157static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1158 struct kvm_cpuid *cpuid,
1159 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1160{
1161 int r, i;
1162 struct kvm_cpuid_entry *cpuid_entries;
1163
1164 r = -E2BIG;
1165 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1166 goto out;
1167 r = -ENOMEM;
1168 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1169 if (!cpuid_entries)
1170 goto out;
1171 r = -EFAULT;
1172 if (copy_from_user(cpuid_entries, entries,
1173 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1174 goto out_free;
1175 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1176 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1177 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1178 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1179 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1180 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1181 vcpu->arch.cpuid_entries[i].index = 0;
1182 vcpu->arch.cpuid_entries[i].flags = 0;
1183 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1184 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1185 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1186 }
1187 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1188 cpuid_fix_nx_cap(vcpu);
1189 r = 0;
1190
1191out_free:
1192 vfree(cpuid_entries);
1193out:
1194 return r;
1195}
1196
1197static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1198 struct kvm_cpuid2 *cpuid,
1199 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1200{
1201 int r;
1202
1203 r = -E2BIG;
1204 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1205 goto out;
1206 r = -EFAULT;
ad312c7c 1207 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1208 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1209 goto out;
ad312c7c 1210 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1211 return 0;
1212
1213out:
1214 return r;
1215}
1216
07716717 1217static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1218 struct kvm_cpuid2 *cpuid,
1219 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1220{
1221 int r;
1222
1223 r = -E2BIG;
ad312c7c 1224 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1225 goto out;
1226 r = -EFAULT;
ad312c7c 1227 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1228 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1229 goto out;
1230 return 0;
1231
1232out:
ad312c7c 1233 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1234 return r;
1235}
1236
07716717 1237static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1238 u32 index)
07716717
DK		 1239{
1240 entry->function = function;
1241 entry->index = index;
1242 cpuid_count(entry->function, entry->index,
19355475 1243 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1244 entry->flags = 0;
1245}
1246
1247static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1248 u32 index, int *nent, int maxnent)
1249{
1250 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1251 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1252 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1253 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1254 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1255 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1256 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1257 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1258 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1259 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1260 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1261 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1262 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1263 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1264 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1265 bit(X86_FEATURE_PGE) |
1266 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1267 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1268 bit(X86_FEATURE_SYSCALL) |
334b8ad7 1269 (is_efer_nx() ? bit(X86_FEATURE_NX) : 0) |
07716717
DK		 1270#ifdef CONFIG_X86_64
1271 bit(X86_FEATURE_LM) |
1272#endif
1b2fd70c 1273 bit(X86_FEATURE_FXSR_OPT) |
07716717
DK		 1274 bit(X86_FEATURE_MMXEXT) |
1275 bit(X86_FEATURE_3DNOWEXT) |
1276 bit(X86_FEATURE_3DNOW);
1277 const u32 kvm_supported_word3_x86_features =
1278 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1279 const u32 kvm_supported_word6_x86_features =
d8017474
AG		 1280 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY) |
1281 bit(X86_FEATURE_SVM);
07716717 1282
19355475 1283 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1284 get_cpu();
1285 do_cpuid_1_ent(entry, function, index);
1286 ++*nent;
1287
1288 switch (function) {
1289 case 0:
1290 entry->eax = min(entry->eax, (u32)0xb);
1291 break;
1292 case 1:
1293 entry->edx &= kvm_supported_word0_x86_features;
1294 entry->ecx &= kvm_supported_word3_x86_features;
1295 break;
1296 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1297 * may return different values. This forces us to get_cpu() before
1298 * issuing the first command, and also to emulate this annoying behavior
1299 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1300 case 2: {
1301 int t, times = entry->eax & 0xff;
1302
1303 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1304 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1305 for (t = 1; t < times && *nent < maxnent; ++t) {
1306 do_cpuid_1_ent(&entry[t], function, 0);
1307 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1308 ++*nent;
1309 }
1310 break;
1311 }
1312 /* function 4 and 0xb have additional index. */
1313 case 4: {
14af3f3c 1314 int i, cache_type;
07716717
DK		 1315
1316 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1317 /* read more entries until cache_type is zero */
14af3f3c
HH		 1318 for (i = 1; *nent < maxnent; ++i) {
1319 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1320 if (!cache_type)
1321 break;
14af3f3c
HH		 1322 do_cpuid_1_ent(&entry[i], function, i);
1323 entry[i].flags |=
07716717
DK		 1324 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1325 ++*nent;
1326 }
1327 break;
1328 }
1329 case 0xb: {
14af3f3c 1330 int i, level_type;
07716717
DK		 1331
1332 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1333 /* read more entries until level_type is zero */
14af3f3c 1334 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1335 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1336 if (!level_type)
1337 break;
14af3f3c
HH		 1338 do_cpuid_1_ent(&entry[i], function, i);
1339 entry[i].flags |=
07716717
DK		 1340 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1341 ++*nent;
1342 }
1343 break;
1344 }
1345 case 0x80000000:
1346 entry->eax = min(entry->eax, 0x8000001a);
1347 break;
1348 case 0x80000001:
1349 entry->edx &= kvm_supported_word1_x86_features;
1350 entry->ecx &= kvm_supported_word6_x86_features;
1351 break;
1352 }
1353 put_cpu();
1354}
1355
674eea0f 1356static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1357 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1358{
1359 struct kvm_cpuid_entry2 *cpuid_entries;
1360 int limit, nent = 0, r = -E2BIG;
1361 u32 func;
1362
1363 if (cpuid->nent < 1)
1364 goto out;
1365 r = -ENOMEM;
1366 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1367 if (!cpuid_entries)
1368 goto out;
1369
1370 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1371 limit = cpuid_entries[0].eax;
1372 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1373 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1374 &nent, cpuid->nent);
07716717
DK		 1375 r = -E2BIG;
1376 if (nent >= cpuid->nent)
1377 goto out_free;
1378
1379 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1380 limit = cpuid_entries[nent - 1].eax;
1381 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1382 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1383 &nent, cpuid->nent);
07716717
DK		 1384 r = -EFAULT;
1385 if (copy_to_user(entries, cpuid_entries,
19355475 1386 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1387 goto out_free;
1388 cpuid->nent = nent;
1389 r = 0;
1390
1391out_free:
1392 vfree(cpuid_entries);
1393out:
1394 return r;
1395}
1396
313a3dc7
CO		 1397static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1398 struct kvm_lapic_state *s)
1399{
1400 vcpu_load(vcpu);
ad312c7c 1401 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1402 vcpu_put(vcpu);
1403
1404 return 0;
1405}
1406
1407static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1408 struct kvm_lapic_state *s)
1409{
1410 vcpu_load(vcpu);
ad312c7c 1411 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1412 kvm_apic_post_state_restore(vcpu);
1413 vcpu_put(vcpu);
1414
1415 return 0;
1416}
1417
f77bc6a4
ZX		 1418static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1419 struct kvm_interrupt *irq)
1420{
1421 if (irq->irq < 0 || irq->irq >= 256)
1422 return -EINVAL;
1423 if (irqchip_in_kernel(vcpu->kvm))
1424 return -ENXIO;
1425 vcpu_load(vcpu);
1426
ad312c7c
ZX		 1427 set_bit(irq->irq, vcpu->arch.irq_pending);
1428 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1429
1430 vcpu_put(vcpu);
1431
1432 return 0;
1433}
1434
c4abb7c9
JK		 1435static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1436{
1437 vcpu_load(vcpu);
1438 kvm_inject_nmi(vcpu);
1439 vcpu_put(vcpu);
1440
1441 return 0;
1442}
1443
b209749f
AK		 1444static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1445 struct kvm_tpr_access_ctl *tac)
1446{
1447 if (tac->flags)
1448 return -EINVAL;
1449 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1450 return 0;
1451}
1452
313a3dc7
CO		 1453long kvm_arch_vcpu_ioctl(struct file *filp,
1454 unsigned int ioctl, unsigned long arg)
1455{
1456 struct kvm_vcpu *vcpu = filp->private_data;
1457 void __user *argp = (void __user *)arg;
1458 int r;
b772ff36 1459 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1460
1461 switch (ioctl) {
1462 case KVM_GET_LAPIC: {
b772ff36 1463 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1464
b772ff36
DH		 1465 r = -ENOMEM;
1466 if (!lapic)
1467 goto out;
1468 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1469 if (r)
1470 goto out;
1471 r = -EFAULT;
b772ff36 1472 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1473 goto out;
1474 r = 0;
1475 break;
1476 }
1477 case KVM_SET_LAPIC: {
b772ff36
DH		 1478 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1479 r = -ENOMEM;
1480 if (!lapic)
1481 goto out;
313a3dc7 1482 r = -EFAULT;
b772ff36 1483 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1484 goto out;
b772ff36 1485 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1486 if (r)
1487 goto out;
1488 r = 0;
1489 break;
1490 }
f77bc6a4
ZX		 1491 case KVM_INTERRUPT: {
1492 struct kvm_interrupt irq;
1493
1494 r = -EFAULT;
1495 if (copy_from_user(&irq, argp, sizeof irq))
1496 goto out;
1497 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1498 if (r)
1499 goto out;
1500 r = 0;
1501 break;
1502 }
c4abb7c9
JK		 1503 case KVM_NMI: {
1504 r = kvm_vcpu_ioctl_nmi(vcpu);
1505 if (r)
1506 goto out;
1507 r = 0;
1508 break;
1509 }
313a3dc7
CO		 1510 case KVM_SET_CPUID: {
1511 struct kvm_cpuid __user *cpuid_arg = argp;
1512 struct kvm_cpuid cpuid;
1513
1514 r = -EFAULT;
1515 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1516 goto out;
1517 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1518 if (r)
1519 goto out;
1520 break;
1521 }
07716717
DK		 1522 case KVM_SET_CPUID2: {
1523 struct kvm_cpuid2 __user *cpuid_arg = argp;
1524 struct kvm_cpuid2 cpuid;
1525
1526 r = -EFAULT;
1527 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1528 goto out;
1529 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1530 cpuid_arg->entries);
07716717
DK		 1531 if (r)
1532 goto out;
1533 break;
1534 }
1535 case KVM_GET_CPUID2: {
1536 struct kvm_cpuid2 __user *cpuid_arg = argp;
1537 struct kvm_cpuid2 cpuid;
1538
1539 r = -EFAULT;
1540 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1541 goto out;
1542 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1543 cpuid_arg->entries);
07716717
DK		 1544 if (r)
1545 goto out;
1546 r = -EFAULT;
1547 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1548 goto out;
1549 r = 0;
1550 break;
1551 }
313a3dc7
CO		 1552 case KVM_GET_MSRS:
1553 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1554 break;
1555 case KVM_SET_MSRS:
1556 r = msr_io(vcpu, argp, do_set_msr, 0);
1557 break;
b209749f
AK		 1558 case KVM_TPR_ACCESS_REPORTING: {
1559 struct kvm_tpr_access_ctl tac;
1560
1561 r = -EFAULT;
1562 if (copy_from_user(&tac, argp, sizeof tac))
1563 goto out;
1564 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1565 if (r)
1566 goto out;
1567 r = -EFAULT;
1568 if (copy_to_user(argp, &tac, sizeof tac))
1569 goto out;
1570 r = 0;
1571 break;
1572 };
b93463aa
AK		 1573 case KVM_SET_VAPIC_ADDR: {
1574 struct kvm_vapic_addr va;
1575
1576 r = -EINVAL;
1577 if (!irqchip_in_kernel(vcpu->kvm))
1578 goto out;
1579 r = -EFAULT;
1580 if (copy_from_user(&va, argp, sizeof va))
1581 goto out;
1582 r = 0;
1583 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1584 break;
1585 }
313a3dc7
CO		 1586 default:
1587 r = -EINVAL;
1588 }
1589out:
b772ff36
DH		 1590 if (lapic)
1591 kfree(lapic);
313a3dc7
CO		 1592 return r;
1593}
1594
1fe779f8
CO		 1595static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1596{
1597 int ret;
1598
1599 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1600 return -1;
1601 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1602 return ret;
1603}
1604
1605static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1606 u32 kvm_nr_mmu_pages)
1607{
1608 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1609 return -EINVAL;
1610
72dc67a6 1611 down_write(&kvm->slots_lock);
1fe779f8
CO		 1612
1613 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1614 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1615
72dc67a6 1616 up_write(&kvm->slots_lock);
1fe779f8
CO		 1617 return 0;
1618}
1619
1620static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1621{
f05e70ac 1622 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1623}
1624
e9f85cde
ZX		 1625gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1626{
1627 int i;
1628 struct kvm_mem_alias *alias;
1629
d69fb81f
ZX		 1630 for (i = 0; i < kvm->arch.naliases; ++i) {
1631 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1632 if (gfn >= alias->base_gfn
1633 && gfn < alias->base_gfn + alias->npages)
1634 return alias->target_gfn + gfn - alias->base_gfn;
1635 }
1636 return gfn;
1637}
1638
1fe779f8
CO		 1639/*
1640 * Set a new alias region. Aliases map a portion of physical memory into
1641 * another portion. This is useful for memory windows, for example the PC
1642 * VGA region.
1643 */
1644static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1645 struct kvm_memory_alias *alias)
1646{
1647 int r, n;
1648 struct kvm_mem_alias *p;
1649
1650 r = -EINVAL;
1651 /* General sanity checks */
1652 if (alias->memory_size & (PAGE_SIZE - 1))
1653 goto out;
1654 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1655 goto out;
1656 if (alias->slot >= KVM_ALIAS_SLOTS)
1657 goto out;
1658 if (alias->guest_phys_addr + alias->memory_size
1659 < alias->guest_phys_addr)
1660 goto out;
1661 if (alias->target_phys_addr + alias->memory_size
1662 < alias->target_phys_addr)
1663 goto out;
1664
72dc67a6 1665 down_write(&kvm->slots_lock);
a1708ce8 1666 spin_lock(&kvm->mmu_lock);
1fe779f8 1667
d69fb81f 1668 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1669 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1670 p->npages = alias->memory_size >> PAGE_SHIFT;
1671 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1672
1673 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1674 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1675 break;
d69fb81f 1676 kvm->arch.naliases = n;
1fe779f8 1677
a1708ce8 1678 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1679 kvm_mmu_zap_all(kvm);
1680
72dc67a6 1681 up_write(&kvm->slots_lock);
1fe779f8
CO		 1682
1683 return 0;
1684
1685out:
1686 return r;
1687}
1688
1689static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1690{
1691 int r;
1692
1693 r = 0;
1694 switch (chip->chip_id) {
1695 case KVM_IRQCHIP_PIC_MASTER:
1696 memcpy(&chip->chip.pic,
1697 &pic_irqchip(kvm)->pics[0],
1698 sizeof(struct kvm_pic_state));
1699 break;
1700 case KVM_IRQCHIP_PIC_SLAVE:
1701 memcpy(&chip->chip.pic,
1702 &pic_irqchip(kvm)->pics[1],
1703 sizeof(struct kvm_pic_state));
1704 break;
1705 case KVM_IRQCHIP_IOAPIC:
1706 memcpy(&chip->chip.ioapic,
1707 ioapic_irqchip(kvm),
1708 sizeof(struct kvm_ioapic_state));
1709 break;
1710 default:
1711 r = -EINVAL;
1712 break;
1713 }
1714 return r;
1715}
1716
1717static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1718{
1719 int r;
1720
1721 r = 0;
1722 switch (chip->chip_id) {
1723 case KVM_IRQCHIP_PIC_MASTER:
1724 memcpy(&pic_irqchip(kvm)->pics[0],
1725 &chip->chip.pic,
1726 sizeof(struct kvm_pic_state));
1727 break;
1728 case KVM_IRQCHIP_PIC_SLAVE:
1729 memcpy(&pic_irqchip(kvm)->pics[1],
1730 &chip->chip.pic,
1731 sizeof(struct kvm_pic_state));
1732 break;
1733 case KVM_IRQCHIP_IOAPIC:
1734 memcpy(ioapic_irqchip(kvm),
1735 &chip->chip.ioapic,
1736 sizeof(struct kvm_ioapic_state));
1737 break;
1738 default:
1739 r = -EINVAL;
1740 break;
1741 }
1742 kvm_pic_update_irq(pic_irqchip(kvm));
1743 return r;
1744}
1745
e0f63cb9
SY		 1746static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1747{
1748 int r = 0;
1749
1750 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1751 return r;
1752}
1753
1754static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1755{
1756 int r = 0;
1757
1758 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1759 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1760 return r;
1761}
1762
52d939a0
MT		 1763static int kvm_vm_ioctl_reinject(struct kvm *kvm,
1764 struct kvm_reinject_control *control)
1765{
1766 if (!kvm->arch.vpit)
1767 return -ENXIO;
1768 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
1769 return 0;
1770}
1771
5bb064dc
ZX		 1772/*
1773 * Get (and clear) the dirty memory log for a memory slot.
1774 */
1775int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1776 struct kvm_dirty_log *log)
1777{
1778 int r;
1779 int n;
1780 struct kvm_memory_slot *memslot;
1781 int is_dirty = 0;
1782
72dc67a6 1783 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1784
1785 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1786 if (r)
1787 goto out;
1788
1789 /* If nothing is dirty, don't bother messing with page tables. */
1790 if (is_dirty) {
1791 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1792 kvm_flush_remote_tlbs(kvm);
1793 memslot = &kvm->memslots[log->slot];
1794 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1795 memset(memslot->dirty_bitmap, 0, n);
1796 }
1797 r = 0;
1798out:
72dc67a6 1799 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1800 return r;
1801}
1802
1fe779f8
CO		 1803long kvm_arch_vm_ioctl(struct file *filp,
1804 unsigned int ioctl, unsigned long arg)
1805{
1806 struct kvm *kvm = filp->private_data;
1807 void __user *argp = (void __user *)arg;
1808 int r = -EINVAL;
f0d66275
DH		 1809 /*
1810 * This union makes it completely explicit to gcc-3.x
1811 * that these two variables' stack usage should be
1812 * combined, not added together.
1813 */
1814 union {
1815 struct kvm_pit_state ps;
1816 struct kvm_memory_alias alias;
1817 } u;
1fe779f8
CO		 1818
1819 switch (ioctl) {
1820 case KVM_SET_TSS_ADDR:
1821 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1822 if (r < 0)
1823 goto out;
1824 break;
1825 case KVM_SET_MEMORY_REGION: {
1826 struct kvm_memory_region kvm_mem;
1827 struct kvm_userspace_memory_region kvm_userspace_mem;
1828
1829 r = -EFAULT;
1830 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1831 goto out;
1832 kvm_userspace_mem.slot = kvm_mem.slot;
1833 kvm_userspace_mem.flags = kvm_mem.flags;
1834 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1835 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1836 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1837 if (r)
1838 goto out;
1839 break;
1840 }
1841 case KVM_SET_NR_MMU_PAGES:
1842 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1843 if (r)
1844 goto out;
1845 break;
1846 case KVM_GET_NR_MMU_PAGES:
1847 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1848 break;
f0d66275 1849 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1850 r = -EFAULT;
f0d66275 1851 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1852 goto out;
f0d66275 1853 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1854 if (r)
1855 goto out;
1856 break;
1fe779f8
CO		 1857 case KVM_CREATE_IRQCHIP:
1858 r = -ENOMEM;
d7deeeb0
ZX		 1859 kvm->arch.vpic = kvm_create_pic(kvm);
1860 if (kvm->arch.vpic) {
1fe779f8
CO		 1861 r = kvm_ioapic_init(kvm);
1862 if (r) {
d7deeeb0
ZX		 1863 kfree(kvm->arch.vpic);
1864 kvm->arch.vpic = NULL;
1fe779f8
CO		 1865 goto out;
1866 }
1867 } else
1868 goto out;
399ec807
AK		 1869 r = kvm_setup_default_irq_routing(kvm);
1870 if (r) {
1871 kfree(kvm->arch.vpic);
1872 kfree(kvm->arch.vioapic);
1873 goto out;
1874 }
1fe779f8 1875 break;
7837699f 1876 case KVM_CREATE_PIT:
269e05e4
AK		 1877 mutex_lock(&kvm->lock);
1878 r = -EEXIST;
1879 if (kvm->arch.vpit)
1880 goto create_pit_unlock;
7837699f
SY		 1881 r = -ENOMEM;
1882 kvm->arch.vpit = kvm_create_pit(kvm);
1883 if (kvm->arch.vpit)
1884 r = 0;
269e05e4
AK		 1885 create_pit_unlock:
1886 mutex_unlock(&kvm->lock);
7837699f 1887 break;
4925663a 1888 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 1889 case KVM_IRQ_LINE: {
1890 struct kvm_irq_level irq_event;
1891
1892 r = -EFAULT;
1893 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1894 goto out;
1895 if (irqchip_in_kernel(kvm)) {
4925663a 1896 __s32 status;
1fe779f8 1897 mutex_lock(&kvm->lock);
4925663a
GN		 1898 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1899 irq_event.irq, irq_event.level);
1fe779f8 1900 mutex_unlock(&kvm->lock);
4925663a
GN		 1901 if (ioctl == KVM_IRQ_LINE_STATUS) {
1902 irq_event.status = status;
1903 if (copy_to_user(argp, &irq_event,
1904 sizeof irq_event))
1905 goto out;
1906 }
1fe779f8
CO		 1907 r = 0;
1908 }
1909 break;
1910 }
1911 case KVM_GET_IRQCHIP: {
1912 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1913 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1914
f0d66275
DH		 1915 r = -ENOMEM;
1916 if (!chip)
1fe779f8 1917 goto out;
f0d66275
DH		 1918 r = -EFAULT;
1919 if (copy_from_user(chip, argp, sizeof *chip))
1920 goto get_irqchip_out;
1fe779f8
CO		 1921 r = -ENXIO;
1922 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1923 goto get_irqchip_out;
1924 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1925 if (r)
f0d66275 1926 goto get_irqchip_out;
1fe779f8 1927 r = -EFAULT;
f0d66275
DH		 1928 if (copy_to_user(argp, chip, sizeof *chip))
1929 goto get_irqchip_out;
1fe779f8 1930 r = 0;
f0d66275
DH		 1931 get_irqchip_out:
1932 kfree(chip);
1933 if (r)
1934 goto out;
1fe779f8
CO		 1935 break;
1936 }
1937 case KVM_SET_IRQCHIP: {
1938 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1939 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1940
f0d66275
DH		 1941 r = -ENOMEM;
1942 if (!chip)
1fe779f8 1943 goto out;
f0d66275
DH		 1944 r = -EFAULT;
1945 if (copy_from_user(chip, argp, sizeof *chip))
1946 goto set_irqchip_out;
1fe779f8
CO		 1947 r = -ENXIO;
1948 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1949 goto set_irqchip_out;
1950 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1951 if (r)
f0d66275 1952 goto set_irqchip_out;
1fe779f8 1953 r = 0;
f0d66275
DH		 1954 set_irqchip_out:
1955 kfree(chip);
1956 if (r)
1957 goto out;
1fe779f8
CO		 1958 break;
1959 }
e0f63cb9 1960 case KVM_GET_PIT: {
e0f63cb9 1961 r = -EFAULT;
f0d66275 1962 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1963 goto out;
1964 r = -ENXIO;
1965 if (!kvm->arch.vpit)
1966 goto out;
f0d66275 1967 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1968 if (r)
1969 goto out;
1970 r = -EFAULT;
f0d66275 1971 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1972 goto out;
1973 r = 0;
1974 break;
1975 }
1976 case KVM_SET_PIT: {
e0f63cb9 1977 r = -EFAULT;
f0d66275 1978 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1979 goto out;
1980 r = -ENXIO;
1981 if (!kvm->arch.vpit)
1982 goto out;
f0d66275 1983 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1984 if (r)
1985 goto out;
1986 r = 0;
1987 break;
1988 }
52d939a0
MT		 1989 case KVM_REINJECT_CONTROL: {
1990 struct kvm_reinject_control control;
1991 r = -EFAULT;
1992 if (copy_from_user(&control, argp, sizeof(control)))
1993 goto out;
1994 r = kvm_vm_ioctl_reinject(kvm, &control);
1995 if (r)
1996 goto out;
1997 r = 0;
1998 break;
1999 }
1fe779f8
CO		 2000 default:
2001 ;
2002 }
2003out:
2004 return r;
2005}
2006
a16b043c 2007static void kvm_init_msr_list(void)
043405e1
CO		 2008{
2009 u32 dummy[2];
2010 unsigned i, j;
2011
2012 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2013 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2014 continue;
2015 if (j < i)
2016 msrs_to_save[j] = msrs_to_save[i];
2017 j++;
2018 }
2019 num_msrs_to_save = j;
2020}
2021
bbd9b64e
CO		 2022/*
2023 * Only apic need an MMIO device hook, so shortcut now..
2024 */
2025static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2026 gpa_t addr, int len,
2027 int is_write)
bbd9b64e
CO		 2028{
2029 struct kvm_io_device *dev;
2030
ad312c7c
ZX		 2031 if (vcpu->arch.apic) {
2032 dev = &vcpu->arch.apic->dev;
92760499 2033 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2034 return dev;
2035 }
2036 return NULL;
2037}
2038
2039
2040static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2041 gpa_t addr, int len,
2042 int is_write)
bbd9b64e
CO		 2043{
2044 struct kvm_io_device *dev;
2045
92760499 2046 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2047 if (dev == NULL)
92760499
LV		 2048 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2049 is_write);
bbd9b64e
CO		 2050 return dev;
2051}
2052
cded19f3
HE		 2053static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2054 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2055{
2056 void *data = val;
10589a46 2057 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2058
2059 while (bytes) {
ad312c7c 2060 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2061 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2062 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2063 int ret;
2064
10589a46
MT		 2065 if (gpa == UNMAPPED_GVA) {
2066 r = X86EMUL_PROPAGATE_FAULT;
2067 goto out;
2068 }
77c2002e 2069 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2070 if (ret < 0) {
2071 r = X86EMUL_UNHANDLEABLE;
2072 goto out;
2073 }
bbd9b64e 2074
77c2002e
IE		 2075 bytes -= toread;
2076 data += toread;
2077 addr += toread;
bbd9b64e 2078 }
10589a46 2079out:
10589a46 2080 return r;
bbd9b64e 2081}
77c2002e 2082
cded19f3
HE		 2083static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2084 struct kvm_vcpu *vcpu)
77c2002e
IE		 2085{
2086 void *data = val;
2087 int r = X86EMUL_CONTINUE;
2088
2089 while (bytes) {
2090 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2091 unsigned offset = addr & (PAGE_SIZE-1);
2092 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2093 int ret;
2094
2095 if (gpa == UNMAPPED_GVA) {
2096 r = X86EMUL_PROPAGATE_FAULT;
2097 goto out;
2098 }
2099 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2100 if (ret < 0) {
2101 r = X86EMUL_UNHANDLEABLE;
2102 goto out;
2103 }
2104
2105 bytes -= towrite;
2106 data += towrite;
2107 addr += towrite;
2108 }
2109out:
2110 return r;
2111}
2112
bbd9b64e 2113
bbd9b64e
CO		 2114static int emulator_read_emulated(unsigned long addr,
2115 void *val,
2116 unsigned int bytes,
2117 struct kvm_vcpu *vcpu)
2118{
2119 struct kvm_io_device *mmio_dev;
2120 gpa_t gpa;
2121
2122 if (vcpu->mmio_read_completed) {
2123 memcpy(val, vcpu->mmio_data, bytes);
2124 vcpu->mmio_read_completed = 0;
2125 return X86EMUL_CONTINUE;
2126 }
2127
ad312c7c 2128 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2129
2130 /* For APIC access vmexit */
2131 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2132 goto mmio;
2133
77c2002e
IE		 2134 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2135 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2136 return X86EMUL_CONTINUE;
2137 if (gpa == UNMAPPED_GVA)
2138 return X86EMUL_PROPAGATE_FAULT;
2139
2140mmio:
2141 /*
2142 * Is this MMIO handled locally?
2143 */
10589a46 2144 mutex_lock(&vcpu->kvm->lock);
92760499 2145 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2146 if (mmio_dev) {
2147 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2148 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2149 return X86EMUL_CONTINUE;
2150 }
10589a46 2151 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2152
2153 vcpu->mmio_needed = 1;
2154 vcpu->mmio_phys_addr = gpa;
2155 vcpu->mmio_size = bytes;
2156 vcpu->mmio_is_write = 0;
2157
2158 return X86EMUL_UNHANDLEABLE;
2159}
2160
3200f405 2161int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2162 const void *val, int bytes)
bbd9b64e
CO		 2163{
2164 int ret;
2165
2166 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2167 if (ret < 0)
bbd9b64e 2168 return 0;
ad218f85 2169 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2170 return 1;
2171}
2172
2173static int emulator_write_emulated_onepage(unsigned long addr,
2174 const void *val,
2175 unsigned int bytes,
2176 struct kvm_vcpu *vcpu)
2177{
2178 struct kvm_io_device *mmio_dev;
10589a46
MT		 2179 gpa_t gpa;
2180
10589a46 2181 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2182
2183 if (gpa == UNMAPPED_GVA) {
c3c91fee 2184 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2185 return X86EMUL_PROPAGATE_FAULT;
2186 }
2187
2188 /* For APIC access vmexit */
2189 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2190 goto mmio;
2191
2192 if (emulator_write_phys(vcpu, gpa, val, bytes))
2193 return X86EMUL_CONTINUE;
2194
2195mmio:
2196 /*
2197 * Is this MMIO handled locally?
2198 */
10589a46 2199 mutex_lock(&vcpu->kvm->lock);
92760499 2200 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2201 if (mmio_dev) {
2202 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2203 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2204 return X86EMUL_CONTINUE;
2205 }
10589a46 2206 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2207
2208 vcpu->mmio_needed = 1;
2209 vcpu->mmio_phys_addr = gpa;
2210 vcpu->mmio_size = bytes;
2211 vcpu->mmio_is_write = 1;
2212 memcpy(vcpu->mmio_data, val, bytes);
2213
2214 return X86EMUL_CONTINUE;
2215}
2216
2217int emulator_write_emulated(unsigned long addr,
2218 const void *val,
2219 unsigned int bytes,
2220 struct kvm_vcpu *vcpu)
2221{
2222 /* Crossing a page boundary? */
2223 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2224 int rc, now;
2225
2226 now = -addr & ~PAGE_MASK;
2227 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2228 if (rc != X86EMUL_CONTINUE)
2229 return rc;
2230 addr += now;
2231 val += now;
2232 bytes -= now;
2233 }
2234 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2235}
2236EXPORT_SYMBOL_GPL(emulator_write_emulated);
2237
2238static int emulator_cmpxchg_emulated(unsigned long addr,
2239 const void *old,
2240 const void *new,
2241 unsigned int bytes,
2242 struct kvm_vcpu *vcpu)
2243{
2244 static int reported;
2245
2246 if (!reported) {
2247 reported = 1;
2248 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2249 }
2bacc55c
MT		 2250#ifndef CONFIG_X86_64
2251 /* guests cmpxchg8b have to be emulated atomically */
2252 if (bytes == 8) {
10589a46 2253 gpa_t gpa;
2bacc55c 2254 struct page *page;
c0b49b0d 2255 char *kaddr;
2bacc55c
MT		 2256 u64 val;
2257
10589a46
MT		 2258 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2259
2bacc55c
MT		 2260 if (gpa == UNMAPPED_GVA ||
2261 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2262 goto emul_write;
2263
2264 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2265 goto emul_write;
2266
2267 val = *(u64 *)new;
72dc67a6 2268
2bacc55c 2269 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2270
c0b49b0d
AM		 2271 kaddr = kmap_atomic(page, KM_USER0);
2272 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2273 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2274 kvm_release_page_dirty(page);
2275 }
3200f405 2276emul_write:
2bacc55c
MT		 2277#endif
2278
bbd9b64e
CO		 2279 return emulator_write_emulated(addr, new, bytes, vcpu);
2280}
2281
2282static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2283{
2284 return kvm_x86_ops->get_segment_base(vcpu, seg);
2285}
2286
2287int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2288{
a7052897 2289 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2290 return X86EMUL_CONTINUE;
2291}
2292
2293int emulate_clts(struct kvm_vcpu *vcpu)
2294{
54e445ca 2295 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2296 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2297 return X86EMUL_CONTINUE;
2298}
2299
2300int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2301{
2302 struct kvm_vcpu *vcpu = ctxt->vcpu;
2303
2304 switch (dr) {
2305 case 0 ... 3:
2306 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2307 return X86EMUL_CONTINUE;
2308 default:
b8688d51 2309 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2310 return X86EMUL_UNHANDLEABLE;
2311 }
2312}
2313
2314int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2315{
2316 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2317 int exception;
2318
2319 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2320 if (exception) {
2321 /* FIXME: better handling */
2322 return X86EMUL_UNHANDLEABLE;
2323 }
2324 return X86EMUL_CONTINUE;
2325}
2326
2327void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2328{
bbd9b64e 2329 u8 opcodes[4];
5fdbf976 2330 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2331 unsigned long rip_linear;
2332
f76c710d 2333 if (!printk_ratelimit())
bbd9b64e
CO		 2334 return;
2335
25be4608
GC		 2336 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2337
77c2002e 2338 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2339
2340 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2341 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2342}
2343EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2344
14af3f3c 2345static struct x86_emulate_ops emulate_ops = {
77c2002e 2346 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2347 .read_emulated = emulator_read_emulated,
2348 .write_emulated = emulator_write_emulated,
2349 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2350};
2351
5fdbf976
MT		 2352static void cache_all_regs(struct kvm_vcpu *vcpu)
2353{
2354 kvm_register_read(vcpu, VCPU_REGS_RAX);
2355 kvm_register_read(vcpu, VCPU_REGS_RSP);
2356 kvm_register_read(vcpu, VCPU_REGS_RIP);
2357 vcpu->arch.regs_dirty = ~0;
2358}
2359
bbd9b64e
CO		 2360int emulate_instruction(struct kvm_vcpu *vcpu,
2361 struct kvm_run *run,
2362 unsigned long cr2,
2363 u16 error_code,
571008da 2364 int emulation_type)
bbd9b64e
CO		 2365{
2366 int r;
571008da 2367 struct decode_cache *c;
bbd9b64e 2368
26eef70c 2369 kvm_clear_exception_queue(vcpu);
ad312c7c 2370 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2371 /*
2372 * TODO: fix x86_emulate.c to use guest_read/write_register
2373 * instead of direct ->regs accesses, can save hundred cycles
2374 * on Intel for instructions that don't read/change RSP, for
2375 * for example.
2376 */
2377 cache_all_regs(vcpu);
bbd9b64e
CO		 2378
2379 vcpu->mmio_is_write = 0;
ad312c7c 2380 vcpu->arch.pio.string = 0;
bbd9b64e 2381
571008da 2382 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2383 int cs_db, cs_l;
2384 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2385
ad312c7c
ZX		 2386 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2387 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2388 vcpu->arch.emulate_ctxt.mode =
2389 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2390 ? X86EMUL_MODE_REAL : cs_l
2391 ? X86EMUL_MODE_PROT64 : cs_db
2392 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2393
ad312c7c 2394 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2395
2396 /* Reject the instructions other than VMCALL/VMMCALL when
2397 * try to emulate invalid opcode */
2398 c = &vcpu->arch.emulate_ctxt.decode;
2399 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2400 (!(c->twobyte && c->b == 0x01 &&
2401 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2402 c->modrm_mod == 3 && c->modrm_rm == 1)))
2403 return EMULATE_FAIL;
2404
f2b5756b 2405 ++vcpu->stat.insn_emulation;
bbd9b64e 2406 if (r) {
f2b5756b 2407 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2408 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2409 return EMULATE_DONE;
2410 return EMULATE_FAIL;
2411 }
2412 }
2413
ad312c7c 2414 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2415
ad312c7c 2416 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2417 return EMULATE_DO_MMIO;
2418
2419 if ((r || vcpu->mmio_is_write) && run) {
2420 run->exit_reason = KVM_EXIT_MMIO;
2421 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2422 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2423 run->mmio.len = vcpu->mmio_size;
2424 run->mmio.is_write = vcpu->mmio_is_write;
2425 }
2426
2427 if (r) {
2428 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2429 return EMULATE_DONE;
2430 if (!vcpu->mmio_needed) {
2431 kvm_report_emulation_failure(vcpu, "mmio");
2432 return EMULATE_FAIL;
2433 }
2434 return EMULATE_DO_MMIO;
2435 }
2436
ad312c7c 2437 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2438
2439 if (vcpu->mmio_is_write) {
2440 vcpu->mmio_needed = 0;
2441 return EMULATE_DO_MMIO;
2442 }
2443
2444 return EMULATE_DONE;
2445}
2446EXPORT_SYMBOL_GPL(emulate_instruction);
2447
de7d789a
CO		 2448static int pio_copy_data(struct kvm_vcpu *vcpu)
2449{
ad312c7c 2450 void *p = vcpu->arch.pio_data;
0f346074 2451 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2452 unsigned bytes;
0f346074 2453 int ret;
de7d789a 2454
ad312c7c
ZX		 2455 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2456 if (vcpu->arch.pio.in)
0f346074 2457 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2458 else
0f346074
IE		 2459 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2460 return ret;
de7d789a
CO		 2461}
2462
2463int complete_pio(struct kvm_vcpu *vcpu)
2464{
ad312c7c 2465 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2466 long delta;
2467 int r;
5fdbf976 2468 unsigned long val;
de7d789a
CO		 2469
2470 if (!io->string) {
5fdbf976
MT		 2471 if (io->in) {
2472 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2473 memcpy(&val, vcpu->arch.pio_data, io->size);
2474 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2475 }
de7d789a
CO		 2476 } else {
2477 if (io->in) {
2478 r = pio_copy_data(vcpu);
5fdbf976 2479 if (r)
de7d789a 2480 return r;
de7d789a
CO		 2481 }
2482
2483 delta = 1;
2484 if (io->rep) {
2485 delta *= io->cur_count;
2486 /*
2487 * The size of the register should really depend on
2488 * current address size.
2489 */
5fdbf976
MT		 2490 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2491 val -= delta;
2492 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2493 }
2494 if (io->down)
2495 delta = -delta;
2496 delta *= io->size;
5fdbf976
MT		 2497 if (io->in) {
2498 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2499 val += delta;
2500 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2501 } else {
2502 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2503 val += delta;
2504 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2505 }
de7d789a
CO		 2506 }
2507
de7d789a
CO		 2508 io->count -= io->cur_count;
2509 io->cur_count = 0;
2510
2511 return 0;
2512}
2513
2514static void kernel_pio(struct kvm_io_device *pio_dev,
2515 struct kvm_vcpu *vcpu,
2516 void *pd)
2517{
2518 /* TODO: String I/O for in kernel device */
2519
2520 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2521 if (vcpu->arch.pio.in)
2522 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2523 vcpu->arch.pio.size,
de7d789a
CO		 2524 pd);
2525 else
ad312c7c
ZX		 2526 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2527 vcpu->arch.pio.size,
de7d789a
CO		 2528 pd);
2529 mutex_unlock(&vcpu->kvm->lock);
2530}
2531
2532static void pio_string_write(struct kvm_io_device *pio_dev,
2533 struct kvm_vcpu *vcpu)
2534{
ad312c7c
ZX		 2535 struct kvm_pio_request *io = &vcpu->arch.pio;
2536 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2537 int i;
2538
2539 mutex_lock(&vcpu->kvm->lock);
2540 for (i = 0; i < io->cur_count; i++) {
2541 kvm_iodevice_write(pio_dev, io->port,
2542 io->size,
2543 pd);
2544 pd += io->size;
2545 }
2546 mutex_unlock(&vcpu->kvm->lock);
2547}
2548
2549static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2550 gpa_t addr, int len,
2551 int is_write)
de7d789a 2552{
92760499 2553 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2554}
2555
2556int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2557 int size, unsigned port)
2558{
2559 struct kvm_io_device *pio_dev;
5fdbf976 2560 unsigned long val;
de7d789a
CO		 2561
2562 vcpu->run->exit_reason = KVM_EXIT_IO;
2563 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2564 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2565 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2566 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2567 vcpu->run->io.port = vcpu->arch.pio.port = port;
2568 vcpu->arch.pio.in = in;
2569 vcpu->arch.pio.string = 0;
2570 vcpu->arch.pio.down = 0;
ad312c7c 2571 vcpu->arch.pio.rep = 0;
de7d789a 2572
2714d1d3
FEL		 2573 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2574 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2575 handler);
2576 else
2577 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2578 handler);
2579
5fdbf976
MT		 2580 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2581 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2582
92760499 2583 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2584 if (pio_dev) {
ad312c7c 2585 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2586 complete_pio(vcpu);
2587 return 1;
2588 }
2589 return 0;
2590}
2591EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2592
2593int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2594 int size, unsigned long count, int down,
2595 gva_t address, int rep, unsigned port)
2596{
2597 unsigned now, in_page;
0f346074 2598 int ret = 0;
de7d789a
CO		 2599 struct kvm_io_device *pio_dev;
2600
2601 vcpu->run->exit_reason = KVM_EXIT_IO;
2602 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2603 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2604 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2605 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2606 vcpu->run->io.port = vcpu->arch.pio.port = port;
2607 vcpu->arch.pio.in = in;
2608 vcpu->arch.pio.string = 1;
2609 vcpu->arch.pio.down = down;
ad312c7c 2610 vcpu->arch.pio.rep = rep;
de7d789a 2611
2714d1d3
FEL		 2612 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2613 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2614 handler);
2615 else
2616 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2617 handler);
2618
de7d789a
CO		 2619 if (!count) {
2620 kvm_x86_ops->skip_emulated_instruction(vcpu);
2621 return 1;
2622 }
2623
2624 if (!down)
2625 in_page = PAGE_SIZE - offset_in_page(address);
2626 else
2627 in_page = offset_in_page(address) + size;
2628 now = min(count, (unsigned long)in_page / size);
0f346074 2629 if (!now)
de7d789a 2630 now = 1;
de7d789a
CO		 2631 if (down) {
2632 /*
2633 * String I/O in reverse. Yuck. Kill the guest, fix later.
2634 */
2635 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2636 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2637 return 1;
2638 }
2639 vcpu->run->io.count = now;
ad312c7c 2640 vcpu->arch.pio.cur_count = now;
de7d789a 2641
ad312c7c 2642 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2643 kvm_x86_ops->skip_emulated_instruction(vcpu);
2644
0f346074 2645 vcpu->arch.pio.guest_gva = address;
de7d789a 2646
92760499
LV		 2647 pio_dev = vcpu_find_pio_dev(vcpu, port,
2648 vcpu->arch.pio.cur_count,
2649 !vcpu->arch.pio.in);
ad312c7c 2650 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2651 /* string PIO write */
2652 ret = pio_copy_data(vcpu);
0f346074
IE		 2653 if (ret == X86EMUL_PROPAGATE_FAULT) {
2654 kvm_inject_gp(vcpu, 0);
2655 return 1;
2656 }
2657 if (ret == 0 && pio_dev) {
de7d789a
CO		 2658 pio_string_write(pio_dev, vcpu);
2659 complete_pio(vcpu);
ad312c7c 2660 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2661 ret = 1;
2662 }
2663 } else if (pio_dev)
2664 pr_unimpl(vcpu, "no string pio read support yet, "
2665 "port %x size %d count %ld\n",
2666 port, size, count);
2667
2668 return ret;
2669}
2670EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2671
c8076604
GH		 2672static void bounce_off(void *info)
2673{
2674 /* nothing */
2675}
2676
2677static unsigned int ref_freq;
2678static unsigned long tsc_khz_ref;
2679
2680static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2681 void *data)
2682{
2683 struct cpufreq_freqs *freq = data;
2684 struct kvm *kvm;
2685 struct kvm_vcpu *vcpu;
2686 int i, send_ipi = 0;
2687
2688 if (!ref_freq)
2689 ref_freq = freq->old;
2690
2691 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2692 return 0;
2693 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2694 return 0;
2695 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2696
2697 spin_lock(&kvm_lock);
2698 list_for_each_entry(kvm, &vm_list, vm_list) {
2699 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
2700 vcpu = kvm->vcpus[i];
2701 if (!vcpu)
2702 continue;
2703 if (vcpu->cpu != freq->cpu)
2704 continue;
2705 if (!kvm_request_guest_time_update(vcpu))
2706 continue;
2707 if (vcpu->cpu != smp_processor_id())
2708 send_ipi++;
2709 }
2710 }
2711 spin_unlock(&kvm_lock);
2712
2713 if (freq->old < freq->new && send_ipi) {
2714 /*
2715 * We upscale the frequency. Must make the guest
2716 * doesn't see old kvmclock values while running with
2717 * the new frequency, otherwise we risk the guest sees
2718 * time go backwards.
2719 *
2720 * In case we update the frequency for another cpu
2721 * (which might be in guest context) send an interrupt
2722 * to kick the cpu out of guest context. Next time
2723 * guest context is entered kvmclock will be updated,
2724 * so the guest will not see stale values.
2725 */
2726 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
2727 }
2728 return 0;
2729}
2730
2731static struct notifier_block kvmclock_cpufreq_notifier_block = {
2732 .notifier_call = kvmclock_cpufreq_notifier
2733};
2734
f8c16bba 2735int kvm_arch_init(void *opaque)
043405e1 2736{
c8076604 2737 int r, cpu;
f8c16bba
ZX		 2738 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2739
f8c16bba
ZX		 2740 if (kvm_x86_ops) {
2741 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2742 r = -EEXIST;
2743 goto out;
f8c16bba
ZX		 2744 }
2745
2746 if (!ops->cpu_has_kvm_support()) {
2747 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2748 r = -EOPNOTSUPP;
2749 goto out;
f8c16bba
ZX		 2750 }
2751 if (ops->disabled_by_bios()) {
2752 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2753 r = -EOPNOTSUPP;
2754 goto out;
f8c16bba
ZX		 2755 }
2756
97db56ce
AK		 2757 r = kvm_mmu_module_init();
2758 if (r)
2759 goto out;
2760
2761 kvm_init_msr_list();
2762
f8c16bba 2763 kvm_x86_ops = ops;
56c6d28a 2764 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2765 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2766 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2767 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
c8076604
GH		 2768
2769 for_each_possible_cpu(cpu)
2770 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
2771 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
2772 tsc_khz_ref = tsc_khz;
2773 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
2774 CPUFREQ_TRANSITION_NOTIFIER);
2775 }
2776
f8c16bba 2777 return 0;
56c6d28a
ZX		 2778
2779out:
56c6d28a 2780 return r;
043405e1 2781}
8776e519 2782
f8c16bba
ZX		 2783void kvm_arch_exit(void)
2784{
888d256e
JK		 2785 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
2786 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
2787 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 2788 kvm_x86_ops = NULL;
56c6d28a
ZX		 2789 kvm_mmu_module_exit();
2790}
f8c16bba 2791
8776e519
HB		 2792int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2793{
2794 ++vcpu->stat.halt_exits;
2714d1d3 2795 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2796 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2797 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2798 return 1;
2799 } else {
2800 vcpu->run->exit_reason = KVM_EXIT_HLT;
2801 return 0;
2802 }
2803}
2804EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2805
2f333bcb
MT		 2806static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2807 unsigned long a1)
2808{
2809 if (is_long_mode(vcpu))
2810 return a0;
2811 else
2812 return a0 | ((gpa_t)a1 << 32);
2813}
2814
8776e519
HB		 2815int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2816{
2817 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2818 int r = 1;
8776e519 2819
5fdbf976
MT		 2820 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2821 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2822 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2823 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2824 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2825
2714d1d3
FEL		 2826 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2827
8776e519
HB		 2828 if (!is_long_mode(vcpu)) {
2829 nr &= 0xFFFFFFFF;
2830 a0 &= 0xFFFFFFFF;
2831 a1 &= 0xFFFFFFFF;
2832 a2 &= 0xFFFFFFFF;
2833 a3 &= 0xFFFFFFFF;
2834 }
2835
2836 switch (nr) {
b93463aa
AK		 2837 case KVM_HC_VAPIC_POLL_IRQ:
2838 ret = 0;
2839 break;
2f333bcb
MT		 2840 case KVM_HC_MMU_OP:
2841 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2842 break;
8776e519
HB		 2843 default:
2844 ret = -KVM_ENOSYS;
2845 break;
2846 }
5fdbf976 2847 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2848 ++vcpu->stat.hypercalls;
2f333bcb 2849 return r;
8776e519
HB		 2850}
2851EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2852
2853int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2854{
2855 char instruction[3];
2856 int ret = 0;
5fdbf976 2857 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2858
8776e519
HB		 2859
2860 /*
2861 * Blow out the MMU to ensure that no other VCPU has an active mapping
2862 * to ensure that the updated hypercall appears atomically across all
2863 * VCPUs.
2864 */
2865 kvm_mmu_zap_all(vcpu->kvm);
2866
8776e519 2867 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2868 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2869 != X86EMUL_CONTINUE)
2870 ret = -EFAULT;
2871
8776e519
HB		 2872 return ret;
2873}
2874
2875static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2876{
2877 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2878}
2879
2880void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2881{
2882 struct descriptor_table dt = { limit, base };
2883
2884 kvm_x86_ops->set_gdt(vcpu, &dt);
2885}
2886
2887void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2888{
2889 struct descriptor_table dt = { limit, base };
2890
2891 kvm_x86_ops->set_idt(vcpu, &dt);
2892}
2893
2894void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2895 unsigned long *rflags)
2896{
2d3ad1f4 2897 kvm_lmsw(vcpu, msw);
8776e519
HB		 2898 *rflags = kvm_x86_ops->get_rflags(vcpu);
2899}
2900
2901unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2902{
54e445ca
JR		 2903 unsigned long value;
2904
8776e519
HB		 2905 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2906 switch (cr) {
2907 case 0:
54e445ca
JR		 2908 value = vcpu->arch.cr0;
2909 break;
8776e519 2910 case 2:
54e445ca
JR		 2911 value = vcpu->arch.cr2;
2912 break;
8776e519 2913 case 3:
54e445ca
JR		 2914 value = vcpu->arch.cr3;
2915 break;
8776e519 2916 case 4:
54e445ca
JR		 2917 value = vcpu->arch.cr4;
2918 break;
152ff9be 2919 case 8:
54e445ca
JR		 2920 value = kvm_get_cr8(vcpu);
2921 break;
8776e519 2922 default:
b8688d51 2923 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2924 return 0;
2925 }
54e445ca
JR		 2926 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2927 (u32)((u64)value >> 32), handler);
2928
2929 return value;
8776e519
HB		 2930}
2931
2932void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2933 unsigned long *rflags)
2934{
54e445ca
JR		 2935 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2936 (u32)((u64)val >> 32), handler);
2937
8776e519
HB		 2938 switch (cr) {
2939 case 0:
2d3ad1f4 2940 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2941 *rflags = kvm_x86_ops->get_rflags(vcpu);
2942 break;
2943 case 2:
ad312c7c 2944 vcpu->arch.cr2 = val;
8776e519
HB		 2945 break;
2946 case 3:
2d3ad1f4 2947 kvm_set_cr3(vcpu, val);
8776e519
HB		 2948 break;
2949 case 4:
2d3ad1f4 2950 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2951 break;
152ff9be 2952 case 8:
2d3ad1f4 2953 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2954 break;
8776e519 2955 default:
b8688d51 2956 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2957 }
2958}
2959
07716717
DK		 2960static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2961{
ad312c7c
ZX		 2962 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2963 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2964
2965 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2966 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2967 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2968 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2969 if (ej->function == e->function) {
2970 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2971 return j;
2972 }
2973 }
2974 return 0; /* silence gcc, even though control never reaches here */
2975}
2976
2977/* find an entry with matching function, matching index (if needed), and that
2978 * should be read next (if it's stateful) */
2979static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2980 u32 function, u32 index)
2981{
2982 if (e->function != function)
2983 return 0;
2984 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2985 return 0;
2986 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 2987 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 2988 return 0;
2989 return 1;
2990}
2991
d8017474
AG		 2992struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
2993 u32 function, u32 index)
8776e519
HB		 2994{
2995 int i;
d8017474 2996 struct kvm_cpuid_entry2 *best = NULL;
8776e519 2997
ad312c7c 2998 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 2999 struct kvm_cpuid_entry2 *e;
3000
ad312c7c 3001 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3002 if (is_matching_cpuid_entry(e, function, index)) {
3003 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3004 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3005 best = e;
3006 break;
3007 }
3008 /*
3009 * Both basic or both extended?
3010 */
3011 if (((e->function ^ function) & 0x80000000) == 0)
3012 if (!best || e->function > best->function)
3013 best = e;
3014 }
d8017474
AG		 3015 return best;
3016}
3017
3018void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3019{
3020 u32 function, index;
3021 struct kvm_cpuid_entry2 *best;
3022
3023 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3024 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3025 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3026 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3027 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3028 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3029 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3030 if (best) {
5fdbf976
MT		 3031 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3032 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3033 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3034 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3035 }
8776e519 3036 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 3037 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 3038 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
3039 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
3040 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
3041 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 3042}
3043EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3044
b6c7a5dc
HB		 3045/*
3046 * Check if userspace requested an interrupt window, and that the
3047 * interrupt window is open.
3048 *
3049 * No need to exit to userspace if we already have an interrupt queued.
3050 */
3051static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3052 struct kvm_run *kvm_run)
3053{
ad312c7c 3054 return (!vcpu->arch.irq_summary &&
b6c7a5dc 3055 kvm_run->request_interrupt_window &&
ad312c7c 3056 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 3057 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
3058}
3059
3060static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3061 struct kvm_run *kvm_run)
3062{
3063 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3064 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3065 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3066 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3067 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3068 else
b6c7a5dc 3069 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 3070 (vcpu->arch.interrupt_window_open &&
3071 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 3072}
3073
b93463aa
AK		 3074static void vapic_enter(struct kvm_vcpu *vcpu)
3075{
3076 struct kvm_lapic *apic = vcpu->arch.apic;
3077 struct page *page;
3078
3079 if (!apic || !apic->vapic_addr)
3080 return;
3081
3082 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3083
3084 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3085}
3086
3087static void vapic_exit(struct kvm_vcpu *vcpu)
3088{
3089 struct kvm_lapic *apic = vcpu->arch.apic;
3090
3091 if (!apic || !apic->vapic_addr)
3092 return;
3093
f8b78fa3 3094 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3095 kvm_release_page_dirty(apic->vapic_page);
3096 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3097 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3098}
3099
d7690175 3100static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3101{
3102 int r;
3103
2e53d63a
MT		 3104 if (vcpu->requests)
3105 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3106 kvm_mmu_unload(vcpu);
3107
b6c7a5dc
HB		 3108 r = kvm_mmu_reload(vcpu);
3109 if (unlikely(r))
3110 goto out;
3111
2f52d58c
AK		 3112 if (vcpu->requests) {
3113 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3114 __kvm_migrate_timers(vcpu);
c8076604
GH		 3115 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3116 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3117 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3118 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3119 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3120 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3121 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3122 &vcpu->requests)) {
3123 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3124 r = 0;
3125 goto out;
3126 }
71c4dfaf
JR		 3127 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3128 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3129 r = 0;
3130 goto out;
3131 }
2f52d58c 3132 }
b93463aa 3133
06e05645 3134 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 3135 kvm_inject_pending_timer_irqs(vcpu);
3136
3137 preempt_disable();
3138
3139 kvm_x86_ops->prepare_guest_switch(vcpu);
3140 kvm_load_guest_fpu(vcpu);
3141
3142 local_irq_disable();
3143
d7690175 3144 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3145 local_irq_enable();
3146 preempt_enable();
3147 r = 1;
3148 goto out;
3149 }
3150
e9571ed5
MT		 3151 vcpu->guest_mode = 1;
3152 /*
3153 * Make sure that guest_mode assignment won't happen after
3154 * testing the pending IRQ vector bitmap.
3155 */
3156 smp_wmb();
3157
ad312c7c 3158 if (vcpu->arch.exception.pending)
298101da
AK		 3159 __queue_exception(vcpu);
3160 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3161 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3162 else
b6c7a5dc
HB		 3163 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3164
b93463aa
AK		 3165 kvm_lapic_sync_to_vapic(vcpu);
3166
3200f405
MT		 3167 up_read(&vcpu->kvm->slots_lock);
3168
b6c7a5dc
HB		 3169 kvm_guest_enter();
3170
42dbaa5a
JK		 3171 get_debugreg(vcpu->arch.host_dr6, 6);
3172 get_debugreg(vcpu->arch.host_dr7, 7);
3173 if (unlikely(vcpu->arch.switch_db_regs)) {
3174 get_debugreg(vcpu->arch.host_db[0], 0);
3175 get_debugreg(vcpu->arch.host_db[1], 1);
3176 get_debugreg(vcpu->arch.host_db[2], 2);
3177 get_debugreg(vcpu->arch.host_db[3], 3);
3178
3179 set_debugreg(0, 7);
3180 set_debugreg(vcpu->arch.eff_db[0], 0);
3181 set_debugreg(vcpu->arch.eff_db[1], 1);
3182 set_debugreg(vcpu->arch.eff_db[2], 2);
3183 set_debugreg(vcpu->arch.eff_db[3], 3);
3184 }
b6c7a5dc 3185
2714d1d3 3186 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3187 kvm_x86_ops->run(vcpu, kvm_run);
3188
42dbaa5a
JK		 3189 if (unlikely(vcpu->arch.switch_db_regs)) {
3190 set_debugreg(0, 7);
3191 set_debugreg(vcpu->arch.host_db[0], 0);
3192 set_debugreg(vcpu->arch.host_db[1], 1);
3193 set_debugreg(vcpu->arch.host_db[2], 2);
3194 set_debugreg(vcpu->arch.host_db[3], 3);
3195 }
3196 set_debugreg(vcpu->arch.host_dr6, 6);
3197 set_debugreg(vcpu->arch.host_dr7, 7);
3198
b6c7a5dc
HB		 3199 vcpu->guest_mode = 0;
3200 local_irq_enable();
3201
3202 ++vcpu->stat.exits;
3203
3204 /*
3205 * We must have an instruction between local_irq_enable() and
3206 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3207 * the interrupt shadow. The stat.exits increment will do nicely.
3208 * But we need to prevent reordering, hence this barrier():
3209 */
3210 barrier();
3211
3212 kvm_guest_exit();
3213
3214 preempt_enable();
3215
3200f405
MT		 3216 down_read(&vcpu->kvm->slots_lock);
3217
b6c7a5dc
HB		 3218 /*
3219 * Profile KVM exit RIPs:
3220 */
3221 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3222 unsigned long rip = kvm_rip_read(vcpu);
3223 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3224 }
3225
ad312c7c
ZX		 3226 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3227 vcpu->arch.exception.pending = false;
298101da 3228
b93463aa
AK		 3229 kvm_lapic_sync_from_vapic(vcpu);
3230
b6c7a5dc 3231 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3232out:
3233 return r;
3234}
b6c7a5dc 3235
d7690175
MT		 3236static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3237{
3238 int r;
3239
3240 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3241 pr_debug("vcpu %d received sipi with vector # %x\n",
3242 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3243 kvm_lapic_reset(vcpu);
5f179287 3244 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3245 if (r)
3246 return r;
3247 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3248 }
3249
d7690175
MT		 3250 down_read(&vcpu->kvm->slots_lock);
3251 vapic_enter(vcpu);
3252
3253 r = 1;
3254 while (r > 0) {
af2152f5 3255 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3256 r = vcpu_enter_guest(vcpu, kvm_run);
3257 else {
3258 up_read(&vcpu->kvm->slots_lock);
3259 kvm_vcpu_block(vcpu);
3260 down_read(&vcpu->kvm->slots_lock);
3261 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3262 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3263 vcpu->arch.mp_state =
3264 KVM_MP_STATE_RUNNABLE;
3265 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3266 r = -EINTR;
3267 }
3268
3269 if (r > 0) {
3270 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3271 r = -EINTR;
3272 kvm_run->exit_reason = KVM_EXIT_INTR;
3273 ++vcpu->stat.request_irq_exits;
3274 }
3275 if (signal_pending(current)) {
3276 r = -EINTR;
3277 kvm_run->exit_reason = KVM_EXIT_INTR;
3278 ++vcpu->stat.signal_exits;
3279 }
3280 if (need_resched()) {
3281 up_read(&vcpu->kvm->slots_lock);
3282 kvm_resched(vcpu);
3283 down_read(&vcpu->kvm->slots_lock);
3284 }
3285 }
b6c7a5dc
HB		 3286 }
3287
d7690175 3288 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3289 post_kvm_run_save(vcpu, kvm_run);
3290
b93463aa
AK		 3291 vapic_exit(vcpu);
3292
b6c7a5dc
HB		 3293 return r;
3294}
3295
3296int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3297{
3298 int r;
3299 sigset_t sigsaved;
3300
3301 vcpu_load(vcpu);
3302
ac9f6dc0
AK		 3303 if (vcpu->sigset_active)
3304 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3305
a4535290 3306 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3307 kvm_vcpu_block(vcpu);
d7690175 3308 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3309 r = -EAGAIN;
3310 goto out;
b6c7a5dc
HB		 3311 }
3312
b6c7a5dc
HB		 3313 /* re-sync apic's tpr */
3314 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3315 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3316
ad312c7c 3317 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3318 r = complete_pio(vcpu);
3319 if (r)
3320 goto out;
3321 }
3322#if CONFIG_HAS_IOMEM
3323 if (vcpu->mmio_needed) {
3324 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3325 vcpu->mmio_read_completed = 1;
3326 vcpu->mmio_needed = 0;
3200f405
MT		 3327
3328 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3329 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3330 vcpu->arch.mmio_fault_cr2, 0,
3331 EMULTYPE_NO_DECODE);
3200f405 3332 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3333 if (r == EMULATE_DO_MMIO) {
3334 /*
3335 * Read-modify-write. Back to userspace.
3336 */
3337 r = 0;
3338 goto out;
3339 }
3340 }
3341#endif
5fdbf976
MT		 3342 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3343 kvm_register_write(vcpu, VCPU_REGS_RAX,
3344 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3345
3346 r = __vcpu_run(vcpu, kvm_run);
3347
3348out:
3349 if (vcpu->sigset_active)
3350 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3351
3352 vcpu_put(vcpu);
3353 return r;
3354}
3355
3356int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3357{
3358 vcpu_load(vcpu);
3359
5fdbf976
MT		 3360 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3361 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3362 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3363 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3364 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3365 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3366 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3367 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3368#ifdef CONFIG_X86_64
5fdbf976
MT		 3369 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3370 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3371 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3372 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3373 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3374 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3375 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3376 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3377#endif
3378
5fdbf976 3379 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3380 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3381
3382 /*
3383 * Don't leak debug flags in case they were set for guest debugging
3384 */
d0bfb940 3385 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3386 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3387
3388 vcpu_put(vcpu);
3389
3390 return 0;
3391}
3392
3393int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3394{
3395 vcpu_load(vcpu);
3396
5fdbf976
MT		 3397 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3398 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3399 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3400 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3401 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3402 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3403 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3404 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3405#ifdef CONFIG_X86_64
5fdbf976
MT		 3406 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3407 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3408 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3409 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3410 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3411 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3412 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3413 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3414
b6c7a5dc
HB		 3415#endif
3416
5fdbf976 3417 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3418 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3419
b6c7a5dc 3420
b4f14abd
JK		 3421 vcpu->arch.exception.pending = false;
3422
b6c7a5dc
HB		 3423 vcpu_put(vcpu);
3424
3425 return 0;
3426}
3427
3e6e0aab
GT		 3428void kvm_get_segment(struct kvm_vcpu *vcpu,
3429 struct kvm_segment *var, int seg)
b6c7a5dc 3430{
14af3f3c 3431 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3432}
3433
3434void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3435{
3436 struct kvm_segment cs;
3437
3e6e0aab 3438 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3439 *db = cs.db;
3440 *l = cs.l;
3441}
3442EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3443
3444int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3445 struct kvm_sregs *sregs)
3446{
3447 struct descriptor_table dt;
3448 int pending_vec;
3449
3450 vcpu_load(vcpu);
3451
3e6e0aab
GT		 3452 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3453 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3454 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3455 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3456 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3457 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3458
3e6e0aab
GT		 3459 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3460 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3461
3462 kvm_x86_ops->get_idt(vcpu, &dt);
3463 sregs->idt.limit = dt.limit;
3464 sregs->idt.base = dt.base;
3465 kvm_x86_ops->get_gdt(vcpu, &dt);
3466 sregs->gdt.limit = dt.limit;
3467 sregs->gdt.base = dt.base;
3468
3469 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3470 sregs->cr0 = vcpu->arch.cr0;
3471 sregs->cr2 = vcpu->arch.cr2;
3472 sregs->cr3 = vcpu->arch.cr3;
3473 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3474 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3475 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3476 sregs->apic_base = kvm_get_apic_base(vcpu);
3477
3478 if (irqchip_in_kernel(vcpu->kvm)) {
3479 memset(sregs->interrupt_bitmap, 0,
3480 sizeof sregs->interrupt_bitmap);
3481 pending_vec = kvm_x86_ops->get_irq(vcpu);
3482 if (pending_vec >= 0)
3483 set_bit(pending_vec,
3484 (unsigned long *)sregs->interrupt_bitmap);
3485 } else
ad312c7c 3486 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3487 sizeof sregs->interrupt_bitmap);
3488
3489 vcpu_put(vcpu);
3490
3491 return 0;
3492}
3493
62d9f0db
MT		 3494int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3495 struct kvm_mp_state *mp_state)
3496{
3497 vcpu_load(vcpu);
3498 mp_state->mp_state = vcpu->arch.mp_state;
3499 vcpu_put(vcpu);
3500 return 0;
3501}
3502
3503int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3504 struct kvm_mp_state *mp_state)
3505{
3506 vcpu_load(vcpu);
3507 vcpu->arch.mp_state = mp_state->mp_state;
3508 vcpu_put(vcpu);
3509 return 0;
3510}
3511
3e6e0aab 3512static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3513 struct kvm_segment *var, int seg)
3514{
14af3f3c 3515 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3516}
3517
37817f29
IE		 3518static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3519 struct kvm_segment *kvm_desct)
3520{
3521 kvm_desct->base = seg_desc->base0;
3522 kvm_desct->base |= seg_desc->base1 << 16;
3523 kvm_desct->base |= seg_desc->base2 << 24;
3524 kvm_desct->limit = seg_desc->limit0;
3525 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3526 if (seg_desc->g) {
3527 kvm_desct->limit <<= 12;
3528 kvm_desct->limit |= 0xfff;
3529 }
37817f29
IE		 3530 kvm_desct->selector = selector;
3531 kvm_desct->type = seg_desc->type;
3532 kvm_desct->present = seg_desc->p;
3533 kvm_desct->dpl = seg_desc->dpl;
3534 kvm_desct->db = seg_desc->d;
3535 kvm_desct->s = seg_desc->s;
3536 kvm_desct->l = seg_desc->l;
3537 kvm_desct->g = seg_desc->g;
3538 kvm_desct->avl = seg_desc->avl;
3539 if (!selector)
3540 kvm_desct->unusable = 1;
3541 else
3542 kvm_desct->unusable = 0;
3543 kvm_desct->padding = 0;
3544}
3545
b8222ad2
AS		 3546static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3547 u16 selector,
3548 struct descriptor_table *dtable)
37817f29
IE		 3549{
3550 if (selector & 1 << 2) {
3551 struct kvm_segment kvm_seg;
3552
3e6e0aab 3553 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3554
3555 if (kvm_seg.unusable)
3556 dtable->limit = 0;
3557 else
3558 dtable->limit = kvm_seg.limit;
3559 dtable->base = kvm_seg.base;
3560 }
3561 else
3562 kvm_x86_ops->get_gdt(vcpu, dtable);
3563}
3564
3565/* allowed just for 8 bytes segments */
3566static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3567 struct desc_struct *seg_desc)
3568{
98899aa0 3569 gpa_t gpa;
37817f29
IE		 3570 struct descriptor_table dtable;
3571 u16 index = selector >> 3;
3572
b8222ad2 3573 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3574
3575 if (dtable.limit < index * 8 + 7) {
3576 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3577 return 1;
3578 }
98899aa0
MT		 3579 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3580 gpa += index * 8;
3581 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3582}
3583
3584/* allowed just for 8 bytes segments */
3585static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3586 struct desc_struct *seg_desc)
3587{
98899aa0 3588 gpa_t gpa;
37817f29
IE		 3589 struct descriptor_table dtable;
3590 u16 index = selector >> 3;
3591
b8222ad2 3592 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3593
3594 if (dtable.limit < index * 8 + 7)
3595 return 1;
98899aa0
MT		 3596 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3597 gpa += index * 8;
3598 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3599}
3600
3601static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3602 struct desc_struct *seg_desc)
3603{
3604 u32 base_addr;
3605
3606 base_addr = seg_desc->base0;
3607 base_addr |= (seg_desc->base1 << 16);
3608 base_addr |= (seg_desc->base2 << 24);
3609
98899aa0 3610 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3611}
3612
37817f29
IE		 3613static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3614{
3615 struct kvm_segment kvm_seg;
3616
3e6e0aab 3617 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3618 return kvm_seg.selector;
3619}
3620
3621static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3622 u16 selector,
3623 struct kvm_segment *kvm_seg)
3624{
3625 struct desc_struct seg_desc;
3626
3627 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3628 return 1;
3629 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3630 return 0;
3631}
3632
2259e3a7 3633static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3634{
3635 struct kvm_segment segvar = {
3636 .base = selector << 4,
3637 .limit = 0xffff,
3638 .selector = selector,
3639 .type = 3,
3640 .present = 1,
3641 .dpl = 3,
3642 .db = 0,
3643 .s = 1,
3644 .l = 0,
3645 .g = 0,
3646 .avl = 0,
3647 .unusable = 0,
3648 };
3649 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3650 return 0;
3651}
3652
3e6e0aab
GT		 3653int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3654 int type_bits, int seg)
37817f29
IE		 3655{
3656 struct kvm_segment kvm_seg;
3657
f4bbd9aa
AK		 3658 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3659 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3660 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3661 return 1;
3662 kvm_seg.type |= type_bits;
3663
3664 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3665 seg != VCPU_SREG_LDTR)
3666 if (!kvm_seg.s)
3667 kvm_seg.unusable = 1;
3668
3e6e0aab 3669 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3670 return 0;
3671}
3672
3673static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3674 struct tss_segment_32 *tss)
3675{
3676 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3677 tss->eip = kvm_rip_read(vcpu);
37817f29 3678 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3679 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3680 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3681 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3682 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3683 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3684 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3685 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3686 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3687 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3688 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3689 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3690 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3691 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3692 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3693 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3694 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3695}
3696
3697static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3698 struct tss_segment_32 *tss)
3699{
3700 kvm_set_cr3(vcpu, tss->cr3);
3701
5fdbf976 3702 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3703 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3704
5fdbf976
MT		 3705 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3706 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3707 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3708 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3709 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3710 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3711 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3712 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3713
3e6e0aab 3714 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3715 return 1;
3716
3e6e0aab 3717 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3718 return 1;
3719
3e6e0aab 3720 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3721 return 1;
3722
3e6e0aab 3723 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3724 return 1;
3725
3e6e0aab 3726 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3727 return 1;
3728
3e6e0aab 3729 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3730 return 1;
3731
3e6e0aab 3732 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3733 return 1;
3734 return 0;
3735}
3736
3737static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3738 struct tss_segment_16 *tss)
3739{
5fdbf976 3740 tss->ip = kvm_rip_read(vcpu);
37817f29 3741 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3742 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3743 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3744 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3745 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3746 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3747 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3748 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3749 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3750
3751 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3752 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3753 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3754 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3755 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3756 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3757}
3758
3759static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3760 struct tss_segment_16 *tss)
3761{
5fdbf976 3762 kvm_rip_write(vcpu, tss->ip);
37817f29 3763 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3764 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3765 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3766 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3767 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3768 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3769 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3770 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3771 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3772
3e6e0aab 3773 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3774 return 1;
3775
3e6e0aab 3776 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3777 return 1;
3778
3e6e0aab 3779 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3780 return 1;
3781
3e6e0aab 3782 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3783 return 1;
3784
3e6e0aab 3785 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3786 return 1;
3787 return 0;
3788}
3789
8b2cf73c 3790static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3791 u32 old_tss_base,
37817f29
IE		 3792 struct desc_struct *nseg_desc)
3793{
3794 struct tss_segment_16 tss_segment_16;
3795 int ret = 0;
3796
34198bf8
MT		 3797 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3798 sizeof tss_segment_16))
37817f29
IE		 3799 goto out;
3800
3801 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3802
34198bf8
MT		 3803 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3804 sizeof tss_segment_16))
37817f29 3805 goto out;
34198bf8
MT		 3806
3807 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3808 &tss_segment_16, sizeof tss_segment_16))
3809 goto out;
3810
37817f29
IE		 3811 if (load_state_from_tss16(vcpu, &tss_segment_16))
3812 goto out;
3813
3814 ret = 1;
3815out:
3816 return ret;
3817}
3818
8b2cf73c 3819static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3820 u32 old_tss_base,
37817f29
IE		 3821 struct desc_struct *nseg_desc)
3822{
3823 struct tss_segment_32 tss_segment_32;
3824 int ret = 0;
3825
34198bf8
MT		 3826 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3827 sizeof tss_segment_32))
37817f29
IE		 3828 goto out;
3829
3830 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3831
34198bf8
MT		 3832 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3833 sizeof tss_segment_32))
3834 goto out;
3835
3836 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3837 &tss_segment_32, sizeof tss_segment_32))
37817f29 3838 goto out;
34198bf8 3839
37817f29
IE		 3840 if (load_state_from_tss32(vcpu, &tss_segment_32))
3841 goto out;
3842
3843 ret = 1;
3844out:
3845 return ret;
3846}
3847
3848int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3849{
3850 struct kvm_segment tr_seg;
3851 struct desc_struct cseg_desc;
3852 struct desc_struct nseg_desc;
3853 int ret = 0;
34198bf8
MT		 3854 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3855 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3856
34198bf8 3857 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3858
34198bf8
MT		 3859 /* FIXME: Handle errors. Failure to read either TSS or their
3860 * descriptors should generate a pagefault.
3861 */
37817f29
IE		 3862 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3863 goto out;
3864
34198bf8 3865 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3866 goto out;
3867
37817f29
IE		 3868 if (reason != TASK_SWITCH_IRET) {
3869 int cpl;
3870
3871 cpl = kvm_x86_ops->get_cpl(vcpu);
3872 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3873 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3874 return 1;
3875 }
3876 }
3877
3878 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3879 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3880 return 1;
3881 }
3882
3883 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3884 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3885 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3886 }
3887
3888 if (reason == TASK_SWITCH_IRET) {
3889 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3890 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3891 }
3892
3893 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3894
3895 if (nseg_desc.type & 8)
34198bf8 3896 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3897 &nseg_desc);
3898 else
34198bf8 3899 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3900 &nseg_desc);
3901
3902 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3903 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3904 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3905 }
3906
3907 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3908 nseg_desc.type |= (1 << 1);
37817f29
IE		 3909 save_guest_segment_descriptor(vcpu, tss_selector,
3910 &nseg_desc);
3911 }
3912
3913 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3914 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3915 tr_seg.type = 11;
3e6e0aab 3916 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3917out:
37817f29
IE		 3918 return ret;
3919}
3920EXPORT_SYMBOL_GPL(kvm_task_switch);
3921
b6c7a5dc
HB		 3922int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3923 struct kvm_sregs *sregs)
3924{
3925 int mmu_reset_needed = 0;
3926 int i, pending_vec, max_bits;
3927 struct descriptor_table dt;
3928
3929 vcpu_load(vcpu);
3930
3931 dt.limit = sregs->idt.limit;
3932 dt.base = sregs->idt.base;
3933 kvm_x86_ops->set_idt(vcpu, &dt);
3934 dt.limit = sregs->gdt.limit;
3935 dt.base = sregs->gdt.base;
3936 kvm_x86_ops->set_gdt(vcpu, &dt);
3937
ad312c7c
ZX		 3938 vcpu->arch.cr2 = sregs->cr2;
3939 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3940 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3941
2d3ad1f4 3942 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3943
ad312c7c 3944 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3945 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3946 kvm_set_apic_base(vcpu, sregs->apic_base);
3947
3948 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3949
ad312c7c 3950 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3951 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3952 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3953
ad312c7c 3954 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3955 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3956 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3957 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3958
3959 if (mmu_reset_needed)
3960 kvm_mmu_reset_context(vcpu);
3961
3962 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3963 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3964 sizeof vcpu->arch.irq_pending);
3965 vcpu->arch.irq_summary = 0;
3966 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3967 if (vcpu->arch.irq_pending[i])
3968 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3969 } else {
3970 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3971 pending_vec = find_first_bit(
3972 (const unsigned long *)sregs->interrupt_bitmap,
3973 max_bits);
3974 /* Only pending external irq is handled here */
3975 if (pending_vec < max_bits) {
3976 kvm_x86_ops->set_irq(vcpu, pending_vec);
3977 pr_debug("Set back pending irq %d\n",
3978 pending_vec);
3979 }
e4825800 3980 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 3981 }
3982
3e6e0aab
GT		 3983 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3984 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3985 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3986 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3987 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3988 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3989
3e6e0aab
GT		 3990 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3991 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3992
9c3e4aab
MT		 3993 /* Older userspace won't unhalt the vcpu on reset. */
3994 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3995 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3996 !(vcpu->arch.cr0 & X86_CR0_PE))
3997 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3998
b6c7a5dc
HB		 3999 vcpu_put(vcpu);
4000
4001 return 0;
4002}
4003
d0bfb940
JK		 4004int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4005 struct kvm_guest_debug *dbg)
b6c7a5dc 4006{
ae675ef0 4007 int i, r;
b6c7a5dc
HB		 4008
4009 vcpu_load(vcpu);
4010
ae675ef0
JK		 4011 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4012 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4013 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4014 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4015 vcpu->arch.switch_db_regs =
4016 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4017 } else {
4018 for (i = 0; i < KVM_NR_DB_REGS; i++)
4019 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4020 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4021 }
4022
b6c7a5dc
HB		 4023 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4024
d0bfb940
JK		 4025 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4026 kvm_queue_exception(vcpu, DB_VECTOR);
4027 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4028 kvm_queue_exception(vcpu, BP_VECTOR);
4029
b6c7a5dc
HB		 4030 vcpu_put(vcpu);
4031
4032 return r;
4033}
4034
d0752060
HB		 4035/*
4036 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4037 * we have asm/x86/processor.h
4038 */
4039struct fxsave {
4040 u16 cwd;
4041 u16 swd;
4042 u16 twd;
4043 u16 fop;
4044 u64 rip;
4045 u64 rdp;
4046 u32 mxcsr;
4047 u32 mxcsr_mask;
4048 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4049#ifdef CONFIG_X86_64
4050 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4051#else
4052 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4053#endif
4054};
4055
8b006791
ZX		 4056/*
4057 * Translate a guest virtual address to a guest physical address.
4058 */
4059int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4060 struct kvm_translation *tr)
4061{
4062 unsigned long vaddr = tr->linear_address;
4063 gpa_t gpa;
4064
4065 vcpu_load(vcpu);
72dc67a6 4066 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4067 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4068 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4069 tr->physical_address = gpa;
4070 tr->valid = gpa != UNMAPPED_GVA;
4071 tr->writeable = 1;
4072 tr->usermode = 0;
8b006791
ZX		 4073 vcpu_put(vcpu);
4074
4075 return 0;
4076}
4077
d0752060
HB		 4078int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4079{
ad312c7c 4080 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4081
4082 vcpu_load(vcpu);
4083
4084 memcpy(fpu->fpr, fxsave->st_space, 128);
4085 fpu->fcw = fxsave->cwd;
4086 fpu->fsw = fxsave->swd;
4087 fpu->ftwx = fxsave->twd;
4088 fpu->last_opcode = fxsave->fop;
4089 fpu->last_ip = fxsave->rip;
4090 fpu->last_dp = fxsave->rdp;
4091 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4092
4093 vcpu_put(vcpu);
4094
4095 return 0;
4096}
4097
4098int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4099{
ad312c7c 4100 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4101
4102 vcpu_load(vcpu);
4103
4104 memcpy(fxsave->st_space, fpu->fpr, 128);
4105 fxsave->cwd = fpu->fcw;
4106 fxsave->swd = fpu->fsw;
4107 fxsave->twd = fpu->ftwx;
4108 fxsave->fop = fpu->last_opcode;
4109 fxsave->rip = fpu->last_ip;
4110 fxsave->rdp = fpu->last_dp;
4111 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4112
4113 vcpu_put(vcpu);
4114
4115 return 0;
4116}
4117
4118void fx_init(struct kvm_vcpu *vcpu)
4119{
4120 unsigned after_mxcsr_mask;
4121
bc1a34f1
AA		 4122 /*
4123 * Touch the fpu the first time in non atomic context as if
4124 * this is the first fpu instruction the exception handler
4125 * will fire before the instruction returns and it'll have to
4126 * allocate ram with GFP_KERNEL.
4127 */
4128 if (!used_math())
d6e88aec 4129 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4130
d0752060
HB		 4131 /* Initialize guest FPU by resetting ours and saving into guest's */
4132 preempt_disable();
d6e88aec
AK		 4133 kvm_fx_save(&vcpu->arch.host_fx_image);
4134 kvm_fx_finit();
4135 kvm_fx_save(&vcpu->arch.guest_fx_image);
4136 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4137 preempt_enable();
4138
ad312c7c 4139 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4140 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4141 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4142 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4143 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4144}
4145EXPORT_SYMBOL_GPL(fx_init);
4146
4147void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4148{
4149 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4150 return;
4151
4152 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4153 kvm_fx_save(&vcpu->arch.host_fx_image);
4154 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4155}
4156EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4157
4158void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4159{
4160 if (!vcpu->guest_fpu_loaded)
4161 return;
4162
4163 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4164 kvm_fx_save(&vcpu->arch.guest_fx_image);
4165 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4166 ++vcpu->stat.fpu_reload;
d0752060
HB		 4167}
4168EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4169
4170void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4171{
7f1ea208
JR		 4172 if (vcpu->arch.time_page) {
4173 kvm_release_page_dirty(vcpu->arch.time_page);
4174 vcpu->arch.time_page = NULL;
4175 }
4176
e9b11c17
ZX		 4177 kvm_x86_ops->vcpu_free(vcpu);
4178}
4179
4180struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4181 unsigned int id)
4182{
26e5215f
AK		 4183 return kvm_x86_ops->vcpu_create(kvm, id);
4184}
e9b11c17 4185
26e5215f
AK		 4186int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4187{
4188 int r;
e9b11c17
ZX		 4189
4190 /* We do fxsave: this must be aligned. */
ad312c7c 4191 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4192
0bed3b56 4193 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4194 vcpu_load(vcpu);
4195 r = kvm_arch_vcpu_reset(vcpu);
4196 if (r == 0)
4197 r = kvm_mmu_setup(vcpu);
4198 vcpu_put(vcpu);
4199 if (r < 0)
4200 goto free_vcpu;
4201
26e5215f 4202 return 0;
e9b11c17
ZX		 4203free_vcpu:
4204 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4205 return r;
e9b11c17
ZX		 4206}
4207
d40ccc62 4208void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4209{
4210 vcpu_load(vcpu);
4211 kvm_mmu_unload(vcpu);
4212 vcpu_put(vcpu);
4213
4214 kvm_x86_ops->vcpu_free(vcpu);
4215}
4216
4217int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4218{
448fa4a9
JK		 4219 vcpu->arch.nmi_pending = false;
4220 vcpu->arch.nmi_injected = false;
4221
42dbaa5a
JK		 4222 vcpu->arch.switch_db_regs = 0;
4223 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4224 vcpu->arch.dr6 = DR6_FIXED_1;
4225 vcpu->arch.dr7 = DR7_FIXED_1;
4226
e9b11c17
ZX		 4227 return kvm_x86_ops->vcpu_reset(vcpu);
4228}
4229
4230void kvm_arch_hardware_enable(void *garbage)
4231{
4232 kvm_x86_ops->hardware_enable(garbage);
4233}
4234
4235void kvm_arch_hardware_disable(void *garbage)
4236{
4237 kvm_x86_ops->hardware_disable(garbage);
4238}
4239
4240int kvm_arch_hardware_setup(void)
4241{
4242 return kvm_x86_ops->hardware_setup();
4243}
4244
4245void kvm_arch_hardware_unsetup(void)
4246{
4247 kvm_x86_ops->hardware_unsetup();
4248}
4249
4250void kvm_arch_check_processor_compat(void *rtn)
4251{
4252 kvm_x86_ops->check_processor_compatibility(rtn);
4253}
4254
4255int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4256{
4257 struct page *page;
4258 struct kvm *kvm;
4259 int r;
4260
4261 BUG_ON(vcpu->kvm == NULL);
4262 kvm = vcpu->kvm;
4263
ad312c7c 4264 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4265 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4266 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4267 else
a4535290 4268 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4269
4270 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4271 if (!page) {
4272 r = -ENOMEM;
4273 goto fail;
4274 }
ad312c7c 4275 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4276
4277 r = kvm_mmu_create(vcpu);
4278 if (r < 0)
4279 goto fail_free_pio_data;
4280
4281 if (irqchip_in_kernel(kvm)) {
4282 r = kvm_create_lapic(vcpu);
4283 if (r < 0)
4284 goto fail_mmu_destroy;
4285 }
4286
4287 return 0;
4288
4289fail_mmu_destroy:
4290 kvm_mmu_destroy(vcpu);
4291fail_free_pio_data:
ad312c7c 4292 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4293fail:
4294 return r;
4295}
4296
4297void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4298{
4299 kvm_free_lapic(vcpu);
3200f405 4300 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4301 kvm_mmu_destroy(vcpu);
3200f405 4302 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4303 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4304}
d19a9cd2
ZX		 4305
4306struct kvm *kvm_arch_create_vm(void)
4307{
4308 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4309
4310 if (!kvm)
4311 return ERR_PTR(-ENOMEM);
4312
f05e70ac 4313 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6cffe8ca 4314 INIT_LIST_HEAD(&kvm->arch.oos_global_pages);
4d5c5d0f 4315 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4316
5550af4d
SY		 4317 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4318 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4319
53f658b3
MT		 4320 rdtscll(kvm->arch.vm_init_tsc);
4321
d19a9cd2
ZX		 4322 return kvm;
4323}
4324
4325static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4326{
4327 vcpu_load(vcpu);
4328 kvm_mmu_unload(vcpu);
4329 vcpu_put(vcpu);
4330}
4331
4332static void kvm_free_vcpus(struct kvm *kvm)
4333{
4334 unsigned int i;
4335
4336 /*
4337 * Unpin any mmu pages first.
4338 */
4339 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4340 if (kvm->vcpus[i])
4341 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4342 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4343 if (kvm->vcpus[i]) {
4344 kvm_arch_vcpu_free(kvm->vcpus[i]);
4345 kvm->vcpus[i] = NULL;
4346 }
4347 }
4348
4349}
4350
ad8ba2cd
SY		 4351void kvm_arch_sync_events(struct kvm *kvm)
4352{
ba4cef31 4353 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4354}
4355
d19a9cd2
ZX		 4356void kvm_arch_destroy_vm(struct kvm *kvm)
4357{
6eb55818 4358 kvm_iommu_unmap_guest(kvm);
7837699f 4359 kvm_free_pit(kvm);
d7deeeb0
ZX		 4360 kfree(kvm->arch.vpic);
4361 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4362 kvm_free_vcpus(kvm);
4363 kvm_free_physmem(kvm);
3d45830c
AK		 4364 if (kvm->arch.apic_access_page)
4365 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4366 if (kvm->arch.ept_identity_pagetable)
4367 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4368 kfree(kvm);
4369}
0de10343
ZX		 4370
4371int kvm_arch_set_memory_region(struct kvm *kvm,
4372 struct kvm_userspace_memory_region *mem,
4373 struct kvm_memory_slot old,
4374 int user_alloc)
4375{
4376 int npages = mem->memory_size >> PAGE_SHIFT;
4377 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4378
4379 /*To keep backward compatibility with older userspace,
4380 *x86 needs to hanlde !user_alloc case.
4381 */
4382 if (!user_alloc) {
4383 if (npages && !old.rmap) {
604b38ac
AA		 4384 unsigned long userspace_addr;
4385
72dc67a6 4386 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4387 userspace_addr = do_mmap(NULL, 0,
4388 npages * PAGE_SIZE,
4389 PROT_READ | PROT_WRITE,
acee3c04 4390 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4391 0);
72dc67a6 4392 up_write(&current->mm->mmap_sem);
0de10343 4393
604b38ac
AA		 4394 if (IS_ERR((void *)userspace_addr))
4395 return PTR_ERR((void *)userspace_addr);
4396
4397 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4398 spin_lock(&kvm->mmu_lock);
4399 memslot->userspace_addr = userspace_addr;
4400 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4401 } else {
4402 if (!old.user_alloc && old.rmap) {
4403 int ret;
4404
72dc67a6 4405 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4406 ret = do_munmap(current->mm, old.userspace_addr,
4407 old.npages * PAGE_SIZE);
72dc67a6 4408 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4409 if (ret < 0)
4410 printk(KERN_WARNING
4411 "kvm_vm_ioctl_set_memory_region: "
4412 "failed to munmap memory\n");
4413 }
4414 }
4415 }
4416
f05e70ac 4417 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4418 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4419 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4420 }
4421
4422 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4423 kvm_flush_remote_tlbs(kvm);
4424
4425 return 0;
4426}
1d737c8a 4427
34d4cb8f
MT		 4428void kvm_arch_flush_shadow(struct kvm *kvm)
4429{
4430 kvm_mmu_zap_all(kvm);
4431}
4432
1d737c8a
ZX		 4433int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4434{
a4535290 4435 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4436 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4437 || vcpu->arch.nmi_pending;
1d737c8a 4438}
5736199a
ZX		 4439
4440static void vcpu_kick_intr(void *info)
4441{
4442#ifdef DEBUG
4443 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4444 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4445#endif
4446}
4447
4448void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4449{
4450 int ipi_pcpu = vcpu->cpu;
e9571ed5 4451 int cpu = get_cpu();
5736199a
ZX		 4452
4453 if (waitqueue_active(&vcpu->wq)) {
4454 wake_up_interruptible(&vcpu->wq);
4455 ++vcpu->stat.halt_wakeup;
4456 }
e9571ed5
MT		 4457 /*
4458 * We may be called synchronously with irqs disabled in guest mode,
4459 * So need not to call smp_call_function_single() in that case.
4460 */
4461 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4462 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4463 put_cpu();
5736199a 4464}
Linux 6.x block layer and io_uring tree(s)