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KVM: x86: fix escape of guest dr6 to the host
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM		 110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
9ed96e87
MT		 113unsigned int min_timer_period_us = 500;
114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT		 116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW		 138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK		 141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY		 151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
188 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
191 { "mmu_flooded", VM_STAT(mmu_flooded) },
192 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 194 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 196 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 197 { "max_mmu_page_hash_collisions",
198 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 199 { NULL }
200};
201
2acf923e
DC		 202u64 __read_mostly host_xcr0;
203
b6785def 204static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 205
af585b92
GN		 206static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
207{
208 int i;
209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
210 vcpu->arch.apf.gfns[i] = ~0;
211}
212
18863bdd
AK		 213static void kvm_on_user_return(struct user_return_notifier *urn)
214{
215 unsigned slot;
18863bdd
AK		 216 struct kvm_shared_msrs *locals
217 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 218 struct kvm_shared_msr_values *values;
1650b4eb
IA		 219 unsigned long flags;
220
221 /*
222 * Disabling irqs at this point since the following code could be
223 * interrupted and executed through kvm_arch_hardware_disable()
224 */
225 local_irq_save(flags);
226 if (locals->registered) {
227 locals->registered = false;
228 user_return_notifier_unregister(urn);
229 }
230 local_irq_restore(flags);
18863bdd 231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 232 values = &locals->values[slot];
233 if (values->host != values->curr) {
234 wrmsrl(shared_msrs_global.msrs[slot], values->host);
235 values->curr = values->host;
18863bdd
AK		 236 }
237 }
18863bdd
AK		 238}
239
2bf78fa7 240static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 241{
18863bdd 242 u64 value;
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 245
2bf78fa7
SY		 246 /* only read, and nobody should modify it at this time,
247 * so don't need lock */
248 if (slot >= shared_msrs_global.nr) {
249 printk(KERN_ERR "kvm: invalid MSR slot!");
250 return;
251 }
252 rdmsrl_safe(msr, &value);
253 smsr->values[slot].host = value;
254 smsr->values[slot].curr = value;
255}
256
257void kvm_define_shared_msr(unsigned slot, u32 msr)
258{
0123be42 259 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 260 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 261 if (slot >= shared_msrs_global.nr)
262 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 263}
264EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
265
266static void kvm_shared_msr_cpu_online(void)
267{
268 unsigned i;
18863bdd
AK		 269
270 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 271 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 272}
273
8b3c3104 274int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 278 int err;
18863bdd 279
2bf78fa7 280 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 281 return 0;
2bf78fa7 282 smsr->values[slot].curr = value;
8b3c3104
AH		 283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
284 if (err)
285 return 1;
286
18863bdd
AK		 287 if (!smsr->registered) {
288 smsr->urn.on_user_return = kvm_on_user_return;
289 user_return_notifier_register(&smsr->urn);
290 smsr->registered = true;
291 }
8b3c3104 292 return 0;
18863bdd
AK		 293}
294EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
295
13a34e06 296static void drop_user_return_notifiers(void)
3548bab5 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 300
301 if (smsr->registered)
302 kvm_on_user_return(&smsr->urn);
303}
304
6866b83e
CO		 305u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
306{
8a5a87d9 307 return vcpu->arch.apic_base;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_get_apic_base);
310
58cb628d
JK		 311int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
312{
313 u64 old_state = vcpu->arch.apic_base &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 new_state = msr_info->data &
316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 319
d3802286
JM		 320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
321 return 1;
58cb628d 322 if (!msr_info->host_initiated &&
d3802286 323 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
326 old_state == 0)))
327 return 1;
328
329 kvm_lapic_set_base(vcpu, msr_info->data);
330 return 0;
6866b83e
CO		 331}
332EXPORT_SYMBOL_GPL(kvm_set_apic_base);
333
2605fc21 334asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 335{
336 /* Fault while not rebooting. We want the trace. */
337 BUG();
338}
339EXPORT_SYMBOL_GPL(kvm_spurious_fault);
340
3fd28fce
ED		 341#define EXCPT_BENIGN 0
342#define EXCPT_CONTRIBUTORY 1
343#define EXCPT_PF 2
344
345static int exception_class(int vector)
346{
347 switch (vector) {
348 case PF_VECTOR:
349 return EXCPT_PF;
350 case DE_VECTOR:
351 case TS_VECTOR:
352 case NP_VECTOR:
353 case SS_VECTOR:
354 case GP_VECTOR:
355 return EXCPT_CONTRIBUTORY;
356 default:
357 break;
358 }
359 return EXCPT_BENIGN;
360}
361
d6e8c854
NA		 362#define EXCPT_FAULT 0
363#define EXCPT_TRAP 1
364#define EXCPT_ABORT 2
365#define EXCPT_INTERRUPT 3
366
367static int exception_type(int vector)
368{
369 unsigned int mask;
370
371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
372 return EXCPT_INTERRUPT;
373
374 mask = 1 << vector;
375
376 /* #DB is trap, as instruction watchpoints are handled elsewhere */
377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
378 return EXCPT_TRAP;
379
380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
381 return EXCPT_ABORT;
382
383 /* Reserved exceptions will result in fault */
384 return EXCPT_FAULT;
385}
386
3fd28fce 387static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 388 unsigned nr, bool has_error, u32 error_code,
389 bool reinject)
3fd28fce
ED		 390{
391 u32 prev_nr;
392 int class1, class2;
393
3842d135
AK		 394 kvm_make_request(KVM_REQ_EVENT, vcpu);
395
664f8e26 396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 397 queue:
3ffb2468
NA		 398 if (has_error && !is_protmode(vcpu))
399 has_error = false;
664f8e26
WL		 400 if (reinject) {
401 /*
402 * On vmentry, vcpu->arch.exception.pending is only
403 * true if an event injection was blocked by
404 * nested_run_pending. In that case, however,
405 * vcpu_enter_guest requests an immediate exit,
406 * and the guest shouldn't proceed far enough to
407 * need reinjection.
408 */
409 WARN_ON_ONCE(vcpu->arch.exception.pending);
410 vcpu->arch.exception.injected = true;
411 } else {
412 vcpu->arch.exception.pending = true;
413 vcpu->arch.exception.injected = false;
414 }
3fd28fce
ED		 415 vcpu->arch.exception.has_error_code = has_error;
416 vcpu->arch.exception.nr = nr;
417 vcpu->arch.exception.error_code = error_code;
418 return;
419 }
420
421 /* to check exception */
422 prev_nr = vcpu->arch.exception.nr;
423 if (prev_nr == DF_VECTOR) {
424 /* triple fault -> shutdown */
a8eeb04a 425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 426 return;
427 }
428 class1 = exception_class(prev_nr);
429 class2 = exception_class(nr);
430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 432 /*
433 * Generate double fault per SDM Table 5-5. Set
434 * exception.pending = true so that the double fault
435 * can trigger a nested vmexit.
436 */
3fd28fce 437 vcpu->arch.exception.pending = true;
664f8e26 438 vcpu->arch.exception.injected = false;
3fd28fce
ED		 439 vcpu->arch.exception.has_error_code = true;
440 vcpu->arch.exception.nr = DF_VECTOR;
441 vcpu->arch.exception.error_code = 0;
442 } else
443 /* replace previous exception with a new one in a hope
444 that instruction re-execution will regenerate lost
445 exception */
446 goto queue;
447}
448
298101da
AK		 449void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
450{
ce7ddec4 451 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 452}
453EXPORT_SYMBOL_GPL(kvm_queue_exception);
454
ce7ddec4
JR		 455void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
456{
457 kvm_multiple_exception(vcpu, nr, false, 0, true);
458}
459EXPORT_SYMBOL_GPL(kvm_requeue_exception);
460
6affcbed 461int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 462{
db8fcefa
AP		 463 if (err)
464 kvm_inject_gp(vcpu, 0);
465 else
6affcbed
KH		 466 return kvm_skip_emulated_instruction(vcpu);
467
468 return 1;
db8fcefa
AP		 469}
470EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 471
6389ee94 472void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 473{
474 ++vcpu->stat.pf_guest;
adfe20fb
WL		 475 vcpu->arch.exception.nested_apf =
476 is_guest_mode(vcpu) && fault->async_page_fault;
477 if (vcpu->arch.exception.nested_apf)
478 vcpu->arch.apf.nested_apf_token = fault->address;
479 else
480 vcpu->arch.cr2 = fault->address;
6389ee94 481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 482}
27d6c865 483EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 484
ef54bcfe 485static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 486{
6389ee94
AK		 487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 489 else
6389ee94 490 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 491
492 return fault->nested_page_fault;
d4f8cf66
JR		 493}
494
3419ffc8
SY		 495void kvm_inject_nmi(struct kvm_vcpu *vcpu)
496{
7460fb4a
AK		 497 atomic_inc(&vcpu->arch.nmi_queued);
498 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 499}
500EXPORT_SYMBOL_GPL(kvm_inject_nmi);
501
298101da
AK		 502void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
503{
ce7ddec4 504 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 505}
506EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
507
ce7ddec4
JR		 508void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
509{
510 kvm_multiple_exception(vcpu, nr, true, error_code, true);
511}
512EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
513
0a79b009
AK		 514/*
515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
516 * a #GP and return false.
517 */
518bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 519{
0a79b009
AK		 520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
521 return true;
522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
523 return false;
298101da 524}
0a79b009 525EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 526
16f8a6f9
NA		 527bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
528{
529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
530 return true;
531
532 kvm_queue_exception(vcpu, UD_VECTOR);
533 return false;
534}
535EXPORT_SYMBOL_GPL(kvm_require_dr);
536
ec92fe44
JR		 537/*
538 * This function will be used to read from the physical memory of the currently
54bf36aa 539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 540 * can read from guest physical or from the guest's guest physical memory.
541 */
542int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
543 gfn_t ngfn, void *data, int offset, int len,
544 u32 access)
545{
54987b7a 546 struct x86_exception exception;
ec92fe44
JR		 547 gfn_t real_gfn;
548 gpa_t ngpa;
549
550 ngpa = gfn_to_gpa(ngfn);
54987b7a 551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 552 if (real_gfn == UNMAPPED_GVA)
553 return -EFAULT;
554
555 real_gfn = gpa_to_gfn(real_gfn);
556
54bf36aa 557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 558}
559EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
560
69b0049a 561static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 562 void *data, int offset, int len, u32 access)
563{
564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
565 data, offset, len, access);
566}
567
a03490ed
CO		 568/*
569 * Load the pae pdptrs. Return true is they are all valid.
570 */
ff03a073 571int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 572{
573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
575 int i;
576 int ret;
ff03a073 577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 578
ff03a073
JR		 579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
580 offset * sizeof(u64), sizeof(pdpte),
581 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 582 if (ret < 0) {
583 ret = 0;
584 goto out;
585 }
586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 587 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 588 (pdpte[i] &
589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 590 ret = 0;
591 goto out;
592 }
593 }
594 ret = 1;
595
ff03a073 596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 597 __set_bit(VCPU_EXREG_PDPTR,
598 (unsigned long *)&vcpu->arch.regs_avail);
599 __set_bit(VCPU_EXREG_PDPTR,
600 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 601out:
a03490ed
CO		 602
603 return ret;
604}
cc4b6871 605EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 606
9ed38ffa 607bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 608{
ff03a073 609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 610 bool changed = true;
3d06b8bf
JR		 611 int offset;
612 gfn_t gfn;
d835dfec
AK		 613 int r;
614
615 if (is_long_mode(vcpu) || !is_pae(vcpu))
616 return false;
617
6de4f3ad
AK		 618 if (!test_bit(VCPU_EXREG_PDPTR,
619 (unsigned long *)&vcpu->arch.regs_avail))
620 return true;
621
a512177e
PB		 622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
625 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 626 if (r < 0)
627 goto out;
ff03a073 628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 629out:
d835dfec
AK		 630
631 return changed;
632}
9ed38ffa 633EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 634
49a9b07e 635int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 636{
aad82703 637 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 639
f9a48e6a
AK		 640 cr0 |= X86_CR0_ET;
641
ab344828 642#ifdef CONFIG_X86_64
0f12244f
GN		 643 if (cr0 & 0xffffffff00000000UL)
644 return 1;
ab344828
GN		 645#endif
646
647 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
650 return 1;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
653 return 1;
a03490ed
CO		 654
655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
656#ifdef CONFIG_X86_64
f6801dff 657 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 658 int cs_db, cs_l;
659
0f12244f
GN		 660 if (!is_pae(vcpu))
661 return 1;
a03490ed 662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 663 if (cs_l)
664 return 1;
a03490ed
CO		 665 } else
666#endif
ff03a073 667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 668 kvm_read_cr3(vcpu)))
0f12244f 669 return 1;
a03490ed
CO		 670 }
671
ad756a16
MJ		 672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
673 return 1;
674
a03490ed 675 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 676
d170c419 677 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 678 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 679 kvm_async_pf_hash_reset(vcpu);
680 }
e5f3f027 681
aad82703
SY		 682 if ((cr0 ^ old_cr0) & update_bits)
683 kvm_mmu_reset_context(vcpu);
b18d5431 684
879ae188
LE		 685 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
686 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
689
0f12244f
GN		 690 return 0;
691}
2d3ad1f4 692EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 693
2d3ad1f4 694void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 695{
49a9b07e 696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 697}
2d3ad1f4 698EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 699
42bdf991
MT		 700static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
701{
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
703 !vcpu->guest_xcr0_loaded) {
704 /* kvm_set_xcr() also depends on this */
705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
706 vcpu->guest_xcr0_loaded = 1;
707 }
708}
709
710static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (vcpu->guest_xcr0_loaded) {
713 if (vcpu->arch.xcr0 != host_xcr0)
714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
715 vcpu->guest_xcr0_loaded = 0;
716 }
717}
718
69b0049a 719static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 720{
56c103ec
LJ		 721 u64 xcr0 = xcr;
722 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 723 u64 valid_bits;
2acf923e
DC		 724
725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
726 if (index != XCR_XFEATURE_ENABLED_MASK)
727 return 1;
d91cab78 728 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 729 return 1;
d91cab78 730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 731 return 1;
46c34cb0
PB		 732
733 /*
734 * Do not allow the guest to set bits that we do not support
735 * saving. However, xcr0 bit 0 is always set, even if the
736 * emulated CPU does not support XSAVE (see fx_init).
737 */
d91cab78 738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 739 if (xcr0 & ~valid_bits)
2acf923e 740 return 1;
46c34cb0 741
d91cab78
DH		 742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
743 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 744 return 1;
745
d91cab78
DH		 746 if (xcr0 & XFEATURE_MASK_AVX512) {
747 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 748 return 1;
d91cab78 749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 750 return 1;
751 }
2acf923e 752 vcpu->arch.xcr0 = xcr0;
56c103ec 753
d91cab78 754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 755 kvm_update_cpuid(vcpu);
2acf923e
DC		 756 return 0;
757}
758
759int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
760{
764bcbc5
Z		 761 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
762 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 763 kvm_inject_gp(vcpu, 0);
764 return 1;
765 }
766 return 0;
767}
768EXPORT_SYMBOL_GPL(kvm_set_xcr);
769
a83b29c6 770int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 771{
fc78f519 772 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 775
0f12244f
GN		 776 if (cr4 & CR4_RESERVED_BITS)
777 return 1;
a03490ed 778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 789 return 1;
790
d6321d49 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 792 return 1;
793
fd8cb433 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 795 return 1;
796
ae3e61e1
PB		 797 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
798 return 1;
799
a03490ed 800 if (is_long_mode(vcpu)) {
0f12244f
GN		 801 if (!(cr4 & X86_CR4_PAE))
802 return 1;
a2edf57f
AK		 803 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
804 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 805 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
806 kvm_read_cr3(vcpu)))
0f12244f
GN		 807 return 1;
808
ad756a16 809 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 810 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 811 return 1;
812
813 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
814 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
815 return 1;
816 }
817
5e1746d6 818 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 819 return 1;
a03490ed 820
ad756a16
MJ		 821 if (((cr4 ^ old_cr4) & pdptr_bits) ||
822 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 823 kvm_mmu_reset_context(vcpu);
0f12244f 824
b9baba86 825 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 826 kvm_update_cpuid(vcpu);
2acf923e 827
0f12244f
GN		 828 return 0;
829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 831
2390218b 832int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 833{
ac146235 834#ifdef CONFIG_X86_64
9d88fca7 835 cr3 &= ~CR3_PCID_INVD;
ac146235 836#endif
9d88fca7 837
9f8fe504 838 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 839 kvm_mmu_sync_roots(vcpu);
77c3913b 840 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 841 return 0;
d835dfec
AK		 842 }
843
d1cd3ce9
YZ		 844 if (is_long_mode(vcpu) &&
845 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
846 return 1;
847 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 848 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 849 return 1;
a03490ed 850
0f12244f 851 vcpu->arch.cr3 = cr3;
aff48baa 852 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 853 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 854 return 0;
855}
2d3ad1f4 856EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 857
eea1cff9 858int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 859{
0f12244f
GN		 860 if (cr8 & CR8_RESERVED_BITS)
861 return 1;
35754c98 862 if (lapic_in_kernel(vcpu))
a03490ed
CO		 863 kvm_lapic_set_tpr(vcpu, cr8);
864 else
ad312c7c 865 vcpu->arch.cr8 = cr8;
0f12244f
GN		 866 return 0;
867}
2d3ad1f4 868EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 869
2d3ad1f4 870unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 871{
35754c98 872 if (lapic_in_kernel(vcpu))
a03490ed
CO		 873 return kvm_lapic_get_cr8(vcpu);
874 else
ad312c7c 875 return vcpu->arch.cr8;
a03490ed 876}
2d3ad1f4 877EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 878
ae561ede
NA		 879static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
880{
881 int i;
882
883 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
884 for (i = 0; i < KVM_NR_DB_REGS; i++)
885 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
886 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
887 }
888}
889
73aaf249
JK		 890static void kvm_update_dr6(struct kvm_vcpu *vcpu)
891{
892 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
893 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
894}
895
c8639010
JK		 896static void kvm_update_dr7(struct kvm_vcpu *vcpu)
897{
898 unsigned long dr7;
899
900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
901 dr7 = vcpu->arch.guest_debug_dr7;
902 else
903 dr7 = vcpu->arch.dr7;
904 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 905 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
906 if (dr7 & DR7_BP_EN_MASK)
907 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 908}
909
6f43ed01
NA		 910static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
911{
912 u64 fixed = DR6_FIXED_1;
913
d6321d49 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 915 fixed |= DR6_RTM;
916 return fixed;
917}
918
338dbc97 919static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 920{
921 switch (dr) {
922 case 0 ... 3:
923 vcpu->arch.db[dr] = val;
924 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
925 vcpu->arch.eff_db[dr] = val;
926 break;
927 case 4:
020df079
GN		 928 /* fall through */
929 case 6:
338dbc97
GN		 930 if (val & 0xffffffff00000000ULL)
931 return -1; /* #GP */
6f43ed01 932 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 933 kvm_update_dr6(vcpu);
020df079
GN		 934 break;
935 case 5:
020df079
GN		 936 /* fall through */
937 default: /* 7 */
338dbc97
GN		 938 if (val & 0xffffffff00000000ULL)
939 return -1; /* #GP */
020df079 940 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 941 kvm_update_dr7(vcpu);
020df079
GN		 942 break;
943 }
944
945 return 0;
946}
338dbc97
GN		 947
948int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
949{
16f8a6f9 950 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 951 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 952 return 1;
953 }
954 return 0;
338dbc97 955}
020df079
GN		 956EXPORT_SYMBOL_GPL(kvm_set_dr);
957
16f8a6f9 958int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 959{
960 switch (dr) {
961 case 0 ... 3:
962 *val = vcpu->arch.db[dr];
963 break;
964 case 4:
020df079
GN		 965 /* fall through */
966 case 6:
73aaf249
JK		 967 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
968 *val = vcpu->arch.dr6;
969 else
970 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 971 break;
972 case 5:
020df079
GN		 973 /* fall through */
974 default: /* 7 */
975 *val = vcpu->arch.dr7;
976 break;
977 }
338dbc97
GN		 978 return 0;
979}
020df079
GN		 980EXPORT_SYMBOL_GPL(kvm_get_dr);
981
022cd0e8
AK		 982bool kvm_rdpmc(struct kvm_vcpu *vcpu)
983{
984 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
985 u64 data;
986 int err;
987
c6702c9d 988 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 989 if (err)
990 return err;
991 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
992 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
993 return err;
994}
995EXPORT_SYMBOL_GPL(kvm_rdpmc);
996
043405e1
CO		 997/*
998 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
999 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1000 *
1001 * This list is modified at module load time to reflect the
e3267cbb 1002 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1003 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1004 * may depend on host virtualization features rather than host cpu features.
043405e1 1005 */
e3267cbb 1006
043405e1
CO		 1007static u32 msrs_to_save[] = {
1008 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1009 MSR_STAR,
043405e1
CO		 1010#ifdef CONFIG_X86_64
1011 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1012#endif
b3897a49 1013 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1014 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1015};
1016
1017static unsigned num_msrs_to_save;
1018
62ef68bb
PB		 1019static u32 emulated_msrs[] = {
1020 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1021 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1022 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1023 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1024 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1025 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1026 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1027 HV_X64_MSR_RESET,
11c4b1ca 1028 HV_X64_MSR_VP_INDEX,
9eec50b8 1029 HV_X64_MSR_VP_RUNTIME,
5c919412 1030 HV_X64_MSR_SCONTROL,
1f4b34f8 1031 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1032 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1033 MSR_KVM_PV_EOI_EN,
1034
ba904635 1035 MSR_IA32_TSC_ADJUST,
a3e06bbe 1036 MSR_IA32_TSCDEADLINE,
043405e1 1037 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1038 MSR_IA32_MCG_STATUS,
1039 MSR_IA32_MCG_CTL,
c45dcc71 1040 MSR_IA32_MCG_EXT_CTL,
64d60670 1041 MSR_IA32_SMBASE,
52797bf9 1042 MSR_SMI_COUNT,
db2336a8
KH		 1043 MSR_PLATFORM_INFO,
1044 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1045};
1046
62ef68bb
PB		 1047static unsigned num_emulated_msrs;
1048
384bb783 1049bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1050{
b69e8cae 1051 if (efer & efer_reserved_bits)
384bb783 1052 return false;
15c4a640 1053
1b4d56b8 1054 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1055 return false;
1b2fd70c 1056
1b4d56b8 1057 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1058 return false;
d8017474 1059
384bb783
JK		 1060 return true;
1061}
1062EXPORT_SYMBOL_GPL(kvm_valid_efer);
1063
1064static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1065{
1066 u64 old_efer = vcpu->arch.efer;
1067
1068 if (!kvm_valid_efer(vcpu, efer))
1069 return 1;
1070
1071 if (is_paging(vcpu)
1072 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1073 return 1;
1074
15c4a640 1075 efer &= ~EFER_LMA;
f6801dff 1076 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1077
a3d204e2
SY		 1078 kvm_x86_ops->set_efer(vcpu, efer);
1079
aad82703
SY		 1080 /* Update reserved bits */
1081 if ((efer ^ old_efer) & EFER_NX)
1082 kvm_mmu_reset_context(vcpu);
1083
b69e8cae 1084 return 0;
15c4a640
CO		 1085}
1086
f2b4b7dd
JR		 1087void kvm_enable_efer_bits(u64 mask)
1088{
1089 efer_reserved_bits &= ~mask;
1090}
1091EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1092
15c4a640
CO		 1093/*
1094 * Writes msr value into into the appropriate "register".
1095 * Returns 0 on success, non-0 otherwise.
1096 * Assumes vcpu_load() was already called.
1097 */
8fe8ab46 1098int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1099{
854e8bb1
NA		 1100 switch (msr->index) {
1101 case MSR_FS_BASE:
1102 case MSR_GS_BASE:
1103 case MSR_KERNEL_GS_BASE:
1104 case MSR_CSTAR:
1105 case MSR_LSTAR:
fd8cb433 1106 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1107 return 1;
1108 break;
1109 case MSR_IA32_SYSENTER_EIP:
1110 case MSR_IA32_SYSENTER_ESP:
1111 /*
1112 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1113 * non-canonical address is written on Intel but not on
1114 * AMD (which ignores the top 32-bits, because it does
1115 * not implement 64-bit SYSENTER).
1116 *
1117 * 64-bit code should hence be able to write a non-canonical
1118 * value on AMD. Making the address canonical ensures that
1119 * vmentry does not fail on Intel after writing a non-canonical
1120 * value, and that something deterministic happens if the guest
1121 * invokes 64-bit SYSENTER.
1122 */
fd8cb433 1123 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1124 }
8fe8ab46 1125 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1126}
854e8bb1 1127EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1128
313a3dc7
CO		 1129/*
1130 * Adapt set_msr() to msr_io()'s calling convention
1131 */
609e36d3
PB		 1132static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1133{
1134 struct msr_data msr;
1135 int r;
1136
1137 msr.index = index;
1138 msr.host_initiated = true;
1139 r = kvm_get_msr(vcpu, &msr);
1140 if (r)
1141 return r;
1142
1143 *data = msr.data;
1144 return 0;
1145}
1146
313a3dc7
CO		 1147static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1148{
8fe8ab46
WA		 1149 struct msr_data msr;
1150
1151 msr.data = *data;
1152 msr.index = index;
1153 msr.host_initiated = true;
1154 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1155}
1156
16e8d74d
MT		 1157#ifdef CONFIG_X86_64
1158struct pvclock_gtod_data {
1159 seqcount_t seq;
1160
1161 struct { /* extract of a clocksource struct */
1162 int vclock_mode;
a5a1d1c2
TG		 1163 u64 cycle_last;
1164 u64 mask;
16e8d74d
MT		 1165 u32 mult;
1166 u32 shift;
1167 } clock;
1168
cbcf2dd3
TG		 1169 u64 boot_ns;
1170 u64 nsec_base;
55dd00a7 1171 u64 wall_time_sec;
16e8d74d
MT		 1172};
1173
1174static struct pvclock_gtod_data pvclock_gtod_data;
1175
1176static void update_pvclock_gtod(struct timekeeper *tk)
1177{
1178 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1179 u64 boot_ns;
1180
876e7881 1181 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1182
1183 write_seqcount_begin(&vdata->seq);
1184
1185 /* copy pvclock gtod data */
876e7881
PZ		 1186 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1187 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1188 vdata->clock.mask = tk->tkr_mono.mask;
1189 vdata->clock.mult = tk->tkr_mono.mult;
1190 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1191
cbcf2dd3 1192 vdata->boot_ns = boot_ns;
876e7881 1193 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1194
55dd00a7
MT		 1195 vdata->wall_time_sec = tk->xtime_sec;
1196
16e8d74d
MT		 1197 write_seqcount_end(&vdata->seq);
1198}
1199#endif
1200
bab5bb39
NK		 1201void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1202{
1203 /*
1204 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1205 * vcpu_enter_guest. This function is only called from
1206 * the physical CPU that is running vcpu.
1207 */
1208 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1209}
16e8d74d 1210
18068523
GOC		 1211static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1212{
9ed3c444
AK		 1213 int version;
1214 int r;
50d0a0f9 1215 struct pvclock_wall_clock wc;
87aeb54f 1216 struct timespec64 boot;
18068523
GOC		 1217
1218 if (!wall_clock)
1219 return;
1220
9ed3c444
AK		 1221 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1222 if (r)
1223 return;
1224
1225 if (version & 1)
1226 ++version; /* first time write, random junk */
1227
1228 ++version;
18068523 1229
1dab1345
NK		 1230 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1231 return;
18068523 1232
50d0a0f9
GH		 1233 /*
1234 * The guest calculates current wall clock time by adding
34c238a1 1235 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1236 * wall clock specified here. guest system time equals host
1237 * system time for us, thus we must fill in host boot time here.
1238 */
87aeb54f 1239 getboottime64(&boot);
50d0a0f9 1240
4b648665 1241 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1242 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1243 boot = timespec64_sub(boot, ts);
4b648665 1244 }
87aeb54f 1245 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1246 wc.nsec = boot.tv_nsec;
1247 wc.version = version;
18068523
GOC		 1248
1249 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1250
1251 version++;
1252 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1253}
1254
50d0a0f9
GH		 1255static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1256{
b51012de
PB		 1257 do_shl32_div32(dividend, divisor);
1258 return dividend;
50d0a0f9
GH		 1259}
1260
3ae13faa 1261static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1262 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1263{
5f4e3f88 1264 uint64_t scaled64;
50d0a0f9
GH		 1265 int32_t shift = 0;
1266 uint64_t tps64;
1267 uint32_t tps32;
1268
3ae13faa
PB		 1269 tps64 = base_hz;
1270 scaled64 = scaled_hz;
50933623 1271 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1272 tps64 >>= 1;
1273 shift--;
1274 }
1275
1276 tps32 = (uint32_t)tps64;
50933623
JK		 1277 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1278 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1279 scaled64 >>= 1;
1280 else
1281 tps32 <<= 1;
50d0a0f9
GH		 1282 shift++;
1283 }
1284
5f4e3f88
ZA		 1285 *pshift = shift;
1286 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1287
3ae13faa
PB		 1288 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1289 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1290}
1291
d828199e 1292#ifdef CONFIG_X86_64
16e8d74d 1293static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1294#endif
16e8d74d 1295
c8076604 1296static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1297static unsigned long max_tsc_khz;
c8076604 1298
cc578287 1299static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1300{
cc578287
ZA		 1301 u64 v = (u64)khz * (1000000 + ppm);
1302 do_div(v, 1000000);
1303 return v;
1e993611
JR		 1304}
1305
381d585c
HZ		 1306static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1307{
1308 u64 ratio;
1309
1310 /* Guest TSC same frequency as host TSC? */
1311 if (!scale) {
1312 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1313 return 0;
1314 }
1315
1316 /* TSC scaling supported? */
1317 if (!kvm_has_tsc_control) {
1318 if (user_tsc_khz > tsc_khz) {
1319 vcpu->arch.tsc_catchup = 1;
1320 vcpu->arch.tsc_always_catchup = 1;
1321 return 0;
1322 } else {
1323 WARN(1, "user requested TSC rate below hardware speed\n");
1324 return -1;
1325 }
1326 }
1327
1328 /* TSC scaling required - calculate ratio */
1329 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1330 user_tsc_khz, tsc_khz);
1331
1332 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1333 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1334 user_tsc_khz);
1335 return -1;
1336 }
1337
1338 vcpu->arch.tsc_scaling_ratio = ratio;
1339 return 0;
1340}
1341
4941b8cb 1342static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1343{
cc578287
ZA		 1344 u32 thresh_lo, thresh_hi;
1345 int use_scaling = 0;
217fc9cf 1346
03ba32ca 1347 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1348 if (user_tsc_khz == 0) {
ad721883
HZ		 1349 /* set tsc_scaling_ratio to a safe value */
1350 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1351 return -1;
ad721883 1352 }
03ba32ca 1353
c285545f 1354 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1355 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1356 &vcpu->arch.virtual_tsc_shift,
1357 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1358 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1359
1360 /*
1361 * Compute the variation in TSC rate which is acceptable
1362 * within the range of tolerance and decide if the
1363 * rate being applied is within that bounds of the hardware
1364 * rate. If so, no scaling or compensation need be done.
1365 */
1366 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1367 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1368 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1369 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1370 use_scaling = 1;
1371 }
4941b8cb 1372 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1373}
1374
1375static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1376{
e26101b1 1377 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1378 vcpu->arch.virtual_tsc_mult,
1379 vcpu->arch.virtual_tsc_shift);
e26101b1 1380 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1381 return tsc;
1382}
1383
69b0049a 1384static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1385{
1386#ifdef CONFIG_X86_64
1387 bool vcpus_matched;
b48aa97e
MT		 1388 struct kvm_arch *ka = &vcpu->kvm->arch;
1389 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1390
1391 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1392 atomic_read(&vcpu->kvm->online_vcpus));
1393
7f187922
MT		 1394 /*
1395 * Once the masterclock is enabled, always perform request in
1396 * order to update it.
1397 *
1398 * In order to enable masterclock, the host clocksource must be TSC
1399 * and the vcpus need to have matched TSCs. When that happens,
1400 * perform request to enable masterclock.
1401 */
1402 if (ka->use_master_clock ||
1403 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1404 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1405
1406 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1407 atomic_read(&vcpu->kvm->online_vcpus),
1408 ka->use_master_clock, gtod->clock.vclock_mode);
1409#endif
1410}
1411
ba904635
WA		 1412static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1413{
3e3f5026 1414 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1415 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1416}
1417
35181e86
HZ		 1418/*
1419 * Multiply tsc by a fixed point number represented by ratio.
1420 *
1421 * The most significant 64-N bits (mult) of ratio represent the
1422 * integral part of the fixed point number; the remaining N bits
1423 * (frac) represent the fractional part, ie. ratio represents a fixed
1424 * point number (mult + frac * 2^(-N)).
1425 *
1426 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1427 */
1428static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1429{
1430 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1431}
1432
1433u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1434{
1435 u64 _tsc = tsc;
1436 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1437
1438 if (ratio != kvm_default_tsc_scaling_ratio)
1439 _tsc = __scale_tsc(ratio, tsc);
1440
1441 return _tsc;
1442}
1443EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1444
07c1419a
HZ		 1445static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1446{
1447 u64 tsc;
1448
1449 tsc = kvm_scale_tsc(vcpu, rdtsc());
1450
1451 return target_tsc - tsc;
1452}
1453
4ba76538
HZ		 1454u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1455{
ea26e4ec 1456 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1457}
1458EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1459
a545ab6a
LC		 1460static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1461{
1462 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1463 vcpu->arch.tsc_offset = offset;
1464}
1465
8fe8ab46 1466void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1467{
1468 struct kvm *kvm = vcpu->kvm;
f38e098f 1469 u64 offset, ns, elapsed;
99e3e30a 1470 unsigned long flags;
b48aa97e 1471 bool matched;
0d3da0d2 1472 bool already_matched;
8fe8ab46 1473 u64 data = msr->data;
c5e8ec8e 1474 bool synchronizing = false;
99e3e30a 1475
038f8c11 1476 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1477 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1478 ns = ktime_get_boot_ns();
f38e098f 1479 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1480
03ba32ca 1481 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1482 if (data == 0 && msr->host_initiated) {
1483 /*
1484 * detection of vcpu initialization -- need to sync
1485 * with other vCPUs. This particularly helps to keep
1486 * kvm_clock stable after CPU hotplug
1487 */
1488 synchronizing = true;
1489 } else {
1490 u64 tsc_exp = kvm->arch.last_tsc_write +
1491 nsec_to_cycles(vcpu, elapsed);
1492 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1493 /*
1494 * Special case: TSC write with a small delta (1 second)
1495 * of virtual cycle time against real time is
1496 * interpreted as an attempt to synchronize the CPU.
1497 */
1498 synchronizing = data < tsc_exp + tsc_hz &&
1499 data + tsc_hz > tsc_exp;
1500 }
c5e8ec8e 1501 }
f38e098f
ZA		 1502
1503 /*
5d3cb0f6
ZA		 1504 * For a reliable TSC, we can match TSC offsets, and for an unstable
1505 * TSC, we add elapsed time in this computation. We could let the
1506 * compensation code attempt to catch up if we fall behind, but
1507 * it's better to try to match offsets from the beginning.
1508 */
c5e8ec8e 1509 if (synchronizing &&
5d3cb0f6 1510 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1511 if (!check_tsc_unstable()) {
e26101b1 1512 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1513 pr_debug("kvm: matched tsc offset for %llu\n", data);
1514 } else {
857e4099 1515 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1516 data += delta;
07c1419a 1517 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1518 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1519 }
b48aa97e 1520 matched = true;
0d3da0d2 1521 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1522 } else {
1523 /*
1524 * We split periods of matched TSC writes into generations.
1525 * For each generation, we track the original measured
1526 * nanosecond time, offset, and write, so if TSCs are in
1527 * sync, we can match exact offset, and if not, we can match
4a969980 1528 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1529 *
1530 * These values are tracked in kvm->arch.cur_xxx variables.
1531 */
1532 kvm->arch.cur_tsc_generation++;
1533 kvm->arch.cur_tsc_nsec = ns;
1534 kvm->arch.cur_tsc_write = data;
1535 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1536 matched = false;
0d3da0d2 1537 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1538 kvm->arch.cur_tsc_generation, data);
f38e098f 1539 }
e26101b1
ZA		 1540
1541 /*
1542 * We also track th most recent recorded KHZ, write and time to
1543 * allow the matching interval to be extended at each write.
1544 */
f38e098f
ZA		 1545 kvm->arch.last_tsc_nsec = ns;
1546 kvm->arch.last_tsc_write = data;
5d3cb0f6 1547 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1548
b183aa58 1549 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1550
1551 /* Keep track of which generation this VCPU has synchronized to */
1552 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1553 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1554 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1555
d6321d49 1556 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1557 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1558
a545ab6a 1559 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1560 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1561
1562 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1563 if (!matched) {
b48aa97e 1564 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1565 } else if (!already_matched) {
1566 kvm->arch.nr_vcpus_matched_tsc++;
1567 }
b48aa97e
MT		 1568
1569 kvm_track_tsc_matching(vcpu);
1570 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1571}
e26101b1 1572
99e3e30a
ZA		 1573EXPORT_SYMBOL_GPL(kvm_write_tsc);
1574
58ea6767
HZ		 1575static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1576 s64 adjustment)
1577{
ea26e4ec 1578 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1579}
1580
1581static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1582{
1583 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1584 WARN_ON(adjustment < 0);
1585 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1586 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1587}
1588
d828199e
MT		 1589#ifdef CONFIG_X86_64
1590
a5a1d1c2 1591static u64 read_tsc(void)
d828199e 1592{
a5a1d1c2 1593 u64 ret = (u64)rdtsc_ordered();
03b9730b 1594 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1595
1596 if (likely(ret >= last))
1597 return ret;
1598
1599 /*
1600 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1601 * predictable (it's just a function of time and the likely is
d828199e
MT		 1602 * very likely) and there's a data dependence, so force GCC
1603 * to generate a branch instead. I don't barrier() because
1604 * we don't actually need a barrier, and if this function
1605 * ever gets inlined it will generate worse code.
1606 */
1607 asm volatile ("");
1608 return last;
1609}
1610
a5a1d1c2 1611static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1612{
1613 long v;
1614 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1615
1616 *cycle_now = read_tsc();
1617
1618 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1619 return v * gtod->clock.mult;
1620}
1621
a5a1d1c2 1622static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1623{
cbcf2dd3 1624 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1625 unsigned long seq;
d828199e 1626 int mode;
cbcf2dd3 1627 u64 ns;
d828199e 1628
d828199e
MT		 1629 do {
1630 seq = read_seqcount_begin(&gtod->seq);
1631 mode = gtod->clock.vclock_mode;
cbcf2dd3 1632 ns = gtod->nsec_base;
d828199e
MT		 1633 ns += vgettsc(cycle_now);
1634 ns >>= gtod->clock.shift;
cbcf2dd3 1635 ns += gtod->boot_ns;
d828199e 1636 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1637 *t = ns;
d828199e
MT		 1638
1639 return mode;
1640}
1641
55dd00a7
MT		 1642static int do_realtime(struct timespec *ts, u64 *cycle_now)
1643{
1644 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1645 unsigned long seq;
1646 int mode;
1647 u64 ns;
1648
1649 do {
1650 seq = read_seqcount_begin(&gtod->seq);
1651 mode = gtod->clock.vclock_mode;
1652 ts->tv_sec = gtod->wall_time_sec;
1653 ns = gtod->nsec_base;
1654 ns += vgettsc(cycle_now);
1655 ns >>= gtod->clock.shift;
1656 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1657
1658 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1659 ts->tv_nsec = ns;
1660
1661 return mode;
1662}
1663
d828199e 1664/* returns true if host is using tsc clocksource */
a5a1d1c2 1665static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1666{
d828199e
MT		 1667 /* checked again under seqlock below */
1668 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1669 return false;
1670
cbcf2dd3 1671 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1672}
55dd00a7
MT		 1673
1674/* returns true if host is using tsc clocksource */
1675static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1676 u64 *cycle_now)
1677{
1678 /* checked again under seqlock below */
1679 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1680 return false;
1681
1682 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1683}
d828199e
MT		 1684#endif
1685
1686/*
1687 *
b48aa97e
MT		 1688 * Assuming a stable TSC across physical CPUS, and a stable TSC
1689 * across virtual CPUs, the following condition is possible.
1690 * Each numbered line represents an event visible to both
d828199e
MT		 1691 * CPUs at the next numbered event.
1692 *
1693 * "timespecX" represents host monotonic time. "tscX" represents
1694 * RDTSC value.
1695 *
1696 * VCPU0 on CPU0 | VCPU1 on CPU1
1697 *
1698 * 1. read timespec0,tsc0
1699 * 2. | timespec1 = timespec0 + N
1700 * | tsc1 = tsc0 + M
1701 * 3. transition to guest | transition to guest
1702 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1703 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1704 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1705 *
1706 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1707 *
1708 * - ret0 < ret1
1709 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1710 * ...
1711 * - 0 < N - M => M < N
1712 *
1713 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1714 * always the case (the difference between two distinct xtime instances
1715 * might be smaller then the difference between corresponding TSC reads,
1716 * when updating guest vcpus pvclock areas).
1717 *
1718 * To avoid that problem, do not allow visibility of distinct
1719 * system_timestamp/tsc_timestamp values simultaneously: use a master
1720 * copy of host monotonic time values. Update that master copy
1721 * in lockstep.
1722 *
b48aa97e 1723 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1724 *
1725 */
1726
1727static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1728{
1729#ifdef CONFIG_X86_64
1730 struct kvm_arch *ka = &kvm->arch;
1731 int vclock_mode;
b48aa97e
MT		 1732 bool host_tsc_clocksource, vcpus_matched;
1733
1734 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1735 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1736
1737 /*
1738 * If the host uses TSC clock, then passthrough TSC as stable
1739 * to the guest.
1740 */
b48aa97e 1741 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1742 &ka->master_kernel_ns,
1743 &ka->master_cycle_now);
1744
16a96021 1745 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1746 && !ka->backwards_tsc_observed
54750f2c 1747 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1748
d828199e
MT		 1749 if (ka->use_master_clock)
1750 atomic_set(&kvm_guest_has_master_clock, 1);
1751
1752 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1753 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1754 vcpus_matched);
d828199e
MT		 1755#endif
1756}
1757
2860c4b1
PB		 1758void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1759{
1760 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1761}
1762
2e762ff7
MT		 1763static void kvm_gen_update_masterclock(struct kvm *kvm)
1764{
1765#ifdef CONFIG_X86_64
1766 int i;
1767 struct kvm_vcpu *vcpu;
1768 struct kvm_arch *ka = &kvm->arch;
1769
1770 spin_lock(&ka->pvclock_gtod_sync_lock);
1771 kvm_make_mclock_inprogress_request(kvm);
1772 /* no guest entries from this point */
1773 pvclock_update_vm_gtod_copy(kvm);
1774
1775 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1776 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1777
1778 /* guest entries allowed */
1779 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1780 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1781
1782 spin_unlock(&ka->pvclock_gtod_sync_lock);
1783#endif
1784}
1785
e891a32e 1786u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1787{
108b249c 1788 struct kvm_arch *ka = &kvm->arch;
8b953440 1789 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1790 u64 ret;
108b249c 1791
8b953440
PB		 1792 spin_lock(&ka->pvclock_gtod_sync_lock);
1793 if (!ka->use_master_clock) {
1794 spin_unlock(&ka->pvclock_gtod_sync_lock);
1795 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1796 }
1797
8b953440
PB		 1798 hv_clock.tsc_timestamp = ka->master_cycle_now;
1799 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1800 spin_unlock(&ka->pvclock_gtod_sync_lock);
1801
e2c2206a
WL		 1802 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1803 get_cpu();
1804
e70b57a6
WL		 1805 if (__this_cpu_read(cpu_tsc_khz)) {
1806 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1807 &hv_clock.tsc_shift,
1808 &hv_clock.tsc_to_system_mul);
1809 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1810 } else
1811 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1812
1813 put_cpu();
1814
1815 return ret;
108b249c
PB		 1816}
1817
0d6dd2ff
PB		 1818static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1819{
1820 struct kvm_vcpu_arch *vcpu = &v->arch;
1821 struct pvclock_vcpu_time_info guest_hv_clock;
1822
4e335d9e 1823 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1824 &guest_hv_clock, sizeof(guest_hv_clock))))
1825 return;
1826
1827 /* This VCPU is paused, but it's legal for a guest to read another
1828 * VCPU's kvmclock, so we really have to follow the specification where
1829 * it says that version is odd if data is being modified, and even after
1830 * it is consistent.
1831 *
1832 * Version field updates must be kept separate. This is because
1833 * kvm_write_guest_cached might use a "rep movs" instruction, and
1834 * writes within a string instruction are weakly ordered. So there
1835 * are three writes overall.
1836 *
1837 * As a small optimization, only write the version field in the first
1838 * and third write. The vcpu->pv_time cache is still valid, because the
1839 * version field is the first in the struct.
1840 */
1841 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1842
51c4b8bb
LA		 1843 if (guest_hv_clock.version & 1)
1844 ++guest_hv_clock.version; /* first time write, random junk */
1845
0d6dd2ff 1846 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1847 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1848 &vcpu->hv_clock,
1849 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1850
1851 smp_wmb();
1852
1853 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1854 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1855
1856 if (vcpu->pvclock_set_guest_stopped_request) {
1857 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1858 vcpu->pvclock_set_guest_stopped_request = false;
1859 }
1860
1861 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1862
4e335d9e
PB		 1863 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1864 &vcpu->hv_clock,
1865 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1866
1867 smp_wmb();
1868
1869 vcpu->hv_clock.version++;
4e335d9e
PB		 1870 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1871 &vcpu->hv_clock,
1872 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1873}
1874
34c238a1 1875static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1876{
78db6a50 1877 unsigned long flags, tgt_tsc_khz;
18068523 1878 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1879 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1880 s64 kernel_ns;
d828199e 1881 u64 tsc_timestamp, host_tsc;
51d59c6b 1882 u8 pvclock_flags;
d828199e
MT		 1883 bool use_master_clock;
1884
1885 kernel_ns = 0;
1886 host_tsc = 0;
18068523 1887
d828199e
MT		 1888 /*
1889 * If the host uses TSC clock, then passthrough TSC as stable
1890 * to the guest.
1891 */
1892 spin_lock(&ka->pvclock_gtod_sync_lock);
1893 use_master_clock = ka->use_master_clock;
1894 if (use_master_clock) {
1895 host_tsc = ka->master_cycle_now;
1896 kernel_ns = ka->master_kernel_ns;
1897 }
1898 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1899
1900 /* Keep irq disabled to prevent changes to the clock */
1901 local_irq_save(flags);
78db6a50
PB		 1902 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1903 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1904 local_irq_restore(flags);
1905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1906 return 1;
1907 }
d828199e 1908 if (!use_master_clock) {
4ea1636b 1909 host_tsc = rdtsc();
108b249c 1910 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1911 }
1912
4ba76538 1913 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1914
c285545f
ZA		 1915 /*
1916 * We may have to catch up the TSC to match elapsed wall clock
1917 * time for two reasons, even if kvmclock is used.
1918 * 1) CPU could have been running below the maximum TSC rate
1919 * 2) Broken TSC compensation resets the base at each VCPU
1920 * entry to avoid unknown leaps of TSC even when running
1921 * again on the same CPU. This may cause apparent elapsed
1922 * time to disappear, and the guest to stand still or run
1923 * very slowly.
1924 */
1925 if (vcpu->tsc_catchup) {
1926 u64 tsc = compute_guest_tsc(v, kernel_ns);
1927 if (tsc > tsc_timestamp) {
f1e2b260 1928 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1929 tsc_timestamp = tsc;
1930 }
50d0a0f9
GH		 1931 }
1932
18068523
GOC		 1933 local_irq_restore(flags);
1934
0d6dd2ff 1935 /* With all the info we got, fill in the values */
18068523 1936
78db6a50
PB		 1937 if (kvm_has_tsc_control)
1938 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1939
1940 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1941 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1942 &vcpu->hv_clock.tsc_shift,
1943 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1944 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1945 }
1946
1d5f066e 1947 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1948 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1949 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1950
d828199e 1951 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1952 pvclock_flags = 0;
d828199e
MT		 1953 if (use_master_clock)
1954 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1955
78c0337a
MT		 1956 vcpu->hv_clock.flags = pvclock_flags;
1957
095cf55d
PB		 1958 if (vcpu->pv_time_enabled)
1959 kvm_setup_pvclock_page(v);
1960 if (v == kvm_get_vcpu(v->kvm, 0))
1961 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1962 return 0;
c8076604
GH		 1963}
1964
0061d53d
MT		 1965/*
1966 * kvmclock updates which are isolated to a given vcpu, such as
1967 * vcpu->cpu migration, should not allow system_timestamp from
1968 * the rest of the vcpus to remain static. Otherwise ntp frequency
1969 * correction applies to one vcpu's system_timestamp but not
1970 * the others.
1971 *
1972 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1973 * We need to rate-limit these requests though, as they can
1974 * considerably slow guests that have a large number of vcpus.
1975 * The time for a remote vcpu to update its kvmclock is bound
1976 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1977 */
1978
7e44e449
AJ		 1979#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1980
1981static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1982{
1983 int i;
7e44e449
AJ		 1984 struct delayed_work *dwork = to_delayed_work(work);
1985 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1986 kvmclock_update_work);
1987 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1988 struct kvm_vcpu *vcpu;
1989
1990 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1991 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1992 kvm_vcpu_kick(vcpu);
1993 }
1994}
1995
7e44e449
AJ		 1996static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1997{
1998 struct kvm *kvm = v->kvm;
1999
105b21bb 2000 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2001 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2002 KVMCLOCK_UPDATE_DELAY);
2003}
2004
332967a3
AJ		 2005#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2006
2007static void kvmclock_sync_fn(struct work_struct *work)
2008{
2009 struct delayed_work *dwork = to_delayed_work(work);
2010 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2011 kvmclock_sync_work);
2012 struct kvm *kvm = container_of(ka, struct kvm, arch);
2013
630994b3
MT		 2014 if (!kvmclock_periodic_sync)
2015 return;
2016
332967a3
AJ		 2017 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2018 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2019 KVMCLOCK_SYNC_PERIOD);
2020}
2021
9ffd986c 2022static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2023{
890ca9ae
HY		 2024 u64 mcg_cap = vcpu->arch.mcg_cap;
2025 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2026 u32 msr = msr_info->index;
2027 u64 data = msr_info->data;
890ca9ae 2028
15c4a640 2029 switch (msr) {
15c4a640 2030 case MSR_IA32_MCG_STATUS:
890ca9ae 2031 vcpu->arch.mcg_status = data;
15c4a640 2032 break;
c7ac679c 2033 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2034 if (!(mcg_cap & MCG_CTL_P))
2035 return 1;
2036 if (data != 0 && data != ~(u64)0)
2037 return -1;
2038 vcpu->arch.mcg_ctl = data;
2039 break;
2040 default:
2041 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2042 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2043 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2044 /* only 0 or all 1s can be written to IA32_MCi_CTL
2045 * some Linux kernels though clear bit 10 in bank 4 to
2046 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2047 * this to avoid an uncatched #GP in the guest
2048 */
890ca9ae 2049 if ((offset & 0x3) == 0 &&
114be429 2050 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2051 return -1;
9ffd986c
WL		 2052 if (!msr_info->host_initiated &&
2053 (offset & 0x3) == 1 && data != 0)
2054 return -1;
890ca9ae
HY		 2055 vcpu->arch.mce_banks[offset] = data;
2056 break;
2057 }
2058 return 1;
2059 }
2060 return 0;
2061}
2062
ffde22ac
ES		 2063static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2064{
2065 struct kvm *kvm = vcpu->kvm;
2066 int lm = is_long_mode(vcpu);
2067 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2068 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2069 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2070 : kvm->arch.xen_hvm_config.blob_size_32;
2071 u32 page_num = data & ~PAGE_MASK;
2072 u64 page_addr = data & PAGE_MASK;
2073 u8 *page;
2074 int r;
2075
2076 r = -E2BIG;
2077 if (page_num >= blob_size)
2078 goto out;
2079 r = -ENOMEM;
ff5c2c03
SL		 2080 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2081 if (IS_ERR(page)) {
2082 r = PTR_ERR(page);
ffde22ac 2083 goto out;
ff5c2c03 2084 }
54bf36aa 2085 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2086 goto out_free;
2087 r = 0;
2088out_free:
2089 kfree(page);
2090out:
2091 return r;
2092}
2093
344d9588
GN		 2094static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2095{
2096 gpa_t gpa = data & ~0x3f;
2097
52a5c155
WL		 2098 /* Bits 3:5 are reserved, Should be zero */
2099 if (data & 0x38)
344d9588
GN		 2100 return 1;
2101
2102 vcpu->arch.apf.msr_val = data;
2103
2104 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2105 kvm_clear_async_pf_completion_queue(vcpu);
2106 kvm_async_pf_hash_reset(vcpu);
2107 return 0;
2108 }
2109
4e335d9e 2110 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2111 sizeof(u32)))
344d9588
GN		 2112 return 1;
2113
6adba527 2114 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2115 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2116 kvm_async_pf_wakeup_all(vcpu);
2117 return 0;
2118}
2119
12f9a48f
GC		 2120static void kvmclock_reset(struct kvm_vcpu *vcpu)
2121{
0b79459b 2122 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2123}
2124
f38a7b75
WL		 2125static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2126{
2127 ++vcpu->stat.tlb_flush;
2128 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2129}
2130
c9aaa895
GC		 2131static void record_steal_time(struct kvm_vcpu *vcpu)
2132{
2133 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2134 return;
2135
4e335d9e 2136 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2137 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2138 return;
2139
f38a7b75
WL		 2140 /*
2141 * Doing a TLB flush here, on the guest's behalf, can avoid
2142 * expensive IPIs.
2143 */
2144 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2145 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2146
35f3fae1
WL		 2147 if (vcpu->arch.st.steal.version & 1)
2148 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2149
2150 vcpu->arch.st.steal.version += 1;
2151
4e335d9e 2152 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2153 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2154
2155 smp_wmb();
2156
c54cdf14
LC		 2157 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2158 vcpu->arch.st.last_steal;
2159 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2160
4e335d9e 2161 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2162 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2163
2164 smp_wmb();
2165
2166 vcpu->arch.st.steal.version += 1;
c9aaa895 2167
4e335d9e 2168 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2169 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2170}
2171
8fe8ab46 2172int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2173{
5753785f 2174 bool pr = false;
8fe8ab46
WA		 2175 u32 msr = msr_info->index;
2176 u64 data = msr_info->data;
5753785f 2177
15c4a640 2178 switch (msr) {
2e32b719
BP		 2179 case MSR_AMD64_NB_CFG:
2180 case MSR_IA32_UCODE_REV:
2181 case MSR_IA32_UCODE_WRITE:
2182 case MSR_VM_HSAVE_PA:
2183 case MSR_AMD64_PATCH_LOADER:
2184 case MSR_AMD64_BU_CFG2:
405a353a 2185 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2186 break;
2187
15c4a640 2188 case MSR_EFER:
b69e8cae 2189 return set_efer(vcpu, data);
8f1589d9
AP		 2190 case MSR_K7_HWCR:
2191 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2192 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2193 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2194 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2195 if (data != 0) {
a737f256
CD		 2196 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2197 data);
8f1589d9
AP		 2198 return 1;
2199 }
15c4a640 2200 break;
f7c6d140
AP		 2201 case MSR_FAM10H_MMIO_CONF_BASE:
2202 if (data != 0) {
a737f256
CD		 2203 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2204 "0x%llx\n", data);
f7c6d140
AP		 2205 return 1;
2206 }
15c4a640 2207 break;
b5e2fec0
AG		 2208 case MSR_IA32_DEBUGCTLMSR:
2209 if (!data) {
2210 /* We support the non-activated case already */
2211 break;
2212 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2213 /* Values other than LBR and BTF are vendor-specific,
2214 thus reserved and should throw a #GP */
2215 return 1;
2216 }
a737f256
CD		 2217 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2218 __func__, data);
b5e2fec0 2219 break;
9ba075a6 2220 case 0x200 ... 0x2ff:
ff53604b 2221 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2222 case MSR_IA32_APICBASE:
58cb628d 2223 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2224 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2225 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2226 case MSR_IA32_TSCDEADLINE:
2227 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2228 break;
ba904635 2229 case MSR_IA32_TSC_ADJUST:
d6321d49 2230 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2231 if (!msr_info->host_initiated) {
d913b904 2232 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2233 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2234 }
2235 vcpu->arch.ia32_tsc_adjust_msr = data;
2236 }
2237 break;
15c4a640 2238 case MSR_IA32_MISC_ENABLE:
ad312c7c 2239 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2240 break;
64d60670
PB		 2241 case MSR_IA32_SMBASE:
2242 if (!msr_info->host_initiated)
2243 return 1;
2244 vcpu->arch.smbase = data;
2245 break;
52797bf9
LA		 2246 case MSR_SMI_COUNT:
2247 if (!msr_info->host_initiated)
2248 return 1;
2249 vcpu->arch.smi_count = data;
2250 break;
11c6bffa 2251 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2252 case MSR_KVM_WALL_CLOCK:
2253 vcpu->kvm->arch.wall_clock = data;
2254 kvm_write_wall_clock(vcpu->kvm, data);
2255 break;
11c6bffa 2256 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2257 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2258 struct kvm_arch *ka = &vcpu->kvm->arch;
2259
12f9a48f 2260 kvmclock_reset(vcpu);
18068523 2261
54750f2c
MT		 2262 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2263 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2264
2265 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2266 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2267
2268 ka->boot_vcpu_runs_old_kvmclock = tmp;
2269 }
2270
18068523 2271 vcpu->arch.time = data;
0061d53d 2272 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2273
2274 /* we verify if the enable bit is set... */
2275 if (!(data & 1))
2276 break;
2277
4e335d9e 2278 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2279 &vcpu->arch.pv_time, data & ~1ULL,
2280 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2281 vcpu->arch.pv_time_enabled = false;
2282 else
2283 vcpu->arch.pv_time_enabled = true;
32cad84f 2284
18068523
GOC		 2285 break;
2286 }
344d9588
GN		 2287 case MSR_KVM_ASYNC_PF_EN:
2288 if (kvm_pv_enable_async_pf(vcpu, data))
2289 return 1;
2290 break;
c9aaa895
GC		 2291 case MSR_KVM_STEAL_TIME:
2292
2293 if (unlikely(!sched_info_on()))
2294 return 1;
2295
2296 if (data & KVM_STEAL_RESERVED_MASK)
2297 return 1;
2298
4e335d9e 2299 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2300 data & KVM_STEAL_VALID_BITS,
2301 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2302 return 1;
2303
2304 vcpu->arch.st.msr_val = data;
2305
2306 if (!(data & KVM_MSR_ENABLED))
2307 break;
2308
c9aaa895
GC		 2309 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2310
2311 break;
ae7a2a3f
MT		 2312 case MSR_KVM_PV_EOI_EN:
2313 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2314 return 1;
2315 break;
c9aaa895 2316
890ca9ae
HY		 2317 case MSR_IA32_MCG_CTL:
2318 case MSR_IA32_MCG_STATUS:
81760dcc 2319 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2320 return set_msr_mce(vcpu, msr_info);
71db6023 2321
6912ac32
WH		 2322 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2323 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2324 pr = true; /* fall through */
2325 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2326 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2327 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2328 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2329
2330 if (pr || data != 0)
a737f256
CD		 2331 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2332 "0x%x data 0x%llx\n", msr, data);
5753785f 2333 break;
84e0cefa
JS		 2334 case MSR_K7_CLK_CTL:
2335 /*
2336 * Ignore all writes to this no longer documented MSR.
2337 * Writes are only relevant for old K7 processors,
2338 * all pre-dating SVM, but a recommended workaround from
4a969980 2339 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2340 * affected processor models on the command line, hence
2341 * the need to ignore the workaround.
2342 */
2343 break;
55cd8e5a 2344 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2345 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2346 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2347 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2348 return kvm_hv_set_msr_common(vcpu, msr, data,
2349 msr_info->host_initiated);
91c9c3ed 2350 case MSR_IA32_BBL_CR_CTL3:
2351 /* Drop writes to this legacy MSR -- see rdmsr
2352 * counterpart for further detail.
2353 */
fab0aa3b
EM		 2354 if (report_ignored_msrs)
2355 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2356 msr, data);
91c9c3ed 2357 break;
2b036c6b 2358 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2359 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2360 return 1;
2361 vcpu->arch.osvw.length = data;
2362 break;
2363 case MSR_AMD64_OSVW_STATUS:
d6321d49 2364 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2365 return 1;
2366 vcpu->arch.osvw.status = data;
2367 break;
db2336a8
KH		 2368 case MSR_PLATFORM_INFO:
2369 if (!msr_info->host_initiated ||
2370 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2371 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2372 cpuid_fault_enabled(vcpu)))
2373 return 1;
2374 vcpu->arch.msr_platform_info = data;
2375 break;
2376 case MSR_MISC_FEATURES_ENABLES:
2377 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2378 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2379 !supports_cpuid_fault(vcpu)))
2380 return 1;
2381 vcpu->arch.msr_misc_features_enables = data;
2382 break;
15c4a640 2383 default:
ffde22ac
ES		 2384 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2385 return xen_hvm_config(vcpu, data);
c6702c9d 2386 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2387 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2388 if (!ignore_msrs) {
ae0f5499 2389 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2390 msr, data);
ed85c068
AP		 2391 return 1;
2392 } else {
fab0aa3b
EM		 2393 if (report_ignored_msrs)
2394 vcpu_unimpl(vcpu,
2395 "ignored wrmsr: 0x%x data 0x%llx\n",
2396 msr, data);
ed85c068
AP		 2397 break;
2398 }
15c4a640
CO		 2399 }
2400 return 0;
2401}
2402EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2403
2404
2405/*
2406 * Reads an msr value (of 'msr_index') into 'pdata'.
2407 * Returns 0 on success, non-0 otherwise.
2408 * Assumes vcpu_load() was already called.
2409 */
609e36d3 2410int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2411{
609e36d3 2412 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2413}
ff651cb6 2414EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2415
890ca9ae 2416static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2417{
2418 u64 data;
890ca9ae
HY		 2419 u64 mcg_cap = vcpu->arch.mcg_cap;
2420 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2421
2422 switch (msr) {
15c4a640
CO		 2423 case MSR_IA32_P5_MC_ADDR:
2424 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2425 data = 0;
2426 break;
15c4a640 2427 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2428 data = vcpu->arch.mcg_cap;
2429 break;
c7ac679c 2430 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2431 if (!(mcg_cap & MCG_CTL_P))
2432 return 1;
2433 data = vcpu->arch.mcg_ctl;
2434 break;
2435 case MSR_IA32_MCG_STATUS:
2436 data = vcpu->arch.mcg_status;
2437 break;
2438 default:
2439 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2440 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2441 u32 offset = msr - MSR_IA32_MC0_CTL;
2442 data = vcpu->arch.mce_banks[offset];
2443 break;
2444 }
2445 return 1;
2446 }
2447 *pdata = data;
2448 return 0;
2449}
2450
609e36d3 2451int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2452{
609e36d3 2453 switch (msr_info->index) {
890ca9ae 2454 case MSR_IA32_PLATFORM_ID:
15c4a640 2455 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2456 case MSR_IA32_DEBUGCTLMSR:
2457 case MSR_IA32_LASTBRANCHFROMIP:
2458 case MSR_IA32_LASTBRANCHTOIP:
2459 case MSR_IA32_LASTINTFROMIP:
2460 case MSR_IA32_LASTINTTOIP:
60af2ecd 2461 case MSR_K8_SYSCFG:
3afb1121
PB		 2462 case MSR_K8_TSEG_ADDR:
2463 case MSR_K8_TSEG_MASK:
60af2ecd 2464 case MSR_K7_HWCR:
61a6bd67 2465 case MSR_VM_HSAVE_PA:
1fdbd48c 2466 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2467 case MSR_AMD64_NB_CFG:
f7c6d140 2468 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2469 case MSR_AMD64_BU_CFG2:
0c2df2a1 2470 case MSR_IA32_PERF_CTL:
405a353a 2471 case MSR_AMD64_DC_CFG:
609e36d3 2472 msr_info->data = 0;
15c4a640 2473 break;
6912ac32
WH		 2474 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2475 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2476 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2477 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2478 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2479 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2480 msr_info->data = 0;
5753785f 2481 break;
742bc670 2482 case MSR_IA32_UCODE_REV:
609e36d3 2483 msr_info->data = 0x100000000ULL;
742bc670 2484 break;
9ba075a6 2485 case MSR_MTRRcap:
9ba075a6 2486 case 0x200 ... 0x2ff:
ff53604b 2487 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2488 case 0xcd: /* fsb frequency */
609e36d3 2489 msr_info->data = 3;
15c4a640 2490 break;
7b914098
JS		 2491 /*
2492 * MSR_EBC_FREQUENCY_ID
2493 * Conservative value valid for even the basic CPU models.
2494 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2495 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2496 * and 266MHz for model 3, or 4. Set Core Clock
2497 * Frequency to System Bus Frequency Ratio to 1 (bits
2498 * 31:24) even though these are only valid for CPU
2499 * models > 2, however guests may end up dividing or
2500 * multiplying by zero otherwise.
2501 */
2502 case MSR_EBC_FREQUENCY_ID:
609e36d3 2503 msr_info->data = 1 << 24;
7b914098 2504 break;
15c4a640 2505 case MSR_IA32_APICBASE:
609e36d3 2506 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2507 break;
0105d1a5 2508 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2509 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2510 break;
a3e06bbe 2511 case MSR_IA32_TSCDEADLINE:
609e36d3 2512 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2513 break;
ba904635 2514 case MSR_IA32_TSC_ADJUST:
609e36d3 2515 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2516 break;
15c4a640 2517 case MSR_IA32_MISC_ENABLE:
609e36d3 2518 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2519 break;
64d60670
PB		 2520 case MSR_IA32_SMBASE:
2521 if (!msr_info->host_initiated)
2522 return 1;
2523 msr_info->data = vcpu->arch.smbase;
15c4a640 2524 break;
52797bf9
LA		 2525 case MSR_SMI_COUNT:
2526 msr_info->data = vcpu->arch.smi_count;
2527 break;
847f0ad8
AG		 2528 case MSR_IA32_PERF_STATUS:
2529 /* TSC increment by tick */
609e36d3 2530 msr_info->data = 1000ULL;
847f0ad8 2531 /* CPU multiplier */
b0996ae4 2532 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2533 break;
15c4a640 2534 case MSR_EFER:
609e36d3 2535 msr_info->data = vcpu->arch.efer;
15c4a640 2536 break;
18068523 2537 case MSR_KVM_WALL_CLOCK:
11c6bffa 2538 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2539 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2540 break;
2541 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2542 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2543 msr_info->data = vcpu->arch.time;
18068523 2544 break;
344d9588 2545 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2546 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2547 break;
c9aaa895 2548 case MSR_KVM_STEAL_TIME:
609e36d3 2549 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2550 break;
1d92128f 2551 case MSR_KVM_PV_EOI_EN:
609e36d3 2552 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2553 break;
890ca9ae
HY		 2554 case MSR_IA32_P5_MC_ADDR:
2555 case MSR_IA32_P5_MC_TYPE:
2556 case MSR_IA32_MCG_CAP:
2557 case MSR_IA32_MCG_CTL:
2558 case MSR_IA32_MCG_STATUS:
81760dcc 2559 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2560 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2561 case MSR_K7_CLK_CTL:
2562 /*
2563 * Provide expected ramp-up count for K7. All other
2564 * are set to zero, indicating minimum divisors for
2565 * every field.
2566 *
2567 * This prevents guest kernels on AMD host with CPU
2568 * type 6, model 8 and higher from exploding due to
2569 * the rdmsr failing.
2570 */
609e36d3 2571 msr_info->data = 0x20000000;
84e0cefa 2572 break;
55cd8e5a 2573 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2574 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2575 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2576 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2577 return kvm_hv_get_msr_common(vcpu,
2578 msr_info->index, &msr_info->data);
55cd8e5a 2579 break;
91c9c3ed 2580 case MSR_IA32_BBL_CR_CTL3:
2581 /* This legacy MSR exists but isn't fully documented in current
2582 * silicon. It is however accessed by winxp in very narrow
2583 * scenarios where it sets bit #19, itself documented as
2584 * a "reserved" bit. Best effort attempt to source coherent
2585 * read data here should the balance of the register be
2586 * interpreted by the guest:
2587 *
2588 * L2 cache control register 3: 64GB range, 256KB size,
2589 * enabled, latency 0x1, configured
2590 */
609e36d3 2591 msr_info->data = 0xbe702111;
91c9c3ed 2592 break;
2b036c6b 2593 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2594 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2595 return 1;
609e36d3 2596 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2597 break;
2598 case MSR_AMD64_OSVW_STATUS:
d6321d49 2599 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2600 return 1;
609e36d3 2601 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2602 break;
db2336a8
KH		 2603 case MSR_PLATFORM_INFO:
2604 msr_info->data = vcpu->arch.msr_platform_info;
2605 break;
2606 case MSR_MISC_FEATURES_ENABLES:
2607 msr_info->data = vcpu->arch.msr_misc_features_enables;
2608 break;
15c4a640 2609 default:
c6702c9d 2610 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2611 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2612 if (!ignore_msrs) {
ae0f5499
BD		 2613 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2614 msr_info->index);
ed85c068
AP		 2615 return 1;
2616 } else {
fab0aa3b
EM		 2617 if (report_ignored_msrs)
2618 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2619 msr_info->index);
609e36d3 2620 msr_info->data = 0;
ed85c068
AP		 2621 }
2622 break;
15c4a640 2623 }
15c4a640
CO		 2624 return 0;
2625}
2626EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2627
313a3dc7
CO		 2628/*
2629 * Read or write a bunch of msrs. All parameters are kernel addresses.
2630 *
2631 * @return number of msrs set successfully.
2632 */
2633static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2634 struct kvm_msr_entry *entries,
2635 int (*do_msr)(struct kvm_vcpu *vcpu,
2636 unsigned index, u64 *data))
2637{
f656ce01 2638 int i, idx;
313a3dc7 2639
f656ce01 2640 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2641 for (i = 0; i < msrs->nmsrs; ++i)
2642 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2643 break;
f656ce01 2644 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2645
313a3dc7
CO		 2646 return i;
2647}
2648
2649/*
2650 * Read or write a bunch of msrs. Parameters are user addresses.
2651 *
2652 * @return number of msrs set successfully.
2653 */
2654static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2655 int (*do_msr)(struct kvm_vcpu *vcpu,
2656 unsigned index, u64 *data),
2657 int writeback)
2658{
2659 struct kvm_msrs msrs;
2660 struct kvm_msr_entry *entries;
2661 int r, n;
2662 unsigned size;
2663
2664 r = -EFAULT;
2665 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2666 goto out;
2667
2668 r = -E2BIG;
2669 if (msrs.nmsrs >= MAX_IO_MSRS)
2670 goto out;
2671
313a3dc7 2672 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2673 entries = memdup_user(user_msrs->entries, size);
2674 if (IS_ERR(entries)) {
2675 r = PTR_ERR(entries);
313a3dc7 2676 goto out;
ff5c2c03 2677 }
313a3dc7
CO		 2678
2679 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2680 if (r < 0)
2681 goto out_free;
2682
2683 r = -EFAULT;
2684 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2685 goto out_free;
2686
2687 r = n;
2688
2689out_free:
7a73c028 2690 kfree(entries);
313a3dc7
CO		 2691out:
2692 return r;
2693}
2694
784aa3d7 2695int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2696{
2697 int r;
2698
2699 switch (ext) {
2700 case KVM_CAP_IRQCHIP:
2701 case KVM_CAP_HLT:
2702 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2703 case KVM_CAP_SET_TSS_ADDR:
07716717 2704 case KVM_CAP_EXT_CPUID:
9c15bb1d 2705 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2706 case KVM_CAP_CLOCKSOURCE:
7837699f 2707 case KVM_CAP_PIT:
a28e4f5a 2708 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2709 case KVM_CAP_MP_STATE:
ed848624 2710 case KVM_CAP_SYNC_MMU:
a355c85c 2711 case KVM_CAP_USER_NMI:
52d939a0 2712 case KVM_CAP_REINJECT_CONTROL:
4925663a 2713 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2714 case KVM_CAP_IOEVENTFD:
f848a5a8 2715 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2716 case KVM_CAP_PIT2:
e9f42757 2717 case KVM_CAP_PIT_STATE2:
b927a3ce 2718 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2719 case KVM_CAP_XEN_HVM:
3cfc3092 2720 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2721 case KVM_CAP_HYPERV:
10388a07 2722 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2723 case KVM_CAP_HYPERV_SPIN:
5c919412 2724 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2725 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2726 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2727 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2728 case KVM_CAP_DEBUGREGS:
d2be1651 2729 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2730 case KVM_CAP_XSAVE:
344d9588 2731 case KVM_CAP_ASYNC_PF:
92a1f12d 2732 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2733 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2734 case KVM_CAP_READONLY_MEM:
5f66b620 2735 case KVM_CAP_HYPERV_TIME:
100943c5 2736 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2737 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2738 case KVM_CAP_ENABLE_CAP_VM:
2739 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2740 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2741 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2742 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2743 r = 1;
2744 break;
e3fd9a93
PB		 2745 case KVM_CAP_ADJUST_CLOCK:
2746 r = KVM_CLOCK_TSC_STABLE;
2747 break;
668fffa3
MT		 2748 case KVM_CAP_X86_GUEST_MWAIT:
2749 r = kvm_mwait_in_guest();
2750 break;
6d396b55
PB		 2751 case KVM_CAP_X86_SMM:
2752 /* SMBASE is usually relocated above 1M on modern chipsets,
2753 * and SMM handlers might indeed rely on 4G segment limits,
2754 * so do not report SMM to be available if real mode is
2755 * emulated via vm86 mode. Still, do not go to great lengths
2756 * to avoid userspace's usage of the feature, because it is a
2757 * fringe case that is not enabled except via specific settings
2758 * of the module parameters.
2759 */
2760 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2761 break;
774ead3a
AK		 2762 case KVM_CAP_VAPIC:
2763 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2764 break;
f725230a 2765 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2766 r = KVM_SOFT_MAX_VCPUS;
2767 break;
2768 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2769 r = KVM_MAX_VCPUS;
2770 break;
a988b910 2771 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2772 r = KVM_USER_MEM_SLOTS;
a988b910 2773 break;
a68a6a72
MT		 2774 case KVM_CAP_PV_MMU: /* obsolete */
2775 r = 0;
2f333bcb 2776 break;
890ca9ae
HY		 2777 case KVM_CAP_MCE:
2778 r = KVM_MAX_MCE_BANKS;
2779 break;
2d5b5a66 2780 case KVM_CAP_XCRS:
d366bf7e 2781 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2782 break;
92a1f12d
JR		 2783 case KVM_CAP_TSC_CONTROL:
2784 r = kvm_has_tsc_control;
2785 break;
37131313
RK		 2786 case KVM_CAP_X2APIC_API:
2787 r = KVM_X2APIC_API_VALID_FLAGS;
2788 break;
018d00d2
ZX		 2789 default:
2790 r = 0;
2791 break;
2792 }
2793 return r;
2794
2795}
2796
043405e1
CO		 2797long kvm_arch_dev_ioctl(struct file *filp,
2798 unsigned int ioctl, unsigned long arg)
2799{
2800 void __user *argp = (void __user *)arg;
2801 long r;
2802
2803 switch (ioctl) {
2804 case KVM_GET_MSR_INDEX_LIST: {
2805 struct kvm_msr_list __user *user_msr_list = argp;
2806 struct kvm_msr_list msr_list;
2807 unsigned n;
2808
2809 r = -EFAULT;
2810 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2811 goto out;
2812 n = msr_list.nmsrs;
62ef68bb 2813 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2814 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2815 goto out;
2816 r = -E2BIG;
e125e7b6 2817 if (n < msr_list.nmsrs)
043405e1
CO		 2818 goto out;
2819 r = -EFAULT;
2820 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2821 num_msrs_to_save * sizeof(u32)))
2822 goto out;
e125e7b6 2823 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2824 &emulated_msrs,
62ef68bb 2825 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2826 goto out;
2827 r = 0;
2828 break;
2829 }
9c15bb1d
BP		 2830 case KVM_GET_SUPPORTED_CPUID:
2831 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2832 struct kvm_cpuid2 __user *cpuid_arg = argp;
2833 struct kvm_cpuid2 cpuid;
2834
2835 r = -EFAULT;
2836 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2837 goto out;
9c15bb1d
BP		 2838
2839 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2840 ioctl);
674eea0f
AK		 2841 if (r)
2842 goto out;
2843
2844 r = -EFAULT;
2845 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2846 goto out;
2847 r = 0;
2848 break;
2849 }
890ca9ae 2850 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2851 r = -EFAULT;
c45dcc71
AR		 2852 if (copy_to_user(argp, &kvm_mce_cap_supported,
2853 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2854 goto out;
2855 r = 0;
2856 break;
2857 }
043405e1
CO		 2858 default:
2859 r = -EINVAL;
2860 }
2861out:
2862 return r;
2863}
2864
f5f48ee1
SY		 2865static void wbinvd_ipi(void *garbage)
2866{
2867 wbinvd();
2868}
2869
2870static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2871{
e0f0bbc5 2872 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2873}
2874
313a3dc7
CO		 2875void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2876{
f5f48ee1
SY		 2877 /* Address WBINVD may be executed by guest */
2878 if (need_emulate_wbinvd(vcpu)) {
2879 if (kvm_x86_ops->has_wbinvd_exit())
2880 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2881 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2882 smp_call_function_single(vcpu->cpu,
2883 wbinvd_ipi, NULL, 1);
2884 }
2885
313a3dc7 2886 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2887
0dd6a6ed
ZA		 2888 /* Apply any externally detected TSC adjustments (due to suspend) */
2889 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2890 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2891 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2892 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2893 }
8f6055cb 2894
48434c20 2895 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2896 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2897 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2898 if (tsc_delta < 0)
2899 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2900
c285545f 2901 if (check_tsc_unstable()) {
07c1419a 2902 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2903 vcpu->arch.last_guest_tsc);
a545ab6a 2904 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2905 vcpu->arch.tsc_catchup = 1;
c285545f 2906 }
a749e247
PB		 2907
2908 if (kvm_lapic_hv_timer_in_use(vcpu))
2909 kvm_lapic_restart_hv_timer(vcpu);
2910
d98d07ca
MT		 2911 /*
2912 * On a host with synchronized TSC, there is no need to update
2913 * kvmclock on vcpu->cpu migration
2914 */
2915 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2916 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2917 if (vcpu->cpu != cpu)
1bd2009e 2918 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2919 vcpu->cpu = cpu;
6b7d7e76 2920 }
c9aaa895 2921
c9aaa895 2922 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2923}
2924
0b9f6c46
PX		 2925static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2926{
2927 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2928 return;
2929
fa55eedd 2930 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 2931
4e335d9e 2932 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2933 &vcpu->arch.st.steal.preempted,
2934 offsetof(struct kvm_steal_time, preempted),
2935 sizeof(vcpu->arch.st.steal.preempted));
2936}
2937
313a3dc7
CO		 2938void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2939{
cc0d907c 2940 int idx;
de63ad4c
LM		 2941
2942 if (vcpu->preempted)
2943 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2944
931f261b
AA		 2945 /*
2946 * Disable page faults because we're in atomic context here.
2947 * kvm_write_guest_offset_cached() would call might_fault()
2948 * that relies on pagefault_disable() to tell if there's a
2949 * bug. NOTE: the write to guest memory may not go through if
2950 * during postcopy live migration or if there's heavy guest
2951 * paging.
2952 */
2953 pagefault_disable();
cc0d907c
AA		 2954 /*
2955 * kvm_memslots() will be called by
2956 * kvm_write_guest_offset_cached() so take the srcu lock.
2957 */
2958 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2959 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2960 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2961 pagefault_enable();
02daab21 2962 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 2963 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 2964 /*
2965 * If userspace has set any breakpoints or watchpoints, dr6 is restored
2966 * on every vmexit, but if not, we might have a stale dr6 from the
2967 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
2968 */
2969 set_debugreg(0, 6);
313a3dc7
CO		 2970}
2971
313a3dc7
CO		 2972static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2973 struct kvm_lapic_state *s)
2974{
76dfafd5 2975 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2976 kvm_x86_ops->sync_pir_to_irr(vcpu);
2977
a92e2543 2978 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2979}
2980
2981static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2982 struct kvm_lapic_state *s)
2983{
a92e2543
RK		 2984 int r;
2985
2986 r = kvm_apic_set_state(vcpu, s);
2987 if (r)
2988 return r;
cb142eb7 2989 update_cr8_intercept(vcpu);
313a3dc7
CO		 2990
2991 return 0;
2992}
2993
127a457a
MG		 2994static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2995{
2996 return (!lapic_in_kernel(vcpu) ||
2997 kvm_apic_accept_pic_intr(vcpu));
2998}
2999
782d422b
MG		 3000/*
3001 * if userspace requested an interrupt window, check that the
3002 * interrupt window is open.
3003 *
3004 * No need to exit to userspace if we already have an interrupt queued.
3005 */
3006static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3007{
3008 return kvm_arch_interrupt_allowed(vcpu) &&
3009 !kvm_cpu_has_interrupt(vcpu) &&
3010 !kvm_event_needs_reinjection(vcpu) &&
3011 kvm_cpu_accept_dm_intr(vcpu);
3012}
3013
f77bc6a4
ZX		 3014static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3015 struct kvm_interrupt *irq)
3016{
02cdb50f 3017 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3018 return -EINVAL;
1c1a9ce9
SR		 3019
3020 if (!irqchip_in_kernel(vcpu->kvm)) {
3021 kvm_queue_interrupt(vcpu, irq->irq, false);
3022 kvm_make_request(KVM_REQ_EVENT, vcpu);
3023 return 0;
3024 }
3025
3026 /*
3027 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3028 * fail for in-kernel 8259.
3029 */
3030 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3031 return -ENXIO;
f77bc6a4 3032
1c1a9ce9
SR		 3033 if (vcpu->arch.pending_external_vector != -1)
3034 return -EEXIST;
f77bc6a4 3035
1c1a9ce9 3036 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3037 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3038 return 0;
3039}
3040
c4abb7c9
JK		 3041static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3042{
c4abb7c9 3043 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3044
3045 return 0;
3046}
3047
f077825a
PB		 3048static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3049{
64d60670
PB		 3050 kvm_make_request(KVM_REQ_SMI, vcpu);
3051
f077825a
PB		 3052 return 0;
3053}
3054
b209749f
AK		 3055static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3056 struct kvm_tpr_access_ctl *tac)
3057{
3058 if (tac->flags)
3059 return -EINVAL;
3060 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3061 return 0;
3062}
3063
890ca9ae
HY		 3064static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3065 u64 mcg_cap)
3066{
3067 int r;
3068 unsigned bank_num = mcg_cap & 0xff, bank;
3069
3070 r = -EINVAL;
a9e38c3e 3071 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3072 goto out;
c45dcc71 3073 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3074 goto out;
3075 r = 0;
3076 vcpu->arch.mcg_cap = mcg_cap;
3077 /* Init IA32_MCG_CTL to all 1s */
3078 if (mcg_cap & MCG_CTL_P)
3079 vcpu->arch.mcg_ctl = ~(u64)0;
3080 /* Init IA32_MCi_CTL to all 1s */
3081 for (bank = 0; bank < bank_num; bank++)
3082 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3083
3084 if (kvm_x86_ops->setup_mce)
3085 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3086out:
3087 return r;
3088}
3089
3090static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3091 struct kvm_x86_mce *mce)
3092{
3093 u64 mcg_cap = vcpu->arch.mcg_cap;
3094 unsigned bank_num = mcg_cap & 0xff;
3095 u64 *banks = vcpu->arch.mce_banks;
3096
3097 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3098 return -EINVAL;
3099 /*
3100 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3101 * reporting is disabled
3102 */
3103 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3104 vcpu->arch.mcg_ctl != ~(u64)0)
3105 return 0;
3106 banks += 4 * mce->bank;
3107 /*
3108 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3109 * reporting is disabled for the bank
3110 */
3111 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3112 return 0;
3113 if (mce->status & MCI_STATUS_UC) {
3114 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3115 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3116 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3117 return 0;
3118 }
3119 if (banks[1] & MCI_STATUS_VAL)
3120 mce->status |= MCI_STATUS_OVER;
3121 banks[2] = mce->addr;
3122 banks[3] = mce->misc;
3123 vcpu->arch.mcg_status = mce->mcg_status;
3124 banks[1] = mce->status;
3125 kvm_queue_exception(vcpu, MC_VECTOR);
3126 } else if (!(banks[1] & MCI_STATUS_VAL)
3127 || !(banks[1] & MCI_STATUS_UC)) {
3128 if (banks[1] & MCI_STATUS_VAL)
3129 mce->status |= MCI_STATUS_OVER;
3130 banks[2] = mce->addr;
3131 banks[3] = mce->misc;
3132 banks[1] = mce->status;
3133 } else
3134 banks[1] |= MCI_STATUS_OVER;
3135 return 0;
3136}
3137
3cfc3092
JK		 3138static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3139 struct kvm_vcpu_events *events)
3140{
7460fb4a 3141 process_nmi(vcpu);
664f8e26
WL		 3142 /*
3143 * FIXME: pass injected and pending separately. This is only
3144 * needed for nested virtualization, whose state cannot be
3145 * migrated yet. For now we can combine them.
3146 */
03b82a30 3147 events->exception.injected =
664f8e26
WL		 3148 (vcpu->arch.exception.pending ||
3149 vcpu->arch.exception.injected) &&
03b82a30 3150 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3151 events->exception.nr = vcpu->arch.exception.nr;
3152 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3153 events->exception.pad = 0;
3cfc3092
JK		 3154 events->exception.error_code = vcpu->arch.exception.error_code;
3155
03b82a30
JK		 3156 events->interrupt.injected =
3157 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3158 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3159 events->interrupt.soft = 0;
37ccdcbe 3160 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3161
3162 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3163 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3164 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3165 events->nmi.pad = 0;
3cfc3092 3166
66450a21 3167 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3168
f077825a
PB		 3169 events->smi.smm = is_smm(vcpu);
3170 events->smi.pending = vcpu->arch.smi_pending;
3171 events->smi.smm_inside_nmi =
3172 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3173 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3174
dab4b911 3175 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3176 | KVM_VCPUEVENT_VALID_SHADOW
3177 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3178 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3179}
3180
6ef4e07e
XG		 3181static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3182
3cfc3092
JK		 3183static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3184 struct kvm_vcpu_events *events)
3185{
dab4b911 3186 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3187 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3188 | KVM_VCPUEVENT_VALID_SHADOW
3189 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3190 return -EINVAL;
3191
78e546c8 3192 if (events->exception.injected &&
28d06353
JM		 3193 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3194 is_guest_mode(vcpu)))
78e546c8
PB		 3195 return -EINVAL;
3196
28bf2888
DH		 3197 /* INITs are latched while in SMM */
3198 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3199 (events->smi.smm || events->smi.pending) &&
3200 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3201 return -EINVAL;
3202
7460fb4a 3203 process_nmi(vcpu);
664f8e26 3204 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3205 vcpu->arch.exception.pending = events->exception.injected;
3206 vcpu->arch.exception.nr = events->exception.nr;
3207 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3208 vcpu->arch.exception.error_code = events->exception.error_code;
3209
3210 vcpu->arch.interrupt.pending = events->interrupt.injected;
3211 vcpu->arch.interrupt.nr = events->interrupt.nr;
3212 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3213 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3214 kvm_x86_ops->set_interrupt_shadow(vcpu,
3215 events->interrupt.shadow);
3cfc3092
JK		 3216
3217 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3218 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3219 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3220 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3221
66450a21 3222 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3223 lapic_in_kernel(vcpu))
66450a21 3224 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3225
f077825a 3226 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3227 u32 hflags = vcpu->arch.hflags;
f077825a 3228 if (events->smi.smm)
6ef4e07e 3229 hflags |= HF_SMM_MASK;
f077825a 3230 else
6ef4e07e
XG		 3231 hflags &= ~HF_SMM_MASK;
3232 kvm_set_hflags(vcpu, hflags);
3233
f077825a 3234 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3235
3236 if (events->smi.smm) {
3237 if (events->smi.smm_inside_nmi)
3238 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3239 else
f4ef1910
WL		 3240 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3241 if (lapic_in_kernel(vcpu)) {
3242 if (events->smi.latched_init)
3243 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3244 else
3245 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3246 }
f077825a
PB		 3247 }
3248 }
3249
3842d135
AK		 3250 kvm_make_request(KVM_REQ_EVENT, vcpu);
3251
3cfc3092
JK		 3252 return 0;
3253}
3254
a1efbe77
JK		 3255static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3256 struct kvm_debugregs *dbgregs)
3257{
73aaf249
JK		 3258 unsigned long val;
3259
a1efbe77 3260 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3261 kvm_get_dr(vcpu, 6, &val);
73aaf249 3262 dbgregs->dr6 = val;
a1efbe77
JK		 3263 dbgregs->dr7 = vcpu->arch.dr7;
3264 dbgregs->flags = 0;
97e69aa6 3265 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3266}
3267
3268static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3269 struct kvm_debugregs *dbgregs)
3270{
3271 if (dbgregs->flags)
3272 return -EINVAL;
3273
d14bdb55
PB		 3274 if (dbgregs->dr6 & ~0xffffffffull)
3275 return -EINVAL;
3276 if (dbgregs->dr7 & ~0xffffffffull)
3277 return -EINVAL;
3278
a1efbe77 3279 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3280 kvm_update_dr0123(vcpu);
a1efbe77 3281 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3282 kvm_update_dr6(vcpu);
a1efbe77 3283 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3284 kvm_update_dr7(vcpu);
a1efbe77 3285
a1efbe77
JK		 3286 return 0;
3287}
3288
df1daba7
PB		 3289#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3290
3291static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3292{
c47ada30 3293 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3294 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3295 u64 valid;
3296
3297 /*
3298 * Copy legacy XSAVE area, to avoid complications with CPUID
3299 * leaves 0 and 1 in the loop below.
3300 */
3301 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3302
3303 /* Set XSTATE_BV */
00c87e9a 3304 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3305 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3306
3307 /*
3308 * Copy each region from the possibly compacted offset to the
3309 * non-compacted offset.
3310 */
d91cab78 3311 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3312 while (valid) {
3313 u64 feature = valid & -valid;
3314 int index = fls64(feature) - 1;
3315 void *src = get_xsave_addr(xsave, feature);
3316
3317 if (src) {
3318 u32 size, offset, ecx, edx;
3319 cpuid_count(XSTATE_CPUID, index,
3320 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3321 if (feature == XFEATURE_MASK_PKRU)
3322 memcpy(dest + offset, &vcpu->arch.pkru,
3323 sizeof(vcpu->arch.pkru));
3324 else
3325 memcpy(dest + offset, src, size);
3326
df1daba7
PB		 3327 }
3328
3329 valid -= feature;
3330 }
3331}
3332
3333static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3334{
c47ada30 3335 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3336 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3337 u64 valid;
3338
3339 /*
3340 * Copy legacy XSAVE area, to avoid complications with CPUID
3341 * leaves 0 and 1 in the loop below.
3342 */
3343 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3344
3345 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3346 xsave->header.xfeatures = xstate_bv;
782511b0 3347 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3348 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3349
3350 /*
3351 * Copy each region from the non-compacted offset to the
3352 * possibly compacted offset.
3353 */
d91cab78 3354 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3355 while (valid) {
3356 u64 feature = valid & -valid;
3357 int index = fls64(feature) - 1;
3358 void *dest = get_xsave_addr(xsave, feature);
3359
3360 if (dest) {
3361 u32 size, offset, ecx, edx;
3362 cpuid_count(XSTATE_CPUID, index,
3363 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3364 if (feature == XFEATURE_MASK_PKRU)
3365 memcpy(&vcpu->arch.pkru, src + offset,
3366 sizeof(vcpu->arch.pkru));
3367 else
3368 memcpy(dest, src + offset, size);
ee4100da 3369 }
df1daba7
PB		 3370
3371 valid -= feature;
3372 }
3373}
3374
2d5b5a66
SY		 3375static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3376 struct kvm_xsave *guest_xsave)
3377{
d366bf7e 3378 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3379 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3380 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3381 } else {
2d5b5a66 3382 memcpy(guest_xsave->region,
7366ed77 3383 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3384 sizeof(struct fxregs_state));
2d5b5a66 3385 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3386 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3387 }
3388}
3389
a575813b
WL		 3390#define XSAVE_MXCSR_OFFSET 24
3391
2d5b5a66
SY		 3392static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3393 struct kvm_xsave *guest_xsave)
3394{
3395 u64 xstate_bv =
3396 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3397 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3398
d366bf7e 3399 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3400 /*
3401 * Here we allow setting states that are not present in
3402 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3403 * with old userspace.
3404 */
a575813b
WL		 3405 if (xstate_bv & ~kvm_supported_xcr0() ||
3406 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3407 return -EINVAL;
df1daba7 3408 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3409 } else {
a575813b
WL		 3410 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3411 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3412 return -EINVAL;
7366ed77 3413 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3414 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3415 }
3416 return 0;
3417}
3418
3419static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3420 struct kvm_xcrs *guest_xcrs)
3421{
d366bf7e 3422 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3423 guest_xcrs->nr_xcrs = 0;
3424 return;
3425 }
3426
3427 guest_xcrs->nr_xcrs = 1;
3428 guest_xcrs->flags = 0;
3429 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3430 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3431}
3432
3433static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3434 struct kvm_xcrs *guest_xcrs)
3435{
3436 int i, r = 0;
3437
d366bf7e 3438 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3439 return -EINVAL;
3440
3441 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3442 return -EINVAL;
3443
3444 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3445 /* Only support XCR0 currently */
c67a04cb 3446 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3447 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3448 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3449 break;
3450 }
3451 if (r)
3452 r = -EINVAL;
3453 return r;
3454}
3455
1c0b28c2
EM		 3456/*
3457 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3458 * stopped by the hypervisor. This function will be called from the host only.
3459 * EINVAL is returned when the host attempts to set the flag for a guest that
3460 * does not support pv clocks.
3461 */
3462static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3463{
0b79459b 3464 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3465 return -EINVAL;
51d59c6b 3466 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3467 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3468 return 0;
3469}
3470
5c919412
AS		 3471static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3472 struct kvm_enable_cap *cap)
3473{
3474 if (cap->flags)
3475 return -EINVAL;
3476
3477 switch (cap->cap) {
efc479e6
RK		 3478 case KVM_CAP_HYPERV_SYNIC2:
3479 if (cap->args[0])
3480 return -EINVAL;
5c919412 3481 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3482 if (!irqchip_in_kernel(vcpu->kvm))
3483 return -EINVAL;
efc479e6
RK		 3484 return kvm_hv_activate_synic(vcpu, cap->cap ==
3485 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3486 default:
3487 return -EINVAL;
3488 }
3489}
3490
313a3dc7
CO		 3491long kvm_arch_vcpu_ioctl(struct file *filp,
3492 unsigned int ioctl, unsigned long arg)
3493{
3494 struct kvm_vcpu *vcpu = filp->private_data;
3495 void __user *argp = (void __user *)arg;
3496 int r;
d1ac91d8
AK		 3497 union {
3498 struct kvm_lapic_state *lapic;
3499 struct kvm_xsave *xsave;
3500 struct kvm_xcrs *xcrs;
3501 void *buffer;
3502 } u;
3503
9b062471
CD		 3504 vcpu_load(vcpu);
3505
d1ac91d8 3506 u.buffer = NULL;
313a3dc7
CO		 3507 switch (ioctl) {
3508 case KVM_GET_LAPIC: {
2204ae3c 3509 r = -EINVAL;
bce87cce 3510 if (!lapic_in_kernel(vcpu))
2204ae3c 3511 goto out;
d1ac91d8 3512 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3513
b772ff36 3514 r = -ENOMEM;
d1ac91d8 3515 if (!u.lapic)
b772ff36 3516 goto out;
d1ac91d8 3517 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3518 if (r)
3519 goto out;
3520 r = -EFAULT;
d1ac91d8 3521 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3522 goto out;
3523 r = 0;
3524 break;
3525 }
3526 case KVM_SET_LAPIC: {
2204ae3c 3527 r = -EINVAL;
bce87cce 3528 if (!lapic_in_kernel(vcpu))
2204ae3c 3529 goto out;
ff5c2c03 3530 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3531 if (IS_ERR(u.lapic)) {
3532 r = PTR_ERR(u.lapic);
3533 goto out_nofree;
3534 }
ff5c2c03 3535
d1ac91d8 3536 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3537 break;
3538 }
f77bc6a4
ZX		 3539 case KVM_INTERRUPT: {
3540 struct kvm_interrupt irq;
3541
3542 r = -EFAULT;
3543 if (copy_from_user(&irq, argp, sizeof irq))
3544 goto out;
3545 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3546 break;
3547 }
c4abb7c9
JK		 3548 case KVM_NMI: {
3549 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3550 break;
3551 }
f077825a
PB		 3552 case KVM_SMI: {
3553 r = kvm_vcpu_ioctl_smi(vcpu);
3554 break;
3555 }
313a3dc7
CO		 3556 case KVM_SET_CPUID: {
3557 struct kvm_cpuid __user *cpuid_arg = argp;
3558 struct kvm_cpuid cpuid;
3559
3560 r = -EFAULT;
3561 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3562 goto out;
3563 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3564 break;
3565 }
07716717
DK		 3566 case KVM_SET_CPUID2: {
3567 struct kvm_cpuid2 __user *cpuid_arg = argp;
3568 struct kvm_cpuid2 cpuid;
3569
3570 r = -EFAULT;
3571 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3572 goto out;
3573 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3574 cpuid_arg->entries);
07716717
DK		 3575 break;
3576 }
3577 case KVM_GET_CPUID2: {
3578 struct kvm_cpuid2 __user *cpuid_arg = argp;
3579 struct kvm_cpuid2 cpuid;
3580
3581 r = -EFAULT;
3582 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3583 goto out;
3584 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3585 cpuid_arg->entries);
07716717
DK		 3586 if (r)
3587 goto out;
3588 r = -EFAULT;
3589 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3590 goto out;
3591 r = 0;
3592 break;
3593 }
313a3dc7 3594 case KVM_GET_MSRS:
609e36d3 3595 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3596 break;
3597 case KVM_SET_MSRS:
3598 r = msr_io(vcpu, argp, do_set_msr, 0);
3599 break;
b209749f
AK		 3600 case KVM_TPR_ACCESS_REPORTING: {
3601 struct kvm_tpr_access_ctl tac;
3602
3603 r = -EFAULT;
3604 if (copy_from_user(&tac, argp, sizeof tac))
3605 goto out;
3606 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3607 if (r)
3608 goto out;
3609 r = -EFAULT;
3610 if (copy_to_user(argp, &tac, sizeof tac))
3611 goto out;
3612 r = 0;
3613 break;
3614 };
b93463aa
AK		 3615 case KVM_SET_VAPIC_ADDR: {
3616 struct kvm_vapic_addr va;
7301d6ab 3617 int idx;
b93463aa
AK		 3618
3619 r = -EINVAL;
35754c98 3620 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3621 goto out;
3622 r = -EFAULT;
3623 if (copy_from_user(&va, argp, sizeof va))
3624 goto out;
7301d6ab 3625 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3626 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3627 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3628 break;
3629 }
890ca9ae
HY		 3630 case KVM_X86_SETUP_MCE: {
3631 u64 mcg_cap;
3632
3633 r = -EFAULT;
3634 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3635 goto out;
3636 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3637 break;
3638 }
3639 case KVM_X86_SET_MCE: {
3640 struct kvm_x86_mce mce;
3641
3642 r = -EFAULT;
3643 if (copy_from_user(&mce, argp, sizeof mce))
3644 goto out;
3645 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3646 break;
3647 }
3cfc3092
JK		 3648 case KVM_GET_VCPU_EVENTS: {
3649 struct kvm_vcpu_events events;
3650
3651 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3652
3653 r = -EFAULT;
3654 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3655 break;
3656 r = 0;
3657 break;
3658 }
3659 case KVM_SET_VCPU_EVENTS: {
3660 struct kvm_vcpu_events events;
3661
3662 r = -EFAULT;
3663 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3664 break;
3665
3666 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3667 break;
3668 }
a1efbe77
JK		 3669 case KVM_GET_DEBUGREGS: {
3670 struct kvm_debugregs dbgregs;
3671
3672 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3673
3674 r = -EFAULT;
3675 if (copy_to_user(argp, &dbgregs,
3676 sizeof(struct kvm_debugregs)))
3677 break;
3678 r = 0;
3679 break;
3680 }
3681 case KVM_SET_DEBUGREGS: {
3682 struct kvm_debugregs dbgregs;
3683
3684 r = -EFAULT;
3685 if (copy_from_user(&dbgregs, argp,
3686 sizeof(struct kvm_debugregs)))
3687 break;
3688
3689 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3690 break;
3691 }
2d5b5a66 3692 case KVM_GET_XSAVE: {
d1ac91d8 3693 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3694 r = -ENOMEM;
d1ac91d8 3695 if (!u.xsave)
2d5b5a66
SY		 3696 break;
3697
d1ac91d8 3698 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3699
3700 r = -EFAULT;
d1ac91d8 3701 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3702 break;
3703 r = 0;
3704 break;
3705 }
3706 case KVM_SET_XSAVE: {
ff5c2c03 3707 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3708 if (IS_ERR(u.xsave)) {
3709 r = PTR_ERR(u.xsave);
3710 goto out_nofree;
3711 }
2d5b5a66 3712
d1ac91d8 3713 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3714 break;
3715 }
3716 case KVM_GET_XCRS: {
d1ac91d8 3717 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3718 r = -ENOMEM;
d1ac91d8 3719 if (!u.xcrs)
2d5b5a66
SY		 3720 break;
3721
d1ac91d8 3722 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3723
3724 r = -EFAULT;
d1ac91d8 3725 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3726 sizeof(struct kvm_xcrs)))
3727 break;
3728 r = 0;
3729 break;
3730 }
3731 case KVM_SET_XCRS: {
ff5c2c03 3732 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3733 if (IS_ERR(u.xcrs)) {
3734 r = PTR_ERR(u.xcrs);
3735 goto out_nofree;
3736 }
2d5b5a66 3737
d1ac91d8 3738 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3739 break;
3740 }
92a1f12d
JR		 3741 case KVM_SET_TSC_KHZ: {
3742 u32 user_tsc_khz;
3743
3744 r = -EINVAL;
92a1f12d
JR		 3745 user_tsc_khz = (u32)arg;
3746
3747 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3748 goto out;
3749
cc578287
ZA		 3750 if (user_tsc_khz == 0)
3751 user_tsc_khz = tsc_khz;
3752
381d585c
HZ		 3753 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3754 r = 0;
92a1f12d 3755
92a1f12d
JR		 3756 goto out;
3757 }
3758 case KVM_GET_TSC_KHZ: {
cc578287 3759 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3760 goto out;
3761 }
1c0b28c2
EM		 3762 case KVM_KVMCLOCK_CTRL: {
3763 r = kvm_set_guest_paused(vcpu);
3764 goto out;
3765 }
5c919412
AS		 3766 case KVM_ENABLE_CAP: {
3767 struct kvm_enable_cap cap;
3768
3769 r = -EFAULT;
3770 if (copy_from_user(&cap, argp, sizeof(cap)))
3771 goto out;
3772 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3773 break;
3774 }
313a3dc7
CO		 3775 default:
3776 r = -EINVAL;
3777 }
3778out:
d1ac91d8 3779 kfree(u.buffer);
9b062471
CD		 3780out_nofree:
3781 vcpu_put(vcpu);
313a3dc7
CO		 3782 return r;
3783}
3784
5b1c1493
CO		 3785int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3786{
3787 return VM_FAULT_SIGBUS;
3788}
3789
1fe779f8
CO		 3790static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3791{
3792 int ret;
3793
3794 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3795 return -EINVAL;
1fe779f8
CO		 3796 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3797 return ret;
3798}
3799
b927a3ce
SY		 3800static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3801 u64 ident_addr)
3802{
3803 kvm->arch.ept_identity_map_addr = ident_addr;
3804 return 0;
3805}
3806
1fe779f8
CO		 3807static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3808 u32 kvm_nr_mmu_pages)
3809{
3810 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3811 return -EINVAL;
3812
79fac95e 3813 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3814
3815 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3816 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3817
79fac95e 3818 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3819 return 0;
3820}
3821
3822static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3823{
39de71ec 3824 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3825}
3826
1fe779f8
CO		 3827static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3828{
90bca052 3829 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3830 int r;
3831
3832 r = 0;
3833 switch (chip->chip_id) {
3834 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3835 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3836 sizeof(struct kvm_pic_state));
3837 break;
3838 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3839 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3840 sizeof(struct kvm_pic_state));
3841 break;
3842 case KVM_IRQCHIP_IOAPIC:
33392b49 3843 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3844 break;
3845 default:
3846 r = -EINVAL;
3847 break;
3848 }
3849 return r;
3850}
3851
3852static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3853{
90bca052 3854 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3855 int r;
3856
3857 r = 0;
3858 switch (chip->chip_id) {
3859 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3860 spin_lock(&pic->lock);
3861 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3862 sizeof(struct kvm_pic_state));
90bca052 3863 spin_unlock(&pic->lock);
1fe779f8
CO		 3864 break;
3865 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3866 spin_lock(&pic->lock);
3867 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3868 sizeof(struct kvm_pic_state));
90bca052 3869 spin_unlock(&pic->lock);
1fe779f8
CO		 3870 break;
3871 case KVM_IRQCHIP_IOAPIC:
33392b49 3872 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3873 break;
3874 default:
3875 r = -EINVAL;
3876 break;
3877 }
90bca052 3878 kvm_pic_update_irq(pic);
1fe779f8
CO		 3879 return r;
3880}
3881
e0f63cb9
SY		 3882static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3883{
34f3941c
RK		 3884 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3885
3886 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3887
3888 mutex_lock(&kps->lock);
3889 memcpy(ps, &kps->channels, sizeof(*ps));
3890 mutex_unlock(&kps->lock);
2da29bcc 3891 return 0;
e0f63cb9
SY		 3892}
3893
3894static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3895{
0185604c 3896 int i;
09edea72
RK		 3897 struct kvm_pit *pit = kvm->arch.vpit;
3898
3899 mutex_lock(&pit->pit_state.lock);
34f3941c 3900 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3901 for (i = 0; i < 3; i++)
09edea72
RK		 3902 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3903 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3904 return 0;
e9f42757
BK		 3905}
3906
3907static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3908{
e9f42757
BK		 3909 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3910 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3911 sizeof(ps->channels));
3912 ps->flags = kvm->arch.vpit->pit_state.flags;
3913 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3914 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3915 return 0;
e9f42757
BK		 3916}
3917
3918static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3919{
2da29bcc 3920 int start = 0;
0185604c 3921 int i;
e9f42757 3922 u32 prev_legacy, cur_legacy;
09edea72
RK		 3923 struct kvm_pit *pit = kvm->arch.vpit;
3924
3925 mutex_lock(&pit->pit_state.lock);
3926 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3927 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3928 if (!prev_legacy && cur_legacy)
3929 start = 1;
09edea72
RK		 3930 memcpy(&pit->pit_state.channels, &ps->channels,
3931 sizeof(pit->pit_state.channels));
3932 pit->pit_state.flags = ps->flags;
0185604c 3933 for (i = 0; i < 3; i++)
09edea72 3934 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3935 start && i == 0);
09edea72 3936 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3937 return 0;
e0f63cb9
SY		 3938}
3939
52d939a0
MT		 3940static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3941 struct kvm_reinject_control *control)
3942{
71474e2f
RK		 3943 struct kvm_pit *pit = kvm->arch.vpit;
3944
3945 if (!pit)
52d939a0 3946 return -ENXIO;
b39c90b6 3947
71474e2f
RK		 3948 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3949 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3950 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3951 */
3952 mutex_lock(&pit->pit_state.lock);
3953 kvm_pit_set_reinject(pit, control->pit_reinject);
3954 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3955
52d939a0
MT		 3956 return 0;
3957}
3958
95d4c16c 3959/**
60c34612
TY		 3960 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3961 * @kvm: kvm instance
3962 * @log: slot id and address to which we copy the log
95d4c16c 3963 *
e108ff2f
PB		 3964 * Steps 1-4 below provide general overview of dirty page logging. See
3965 * kvm_get_dirty_log_protect() function description for additional details.
3966 *
3967 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3968 * always flush the TLB (step 4) even if previous step failed and the dirty
3969 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3970 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3971 * writes will be marked dirty for next log read.
95d4c16c 3972 *
60c34612
TY		 3973 * 1. Take a snapshot of the bit and clear it if needed.
3974 * 2. Write protect the corresponding page.
e108ff2f
PB		 3975 * 3. Copy the snapshot to the userspace.
3976 * 4. Flush TLB's if needed.
5bb064dc 3977 */
60c34612 3978int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3979{
60c34612 3980 bool is_dirty = false;
e108ff2f 3981 int r;
5bb064dc 3982
79fac95e 3983 mutex_lock(&kvm->slots_lock);
5bb064dc 3984
88178fd4
KH		 3985 /*
3986 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3987 */
3988 if (kvm_x86_ops->flush_log_dirty)
3989 kvm_x86_ops->flush_log_dirty(kvm);
3990
e108ff2f 3991 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3992
3993 /*
3994 * All the TLBs can be flushed out of mmu lock, see the comments in
3995 * kvm_mmu_slot_remove_write_access().
3996 */
e108ff2f 3997 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3998 if (is_dirty)
3999 kvm_flush_remote_tlbs(kvm);
4000
79fac95e 4001 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4002 return r;
4003}
4004
aa2fbe6d
YZ		 4005int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4006 bool line_status)
23d43cf9
CD		 4007{
4008 if (!irqchip_in_kernel(kvm))
4009 return -ENXIO;
4010
4011 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4012 irq_event->irq, irq_event->level,
4013 line_status);
23d43cf9
CD		 4014 return 0;
4015}
4016
90de4a18
NA		 4017static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4018 struct kvm_enable_cap *cap)
4019{
4020 int r;
4021
4022 if (cap->flags)
4023 return -EINVAL;
4024
4025 switch (cap->cap) {
4026 case KVM_CAP_DISABLE_QUIRKS:
4027 kvm->arch.disabled_quirks = cap->args[0];
4028 r = 0;
4029 break;
49df6397
SR		 4030 case KVM_CAP_SPLIT_IRQCHIP: {
4031 mutex_lock(&kvm->lock);
b053b2ae
SR		 4032 r = -EINVAL;
4033 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4034 goto split_irqchip_unlock;
49df6397
SR		 4035 r = -EEXIST;
4036 if (irqchip_in_kernel(kvm))
4037 goto split_irqchip_unlock;
557abc40 4038 if (kvm->created_vcpus)
49df6397
SR		 4039 goto split_irqchip_unlock;
4040 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4041 if (r)
49df6397
SR		 4042 goto split_irqchip_unlock;
4043 /* Pairs with irqchip_in_kernel. */
4044 smp_wmb();
49776faf 4045 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4046 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4047 r = 0;
4048split_irqchip_unlock:
4049 mutex_unlock(&kvm->lock);
4050 break;
4051 }
37131313
RK		 4052 case KVM_CAP_X2APIC_API:
4053 r = -EINVAL;
4054 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4055 break;
4056
4057 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4058 kvm->arch.x2apic_format = true;
c519265f
RK		 4059 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4060 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4061
4062 r = 0;
4063 break;
90de4a18
NA		 4064 default:
4065 r = -EINVAL;
4066 break;
4067 }
4068 return r;
4069}
4070
1fe779f8
CO		 4071long kvm_arch_vm_ioctl(struct file *filp,
4072 unsigned int ioctl, unsigned long arg)
4073{
4074 struct kvm *kvm = filp->private_data;
4075 void __user *argp = (void __user *)arg;
367e1319 4076 int r = -ENOTTY;
f0d66275
DH		 4077 /*
4078 * This union makes it completely explicit to gcc-3.x
4079 * that these two variables' stack usage should be
4080 * combined, not added together.
4081 */
4082 union {
4083 struct kvm_pit_state ps;
e9f42757 4084 struct kvm_pit_state2 ps2;
c5ff41ce 4085 struct kvm_pit_config pit_config;
f0d66275 4086 } u;
1fe779f8
CO		 4087
4088 switch (ioctl) {
4089 case KVM_SET_TSS_ADDR:
4090 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4091 break;
b927a3ce
SY		 4092 case KVM_SET_IDENTITY_MAP_ADDR: {
4093 u64 ident_addr;
4094
1af1ac91
DH		 4095 mutex_lock(&kvm->lock);
4096 r = -EINVAL;
4097 if (kvm->created_vcpus)
4098 goto set_identity_unlock;
b927a3ce
SY		 4099 r = -EFAULT;
4100 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4101 goto set_identity_unlock;
b927a3ce 4102 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4103set_identity_unlock:
4104 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4105 break;
4106 }
1fe779f8
CO		 4107 case KVM_SET_NR_MMU_PAGES:
4108 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4109 break;
4110 case KVM_GET_NR_MMU_PAGES:
4111 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4112 break;
3ddea128 4113 case KVM_CREATE_IRQCHIP: {
3ddea128 4114 mutex_lock(&kvm->lock);
09941366 4115
3ddea128 4116 r = -EEXIST;
35e6eaa3 4117 if (irqchip_in_kernel(kvm))
3ddea128 4118 goto create_irqchip_unlock;
09941366 4119
3e515705 4120 r = -EINVAL;
557abc40 4121 if (kvm->created_vcpus)
3e515705 4122 goto create_irqchip_unlock;
09941366
RK		 4123
4124 r = kvm_pic_init(kvm);
4125 if (r)
3ddea128 4126 goto create_irqchip_unlock;
09941366
RK		 4127
4128 r = kvm_ioapic_init(kvm);
4129 if (r) {
09941366 4130 kvm_pic_destroy(kvm);
3ddea128 4131 goto create_irqchip_unlock;
09941366
RK		 4132 }
4133
399ec807
AK		 4134 r = kvm_setup_default_irq_routing(kvm);
4135 if (r) {
72bb2fcd 4136 kvm_ioapic_destroy(kvm);
09941366 4137 kvm_pic_destroy(kvm);
71ba994c 4138 goto create_irqchip_unlock;
399ec807 4139 }
49776faf 4140 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4141 smp_wmb();
49776faf 4142 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4143 create_irqchip_unlock:
4144 mutex_unlock(&kvm->lock);
1fe779f8 4145 break;
3ddea128 4146 }
7837699f 4147 case KVM_CREATE_PIT:
c5ff41ce
JK		 4148 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4149 goto create_pit;
4150 case KVM_CREATE_PIT2:
4151 r = -EFAULT;
4152 if (copy_from_user(&u.pit_config, argp,
4153 sizeof(struct kvm_pit_config)))
4154 goto out;
4155 create_pit:
250715a6 4156 mutex_lock(&kvm->lock);
269e05e4
AK		 4157 r = -EEXIST;
4158 if (kvm->arch.vpit)
4159 goto create_pit_unlock;
7837699f 4160 r = -ENOMEM;
c5ff41ce 4161 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4162 if (kvm->arch.vpit)
4163 r = 0;
269e05e4 4164 create_pit_unlock:
250715a6 4165 mutex_unlock(&kvm->lock);
7837699f 4166 break;
1fe779f8
CO		 4167 case KVM_GET_IRQCHIP: {
4168 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4169 struct kvm_irqchip *chip;
1fe779f8 4170
ff5c2c03
SL		 4171 chip = memdup_user(argp, sizeof(*chip));
4172 if (IS_ERR(chip)) {
4173 r = PTR_ERR(chip);
1fe779f8 4174 goto out;
ff5c2c03
SL		 4175 }
4176
1fe779f8 4177 r = -ENXIO;
826da321 4178 if (!irqchip_kernel(kvm))
f0d66275
DH		 4179 goto get_irqchip_out;
4180 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4181 if (r)
f0d66275 4182 goto get_irqchip_out;
1fe779f8 4183 r = -EFAULT;
f0d66275
DH		 4184 if (copy_to_user(argp, chip, sizeof *chip))
4185 goto get_irqchip_out;
1fe779f8 4186 r = 0;
f0d66275
DH		 4187 get_irqchip_out:
4188 kfree(chip);
1fe779f8
CO		 4189 break;
4190 }
4191 case KVM_SET_IRQCHIP: {
4192 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4193 struct kvm_irqchip *chip;
1fe779f8 4194
ff5c2c03
SL		 4195 chip = memdup_user(argp, sizeof(*chip));
4196 if (IS_ERR(chip)) {
4197 r = PTR_ERR(chip);
1fe779f8 4198 goto out;
ff5c2c03
SL		 4199 }
4200
1fe779f8 4201 r = -ENXIO;
826da321 4202 if (!irqchip_kernel(kvm))
f0d66275
DH		 4203 goto set_irqchip_out;
4204 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4205 if (r)
f0d66275 4206 goto set_irqchip_out;
1fe779f8 4207 r = 0;
f0d66275
DH		 4208 set_irqchip_out:
4209 kfree(chip);
1fe779f8
CO		 4210 break;
4211 }
e0f63cb9 4212 case KVM_GET_PIT: {
e0f63cb9 4213 r = -EFAULT;
f0d66275 4214 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4215 goto out;
4216 r = -ENXIO;
4217 if (!kvm->arch.vpit)
4218 goto out;
f0d66275 4219 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4220 if (r)
4221 goto out;
4222 r = -EFAULT;
f0d66275 4223 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4224 goto out;
4225 r = 0;
4226 break;
4227 }
4228 case KVM_SET_PIT: {
e0f63cb9 4229 r = -EFAULT;
f0d66275 4230 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4231 goto out;
4232 r = -ENXIO;
4233 if (!kvm->arch.vpit)
4234 goto out;
f0d66275 4235 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4236 break;
4237 }
e9f42757
BK		 4238 case KVM_GET_PIT2: {
4239 r = -ENXIO;
4240 if (!kvm->arch.vpit)
4241 goto out;
4242 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4243 if (r)
4244 goto out;
4245 r = -EFAULT;
4246 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4247 goto out;
4248 r = 0;
4249 break;
4250 }
4251 case KVM_SET_PIT2: {
4252 r = -EFAULT;
4253 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4254 goto out;
4255 r = -ENXIO;
4256 if (!kvm->arch.vpit)
4257 goto out;
4258 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4259 break;
4260 }
52d939a0
MT		 4261 case KVM_REINJECT_CONTROL: {
4262 struct kvm_reinject_control control;
4263 r = -EFAULT;
4264 if (copy_from_user(&control, argp, sizeof(control)))
4265 goto out;
4266 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4267 break;
4268 }
d71ba788
PB		 4269 case KVM_SET_BOOT_CPU_ID:
4270 r = 0;
4271 mutex_lock(&kvm->lock);
557abc40 4272 if (kvm->created_vcpus)
d71ba788
PB		 4273 r = -EBUSY;
4274 else
4275 kvm->arch.bsp_vcpu_id = arg;
4276 mutex_unlock(&kvm->lock);
4277 break;
ffde22ac
ES		 4278 case KVM_XEN_HVM_CONFIG: {
4279 r = -EFAULT;
4280 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4281 sizeof(struct kvm_xen_hvm_config)))
4282 goto out;
4283 r = -EINVAL;
4284 if (kvm->arch.xen_hvm_config.flags)
4285 goto out;
4286 r = 0;
4287 break;
4288 }
afbcf7ab 4289 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4290 struct kvm_clock_data user_ns;
4291 u64 now_ns;
afbcf7ab
GC		 4292
4293 r = -EFAULT;
4294 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4295 goto out;
4296
4297 r = -EINVAL;
4298 if (user_ns.flags)
4299 goto out;
4300
4301 r = 0;
0bc48bea
RK		 4302 /*
4303 * TODO: userspace has to take care of races with VCPU_RUN, so
4304 * kvm_gen_update_masterclock() can be cut down to locked
4305 * pvclock_update_vm_gtod_copy().
4306 */
4307 kvm_gen_update_masterclock(kvm);
e891a32e 4308 now_ns = get_kvmclock_ns(kvm);
108b249c 4309 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4310 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4311 break;
4312 }
4313 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4314 struct kvm_clock_data user_ns;
4315 u64 now_ns;
4316
e891a32e 4317 now_ns = get_kvmclock_ns(kvm);
108b249c 4318 user_ns.clock = now_ns;
e3fd9a93 4319 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4320 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4321
4322 r = -EFAULT;
4323 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4324 goto out;
4325 r = 0;
4326 break;
4327 }
90de4a18
NA		 4328 case KVM_ENABLE_CAP: {
4329 struct kvm_enable_cap cap;
afbcf7ab 4330
90de4a18
NA		 4331 r = -EFAULT;
4332 if (copy_from_user(&cap, argp, sizeof(cap)))
4333 goto out;
4334 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4335 break;
4336 }
1fe779f8 4337 default:
ad6260da 4338 r = -ENOTTY;
1fe779f8
CO		 4339 }
4340out:
4341 return r;
4342}
4343
a16b043c 4344static void kvm_init_msr_list(void)
043405e1
CO		 4345{
4346 u32 dummy[2];
4347 unsigned i, j;
4348
62ef68bb 4349 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4350 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4351 continue;
93c4adc7
PB		 4352
4353 /*
4354 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4355 * to the guests in some cases.
93c4adc7
PB		 4356 */
4357 switch (msrs_to_save[i]) {
4358 case MSR_IA32_BNDCFGS:
4359 if (!kvm_x86_ops->mpx_supported())
4360 continue;
4361 break;
9dbe6cf9
PB		 4362 case MSR_TSC_AUX:
4363 if (!kvm_x86_ops->rdtscp_supported())
4364 continue;
4365 break;
93c4adc7
PB		 4366 default:
4367 break;
4368 }
4369
043405e1
CO		 4370 if (j < i)
4371 msrs_to_save[j] = msrs_to_save[i];
4372 j++;
4373 }
4374 num_msrs_to_save = j;
62ef68bb
PB		 4375
4376 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4377 switch (emulated_msrs[i]) {
6d396b55
PB		 4378 case MSR_IA32_SMBASE:
4379 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4380 continue;
4381 break;
62ef68bb
PB		 4382 default:
4383 break;
4384 }
4385
4386 if (j < i)
4387 emulated_msrs[j] = emulated_msrs[i];
4388 j++;
4389 }
4390 num_emulated_msrs = j;
043405e1
CO		 4391}
4392
bda9020e
MT		 4393static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4394 const void *v)
bbd9b64e 4395{
70252a10
AK		 4396 int handled = 0;
4397 int n;
4398
4399 do {
4400 n = min(len, 8);
bce87cce 4401 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4402 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4403 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4404 break;
4405 handled += n;
4406 addr += n;
4407 len -= n;
4408 v += n;
4409 } while (len);
bbd9b64e 4410
70252a10 4411 return handled;
bbd9b64e
CO		 4412}
4413
bda9020e 4414static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4415{
70252a10
AK		 4416 int handled = 0;
4417 int n;
4418
4419 do {
4420 n = min(len, 8);
bce87cce 4421 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4422 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4423 addr, n, v))
4424 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4425 break;
4426 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4427 handled += n;
4428 addr += n;
4429 len -= n;
4430 v += n;
4431 } while (len);
bbd9b64e 4432
70252a10 4433 return handled;
bbd9b64e
CO		 4434}
4435
2dafc6c2
GN		 4436static void kvm_set_segment(struct kvm_vcpu *vcpu,
4437 struct kvm_segment *var, int seg)
4438{
4439 kvm_x86_ops->set_segment(vcpu, var, seg);
4440}
4441
4442void kvm_get_segment(struct kvm_vcpu *vcpu,
4443 struct kvm_segment *var, int seg)
4444{
4445 kvm_x86_ops->get_segment(vcpu, var, seg);
4446}
4447
54987b7a
PB		 4448gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4449 struct x86_exception *exception)
02f59dc9
JR		 4450{
4451 gpa_t t_gpa;
02f59dc9
JR		 4452
4453 BUG_ON(!mmu_is_nested(vcpu));
4454
4455 /* NPT walks are always user-walks */
4456 access |= PFERR_USER_MASK;
54987b7a 4457 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4458
4459 return t_gpa;
4460}
4461
ab9ae313
AK		 4462gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4463 struct x86_exception *exception)
1871c602
GN		 4464{
4465 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4466 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4467}
4468
ab9ae313
AK		 4469 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4470 struct x86_exception *exception)
1871c602
GN		 4471{
4472 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4473 access |= PFERR_FETCH_MASK;
ab9ae313 4474 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4475}
4476
ab9ae313
AK		 4477gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4478 struct x86_exception *exception)
1871c602
GN		 4479{
4480 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4481 access |= PFERR_WRITE_MASK;
ab9ae313 4482 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4483}
4484
4485/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4486gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4487 struct x86_exception *exception)
1871c602 4488{
ab9ae313 4489 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4490}
4491
4492static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4493 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4494 struct x86_exception *exception)
bbd9b64e
CO		 4495{
4496 void *data = val;
10589a46 4497 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4498
4499 while (bytes) {
14dfe855 4500 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4501 exception);
bbd9b64e 4502 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4503 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4504 int ret;
4505
bcc55cba 4506 if (gpa == UNMAPPED_GVA)
ab9ae313 4507 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4508 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4509 offset, toread);
10589a46 4510 if (ret < 0) {
c3cd7ffa 4511 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4512 goto out;
4513 }
bbd9b64e 4514
77c2002e
IE		 4515 bytes -= toread;
4516 data += toread;
4517 addr += toread;
bbd9b64e 4518 }
10589a46 4519out:
10589a46 4520 return r;
bbd9b64e 4521}
77c2002e 4522
1871c602 4523/* used for instruction fetching */
0f65dd70
AK		 4524static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4525 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4526 struct x86_exception *exception)
1871c602 4527{
0f65dd70 4528 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4529 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4530 unsigned offset;
4531 int ret;
0f65dd70 4532
44583cba
PB		 4533 /* Inline kvm_read_guest_virt_helper for speed. */
4534 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4535 exception);
4536 if (unlikely(gpa == UNMAPPED_GVA))
4537 return X86EMUL_PROPAGATE_FAULT;
4538
4539 offset = addr & (PAGE_SIZE-1);
4540 if (WARN_ON(offset + bytes > PAGE_SIZE))
4541 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4542 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4543 offset, bytes);
44583cba
PB		 4544 if (unlikely(ret < 0))
4545 return X86EMUL_IO_NEEDED;
4546
4547 return X86EMUL_CONTINUE;
1871c602
GN		 4548}
4549
064aea77 4550int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4551 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4552 struct x86_exception *exception)
1871c602 4553{
0f65dd70 4554 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4555 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4556
1871c602 4557 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4558 exception);
1871c602 4559}
064aea77 4560EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4561
0f65dd70
AK		 4562static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4563 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4564 struct x86_exception *exception)
1871c602 4565{
0f65dd70 4566 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4567 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4568}
4569
7a036a6f
RK		 4570static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4571 unsigned long addr, void *val, unsigned int bytes)
4572{
4573 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4574 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4575
4576 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4577}
4578
6a4d7550 4579int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4580 gva_t addr, void *val,
2dafc6c2 4581 unsigned int bytes,
bcc55cba 4582 struct x86_exception *exception)
77c2002e 4583{
0f65dd70 4584 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4585 void *data = val;
4586 int r = X86EMUL_CONTINUE;
4587
4588 while (bytes) {
14dfe855
JR		 4589 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4590 PFERR_WRITE_MASK,
ab9ae313 4591 exception);
77c2002e
IE		 4592 unsigned offset = addr & (PAGE_SIZE-1);
4593 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4594 int ret;
4595
bcc55cba 4596 if (gpa == UNMAPPED_GVA)
ab9ae313 4597 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4598 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4599 if (ret < 0) {
c3cd7ffa 4600 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4601 goto out;
4602 }
4603
4604 bytes -= towrite;
4605 data += towrite;
4606 addr += towrite;
4607 }
4608out:
4609 return r;
4610}
6a4d7550 4611EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4612
0f89b207
TL		 4613static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4614 gpa_t gpa, bool write)
4615{
4616 /* For APIC access vmexit */
4617 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4618 return 1;
4619
4620 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4621 trace_vcpu_match_mmio(gva, gpa, write, true);
4622 return 1;
4623 }
4624
4625 return 0;
4626}
4627
af7cc7d1
XG		 4628static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4629 gpa_t *gpa, struct x86_exception *exception,
4630 bool write)
4631{
97d64b78
AK		 4632 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4633 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4634
be94f6b7
HH		 4635 /*
4636 * currently PKRU is only applied to ept enabled guest so
4637 * there is no pkey in EPT page table for L1 guest or EPT
4638 * shadow page table for L2 guest.
4639 */
97d64b78 4640 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4641 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4642 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4643 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4644 (gva & (PAGE_SIZE - 1));
4f022648 4645 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4646 return 1;
4647 }
4648
af7cc7d1
XG		 4649 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4650
4651 if (*gpa == UNMAPPED_GVA)
4652 return -1;
4653
0f89b207 4654 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4655}
4656
3200f405 4657int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4658 const void *val, int bytes)
bbd9b64e
CO		 4659{
4660 int ret;
4661
54bf36aa 4662 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4663 if (ret < 0)
bbd9b64e 4664 return 0;
0eb05bf2 4665 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4666 return 1;
4667}
4668
77d197b2
XG		 4669struct read_write_emulator_ops {
4670 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4671 int bytes);
4672 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4673 void *val, int bytes);
4674 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4675 int bytes, void *val);
4676 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4677 void *val, int bytes);
4678 bool write;
4679};
4680
4681static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4682{
4683 if (vcpu->mmio_read_completed) {
77d197b2 4684 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4685 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4686 vcpu->mmio_read_completed = 0;
4687 return 1;
4688 }
4689
4690 return 0;
4691}
4692
4693static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4694 void *val, int bytes)
4695{
54bf36aa 4696 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4697}
4698
4699static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4700 void *val, int bytes)
4701{
4702 return emulator_write_phys(vcpu, gpa, val, bytes);
4703}
4704
4705static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4706{
4707 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4708 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4709}
4710
4711static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4712 void *val, int bytes)
4713{
4714 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4715 return X86EMUL_IO_NEEDED;
4716}
4717
4718static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4719 void *val, int bytes)
4720{
f78146b0
AK		 4721 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4722
87da7e66 4723 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4724 return X86EMUL_CONTINUE;
4725}
4726
0fbe9b0b 4727static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4728 .read_write_prepare = read_prepare,
4729 .read_write_emulate = read_emulate,
4730 .read_write_mmio = vcpu_mmio_read,
4731 .read_write_exit_mmio = read_exit_mmio,
4732};
4733
0fbe9b0b 4734static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4735 .read_write_emulate = write_emulate,
4736 .read_write_mmio = write_mmio,
4737 .read_write_exit_mmio = write_exit_mmio,
4738 .write = true,
4739};
4740
22388a3c
XG		 4741static int emulator_read_write_onepage(unsigned long addr, void *val,
4742 unsigned int bytes,
4743 struct x86_exception *exception,
4744 struct kvm_vcpu *vcpu,
0fbe9b0b 4745 const struct read_write_emulator_ops *ops)
bbd9b64e 4746{
af7cc7d1
XG		 4747 gpa_t gpa;
4748 int handled, ret;
22388a3c 4749 bool write = ops->write;
f78146b0 4750 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4751 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4752
4753 /*
4754 * If the exit was due to a NPF we may already have a GPA.
4755 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4756 * Note, this cannot be used on string operations since string
4757 * operation using rep will only have the initial GPA from the NPF
4758 * occurred.
4759 */
4760 if (vcpu->arch.gpa_available &&
4761 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4762 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4763 gpa = vcpu->arch.gpa_val;
4764 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4765 } else {
4766 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4767 if (ret < 0)
4768 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4769 }
10589a46 4770
618232e2 4771 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4772 return X86EMUL_CONTINUE;
4773
bbd9b64e
CO		 4774 /*
4775 * Is this MMIO handled locally?
4776 */
22388a3c 4777 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4778 if (handled == bytes)
bbd9b64e 4779 return X86EMUL_CONTINUE;
bbd9b64e 4780
70252a10
AK		 4781 gpa += handled;
4782 bytes -= handled;
4783 val += handled;
4784
87da7e66
XG		 4785 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4786 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4787 frag->gpa = gpa;
4788 frag->data = val;
4789 frag->len = bytes;
f78146b0 4790 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4791}
4792
52eb5a6d
XL		 4793static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4794 unsigned long addr,
22388a3c
XG		 4795 void *val, unsigned int bytes,
4796 struct x86_exception *exception,
0fbe9b0b 4797 const struct read_write_emulator_ops *ops)
bbd9b64e 4798{
0f65dd70 4799 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4800 gpa_t gpa;
4801 int rc;
4802
4803 if (ops->read_write_prepare &&
4804 ops->read_write_prepare(vcpu, val, bytes))
4805 return X86EMUL_CONTINUE;
4806
4807 vcpu->mmio_nr_fragments = 0;
0f65dd70 4808
bbd9b64e
CO		 4809 /* Crossing a page boundary? */
4810 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4811 int now;
bbd9b64e
CO		 4812
4813 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4814 rc = emulator_read_write_onepage(addr, val, now, exception,
4815 vcpu, ops);
4816
bbd9b64e
CO		 4817 if (rc != X86EMUL_CONTINUE)
4818 return rc;
4819 addr += now;
bac15531
NA		 4820 if (ctxt->mode != X86EMUL_MODE_PROT64)
4821 addr = (u32)addr;
bbd9b64e
CO		 4822 val += now;
4823 bytes -= now;
4824 }
22388a3c 4825
f78146b0
AK		 4826 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4827 vcpu, ops);
4828 if (rc != X86EMUL_CONTINUE)
4829 return rc;
4830
4831 if (!vcpu->mmio_nr_fragments)
4832 return rc;
4833
4834 gpa = vcpu->mmio_fragments[0].gpa;
4835
4836 vcpu->mmio_needed = 1;
4837 vcpu->mmio_cur_fragment = 0;
4838
87da7e66 4839 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4840 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4841 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4842 vcpu->run->mmio.phys_addr = gpa;
4843
4844 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4845}
4846
4847static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4848 unsigned long addr,
4849 void *val,
4850 unsigned int bytes,
4851 struct x86_exception *exception)
4852{
4853 return emulator_read_write(ctxt, addr, val, bytes,
4854 exception, &read_emultor);
4855}
4856
52eb5a6d 4857static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4858 unsigned long addr,
4859 const void *val,
4860 unsigned int bytes,
4861 struct x86_exception *exception)
4862{
4863 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4864 exception, &write_emultor);
bbd9b64e 4865}
bbd9b64e 4866
daea3e73
AK		 4867#define CMPXCHG_TYPE(t, ptr, old, new) \
4868 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4869
4870#ifdef CONFIG_X86_64
4871# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4872#else
4873# define CMPXCHG64(ptr, old, new) \
9749a6c0 4874 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4875#endif
4876
0f65dd70
AK		 4877static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4878 unsigned long addr,
bbd9b64e
CO		 4879 const void *old,
4880 const void *new,
4881 unsigned int bytes,
0f65dd70 4882 struct x86_exception *exception)
bbd9b64e 4883{
0f65dd70 4884 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4885 gpa_t gpa;
4886 struct page *page;
4887 char *kaddr;
4888 bool exchanged;
2bacc55c 4889
daea3e73
AK		 4890 /* guests cmpxchg8b have to be emulated atomically */
4891 if (bytes > 8 || (bytes & (bytes - 1)))
4892 goto emul_write;
10589a46 4893
daea3e73 4894 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4895
daea3e73
AK		 4896 if (gpa == UNMAPPED_GVA ||
4897 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4898 goto emul_write;
2bacc55c 4899
daea3e73
AK		 4900 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4901 goto emul_write;
72dc67a6 4902
54bf36aa 4903 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4904 if (is_error_page(page))
c19b8bd6 4905 goto emul_write;
72dc67a6 4906
8fd75e12 4907 kaddr = kmap_atomic(page);
daea3e73
AK		 4908 kaddr += offset_in_page(gpa);
4909 switch (bytes) {
4910 case 1:
4911 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4912 break;
4913 case 2:
4914 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4915 break;
4916 case 4:
4917 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4918 break;
4919 case 8:
4920 exchanged = CMPXCHG64(kaddr, old, new);
4921 break;
4922 default:
4923 BUG();
2bacc55c 4924 }
8fd75e12 4925 kunmap_atomic(kaddr);
daea3e73
AK		 4926 kvm_release_page_dirty(page);
4927
4928 if (!exchanged)
4929 return X86EMUL_CMPXCHG_FAILED;
4930
54bf36aa 4931 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4932 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4933
4934 return X86EMUL_CONTINUE;
4a5f48f6 4935
3200f405 4936emul_write:
daea3e73 4937 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4938
0f65dd70 4939 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4940}
4941
cf8f70bf
GN		 4942static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4943{
cbfc6c91 4944 int r = 0, i;
cf8f70bf 4945
cbfc6c91
WL		 4946 for (i = 0; i < vcpu->arch.pio.count; i++) {
4947 if (vcpu->arch.pio.in)
4948 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4949 vcpu->arch.pio.size, pd);
4950 else
4951 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4952 vcpu->arch.pio.port, vcpu->arch.pio.size,
4953 pd);
4954 if (r)
4955 break;
4956 pd += vcpu->arch.pio.size;
4957 }
cf8f70bf
GN		 4958 return r;
4959}
4960
6f6fbe98
XG		 4961static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4962 unsigned short port, void *val,
4963 unsigned int count, bool in)
cf8f70bf 4964{
cf8f70bf 4965 vcpu->arch.pio.port = port;
6f6fbe98 4966 vcpu->arch.pio.in = in;
7972995b 4967 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4968 vcpu->arch.pio.size = size;
4969
4970 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4971 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4972 return 1;
4973 }
4974
4975 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4976 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4977 vcpu->run->io.size = size;
4978 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4979 vcpu->run->io.count = count;
4980 vcpu->run->io.port = port;
4981
4982 return 0;
4983}
4984
6f6fbe98
XG		 4985static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4986 int size, unsigned short port, void *val,
4987 unsigned int count)
cf8f70bf 4988{
ca1d4a9e 4989 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4990 int ret;
ca1d4a9e 4991
6f6fbe98
XG		 4992 if (vcpu->arch.pio.count)
4993 goto data_avail;
cf8f70bf 4994
cbfc6c91
WL		 4995 memset(vcpu->arch.pio_data, 0, size * count);
4996
6f6fbe98
XG		 4997 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4998 if (ret) {
4999data_avail:
5000 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5001 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5002 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5003 return 1;
5004 }
5005
cf8f70bf
GN		 5006 return 0;
5007}
5008
6f6fbe98
XG		 5009static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5010 int size, unsigned short port,
5011 const void *val, unsigned int count)
5012{
5013 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5014
5015 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5016 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5017 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5018}
5019
bbd9b64e
CO		 5020static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5021{
5022 return kvm_x86_ops->get_segment_base(vcpu, seg);
5023}
5024
3cb16fe7 5025static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5026{
3cb16fe7 5027 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5028}
5029
ae6a2375 5030static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5031{
5032 if (!need_emulate_wbinvd(vcpu))
5033 return X86EMUL_CONTINUE;
5034
5035 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5036 int cpu = get_cpu();
5037
5038 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5039 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5040 wbinvd_ipi, NULL, 1);
2eec7343 5041 put_cpu();
f5f48ee1 5042 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5043 } else
5044 wbinvd();
f5f48ee1
SY		 5045 return X86EMUL_CONTINUE;
5046}
5cb56059
JS		 5047
5048int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5049{
6affcbed
KH		 5050 kvm_emulate_wbinvd_noskip(vcpu);
5051 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5052}
f5f48ee1
SY		 5053EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5054
5cb56059
JS		 5055
5056
bcaf5cc5
AK		 5057static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5058{
5cb56059 5059 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5060}
5061
52eb5a6d
XL		 5062static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5063 unsigned long *dest)
bbd9b64e 5064{
16f8a6f9 5065 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5066}
5067
52eb5a6d
XL		 5068static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5069 unsigned long value)
bbd9b64e 5070{
338dbc97 5071
717746e3 5072 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5073}
5074
52a46617 5075static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5076{
52a46617 5077 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5078}
5079
717746e3 5080static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5081{
717746e3 5082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5083 unsigned long value;
5084
5085 switch (cr) {
5086 case 0:
5087 value = kvm_read_cr0(vcpu);
5088 break;
5089 case 2:
5090 value = vcpu->arch.cr2;
5091 break;
5092 case 3:
9f8fe504 5093 value = kvm_read_cr3(vcpu);
52a46617
GN		 5094 break;
5095 case 4:
5096 value = kvm_read_cr4(vcpu);
5097 break;
5098 case 8:
5099 value = kvm_get_cr8(vcpu);
5100 break;
5101 default:
a737f256 5102 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5103 return 0;
5104 }
5105
5106 return value;
5107}
5108
717746e3 5109static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5110{
717746e3 5111 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5112 int res = 0;
5113
52a46617
GN		 5114 switch (cr) {
5115 case 0:
49a9b07e 5116 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5117 break;
5118 case 2:
5119 vcpu->arch.cr2 = val;
5120 break;
5121 case 3:
2390218b 5122 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5123 break;
5124 case 4:
a83b29c6 5125 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5126 break;
5127 case 8:
eea1cff9 5128 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5129 break;
5130 default:
a737f256 5131 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5132 res = -1;
52a46617 5133 }
0f12244f
GN		 5134
5135 return res;
52a46617
GN		 5136}
5137
717746e3 5138static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5139{
717746e3 5140 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5141}
5142
4bff1e86 5143static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5144{
4bff1e86 5145 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5146}
5147
4bff1e86 5148static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5149{
4bff1e86 5150 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5151}
5152
1ac9d0cf
AK		 5153static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5154{
5155 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5156}
5157
5158static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5159{
5160 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5161}
5162
4bff1e86
AK		 5163static unsigned long emulator_get_cached_segment_base(
5164 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5165{
4bff1e86 5166 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5167}
5168
1aa36616
AK		 5169static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5170 struct desc_struct *desc, u32 *base3,
5171 int seg)
2dafc6c2
GN		 5172{
5173 struct kvm_segment var;
5174
4bff1e86 5175 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5176 *selector = var.selector;
2dafc6c2 5177
378a8b09
GN		 5178 if (var.unusable) {
5179 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5180 if (base3)
5181 *base3 = 0;
2dafc6c2 5182 return false;
378a8b09 5183 }
2dafc6c2
GN		 5184
5185 if (var.g)
5186 var.limit >>= 12;
5187 set_desc_limit(desc, var.limit);
5188 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5189#ifdef CONFIG_X86_64
5190 if (base3)
5191 *base3 = var.base >> 32;
5192#endif
2dafc6c2
GN		 5193 desc->type = var.type;
5194 desc->s = var.s;
5195 desc->dpl = var.dpl;
5196 desc->p = var.present;
5197 desc->avl = var.avl;
5198 desc->l = var.l;
5199 desc->d = var.db;
5200 desc->g = var.g;
5201
5202 return true;
5203}
5204
1aa36616
AK		 5205static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5206 struct desc_struct *desc, u32 base3,
5207 int seg)
2dafc6c2 5208{
4bff1e86 5209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5210 struct kvm_segment var;
5211
1aa36616 5212 var.selector = selector;
2dafc6c2 5213 var.base = get_desc_base(desc);
5601d05b
GN		 5214#ifdef CONFIG_X86_64
5215 var.base |= ((u64)base3) << 32;
5216#endif
2dafc6c2
GN		 5217 var.limit = get_desc_limit(desc);
5218 if (desc->g)
5219 var.limit = (var.limit << 12) | 0xfff;
5220 var.type = desc->type;
2dafc6c2
GN		 5221 var.dpl = desc->dpl;
5222 var.db = desc->d;
5223 var.s = desc->s;
5224 var.l = desc->l;
5225 var.g = desc->g;
5226 var.avl = desc->avl;
5227 var.present = desc->p;
5228 var.unusable = !var.present;
5229 var.padding = 0;
5230
5231 kvm_set_segment(vcpu, &var, seg);
5232 return;
5233}
5234
717746e3
AK		 5235static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5236 u32 msr_index, u64 *pdata)
5237{
609e36d3
PB		 5238 struct msr_data msr;
5239 int r;
5240
5241 msr.index = msr_index;
5242 msr.host_initiated = false;
5243 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5244 if (r)
5245 return r;
5246
5247 *pdata = msr.data;
5248 return 0;
717746e3
AK		 5249}
5250
5251static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5252 u32 msr_index, u64 data)
5253{
8fe8ab46
WA		 5254 struct msr_data msr;
5255
5256 msr.data = data;
5257 msr.index = msr_index;
5258 msr.host_initiated = false;
5259 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5260}
5261
64d60670
PB		 5262static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5263{
5264 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5265
5266 return vcpu->arch.smbase;
5267}
5268
5269static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5270{
5271 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5272
5273 vcpu->arch.smbase = smbase;
5274}
5275
67f4d428
NA		 5276static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5277 u32 pmc)
5278{
c6702c9d 5279 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5280}
5281
222d21aa
AK		 5282static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5283 u32 pmc, u64 *pdata)
5284{
c6702c9d 5285 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5286}
5287
6c3287f7
AK		 5288static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5289{
5290 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5291}
5292
2953538e 5293static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5294 struct x86_instruction_info *info,
c4f035c6
AK		 5295 enum x86_intercept_stage stage)
5296{
2953538e 5297 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5298}
5299
e911eb3b
YZ		 5300static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5301 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5302{
e911eb3b 5303 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5304}
5305
dd856efa
AK		 5306static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5307{
5308 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5309}
5310
5311static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5312{
5313 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5314}
5315
801806d9
NA		 5316static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5317{
5318 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5319}
5320
6ed071f0
LP		 5321static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5322{
5323 return emul_to_vcpu(ctxt)->arch.hflags;
5324}
5325
5326static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5327{
5328 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5329}
5330
0234bf88
LP		 5331static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5332{
5333 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5334}
5335
0225fb50 5336static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5337 .read_gpr = emulator_read_gpr,
5338 .write_gpr = emulator_write_gpr,
1871c602 5339 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5340 .write_std = kvm_write_guest_virt_system,
7a036a6f 5341 .read_phys = kvm_read_guest_phys_system,
1871c602 5342 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5343 .read_emulated = emulator_read_emulated,
5344 .write_emulated = emulator_write_emulated,
5345 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5346 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5347 .pio_in_emulated = emulator_pio_in_emulated,
5348 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5349 .get_segment = emulator_get_segment,
5350 .set_segment = emulator_set_segment,
5951c442 5351 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5352 .get_gdt = emulator_get_gdt,
160ce1f1 5353 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5354 .set_gdt = emulator_set_gdt,
5355 .set_idt = emulator_set_idt,
52a46617
GN		 5356 .get_cr = emulator_get_cr,
5357 .set_cr = emulator_set_cr,
9c537244 5358 .cpl = emulator_get_cpl,
35aa5375
GN		 5359 .get_dr = emulator_get_dr,
5360 .set_dr = emulator_set_dr,
64d60670
PB		 5361 .get_smbase = emulator_get_smbase,
5362 .set_smbase = emulator_set_smbase,
717746e3
AK		 5363 .set_msr = emulator_set_msr,
5364 .get_msr = emulator_get_msr,
67f4d428 5365 .check_pmc = emulator_check_pmc,
222d21aa 5366 .read_pmc = emulator_read_pmc,
6c3287f7 5367 .halt = emulator_halt,
bcaf5cc5 5368 .wbinvd = emulator_wbinvd,
d6aa1000 5369 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5370 .intercept = emulator_intercept,
bdb42f5a 5371 .get_cpuid = emulator_get_cpuid,
801806d9 5372 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5373 .get_hflags = emulator_get_hflags,
5374 .set_hflags = emulator_set_hflags,
0234bf88 5375 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5376};
5377
95cb2295
GN		 5378static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5379{
37ccdcbe 5380 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5381 /*
5382 * an sti; sti; sequence only disable interrupts for the first
5383 * instruction. So, if the last instruction, be it emulated or
5384 * not, left the system with the INT_STI flag enabled, it
5385 * means that the last instruction is an sti. We should not
5386 * leave the flag on in this case. The same goes for mov ss
5387 */
37ccdcbe
PB		 5388 if (int_shadow & mask)
5389 mask = 0;
6addfc42 5390 if (unlikely(int_shadow || mask)) {
95cb2295 5391 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5392 if (!mask)
5393 kvm_make_request(KVM_REQ_EVENT, vcpu);
5394 }
95cb2295
GN		 5395}
5396
ef54bcfe 5397static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5398{
5399 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5400 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5401 return kvm_propagate_fault(vcpu, &ctxt->exception);
5402
5403 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5404 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5405 ctxt->exception.error_code);
54b8486f 5406 else
da9cb575 5407 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5408 return false;
54b8486f
GN		 5409}
5410
8ec4722d
MG		 5411static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5412{
adf52235 5413 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5414 int cs_db, cs_l;
5415
8ec4722d
MG		 5416 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5417
adf52235 5418 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5419 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5420
adf52235
TY		 5421 ctxt->eip = kvm_rip_read(vcpu);
5422 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5423 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5424 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5425 cs_db ? X86EMUL_MODE_PROT32 :
5426 X86EMUL_MODE_PROT16;
a584539b 5427 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5428 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5429 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5430
dd856efa 5431 init_decode_cache(ctxt);
7ae441ea 5432 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5433}
5434
71f9833b 5435int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5436{
9d74191a 5437 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5438 int ret;
5439
5440 init_emulate_ctxt(vcpu);
5441
9dac77fa
AK		 5442 ctxt->op_bytes = 2;
5443 ctxt->ad_bytes = 2;
5444 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5445 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5446
5447 if (ret != X86EMUL_CONTINUE)
5448 return EMULATE_FAIL;
5449
9dac77fa 5450 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5451 kvm_rip_write(vcpu, ctxt->eip);
5452 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5453
5454 if (irq == NMI_VECTOR)
7460fb4a 5455 vcpu->arch.nmi_pending = 0;
63995653
MG		 5456 else
5457 vcpu->arch.interrupt.pending = false;
5458
5459 return EMULATE_DONE;
5460}
5461EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5462
6d77dbfc
GN		 5463static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5464{
fc3a9157
JR		 5465 int r = EMULATE_DONE;
5466
6d77dbfc
GN		 5467 ++vcpu->stat.insn_emulation_fail;
5468 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5469 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5470 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5471 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5472 vcpu->run->internal.ndata = 0;
1f4dcb3b 5473 r = EMULATE_USER_EXIT;
fc3a9157 5474 }
6d77dbfc 5475 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5476
5477 return r;
6d77dbfc
GN		 5478}
5479
93c05d3e 5480static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5481 bool write_fault_to_shadow_pgtable,
5482 int emulation_type)
a6f177ef 5483{
95b3cf69 5484 gpa_t gpa = cr2;
ba049e93 5485 kvm_pfn_t pfn;
a6f177ef 5486
991eebf9
GN		 5487 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5488 return false;
5489
95b3cf69
XG		 5490 if (!vcpu->arch.mmu.direct_map) {
5491 /*
5492 * Write permission should be allowed since only
5493 * write access need to be emulated.
5494 */
5495 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5496
95b3cf69
XG		 5497 /*
5498 * If the mapping is invalid in guest, let cpu retry
5499 * it to generate fault.
5500 */
5501 if (gpa == UNMAPPED_GVA)
5502 return true;
5503 }
a6f177ef 5504
8e3d9d06
XG		 5505 /*
5506 * Do not retry the unhandleable instruction if it faults on the
5507 * readonly host memory, otherwise it will goto a infinite loop:
5508 * retry instruction -> write #PF -> emulation fail -> retry
5509 * instruction -> ...
5510 */
5511 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5512
5513 /*
5514 * If the instruction failed on the error pfn, it can not be fixed,
5515 * report the error to userspace.
5516 */
5517 if (is_error_noslot_pfn(pfn))
5518 return false;
5519
5520 kvm_release_pfn_clean(pfn);
5521
5522 /* The instructions are well-emulated on direct mmu. */
5523 if (vcpu->arch.mmu.direct_map) {
5524 unsigned int indirect_shadow_pages;
5525
5526 spin_lock(&vcpu->kvm->mmu_lock);
5527 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5528 spin_unlock(&vcpu->kvm->mmu_lock);
5529
5530 if (indirect_shadow_pages)
5531 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5532
a6f177ef 5533 return true;
8e3d9d06 5534 }
a6f177ef 5535
95b3cf69
XG		 5536 /*
5537 * if emulation was due to access to shadowed page table
5538 * and it failed try to unshadow page and re-enter the
5539 * guest to let CPU execute the instruction.
5540 */
5541 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5542
5543 /*
5544 * If the access faults on its page table, it can not
5545 * be fixed by unprotecting shadow page and it should
5546 * be reported to userspace.
5547 */
5548 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5549}
5550
1cb3f3ae
XG		 5551static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5552 unsigned long cr2, int emulation_type)
5553{
5554 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5555 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5556
5557 last_retry_eip = vcpu->arch.last_retry_eip;
5558 last_retry_addr = vcpu->arch.last_retry_addr;
5559
5560 /*
5561 * If the emulation is caused by #PF and it is non-page_table
5562 * writing instruction, it means the VM-EXIT is caused by shadow
5563 * page protected, we can zap the shadow page and retry this
5564 * instruction directly.
5565 *
5566 * Note: if the guest uses a non-page-table modifying instruction
5567 * on the PDE that points to the instruction, then we will unmap
5568 * the instruction and go to an infinite loop. So, we cache the
5569 * last retried eip and the last fault address, if we meet the eip
5570 * and the address again, we can break out of the potential infinite
5571 * loop.
5572 */
5573 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5574
5575 if (!(emulation_type & EMULTYPE_RETRY))
5576 return false;
5577
5578 if (x86_page_table_writing_insn(ctxt))
5579 return false;
5580
5581 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5582 return false;
5583
5584 vcpu->arch.last_retry_eip = ctxt->eip;
5585 vcpu->arch.last_retry_addr = cr2;
5586
5587 if (!vcpu->arch.mmu.direct_map)
5588 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5589
22368028 5590 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5591
5592 return true;
5593}
5594
716d51ab
GN		 5595static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5596static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5597
64d60670 5598static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5599{
64d60670 5600 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5601 /* This is a good place to trace that we are exiting SMM. */
5602 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5603
c43203ca
PB		 5604 /* Process a latched INIT or SMI, if any. */
5605 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5606 }
699023e2
PB		 5607
5608 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5609}
5610
5611static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5612{
5613 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5614
a584539b 5615 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5616
5617 if (changed & HF_SMM_MASK)
5618 kvm_smm_changed(vcpu);
a584539b
PB		 5619}
5620
4a1e10d5
PB		 5621static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5622 unsigned long *db)
5623{
5624 u32 dr6 = 0;
5625 int i;
5626 u32 enable, rwlen;
5627
5628 enable = dr7;
5629 rwlen = dr7 >> 16;
5630 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5631 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5632 dr6 |= (1 << i);
5633 return dr6;
5634}
5635
c8401dda 5636static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5637{
5638 struct kvm_run *kvm_run = vcpu->run;
5639
c8401dda
PB		 5640 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5641 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5642 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5643 kvm_run->debug.arch.exception = DB_VECTOR;
5644 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5645 *r = EMULATE_USER_EXIT;
5646 } else {
5647 /*
5648 * "Certain debug exceptions may clear bit 0-3. The
5649 * remaining contents of the DR6 register are never
5650 * cleared by the processor".
5651 */
5652 vcpu->arch.dr6 &= ~15;
5653 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5654 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5655 }
5656}
5657
6affcbed
KH		 5658int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5659{
5660 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5661 int r = EMULATE_DONE;
5662
5663 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5664
5665 /*
5666 * rflags is the old, "raw" value of the flags. The new value has
5667 * not been saved yet.
5668 *
5669 * This is correct even for TF set by the guest, because "the
5670 * processor will not generate this exception after the instruction
5671 * that sets the TF flag".
5672 */
5673 if (unlikely(rflags & X86_EFLAGS_TF))
5674 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5675 return r == EMULATE_DONE;
5676}
5677EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5678
4a1e10d5
PB		 5679static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5680{
4a1e10d5
PB		 5681 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5682 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5683 struct kvm_run *kvm_run = vcpu->run;
5684 unsigned long eip = kvm_get_linear_rip(vcpu);
5685 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5686 vcpu->arch.guest_debug_dr7,
5687 vcpu->arch.eff_db);
5688
5689 if (dr6 != 0) {
6f43ed01 5690 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5691 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5692 kvm_run->debug.arch.exception = DB_VECTOR;
5693 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5694 *r = EMULATE_USER_EXIT;
5695 return true;
5696 }
5697 }
5698
4161a569
NA		 5699 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5700 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5701 unsigned long eip = kvm_get_linear_rip(vcpu);
5702 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5703 vcpu->arch.dr7,
5704 vcpu->arch.db);
5705
5706 if (dr6 != 0) {
5707 vcpu->arch.dr6 &= ~15;
6f43ed01 5708 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5709 kvm_queue_exception(vcpu, DB_VECTOR);
5710 *r = EMULATE_DONE;
5711 return true;
5712 }
5713 }
5714
5715 return false;
5716}
5717
51d8b661
AP		 5718int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5719 unsigned long cr2,
dc25e89e
AP		 5720 int emulation_type,
5721 void *insn,
5722 int insn_len)
bbd9b64e 5723{
95cb2295 5724 int r;
9d74191a 5725 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5726 bool writeback = true;
93c05d3e 5727 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5728
93c05d3e
XG		 5729 /*
5730 * Clear write_fault_to_shadow_pgtable here to ensure it is
5731 * never reused.
5732 */
5733 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5734 kvm_clear_exception_queue(vcpu);
8d7d8102 5735
571008da 5736 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5737 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5738
5739 /*
5740 * We will reenter on the same instruction since
5741 * we do not set complete_userspace_io. This does not
5742 * handle watchpoints yet, those would be handled in
5743 * the emulate_ops.
5744 */
5745 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5746 return r;
5747
9d74191a
TY		 5748 ctxt->interruptibility = 0;
5749 ctxt->have_exception = false;
e0ad0b47 5750 ctxt->exception.vector = -1;
9d74191a 5751 ctxt->perm_ok = false;
bbd9b64e 5752
b51e974f 5753 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5754
9d74191a 5755 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5756
e46479f8 5757 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5758 ++vcpu->stat.insn_emulation;
1d2887e2 5759 if (r != EMULATION_OK) {
4005996e
AK		 5760 if (emulation_type & EMULTYPE_TRAP_UD)
5761 return EMULATE_FAIL;
991eebf9
GN		 5762 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5763 emulation_type))
bbd9b64e 5764 return EMULATE_DONE;
6ea6e843
PB		 5765 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5766 return EMULATE_DONE;
6d77dbfc
GN		 5767 if (emulation_type & EMULTYPE_SKIP)
5768 return EMULATE_FAIL;
5769 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5770 }
5771 }
5772
ba8afb6b 5773 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5774 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5775 if (ctxt->eflags & X86_EFLAGS_RF)
5776 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5777 return EMULATE_DONE;
5778 }
5779
1cb3f3ae
XG		 5780 if (retry_instruction(ctxt, cr2, emulation_type))
5781 return EMULATE_DONE;
5782
7ae441ea 5783 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5784 changes registers values during IO operation */
7ae441ea
GN		 5785 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5786 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5787 emulator_invalidate_register_cache(ctxt);
7ae441ea 5788 }
4d2179e1 5789
5cd21917 5790restart:
0f89b207
TL		 5791 /* Save the faulting GPA (cr2) in the address field */
5792 ctxt->exception.address = cr2;
5793
9d74191a 5794 r = x86_emulate_insn(ctxt);
bbd9b64e 5795
775fde86
JR		 5796 if (r == EMULATION_INTERCEPTED)
5797 return EMULATE_DONE;
5798
d2ddd1c4 5799 if (r == EMULATION_FAILED) {
991eebf9
GN		 5800 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5801 emulation_type))
c3cd7ffa
GN		 5802 return EMULATE_DONE;
5803
6d77dbfc 5804 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5805 }
5806
9d74191a 5807 if (ctxt->have_exception) {
d2ddd1c4 5808 r = EMULATE_DONE;
ef54bcfe
PB		 5809 if (inject_emulated_exception(vcpu))
5810 return r;
d2ddd1c4 5811 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5812 if (!vcpu->arch.pio.in) {
5813 /* FIXME: return into emulator if single-stepping. */
3457e419 5814 vcpu->arch.pio.count = 0;
0912c977 5815 } else {
7ae441ea 5816 writeback = false;
716d51ab
GN		 5817 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5818 }
ac0a48c3 5819 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5820 } else if (vcpu->mmio_needed) {
5821 if (!vcpu->mmio_is_write)
5822 writeback = false;
ac0a48c3 5823 r = EMULATE_USER_EXIT;
716d51ab 5824 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5825 } else if (r == EMULATION_RESTART)
5cd21917 5826 goto restart;
d2ddd1c4
GN		 5827 else
5828 r = EMULATE_DONE;
f850e2e6 5829
7ae441ea 5830 if (writeback) {
6addfc42 5831 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5832 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5833 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5834 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5835 if (r == EMULATE_DONE &&
5836 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5837 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5838 if (!ctxt->have_exception ||
5839 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5840 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5841
5842 /*
5843 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5844 * do nothing, and it will be requested again as soon as
5845 * the shadow expires. But we still need to check here,
5846 * because POPF has no interrupt shadow.
5847 */
5848 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5849 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5850 } else
5851 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5852
5853 return r;
de7d789a 5854}
51d8b661 5855EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5856
cf8f70bf 5857int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5858{
cf8f70bf 5859 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5860 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5861 size, port, &val, 1);
cf8f70bf 5862 /* do not return to emulator after return from userspace */
7972995b 5863 vcpu->arch.pio.count = 0;
de7d789a
CO		 5864 return ret;
5865}
cf8f70bf 5866EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5867
8370c3d0
TL		 5868static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5869{
5870 unsigned long val;
5871
5872 /* We should only ever be called with arch.pio.count equal to 1 */
5873 BUG_ON(vcpu->arch.pio.count != 1);
5874
5875 /* For size less than 4 we merge, else we zero extend */
5876 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5877 : 0;
5878
5879 /*
5880 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5881 * the copy and tracing
5882 */
5883 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5884 vcpu->arch.pio.port, &val, 1);
5885 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5886
5887 return 1;
5888}
5889
5890int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5891{
5892 unsigned long val;
5893 int ret;
5894
5895 /* For size less than 4 we merge, else we zero extend */
5896 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5897
5898 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5899 &val, 1);
5900 if (ret) {
5901 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5902 return ret;
5903 }
5904
5905 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5906
5907 return 0;
5908}
5909EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5910
251a5fd6 5911static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5912{
0a3aee0d 5913 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5914 return 0;
8cfdc000
ZA		 5915}
5916
5917static void tsc_khz_changed(void *data)
c8076604 5918{
8cfdc000
ZA		 5919 struct cpufreq_freqs *freq = data;
5920 unsigned long khz = 0;
5921
5922 if (data)
5923 khz = freq->new;
5924 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5925 khz = cpufreq_quick_get(raw_smp_processor_id());
5926 if (!khz)
5927 khz = tsc_khz;
0a3aee0d 5928 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5929}
5930
c8076604
GH		 5931static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5932 void *data)
5933{
5934 struct cpufreq_freqs *freq = data;
5935 struct kvm *kvm;
5936 struct kvm_vcpu *vcpu;
5937 int i, send_ipi = 0;
5938
8cfdc000
ZA		 5939 /*
5940 * We allow guests to temporarily run on slowing clocks,
5941 * provided we notify them after, or to run on accelerating
5942 * clocks, provided we notify them before. Thus time never
5943 * goes backwards.
5944 *
5945 * However, we have a problem. We can't atomically update
5946 * the frequency of a given CPU from this function; it is
5947 * merely a notifier, which can be called from any CPU.
5948 * Changing the TSC frequency at arbitrary points in time
5949 * requires a recomputation of local variables related to
5950 * the TSC for each VCPU. We must flag these local variables
5951 * to be updated and be sure the update takes place with the
5952 * new frequency before any guests proceed.
5953 *
5954 * Unfortunately, the combination of hotplug CPU and frequency
5955 * change creates an intractable locking scenario; the order
5956 * of when these callouts happen is undefined with respect to
5957 * CPU hotplug, and they can race with each other. As such,
5958 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5959 * undefined; you can actually have a CPU frequency change take
5960 * place in between the computation of X and the setting of the
5961 * variable. To protect against this problem, all updates of
5962 * the per_cpu tsc_khz variable are done in an interrupt
5963 * protected IPI, and all callers wishing to update the value
5964 * must wait for a synchronous IPI to complete (which is trivial
5965 * if the caller is on the CPU already). This establishes the
5966 * necessary total order on variable updates.
5967 *
5968 * Note that because a guest time update may take place
5969 * anytime after the setting of the VCPU's request bit, the
5970 * correct TSC value must be set before the request. However,
5971 * to ensure the update actually makes it to any guest which
5972 * starts running in hardware virtualization between the set
5973 * and the acquisition of the spinlock, we must also ping the
5974 * CPU after setting the request bit.
5975 *
5976 */
5977
c8076604
GH		 5978 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5979 return 0;
5980 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5981 return 0;
8cfdc000
ZA		 5982
5983 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5984
2f303b74 5985 spin_lock(&kvm_lock);
c8076604 5986 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5987 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5988 if (vcpu->cpu != freq->cpu)
5989 continue;
c285545f 5990 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5991 if (vcpu->cpu != smp_processor_id())
8cfdc000 5992 send_ipi = 1;
c8076604
GH		 5993 }
5994 }
2f303b74 5995 spin_unlock(&kvm_lock);
c8076604
GH		 5996
5997 if (freq->old < freq->new && send_ipi) {
5998 /*
5999 * We upscale the frequency. Must make the guest
6000 * doesn't see old kvmclock values while running with
6001 * the new frequency, otherwise we risk the guest sees
6002 * time go backwards.
6003 *
6004 * In case we update the frequency for another cpu
6005 * (which might be in guest context) send an interrupt
6006 * to kick the cpu out of guest context. Next time
6007 * guest context is entered kvmclock will be updated,
6008 * so the guest will not see stale values.
6009 */
8cfdc000 6010 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6011 }
6012 return 0;
6013}
6014
6015static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6016 .notifier_call = kvmclock_cpufreq_notifier
6017};
6018
251a5fd6 6019static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6020{
251a5fd6
SAS		 6021 tsc_khz_changed(NULL);
6022 return 0;
8cfdc000
ZA		 6023}
6024
b820cc0c
ZA		 6025static void kvm_timer_init(void)
6026{
c285545f 6027 max_tsc_khz = tsc_khz;
460dd42e 6028
b820cc0c 6029 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6030#ifdef CONFIG_CPU_FREQ
6031 struct cpufreq_policy policy;
758f588d
BP		 6032 int cpu;
6033
c285545f 6034 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6035 cpu = get_cpu();
6036 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6037 if (policy.cpuinfo.max_freq)
6038 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6039 put_cpu();
c285545f 6040#endif
b820cc0c
ZA		 6041 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6042 CPUFREQ_TRANSITION_NOTIFIER);
6043 }
c285545f 6044 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6045
73c1b41e 6046 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6047 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6048}
6049
ff9d07a0
ZY		 6050static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6051
f5132b01 6052int kvm_is_in_guest(void)
ff9d07a0 6053{
086c9855 6054 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6055}
6056
6057static int kvm_is_user_mode(void)
6058{
6059 int user_mode = 3;
dcf46b94 6060
086c9855
AS		 6061 if (__this_cpu_read(current_vcpu))
6062 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6063
ff9d07a0
ZY		 6064 return user_mode != 0;
6065}
6066
6067static unsigned long kvm_get_guest_ip(void)
6068{
6069 unsigned long ip = 0;
dcf46b94 6070
086c9855
AS		 6071 if (__this_cpu_read(current_vcpu))
6072 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6073
ff9d07a0
ZY		 6074 return ip;
6075}
6076
6077static struct perf_guest_info_callbacks kvm_guest_cbs = {
6078 .is_in_guest = kvm_is_in_guest,
6079 .is_user_mode = kvm_is_user_mode,
6080 .get_guest_ip = kvm_get_guest_ip,
6081};
6082
6083void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6084{
086c9855 6085 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6086}
6087EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6088
6089void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6090{
086c9855 6091 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6092}
6093EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6094
ce88decf
XG		 6095static void kvm_set_mmio_spte_mask(void)
6096{
6097 u64 mask;
6098 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6099
6100 /*
6101 * Set the reserved bits and the present bit of an paging-structure
6102 * entry to generate page fault with PFER.RSV = 1.
6103 */
885032b9 6104 /* Mask the reserved physical address bits. */
d1431483 6105 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6106
885032b9 6107 /* Set the present bit. */
ce88decf
XG		 6108 mask |= 1ull;
6109
6110#ifdef CONFIG_X86_64
6111 /*
6112 * If reserved bit is not supported, clear the present bit to disable
6113 * mmio page fault.
6114 */
6115 if (maxphyaddr == 52)
6116 mask &= ~1ull;
6117#endif
6118
dcdca5fe 6119 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6120}
6121
16e8d74d
MT		 6122#ifdef CONFIG_X86_64
6123static void pvclock_gtod_update_fn(struct work_struct *work)
6124{
d828199e
MT		 6125 struct kvm *kvm;
6126
6127 struct kvm_vcpu *vcpu;
6128 int i;
6129
2f303b74 6130 spin_lock(&kvm_lock);
d828199e
MT		 6131 list_for_each_entry(kvm, &vm_list, vm_list)
6132 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6133 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6134 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6135 spin_unlock(&kvm_lock);
16e8d74d
MT		 6136}
6137
6138static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6139
6140/*
6141 * Notification about pvclock gtod data update.
6142 */
6143static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6144 void *priv)
6145{
6146 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6147 struct timekeeper *tk = priv;
6148
6149 update_pvclock_gtod(tk);
6150
6151 /* disable master clock if host does not trust, or does not
6152 * use, TSC clocksource
6153 */
6154 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6155 atomic_read(&kvm_guest_has_master_clock) != 0)
6156 queue_work(system_long_wq, &pvclock_gtod_work);
6157
6158 return 0;
6159}
6160
6161static struct notifier_block pvclock_gtod_notifier = {
6162 .notifier_call = pvclock_gtod_notify,
6163};
6164#endif
6165
f8c16bba 6166int kvm_arch_init(void *opaque)
043405e1 6167{
b820cc0c 6168 int r;
6b61edf7 6169 struct kvm_x86_ops *ops = opaque;
f8c16bba 6170
f8c16bba
ZX		 6171 if (kvm_x86_ops) {
6172 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6173 r = -EEXIST;
6174 goto out;
f8c16bba
ZX		 6175 }
6176
6177 if (!ops->cpu_has_kvm_support()) {
6178 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6179 r = -EOPNOTSUPP;
6180 goto out;
f8c16bba
ZX		 6181 }
6182 if (ops->disabled_by_bios()) {
6183 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6184 r = -EOPNOTSUPP;
6185 goto out;
f8c16bba
ZX		 6186 }
6187
013f6a5d
MT		 6188 r = -ENOMEM;
6189 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6190 if (!shared_msrs) {
6191 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6192 goto out;
6193 }
6194
97db56ce
AK		 6195 r = kvm_mmu_module_init();
6196 if (r)
013f6a5d 6197 goto out_free_percpu;
97db56ce 6198
ce88decf 6199 kvm_set_mmio_spte_mask();
97db56ce 6200
f8c16bba 6201 kvm_x86_ops = ops;
920c8377 6202
7b52345e 6203 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6204 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6205 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6206 kvm_timer_init();
c8076604 6207
ff9d07a0
ZY		 6208 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6209
d366bf7e 6210 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6211 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6212
c5cc421b 6213 kvm_lapic_init();
16e8d74d
MT		 6214#ifdef CONFIG_X86_64
6215 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6216#endif
6217
f8c16bba 6218 return 0;
56c6d28a 6219
013f6a5d
MT		 6220out_free_percpu:
6221 free_percpu(shared_msrs);
56c6d28a 6222out:
56c6d28a 6223 return r;
043405e1 6224}
8776e519 6225
f8c16bba
ZX		 6226void kvm_arch_exit(void)
6227{
cef84c30 6228 kvm_lapic_exit();
ff9d07a0
ZY		 6229 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6230
888d256e
JK		 6231 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6232 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6233 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6234 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6235#ifdef CONFIG_X86_64
6236 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6237#endif
f8c16bba 6238 kvm_x86_ops = NULL;
56c6d28a 6239 kvm_mmu_module_exit();
013f6a5d 6240 free_percpu(shared_msrs);
56c6d28a 6241}
f8c16bba 6242
5cb56059 6243int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6244{
6245 ++vcpu->stat.halt_exits;
35754c98 6246 if (lapic_in_kernel(vcpu)) {
a4535290 6247 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6248 return 1;
6249 } else {
6250 vcpu->run->exit_reason = KVM_EXIT_HLT;
6251 return 0;
6252 }
6253}
5cb56059
JS		 6254EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6255
6256int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6257{
6affcbed
KH		 6258 int ret = kvm_skip_emulated_instruction(vcpu);
6259 /*
6260 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6261 * KVM_EXIT_DEBUG here.
6262 */
6263 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6264}
8776e519
HB		 6265EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6266
8ef81a9a 6267#ifdef CONFIG_X86_64
55dd00a7
MT		 6268static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6269 unsigned long clock_type)
6270{
6271 struct kvm_clock_pairing clock_pairing;
6272 struct timespec ts;
80fbd89c 6273 u64 cycle;
55dd00a7
MT		 6274 int ret;
6275
6276 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6277 return -KVM_EOPNOTSUPP;
6278
6279 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6280 return -KVM_EOPNOTSUPP;
6281
6282 clock_pairing.sec = ts.tv_sec;
6283 clock_pairing.nsec = ts.tv_nsec;
6284 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6285 clock_pairing.flags = 0;
6286
6287 ret = 0;
6288 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6289 sizeof(struct kvm_clock_pairing)))
6290 ret = -KVM_EFAULT;
6291
6292 return ret;
6293}
8ef81a9a 6294#endif
55dd00a7 6295
6aef266c
SV		 6296/*
6297 * kvm_pv_kick_cpu_op: Kick a vcpu.
6298 *
6299 * @apicid - apicid of vcpu to be kicked.
6300 */
6301static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6302{
24d2166b 6303 struct kvm_lapic_irq lapic_irq;
6aef266c 6304
24d2166b
R		 6305 lapic_irq.shorthand = 0;
6306 lapic_irq.dest_mode = 0;
ebd28fcb 6307 lapic_irq.level = 0;
24d2166b 6308 lapic_irq.dest_id = apicid;
93bbf0b8 6309 lapic_irq.msi_redir_hint = false;
6aef266c 6310
24d2166b 6311 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6312 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6313}
6314
d62caabb
AS		 6315void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6316{
6317 vcpu->arch.apicv_active = false;
6318 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6319}
6320
8776e519
HB		 6321int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6322{
6323 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6324 int op_64_bit, r;
8776e519 6325
6affcbed 6326 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6327
55cd8e5a
GN		 6328 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6329 return kvm_hv_hypercall(vcpu);
6330
5fdbf976
MT		 6331 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6332 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6333 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6334 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6335 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6336
229456fc 6337 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6338
a449c7aa
NA		 6339 op_64_bit = is_64_bit_mode(vcpu);
6340 if (!op_64_bit) {
8776e519
HB		 6341 nr &= 0xFFFFFFFF;
6342 a0 &= 0xFFFFFFFF;
6343 a1 &= 0xFFFFFFFF;
6344 a2 &= 0xFFFFFFFF;
6345 a3 &= 0xFFFFFFFF;
6346 }
6347
07708c4a
JK		 6348 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6349 ret = -KVM_EPERM;
6350 goto out;
6351 }
6352
8776e519 6353 switch (nr) {
b93463aa
AK		 6354 case KVM_HC_VAPIC_POLL_IRQ:
6355 ret = 0;
6356 break;
6aef266c
SV		 6357 case KVM_HC_KICK_CPU:
6358 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6359 ret = 0;
6360 break;
8ef81a9a 6361#ifdef CONFIG_X86_64
55dd00a7
MT		 6362 case KVM_HC_CLOCK_PAIRING:
6363 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6364 break;
8ef81a9a 6365#endif
8776e519
HB		 6366 default:
6367 ret = -KVM_ENOSYS;
6368 break;
6369 }
07708c4a 6370out:
a449c7aa
NA		 6371 if (!op_64_bit)
6372 ret = (u32)ret;
5fdbf976 6373 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6374 ++vcpu->stat.hypercalls;
2f333bcb 6375 return r;
8776e519
HB		 6376}
6377EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6378
b6785def 6379static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6380{
d6aa1000 6381 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6382 char instruction[3];
5fdbf976 6383 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6384
8776e519 6385 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6386
ce2e852e
DV		 6387 return emulator_write_emulated(ctxt, rip, instruction, 3,
6388 &ctxt->exception);
8776e519
HB		 6389}
6390
851ba692 6391static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6392{
782d422b
MG		 6393 return vcpu->run->request_interrupt_window &&
6394 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6395}
6396
851ba692 6397static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6398{
851ba692
AK		 6399 struct kvm_run *kvm_run = vcpu->run;
6400
91586a3b 6401 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6402 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6403 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6404 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6405 kvm_run->ready_for_interrupt_injection =
6406 pic_in_kernel(vcpu->kvm) ||
782d422b 6407 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6408}
6409
95ba8273
GN		 6410static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6411{
6412 int max_irr, tpr;
6413
6414 if (!kvm_x86_ops->update_cr8_intercept)
6415 return;
6416
bce87cce 6417 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6418 return;
6419
d62caabb
AS		 6420 if (vcpu->arch.apicv_active)
6421 return;
6422
8db3baa2
GN		 6423 if (!vcpu->arch.apic->vapic_addr)
6424 max_irr = kvm_lapic_find_highest_irr(vcpu);
6425 else
6426 max_irr = -1;
95ba8273
GN		 6427
6428 if (max_irr != -1)
6429 max_irr >>= 4;
6430
6431 tpr = kvm_lapic_get_cr8(vcpu);
6432
6433 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6434}
6435
b6b8a145 6436static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6437{
b6b8a145
JK		 6438 int r;
6439
95ba8273 6440 /* try to reinject previous events if any */
664f8e26
WL		 6441 if (vcpu->arch.exception.injected) {
6442 kvm_x86_ops->queue_exception(vcpu);
6443 return 0;
6444 }
6445
6446 /*
6447 * Exceptions must be injected immediately, or the exception
6448 * frame will have the address of the NMI or interrupt handler.
6449 */
6450 if (!vcpu->arch.exception.pending) {
6451 if (vcpu->arch.nmi_injected) {
6452 kvm_x86_ops->set_nmi(vcpu);
6453 return 0;
6454 }
6455
6456 if (vcpu->arch.interrupt.pending) {
6457 kvm_x86_ops->set_irq(vcpu);
6458 return 0;
6459 }
6460 }
6461
6462 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6463 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6464 if (r != 0)
6465 return r;
6466 }
6467
6468 /* try to inject new event if pending */
b59bb7bd 6469 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6470 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6471 vcpu->arch.exception.has_error_code,
6472 vcpu->arch.exception.error_code);
d6e8c854 6473
664f8e26
WL		 6474 vcpu->arch.exception.pending = false;
6475 vcpu->arch.exception.injected = true;
6476
d6e8c854
NA		 6477 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6478 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6479 X86_EFLAGS_RF);
6480
6bdf0662
NA		 6481 if (vcpu->arch.exception.nr == DB_VECTOR &&
6482 (vcpu->arch.dr7 & DR7_GD)) {
6483 vcpu->arch.dr7 &= ~DR7_GD;
6484 kvm_update_dr7(vcpu);
6485 }
6486
cfcd20e5 6487 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6488 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6489 vcpu->arch.smi_pending = false;
52797bf9 6490 ++vcpu->arch.smi_count;
ee2cd4b7 6491 enter_smm(vcpu);
c43203ca 6492 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6493 --vcpu->arch.nmi_pending;
6494 vcpu->arch.nmi_injected = true;
6495 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6496 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6497 /*
6498 * Because interrupts can be injected asynchronously, we are
6499 * calling check_nested_events again here to avoid a race condition.
6500 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6501 * proposal and current concerns. Perhaps we should be setting
6502 * KVM_REQ_EVENT only on certain events and not unconditionally?
6503 */
6504 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6505 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6506 if (r != 0)
6507 return r;
6508 }
95ba8273 6509 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6510 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6511 false);
6512 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6513 }
6514 }
ee2cd4b7 6515
b6b8a145 6516 return 0;
95ba8273
GN		 6517}
6518
7460fb4a
AK		 6519static void process_nmi(struct kvm_vcpu *vcpu)
6520{
6521 unsigned limit = 2;
6522
6523 /*
6524 * x86 is limited to one NMI running, and one NMI pending after it.
6525 * If an NMI is already in progress, limit further NMIs to just one.
6526 * Otherwise, allow two (and we'll inject the first one immediately).
6527 */
6528 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6529 limit = 1;
6530
6531 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6532 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6533 kvm_make_request(KVM_REQ_EVENT, vcpu);
6534}
6535
ee2cd4b7 6536static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6537{
6538 u32 flags = 0;
6539 flags |= seg->g << 23;
6540 flags |= seg->db << 22;
6541 flags |= seg->l << 21;
6542 flags |= seg->avl << 20;
6543 flags |= seg->present << 15;
6544 flags |= seg->dpl << 13;
6545 flags |= seg->s << 12;
6546 flags |= seg->type << 8;
6547 return flags;
6548}
6549
ee2cd4b7 6550static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6551{
6552 struct kvm_segment seg;
6553 int offset;
6554
6555 kvm_get_segment(vcpu, &seg, n);
6556 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6557
6558 if (n < 3)
6559 offset = 0x7f84 + n * 12;
6560 else
6561 offset = 0x7f2c + (n - 3) * 12;
6562
6563 put_smstate(u32, buf, offset + 8, seg.base);
6564 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6565 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6566}
6567
efbb288a 6568#ifdef CONFIG_X86_64
ee2cd4b7 6569static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6570{
6571 struct kvm_segment seg;
6572 int offset;
6573 u16 flags;
6574
6575 kvm_get_segment(vcpu, &seg, n);
6576 offset = 0x7e00 + n * 16;
6577
ee2cd4b7 6578 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6579 put_smstate(u16, buf, offset, seg.selector);
6580 put_smstate(u16, buf, offset + 2, flags);
6581 put_smstate(u32, buf, offset + 4, seg.limit);
6582 put_smstate(u64, buf, offset + 8, seg.base);
6583}
efbb288a 6584#endif
660a5d51 6585
ee2cd4b7 6586static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6587{
6588 struct desc_ptr dt;
6589 struct kvm_segment seg;
6590 unsigned long val;
6591 int i;
6592
6593 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6594 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6595 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6596 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6597
6598 for (i = 0; i < 8; i++)
6599 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6600
6601 kvm_get_dr(vcpu, 6, &val);
6602 put_smstate(u32, buf, 0x7fcc, (u32)val);
6603 kvm_get_dr(vcpu, 7, &val);
6604 put_smstate(u32, buf, 0x7fc8, (u32)val);
6605
6606 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6607 put_smstate(u32, buf, 0x7fc4, seg.selector);
6608 put_smstate(u32, buf, 0x7f64, seg.base);
6609 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6610 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6611
6612 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6613 put_smstate(u32, buf, 0x7fc0, seg.selector);
6614 put_smstate(u32, buf, 0x7f80, seg.base);
6615 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6616 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6617
6618 kvm_x86_ops->get_gdt(vcpu, &dt);
6619 put_smstate(u32, buf, 0x7f74, dt.address);
6620 put_smstate(u32, buf, 0x7f70, dt.size);
6621
6622 kvm_x86_ops->get_idt(vcpu, &dt);
6623 put_smstate(u32, buf, 0x7f58, dt.address);
6624 put_smstate(u32, buf, 0x7f54, dt.size);
6625
6626 for (i = 0; i < 6; i++)
ee2cd4b7 6627 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6628
6629 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6630
6631 /* revision id */
6632 put_smstate(u32, buf, 0x7efc, 0x00020000);
6633 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6634}
6635
ee2cd4b7 6636static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6637{
6638#ifdef CONFIG_X86_64
6639 struct desc_ptr dt;
6640 struct kvm_segment seg;
6641 unsigned long val;
6642 int i;
6643
6644 for (i = 0; i < 16; i++)
6645 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6646
6647 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6648 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6649
6650 kvm_get_dr(vcpu, 6, &val);
6651 put_smstate(u64, buf, 0x7f68, val);
6652 kvm_get_dr(vcpu, 7, &val);
6653 put_smstate(u64, buf, 0x7f60, val);
6654
6655 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6656 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6657 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6658
6659 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6660
6661 /* revision id */
6662 put_smstate(u32, buf, 0x7efc, 0x00020064);
6663
6664 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6665
6666 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6667 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6668 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6669 put_smstate(u32, buf, 0x7e94, seg.limit);
6670 put_smstate(u64, buf, 0x7e98, seg.base);
6671
6672 kvm_x86_ops->get_idt(vcpu, &dt);
6673 put_smstate(u32, buf, 0x7e84, dt.size);
6674 put_smstate(u64, buf, 0x7e88, dt.address);
6675
6676 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6677 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6678 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6679 put_smstate(u32, buf, 0x7e74, seg.limit);
6680 put_smstate(u64, buf, 0x7e78, seg.base);
6681
6682 kvm_x86_ops->get_gdt(vcpu, &dt);
6683 put_smstate(u32, buf, 0x7e64, dt.size);
6684 put_smstate(u64, buf, 0x7e68, dt.address);
6685
6686 for (i = 0; i < 6; i++)
ee2cd4b7 6687 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6688#else
6689 WARN_ON_ONCE(1);
6690#endif
6691}
6692
ee2cd4b7 6693static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6694{
660a5d51 6695 struct kvm_segment cs, ds;
18c3626e 6696 struct desc_ptr dt;
660a5d51
PB		 6697 char buf[512];
6698 u32 cr0;
6699
660a5d51 6700 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6701 memset(buf, 0, 512);
d6321d49 6702 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6703 enter_smm_save_state_64(vcpu, buf);
660a5d51 6704 else
ee2cd4b7 6705 enter_smm_save_state_32(vcpu, buf);
660a5d51 6706
0234bf88
LP		 6707 /*
6708 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6709 * vCPU state (e.g. leave guest mode) after we've saved the state into
6710 * the SMM state-save area.
6711 */
6712 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6713
6714 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6715 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6716
6717 if (kvm_x86_ops->get_nmi_mask(vcpu))
6718 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6719 else
6720 kvm_x86_ops->set_nmi_mask(vcpu, true);
6721
6722 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6723 kvm_rip_write(vcpu, 0x8000);
6724
6725 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6726 kvm_x86_ops->set_cr0(vcpu, cr0);
6727 vcpu->arch.cr0 = cr0;
6728
6729 kvm_x86_ops->set_cr4(vcpu, 0);
6730
18c3626e
PB		 6731 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6732 dt.address = dt.size = 0;
6733 kvm_x86_ops->set_idt(vcpu, &dt);
6734
660a5d51
PB		 6735 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6736
6737 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6738 cs.base = vcpu->arch.smbase;
6739
6740 ds.selector = 0;
6741 ds.base = 0;
6742
6743 cs.limit = ds.limit = 0xffffffff;
6744 cs.type = ds.type = 0x3;
6745 cs.dpl = ds.dpl = 0;
6746 cs.db = ds.db = 0;
6747 cs.s = ds.s = 1;
6748 cs.l = ds.l = 0;
6749 cs.g = ds.g = 1;
6750 cs.avl = ds.avl = 0;
6751 cs.present = ds.present = 1;
6752 cs.unusable = ds.unusable = 0;
6753 cs.padding = ds.padding = 0;
6754
6755 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6756 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6757 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6758 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6759 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6760 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6761
d6321d49 6762 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6763 kvm_x86_ops->set_efer(vcpu, 0);
6764
6765 kvm_update_cpuid(vcpu);
6766 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6767}
6768
ee2cd4b7 6769static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6770{
6771 vcpu->arch.smi_pending = true;
6772 kvm_make_request(KVM_REQ_EVENT, vcpu);
6773}
6774
2860c4b1
PB		 6775void kvm_make_scan_ioapic_request(struct kvm *kvm)
6776{
6777 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6778}
6779
3d81bc7e 6780static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6781{
5c919412
AS		 6782 u64 eoi_exit_bitmap[4];
6783
3d81bc7e
YZ		 6784 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6785 return;
c7c9c56c 6786
6308630b 6787 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6788
b053b2ae 6789 if (irqchip_split(vcpu->kvm))
6308630b 6790 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6791 else {
76dfafd5 6792 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6793 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6794 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6795 }
5c919412
AS		 6796 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6797 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6798 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6799}
6800
b1394e74
RK		 6801void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6802 unsigned long start, unsigned long end)
6803{
6804 unsigned long apic_address;
6805
6806 /*
6807 * The physical address of apic access page is stored in the VMCS.
6808 * Update it when it becomes invalid.
6809 */
6810 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6811 if (start <= apic_address && apic_address < end)
6812 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6813}
6814
4256f43f
TC		 6815void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6816{
c24ae0dc
TC		 6817 struct page *page = NULL;
6818
35754c98 6819 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6820 return;
6821
4256f43f
TC		 6822 if (!kvm_x86_ops->set_apic_access_page_addr)
6823 return;
6824
c24ae0dc 6825 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6826 if (is_error_page(page))
6827 return;
c24ae0dc
TC		 6828 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6829
6830 /*
6831 * Do not pin apic access page in memory, the MMU notifier
6832 * will call us again if it is migrated or swapped out.
6833 */
6834 put_page(page);
4256f43f
TC		 6835}
6836EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6837
9357d939 6838/*
362c698f 6839 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6840 * exiting to the userspace. Otherwise, the value will be returned to the
6841 * userspace.
6842 */
851ba692 6843static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6844{
6845 int r;
62a193ed
MG		 6846 bool req_int_win =
6847 dm_request_for_irq_injection(vcpu) &&
6848 kvm_cpu_accept_dm_intr(vcpu);
6849
730dca42 6850 bool req_immediate_exit = false;
b6c7a5dc 6851
2fa6e1e1 6852 if (kvm_request_pending(vcpu)) {
a8eeb04a 6853 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6854 kvm_mmu_unload(vcpu);
a8eeb04a 6855 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6856 __kvm_migrate_timers(vcpu);
d828199e
MT		 6857 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6858 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6859 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6860 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6861 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6862 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6863 if (unlikely(r))
6864 goto out;
6865 }
a8eeb04a 6866 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6867 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6868 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 6869 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 6870 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6871 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6872 r = 0;
6873 goto out;
6874 }
a8eeb04a 6875 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6876 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6877 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6878 r = 0;
6879 goto out;
6880 }
af585b92
GN		 6881 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6882 /* Page is swapped out. Do synthetic halt */
6883 vcpu->arch.apf.halted = true;
6884 r = 1;
6885 goto out;
6886 }
c9aaa895
GC		 6887 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6888 record_steal_time(vcpu);
64d60670
PB		 6889 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6890 process_smi(vcpu);
7460fb4a
AK		 6891 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6892 process_nmi(vcpu);
f5132b01 6893 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6894 kvm_pmu_handle_event(vcpu);
f5132b01 6895 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6896 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6897 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6898 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6899 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6900 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6901 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6902 vcpu->run->eoi.vector =
6903 vcpu->arch.pending_ioapic_eoi;
6904 r = 0;
6905 goto out;
6906 }
6907 }
3d81bc7e
YZ		 6908 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6909 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6910 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6911 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6912 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6913 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6914 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6915 r = 0;
6916 goto out;
6917 }
e516cebb
AS		 6918 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6919 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6920 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6921 r = 0;
6922 goto out;
6923 }
db397571
AS		 6924 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6925 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6926 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6927 r = 0;
6928 goto out;
6929 }
f3b138c5
AS		 6930
6931 /*
6932 * KVM_REQ_HV_STIMER has to be processed after
6933 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6934 * depend on the guest clock being up-to-date
6935 */
1f4b34f8
AS		 6936 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6937 kvm_hv_process_stimers(vcpu);
2f52d58c 6938 }
b93463aa 6939
b463a6f7 6940 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6941 ++vcpu->stat.req_event;
66450a21
JK		 6942 kvm_apic_accept_events(vcpu);
6943 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6944 r = 1;
6945 goto out;
6946 }
6947
b6b8a145
JK		 6948 if (inject_pending_event(vcpu, req_int_win) != 0)
6949 req_immediate_exit = true;
321c5658 6950 else {
cc3d967f 6951 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6952 *
cc3d967f
LP		 6953 * SMIs have three cases:
6954 * 1) They can be nested, and then there is nothing to
6955 * do here because RSM will cause a vmexit anyway.
6956 * 2) There is an ISA-specific reason why SMI cannot be
6957 * injected, and the moment when this changes can be
6958 * intercepted.
6959 * 3) Or the SMI can be pending because
6960 * inject_pending_event has completed the injection
6961 * of an IRQ or NMI from the previous vmexit, and
6962 * then we request an immediate exit to inject the
6963 * SMI.
c43203ca
PB		 6964 */
6965 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6966 if (!kvm_x86_ops->enable_smi_window(vcpu))
6967 req_immediate_exit = true;
321c5658
YS		 6968 if (vcpu->arch.nmi_pending)
6969 kvm_x86_ops->enable_nmi_window(vcpu);
6970 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6971 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6972 WARN_ON(vcpu->arch.exception.pending);
321c5658 6973 }
b463a6f7
AK		 6974
6975 if (kvm_lapic_enabled(vcpu)) {
6976 update_cr8_intercept(vcpu);
6977 kvm_lapic_sync_to_vapic(vcpu);
6978 }
6979 }
6980
d8368af8
AK		 6981 r = kvm_mmu_reload(vcpu);
6982 if (unlikely(r)) {
d905c069 6983 goto cancel_injection;
d8368af8
AK		 6984 }
6985
b6c7a5dc
HB		 6986 preempt_disable();
6987
6988 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 6989
6990 /*
6991 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6992 * IPI are then delayed after guest entry, which ensures that they
6993 * result in virtual interrupt delivery.
6994 */
6995 local_irq_disable();
6b7e2d09
XG		 6996 vcpu->mode = IN_GUEST_MODE;
6997
01b71917
MT		 6998 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6999
0f127d12 7000 /*
b95234c8 7001 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7002 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7003 *
7004 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7005 * pairs with the memory barrier implicit in pi_test_and_set_on
7006 * (see vmx_deliver_posted_interrupt).
7007 *
7008 * 3) This also orders the write to mode from any reads to the page
7009 * tables done while the VCPU is running. Please see the comment
7010 * in kvm_flush_remote_tlbs.
6b7e2d09 7011 */
01b71917 7012 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7013
b95234c8
PB		 7014 /*
7015 * This handles the case where a posted interrupt was
7016 * notified with kvm_vcpu_kick.
7017 */
7018 if (kvm_lapic_enabled(vcpu)) {
7019 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7020 kvm_x86_ops->sync_pir_to_irr(vcpu);
7021 }
32f88400 7022
2fa6e1e1 7023 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7024 || need_resched() || signal_pending(current)) {
6b7e2d09 7025 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7026 smp_wmb();
6c142801
AK		 7027 local_irq_enable();
7028 preempt_enable();
01b71917 7029 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7030 r = 1;
d905c069 7031 goto cancel_injection;
6c142801
AK		 7032 }
7033
fc5b7f3b
DM		 7034 kvm_load_guest_xcr0(vcpu);
7035
c43203ca
PB		 7036 if (req_immediate_exit) {
7037 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7038 smp_send_reschedule(vcpu->cpu);
c43203ca 7039 }
d6185f20 7040
8b89fe1f 7041 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7042 if (lapic_timer_advance_ns)
7043 wait_lapic_expire(vcpu);
6edaa530 7044 guest_enter_irqoff();
b6c7a5dc 7045
42dbaa5a 7046 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7047 set_debugreg(0, 7);
7048 set_debugreg(vcpu->arch.eff_db[0], 0);
7049 set_debugreg(vcpu->arch.eff_db[1], 1);
7050 set_debugreg(vcpu->arch.eff_db[2], 2);
7051 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7052 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7053 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7054 }
b6c7a5dc 7055
851ba692 7056 kvm_x86_ops->run(vcpu);
b6c7a5dc 7057
c77fb5fe
PB		 7058 /*
7059 * Do this here before restoring debug registers on the host. And
7060 * since we do this before handling the vmexit, a DR access vmexit
7061 * can (a) read the correct value of the debug registers, (b) set
7062 * KVM_DEBUGREG_WONT_EXIT again.
7063 */
7064 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7065 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7066 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7067 kvm_update_dr0123(vcpu);
7068 kvm_update_dr6(vcpu);
7069 kvm_update_dr7(vcpu);
7070 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7071 }
7072
24f1e32c
FW		 7073 /*
7074 * If the guest has used debug registers, at least dr7
7075 * will be disabled while returning to the host.
7076 * If we don't have active breakpoints in the host, we don't
7077 * care about the messed up debug address registers. But if
7078 * we have some of them active, restore the old state.
7079 */
59d8eb53 7080 if (hw_breakpoint_active())
24f1e32c 7081 hw_breakpoint_restore();
42dbaa5a 7082
4ba76538 7083 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7084
6b7e2d09 7085 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7086 smp_wmb();
a547c6db 7087
fc5b7f3b
DM		 7088 kvm_put_guest_xcr0(vcpu);
7089
a547c6db 7090 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7091
7092 ++vcpu->stat.exits;
7093
f2485b3e 7094 guest_exit_irqoff();
b6c7a5dc 7095
f2485b3e 7096 local_irq_enable();
b6c7a5dc
HB		 7097 preempt_enable();
7098
f656ce01 7099 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7100
b6c7a5dc
HB		 7101 /*
7102 * Profile KVM exit RIPs:
7103 */
7104 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7105 unsigned long rip = kvm_rip_read(vcpu);
7106 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7107 }
7108
cc578287
ZA		 7109 if (unlikely(vcpu->arch.tsc_always_catchup))
7110 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7111
5cfb1d5a
MT		 7112 if (vcpu->arch.apic_attention)
7113 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7114
618232e2 7115 vcpu->arch.gpa_available = false;
851ba692 7116 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7117 return r;
7118
7119cancel_injection:
7120 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7121 if (unlikely(vcpu->arch.apic_attention))
7122 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7123out:
7124 return r;
7125}
b6c7a5dc 7126
362c698f
PB		 7127static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7128{
bf9f6ac8
FW		 7129 if (!kvm_arch_vcpu_runnable(vcpu) &&
7130 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7131 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7132 kvm_vcpu_block(vcpu);
7133 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7134
7135 if (kvm_x86_ops->post_block)
7136 kvm_x86_ops->post_block(vcpu);
7137
9c8fd1ba
PB		 7138 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7139 return 1;
7140 }
362c698f
PB		 7141
7142 kvm_apic_accept_events(vcpu);
7143 switch(vcpu->arch.mp_state) {
7144 case KVM_MP_STATE_HALTED:
7145 vcpu->arch.pv.pv_unhalted = false;
7146 vcpu->arch.mp_state =
7147 KVM_MP_STATE_RUNNABLE;
7148 case KVM_MP_STATE_RUNNABLE:
7149 vcpu->arch.apf.halted = false;
7150 break;
7151 case KVM_MP_STATE_INIT_RECEIVED:
7152 break;
7153 default:
7154 return -EINTR;
7155 break;
7156 }
7157 return 1;
7158}
09cec754 7159
5d9bc648
PB		 7160static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7161{
0ad3bed6
PB		 7162 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7163 kvm_x86_ops->check_nested_events(vcpu, false);
7164
5d9bc648
PB		 7165 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7166 !vcpu->arch.apf.halted);
7167}
7168
362c698f 7169static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7170{
7171 int r;
f656ce01 7172 struct kvm *kvm = vcpu->kvm;
d7690175 7173
f656ce01 7174 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7175
362c698f 7176 for (;;) {
58f800d5 7177 if (kvm_vcpu_running(vcpu)) {
851ba692 7178 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7179 } else {
362c698f 7180 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7181 }
7182
09cec754
GN		 7183 if (r <= 0)
7184 break;
7185
72875d8a 7186 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7187 if (kvm_cpu_has_pending_timer(vcpu))
7188 kvm_inject_pending_timer_irqs(vcpu);
7189
782d422b
MG		 7190 if (dm_request_for_irq_injection(vcpu) &&
7191 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7192 r = 0;
7193 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7194 ++vcpu->stat.request_irq_exits;
362c698f 7195 break;
09cec754 7196 }
af585b92
GN		 7197
7198 kvm_check_async_pf_completion(vcpu);
7199
09cec754
GN		 7200 if (signal_pending(current)) {
7201 r = -EINTR;
851ba692 7202 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7203 ++vcpu->stat.signal_exits;
362c698f 7204 break;
09cec754
GN		 7205 }
7206 if (need_resched()) {
f656ce01 7207 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7208 cond_resched();
f656ce01 7209 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7210 }
b6c7a5dc
HB		 7211 }
7212
f656ce01 7213 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7214
7215 return r;
7216}
7217
716d51ab
GN		 7218static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7219{
7220 int r;
7221 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7222 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7223 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7224 if (r != EMULATE_DONE)
7225 return 0;
7226 return 1;
7227}
7228
7229static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7230{
7231 BUG_ON(!vcpu->arch.pio.count);
7232
7233 return complete_emulated_io(vcpu);
7234}
7235
f78146b0
AK		 7236/*
7237 * Implements the following, as a state machine:
7238 *
7239 * read:
7240 * for each fragment
87da7e66
XG		 7241 * for each mmio piece in the fragment
7242 * write gpa, len
7243 * exit
7244 * copy data
f78146b0
AK		 7245 * execute insn
7246 *
7247 * write:
7248 * for each fragment
87da7e66
XG		 7249 * for each mmio piece in the fragment
7250 * write gpa, len
7251 * copy data
7252 * exit
f78146b0 7253 */
716d51ab 7254static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7255{
7256 struct kvm_run *run = vcpu->run;
f78146b0 7257 struct kvm_mmio_fragment *frag;
87da7e66 7258 unsigned len;
5287f194 7259
716d51ab 7260 BUG_ON(!vcpu->mmio_needed);
5287f194 7261
716d51ab 7262 /* Complete previous fragment */
87da7e66
XG		 7263 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7264 len = min(8u, frag->len);
716d51ab 7265 if (!vcpu->mmio_is_write)
87da7e66
XG		 7266 memcpy(frag->data, run->mmio.data, len);
7267
7268 if (frag->len <= 8) {
7269 /* Switch to the next fragment. */
7270 frag++;
7271 vcpu->mmio_cur_fragment++;
7272 } else {
7273 /* Go forward to the next mmio piece. */
7274 frag->data += len;
7275 frag->gpa += len;
7276 frag->len -= len;
7277 }
7278
a08d3b3b 7279 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7280 vcpu->mmio_needed = 0;
0912c977
PB		 7281
7282 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7283 if (vcpu->mmio_is_write)
716d51ab
GN		 7284 return 1;
7285 vcpu->mmio_read_completed = 1;
7286 return complete_emulated_io(vcpu);
7287 }
87da7e66 7288
716d51ab
GN		 7289 run->exit_reason = KVM_EXIT_MMIO;
7290 run->mmio.phys_addr = frag->gpa;
7291 if (vcpu->mmio_is_write)
87da7e66
XG		 7292 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7293 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7294 run->mmio.is_write = vcpu->mmio_is_write;
7295 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7296 return 0;
5287f194
AK		 7297}
7298
716d51ab 7299
b6c7a5dc
HB		 7300int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7301{
7302 int r;
b6c7a5dc 7303
accb757d 7304 vcpu_load(vcpu);
20b7035c 7305 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7306 kvm_load_guest_fpu(vcpu);
7307
a4535290 7308 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7309 if (kvm_run->immediate_exit) {
7310 r = -EINTR;
7311 goto out;
7312 }
b6c7a5dc 7313 kvm_vcpu_block(vcpu);
66450a21 7314 kvm_apic_accept_events(vcpu);
72875d8a 7315 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7316 r = -EAGAIN;
a0595000
JS		 7317 if (signal_pending(current)) {
7318 r = -EINTR;
7319 vcpu->run->exit_reason = KVM_EXIT_INTR;
7320 ++vcpu->stat.signal_exits;
7321 }
ac9f6dc0 7322 goto out;
b6c7a5dc
HB		 7323 }
7324
b6c7a5dc 7325 /* re-sync apic's tpr */
35754c98 7326 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7327 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7328 r = -EINVAL;
7329 goto out;
7330 }
7331 }
b6c7a5dc 7332
716d51ab
GN		 7333 if (unlikely(vcpu->arch.complete_userspace_io)) {
7334 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7335 vcpu->arch.complete_userspace_io = NULL;
7336 r = cui(vcpu);
7337 if (r <= 0)
5663d8f9 7338 goto out;
716d51ab
GN		 7339 } else
7340 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7341
460df4c1
PB		 7342 if (kvm_run->immediate_exit)
7343 r = -EINTR;
7344 else
7345 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7346
7347out:
5663d8f9 7348 kvm_put_guest_fpu(vcpu);
f1d86e46 7349 post_kvm_run_save(vcpu);
20b7035c 7350 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7351
accb757d 7352 vcpu_put(vcpu);
b6c7a5dc
HB		 7353 return r;
7354}
7355
7356int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7357{
1fc9b76b
CD		 7358 vcpu_load(vcpu);
7359
7ae441ea
GN		 7360 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7361 /*
7362 * We are here if userspace calls get_regs() in the middle of
7363 * instruction emulation. Registers state needs to be copied
4a969980 7364 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7365 * that usually, but some bad designed PV devices (vmware
7366 * backdoor interface) need this to work
7367 */
dd856efa 7368 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7369 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7370 }
5fdbf976
MT		 7371 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7372 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7373 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7374 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7375 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7376 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7377 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7378 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7379#ifdef CONFIG_X86_64
5fdbf976
MT		 7380 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7381 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7382 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7383 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7384 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7385 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7386 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7387 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7388#endif
7389
5fdbf976 7390 regs->rip = kvm_rip_read(vcpu);
91586a3b 7391 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7392
1fc9b76b 7393 vcpu_put(vcpu);
b6c7a5dc
HB		 7394 return 0;
7395}
7396
7397int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7398{
875656fe
CD		 7399 vcpu_load(vcpu);
7400
7ae441ea
GN		 7401 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7402 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7403
5fdbf976
MT		 7404 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7405 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7406 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7407 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7408 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7409 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7410 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7411 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7412#ifdef CONFIG_X86_64
5fdbf976
MT		 7413 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7414 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7415 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7416 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7417 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7418 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7419 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7420 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7421#endif
7422
5fdbf976 7423 kvm_rip_write(vcpu, regs->rip);
d73235d1 7424 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7425
b4f14abd
JK		 7426 vcpu->arch.exception.pending = false;
7427
3842d135
AK		 7428 kvm_make_request(KVM_REQ_EVENT, vcpu);
7429
875656fe 7430 vcpu_put(vcpu);
b6c7a5dc
HB		 7431 return 0;
7432}
7433
b6c7a5dc
HB		 7434void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7435{
7436 struct kvm_segment cs;
7437
3e6e0aab 7438 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7439 *db = cs.db;
7440 *l = cs.l;
7441}
7442EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7443
7444int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7445 struct kvm_sregs *sregs)
7446{
89a27f4d 7447 struct desc_ptr dt;
b6c7a5dc 7448
bcdec41c
CD		 7449 vcpu_load(vcpu);
7450
3e6e0aab
GT		 7451 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7452 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7453 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7454 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7455 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7456 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7457
3e6e0aab
GT		 7458 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7459 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7460
7461 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7462 sregs->idt.limit = dt.size;
7463 sregs->idt.base = dt.address;
b6c7a5dc 7464 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7465 sregs->gdt.limit = dt.size;
7466 sregs->gdt.base = dt.address;
b6c7a5dc 7467
4d4ec087 7468 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7469 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7470 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7471 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7472 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7473 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7474 sregs->apic_base = kvm_get_apic_base(vcpu);
7475
923c61bb 7476 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7477
36752c9b 7478 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7479 set_bit(vcpu->arch.interrupt.nr,
7480 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7481
bcdec41c 7482 vcpu_put(vcpu);
b6c7a5dc
HB		 7483 return 0;
7484}
7485
62d9f0db
MT		 7486int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7487 struct kvm_mp_state *mp_state)
7488{
fd232561
CD		 7489 vcpu_load(vcpu);
7490
66450a21 7491 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7492 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7493 vcpu->arch.pv.pv_unhalted)
7494 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7495 else
7496 mp_state->mp_state = vcpu->arch.mp_state;
7497
fd232561 7498 vcpu_put(vcpu);
62d9f0db
MT		 7499 return 0;
7500}
7501
7502int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7503 struct kvm_mp_state *mp_state)
7504{
e83dff5e
CD		 7505 int ret = -EINVAL;
7506
7507 vcpu_load(vcpu);
7508
bce87cce 7509 if (!lapic_in_kernel(vcpu) &&
66450a21 7510 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7511 goto out;
66450a21 7512
28bf2888
DH		 7513 /* INITs are latched while in SMM */
7514 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7515 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7516 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7517 goto out;
28bf2888 7518
66450a21
JK		 7519 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7520 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7521 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7522 } else
7523 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7524 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7525
7526 ret = 0;
7527out:
7528 vcpu_put(vcpu);
7529 return ret;
62d9f0db
MT		 7530}
7531
7f3d35fd
KW		 7532int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7533 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7534{
9d74191a 7535 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7536 int ret;
e01c2426 7537
8ec4722d 7538 init_emulate_ctxt(vcpu);
c697518a 7539
7f3d35fd 7540 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7541 has_error_code, error_code);
c697518a 7542
c697518a 7543 if (ret)
19d04437 7544 return EMULATE_FAIL;
37817f29 7545
9d74191a
TY		 7546 kvm_rip_write(vcpu, ctxt->eip);
7547 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7548 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7549 return EMULATE_DONE;
37817f29
IE		 7550}
7551EXPORT_SYMBOL_GPL(kvm_task_switch);
7552
b6c7a5dc
HB		 7553int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7554 struct kvm_sregs *sregs)
7555{
58cb628d 7556 struct msr_data apic_base_msr;
b6c7a5dc 7557 int mmu_reset_needed = 0;
63f42e02 7558 int pending_vec, max_bits, idx;
89a27f4d 7559 struct desc_ptr dt;
b4ef9d4e
CD		 7560 int ret = -EINVAL;
7561
7562 vcpu_load(vcpu);
b6c7a5dc 7563
d6321d49
RK		 7564 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7565 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7566 goto out;
6d1068b3 7567
d3802286
JM		 7568 apic_base_msr.data = sregs->apic_base;
7569 apic_base_msr.host_initiated = true;
7570 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7571 goto out;
6d1068b3 7572
89a27f4d
GN		 7573 dt.size = sregs->idt.limit;
7574 dt.address = sregs->idt.base;
b6c7a5dc 7575 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7576 dt.size = sregs->gdt.limit;
7577 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7578 kvm_x86_ops->set_gdt(vcpu, &dt);
7579
ad312c7c 7580 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7581 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7582 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7583 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7584
2d3ad1f4 7585 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7586
f6801dff 7587 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7588 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7589
4d4ec087 7590 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7591 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7592 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7593
fc78f519 7594 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7595 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7596 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7597 kvm_update_cpuid(vcpu);
63f42e02
XG		 7598
7599 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7600 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7601 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7602 mmu_reset_needed = 1;
7603 }
63f42e02 7604 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7605
7606 if (mmu_reset_needed)
7607 kvm_mmu_reset_context(vcpu);
7608
a50abc3b 7609 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7610 pending_vec = find_first_bit(
7611 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7612 if (pending_vec < max_bits) {
66fd3f7f 7613 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7614 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7615 }
7616
3e6e0aab
GT		 7617 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7618 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7619 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7620 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7621 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7622 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7623
3e6e0aab
GT		 7624 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7625 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7626
5f0269f5
ME		 7627 update_cr8_intercept(vcpu);
7628
9c3e4aab 7629 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7630 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7631 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7632 !is_protmode(vcpu))
9c3e4aab
MT		 7633 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7634
3842d135
AK		 7635 kvm_make_request(KVM_REQ_EVENT, vcpu);
7636
b4ef9d4e
CD		 7637 ret = 0;
7638out:
7639 vcpu_put(vcpu);
7640 return ret;
b6c7a5dc
HB		 7641}
7642
d0bfb940
JK		 7643int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7644 struct kvm_guest_debug *dbg)
b6c7a5dc 7645{
355be0b9 7646 unsigned long rflags;
ae675ef0 7647 int i, r;
b6c7a5dc 7648
66b56562
CD		 7649 vcpu_load(vcpu);
7650
4f926bf2
JK		 7651 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7652 r = -EBUSY;
7653 if (vcpu->arch.exception.pending)
2122ff5e 7654 goto out;
4f926bf2
JK		 7655 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7656 kvm_queue_exception(vcpu, DB_VECTOR);
7657 else
7658 kvm_queue_exception(vcpu, BP_VECTOR);
7659 }
7660
91586a3b
JK		 7661 /*
7662 * Read rflags as long as potentially injected trace flags are still
7663 * filtered out.
7664 */
7665 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7666
7667 vcpu->guest_debug = dbg->control;
7668 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7669 vcpu->guest_debug = 0;
7670
7671 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7672 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7673 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7674 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7675 } else {
7676 for (i = 0; i < KVM_NR_DB_REGS; i++)
7677 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7678 }
c8639010 7679 kvm_update_dr7(vcpu);
ae675ef0 7680
f92653ee
JK		 7681 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7682 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7683 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7684
91586a3b
JK		 7685 /*
7686 * Trigger an rflags update that will inject or remove the trace
7687 * flags.
7688 */
7689 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7690
a96036b8 7691 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7692
4f926bf2 7693 r = 0;
d0bfb940 7694
2122ff5e 7695out:
66b56562 7696 vcpu_put(vcpu);
b6c7a5dc
HB		 7697 return r;
7698}
7699
8b006791
ZX		 7700/*
7701 * Translate a guest virtual address to a guest physical address.
7702 */
7703int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7704 struct kvm_translation *tr)
7705{
7706 unsigned long vaddr = tr->linear_address;
7707 gpa_t gpa;
f656ce01 7708 int idx;
8b006791 7709
1da5b61d
CD		 7710 vcpu_load(vcpu);
7711
f656ce01 7712 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7713 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7714 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7715 tr->physical_address = gpa;
7716 tr->valid = gpa != UNMAPPED_GVA;
7717 tr->writeable = 1;
7718 tr->usermode = 0;
8b006791 7719
1da5b61d 7720 vcpu_put(vcpu);
8b006791
ZX		 7721 return 0;
7722}
7723
d0752060
HB		 7724int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7725{
1393123e 7726 struct fxregs_state *fxsave;
d0752060 7727
1393123e
CD		 7728 vcpu_load(vcpu);
7729
7730 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 7731 memcpy(fpu->fpr, fxsave->st_space, 128);
7732 fpu->fcw = fxsave->cwd;
7733 fpu->fsw = fxsave->swd;
7734 fpu->ftwx = fxsave->twd;
7735 fpu->last_opcode = fxsave->fop;
7736 fpu->last_ip = fxsave->rip;
7737 fpu->last_dp = fxsave->rdp;
7738 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7739
1393123e 7740 vcpu_put(vcpu);
d0752060
HB		 7741 return 0;
7742}
7743
7744int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7745{
6a96bc7f
CD		 7746 struct fxregs_state *fxsave;
7747
7748 vcpu_load(vcpu);
7749
7750 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7751
d0752060
HB		 7752 memcpy(fxsave->st_space, fpu->fpr, 128);
7753 fxsave->cwd = fpu->fcw;
7754 fxsave->swd = fpu->fsw;
7755 fxsave->twd = fpu->ftwx;
7756 fxsave->fop = fpu->last_opcode;
7757 fxsave->rip = fpu->last_ip;
7758 fxsave->rdp = fpu->last_dp;
7759 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7760
6a96bc7f 7761 vcpu_put(vcpu);
d0752060
HB		 7762 return 0;
7763}
7764
0ee6a517 7765static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7766{
bf935b0b 7767 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7768 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7769 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7770 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7771
2acf923e
DC		 7772 /*
7773 * Ensure guest xcr0 is valid for loading
7774 */
d91cab78 7775 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7776
ad312c7c 7777 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7778}
d0752060 7779
f775b13e 7780/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7781void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7782{
f775b13e
RR		 7783 preempt_disable();
7784 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7785 /* PKRU is separately restored in kvm_x86_ops->run. */
7786 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7787 ~XFEATURE_MASK_PKRU);
f775b13e 7788 preempt_enable();
0c04851c 7789 trace_kvm_fpu(1);
d0752060 7790}
d0752060 7791
f775b13e 7792/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 7793void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7794{
f775b13e 7795 preempt_disable();
4f836347 7796 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 7797 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7798 preempt_enable();
f096ed85 7799 ++vcpu->stat.fpu_reload;
0c04851c 7800 trace_kvm_fpu(0);
d0752060 7801}
e9b11c17
ZX		 7802
7803void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7804{
bd768e14
IY		 7805 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7806
12f9a48f 7807 kvmclock_reset(vcpu);
7f1ea208 7808
e9b11c17 7809 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7810 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7811}
7812
7813struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7814 unsigned int id)
7815{
c447e76b
LL		 7816 struct kvm_vcpu *vcpu;
7817
6755bae8
ZA		 7818 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7819 printk_once(KERN_WARNING
7820 "kvm: SMP vm created on host with unstable TSC; "
7821 "guest TSC will not be reliable\n");
c447e76b
LL		 7822
7823 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7824
c447e76b 7825 return vcpu;
26e5215f 7826}
e9b11c17 7827
26e5215f
AK		 7828int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7829{
19efffa2 7830 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 7831 vcpu_load(vcpu);
d28bc9dd 7832 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7833 kvm_mmu_setup(vcpu);
e9b11c17 7834 vcpu_put(vcpu);
ec7660cc 7835 return 0;
e9b11c17
ZX		 7836}
7837
31928aa5 7838void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7839{
8fe8ab46 7840 struct msr_data msr;
332967a3 7841 struct kvm *kvm = vcpu->kvm;
42897d86 7842
d3457c87
RK		 7843 kvm_hv_vcpu_postcreate(vcpu);
7844
ec7660cc 7845 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 7846 return;
ec7660cc 7847 vcpu_load(vcpu);
8fe8ab46
WA		 7848 msr.data = 0x0;
7849 msr.index = MSR_IA32_TSC;
7850 msr.host_initiated = true;
7851 kvm_write_tsc(vcpu, &msr);
42897d86 7852 vcpu_put(vcpu);
ec7660cc 7853 mutex_unlock(&vcpu->mutex);
42897d86 7854
630994b3
MT		 7855 if (!kvmclock_periodic_sync)
7856 return;
7857
332967a3
AJ		 7858 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7859 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7860}
7861
d40ccc62 7862void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7863{
344d9588
GN		 7864 vcpu->arch.apf.msr_val = 0;
7865
ec7660cc 7866 vcpu_load(vcpu);
e9b11c17
ZX		 7867 kvm_mmu_unload(vcpu);
7868 vcpu_put(vcpu);
7869
7870 kvm_x86_ops->vcpu_free(vcpu);
7871}
7872
d28bc9dd 7873void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7874{
e69fab5d
PB		 7875 vcpu->arch.hflags = 0;
7876
c43203ca 7877 vcpu->arch.smi_pending = 0;
52797bf9 7878 vcpu->arch.smi_count = 0;
7460fb4a
AK		 7879 atomic_set(&vcpu->arch.nmi_queued, 0);
7880 vcpu->arch.nmi_pending = 0;
448fa4a9 7881 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7882 kvm_clear_interrupt_queue(vcpu);
7883 kvm_clear_exception_queue(vcpu);
664f8e26 7884 vcpu->arch.exception.pending = false;
448fa4a9 7885
42dbaa5a 7886 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7887 kvm_update_dr0123(vcpu);
6f43ed01 7888 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7889 kvm_update_dr6(vcpu);
42dbaa5a 7890 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7891 kvm_update_dr7(vcpu);
42dbaa5a 7892
1119022c
NA		 7893 vcpu->arch.cr2 = 0;
7894
3842d135 7895 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7896 vcpu->arch.apf.msr_val = 0;
c9aaa895 7897 vcpu->arch.st.msr_val = 0;
3842d135 7898
12f9a48f
GC		 7899 kvmclock_reset(vcpu);
7900
af585b92
GN		 7901 kvm_clear_async_pf_completion_queue(vcpu);
7902 kvm_async_pf_hash_reset(vcpu);
7903 vcpu->arch.apf.halted = false;
3842d135 7904
a554d207
WL		 7905 if (kvm_mpx_supported()) {
7906 void *mpx_state_buffer;
7907
7908 /*
7909 * To avoid have the INIT path from kvm_apic_has_events() that be
7910 * called with loaded FPU and does not let userspace fix the state.
7911 */
f775b13e
RR		 7912 if (init_event)
7913 kvm_put_guest_fpu(vcpu);
a554d207
WL		 7914 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7915 XFEATURE_MASK_BNDREGS);
7916 if (mpx_state_buffer)
7917 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7918 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7919 XFEATURE_MASK_BNDCSR);
7920 if (mpx_state_buffer)
7921 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 7922 if (init_event)
7923 kvm_load_guest_fpu(vcpu);
a554d207
WL		 7924 }
7925
64d60670 7926 if (!init_event) {
d28bc9dd 7927 kvm_pmu_reset(vcpu);
64d60670 7928 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7929
7930 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7931 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7932
7933 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7934 }
f5132b01 7935
66f7b72e
JS		 7936 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7937 vcpu->arch.regs_avail = ~0;
7938 vcpu->arch.regs_dirty = ~0;
7939
a554d207
WL		 7940 vcpu->arch.ia32_xss = 0;
7941
d28bc9dd 7942 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7943}
7944
2b4a273b 7945void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7946{
7947 struct kvm_segment cs;
7948
7949 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7950 cs.selector = vector << 8;
7951 cs.base = vector << 12;
7952 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7953 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7954}
7955
13a34e06 7956int kvm_arch_hardware_enable(void)
e9b11c17 7957{
ca84d1a2
ZA		 7958 struct kvm *kvm;
7959 struct kvm_vcpu *vcpu;
7960 int i;
0dd6a6ed
ZA		 7961 int ret;
7962 u64 local_tsc;
7963 u64 max_tsc = 0;
7964 bool stable, backwards_tsc = false;
18863bdd
AK		 7965
7966 kvm_shared_msr_cpu_online();
13a34e06 7967 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7968 if (ret != 0)
7969 return ret;
7970
4ea1636b 7971 local_tsc = rdtsc();
0dd6a6ed
ZA		 7972 stable = !check_tsc_unstable();
7973 list_for_each_entry(kvm, &vm_list, vm_list) {
7974 kvm_for_each_vcpu(i, vcpu, kvm) {
7975 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7976 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7977 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7978 backwards_tsc = true;
7979 if (vcpu->arch.last_host_tsc > max_tsc)
7980 max_tsc = vcpu->arch.last_host_tsc;
7981 }
7982 }
7983 }
7984
7985 /*
7986 * Sometimes, even reliable TSCs go backwards. This happens on
7987 * platforms that reset TSC during suspend or hibernate actions, but
7988 * maintain synchronization. We must compensate. Fortunately, we can
7989 * detect that condition here, which happens early in CPU bringup,
7990 * before any KVM threads can be running. Unfortunately, we can't
7991 * bring the TSCs fully up to date with real time, as we aren't yet far
7992 * enough into CPU bringup that we know how much real time has actually
108b249c 7993 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7994 * variables that haven't been updated yet.
7995 *
7996 * So we simply find the maximum observed TSC above, then record the
7997 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7998 * the adjustment will be applied. Note that we accumulate
7999 * adjustments, in case multiple suspend cycles happen before some VCPU
8000 * gets a chance to run again. In the event that no KVM threads get a
8001 * chance to run, we will miss the entire elapsed period, as we'll have
8002 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8003 * loose cycle time. This isn't too big a deal, since the loss will be
8004 * uniform across all VCPUs (not to mention the scenario is extremely
8005 * unlikely). It is possible that a second hibernate recovery happens
8006 * much faster than a first, causing the observed TSC here to be
8007 * smaller; this would require additional padding adjustment, which is
8008 * why we set last_host_tsc to the local tsc observed here.
8009 *
8010 * N.B. - this code below runs only on platforms with reliable TSC,
8011 * as that is the only way backwards_tsc is set above. Also note
8012 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8013 * have the same delta_cyc adjustment applied if backwards_tsc
8014 * is detected. Note further, this adjustment is only done once,
8015 * as we reset last_host_tsc on all VCPUs to stop this from being
8016 * called multiple times (one for each physical CPU bringup).
8017 *
4a969980 8018 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8019 * will be compensated by the logic in vcpu_load, which sets the TSC to
8020 * catchup mode. This will catchup all VCPUs to real time, but cannot
8021 * guarantee that they stay in perfect synchronization.
8022 */
8023 if (backwards_tsc) {
8024 u64 delta_cyc = max_tsc - local_tsc;
8025 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8026 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8027 kvm_for_each_vcpu(i, vcpu, kvm) {
8028 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8029 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8030 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8031 }
8032
8033 /*
8034 * We have to disable TSC offset matching.. if you were
8035 * booting a VM while issuing an S4 host suspend....
8036 * you may have some problem. Solving this issue is
8037 * left as an exercise to the reader.
8038 */
8039 kvm->arch.last_tsc_nsec = 0;
8040 kvm->arch.last_tsc_write = 0;
8041 }
8042
8043 }
8044 return 0;
e9b11c17
ZX		 8045}
8046
13a34e06 8047void kvm_arch_hardware_disable(void)
e9b11c17 8048{
13a34e06
RK		 8049 kvm_x86_ops->hardware_disable();
8050 drop_user_return_notifiers();
e9b11c17
ZX		 8051}
8052
8053int kvm_arch_hardware_setup(void)
8054{
9e9c3fe4
NA		 8055 int r;
8056
8057 r = kvm_x86_ops->hardware_setup();
8058 if (r != 0)
8059 return r;
8060
35181e86
HZ		 8061 if (kvm_has_tsc_control) {
8062 /*
8063 * Make sure the user can only configure tsc_khz values that
8064 * fit into a signed integer.
8065 * A min value is not calculated needed because it will always
8066 * be 1 on all machines.
8067 */
8068 u64 max = min(0x7fffffffULL,
8069 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8070 kvm_max_guest_tsc_khz = max;
8071
ad721883 8072 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8073 }
ad721883 8074
9e9c3fe4
NA		 8075 kvm_init_msr_list();
8076 return 0;
e9b11c17
ZX		 8077}
8078
8079void kvm_arch_hardware_unsetup(void)
8080{
8081 kvm_x86_ops->hardware_unsetup();
8082}
8083
8084void kvm_arch_check_processor_compat(void *rtn)
8085{
8086 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8087}
8088
8089bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8090{
8091 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8092}
8093EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8094
8095bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8096{
8097 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8098}
8099
54e9818f 8100struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8101EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8102
e9b11c17
ZX		 8103int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8104{
8105 struct page *page;
e9b11c17
ZX		 8106 int r;
8107
b2a05fef 8108 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8109 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8110 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8111 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8112 else
a4535290 8113 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8114
8115 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8116 if (!page) {
8117 r = -ENOMEM;
8118 goto fail;
8119 }
ad312c7c 8120 vcpu->arch.pio_data = page_address(page);
e9b11c17 8121
cc578287 8122 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8123
e9b11c17
ZX		 8124 r = kvm_mmu_create(vcpu);
8125 if (r < 0)
8126 goto fail_free_pio_data;
8127
26de7988 8128 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8129 r = kvm_create_lapic(vcpu);
8130 if (r < 0)
8131 goto fail_mmu_destroy;
54e9818f
GN		 8132 } else
8133 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8134
890ca9ae
HY		 8135 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8136 GFP_KERNEL);
8137 if (!vcpu->arch.mce_banks) {
8138 r = -ENOMEM;
443c39bc 8139 goto fail_free_lapic;
890ca9ae
HY		 8140 }
8141 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8142
f1797359
WY		 8143 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8144 r = -ENOMEM;
f5f48ee1 8145 goto fail_free_mce_banks;
f1797359 8146 }
f5f48ee1 8147
0ee6a517 8148 fx_init(vcpu);
66f7b72e 8149
4344ee98 8150 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8151
5a4f55cd
EK		 8152 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8153
74545705
RK		 8154 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8155
af585b92 8156 kvm_async_pf_hash_reset(vcpu);
f5132b01 8157 kvm_pmu_init(vcpu);
af585b92 8158
1c1a9ce9 8159 vcpu->arch.pending_external_vector = -1;
de63ad4c 8160 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8161
5c919412
AS		 8162 kvm_hv_vcpu_init(vcpu);
8163
e9b11c17 8164 return 0;
0ee6a517 8165
f5f48ee1
SY		 8166fail_free_mce_banks:
8167 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8168fail_free_lapic:
8169 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8170fail_mmu_destroy:
8171 kvm_mmu_destroy(vcpu);
8172fail_free_pio_data:
ad312c7c 8173 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8174fail:
8175 return r;
8176}
8177
8178void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8179{
f656ce01
MT		 8180 int idx;
8181
1f4b34f8 8182 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8183 kvm_pmu_destroy(vcpu);
36cb93fd 8184 kfree(vcpu->arch.mce_banks);
e9b11c17 8185 kvm_free_lapic(vcpu);
f656ce01 8186 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8187 kvm_mmu_destroy(vcpu);
f656ce01 8188 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8189 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8190 if (!lapic_in_kernel(vcpu))
54e9818f 8191 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8192}
d19a9cd2 8193
e790d9ef
RK		 8194void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8195{
ae97a3b8 8196 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8197}
8198
e08b9637 8199int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8200{
e08b9637
CO		 8201 if (type)
8202 return -EINVAL;
8203
6ef768fa 8204 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8205 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8206 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8207 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8208 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8209
5550af4d
SY		 8210 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8211 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8212 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8213 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8214 &kvm->arch.irq_sources_bitmap);
5550af4d 8215
038f8c11 8216 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8217 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8218 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8219 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8220
108b249c 8221 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8222 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8223
7e44e449 8224 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8225 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8226
0eb05bf2 8227 kvm_page_track_init(kvm);
13d268ca 8228 kvm_mmu_init_vm(kvm);
0eb05bf2 8229
03543133
SS		 8230 if (kvm_x86_ops->vm_init)
8231 return kvm_x86_ops->vm_init(kvm);
8232
d89f5eff 8233 return 0;
d19a9cd2
ZX		 8234}
8235
8236static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8237{
ec7660cc 8238 vcpu_load(vcpu);
d19a9cd2
ZX		 8239 kvm_mmu_unload(vcpu);
8240 vcpu_put(vcpu);
8241}
8242
8243static void kvm_free_vcpus(struct kvm *kvm)
8244{
8245 unsigned int i;
988a2cae 8246 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8247
8248 /*
8249 * Unpin any mmu pages first.
8250 */
af585b92
GN		 8251 kvm_for_each_vcpu(i, vcpu, kvm) {
8252 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8253 kvm_unload_vcpu_mmu(vcpu);
af585b92 8254 }
988a2cae
GN		 8255 kvm_for_each_vcpu(i, vcpu, kvm)
8256 kvm_arch_vcpu_free(vcpu);
8257
8258 mutex_lock(&kvm->lock);
8259 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8260 kvm->vcpus[i] = NULL;
d19a9cd2 8261
988a2cae
GN		 8262 atomic_set(&kvm->online_vcpus, 0);
8263 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8264}
8265
ad8ba2cd
SY		 8266void kvm_arch_sync_events(struct kvm *kvm)
8267{
332967a3 8268 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8269 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8270 kvm_free_pit(kvm);
ad8ba2cd
SY		 8271}
8272
1d8007bd 8273int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8274{
8275 int i, r;
25188b99 8276 unsigned long hva;
f0d648bd
PB		 8277 struct kvm_memslots *slots = kvm_memslots(kvm);
8278 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8279
8280 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8281 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8282 return -EINVAL;
9da0e4d5 8283
f0d648bd
PB		 8284 slot = id_to_memslot(slots, id);
8285 if (size) {
b21629da 8286 if (slot->npages)
f0d648bd
PB		 8287 return -EEXIST;
8288
8289 /*
8290 * MAP_SHARED to prevent internal slot pages from being moved
8291 * by fork()/COW.
8292 */
8293 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8294 MAP_SHARED | MAP_ANONYMOUS, 0);
8295 if (IS_ERR((void *)hva))
8296 return PTR_ERR((void *)hva);
8297 } else {
8298 if (!slot->npages)
8299 return 0;
8300
8301 hva = 0;
8302 }
8303
8304 old = *slot;
9da0e4d5 8305 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8306 struct kvm_userspace_memory_region m;
9da0e4d5 8307
1d8007bd
PB		 8308 m.slot = id | (i << 16);
8309 m.flags = 0;
8310 m.guest_phys_addr = gpa;
f0d648bd 8311 m.userspace_addr = hva;
1d8007bd 8312 m.memory_size = size;
9da0e4d5
PB		 8313 r = __kvm_set_memory_region(kvm, &m);
8314 if (r < 0)
8315 return r;
8316 }
8317
f0d648bd
PB		 8318 if (!size) {
8319 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8320 WARN_ON(r < 0);
8321 }
8322
9da0e4d5
PB		 8323 return 0;
8324}
8325EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8326
1d8007bd 8327int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8328{
8329 int r;
8330
8331 mutex_lock(&kvm->slots_lock);
1d8007bd 8332 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8333 mutex_unlock(&kvm->slots_lock);
8334
8335 return r;
8336}
8337EXPORT_SYMBOL_GPL(x86_set_memory_region);
8338
d19a9cd2
ZX		 8339void kvm_arch_destroy_vm(struct kvm *kvm)
8340{
27469d29
AH		 8341 if (current->mm == kvm->mm) {
8342 /*
8343 * Free memory regions allocated on behalf of userspace,
8344 * unless the the memory map has changed due to process exit
8345 * or fd copying.
8346 */
1d8007bd
PB		 8347 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8348 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8349 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8350 }
03543133
SS		 8351 if (kvm_x86_ops->vm_destroy)
8352 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8353 kvm_pic_destroy(kvm);
8354 kvm_ioapic_destroy(kvm);
d19a9cd2 8355 kvm_free_vcpus(kvm);
af1bae54 8356 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8357 kvm_mmu_uninit_vm(kvm);
2beb6dad 8358 kvm_page_track_cleanup(kvm);
d19a9cd2 8359}
0de10343 8360
5587027c 8361void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8362 struct kvm_memory_slot *dont)
8363{
8364 int i;
8365
d89cc617
TY		 8366 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8367 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8368 kvfree(free->arch.rmap[i]);
d89cc617 8369 free->arch.rmap[i] = NULL;
77d11309 8370 }
d89cc617
TY		 8371 if (i == 0)
8372 continue;
8373
8374 if (!dont || free->arch.lpage_info[i - 1] !=
8375 dont->arch.lpage_info[i - 1]) {
548ef284 8376 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8377 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8378 }
8379 }
21ebbeda
XG		 8380
8381 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8382}
8383
5587027c
AK		 8384int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8385 unsigned long npages)
db3fe4eb
TY		 8386{
8387 int i;
8388
d89cc617 8389 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8390 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8391 unsigned long ugfn;
8392 int lpages;
d89cc617 8393 int level = i + 1;
db3fe4eb
TY		 8394
8395 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8396 slot->base_gfn, level) + 1;
8397
d89cc617 8398 slot->arch.rmap[i] =
a7c3e901 8399 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8400 if (!slot->arch.rmap[i])
77d11309 8401 goto out_free;
d89cc617
TY		 8402 if (i == 0)
8403 continue;
77d11309 8404
a7c3e901 8405 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8406 if (!linfo)
db3fe4eb
TY		 8407 goto out_free;
8408
92f94f1e
XG		 8409 slot->arch.lpage_info[i - 1] = linfo;
8410
db3fe4eb 8411 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8412 linfo[0].disallow_lpage = 1;
db3fe4eb 8413 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8414 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8415 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8416 /*
8417 * If the gfn and userspace address are not aligned wrt each
8418 * other, or if explicitly asked to, disable large page
8419 * support for this slot
8420 */
8421 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8422 !kvm_largepages_enabled()) {
8423 unsigned long j;
8424
8425 for (j = 0; j < lpages; ++j)
92f94f1e 8426 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8427 }
8428 }
8429
21ebbeda
XG		 8430 if (kvm_page_track_create_memslot(slot, npages))
8431 goto out_free;
8432
db3fe4eb
TY		 8433 return 0;
8434
8435out_free:
d89cc617 8436 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8437 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8438 slot->arch.rmap[i] = NULL;
8439 if (i == 0)
8440 continue;
8441
548ef284 8442 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8443 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8444 }
8445 return -ENOMEM;
8446}
8447
15f46015 8448void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8449{
e6dff7d1
TY		 8450 /*
8451 * memslots->generation has been incremented.
8452 * mmio generation may have reached its maximum value.
8453 */
54bf36aa 8454 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8455}
8456
f7784b8e
MT		 8457int kvm_arch_prepare_memory_region(struct kvm *kvm,
8458 struct kvm_memory_slot *memslot,
09170a49 8459 const struct kvm_userspace_memory_region *mem,
7b6195a9 8460 enum kvm_mr_change change)
0de10343 8461{
f7784b8e
MT		 8462 return 0;
8463}
8464
88178fd4
KH		 8465static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8466 struct kvm_memory_slot *new)
8467{
8468 /* Still write protect RO slot */
8469 if (new->flags & KVM_MEM_READONLY) {
8470 kvm_mmu_slot_remove_write_access(kvm, new);
8471 return;
8472 }
8473
8474 /*
8475 * Call kvm_x86_ops dirty logging hooks when they are valid.
8476 *
8477 * kvm_x86_ops->slot_disable_log_dirty is called when:
8478 *
8479 * - KVM_MR_CREATE with dirty logging is disabled
8480 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8481 *
8482 * The reason is, in case of PML, we need to set D-bit for any slots
8483 * with dirty logging disabled in order to eliminate unnecessary GPA
8484 * logging in PML buffer (and potential PML buffer full VMEXT). This
8485 * guarantees leaving PML enabled during guest's lifetime won't have
8486 * any additonal overhead from PML when guest is running with dirty
8487 * logging disabled for memory slots.
8488 *
8489 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8490 * to dirty logging mode.
8491 *
8492 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8493 *
8494 * In case of write protect:
8495 *
8496 * Write protect all pages for dirty logging.
8497 *
8498 * All the sptes including the large sptes which point to this
8499 * slot are set to readonly. We can not create any new large
8500 * spte on this slot until the end of the logging.
8501 *
8502 * See the comments in fast_page_fault().
8503 */
8504 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8505 if (kvm_x86_ops->slot_enable_log_dirty)
8506 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8507 else
8508 kvm_mmu_slot_remove_write_access(kvm, new);
8509 } else {
8510 if (kvm_x86_ops->slot_disable_log_dirty)
8511 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8512 }
8513}
8514
f7784b8e 8515void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8516 const struct kvm_userspace_memory_region *mem,
8482644a 8517 const struct kvm_memory_slot *old,
f36f3f28 8518 const struct kvm_memory_slot *new,
8482644a 8519 enum kvm_mr_change change)
f7784b8e 8520{
8482644a 8521 int nr_mmu_pages = 0;
f7784b8e 8522
48c0e4e9
XG		 8523 if (!kvm->arch.n_requested_mmu_pages)
8524 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8525
48c0e4e9 8526 if (nr_mmu_pages)
0de10343 8527 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8528
3ea3b7fa
WL		 8529 /*
8530 * Dirty logging tracks sptes in 4k granularity, meaning that large
8531 * sptes have to be split. If live migration is successful, the guest
8532 * in the source machine will be destroyed and large sptes will be
8533 * created in the destination. However, if the guest continues to run
8534 * in the source machine (for example if live migration fails), small
8535 * sptes will remain around and cause bad performance.
8536 *
8537 * Scan sptes if dirty logging has been stopped, dropping those
8538 * which can be collapsed into a single large-page spte. Later
8539 * page faults will create the large-page sptes.
8540 */
8541 if ((change != KVM_MR_DELETE) &&
8542 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8543 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8544 kvm_mmu_zap_collapsible_sptes(kvm, new);
8545
c972f3b1 8546 /*
88178fd4 8547 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8548 *
88178fd4
KH		 8549 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8550 * been zapped so no dirty logging staff is needed for old slot. For
8551 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8552 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8553 *
8554 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8555 */
88178fd4 8556 if (change != KVM_MR_DELETE)
f36f3f28 8557 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8558}
1d737c8a 8559
2df72e9b 8560void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8561{
6ca18b69 8562 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8563}
8564
2df72e9b
MT		 8565void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8566 struct kvm_memory_slot *slot)
8567{
ae7cd873 8568 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8569}
8570
5d9bc648
PB		 8571static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8572{
8573 if (!list_empty_careful(&vcpu->async_pf.done))
8574 return true;
8575
8576 if (kvm_apic_has_events(vcpu))
8577 return true;
8578
8579 if (vcpu->arch.pv.pv_unhalted)
8580 return true;
8581
a5f01f8e
WL		 8582 if (vcpu->arch.exception.pending)
8583 return true;
8584
47a66eed
Z		 8585 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8586 (vcpu->arch.nmi_pending &&
8587 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8588 return true;
8589
47a66eed
Z		 8590 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8591 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8592 return true;
8593
5d9bc648
PB		 8594 if (kvm_arch_interrupt_allowed(vcpu) &&
8595 kvm_cpu_has_interrupt(vcpu))
8596 return true;
8597
1f4b34f8
AS		 8598 if (kvm_hv_has_stimer_pending(vcpu))
8599 return true;
8600
5d9bc648
PB		 8601 return false;
8602}
8603
1d737c8a
ZX		 8604int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8605{
5d9bc648 8606 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8607}
5736199a 8608
199b5763
LM		 8609bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8610{
de63ad4c 8611 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8612}
8613
b6d33834 8614int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8615{
b6d33834 8616 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8617}
78646121
GN		 8618
8619int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8620{
8621 return kvm_x86_ops->interrupt_allowed(vcpu);
8622}
229456fc 8623
82b32774 8624unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8625{
82b32774
NA		 8626 if (is_64_bit_mode(vcpu))
8627 return kvm_rip_read(vcpu);
8628 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8629 kvm_rip_read(vcpu));
8630}
8631EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8632
82b32774
NA		 8633bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8634{
8635 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8636}
8637EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8638
94fe45da
JK		 8639unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8640{
8641 unsigned long rflags;
8642
8643 rflags = kvm_x86_ops->get_rflags(vcpu);
8644 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8645 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8646 return rflags;
8647}
8648EXPORT_SYMBOL_GPL(kvm_get_rflags);
8649
6addfc42 8650static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8651{
8652 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8653 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8654 rflags |= X86_EFLAGS_TF;
94fe45da 8655 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8656}
8657
8658void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8659{
8660 __kvm_set_rflags(vcpu, rflags);
3842d135 8661 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8662}
8663EXPORT_SYMBOL_GPL(kvm_set_rflags);
8664
56028d08
GN		 8665void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8666{
8667 int r;
8668
fb67e14f 8669 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8670 work->wakeup_all)
56028d08
GN		 8671 return;
8672
8673 r = kvm_mmu_reload(vcpu);
8674 if (unlikely(r))
8675 return;
8676
fb67e14f
XG		 8677 if (!vcpu->arch.mmu.direct_map &&
8678 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8679 return;
8680
56028d08
GN		 8681 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8682}
8683
af585b92
GN		 8684static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8685{
8686 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8687}
8688
8689static inline u32 kvm_async_pf_next_probe(u32 key)
8690{
8691 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8692}
8693
8694static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8695{
8696 u32 key = kvm_async_pf_hash_fn(gfn);
8697
8698 while (vcpu->arch.apf.gfns[key] != ~0)
8699 key = kvm_async_pf_next_probe(key);
8700
8701 vcpu->arch.apf.gfns[key] = gfn;
8702}
8703
8704static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8705{
8706 int i;
8707 u32 key = kvm_async_pf_hash_fn(gfn);
8708
8709 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8710 (vcpu->arch.apf.gfns[key] != gfn &&
8711 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8712 key = kvm_async_pf_next_probe(key);
8713
8714 return key;
8715}
8716
8717bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8718{
8719 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8720}
8721
8722static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8723{
8724 u32 i, j, k;
8725
8726 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8727 while (true) {
8728 vcpu->arch.apf.gfns[i] = ~0;
8729 do {
8730 j = kvm_async_pf_next_probe(j);
8731 if (vcpu->arch.apf.gfns[j] == ~0)
8732 return;
8733 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8734 /*
8735 * k lies cyclically in ]i,j]
8736 * | i.k.j |
8737 * |....j i.k.| or |.k..j i...|
8738 */
8739 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8740 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8741 i = j;
8742 }
8743}
8744
7c90705b
GN		 8745static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8746{
4e335d9e
PB		 8747
8748 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8749 sizeof(val));
7c90705b
GN		 8750}
8751
9a6e7c39
WL		 8752static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8753{
8754
8755 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8756 sizeof(u32));
8757}
8758
af585b92
GN		 8759void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8760 struct kvm_async_pf *work)
8761{
6389ee94
AK		 8762 struct x86_exception fault;
8763
7c90705b 8764 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8765 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8766
8767 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8768 (vcpu->arch.apf.send_user_only &&
8769 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8770 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8771 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8772 fault.vector = PF_VECTOR;
8773 fault.error_code_valid = true;
8774 fault.error_code = 0;
8775 fault.nested_page_fault = false;
8776 fault.address = work->arch.token;
adfe20fb 8777 fault.async_page_fault = true;
6389ee94 8778 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8779 }
af585b92
GN		 8780}
8781
8782void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8783 struct kvm_async_pf *work)
8784{
6389ee94 8785 struct x86_exception fault;
9a6e7c39 8786 u32 val;
6389ee94 8787
f2e10669 8788 if (work->wakeup_all)
7c90705b
GN		 8789 work->arch.token = ~0; /* broadcast wakeup */
8790 else
8791 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8792 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8793
9a6e7c39
WL		 8794 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8795 !apf_get_user(vcpu, &val)) {
8796 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8797 vcpu->arch.exception.pending &&
8798 vcpu->arch.exception.nr == PF_VECTOR &&
8799 !apf_put_user(vcpu, 0)) {
8800 vcpu->arch.exception.injected = false;
8801 vcpu->arch.exception.pending = false;
8802 vcpu->arch.exception.nr = 0;
8803 vcpu->arch.exception.has_error_code = false;
8804 vcpu->arch.exception.error_code = 0;
8805 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8806 fault.vector = PF_VECTOR;
8807 fault.error_code_valid = true;
8808 fault.error_code = 0;
8809 fault.nested_page_fault = false;
8810 fault.address = work->arch.token;
8811 fault.async_page_fault = true;
8812 kvm_inject_page_fault(vcpu, &fault);
8813 }
7c90705b 8814 }
e6d53e3b 8815 vcpu->arch.apf.halted = false;
a4fa1635 8816 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8817}
8818
8819bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8820{
8821 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8822 return true;
8823 else
9bc1f09f 8824 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8825}
8826
5544eb9b
PB		 8827void kvm_arch_start_assignment(struct kvm *kvm)
8828{
8829 atomic_inc(&kvm->arch.assigned_device_count);
8830}
8831EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8832
8833void kvm_arch_end_assignment(struct kvm *kvm)
8834{
8835 atomic_dec(&kvm->arch.assigned_device_count);
8836}
8837EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8838
8839bool kvm_arch_has_assigned_device(struct kvm *kvm)
8840{
8841 return atomic_read(&kvm->arch.assigned_device_count);
8842}
8843EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8844
e0f0bbc5
AW		 8845void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8846{
8847 atomic_inc(&kvm->arch.noncoherent_dma_count);
8848}
8849EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8850
8851void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8852{
8853 atomic_dec(&kvm->arch.noncoherent_dma_count);
8854}
8855EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8856
8857bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8858{
8859 return atomic_read(&kvm->arch.noncoherent_dma_count);
8860}
8861EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8862
14717e20
AW		 8863bool kvm_arch_has_irq_bypass(void)
8864{
8865 return kvm_x86_ops->update_pi_irte != NULL;
8866}
8867
87276880
FW		 8868int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8869 struct irq_bypass_producer *prod)
8870{
8871 struct kvm_kernel_irqfd *irqfd =
8872 container_of(cons, struct kvm_kernel_irqfd, consumer);
8873
14717e20 8874 irqfd->producer = prod;
87276880 8875
14717e20
AW		 8876 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8877 prod->irq, irqfd->gsi, 1);
87276880
FW		 8878}
8879
8880void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8881 struct irq_bypass_producer *prod)
8882{
8883 int ret;
8884 struct kvm_kernel_irqfd *irqfd =
8885 container_of(cons, struct kvm_kernel_irqfd, consumer);
8886
87276880
FW		 8887 WARN_ON(irqfd->producer != prod);
8888 irqfd->producer = NULL;
8889
8890 /*
8891 * When producer of consumer is unregistered, we change back to
8892 * remapped mode, so we can re-use the current implementation
bb3541f1 8893 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8894 * int this case doesn't want to receive the interrupts.
8895 */
8896 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8897 if (ret)
8898 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8899 " fails: %d\n", irqfd->consumer.token, ret);
8900}
8901
8902int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8903 uint32_t guest_irq, bool set)
8904{
8905 if (!kvm_x86_ops->update_pi_irte)
8906 return -EINVAL;
8907
8908 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8909}
8910
52004014
FW		 8911bool kvm_vector_hashing_enabled(void)
8912{
8913 return vector_hashing;
8914}
8915EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8916
229456fc 8917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8918EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8919EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8920EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8921EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8922EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8923EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8924EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8925EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8926EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8927EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8928EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8929EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8930EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8931EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8932EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8933EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8934EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8935EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)