projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'kvm-s390-20140715' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms39...
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
18863bdd
AK		 215 if (slot >= shared_msrs_global.nr)
216 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 217 shared_msrs_global.msrs[slot] = msr;
218 /* we need ensured the shared_msr_global have been updated */
219 smp_wmb();
18863bdd
AK		 220}
221EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
222
223static void kvm_shared_msr_cpu_online(void)
224{
225 unsigned i;
18863bdd
AK		 226
227 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 228 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 229}
230
d5696725 231void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 232{
013f6a5d
MT		 233 unsigned int cpu = smp_processor_id();
234 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 235
2bf78fa7 236 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 237 return;
2bf78fa7
SY		 238 smsr->values[slot].curr = value;
239 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 240 if (!smsr->registered) {
241 smsr->urn.on_user_return = kvm_on_user_return;
242 user_return_notifier_register(&smsr->urn);
243 smsr->registered = true;
244 }
245}
246EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
247
3548bab5
AK		 248static void drop_user_return_notifiers(void *ignore)
249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 252
253 if (smsr->registered)
254 kvm_on_user_return(&smsr->urn);
255}
256
6866b83e
CO		 257u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
258{
8a5a87d9 259 return vcpu->arch.apic_base;
6866b83e
CO		 260}
261EXPORT_SYMBOL_GPL(kvm_get_apic_base);
262
58cb628d
JK		 263int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
264{
265 u64 old_state = vcpu->arch.apic_base &
266 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
267 u64 new_state = msr_info->data &
268 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
269 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
270 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
271
272 if (!msr_info->host_initiated &&
273 ((msr_info->data & reserved_bits) != 0 ||
274 new_state == X2APIC_ENABLE ||
275 (new_state == MSR_IA32_APICBASE_ENABLE &&
276 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
277 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
278 old_state == 0)))
279 return 1;
280
281 kvm_lapic_set_base(vcpu, msr_info->data);
282 return 0;
6866b83e
CO		 283}
284EXPORT_SYMBOL_GPL(kvm_set_apic_base);
285
2605fc21 286asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 287{
288 /* Fault while not rebooting. We want the trace. */
289 BUG();
290}
291EXPORT_SYMBOL_GPL(kvm_spurious_fault);
292
3fd28fce
ED		 293#define EXCPT_BENIGN 0
294#define EXCPT_CONTRIBUTORY 1
295#define EXCPT_PF 2
296
297static int exception_class(int vector)
298{
299 switch (vector) {
300 case PF_VECTOR:
301 return EXCPT_PF;
302 case DE_VECTOR:
303 case TS_VECTOR:
304 case NP_VECTOR:
305 case SS_VECTOR:
306 case GP_VECTOR:
307 return EXCPT_CONTRIBUTORY;
308 default:
309 break;
310 }
311 return EXCPT_BENIGN;
312}
313
314static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 315 unsigned nr, bool has_error, u32 error_code,
316 bool reinject)
3fd28fce
ED		 317{
318 u32 prev_nr;
319 int class1, class2;
320
3842d135
AK		 321 kvm_make_request(KVM_REQ_EVENT, vcpu);
322
3fd28fce
ED		 323 if (!vcpu->arch.exception.pending) {
324 queue:
325 vcpu->arch.exception.pending = true;
326 vcpu->arch.exception.has_error_code = has_error;
327 vcpu->arch.exception.nr = nr;
328 vcpu->arch.exception.error_code = error_code;
3f0fd292 329 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 330 return;
331 }
332
333 /* to check exception */
334 prev_nr = vcpu->arch.exception.nr;
335 if (prev_nr == DF_VECTOR) {
336 /* triple fault -> shutdown */
a8eeb04a 337 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 338 return;
339 }
340 class1 = exception_class(prev_nr);
341 class2 = exception_class(nr);
342 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
343 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
344 /* generate double fault per SDM Table 5-5 */
345 vcpu->arch.exception.pending = true;
346 vcpu->arch.exception.has_error_code = true;
347 vcpu->arch.exception.nr = DF_VECTOR;
348 vcpu->arch.exception.error_code = 0;
349 } else
350 /* replace previous exception with a new one in a hope
351 that instruction re-execution will regenerate lost
352 exception */
353 goto queue;
354}
355
298101da
AK		 356void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
357{
ce7ddec4 358 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 359}
360EXPORT_SYMBOL_GPL(kvm_queue_exception);
361
ce7ddec4
JR		 362void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
363{
364 kvm_multiple_exception(vcpu, nr, false, 0, true);
365}
366EXPORT_SYMBOL_GPL(kvm_requeue_exception);
367
db8fcefa 368void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 369{
db8fcefa
AP		 370 if (err)
371 kvm_inject_gp(vcpu, 0);
372 else
373 kvm_x86_ops->skip_emulated_instruction(vcpu);
374}
375EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 376
6389ee94 377void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 378{
379 ++vcpu->stat.pf_guest;
6389ee94
AK		 380 vcpu->arch.cr2 = fault->address;
381 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 382}
27d6c865 383EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 384
6389ee94 385void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 386{
6389ee94
AK		 387 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
388 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 389 else
6389ee94 390 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 391}
392
3419ffc8
SY		 393void kvm_inject_nmi(struct kvm_vcpu *vcpu)
394{
7460fb4a
AK		 395 atomic_inc(&vcpu->arch.nmi_queued);
396 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 397}
398EXPORT_SYMBOL_GPL(kvm_inject_nmi);
399
298101da
AK		 400void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
401{
ce7ddec4 402 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 403}
404EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
405
ce7ddec4
JR		 406void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
407{
408 kvm_multiple_exception(vcpu, nr, true, error_code, true);
409}
410EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
411
0a79b009
AK		 412/*
413 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
414 * a #GP and return false.
415 */
416bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 417{
0a79b009
AK		 418 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
419 return true;
420 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
421 return false;
298101da 422}
0a79b009 423EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 424
ec92fe44
JR		 425/*
426 * This function will be used to read from the physical memory of the currently
427 * running guest. The difference to kvm_read_guest_page is that this function
428 * can read from guest physical or from the guest's guest physical memory.
429 */
430int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
431 gfn_t ngfn, void *data, int offset, int len,
432 u32 access)
433{
434 gfn_t real_gfn;
435 gpa_t ngpa;
436
437 ngpa = gfn_to_gpa(ngfn);
438 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
439 if (real_gfn == UNMAPPED_GVA)
440 return -EFAULT;
441
442 real_gfn = gpa_to_gfn(real_gfn);
443
444 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
445}
446EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
447
3d06b8bf
JR		 448int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
449 void *data, int offset, int len, u32 access)
450{
451 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
452 data, offset, len, access);
453}
454
a03490ed
CO		 455/*
456 * Load the pae pdptrs. Return true is they are all valid.
457 */
ff03a073 458int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 459{
460 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
461 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
462 int i;
463 int ret;
ff03a073 464 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 465
ff03a073
JR		 466 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
467 offset * sizeof(u64), sizeof(pdpte),
468 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 469 if (ret < 0) {
470 ret = 0;
471 goto out;
472 }
473 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 474 if (is_present_gpte(pdpte[i]) &&
20c466b5 475 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 476 ret = 0;
477 goto out;
478 }
479 }
480 ret = 1;
481
ff03a073 482 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 483 __set_bit(VCPU_EXREG_PDPTR,
484 (unsigned long *)&vcpu->arch.regs_avail);
485 __set_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 487out:
a03490ed
CO		 488
489 return ret;
490}
cc4b6871 491EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 492
d835dfec
AK		 493static bool pdptrs_changed(struct kvm_vcpu *vcpu)
494{
ff03a073 495 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 496 bool changed = true;
3d06b8bf
JR		 497 int offset;
498 gfn_t gfn;
d835dfec
AK		 499 int r;
500
501 if (is_long_mode(vcpu) || !is_pae(vcpu))
502 return false;
503
6de4f3ad
AK		 504 if (!test_bit(VCPU_EXREG_PDPTR,
505 (unsigned long *)&vcpu->arch.regs_avail))
506 return true;
507
9f8fe504
AK		 508 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
509 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 510 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
511 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 512 if (r < 0)
513 goto out;
ff03a073 514 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 515out:
d835dfec
AK		 516
517 return changed;
518}
519
49a9b07e 520int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 521{
aad82703
SY		 522 unsigned long old_cr0 = kvm_read_cr0(vcpu);
523 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
524 X86_CR0_CD | X86_CR0_NW;
525
f9a48e6a
AK		 526 cr0 |= X86_CR0_ET;
527
ab344828 528#ifdef CONFIG_X86_64
0f12244f
GN		 529 if (cr0 & 0xffffffff00000000UL)
530 return 1;
ab344828
GN		 531#endif
532
533 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
536 return 1;
a03490ed 537
0f12244f
GN		 538 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
539 return 1;
a03490ed
CO		 540
541 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
542#ifdef CONFIG_X86_64
f6801dff 543 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 544 int cs_db, cs_l;
545
0f12244f
GN		 546 if (!is_pae(vcpu))
547 return 1;
a03490ed 548 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 549 if (cs_l)
550 return 1;
a03490ed
CO		 551 } else
552#endif
ff03a073 553 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 554 kvm_read_cr3(vcpu)))
0f12244f 555 return 1;
a03490ed
CO		 556 }
557
ad756a16
MJ		 558 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
559 return 1;
560
a03490ed 561 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 562
d170c419 563 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 564 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 565 kvm_async_pf_hash_reset(vcpu);
566 }
e5f3f027 567
aad82703
SY		 568 if ((cr0 ^ old_cr0) & update_bits)
569 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 570 return 0;
571}
2d3ad1f4 572EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 573
2d3ad1f4 574void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 575{
49a9b07e 576 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 577}
2d3ad1f4 578EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 579
42bdf991
MT		 580static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
581{
582 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
583 !vcpu->guest_xcr0_loaded) {
584 /* kvm_set_xcr() also depends on this */
585 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
586 vcpu->guest_xcr0_loaded = 1;
587 }
588}
589
590static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
591{
592 if (vcpu->guest_xcr0_loaded) {
593 if (vcpu->arch.xcr0 != host_xcr0)
594 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
595 vcpu->guest_xcr0_loaded = 0;
596 }
597}
598
2acf923e
DC		 599int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
600{
56c103ec
LJ		 601 u64 xcr0 = xcr;
602 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 603 u64 valid_bits;
2acf923e
DC		 604
605 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
606 if (index != XCR_XFEATURE_ENABLED_MASK)
607 return 1;
2acf923e
DC		 608 if (!(xcr0 & XSTATE_FP))
609 return 1;
610 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
611 return 1;
46c34cb0
PB		 612
613 /*
614 * Do not allow the guest to set bits that we do not support
615 * saving. However, xcr0 bit 0 is always set, even if the
616 * emulated CPU does not support XSAVE (see fx_init).
617 */
618 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
619 if (xcr0 & ~valid_bits)
2acf923e 620 return 1;
46c34cb0 621
390bd528
LJ		 622 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
623 return 1;
624
42bdf991 625 kvm_put_guest_xcr0(vcpu);
2acf923e 626 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 627
628 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
629 kvm_update_cpuid(vcpu);
2acf923e
DC		 630 return 0;
631}
632
633int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
634{
764bcbc5
Z		 635 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
636 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 637 kvm_inject_gp(vcpu, 0);
638 return 1;
639 }
640 return 0;
641}
642EXPORT_SYMBOL_GPL(kvm_set_xcr);
643
a83b29c6 644int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 645{
fc78f519 646 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 647 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
648 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 649 if (cr4 & CR4_RESERVED_BITS)
650 return 1;
a03490ed 651
2acf923e
DC		 652 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
653 return 1;
654
c68b734f
YW		 655 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
656 return 1;
657
97ec8c06
FW		 658 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
659 return 1;
660
afcbf13f 661 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 662 return 1;
663
a03490ed 664 if (is_long_mode(vcpu)) {
0f12244f
GN		 665 if (!(cr4 & X86_CR4_PAE))
666 return 1;
a2edf57f
AK		 667 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
668 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 669 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
670 kvm_read_cr3(vcpu)))
0f12244f
GN		 671 return 1;
672
ad756a16
MJ		 673 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
674 if (!guest_cpuid_has_pcid(vcpu))
675 return 1;
676
677 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
678 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
679 return 1;
680 }
681
5e1746d6 682 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 683 return 1;
a03490ed 684
ad756a16
MJ		 685 if (((cr4 ^ old_cr4) & pdptr_bits) ||
686 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 687 kvm_mmu_reset_context(vcpu);
0f12244f 688
97ec8c06
FW		 689 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
690 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
691
2acf923e 692 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 693 kvm_update_cpuid(vcpu);
2acf923e 694
0f12244f
GN		 695 return 0;
696}
2d3ad1f4 697EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 698
2390218b 699int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 700{
9f8fe504 701 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 702 kvm_mmu_sync_roots(vcpu);
d835dfec 703 kvm_mmu_flush_tlb(vcpu);
0f12244f 704 return 0;
d835dfec
AK		 705 }
706
a03490ed 707 if (is_long_mode(vcpu)) {
d9f89b88
JK		 708 if (cr3 & CR3_L_MODE_RESERVED_BITS)
709 return 1;
710 } else if (is_pae(vcpu) && is_paging(vcpu) &&
711 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 712 return 1;
a03490ed 713
0f12244f 714 vcpu->arch.cr3 = cr3;
aff48baa 715 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 716 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 717 return 0;
718}
2d3ad1f4 719EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 720
eea1cff9 721int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 722{
0f12244f
GN		 723 if (cr8 & CR8_RESERVED_BITS)
724 return 1;
a03490ed
CO		 725 if (irqchip_in_kernel(vcpu->kvm))
726 kvm_lapic_set_tpr(vcpu, cr8);
727 else
ad312c7c 728 vcpu->arch.cr8 = cr8;
0f12244f
GN		 729 return 0;
730}
2d3ad1f4 731EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 732
2d3ad1f4 733unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 734{
735 if (irqchip_in_kernel(vcpu->kvm))
736 return kvm_lapic_get_cr8(vcpu);
737 else
ad312c7c 738 return vcpu->arch.cr8;
a03490ed 739}
2d3ad1f4 740EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 741
73aaf249
JK		 742static void kvm_update_dr6(struct kvm_vcpu *vcpu)
743{
744 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
745 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
746}
747
c8639010
JK		 748static void kvm_update_dr7(struct kvm_vcpu *vcpu)
749{
750 unsigned long dr7;
751
752 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
753 dr7 = vcpu->arch.guest_debug_dr7;
754 else
755 dr7 = vcpu->arch.dr7;
756 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 757 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
758 if (dr7 & DR7_BP_EN_MASK)
759 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 760}
761
338dbc97 762static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 763{
764 switch (dr) {
765 case 0 ... 3:
766 vcpu->arch.db[dr] = val;
767 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
768 vcpu->arch.eff_db[dr] = val;
769 break;
770 case 4:
338dbc97
GN		 771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
772 return 1; /* #UD */
020df079
GN		 773 /* fall through */
774 case 6:
338dbc97
GN		 775 if (val & 0xffffffff00000000ULL)
776 return -1; /* #GP */
020df079 777 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 778 kvm_update_dr6(vcpu);
020df079
GN		 779 break;
780 case 5:
338dbc97
GN		 781 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
782 return 1; /* #UD */
020df079
GN		 783 /* fall through */
784 default: /* 7 */
338dbc97
GN		 785 if (val & 0xffffffff00000000ULL)
786 return -1; /* #GP */
020df079 787 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 788 kvm_update_dr7(vcpu);
020df079
GN		 789 break;
790 }
791
792 return 0;
793}
338dbc97
GN		 794
795int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
796{
797 int res;
798
799 res = __kvm_set_dr(vcpu, dr, val);
800 if (res > 0)
801 kvm_queue_exception(vcpu, UD_VECTOR);
802 else if (res < 0)
803 kvm_inject_gp(vcpu, 0);
804
805 return res;
806}
020df079
GN		 807EXPORT_SYMBOL_GPL(kvm_set_dr);
808
338dbc97 809static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 810{
811 switch (dr) {
812 case 0 ... 3:
813 *val = vcpu->arch.db[dr];
814 break;
815 case 4:
338dbc97 816 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 817 return 1;
020df079
GN		 818 /* fall through */
819 case 6:
73aaf249
JK		 820 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
821 *val = vcpu->arch.dr6;
822 else
823 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 824 break;
825 case 5:
338dbc97 826 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 827 return 1;
020df079
GN		 828 /* fall through */
829 default: /* 7 */
830 *val = vcpu->arch.dr7;
831 break;
832 }
833
834 return 0;
835}
338dbc97
GN		 836
837int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
838{
839 if (_kvm_get_dr(vcpu, dr, val)) {
840 kvm_queue_exception(vcpu, UD_VECTOR);
841 return 1;
842 }
843 return 0;
844}
020df079
GN		 845EXPORT_SYMBOL_GPL(kvm_get_dr);
846
022cd0e8
AK		 847bool kvm_rdpmc(struct kvm_vcpu *vcpu)
848{
849 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
850 u64 data;
851 int err;
852
853 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
854 if (err)
855 return err;
856 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
857 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
858 return err;
859}
860EXPORT_SYMBOL_GPL(kvm_rdpmc);
861
043405e1
CO		 862/*
863 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
864 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
865 *
866 * This list is modified at module load time to reflect the
e3267cbb
GC		 867 * capabilities of the host cpu. This capabilities test skips MSRs that are
868 * kvm-specific. Those are put in the beginning of the list.
043405e1 869 */
e3267cbb 870
e984097b 871#define KVM_SAVE_MSRS_BEGIN 12
043405e1 872static u32 msrs_to_save[] = {
e3267cbb 873 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 874 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 875 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 876 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 877 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 878 MSR_KVM_PV_EOI_EN,
043405e1 879 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 880 MSR_STAR,
043405e1
CO		 881#ifdef CONFIG_X86_64
882 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
883#endif
b3897a49 884 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 885 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 886};
887
888static unsigned num_msrs_to_save;
889
f1d24831 890static const u32 emulated_msrs[] = {
ba904635 891 MSR_IA32_TSC_ADJUST,
a3e06bbe 892 MSR_IA32_TSCDEADLINE,
043405e1 893 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 894 MSR_IA32_MCG_STATUS,
895 MSR_IA32_MCG_CTL,
043405e1
CO		 896};
897
384bb783 898bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 899{
b69e8cae 900 if (efer & efer_reserved_bits)
384bb783 901 return false;
15c4a640 902
1b2fd70c
AG		 903 if (efer & EFER_FFXSR) {
904 struct kvm_cpuid_entry2 *feat;
905
906 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 907 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 908 return false;
1b2fd70c
AG		 909 }
910
d8017474
AG		 911 if (efer & EFER_SVME) {
912 struct kvm_cpuid_entry2 *feat;
913
914 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 915 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 916 return false;
d8017474
AG		 917 }
918
384bb783
JK		 919 return true;
920}
921EXPORT_SYMBOL_GPL(kvm_valid_efer);
922
923static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
924{
925 u64 old_efer = vcpu->arch.efer;
926
927 if (!kvm_valid_efer(vcpu, efer))
928 return 1;
929
930 if (is_paging(vcpu)
931 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
932 return 1;
933
15c4a640 934 efer &= ~EFER_LMA;
f6801dff 935 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 936
a3d204e2
SY		 937 kvm_x86_ops->set_efer(vcpu, efer);
938
aad82703
SY		 939 /* Update reserved bits */
940 if ((efer ^ old_efer) & EFER_NX)
941 kvm_mmu_reset_context(vcpu);
942
b69e8cae 943 return 0;
15c4a640
CO		 944}
945
f2b4b7dd
JR		 946void kvm_enable_efer_bits(u64 mask)
947{
948 efer_reserved_bits &= ~mask;
949}
950EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
951
952
15c4a640
CO		 953/*
954 * Writes msr value into into the appropriate "register".
955 * Returns 0 on success, non-0 otherwise.
956 * Assumes vcpu_load() was already called.
957 */
8fe8ab46 958int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 959{
8fe8ab46 960 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 961}
962
313a3dc7
CO		 963/*
964 * Adapt set_msr() to msr_io()'s calling convention
965 */
966static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
967{
8fe8ab46
WA		 968 struct msr_data msr;
969
970 msr.data = *data;
971 msr.index = index;
972 msr.host_initiated = true;
973 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 974}
975
16e8d74d
MT		 976#ifdef CONFIG_X86_64
977struct pvclock_gtod_data {
978 seqcount_t seq;
979
980 struct { /* extract of a clocksource struct */
981 int vclock_mode;
982 cycle_t cycle_last;
983 cycle_t mask;
984 u32 mult;
985 u32 shift;
986 } clock;
987
988 /* open coded 'struct timespec' */
989 u64 monotonic_time_snsec;
990 time_t monotonic_time_sec;
991};
992
993static struct pvclock_gtod_data pvclock_gtod_data;
994
995static void update_pvclock_gtod(struct timekeeper *tk)
996{
997 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
998
999 write_seqcount_begin(&vdata->seq);
1000
1001 /* copy pvclock gtod data */
1002 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1003 vdata->clock.cycle_last = tk->clock->cycle_last;
1004 vdata->clock.mask = tk->clock->mask;
1005 vdata->clock.mult = tk->mult;
1006 vdata->clock.shift = tk->shift;
1007
1008 vdata->monotonic_time_sec = tk->xtime_sec
1009 + tk->wall_to_monotonic.tv_sec;
1010 vdata->monotonic_time_snsec = tk->xtime_nsec
1011 + (tk->wall_to_monotonic.tv_nsec
1012 << tk->shift);
1013 while (vdata->monotonic_time_snsec >=
1014 (((u64)NSEC_PER_SEC) << tk->shift)) {
1015 vdata->monotonic_time_snsec -=
1016 ((u64)NSEC_PER_SEC) << tk->shift;
1017 vdata->monotonic_time_sec++;
1018 }
1019
1020 write_seqcount_end(&vdata->seq);
1021}
1022#endif
1023
1024
18068523
GOC		 1025static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1026{
9ed3c444
AK		 1027 int version;
1028 int r;
50d0a0f9 1029 struct pvclock_wall_clock wc;
923de3cf 1030 struct timespec boot;
18068523
GOC		 1031
1032 if (!wall_clock)
1033 return;
1034
9ed3c444
AK		 1035 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1036 if (r)
1037 return;
1038
1039 if (version & 1)
1040 ++version; /* first time write, random junk */
1041
1042 ++version;
18068523 1043
18068523
GOC		 1044 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1045
50d0a0f9
GH		 1046 /*
1047 * The guest calculates current wall clock time by adding
34c238a1 1048 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1049 * wall clock specified here. guest system time equals host
1050 * system time for us, thus we must fill in host boot time here.
1051 */
923de3cf 1052 getboottime(&boot);
50d0a0f9 1053
4b648665
BR		 1054 if (kvm->arch.kvmclock_offset) {
1055 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1056 boot = timespec_sub(boot, ts);
1057 }
50d0a0f9
GH		 1058 wc.sec = boot.tv_sec;
1059 wc.nsec = boot.tv_nsec;
1060 wc.version = version;
18068523
GOC		 1061
1062 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1063
1064 version++;
1065 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1066}
1067
50d0a0f9
GH		 1068static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1069{
1070 uint32_t quotient, remainder;
1071
1072 /* Don't try to replace with do_div(), this one calculates
1073 * "(dividend << 32) / divisor" */
1074 __asm__ ( "divl %4"
1075 : "=a" (quotient), "=d" (remainder)
1076 : "0" (0), "1" (dividend), "r" (divisor) );
1077 return quotient;
1078}
1079
5f4e3f88
ZA		 1080static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1081 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1082{
5f4e3f88 1083 uint64_t scaled64;
50d0a0f9
GH		 1084 int32_t shift = 0;
1085 uint64_t tps64;
1086 uint32_t tps32;
1087
5f4e3f88
ZA		 1088 tps64 = base_khz * 1000LL;
1089 scaled64 = scaled_khz * 1000LL;
50933623 1090 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1091 tps64 >>= 1;
1092 shift--;
1093 }
1094
1095 tps32 = (uint32_t)tps64;
50933623
JK		 1096 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1097 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1098 scaled64 >>= 1;
1099 else
1100 tps32 <<= 1;
50d0a0f9
GH		 1101 shift++;
1102 }
1103
5f4e3f88
ZA		 1104 *pshift = shift;
1105 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1106
5f4e3f88
ZA		 1107 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1108 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1109}
1110
759379dd
ZA		 1111static inline u64 get_kernel_ns(void)
1112{
1113 struct timespec ts;
1114
759379dd
ZA		 1115 ktime_get_ts(&ts);
1116 monotonic_to_bootbased(&ts);
1117 return timespec_to_ns(&ts);
50d0a0f9
GH		 1118}
1119
d828199e 1120#ifdef CONFIG_X86_64
16e8d74d 1121static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1122#endif
16e8d74d 1123
c8076604 1124static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1125unsigned long max_tsc_khz;
c8076604 1126
cc578287 1127static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1128{
cc578287
ZA		 1129 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1130 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1131}
1132
cc578287 1133static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1134{
cc578287
ZA		 1135 u64 v = (u64)khz * (1000000 + ppm);
1136 do_div(v, 1000000);
1137 return v;
1e993611
JR		 1138}
1139
cc578287 1140static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1141{
cc578287
ZA		 1142 u32 thresh_lo, thresh_hi;
1143 int use_scaling = 0;
217fc9cf 1144
03ba32ca
MT		 1145 /* tsc_khz can be zero if TSC calibration fails */
1146 if (this_tsc_khz == 0)
1147 return;
1148
c285545f
ZA		 1149 /* Compute a scale to convert nanoseconds in TSC cycles */
1150 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1151 &vcpu->arch.virtual_tsc_shift,
1152 &vcpu->arch.virtual_tsc_mult);
1153 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1154
1155 /*
1156 * Compute the variation in TSC rate which is acceptable
1157 * within the range of tolerance and decide if the
1158 * rate being applied is within that bounds of the hardware
1159 * rate. If so, no scaling or compensation need be done.
1160 */
1161 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1162 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1163 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1164 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1165 use_scaling = 1;
1166 }
1167 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1168}
1169
1170static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1171{
e26101b1 1172 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1173 vcpu->arch.virtual_tsc_mult,
1174 vcpu->arch.virtual_tsc_shift);
e26101b1 1175 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1176 return tsc;
1177}
1178
b48aa97e
MT		 1179void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1180{
1181#ifdef CONFIG_X86_64
1182 bool vcpus_matched;
1183 bool do_request = false;
1184 struct kvm_arch *ka = &vcpu->kvm->arch;
1185 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1186
1187 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1188 atomic_read(&vcpu->kvm->online_vcpus));
1189
1190 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1191 if (!ka->use_master_clock)
1192 do_request = 1;
1193
1194 if (!vcpus_matched && ka->use_master_clock)
1195 do_request = 1;
1196
1197 if (do_request)
1198 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1199
1200 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1201 atomic_read(&vcpu->kvm->online_vcpus),
1202 ka->use_master_clock, gtod->clock.vclock_mode);
1203#endif
1204}
1205
ba904635
WA		 1206static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1207{
1208 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1209 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1210}
1211
8fe8ab46 1212void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1213{
1214 struct kvm *kvm = vcpu->kvm;
f38e098f 1215 u64 offset, ns, elapsed;
99e3e30a 1216 unsigned long flags;
02626b6a 1217 s64 usdiff;
b48aa97e 1218 bool matched;
0d3da0d2 1219 bool already_matched;
8fe8ab46 1220 u64 data = msr->data;
99e3e30a 1221
038f8c11 1222 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1223 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1224 ns = get_kernel_ns();
f38e098f 1225 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1226
03ba32ca 1227 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1228 int faulted = 0;
1229
03ba32ca
MT		 1230 /* n.b - signed multiplication and division required */
1231 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1232#ifdef CONFIG_X86_64
03ba32ca 1233 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1234#else
03ba32ca 1235 /* do_div() only does unsigned */
8915aa27
MT		 1236 asm("1: idivl %[divisor]\n"
1237 "2: xor %%edx, %%edx\n"
1238 " movl $0, %[faulted]\n"
1239 "3:\n"
1240 ".section .fixup,\"ax\"\n"
1241 "4: movl $1, %[faulted]\n"
1242 " jmp 3b\n"
1243 ".previous\n"
1244
1245 _ASM_EXTABLE(1b, 4b)
1246
1247 : "=A"(usdiff), [faulted] "=r" (faulted)
1248 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1249
5d3cb0f6 1250#endif
03ba32ca
MT		 1251 do_div(elapsed, 1000);
1252 usdiff -= elapsed;
1253 if (usdiff < 0)
1254 usdiff = -usdiff;
8915aa27
MT		 1255
1256 /* idivl overflow => difference is larger than USEC_PER_SEC */
1257 if (faulted)
1258 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1259 } else
1260 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1261
1262 /*
5d3cb0f6
ZA		 1263 * Special case: TSC write with a small delta (1 second) of virtual
1264 * cycle time against real time is interpreted as an attempt to
1265 * synchronize the CPU.
1266 *
1267 * For a reliable TSC, we can match TSC offsets, and for an unstable
1268 * TSC, we add elapsed time in this computation. We could let the
1269 * compensation code attempt to catch up if we fall behind, but
1270 * it's better to try to match offsets from the beginning.
1271 */
02626b6a 1272 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1273 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1274 if (!check_tsc_unstable()) {
e26101b1 1275 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1276 pr_debug("kvm: matched tsc offset for %llu\n", data);
1277 } else {
857e4099 1278 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1279 data += delta;
1280 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1281 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1282 }
b48aa97e 1283 matched = true;
0d3da0d2 1284 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1285 } else {
1286 /*
1287 * We split periods of matched TSC writes into generations.
1288 * For each generation, we track the original measured
1289 * nanosecond time, offset, and write, so if TSCs are in
1290 * sync, we can match exact offset, and if not, we can match
4a969980 1291 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1292 *
1293 * These values are tracked in kvm->arch.cur_xxx variables.
1294 */
1295 kvm->arch.cur_tsc_generation++;
1296 kvm->arch.cur_tsc_nsec = ns;
1297 kvm->arch.cur_tsc_write = data;
1298 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1299 matched = false;
0d3da0d2 1300 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1301 kvm->arch.cur_tsc_generation, data);
f38e098f 1302 }
e26101b1
ZA		 1303
1304 /*
1305 * We also track th most recent recorded KHZ, write and time to
1306 * allow the matching interval to be extended at each write.
1307 */
f38e098f
ZA		 1308 kvm->arch.last_tsc_nsec = ns;
1309 kvm->arch.last_tsc_write = data;
5d3cb0f6 1310 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1311
b183aa58 1312 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1313
1314 /* Keep track of which generation this VCPU has synchronized to */
1315 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1316 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1317 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1318
ba904635
WA		 1319 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1320 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1321 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1322 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1323
1324 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1325 if (!matched) {
b48aa97e 1326 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1327 } else if (!already_matched) {
1328 kvm->arch.nr_vcpus_matched_tsc++;
1329 }
b48aa97e
MT		 1330
1331 kvm_track_tsc_matching(vcpu);
1332 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1333}
e26101b1 1334
99e3e30a
ZA		 1335EXPORT_SYMBOL_GPL(kvm_write_tsc);
1336
d828199e
MT		 1337#ifdef CONFIG_X86_64
1338
1339static cycle_t read_tsc(void)
1340{
1341 cycle_t ret;
1342 u64 last;
1343
1344 /*
1345 * Empirically, a fence (of type that depends on the CPU)
1346 * before rdtsc is enough to ensure that rdtsc is ordered
1347 * with respect to loads. The various CPU manuals are unclear
1348 * as to whether rdtsc can be reordered with later loads,
1349 * but no one has ever seen it happen.
1350 */
1351 rdtsc_barrier();
1352 ret = (cycle_t)vget_cycles();
1353
1354 last = pvclock_gtod_data.clock.cycle_last;
1355
1356 if (likely(ret >= last))
1357 return ret;
1358
1359 /*
1360 * GCC likes to generate cmov here, but this branch is extremely
1361 * predictable (it's just a funciton of time and the likely is
1362 * very likely) and there's a data dependence, so force GCC
1363 * to generate a branch instead. I don't barrier() because
1364 * we don't actually need a barrier, and if this function
1365 * ever gets inlined it will generate worse code.
1366 */
1367 asm volatile ("");
1368 return last;
1369}
1370
1371static inline u64 vgettsc(cycle_t *cycle_now)
1372{
1373 long v;
1374 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1375
1376 *cycle_now = read_tsc();
1377
1378 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1379 return v * gtod->clock.mult;
1380}
1381
1382static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1383{
1384 unsigned long seq;
1385 u64 ns;
1386 int mode;
1387 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1388
1389 ts->tv_nsec = 0;
1390 do {
1391 seq = read_seqcount_begin(&gtod->seq);
1392 mode = gtod->clock.vclock_mode;
1393 ts->tv_sec = gtod->monotonic_time_sec;
1394 ns = gtod->monotonic_time_snsec;
1395 ns += vgettsc(cycle_now);
1396 ns >>= gtod->clock.shift;
1397 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1398 timespec_add_ns(ts, ns);
1399
1400 return mode;
1401}
1402
1403/* returns true if host is using tsc clocksource */
1404static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1405{
1406 struct timespec ts;
1407
1408 /* checked again under seqlock below */
1409 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1410 return false;
1411
1412 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1413 return false;
1414
1415 monotonic_to_bootbased(&ts);
1416 *kernel_ns = timespec_to_ns(&ts);
1417
1418 return true;
1419}
1420#endif
1421
1422/*
1423 *
b48aa97e
MT		 1424 * Assuming a stable TSC across physical CPUS, and a stable TSC
1425 * across virtual CPUs, the following condition is possible.
1426 * Each numbered line represents an event visible to both
d828199e
MT		 1427 * CPUs at the next numbered event.
1428 *
1429 * "timespecX" represents host monotonic time. "tscX" represents
1430 * RDTSC value.
1431 *
1432 * VCPU0 on CPU0 | VCPU1 on CPU1
1433 *
1434 * 1. read timespec0,tsc0
1435 * 2. | timespec1 = timespec0 + N
1436 * | tsc1 = tsc0 + M
1437 * 3. transition to guest | transition to guest
1438 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1439 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1440 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1441 *
1442 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1443 *
1444 * - ret0 < ret1
1445 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1446 * ...
1447 * - 0 < N - M => M < N
1448 *
1449 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1450 * always the case (the difference between two distinct xtime instances
1451 * might be smaller then the difference between corresponding TSC reads,
1452 * when updating guest vcpus pvclock areas).
1453 *
1454 * To avoid that problem, do not allow visibility of distinct
1455 * system_timestamp/tsc_timestamp values simultaneously: use a master
1456 * copy of host monotonic time values. Update that master copy
1457 * in lockstep.
1458 *
b48aa97e 1459 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1460 *
1461 */
1462
1463static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1464{
1465#ifdef CONFIG_X86_64
1466 struct kvm_arch *ka = &kvm->arch;
1467 int vclock_mode;
b48aa97e
MT		 1468 bool host_tsc_clocksource, vcpus_matched;
1469
1470 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1471 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1472
1473 /*
1474 * If the host uses TSC clock, then passthrough TSC as stable
1475 * to the guest.
1476 */
b48aa97e 1477 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1478 &ka->master_kernel_ns,
1479 &ka->master_cycle_now);
1480
16a96021
MT		 1481 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1482 && !backwards_tsc_observed;
b48aa97e 1483
d828199e
MT		 1484 if (ka->use_master_clock)
1485 atomic_set(&kvm_guest_has_master_clock, 1);
1486
1487 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1488 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1489 vcpus_matched);
d828199e
MT		 1490#endif
1491}
1492
2e762ff7
MT		 1493static void kvm_gen_update_masterclock(struct kvm *kvm)
1494{
1495#ifdef CONFIG_X86_64
1496 int i;
1497 struct kvm_vcpu *vcpu;
1498 struct kvm_arch *ka = &kvm->arch;
1499
1500 spin_lock(&ka->pvclock_gtod_sync_lock);
1501 kvm_make_mclock_inprogress_request(kvm);
1502 /* no guest entries from this point */
1503 pvclock_update_vm_gtod_copy(kvm);
1504
1505 kvm_for_each_vcpu(i, vcpu, kvm)
1506 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1507
1508 /* guest entries allowed */
1509 kvm_for_each_vcpu(i, vcpu, kvm)
1510 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1511
1512 spin_unlock(&ka->pvclock_gtod_sync_lock);
1513#endif
1514}
1515
34c238a1 1516static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1517{
d828199e 1518 unsigned long flags, this_tsc_khz;
18068523 1519 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1520 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1521 s64 kernel_ns;
d828199e 1522 u64 tsc_timestamp, host_tsc;
0b79459b 1523 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1524 u8 pvclock_flags;
d828199e
MT		 1525 bool use_master_clock;
1526
1527 kernel_ns = 0;
1528 host_tsc = 0;
18068523 1529
d828199e
MT		 1530 /*
1531 * If the host uses TSC clock, then passthrough TSC as stable
1532 * to the guest.
1533 */
1534 spin_lock(&ka->pvclock_gtod_sync_lock);
1535 use_master_clock = ka->use_master_clock;
1536 if (use_master_clock) {
1537 host_tsc = ka->master_cycle_now;
1538 kernel_ns = ka->master_kernel_ns;
1539 }
1540 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1541
1542 /* Keep irq disabled to prevent changes to the clock */
1543 local_irq_save(flags);
1544 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1545 if (unlikely(this_tsc_khz == 0)) {
1546 local_irq_restore(flags);
1547 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1548 return 1;
1549 }
d828199e
MT		 1550 if (!use_master_clock) {
1551 host_tsc = native_read_tsc();
1552 kernel_ns = get_kernel_ns();
1553 }
1554
1555 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1556
c285545f
ZA		 1557 /*
1558 * We may have to catch up the TSC to match elapsed wall clock
1559 * time for two reasons, even if kvmclock is used.
1560 * 1) CPU could have been running below the maximum TSC rate
1561 * 2) Broken TSC compensation resets the base at each VCPU
1562 * entry to avoid unknown leaps of TSC even when running
1563 * again on the same CPU. This may cause apparent elapsed
1564 * time to disappear, and the guest to stand still or run
1565 * very slowly.
1566 */
1567 if (vcpu->tsc_catchup) {
1568 u64 tsc = compute_guest_tsc(v, kernel_ns);
1569 if (tsc > tsc_timestamp) {
f1e2b260 1570 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1571 tsc_timestamp = tsc;
1572 }
50d0a0f9
GH		 1573 }
1574
18068523
GOC		 1575 local_irq_restore(flags);
1576
0b79459b 1577 if (!vcpu->pv_time_enabled)
c285545f 1578 return 0;
18068523 1579
e48672fa 1580 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1581 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1582 &vcpu->hv_clock.tsc_shift,
1583 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1584 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1585 }
1586
1587 /* With all the info we got, fill in the values */
1d5f066e 1588 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1589 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1590 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1591
18068523
GOC		 1592 /*
1593 * The interface expects us to write an even number signaling that the
1594 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1595 * state, we just increase by 2 at the end.
18068523 1596 */
50d0a0f9 1597 vcpu->hv_clock.version += 2;
18068523 1598
0b79459b
AH		 1599 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1600 &guest_hv_clock, sizeof(guest_hv_clock))))
1601 return 0;
78c0337a
MT		 1602
1603 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1604 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1605
1606 if (vcpu->pvclock_set_guest_stopped_request) {
1607 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1608 vcpu->pvclock_set_guest_stopped_request = false;
1609 }
1610
d828199e
MT		 1611 /* If the host uses TSC clocksource, then it is stable */
1612 if (use_master_clock)
1613 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1614
78c0337a
MT		 1615 vcpu->hv_clock.flags = pvclock_flags;
1616
0b79459b
AH		 1617 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1618 &vcpu->hv_clock,
1619 sizeof(vcpu->hv_clock));
8cfdc000 1620 return 0;
c8076604
GH		 1621}
1622
0061d53d
MT		 1623/*
1624 * kvmclock updates which are isolated to a given vcpu, such as
1625 * vcpu->cpu migration, should not allow system_timestamp from
1626 * the rest of the vcpus to remain static. Otherwise ntp frequency
1627 * correction applies to one vcpu's system_timestamp but not
1628 * the others.
1629 *
1630 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1631 * We need to rate-limit these requests though, as they can
1632 * considerably slow guests that have a large number of vcpus.
1633 * The time for a remote vcpu to update its kvmclock is bound
1634 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1635 */
1636
7e44e449
AJ		 1637#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1638
1639static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1640{
1641 int i;
7e44e449
AJ		 1642 struct delayed_work *dwork = to_delayed_work(work);
1643 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1644 kvmclock_update_work);
1645 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1646 struct kvm_vcpu *vcpu;
1647
1648 kvm_for_each_vcpu(i, vcpu, kvm) {
1649 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1650 kvm_vcpu_kick(vcpu);
1651 }
1652}
1653
7e44e449
AJ		 1654static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1655{
1656 struct kvm *kvm = v->kvm;
1657
1658 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1659 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1660 KVMCLOCK_UPDATE_DELAY);
1661}
1662
332967a3
AJ		 1663#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1664
1665static void kvmclock_sync_fn(struct work_struct *work)
1666{
1667 struct delayed_work *dwork = to_delayed_work(work);
1668 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1669 kvmclock_sync_work);
1670 struct kvm *kvm = container_of(ka, struct kvm, arch);
1671
1672 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1673 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1674 KVMCLOCK_SYNC_PERIOD);
1675}
1676
9ba075a6
AK		 1677static bool msr_mtrr_valid(unsigned msr)
1678{
1679 switch (msr) {
1680 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1681 case MSR_MTRRfix64K_00000:
1682 case MSR_MTRRfix16K_80000:
1683 case MSR_MTRRfix16K_A0000:
1684 case MSR_MTRRfix4K_C0000:
1685 case MSR_MTRRfix4K_C8000:
1686 case MSR_MTRRfix4K_D0000:
1687 case MSR_MTRRfix4K_D8000:
1688 case MSR_MTRRfix4K_E0000:
1689 case MSR_MTRRfix4K_E8000:
1690 case MSR_MTRRfix4K_F0000:
1691 case MSR_MTRRfix4K_F8000:
1692 case MSR_MTRRdefType:
1693 case MSR_IA32_CR_PAT:
1694 return true;
1695 case 0x2f8:
1696 return true;
1697 }
1698 return false;
1699}
1700
d6289b93
MT		 1701static bool valid_pat_type(unsigned t)
1702{
1703 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1704}
1705
1706static bool valid_mtrr_type(unsigned t)
1707{
1708 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1709}
1710
1711static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1712{
1713 int i;
1714
1715 if (!msr_mtrr_valid(msr))
1716 return false;
1717
1718 if (msr == MSR_IA32_CR_PAT) {
1719 for (i = 0; i < 8; i++)
1720 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1721 return false;
1722 return true;
1723 } else if (msr == MSR_MTRRdefType) {
1724 if (data & ~0xcff)
1725 return false;
1726 return valid_mtrr_type(data & 0xff);
1727 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1728 for (i = 0; i < 8 ; i++)
1729 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1730 return false;
1731 return true;
1732 }
1733
1734 /* variable MTRRs */
1735 return valid_mtrr_type(data & 0xff);
1736}
1737
9ba075a6
AK		 1738static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1739{
0bed3b56
SY		 1740 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1741
d6289b93 1742 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1743 return 1;
1744
0bed3b56
SY		 1745 if (msr == MSR_MTRRdefType) {
1746 vcpu->arch.mtrr_state.def_type = data;
1747 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1748 } else if (msr == MSR_MTRRfix64K_00000)
1749 p[0] = data;
1750 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1751 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1752 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1753 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1754 else if (msr == MSR_IA32_CR_PAT)
1755 vcpu->arch.pat = data;
1756 else { /* Variable MTRRs */
1757 int idx, is_mtrr_mask;
1758 u64 *pt;
1759
1760 idx = (msr - 0x200) / 2;
1761 is_mtrr_mask = msr - 0x200 - 2 * idx;
1762 if (!is_mtrr_mask)
1763 pt =
1764 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1765 else
1766 pt =
1767 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1768 *pt = data;
1769 }
1770
1771 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1772 return 0;
1773}
15c4a640 1774
890ca9ae 1775static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1776{
890ca9ae
HY		 1777 u64 mcg_cap = vcpu->arch.mcg_cap;
1778 unsigned bank_num = mcg_cap & 0xff;
1779
15c4a640 1780 switch (msr) {
15c4a640 1781 case MSR_IA32_MCG_STATUS:
890ca9ae 1782 vcpu->arch.mcg_status = data;
15c4a640 1783 break;
c7ac679c 1784 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1785 if (!(mcg_cap & MCG_CTL_P))
1786 return 1;
1787 if (data != 0 && data != ~(u64)0)
1788 return -1;
1789 vcpu->arch.mcg_ctl = data;
1790 break;
1791 default:
1792 if (msr >= MSR_IA32_MC0_CTL &&
1793 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1794 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1795 /* only 0 or all 1s can be written to IA32_MCi_CTL
1796 * some Linux kernels though clear bit 10 in bank 4 to
1797 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1798 * this to avoid an uncatched #GP in the guest
1799 */
890ca9ae 1800 if ((offset & 0x3) == 0 &&
114be429 1801 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1802 return -1;
1803 vcpu->arch.mce_banks[offset] = data;
1804 break;
1805 }
1806 return 1;
1807 }
1808 return 0;
1809}
1810
ffde22ac
ES		 1811static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1812{
1813 struct kvm *kvm = vcpu->kvm;
1814 int lm = is_long_mode(vcpu);
1815 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1816 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1817 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1818 : kvm->arch.xen_hvm_config.blob_size_32;
1819 u32 page_num = data & ~PAGE_MASK;
1820 u64 page_addr = data & PAGE_MASK;
1821 u8 *page;
1822 int r;
1823
1824 r = -E2BIG;
1825 if (page_num >= blob_size)
1826 goto out;
1827 r = -ENOMEM;
ff5c2c03
SL		 1828 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1829 if (IS_ERR(page)) {
1830 r = PTR_ERR(page);
ffde22ac 1831 goto out;
ff5c2c03 1832 }
ffde22ac
ES		 1833 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1834 goto out_free;
1835 r = 0;
1836out_free:
1837 kfree(page);
1838out:
1839 return r;
1840}
1841
55cd8e5a
GN		 1842static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1843{
1844 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1845}
1846
1847static bool kvm_hv_msr_partition_wide(u32 msr)
1848{
1849 bool r = false;
1850 switch (msr) {
1851 case HV_X64_MSR_GUEST_OS_ID:
1852 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1853 case HV_X64_MSR_REFERENCE_TSC:
1854 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1855 r = true;
1856 break;
1857 }
1858
1859 return r;
1860}
1861
1862static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1863{
1864 struct kvm *kvm = vcpu->kvm;
1865
1866 switch (msr) {
1867 case HV_X64_MSR_GUEST_OS_ID:
1868 kvm->arch.hv_guest_os_id = data;
1869 /* setting guest os id to zero disables hypercall page */
1870 if (!kvm->arch.hv_guest_os_id)
1871 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1872 break;
1873 case HV_X64_MSR_HYPERCALL: {
1874 u64 gfn;
1875 unsigned long addr;
1876 u8 instructions[4];
1877
1878 /* if guest os id is not set hypercall should remain disabled */
1879 if (!kvm->arch.hv_guest_os_id)
1880 break;
1881 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1882 kvm->arch.hv_hypercall = data;
1883 break;
1884 }
1885 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1886 addr = gfn_to_hva(kvm, gfn);
1887 if (kvm_is_error_hva(addr))
1888 return 1;
1889 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1890 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1891 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1892 return 1;
1893 kvm->arch.hv_hypercall = data;
b94b64c9 1894 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1895 break;
1896 }
e984097b
VR		 1897 case HV_X64_MSR_REFERENCE_TSC: {
1898 u64 gfn;
1899 HV_REFERENCE_TSC_PAGE tsc_ref;
1900 memset(&tsc_ref, 0, sizeof(tsc_ref));
1901 kvm->arch.hv_tsc_page = data;
1902 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1903 break;
1904 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1905 if (kvm_write_guest(kvm, data,
1906 &tsc_ref, sizeof(tsc_ref)))
1907 return 1;
1908 mark_page_dirty(kvm, gfn);
1909 break;
1910 }
55cd8e5a 1911 default:
a737f256
CD		 1912 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1913 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1914 return 1;
1915 }
1916 return 0;
1917}
1918
1919static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1920{
10388a07
GN		 1921 switch (msr) {
1922 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1923 u64 gfn;
10388a07 1924 unsigned long addr;
55cd8e5a 1925
10388a07
GN		 1926 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1927 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1928 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1929 return 1;
10388a07
GN		 1930 break;
1931 }
b3af1e88
VR		 1932 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1933 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1934 if (kvm_is_error_hva(addr))
1935 return 1;
8b0cedff 1936 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1937 return 1;
1938 vcpu->arch.hv_vapic = data;
b3af1e88 1939 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1940 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1941 return 1;
10388a07
GN		 1942 break;
1943 }
1944 case HV_X64_MSR_EOI:
1945 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1946 case HV_X64_MSR_ICR:
1947 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1948 case HV_X64_MSR_TPR:
1949 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1950 default:
a737f256
CD		 1951 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1952 "data 0x%llx\n", msr, data);
10388a07
GN		 1953 return 1;
1954 }
1955
1956 return 0;
55cd8e5a
GN		 1957}
1958
344d9588
GN		 1959static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1960{
1961 gpa_t gpa = data & ~0x3f;
1962
4a969980 1963 /* Bits 2:5 are reserved, Should be zero */
6adba527 1964 if (data & 0x3c)
344d9588
GN		 1965 return 1;
1966
1967 vcpu->arch.apf.msr_val = data;
1968
1969 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1970 kvm_clear_async_pf_completion_queue(vcpu);
1971 kvm_async_pf_hash_reset(vcpu);
1972 return 0;
1973 }
1974
8f964525
AH		 1975 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1976 sizeof(u32)))
344d9588
GN		 1977 return 1;
1978
6adba527 1979 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1980 kvm_async_pf_wakeup_all(vcpu);
1981 return 0;
1982}
1983
12f9a48f
GC		 1984static void kvmclock_reset(struct kvm_vcpu *vcpu)
1985{
0b79459b 1986 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1987}
1988
c9aaa895
GC		 1989static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1990{
1991 u64 delta;
1992
1993 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1994 return;
1995
1996 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1997 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1998 vcpu->arch.st.accum_steal = delta;
1999}
2000
2001static void record_steal_time(struct kvm_vcpu *vcpu)
2002{
2003 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2004 return;
2005
2006 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2007 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2008 return;
2009
2010 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2011 vcpu->arch.st.steal.version += 2;
2012 vcpu->arch.st.accum_steal = 0;
2013
2014 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2015 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2016}
2017
8fe8ab46 2018int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2019{
5753785f 2020 bool pr = false;
8fe8ab46
WA		 2021 u32 msr = msr_info->index;
2022 u64 data = msr_info->data;
5753785f 2023
15c4a640 2024 switch (msr) {
2e32b719
BP		 2025 case MSR_AMD64_NB_CFG:
2026 case MSR_IA32_UCODE_REV:
2027 case MSR_IA32_UCODE_WRITE:
2028 case MSR_VM_HSAVE_PA:
2029 case MSR_AMD64_PATCH_LOADER:
2030 case MSR_AMD64_BU_CFG2:
2031 break;
2032
15c4a640 2033 case MSR_EFER:
b69e8cae 2034 return set_efer(vcpu, data);
8f1589d9
AP		 2035 case MSR_K7_HWCR:
2036 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2037 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2038 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2039 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2040 if (data != 0) {
a737f256
CD		 2041 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2042 data);
8f1589d9
AP		 2043 return 1;
2044 }
15c4a640 2045 break;
f7c6d140
AP		 2046 case MSR_FAM10H_MMIO_CONF_BASE:
2047 if (data != 0) {
a737f256
CD		 2048 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2049 "0x%llx\n", data);
f7c6d140
AP		 2050 return 1;
2051 }
15c4a640 2052 break;
b5e2fec0
AG		 2053 case MSR_IA32_DEBUGCTLMSR:
2054 if (!data) {
2055 /* We support the non-activated case already */
2056 break;
2057 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2058 /* Values other than LBR and BTF are vendor-specific,
2059 thus reserved and should throw a #GP */
2060 return 1;
2061 }
a737f256
CD		 2062 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2063 __func__, data);
b5e2fec0 2064 break;
9ba075a6
AK		 2065 case 0x200 ... 0x2ff:
2066 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2067 case MSR_IA32_APICBASE:
58cb628d 2068 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2069 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2070 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2071 case MSR_IA32_TSCDEADLINE:
2072 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2073 break;
ba904635
WA		 2074 case MSR_IA32_TSC_ADJUST:
2075 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2076 if (!msr_info->host_initiated) {
2077 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2078 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2079 }
2080 vcpu->arch.ia32_tsc_adjust_msr = data;
2081 }
2082 break;
15c4a640 2083 case MSR_IA32_MISC_ENABLE:
ad312c7c 2084 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2085 break;
11c6bffa 2086 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2087 case MSR_KVM_WALL_CLOCK:
2088 vcpu->kvm->arch.wall_clock = data;
2089 kvm_write_wall_clock(vcpu->kvm, data);
2090 break;
11c6bffa 2091 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2092 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2093 u64 gpa_offset;
12f9a48f 2094 kvmclock_reset(vcpu);
18068523
GOC		 2095
2096 vcpu->arch.time = data;
0061d53d 2097 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2098
2099 /* we verify if the enable bit is set... */
2100 if (!(data & 1))
2101 break;
2102
0b79459b 2103 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2104
0b79459b 2105 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2106 &vcpu->arch.pv_time, data & ~1ULL,
2107 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2108 vcpu->arch.pv_time_enabled = false;
2109 else
2110 vcpu->arch.pv_time_enabled = true;
32cad84f 2111
18068523
GOC		 2112 break;
2113 }
344d9588
GN		 2114 case MSR_KVM_ASYNC_PF_EN:
2115 if (kvm_pv_enable_async_pf(vcpu, data))
2116 return 1;
2117 break;
c9aaa895
GC		 2118 case MSR_KVM_STEAL_TIME:
2119
2120 if (unlikely(!sched_info_on()))
2121 return 1;
2122
2123 if (data & KVM_STEAL_RESERVED_MASK)
2124 return 1;
2125
2126 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2127 data & KVM_STEAL_VALID_BITS,
2128 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2129 return 1;
2130
2131 vcpu->arch.st.msr_val = data;
2132
2133 if (!(data & KVM_MSR_ENABLED))
2134 break;
2135
2136 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2137
2138 preempt_disable();
2139 accumulate_steal_time(vcpu);
2140 preempt_enable();
2141
2142 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2143
2144 break;
ae7a2a3f
MT		 2145 case MSR_KVM_PV_EOI_EN:
2146 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2147 return 1;
2148 break;
c9aaa895 2149
890ca9ae
HY		 2150 case MSR_IA32_MCG_CTL:
2151 case MSR_IA32_MCG_STATUS:
2152 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2153 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2154
2155 /* Performance counters are not protected by a CPUID bit,
2156 * so we should check all of them in the generic path for the sake of
2157 * cross vendor migration.
2158 * Writing a zero into the event select MSRs disables them,
2159 * which we perfectly emulate ;-). Any other value should be at least
2160 * reported, some guests depend on them.
2161 */
71db6023
AP		 2162 case MSR_K7_EVNTSEL0:
2163 case MSR_K7_EVNTSEL1:
2164 case MSR_K7_EVNTSEL2:
2165 case MSR_K7_EVNTSEL3:
2166 if (data != 0)
a737f256
CD		 2167 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2168 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2169 break;
2170 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2171 * so we ignore writes to make it happy.
2172 */
71db6023
AP		 2173 case MSR_K7_PERFCTR0:
2174 case MSR_K7_PERFCTR1:
2175 case MSR_K7_PERFCTR2:
2176 case MSR_K7_PERFCTR3:
a737f256
CD		 2177 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2178 "0x%x data 0x%llx\n", msr, data);
71db6023 2179 break;
5753785f
GN		 2180 case MSR_P6_PERFCTR0:
2181 case MSR_P6_PERFCTR1:
2182 pr = true;
2183 case MSR_P6_EVNTSEL0:
2184 case MSR_P6_EVNTSEL1:
2185 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2186 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2187
2188 if (pr || data != 0)
a737f256
CD		 2189 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2190 "0x%x data 0x%llx\n", msr, data);
5753785f 2191 break;
84e0cefa
JS		 2192 case MSR_K7_CLK_CTL:
2193 /*
2194 * Ignore all writes to this no longer documented MSR.
2195 * Writes are only relevant for old K7 processors,
2196 * all pre-dating SVM, but a recommended workaround from
4a969980 2197 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2198 * affected processor models on the command line, hence
2199 * the need to ignore the workaround.
2200 */
2201 break;
55cd8e5a
GN		 2202 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2203 if (kvm_hv_msr_partition_wide(msr)) {
2204 int r;
2205 mutex_lock(&vcpu->kvm->lock);
2206 r = set_msr_hyperv_pw(vcpu, msr, data);
2207 mutex_unlock(&vcpu->kvm->lock);
2208 return r;
2209 } else
2210 return set_msr_hyperv(vcpu, msr, data);
2211 break;
91c9c3ed 2212 case MSR_IA32_BBL_CR_CTL3:
2213 /* Drop writes to this legacy MSR -- see rdmsr
2214 * counterpart for further detail.
2215 */
a737f256 2216 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2217 break;
2b036c6b
BO		 2218 case MSR_AMD64_OSVW_ID_LENGTH:
2219 if (!guest_cpuid_has_osvw(vcpu))
2220 return 1;
2221 vcpu->arch.osvw.length = data;
2222 break;
2223 case MSR_AMD64_OSVW_STATUS:
2224 if (!guest_cpuid_has_osvw(vcpu))
2225 return 1;
2226 vcpu->arch.osvw.status = data;
2227 break;
15c4a640 2228 default:
ffde22ac
ES		 2229 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2230 return xen_hvm_config(vcpu, data);
f5132b01 2231 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2232 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2233 if (!ignore_msrs) {
a737f256
CD		 2234 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2235 msr, data);
ed85c068
AP		 2236 return 1;
2237 } else {
a737f256
CD		 2238 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2239 msr, data);
ed85c068
AP		 2240 break;
2241 }
15c4a640
CO		 2242 }
2243 return 0;
2244}
2245EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2246
2247
2248/*
2249 * Reads an msr value (of 'msr_index') into 'pdata'.
2250 * Returns 0 on success, non-0 otherwise.
2251 * Assumes vcpu_load() was already called.
2252 */
2253int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2254{
2255 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2256}
2257
9ba075a6
AK		 2258static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2259{
0bed3b56
SY		 2260 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2261
9ba075a6
AK		 2262 if (!msr_mtrr_valid(msr))
2263 return 1;
2264
0bed3b56
SY		 2265 if (msr == MSR_MTRRdefType)
2266 *pdata = vcpu->arch.mtrr_state.def_type +
2267 (vcpu->arch.mtrr_state.enabled << 10);
2268 else if (msr == MSR_MTRRfix64K_00000)
2269 *pdata = p[0];
2270 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2271 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2272 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2273 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2274 else if (msr == MSR_IA32_CR_PAT)
2275 *pdata = vcpu->arch.pat;
2276 else { /* Variable MTRRs */
2277 int idx, is_mtrr_mask;
2278 u64 *pt;
2279
2280 idx = (msr - 0x200) / 2;
2281 is_mtrr_mask = msr - 0x200 - 2 * idx;
2282 if (!is_mtrr_mask)
2283 pt =
2284 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2285 else
2286 pt =
2287 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2288 *pdata = *pt;
2289 }
2290
9ba075a6
AK		 2291 return 0;
2292}
2293
890ca9ae 2294static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2295{
2296 u64 data;
890ca9ae
HY		 2297 u64 mcg_cap = vcpu->arch.mcg_cap;
2298 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2299
2300 switch (msr) {
15c4a640
CO		 2301 case MSR_IA32_P5_MC_ADDR:
2302 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2303 data = 0;
2304 break;
15c4a640 2305 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2306 data = vcpu->arch.mcg_cap;
2307 break;
c7ac679c 2308 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2309 if (!(mcg_cap & MCG_CTL_P))
2310 return 1;
2311 data = vcpu->arch.mcg_ctl;
2312 break;
2313 case MSR_IA32_MCG_STATUS:
2314 data = vcpu->arch.mcg_status;
2315 break;
2316 default:
2317 if (msr >= MSR_IA32_MC0_CTL &&
2318 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2319 u32 offset = msr - MSR_IA32_MC0_CTL;
2320 data = vcpu->arch.mce_banks[offset];
2321 break;
2322 }
2323 return 1;
2324 }
2325 *pdata = data;
2326 return 0;
2327}
2328
55cd8e5a
GN		 2329static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2330{
2331 u64 data = 0;
2332 struct kvm *kvm = vcpu->kvm;
2333
2334 switch (msr) {
2335 case HV_X64_MSR_GUEST_OS_ID:
2336 data = kvm->arch.hv_guest_os_id;
2337 break;
2338 case HV_X64_MSR_HYPERCALL:
2339 data = kvm->arch.hv_hypercall;
2340 break;
e984097b
VR		 2341 case HV_X64_MSR_TIME_REF_COUNT: {
2342 data =
2343 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2344 break;
2345 }
2346 case HV_X64_MSR_REFERENCE_TSC:
2347 data = kvm->arch.hv_tsc_page;
2348 break;
55cd8e5a 2349 default:
a737f256 2350 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2351 return 1;
2352 }
2353
2354 *pdata = data;
2355 return 0;
2356}
2357
2358static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2359{
2360 u64 data = 0;
2361
2362 switch (msr) {
2363 case HV_X64_MSR_VP_INDEX: {
2364 int r;
2365 struct kvm_vcpu *v;
684851a1
TY		 2366 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2367 if (v == vcpu) {
55cd8e5a 2368 data = r;
684851a1
TY		 2369 break;
2370 }
2371 }
55cd8e5a
GN		 2372 break;
2373 }
10388a07
GN		 2374 case HV_X64_MSR_EOI:
2375 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2376 case HV_X64_MSR_ICR:
2377 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2378 case HV_X64_MSR_TPR:
2379 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2380 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2381 data = vcpu->arch.hv_vapic;
2382 break;
55cd8e5a 2383 default:
a737f256 2384 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2385 return 1;
2386 }
2387 *pdata = data;
2388 return 0;
2389}
2390
890ca9ae
HY		 2391int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2392{
2393 u64 data;
2394
2395 switch (msr) {
890ca9ae 2396 case MSR_IA32_PLATFORM_ID:
15c4a640 2397 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2398 case MSR_IA32_DEBUGCTLMSR:
2399 case MSR_IA32_LASTBRANCHFROMIP:
2400 case MSR_IA32_LASTBRANCHTOIP:
2401 case MSR_IA32_LASTINTFROMIP:
2402 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2403 case MSR_K8_SYSCFG:
2404 case MSR_K7_HWCR:
61a6bd67 2405 case MSR_VM_HSAVE_PA:
9e699624 2406 case MSR_K7_EVNTSEL0:
1f3ee616 2407 case MSR_K7_PERFCTR0:
1fdbd48c 2408 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2409 case MSR_AMD64_NB_CFG:
f7c6d140 2410 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2411 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2412 data = 0;
2413 break;
5753785f
GN		 2414 case MSR_P6_PERFCTR0:
2415 case MSR_P6_PERFCTR1:
2416 case MSR_P6_EVNTSEL0:
2417 case MSR_P6_EVNTSEL1:
2418 if (kvm_pmu_msr(vcpu, msr))
2419 return kvm_pmu_get_msr(vcpu, msr, pdata);
2420 data = 0;
2421 break;
742bc670
MT		 2422 case MSR_IA32_UCODE_REV:
2423 data = 0x100000000ULL;
2424 break;
9ba075a6
AK		 2425 case MSR_MTRRcap:
2426 data = 0x500 | KVM_NR_VAR_MTRR;
2427 break;
2428 case 0x200 ... 0x2ff:
2429 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2430 case 0xcd: /* fsb frequency */
2431 data = 3;
2432 break;
7b914098
JS		 2433 /*
2434 * MSR_EBC_FREQUENCY_ID
2435 * Conservative value valid for even the basic CPU models.
2436 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2437 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2438 * and 266MHz for model 3, or 4. Set Core Clock
2439 * Frequency to System Bus Frequency Ratio to 1 (bits
2440 * 31:24) even though these are only valid for CPU
2441 * models > 2, however guests may end up dividing or
2442 * multiplying by zero otherwise.
2443 */
2444 case MSR_EBC_FREQUENCY_ID:
2445 data = 1 << 24;
2446 break;
15c4a640
CO		 2447 case MSR_IA32_APICBASE:
2448 data = kvm_get_apic_base(vcpu);
2449 break;
0105d1a5
GN		 2450 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2451 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2452 break;
a3e06bbe
LJ		 2453 case MSR_IA32_TSCDEADLINE:
2454 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2455 break;
ba904635
WA		 2456 case MSR_IA32_TSC_ADJUST:
2457 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2458 break;
15c4a640 2459 case MSR_IA32_MISC_ENABLE:
ad312c7c 2460 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2461 break;
847f0ad8
AG		 2462 case MSR_IA32_PERF_STATUS:
2463 /* TSC increment by tick */
2464 data = 1000ULL;
2465 /* CPU multiplier */
2466 data |= (((uint64_t)4ULL) << 40);
2467 break;
15c4a640 2468 case MSR_EFER:
f6801dff 2469 data = vcpu->arch.efer;
15c4a640 2470 break;
18068523 2471 case MSR_KVM_WALL_CLOCK:
11c6bffa 2472 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2473 data = vcpu->kvm->arch.wall_clock;
2474 break;
2475 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2476 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2477 data = vcpu->arch.time;
2478 break;
344d9588
GN		 2479 case MSR_KVM_ASYNC_PF_EN:
2480 data = vcpu->arch.apf.msr_val;
2481 break;
c9aaa895
GC		 2482 case MSR_KVM_STEAL_TIME:
2483 data = vcpu->arch.st.msr_val;
2484 break;
1d92128f
MT		 2485 case MSR_KVM_PV_EOI_EN:
2486 data = vcpu->arch.pv_eoi.msr_val;
2487 break;
890ca9ae
HY		 2488 case MSR_IA32_P5_MC_ADDR:
2489 case MSR_IA32_P5_MC_TYPE:
2490 case MSR_IA32_MCG_CAP:
2491 case MSR_IA32_MCG_CTL:
2492 case MSR_IA32_MCG_STATUS:
2493 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2494 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2495 case MSR_K7_CLK_CTL:
2496 /*
2497 * Provide expected ramp-up count for K7. All other
2498 * are set to zero, indicating minimum divisors for
2499 * every field.
2500 *
2501 * This prevents guest kernels on AMD host with CPU
2502 * type 6, model 8 and higher from exploding due to
2503 * the rdmsr failing.
2504 */
2505 data = 0x20000000;
2506 break;
55cd8e5a
GN		 2507 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2508 if (kvm_hv_msr_partition_wide(msr)) {
2509 int r;
2510 mutex_lock(&vcpu->kvm->lock);
2511 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2512 mutex_unlock(&vcpu->kvm->lock);
2513 return r;
2514 } else
2515 return get_msr_hyperv(vcpu, msr, pdata);
2516 break;
91c9c3ed 2517 case MSR_IA32_BBL_CR_CTL3:
2518 /* This legacy MSR exists but isn't fully documented in current
2519 * silicon. It is however accessed by winxp in very narrow
2520 * scenarios where it sets bit #19, itself documented as
2521 * a "reserved" bit. Best effort attempt to source coherent
2522 * read data here should the balance of the register be
2523 * interpreted by the guest:
2524 *
2525 * L2 cache control register 3: 64GB range, 256KB size,
2526 * enabled, latency 0x1, configured
2527 */
2528 data = 0xbe702111;
2529 break;
2b036c6b
BO		 2530 case MSR_AMD64_OSVW_ID_LENGTH:
2531 if (!guest_cpuid_has_osvw(vcpu))
2532 return 1;
2533 data = vcpu->arch.osvw.length;
2534 break;
2535 case MSR_AMD64_OSVW_STATUS:
2536 if (!guest_cpuid_has_osvw(vcpu))
2537 return 1;
2538 data = vcpu->arch.osvw.status;
2539 break;
15c4a640 2540 default:
f5132b01
GN		 2541 if (kvm_pmu_msr(vcpu, msr))
2542 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2543 if (!ignore_msrs) {
a737f256 2544 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2545 return 1;
2546 } else {
a737f256 2547 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2548 data = 0;
2549 }
2550 break;
15c4a640
CO		 2551 }
2552 *pdata = data;
2553 return 0;
2554}
2555EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2556
313a3dc7
CO		 2557/*
2558 * Read or write a bunch of msrs. All parameters are kernel addresses.
2559 *
2560 * @return number of msrs set successfully.
2561 */
2562static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2563 struct kvm_msr_entry *entries,
2564 int (*do_msr)(struct kvm_vcpu *vcpu,
2565 unsigned index, u64 *data))
2566{
f656ce01 2567 int i, idx;
313a3dc7 2568
f656ce01 2569 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2570 for (i = 0; i < msrs->nmsrs; ++i)
2571 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2572 break;
f656ce01 2573 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2574
313a3dc7
CO		 2575 return i;
2576}
2577
2578/*
2579 * Read or write a bunch of msrs. Parameters are user addresses.
2580 *
2581 * @return number of msrs set successfully.
2582 */
2583static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2584 int (*do_msr)(struct kvm_vcpu *vcpu,
2585 unsigned index, u64 *data),
2586 int writeback)
2587{
2588 struct kvm_msrs msrs;
2589 struct kvm_msr_entry *entries;
2590 int r, n;
2591 unsigned size;
2592
2593 r = -EFAULT;
2594 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2595 goto out;
2596
2597 r = -E2BIG;
2598 if (msrs.nmsrs >= MAX_IO_MSRS)
2599 goto out;
2600
313a3dc7 2601 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2602 entries = memdup_user(user_msrs->entries, size);
2603 if (IS_ERR(entries)) {
2604 r = PTR_ERR(entries);
313a3dc7 2605 goto out;
ff5c2c03 2606 }
313a3dc7
CO		 2607
2608 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2609 if (r < 0)
2610 goto out_free;
2611
2612 r = -EFAULT;
2613 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2614 goto out_free;
2615
2616 r = n;
2617
2618out_free:
7a73c028 2619 kfree(entries);
313a3dc7
CO		 2620out:
2621 return r;
2622}
2623
018d00d2
ZX		 2624int kvm_dev_ioctl_check_extension(long ext)
2625{
2626 int r;
2627
2628 switch (ext) {
2629 case KVM_CAP_IRQCHIP:
2630 case KVM_CAP_HLT:
2631 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2632 case KVM_CAP_SET_TSS_ADDR:
07716717 2633 case KVM_CAP_EXT_CPUID:
9c15bb1d 2634 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2635 case KVM_CAP_CLOCKSOURCE:
7837699f 2636 case KVM_CAP_PIT:
a28e4f5a 2637 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2638 case KVM_CAP_MP_STATE:
ed848624 2639 case KVM_CAP_SYNC_MMU:
a355c85c 2640 case KVM_CAP_USER_NMI:
52d939a0 2641 case KVM_CAP_REINJECT_CONTROL:
4925663a 2642 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2643 case KVM_CAP_IRQFD:
d34e6b17 2644 case KVM_CAP_IOEVENTFD:
f848a5a8 2645 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2646 case KVM_CAP_PIT2:
e9f42757 2647 case KVM_CAP_PIT_STATE2:
b927a3ce 2648 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2649 case KVM_CAP_XEN_HVM:
afbcf7ab 2650 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2651 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2652 case KVM_CAP_HYPERV:
10388a07 2653 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2654 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2655 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2656 case KVM_CAP_DEBUGREGS:
d2be1651 2657 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2658 case KVM_CAP_XSAVE:
344d9588 2659 case KVM_CAP_ASYNC_PF:
92a1f12d 2660 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2661 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2662 case KVM_CAP_READONLY_MEM:
5f66b620 2663 case KVM_CAP_HYPERV_TIME:
100943c5 2664 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2665#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2666 case KVM_CAP_ASSIGN_DEV_IRQ:
2667 case KVM_CAP_PCI_2_3:
2668#endif
018d00d2
ZX		 2669 r = 1;
2670 break;
542472b5
LV		 2671 case KVM_CAP_COALESCED_MMIO:
2672 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2673 break;
774ead3a
AK		 2674 case KVM_CAP_VAPIC:
2675 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2676 break;
f725230a 2677 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2678 r = KVM_SOFT_MAX_VCPUS;
2679 break;
2680 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2681 r = KVM_MAX_VCPUS;
2682 break;
a988b910 2683 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2684 r = KVM_USER_MEM_SLOTS;
a988b910 2685 break;
a68a6a72
MT		 2686 case KVM_CAP_PV_MMU: /* obsolete */
2687 r = 0;
2f333bcb 2688 break;
4cee4b72 2689#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2690 case KVM_CAP_IOMMU:
a1b60c1c 2691 r = iommu_present(&pci_bus_type);
62c476c7 2692 break;
4cee4b72 2693#endif
890ca9ae
HY		 2694 case KVM_CAP_MCE:
2695 r = KVM_MAX_MCE_BANKS;
2696 break;
2d5b5a66
SY		 2697 case KVM_CAP_XCRS:
2698 r = cpu_has_xsave;
2699 break;
92a1f12d
JR		 2700 case KVM_CAP_TSC_CONTROL:
2701 r = kvm_has_tsc_control;
2702 break;
4d25a066
JK		 2703 case KVM_CAP_TSC_DEADLINE_TIMER:
2704 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2705 break;
018d00d2
ZX		 2706 default:
2707 r = 0;
2708 break;
2709 }
2710 return r;
2711
2712}
2713
043405e1
CO		 2714long kvm_arch_dev_ioctl(struct file *filp,
2715 unsigned int ioctl, unsigned long arg)
2716{
2717 void __user *argp = (void __user *)arg;
2718 long r;
2719
2720 switch (ioctl) {
2721 case KVM_GET_MSR_INDEX_LIST: {
2722 struct kvm_msr_list __user *user_msr_list = argp;
2723 struct kvm_msr_list msr_list;
2724 unsigned n;
2725
2726 r = -EFAULT;
2727 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2728 goto out;
2729 n = msr_list.nmsrs;
2730 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2731 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2732 goto out;
2733 r = -E2BIG;
e125e7b6 2734 if (n < msr_list.nmsrs)
043405e1
CO		 2735 goto out;
2736 r = -EFAULT;
2737 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2738 num_msrs_to_save * sizeof(u32)))
2739 goto out;
e125e7b6 2740 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2741 &emulated_msrs,
2742 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2743 goto out;
2744 r = 0;
2745 break;
2746 }
9c15bb1d
BP		 2747 case KVM_GET_SUPPORTED_CPUID:
2748 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2749 struct kvm_cpuid2 __user *cpuid_arg = argp;
2750 struct kvm_cpuid2 cpuid;
2751
2752 r = -EFAULT;
2753 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2754 goto out;
9c15bb1d
BP		 2755
2756 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2757 ioctl);
674eea0f
AK		 2758 if (r)
2759 goto out;
2760
2761 r = -EFAULT;
2762 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2763 goto out;
2764 r = 0;
2765 break;
2766 }
890ca9ae
HY		 2767 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2768 u64 mce_cap;
2769
2770 mce_cap = KVM_MCE_CAP_SUPPORTED;
2771 r = -EFAULT;
2772 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2773 goto out;
2774 r = 0;
2775 break;
2776 }
043405e1
CO		 2777 default:
2778 r = -EINVAL;
2779 }
2780out:
2781 return r;
2782}
2783
f5f48ee1
SY		 2784static void wbinvd_ipi(void *garbage)
2785{
2786 wbinvd();
2787}
2788
2789static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2790{
e0f0bbc5 2791 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2792}
2793
313a3dc7
CO		 2794void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2795{
f5f48ee1
SY		 2796 /* Address WBINVD may be executed by guest */
2797 if (need_emulate_wbinvd(vcpu)) {
2798 if (kvm_x86_ops->has_wbinvd_exit())
2799 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2800 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2801 smp_call_function_single(vcpu->cpu,
2802 wbinvd_ipi, NULL, 1);
2803 }
2804
313a3dc7 2805 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2806
0dd6a6ed
ZA		 2807 /* Apply any externally detected TSC adjustments (due to suspend) */
2808 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2809 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2810 vcpu->arch.tsc_offset_adjustment = 0;
2811 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2812 }
8f6055cb 2813
48434c20 2814 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2815 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2816 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2817 if (tsc_delta < 0)
2818 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2819 if (check_tsc_unstable()) {
b183aa58
ZA		 2820 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2821 vcpu->arch.last_guest_tsc);
2822 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2823 vcpu->arch.tsc_catchup = 1;
c285545f 2824 }
d98d07ca
MT		 2825 /*
2826 * On a host with synchronized TSC, there is no need to update
2827 * kvmclock on vcpu->cpu migration
2828 */
2829 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2830 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2831 if (vcpu->cpu != cpu)
2832 kvm_migrate_timers(vcpu);
e48672fa 2833 vcpu->cpu = cpu;
6b7d7e76 2834 }
c9aaa895
GC		 2835
2836 accumulate_steal_time(vcpu);
2837 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2838}
2839
2840void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2841{
02daab21 2842 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2843 kvm_put_guest_fpu(vcpu);
6f526ec5 2844 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2845}
2846
313a3dc7
CO		 2847static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2848 struct kvm_lapic_state *s)
2849{
5a71785d 2850 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2851 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2852
2853 return 0;
2854}
2855
2856static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2857 struct kvm_lapic_state *s)
2858{
64eb0620 2859 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2860 update_cr8_intercept(vcpu);
313a3dc7
CO		 2861
2862 return 0;
2863}
2864
f77bc6a4
ZX		 2865static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2866 struct kvm_interrupt *irq)
2867{
02cdb50f 2868 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2869 return -EINVAL;
2870 if (irqchip_in_kernel(vcpu->kvm))
2871 return -ENXIO;
f77bc6a4 2872
66fd3f7f 2873 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2874 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2875
f77bc6a4
ZX		 2876 return 0;
2877}
2878
c4abb7c9
JK		 2879static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2880{
c4abb7c9 2881 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2882
2883 return 0;
2884}
2885
b209749f
AK		 2886static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2887 struct kvm_tpr_access_ctl *tac)
2888{
2889 if (tac->flags)
2890 return -EINVAL;
2891 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2892 return 0;
2893}
2894
890ca9ae
HY		 2895static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2896 u64 mcg_cap)
2897{
2898 int r;
2899 unsigned bank_num = mcg_cap & 0xff, bank;
2900
2901 r = -EINVAL;
a9e38c3e 2902 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2903 goto out;
2904 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2905 goto out;
2906 r = 0;
2907 vcpu->arch.mcg_cap = mcg_cap;
2908 /* Init IA32_MCG_CTL to all 1s */
2909 if (mcg_cap & MCG_CTL_P)
2910 vcpu->arch.mcg_ctl = ~(u64)0;
2911 /* Init IA32_MCi_CTL to all 1s */
2912 for (bank = 0; bank < bank_num; bank++)
2913 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2914out:
2915 return r;
2916}
2917
2918static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2919 struct kvm_x86_mce *mce)
2920{
2921 u64 mcg_cap = vcpu->arch.mcg_cap;
2922 unsigned bank_num = mcg_cap & 0xff;
2923 u64 *banks = vcpu->arch.mce_banks;
2924
2925 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2926 return -EINVAL;
2927 /*
2928 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2929 * reporting is disabled
2930 */
2931 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2932 vcpu->arch.mcg_ctl != ~(u64)0)
2933 return 0;
2934 banks += 4 * mce->bank;
2935 /*
2936 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2937 * reporting is disabled for the bank
2938 */
2939 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2940 return 0;
2941 if (mce->status & MCI_STATUS_UC) {
2942 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2943 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2944 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2945 return 0;
2946 }
2947 if (banks[1] & MCI_STATUS_VAL)
2948 mce->status |= MCI_STATUS_OVER;
2949 banks[2] = mce->addr;
2950 banks[3] = mce->misc;
2951 vcpu->arch.mcg_status = mce->mcg_status;
2952 banks[1] = mce->status;
2953 kvm_queue_exception(vcpu, MC_VECTOR);
2954 } else if (!(banks[1] & MCI_STATUS_VAL)
2955 || !(banks[1] & MCI_STATUS_UC)) {
2956 if (banks[1] & MCI_STATUS_VAL)
2957 mce->status |= MCI_STATUS_OVER;
2958 banks[2] = mce->addr;
2959 banks[3] = mce->misc;
2960 banks[1] = mce->status;
2961 } else
2962 banks[1] |= MCI_STATUS_OVER;
2963 return 0;
2964}
2965
3cfc3092
JK		 2966static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2967 struct kvm_vcpu_events *events)
2968{
7460fb4a 2969 process_nmi(vcpu);
03b82a30
JK		 2970 events->exception.injected =
2971 vcpu->arch.exception.pending &&
2972 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2973 events->exception.nr = vcpu->arch.exception.nr;
2974 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2975 events->exception.pad = 0;
3cfc3092
JK		 2976 events->exception.error_code = vcpu->arch.exception.error_code;
2977
03b82a30
JK		 2978 events->interrupt.injected =
2979 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2980 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2981 events->interrupt.soft = 0;
37ccdcbe 2982 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2983
2984 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2985 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2986 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2987 events->nmi.pad = 0;
3cfc3092 2988
66450a21 2989 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2990
dab4b911 2991 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2992 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2993 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2994}
2995
2996static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2997 struct kvm_vcpu_events *events)
2998{
dab4b911 2999 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3000 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3001 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3002 return -EINVAL;
3003
7460fb4a 3004 process_nmi(vcpu);
3cfc3092
JK		 3005 vcpu->arch.exception.pending = events->exception.injected;
3006 vcpu->arch.exception.nr = events->exception.nr;
3007 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3008 vcpu->arch.exception.error_code = events->exception.error_code;
3009
3010 vcpu->arch.interrupt.pending = events->interrupt.injected;
3011 vcpu->arch.interrupt.nr = events->interrupt.nr;
3012 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3013 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3014 kvm_x86_ops->set_interrupt_shadow(vcpu,
3015 events->interrupt.shadow);
3cfc3092
JK		 3016
3017 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3018 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3019 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3020 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3021
66450a21
JK		 3022 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3023 kvm_vcpu_has_lapic(vcpu))
3024 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3025
3842d135
AK		 3026 kvm_make_request(KVM_REQ_EVENT, vcpu);
3027
3cfc3092
JK		 3028 return 0;
3029}
3030
a1efbe77
JK		 3031static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3032 struct kvm_debugregs *dbgregs)
3033{
73aaf249
JK		 3034 unsigned long val;
3035
a1efbe77 3036 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3037 _kvm_get_dr(vcpu, 6, &val);
3038 dbgregs->dr6 = val;
a1efbe77
JK		 3039 dbgregs->dr7 = vcpu->arch.dr7;
3040 dbgregs->flags = 0;
97e69aa6 3041 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3042}
3043
3044static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3045 struct kvm_debugregs *dbgregs)
3046{
3047 if (dbgregs->flags)
3048 return -EINVAL;
3049
a1efbe77
JK		 3050 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3051 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3052 kvm_update_dr6(vcpu);
a1efbe77 3053 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3054 kvm_update_dr7(vcpu);
a1efbe77 3055
a1efbe77
JK		 3056 return 0;
3057}
3058
2d5b5a66
SY		 3059static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3060 struct kvm_xsave *guest_xsave)
3061{
4344ee98 3062 if (cpu_has_xsave) {
2d5b5a66
SY		 3063 memcpy(guest_xsave->region,
3064 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3065 vcpu->arch.guest_xstate_size);
3066 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3067 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3068 } else {
2d5b5a66
SY		 3069 memcpy(guest_xsave->region,
3070 &vcpu->arch.guest_fpu.state->fxsave,
3071 sizeof(struct i387_fxsave_struct));
3072 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3073 XSTATE_FPSSE;
3074 }
3075}
3076
3077static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3078 struct kvm_xsave *guest_xsave)
3079{
3080 u64 xstate_bv =
3081 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3082
d7876f1b
PB		 3083 if (cpu_has_xsave) {
3084 /*
3085 * Here we allow setting states that are not present in
3086 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3087 * with old userspace.
3088 */
4ff41732 3089 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3090 return -EINVAL;
2d5b5a66 3091 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3092 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3093 } else {
2d5b5a66
SY		 3094 if (xstate_bv & ~XSTATE_FPSSE)
3095 return -EINVAL;
3096 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3097 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3098 }
3099 return 0;
3100}
3101
3102static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3103 struct kvm_xcrs *guest_xcrs)
3104{
3105 if (!cpu_has_xsave) {
3106 guest_xcrs->nr_xcrs = 0;
3107 return;
3108 }
3109
3110 guest_xcrs->nr_xcrs = 1;
3111 guest_xcrs->flags = 0;
3112 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3113 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3114}
3115
3116static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3117 struct kvm_xcrs *guest_xcrs)
3118{
3119 int i, r = 0;
3120
3121 if (!cpu_has_xsave)
3122 return -EINVAL;
3123
3124 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3125 return -EINVAL;
3126
3127 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3128 /* Only support XCR0 currently */
c67a04cb 3129 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3130 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3131 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3132 break;
3133 }
3134 if (r)
3135 r = -EINVAL;
3136 return r;
3137}
3138
1c0b28c2
EM		 3139/*
3140 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3141 * stopped by the hypervisor. This function will be called from the host only.
3142 * EINVAL is returned when the host attempts to set the flag for a guest that
3143 * does not support pv clocks.
3144 */
3145static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3146{
0b79459b 3147 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3148 return -EINVAL;
51d59c6b 3149 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3150 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3151 return 0;
3152}
3153
313a3dc7
CO		 3154long kvm_arch_vcpu_ioctl(struct file *filp,
3155 unsigned int ioctl, unsigned long arg)
3156{
3157 struct kvm_vcpu *vcpu = filp->private_data;
3158 void __user *argp = (void __user *)arg;
3159 int r;
d1ac91d8
AK		 3160 union {
3161 struct kvm_lapic_state *lapic;
3162 struct kvm_xsave *xsave;
3163 struct kvm_xcrs *xcrs;
3164 void *buffer;
3165 } u;
3166
3167 u.buffer = NULL;
313a3dc7
CO		 3168 switch (ioctl) {
3169 case KVM_GET_LAPIC: {
2204ae3c
MT		 3170 r = -EINVAL;
3171 if (!vcpu->arch.apic)
3172 goto out;
d1ac91d8 3173 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3174
b772ff36 3175 r = -ENOMEM;
d1ac91d8 3176 if (!u.lapic)
b772ff36 3177 goto out;
d1ac91d8 3178 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3179 if (r)
3180 goto out;
3181 r = -EFAULT;
d1ac91d8 3182 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3183 goto out;
3184 r = 0;
3185 break;
3186 }
3187 case KVM_SET_LAPIC: {
2204ae3c
MT		 3188 r = -EINVAL;
3189 if (!vcpu->arch.apic)
3190 goto out;
ff5c2c03 3191 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3192 if (IS_ERR(u.lapic))
3193 return PTR_ERR(u.lapic);
ff5c2c03 3194
d1ac91d8 3195 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3196 break;
3197 }
f77bc6a4
ZX		 3198 case KVM_INTERRUPT: {
3199 struct kvm_interrupt irq;
3200
3201 r = -EFAULT;
3202 if (copy_from_user(&irq, argp, sizeof irq))
3203 goto out;
3204 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3205 break;
3206 }
c4abb7c9
JK		 3207 case KVM_NMI: {
3208 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3209 break;
3210 }
313a3dc7
CO		 3211 case KVM_SET_CPUID: {
3212 struct kvm_cpuid __user *cpuid_arg = argp;
3213 struct kvm_cpuid cpuid;
3214
3215 r = -EFAULT;
3216 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3217 goto out;
3218 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3219 break;
3220 }
07716717
DK		 3221 case KVM_SET_CPUID2: {
3222 struct kvm_cpuid2 __user *cpuid_arg = argp;
3223 struct kvm_cpuid2 cpuid;
3224
3225 r = -EFAULT;
3226 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3227 goto out;
3228 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3229 cpuid_arg->entries);
07716717
DK		 3230 break;
3231 }
3232 case KVM_GET_CPUID2: {
3233 struct kvm_cpuid2 __user *cpuid_arg = argp;
3234 struct kvm_cpuid2 cpuid;
3235
3236 r = -EFAULT;
3237 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3238 goto out;
3239 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3240 cpuid_arg->entries);
07716717
DK		 3241 if (r)
3242 goto out;
3243 r = -EFAULT;
3244 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3245 goto out;
3246 r = 0;
3247 break;
3248 }
313a3dc7
CO		 3249 case KVM_GET_MSRS:
3250 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3251 break;
3252 case KVM_SET_MSRS:
3253 r = msr_io(vcpu, argp, do_set_msr, 0);
3254 break;
b209749f
AK		 3255 case KVM_TPR_ACCESS_REPORTING: {
3256 struct kvm_tpr_access_ctl tac;
3257
3258 r = -EFAULT;
3259 if (copy_from_user(&tac, argp, sizeof tac))
3260 goto out;
3261 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3262 if (r)
3263 goto out;
3264 r = -EFAULT;
3265 if (copy_to_user(argp, &tac, sizeof tac))
3266 goto out;
3267 r = 0;
3268 break;
3269 };
b93463aa
AK		 3270 case KVM_SET_VAPIC_ADDR: {
3271 struct kvm_vapic_addr va;
3272
3273 r = -EINVAL;
3274 if (!irqchip_in_kernel(vcpu->kvm))
3275 goto out;
3276 r = -EFAULT;
3277 if (copy_from_user(&va, argp, sizeof va))
3278 goto out;
fda4e2e8 3279 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3280 break;
3281 }
890ca9ae
HY		 3282 case KVM_X86_SETUP_MCE: {
3283 u64 mcg_cap;
3284
3285 r = -EFAULT;
3286 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3287 goto out;
3288 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3289 break;
3290 }
3291 case KVM_X86_SET_MCE: {
3292 struct kvm_x86_mce mce;
3293
3294 r = -EFAULT;
3295 if (copy_from_user(&mce, argp, sizeof mce))
3296 goto out;
3297 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3298 break;
3299 }
3cfc3092
JK		 3300 case KVM_GET_VCPU_EVENTS: {
3301 struct kvm_vcpu_events events;
3302
3303 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3304
3305 r = -EFAULT;
3306 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3307 break;
3308 r = 0;
3309 break;
3310 }
3311 case KVM_SET_VCPU_EVENTS: {
3312 struct kvm_vcpu_events events;
3313
3314 r = -EFAULT;
3315 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3316 break;
3317
3318 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3319 break;
3320 }
a1efbe77
JK		 3321 case KVM_GET_DEBUGREGS: {
3322 struct kvm_debugregs dbgregs;
3323
3324 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3325
3326 r = -EFAULT;
3327 if (copy_to_user(argp, &dbgregs,
3328 sizeof(struct kvm_debugregs)))
3329 break;
3330 r = 0;
3331 break;
3332 }
3333 case KVM_SET_DEBUGREGS: {
3334 struct kvm_debugregs dbgregs;
3335
3336 r = -EFAULT;
3337 if (copy_from_user(&dbgregs, argp,
3338 sizeof(struct kvm_debugregs)))
3339 break;
3340
3341 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3342 break;
3343 }
2d5b5a66 3344 case KVM_GET_XSAVE: {
d1ac91d8 3345 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3346 r = -ENOMEM;
d1ac91d8 3347 if (!u.xsave)
2d5b5a66
SY		 3348 break;
3349
d1ac91d8 3350 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3351
3352 r = -EFAULT;
d1ac91d8 3353 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3354 break;
3355 r = 0;
3356 break;
3357 }
3358 case KVM_SET_XSAVE: {
ff5c2c03 3359 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3360 if (IS_ERR(u.xsave))
3361 return PTR_ERR(u.xsave);
2d5b5a66 3362
d1ac91d8 3363 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3364 break;
3365 }
3366 case KVM_GET_XCRS: {
d1ac91d8 3367 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3368 r = -ENOMEM;
d1ac91d8 3369 if (!u.xcrs)
2d5b5a66
SY		 3370 break;
3371
d1ac91d8 3372 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3373
3374 r = -EFAULT;
d1ac91d8 3375 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3376 sizeof(struct kvm_xcrs)))
3377 break;
3378 r = 0;
3379 break;
3380 }
3381 case KVM_SET_XCRS: {
ff5c2c03 3382 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3383 if (IS_ERR(u.xcrs))
3384 return PTR_ERR(u.xcrs);
2d5b5a66 3385
d1ac91d8 3386 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3387 break;
3388 }
92a1f12d
JR		 3389 case KVM_SET_TSC_KHZ: {
3390 u32 user_tsc_khz;
3391
3392 r = -EINVAL;
92a1f12d
JR		 3393 user_tsc_khz = (u32)arg;
3394
3395 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3396 goto out;
3397
cc578287
ZA		 3398 if (user_tsc_khz == 0)
3399 user_tsc_khz = tsc_khz;
3400
3401 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3402
3403 r = 0;
3404 goto out;
3405 }
3406 case KVM_GET_TSC_KHZ: {
cc578287 3407 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3408 goto out;
3409 }
1c0b28c2
EM		 3410 case KVM_KVMCLOCK_CTRL: {
3411 r = kvm_set_guest_paused(vcpu);
3412 goto out;
3413 }
313a3dc7
CO		 3414 default:
3415 r = -EINVAL;
3416 }
3417out:
d1ac91d8 3418 kfree(u.buffer);
313a3dc7
CO		 3419 return r;
3420}
3421
5b1c1493
CO		 3422int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3423{
3424 return VM_FAULT_SIGBUS;
3425}
3426
1fe779f8
CO		 3427static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3428{
3429 int ret;
3430
3431 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3432 return -EINVAL;
1fe779f8
CO		 3433 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3434 return ret;
3435}
3436
b927a3ce
SY		 3437static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3438 u64 ident_addr)
3439{
3440 kvm->arch.ept_identity_map_addr = ident_addr;
3441 return 0;
3442}
3443
1fe779f8
CO		 3444static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3445 u32 kvm_nr_mmu_pages)
3446{
3447 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3448 return -EINVAL;
3449
79fac95e 3450 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3451
3452 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3453 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3454
79fac95e 3455 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3456 return 0;
3457}
3458
3459static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3460{
39de71ec 3461 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3462}
3463
1fe779f8
CO		 3464static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3465{
3466 int r;
3467
3468 r = 0;
3469 switch (chip->chip_id) {
3470 case KVM_IRQCHIP_PIC_MASTER:
3471 memcpy(&chip->chip.pic,
3472 &pic_irqchip(kvm)->pics[0],
3473 sizeof(struct kvm_pic_state));
3474 break;
3475 case KVM_IRQCHIP_PIC_SLAVE:
3476 memcpy(&chip->chip.pic,
3477 &pic_irqchip(kvm)->pics[1],
3478 sizeof(struct kvm_pic_state));
3479 break;
3480 case KVM_IRQCHIP_IOAPIC:
eba0226b 3481 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3482 break;
3483 default:
3484 r = -EINVAL;
3485 break;
3486 }
3487 return r;
3488}
3489
3490static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3491{
3492 int r;
3493
3494 r = 0;
3495 switch (chip->chip_id) {
3496 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3497 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3498 memcpy(&pic_irqchip(kvm)->pics[0],
3499 &chip->chip.pic,
3500 sizeof(struct kvm_pic_state));
f4f51050 3501 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3502 break;
3503 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3504 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3505 memcpy(&pic_irqchip(kvm)->pics[1],
3506 &chip->chip.pic,
3507 sizeof(struct kvm_pic_state));
f4f51050 3508 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3509 break;
3510 case KVM_IRQCHIP_IOAPIC:
eba0226b 3511 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3512 break;
3513 default:
3514 r = -EINVAL;
3515 break;
3516 }
3517 kvm_pic_update_irq(pic_irqchip(kvm));
3518 return r;
3519}
3520
e0f63cb9
SY		 3521static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3522{
3523 int r = 0;
3524
894a9c55 3525 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3526 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3527 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3528 return r;
3529}
3530
3531static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3532{
3533 int r = 0;
3534
894a9c55 3535 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3536 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3537 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3538 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3539 return r;
3540}
3541
3542static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3543{
3544 int r = 0;
3545
3546 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3547 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3548 sizeof(ps->channels));
3549 ps->flags = kvm->arch.vpit->pit_state.flags;
3550 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3551 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3552 return r;
3553}
3554
3555static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3556{
3557 int r = 0, start = 0;
3558 u32 prev_legacy, cur_legacy;
3559 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3560 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3561 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3562 if (!prev_legacy && cur_legacy)
3563 start = 1;
3564 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3565 sizeof(kvm->arch.vpit->pit_state.channels));
3566 kvm->arch.vpit->pit_state.flags = ps->flags;
3567 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3568 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3569 return r;
3570}
3571
52d939a0
MT		 3572static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3573 struct kvm_reinject_control *control)
3574{
3575 if (!kvm->arch.vpit)
3576 return -ENXIO;
894a9c55 3577 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3578 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3579 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3580 return 0;
3581}
3582
95d4c16c 3583/**
60c34612
TY		 3584 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3585 * @kvm: kvm instance
3586 * @log: slot id and address to which we copy the log
95d4c16c 3587 *
60c34612
TY		 3588 * We need to keep it in mind that VCPU threads can write to the bitmap
3589 * concurrently. So, to avoid losing data, we keep the following order for
3590 * each bit:
95d4c16c 3591 *
60c34612
TY		 3592 * 1. Take a snapshot of the bit and clear it if needed.
3593 * 2. Write protect the corresponding page.
3594 * 3. Flush TLB's if needed.
3595 * 4. Copy the snapshot to the userspace.
95d4c16c 3596 *
60c34612
TY		 3597 * Between 2 and 3, the guest may write to the page using the remaining TLB
3598 * entry. This is not a problem because the page will be reported dirty at
3599 * step 4 using the snapshot taken before and step 3 ensures that successive
3600 * writes will be logged for the next call.
5bb064dc 3601 */
60c34612 3602int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3603{
7850ac54 3604 int r;
5bb064dc 3605 struct kvm_memory_slot *memslot;
60c34612
TY		 3606 unsigned long n, i;
3607 unsigned long *dirty_bitmap;
3608 unsigned long *dirty_bitmap_buffer;
3609 bool is_dirty = false;
5bb064dc 3610
79fac95e 3611 mutex_lock(&kvm->slots_lock);
5bb064dc 3612
b050b015 3613 r = -EINVAL;
bbacc0c1 3614 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3615 goto out;
3616
28a37544 3617 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3618
3619 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3620 r = -ENOENT;
60c34612 3621 if (!dirty_bitmap)
b050b015
MT		 3622 goto out;
3623
87bf6e7d 3624 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3625
60c34612
TY		 3626 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3627 memset(dirty_bitmap_buffer, 0, n);
b050b015 3628
60c34612 3629 spin_lock(&kvm->mmu_lock);
b050b015 3630
60c34612
TY		 3631 for (i = 0; i < n / sizeof(long); i++) {
3632 unsigned long mask;
3633 gfn_t offset;
cdfca7b3 3634
60c34612
TY		 3635 if (!dirty_bitmap[i])
3636 continue;
b050b015 3637
60c34612 3638 is_dirty = true;
914ebccd 3639
60c34612
TY		 3640 mask = xchg(&dirty_bitmap[i], 0);
3641 dirty_bitmap_buffer[i] = mask;
edde99ce 3642
60c34612
TY		 3643 offset = i * BITS_PER_LONG;
3644 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3645 }
60c34612
TY		 3646
3647 spin_unlock(&kvm->mmu_lock);
3648
198c74f4
XG		 3649 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3650 lockdep_assert_held(&kvm->slots_lock);
3651
3652 /*
3653 * All the TLBs can be flushed out of mmu lock, see the comments in
3654 * kvm_mmu_slot_remove_write_access().
3655 */
3656 if (is_dirty)
3657 kvm_flush_remote_tlbs(kvm);
3658
60c34612
TY		 3659 r = -EFAULT;
3660 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3661 goto out;
b050b015 3662
5bb064dc
ZX		 3663 r = 0;
3664out:
79fac95e 3665 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3666 return r;
3667}
3668
aa2fbe6d
YZ		 3669int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3670 bool line_status)
23d43cf9
CD		 3671{
3672 if (!irqchip_in_kernel(kvm))
3673 return -ENXIO;
3674
3675 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3676 irq_event->irq, irq_event->level,
3677 line_status);
23d43cf9
CD		 3678 return 0;
3679}
3680
1fe779f8
CO		 3681long kvm_arch_vm_ioctl(struct file *filp,
3682 unsigned int ioctl, unsigned long arg)
3683{
3684 struct kvm *kvm = filp->private_data;
3685 void __user *argp = (void __user *)arg;
367e1319 3686 int r = -ENOTTY;
f0d66275
DH		 3687 /*
3688 * This union makes it completely explicit to gcc-3.x
3689 * that these two variables' stack usage should be
3690 * combined, not added together.
3691 */
3692 union {
3693 struct kvm_pit_state ps;
e9f42757 3694 struct kvm_pit_state2 ps2;
c5ff41ce 3695 struct kvm_pit_config pit_config;
f0d66275 3696 } u;
1fe779f8
CO		 3697
3698 switch (ioctl) {
3699 case KVM_SET_TSS_ADDR:
3700 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3701 break;
b927a3ce
SY		 3702 case KVM_SET_IDENTITY_MAP_ADDR: {
3703 u64 ident_addr;
3704
3705 r = -EFAULT;
3706 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3707 goto out;
3708 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3709 break;
3710 }
1fe779f8
CO		 3711 case KVM_SET_NR_MMU_PAGES:
3712 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3713 break;
3714 case KVM_GET_NR_MMU_PAGES:
3715 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3716 break;
3ddea128
MT		 3717 case KVM_CREATE_IRQCHIP: {
3718 struct kvm_pic *vpic;
3719
3720 mutex_lock(&kvm->lock);
3721 r = -EEXIST;
3722 if (kvm->arch.vpic)
3723 goto create_irqchip_unlock;
3e515705
AK		 3724 r = -EINVAL;
3725 if (atomic_read(&kvm->online_vcpus))
3726 goto create_irqchip_unlock;
1fe779f8 3727 r = -ENOMEM;
3ddea128
MT		 3728 vpic = kvm_create_pic(kvm);
3729 if (vpic) {
1fe779f8
CO		 3730 r = kvm_ioapic_init(kvm);
3731 if (r) {
175504cd 3732 mutex_lock(&kvm->slots_lock);
72bb2fcd 3733 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3734 &vpic->dev_master);
3735 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3736 &vpic->dev_slave);
3737 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3738 &vpic->dev_eclr);
175504cd 3739 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3740 kfree(vpic);
3741 goto create_irqchip_unlock;
1fe779f8
CO		 3742 }
3743 } else
3ddea128
MT		 3744 goto create_irqchip_unlock;
3745 smp_wmb();
3746 kvm->arch.vpic = vpic;
3747 smp_wmb();
399ec807
AK		 3748 r = kvm_setup_default_irq_routing(kvm);
3749 if (r) {
175504cd 3750 mutex_lock(&kvm->slots_lock);
3ddea128 3751 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3752 kvm_ioapic_destroy(kvm);
3753 kvm_destroy_pic(kvm);
3ddea128 3754 mutex_unlock(&kvm->irq_lock);
175504cd 3755 mutex_unlock(&kvm->slots_lock);
399ec807 3756 }
3ddea128
MT		 3757 create_irqchip_unlock:
3758 mutex_unlock(&kvm->lock);
1fe779f8 3759 break;
3ddea128 3760 }
7837699f 3761 case KVM_CREATE_PIT:
c5ff41ce
JK		 3762 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3763 goto create_pit;
3764 case KVM_CREATE_PIT2:
3765 r = -EFAULT;
3766 if (copy_from_user(&u.pit_config, argp,
3767 sizeof(struct kvm_pit_config)))
3768 goto out;
3769 create_pit:
79fac95e 3770 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3771 r = -EEXIST;
3772 if (kvm->arch.vpit)
3773 goto create_pit_unlock;
7837699f 3774 r = -ENOMEM;
c5ff41ce 3775 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3776 if (kvm->arch.vpit)
3777 r = 0;
269e05e4 3778 create_pit_unlock:
79fac95e 3779 mutex_unlock(&kvm->slots_lock);
7837699f 3780 break;
1fe779f8
CO		 3781 case KVM_GET_IRQCHIP: {
3782 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3783 struct kvm_irqchip *chip;
1fe779f8 3784
ff5c2c03
SL		 3785 chip = memdup_user(argp, sizeof(*chip));
3786 if (IS_ERR(chip)) {
3787 r = PTR_ERR(chip);
1fe779f8 3788 goto out;
ff5c2c03
SL		 3789 }
3790
1fe779f8
CO		 3791 r = -ENXIO;
3792 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3793 goto get_irqchip_out;
3794 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3795 if (r)
f0d66275 3796 goto get_irqchip_out;
1fe779f8 3797 r = -EFAULT;
f0d66275
DH		 3798 if (copy_to_user(argp, chip, sizeof *chip))
3799 goto get_irqchip_out;
1fe779f8 3800 r = 0;
f0d66275
DH		 3801 get_irqchip_out:
3802 kfree(chip);
1fe779f8
CO		 3803 break;
3804 }
3805 case KVM_SET_IRQCHIP: {
3806 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3807 struct kvm_irqchip *chip;
1fe779f8 3808
ff5c2c03
SL		 3809 chip = memdup_user(argp, sizeof(*chip));
3810 if (IS_ERR(chip)) {
3811 r = PTR_ERR(chip);
1fe779f8 3812 goto out;
ff5c2c03
SL		 3813 }
3814
1fe779f8
CO		 3815 r = -ENXIO;
3816 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3817 goto set_irqchip_out;
3818 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3819 if (r)
f0d66275 3820 goto set_irqchip_out;
1fe779f8 3821 r = 0;
f0d66275
DH		 3822 set_irqchip_out:
3823 kfree(chip);
1fe779f8
CO		 3824 break;
3825 }
e0f63cb9 3826 case KVM_GET_PIT: {
e0f63cb9 3827 r = -EFAULT;
f0d66275 3828 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3829 goto out;
3830 r = -ENXIO;
3831 if (!kvm->arch.vpit)
3832 goto out;
f0d66275 3833 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3834 if (r)
3835 goto out;
3836 r = -EFAULT;
f0d66275 3837 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3838 goto out;
3839 r = 0;
3840 break;
3841 }
3842 case KVM_SET_PIT: {
e0f63cb9 3843 r = -EFAULT;
f0d66275 3844 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3845 goto out;
3846 r = -ENXIO;
3847 if (!kvm->arch.vpit)
3848 goto out;
f0d66275 3849 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3850 break;
3851 }
e9f42757
BK		 3852 case KVM_GET_PIT2: {
3853 r = -ENXIO;
3854 if (!kvm->arch.vpit)
3855 goto out;
3856 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3857 if (r)
3858 goto out;
3859 r = -EFAULT;
3860 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3861 goto out;
3862 r = 0;
3863 break;
3864 }
3865 case KVM_SET_PIT2: {
3866 r = -EFAULT;
3867 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3868 goto out;
3869 r = -ENXIO;
3870 if (!kvm->arch.vpit)
3871 goto out;
3872 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3873 break;
3874 }
52d939a0
MT		 3875 case KVM_REINJECT_CONTROL: {
3876 struct kvm_reinject_control control;
3877 r = -EFAULT;
3878 if (copy_from_user(&control, argp, sizeof(control)))
3879 goto out;
3880 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3881 break;
3882 }
ffde22ac
ES		 3883 case KVM_XEN_HVM_CONFIG: {
3884 r = -EFAULT;
3885 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3886 sizeof(struct kvm_xen_hvm_config)))
3887 goto out;
3888 r = -EINVAL;
3889 if (kvm->arch.xen_hvm_config.flags)
3890 goto out;
3891 r = 0;
3892 break;
3893 }
afbcf7ab 3894 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3895 struct kvm_clock_data user_ns;
3896 u64 now_ns;
3897 s64 delta;
3898
3899 r = -EFAULT;
3900 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3901 goto out;
3902
3903 r = -EINVAL;
3904 if (user_ns.flags)
3905 goto out;
3906
3907 r = 0;
395c6b0a 3908 local_irq_disable();
759379dd 3909 now_ns = get_kernel_ns();
afbcf7ab 3910 delta = user_ns.clock - now_ns;
395c6b0a 3911 local_irq_enable();
afbcf7ab 3912 kvm->arch.kvmclock_offset = delta;
2e762ff7 3913 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3914 break;
3915 }
3916 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3917 struct kvm_clock_data user_ns;
3918 u64 now_ns;
3919
395c6b0a 3920 local_irq_disable();
759379dd 3921 now_ns = get_kernel_ns();
afbcf7ab 3922 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3923 local_irq_enable();
afbcf7ab 3924 user_ns.flags = 0;
97e69aa6 3925 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3926
3927 r = -EFAULT;
3928 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3929 goto out;
3930 r = 0;
3931 break;
3932 }
3933
1fe779f8
CO		 3934 default:
3935 ;
3936 }
3937out:
3938 return r;
3939}
3940
a16b043c 3941static void kvm_init_msr_list(void)
043405e1
CO		 3942{
3943 u32 dummy[2];
3944 unsigned i, j;
3945
e3267cbb
GC		 3946 /* skip the first msrs in the list. KVM-specific */
3947 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3948 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3949 continue;
93c4adc7
PB		 3950
3951 /*
3952 * Even MSRs that are valid in the host may not be exposed
3953 * to the guests in some cases. We could work around this
3954 * in VMX with the generic MSR save/load machinery, but it
3955 * is not really worthwhile since it will really only
3956 * happen with nested virtualization.
3957 */
3958 switch (msrs_to_save[i]) {
3959 case MSR_IA32_BNDCFGS:
3960 if (!kvm_x86_ops->mpx_supported())
3961 continue;
3962 break;
3963 default:
3964 break;
3965 }
3966
043405e1
CO		 3967 if (j < i)
3968 msrs_to_save[j] = msrs_to_save[i];
3969 j++;
3970 }
3971 num_msrs_to_save = j;
3972}
3973
bda9020e
MT		 3974static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3975 const void *v)
bbd9b64e 3976{
70252a10
AK		 3977 int handled = 0;
3978 int n;
3979
3980 do {
3981 n = min(len, 8);
3982 if (!(vcpu->arch.apic &&
3983 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3984 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3985 break;
3986 handled += n;
3987 addr += n;
3988 len -= n;
3989 v += n;
3990 } while (len);
bbd9b64e 3991
70252a10 3992 return handled;
bbd9b64e
CO		 3993}
3994
bda9020e 3995static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3996{
70252a10
AK		 3997 int handled = 0;
3998 int n;
3999
4000 do {
4001 n = min(len, 8);
4002 if (!(vcpu->arch.apic &&
4003 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4004 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4005 break;
4006 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4007 handled += n;
4008 addr += n;
4009 len -= n;
4010 v += n;
4011 } while (len);
bbd9b64e 4012
70252a10 4013 return handled;
bbd9b64e
CO		 4014}
4015
2dafc6c2
GN		 4016static void kvm_set_segment(struct kvm_vcpu *vcpu,
4017 struct kvm_segment *var, int seg)
4018{
4019 kvm_x86_ops->set_segment(vcpu, var, seg);
4020}
4021
4022void kvm_get_segment(struct kvm_vcpu *vcpu,
4023 struct kvm_segment *var, int seg)
4024{
4025 kvm_x86_ops->get_segment(vcpu, var, seg);
4026}
4027
e459e322 4028gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4029{
4030 gpa_t t_gpa;
ab9ae313 4031 struct x86_exception exception;
02f59dc9
JR		 4032
4033 BUG_ON(!mmu_is_nested(vcpu));
4034
4035 /* NPT walks are always user-walks */
4036 access |= PFERR_USER_MASK;
ab9ae313 4037 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4038
4039 return t_gpa;
4040}
4041
ab9ae313
AK		 4042gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4043 struct x86_exception *exception)
1871c602
GN		 4044{
4045 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4046 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4047}
4048
ab9ae313
AK		 4049 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4050 struct x86_exception *exception)
1871c602
GN		 4051{
4052 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4053 access |= PFERR_FETCH_MASK;
ab9ae313 4054 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4055}
4056
ab9ae313
AK		 4057gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4058 struct x86_exception *exception)
1871c602
GN		 4059{
4060 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4061 access |= PFERR_WRITE_MASK;
ab9ae313 4062 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4063}
4064
4065/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4066gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4067 struct x86_exception *exception)
1871c602 4068{
ab9ae313 4069 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4070}
4071
4072static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4073 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4074 struct x86_exception *exception)
bbd9b64e
CO		 4075{
4076 void *data = val;
10589a46 4077 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4078
4079 while (bytes) {
14dfe855 4080 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4081 exception);
bbd9b64e 4082 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4083 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4084 int ret;
4085
bcc55cba 4086 if (gpa == UNMAPPED_GVA)
ab9ae313 4087 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4088 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4089 offset, toread);
10589a46 4090 if (ret < 0) {
c3cd7ffa 4091 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4092 goto out;
4093 }
bbd9b64e 4094
77c2002e
IE		 4095 bytes -= toread;
4096 data += toread;
4097 addr += toread;
bbd9b64e 4098 }
10589a46 4099out:
10589a46 4100 return r;
bbd9b64e 4101}
77c2002e 4102
1871c602 4103/* used for instruction fetching */
0f65dd70
AK		 4104static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4105 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4106 struct x86_exception *exception)
1871c602 4107{
0f65dd70 4108 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4109 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4110 unsigned offset;
4111 int ret;
0f65dd70 4112
44583cba
PB		 4113 /* Inline kvm_read_guest_virt_helper for speed. */
4114 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4115 exception);
4116 if (unlikely(gpa == UNMAPPED_GVA))
4117 return X86EMUL_PROPAGATE_FAULT;
4118
4119 offset = addr & (PAGE_SIZE-1);
4120 if (WARN_ON(offset + bytes > PAGE_SIZE))
4121 bytes = (unsigned)PAGE_SIZE - offset;
4122 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4123 offset, bytes);
4124 if (unlikely(ret < 0))
4125 return X86EMUL_IO_NEEDED;
4126
4127 return X86EMUL_CONTINUE;
1871c602
GN		 4128}
4129
064aea77 4130int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4131 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4132 struct x86_exception *exception)
1871c602 4133{
0f65dd70 4134 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4135 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4136
1871c602 4137 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4138 exception);
1871c602 4139}
064aea77 4140EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4141
0f65dd70
AK		 4142static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4143 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4144 struct x86_exception *exception)
1871c602 4145{
0f65dd70 4146 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4147 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4148}
4149
6a4d7550 4150int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4151 gva_t addr, void *val,
2dafc6c2 4152 unsigned int bytes,
bcc55cba 4153 struct x86_exception *exception)
77c2002e 4154{
0f65dd70 4155 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4156 void *data = val;
4157 int r = X86EMUL_CONTINUE;
4158
4159 while (bytes) {
14dfe855
JR		 4160 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4161 PFERR_WRITE_MASK,
ab9ae313 4162 exception);
77c2002e
IE		 4163 unsigned offset = addr & (PAGE_SIZE-1);
4164 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4165 int ret;
4166
bcc55cba 4167 if (gpa == UNMAPPED_GVA)
ab9ae313 4168 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4169 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4170 if (ret < 0) {
c3cd7ffa 4171 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4172 goto out;
4173 }
4174
4175 bytes -= towrite;
4176 data += towrite;
4177 addr += towrite;
4178 }
4179out:
4180 return r;
4181}
6a4d7550 4182EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4183
af7cc7d1
XG		 4184static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4185 gpa_t *gpa, struct x86_exception *exception,
4186 bool write)
4187{
97d64b78
AK		 4188 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4189 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4190
97d64b78 4191 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4192 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4193 vcpu->arch.access, access)) {
bebb106a
XG		 4194 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4195 (gva & (PAGE_SIZE - 1));
4f022648 4196 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4197 return 1;
4198 }
4199
af7cc7d1
XG		 4200 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4201
4202 if (*gpa == UNMAPPED_GVA)
4203 return -1;
4204
4205 /* For APIC access vmexit */
4206 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4207 return 1;
4208
4f022648
XG		 4209 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4210 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4211 return 1;
4f022648 4212 }
bebb106a 4213
af7cc7d1
XG		 4214 return 0;
4215}
4216
3200f405 4217int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4218 const void *val, int bytes)
bbd9b64e
CO		 4219{
4220 int ret;
4221
4222 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4223 if (ret < 0)
bbd9b64e 4224 return 0;
f57f2ef5 4225 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4226 return 1;
4227}
4228
77d197b2
XG		 4229struct read_write_emulator_ops {
4230 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4231 int bytes);
4232 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4233 void *val, int bytes);
4234 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4235 int bytes, void *val);
4236 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4237 void *val, int bytes);
4238 bool write;
4239};
4240
4241static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4242{
4243 if (vcpu->mmio_read_completed) {
77d197b2 4244 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4245 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4246 vcpu->mmio_read_completed = 0;
4247 return 1;
4248 }
4249
4250 return 0;
4251}
4252
4253static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4254 void *val, int bytes)
4255{
4256 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4257}
4258
4259static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4260 void *val, int bytes)
4261{
4262 return emulator_write_phys(vcpu, gpa, val, bytes);
4263}
4264
4265static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4266{
4267 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4268 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4269}
4270
4271static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4272 void *val, int bytes)
4273{
4274 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4275 return X86EMUL_IO_NEEDED;
4276}
4277
4278static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4279 void *val, int bytes)
4280{
f78146b0
AK		 4281 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4282
87da7e66 4283 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4284 return X86EMUL_CONTINUE;
4285}
4286
0fbe9b0b 4287static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4288 .read_write_prepare = read_prepare,
4289 .read_write_emulate = read_emulate,
4290 .read_write_mmio = vcpu_mmio_read,
4291 .read_write_exit_mmio = read_exit_mmio,
4292};
4293
0fbe9b0b 4294static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4295 .read_write_emulate = write_emulate,
4296 .read_write_mmio = write_mmio,
4297 .read_write_exit_mmio = write_exit_mmio,
4298 .write = true,
4299};
4300
22388a3c
XG		 4301static int emulator_read_write_onepage(unsigned long addr, void *val,
4302 unsigned int bytes,
4303 struct x86_exception *exception,
4304 struct kvm_vcpu *vcpu,
0fbe9b0b 4305 const struct read_write_emulator_ops *ops)
bbd9b64e 4306{
af7cc7d1
XG		 4307 gpa_t gpa;
4308 int handled, ret;
22388a3c 4309 bool write = ops->write;
f78146b0 4310 struct kvm_mmio_fragment *frag;
10589a46 4311
22388a3c 4312 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4313
af7cc7d1 4314 if (ret < 0)
bbd9b64e 4315 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4316
4317 /* For APIC access vmexit */
af7cc7d1 4318 if (ret)
bbd9b64e
CO		 4319 goto mmio;
4320
22388a3c 4321 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4322 return X86EMUL_CONTINUE;
4323
4324mmio:
4325 /*
4326 * Is this MMIO handled locally?
4327 */
22388a3c 4328 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4329 if (handled == bytes)
bbd9b64e 4330 return X86EMUL_CONTINUE;
bbd9b64e 4331
70252a10
AK		 4332 gpa += handled;
4333 bytes -= handled;
4334 val += handled;
4335
87da7e66
XG		 4336 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4337 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4338 frag->gpa = gpa;
4339 frag->data = val;
4340 frag->len = bytes;
f78146b0 4341 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4342}
4343
22388a3c
XG		 4344int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4345 void *val, unsigned int bytes,
4346 struct x86_exception *exception,
0fbe9b0b 4347 const struct read_write_emulator_ops *ops)
bbd9b64e 4348{
0f65dd70 4349 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4350 gpa_t gpa;
4351 int rc;
4352
4353 if (ops->read_write_prepare &&
4354 ops->read_write_prepare(vcpu, val, bytes))
4355 return X86EMUL_CONTINUE;
4356
4357 vcpu->mmio_nr_fragments = 0;
0f65dd70 4358
bbd9b64e
CO		 4359 /* Crossing a page boundary? */
4360 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4361 int now;
bbd9b64e
CO		 4362
4363 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4364 rc = emulator_read_write_onepage(addr, val, now, exception,
4365 vcpu, ops);
4366
bbd9b64e
CO		 4367 if (rc != X86EMUL_CONTINUE)
4368 return rc;
4369 addr += now;
4370 val += now;
4371 bytes -= now;
4372 }
22388a3c 4373
f78146b0
AK		 4374 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4375 vcpu, ops);
4376 if (rc != X86EMUL_CONTINUE)
4377 return rc;
4378
4379 if (!vcpu->mmio_nr_fragments)
4380 return rc;
4381
4382 gpa = vcpu->mmio_fragments[0].gpa;
4383
4384 vcpu->mmio_needed = 1;
4385 vcpu->mmio_cur_fragment = 0;
4386
87da7e66 4387 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4388 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4389 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4390 vcpu->run->mmio.phys_addr = gpa;
4391
4392 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4393}
4394
4395static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4396 unsigned long addr,
4397 void *val,
4398 unsigned int bytes,
4399 struct x86_exception *exception)
4400{
4401 return emulator_read_write(ctxt, addr, val, bytes,
4402 exception, &read_emultor);
4403}
4404
4405int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4406 unsigned long addr,
4407 const void *val,
4408 unsigned int bytes,
4409 struct x86_exception *exception)
4410{
4411 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4412 exception, &write_emultor);
bbd9b64e 4413}
bbd9b64e 4414
daea3e73
AK		 4415#define CMPXCHG_TYPE(t, ptr, old, new) \
4416 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4417
4418#ifdef CONFIG_X86_64
4419# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4420#else
4421# define CMPXCHG64(ptr, old, new) \
9749a6c0 4422 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4423#endif
4424
0f65dd70
AK		 4425static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4426 unsigned long addr,
bbd9b64e
CO		 4427 const void *old,
4428 const void *new,
4429 unsigned int bytes,
0f65dd70 4430 struct x86_exception *exception)
bbd9b64e 4431{
0f65dd70 4432 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4433 gpa_t gpa;
4434 struct page *page;
4435 char *kaddr;
4436 bool exchanged;
2bacc55c 4437
daea3e73
AK		 4438 /* guests cmpxchg8b have to be emulated atomically */
4439 if (bytes > 8 || (bytes & (bytes - 1)))
4440 goto emul_write;
10589a46 4441
daea3e73 4442 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4443
daea3e73
AK		 4444 if (gpa == UNMAPPED_GVA ||
4445 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4446 goto emul_write;
2bacc55c 4447
daea3e73
AK		 4448 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4449 goto emul_write;
72dc67a6 4450
daea3e73 4451 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4452 if (is_error_page(page))
c19b8bd6 4453 goto emul_write;
72dc67a6 4454
8fd75e12 4455 kaddr = kmap_atomic(page);
daea3e73
AK		 4456 kaddr += offset_in_page(gpa);
4457 switch (bytes) {
4458 case 1:
4459 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4460 break;
4461 case 2:
4462 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4463 break;
4464 case 4:
4465 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4466 break;
4467 case 8:
4468 exchanged = CMPXCHG64(kaddr, old, new);
4469 break;
4470 default:
4471 BUG();
2bacc55c 4472 }
8fd75e12 4473 kunmap_atomic(kaddr);
daea3e73
AK		 4474 kvm_release_page_dirty(page);
4475
4476 if (!exchanged)
4477 return X86EMUL_CMPXCHG_FAILED;
4478
d3714010 4479 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4480 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4481
4482 return X86EMUL_CONTINUE;
4a5f48f6 4483
3200f405 4484emul_write:
daea3e73 4485 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4486
0f65dd70 4487 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4488}
4489
cf8f70bf
GN		 4490static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4491{
4492 /* TODO: String I/O for in kernel device */
4493 int r;
4494
4495 if (vcpu->arch.pio.in)
4496 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4497 vcpu->arch.pio.size, pd);
4498 else
4499 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4500 vcpu->arch.pio.port, vcpu->arch.pio.size,
4501 pd);
4502 return r;
4503}
4504
6f6fbe98
XG		 4505static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4506 unsigned short port, void *val,
4507 unsigned int count, bool in)
cf8f70bf 4508{
cf8f70bf 4509 vcpu->arch.pio.port = port;
6f6fbe98 4510 vcpu->arch.pio.in = in;
7972995b 4511 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4512 vcpu->arch.pio.size = size;
4513
4514 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4515 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4516 return 1;
4517 }
4518
4519 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4520 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4521 vcpu->run->io.size = size;
4522 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4523 vcpu->run->io.count = count;
4524 vcpu->run->io.port = port;
4525
4526 return 0;
4527}
4528
6f6fbe98
XG		 4529static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4530 int size, unsigned short port, void *val,
4531 unsigned int count)
cf8f70bf 4532{
ca1d4a9e 4533 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4534 int ret;
ca1d4a9e 4535
6f6fbe98
XG		 4536 if (vcpu->arch.pio.count)
4537 goto data_avail;
cf8f70bf 4538
6f6fbe98
XG		 4539 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4540 if (ret) {
4541data_avail:
4542 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4543 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4544 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4545 return 1;
4546 }
4547
cf8f70bf
GN		 4548 return 0;
4549}
4550
6f6fbe98
XG		 4551static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4552 int size, unsigned short port,
4553 const void *val, unsigned int count)
4554{
4555 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4556
4557 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4558 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4559 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4560}
4561
bbd9b64e
CO		 4562static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4563{
4564 return kvm_x86_ops->get_segment_base(vcpu, seg);
4565}
4566
3cb16fe7 4567static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4568{
3cb16fe7 4569 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4570}
4571
f5f48ee1
SY		 4572int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4573{
4574 if (!need_emulate_wbinvd(vcpu))
4575 return X86EMUL_CONTINUE;
4576
4577 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4578 int cpu = get_cpu();
4579
4580 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4581 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4582 wbinvd_ipi, NULL, 1);
2eec7343 4583 put_cpu();
f5f48ee1 4584 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4585 } else
4586 wbinvd();
f5f48ee1
SY		 4587 return X86EMUL_CONTINUE;
4588}
4589EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4590
bcaf5cc5
AK		 4591static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4592{
4593 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4594}
4595
717746e3 4596int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4597{
717746e3 4598 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4599}
4600
717746e3 4601int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4602{
338dbc97 4603
717746e3 4604 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4605}
4606
52a46617 4607static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4608{
52a46617 4609 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4610}
4611
717746e3 4612static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4613{
717746e3 4614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4615 unsigned long value;
4616
4617 switch (cr) {
4618 case 0:
4619 value = kvm_read_cr0(vcpu);
4620 break;
4621 case 2:
4622 value = vcpu->arch.cr2;
4623 break;
4624 case 3:
9f8fe504 4625 value = kvm_read_cr3(vcpu);
52a46617
GN		 4626 break;
4627 case 4:
4628 value = kvm_read_cr4(vcpu);
4629 break;
4630 case 8:
4631 value = kvm_get_cr8(vcpu);
4632 break;
4633 default:
a737f256 4634 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4635 return 0;
4636 }
4637
4638 return value;
4639}
4640
717746e3 4641static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4642{
717746e3 4643 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4644 int res = 0;
4645
52a46617
GN		 4646 switch (cr) {
4647 case 0:
49a9b07e 4648 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4649 break;
4650 case 2:
4651 vcpu->arch.cr2 = val;
4652 break;
4653 case 3:
2390218b 4654 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4655 break;
4656 case 4:
a83b29c6 4657 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4658 break;
4659 case 8:
eea1cff9 4660 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4661 break;
4662 default:
a737f256 4663 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4664 res = -1;
52a46617 4665 }
0f12244f
GN		 4666
4667 return res;
52a46617
GN		 4668}
4669
717746e3 4670static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4671{
717746e3 4672 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4673}
4674
4bff1e86 4675static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4676{
4bff1e86 4677 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4678}
4679
4bff1e86 4680static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4681{
4bff1e86 4682 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4683}
4684
1ac9d0cf
AK		 4685static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4686{
4687 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4688}
4689
4690static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4691{
4692 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4693}
4694
4bff1e86
AK		 4695static unsigned long emulator_get_cached_segment_base(
4696 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4697{
4bff1e86 4698 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4699}
4700
1aa36616
AK		 4701static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4702 struct desc_struct *desc, u32 *base3,
4703 int seg)
2dafc6c2
GN		 4704{
4705 struct kvm_segment var;
4706
4bff1e86 4707 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4708 *selector = var.selector;
2dafc6c2 4709
378a8b09
GN		 4710 if (var.unusable) {
4711 memset(desc, 0, sizeof(*desc));
2dafc6c2 4712 return false;
378a8b09 4713 }
2dafc6c2
GN		 4714
4715 if (var.g)
4716 var.limit >>= 12;
4717 set_desc_limit(desc, var.limit);
4718 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4719#ifdef CONFIG_X86_64
4720 if (base3)
4721 *base3 = var.base >> 32;
4722#endif
2dafc6c2
GN		 4723 desc->type = var.type;
4724 desc->s = var.s;
4725 desc->dpl = var.dpl;
4726 desc->p = var.present;
4727 desc->avl = var.avl;
4728 desc->l = var.l;
4729 desc->d = var.db;
4730 desc->g = var.g;
4731
4732 return true;
4733}
4734
1aa36616
AK		 4735static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4736 struct desc_struct *desc, u32 base3,
4737 int seg)
2dafc6c2 4738{
4bff1e86 4739 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4740 struct kvm_segment var;
4741
1aa36616 4742 var.selector = selector;
2dafc6c2 4743 var.base = get_desc_base(desc);
5601d05b
GN		 4744#ifdef CONFIG_X86_64
4745 var.base |= ((u64)base3) << 32;
4746#endif
2dafc6c2
GN		 4747 var.limit = get_desc_limit(desc);
4748 if (desc->g)
4749 var.limit = (var.limit << 12) | 0xfff;
4750 var.type = desc->type;
2dafc6c2
GN		 4751 var.dpl = desc->dpl;
4752 var.db = desc->d;
4753 var.s = desc->s;
4754 var.l = desc->l;
4755 var.g = desc->g;
4756 var.avl = desc->avl;
4757 var.present = desc->p;
4758 var.unusable = !var.present;
4759 var.padding = 0;
4760
4761 kvm_set_segment(vcpu, &var, seg);
4762 return;
4763}
4764
717746e3
AK		 4765static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4766 u32 msr_index, u64 *pdata)
4767{
4768 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4769}
4770
4771static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4772 u32 msr_index, u64 data)
4773{
8fe8ab46
WA		 4774 struct msr_data msr;
4775
4776 msr.data = data;
4777 msr.index = msr_index;
4778 msr.host_initiated = false;
4779 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4780}
4781
67f4d428
NA		 4782static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4783 u32 pmc)
4784{
4785 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4786}
4787
222d21aa
AK		 4788static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4789 u32 pmc, u64 *pdata)
4790{
4791 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4792}
4793
6c3287f7
AK		 4794static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4795{
4796 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4797}
4798
5037f6f3
AK		 4799static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4800{
4801 preempt_disable();
5197b808 4802 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4803 /*
4804 * CR0.TS may reference the host fpu state, not the guest fpu state,
4805 * so it may be clear at this point.
4806 */
4807 clts();
4808}
4809
4810static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4811{
4812 preempt_enable();
4813}
4814
2953538e 4815static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4816 struct x86_instruction_info *info,
c4f035c6
AK		 4817 enum x86_intercept_stage stage)
4818{
2953538e 4819 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4820}
4821
0017f93a 4822static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4823 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4824{
0017f93a 4825 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4826}
4827
dd856efa
AK		 4828static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4829{
4830 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4831}
4832
4833static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4834{
4835 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4836}
4837
0225fb50 4838static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4839 .read_gpr = emulator_read_gpr,
4840 .write_gpr = emulator_write_gpr,
1871c602 4841 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4842 .write_std = kvm_write_guest_virt_system,
1871c602 4843 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4844 .read_emulated = emulator_read_emulated,
4845 .write_emulated = emulator_write_emulated,
4846 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4847 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4848 .pio_in_emulated = emulator_pio_in_emulated,
4849 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4850 .get_segment = emulator_get_segment,
4851 .set_segment = emulator_set_segment,
5951c442 4852 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4853 .get_gdt = emulator_get_gdt,
160ce1f1 4854 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4855 .set_gdt = emulator_set_gdt,
4856 .set_idt = emulator_set_idt,
52a46617
GN		 4857 .get_cr = emulator_get_cr,
4858 .set_cr = emulator_set_cr,
9c537244 4859 .cpl = emulator_get_cpl,
35aa5375
GN		 4860 .get_dr = emulator_get_dr,
4861 .set_dr = emulator_set_dr,
717746e3
AK		 4862 .set_msr = emulator_set_msr,
4863 .get_msr = emulator_get_msr,
67f4d428 4864 .check_pmc = emulator_check_pmc,
222d21aa 4865 .read_pmc = emulator_read_pmc,
6c3287f7 4866 .halt = emulator_halt,
bcaf5cc5 4867 .wbinvd = emulator_wbinvd,
d6aa1000 4868 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4869 .get_fpu = emulator_get_fpu,
4870 .put_fpu = emulator_put_fpu,
c4f035c6 4871 .intercept = emulator_intercept,
bdb42f5a 4872 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4873};
4874
95cb2295
GN		 4875static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4876{
37ccdcbe 4877 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4878 /*
4879 * an sti; sti; sequence only disable interrupts for the first
4880 * instruction. So, if the last instruction, be it emulated or
4881 * not, left the system with the INT_STI flag enabled, it
4882 * means that the last instruction is an sti. We should not
4883 * leave the flag on in this case. The same goes for mov ss
4884 */
37ccdcbe
PB		 4885 if (int_shadow & mask)
4886 mask = 0;
6addfc42 4887 if (unlikely(int_shadow || mask)) {
95cb2295 4888 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4889 if (!mask)
4890 kvm_make_request(KVM_REQ_EVENT, vcpu);
4891 }
95cb2295
GN		 4892}
4893
54b8486f
GN		 4894static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4895{
4896 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4897 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4898 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4899 else if (ctxt->exception.error_code_valid)
4900 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4901 ctxt->exception.error_code);
54b8486f 4902 else
da9cb575 4903 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4904}
4905
8ec4722d
MG		 4906static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4907{
adf52235 4908 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4909 int cs_db, cs_l;
4910
8ec4722d
MG		 4911 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4912
adf52235
TY		 4913 ctxt->eflags = kvm_get_rflags(vcpu);
4914 ctxt->eip = kvm_rip_read(vcpu);
4915 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4916 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4917 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4918 cs_db ? X86EMUL_MODE_PROT32 :
4919 X86EMUL_MODE_PROT16;
4920 ctxt->guest_mode = is_guest_mode(vcpu);
4921
dd856efa 4922 init_decode_cache(ctxt);
7ae441ea 4923 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4924}
4925
71f9833b 4926int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4927{
9d74191a 4928 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4929 int ret;
4930
4931 init_emulate_ctxt(vcpu);
4932
9dac77fa
AK		 4933 ctxt->op_bytes = 2;
4934 ctxt->ad_bytes = 2;
4935 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4936 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4937
4938 if (ret != X86EMUL_CONTINUE)
4939 return EMULATE_FAIL;
4940
9dac77fa 4941 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4942 kvm_rip_write(vcpu, ctxt->eip);
4943 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4944
4945 if (irq == NMI_VECTOR)
7460fb4a 4946 vcpu->arch.nmi_pending = 0;
63995653
MG		 4947 else
4948 vcpu->arch.interrupt.pending = false;
4949
4950 return EMULATE_DONE;
4951}
4952EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4953
6d77dbfc
GN		 4954static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4955{
fc3a9157
JR		 4956 int r = EMULATE_DONE;
4957
6d77dbfc
GN		 4958 ++vcpu->stat.insn_emulation_fail;
4959 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4960 if (!is_guest_mode(vcpu)) {
4961 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4962 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4963 vcpu->run->internal.ndata = 0;
4964 r = EMULATE_FAIL;
4965 }
6d77dbfc 4966 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4967
4968 return r;
6d77dbfc
GN		 4969}
4970
93c05d3e 4971static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4972 bool write_fault_to_shadow_pgtable,
4973 int emulation_type)
a6f177ef 4974{
95b3cf69 4975 gpa_t gpa = cr2;
8e3d9d06 4976 pfn_t pfn;
a6f177ef 4977
991eebf9
GN		 4978 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4979 return false;
4980
95b3cf69
XG		 4981 if (!vcpu->arch.mmu.direct_map) {
4982 /*
4983 * Write permission should be allowed since only
4984 * write access need to be emulated.
4985 */
4986 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4987
95b3cf69
XG		 4988 /*
4989 * If the mapping is invalid in guest, let cpu retry
4990 * it to generate fault.
4991 */
4992 if (gpa == UNMAPPED_GVA)
4993 return true;
4994 }
a6f177ef 4995
8e3d9d06
XG		 4996 /*
4997 * Do not retry the unhandleable instruction if it faults on the
4998 * readonly host memory, otherwise it will goto a infinite loop:
4999 * retry instruction -> write #PF -> emulation fail -> retry
5000 * instruction -> ...
5001 */
5002 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5003
5004 /*
5005 * If the instruction failed on the error pfn, it can not be fixed,
5006 * report the error to userspace.
5007 */
5008 if (is_error_noslot_pfn(pfn))
5009 return false;
5010
5011 kvm_release_pfn_clean(pfn);
5012
5013 /* The instructions are well-emulated on direct mmu. */
5014 if (vcpu->arch.mmu.direct_map) {
5015 unsigned int indirect_shadow_pages;
5016
5017 spin_lock(&vcpu->kvm->mmu_lock);
5018 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5019 spin_unlock(&vcpu->kvm->mmu_lock);
5020
5021 if (indirect_shadow_pages)
5022 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5023
a6f177ef 5024 return true;
8e3d9d06 5025 }
a6f177ef 5026
95b3cf69
XG		 5027 /*
5028 * if emulation was due to access to shadowed page table
5029 * and it failed try to unshadow page and re-enter the
5030 * guest to let CPU execute the instruction.
5031 */
5032 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5033
5034 /*
5035 * If the access faults on its page table, it can not
5036 * be fixed by unprotecting shadow page and it should
5037 * be reported to userspace.
5038 */
5039 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5040}
5041
1cb3f3ae
XG		 5042static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5043 unsigned long cr2, int emulation_type)
5044{
5045 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5046 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5047
5048 last_retry_eip = vcpu->arch.last_retry_eip;
5049 last_retry_addr = vcpu->arch.last_retry_addr;
5050
5051 /*
5052 * If the emulation is caused by #PF and it is non-page_table
5053 * writing instruction, it means the VM-EXIT is caused by shadow
5054 * page protected, we can zap the shadow page and retry this
5055 * instruction directly.
5056 *
5057 * Note: if the guest uses a non-page-table modifying instruction
5058 * on the PDE that points to the instruction, then we will unmap
5059 * the instruction and go to an infinite loop. So, we cache the
5060 * last retried eip and the last fault address, if we meet the eip
5061 * and the address again, we can break out of the potential infinite
5062 * loop.
5063 */
5064 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5065
5066 if (!(emulation_type & EMULTYPE_RETRY))
5067 return false;
5068
5069 if (x86_page_table_writing_insn(ctxt))
5070 return false;
5071
5072 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5073 return false;
5074
5075 vcpu->arch.last_retry_eip = ctxt->eip;
5076 vcpu->arch.last_retry_addr = cr2;
5077
5078 if (!vcpu->arch.mmu.direct_map)
5079 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5080
22368028 5081 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5082
5083 return true;
5084}
5085
716d51ab
GN		 5086static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5087static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5088
4a1e10d5
PB		 5089static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5090 unsigned long *db)
5091{
5092 u32 dr6 = 0;
5093 int i;
5094 u32 enable, rwlen;
5095
5096 enable = dr7;
5097 rwlen = dr7 >> 16;
5098 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5099 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5100 dr6 |= (1 << i);
5101 return dr6;
5102}
5103
6addfc42 5104static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5105{
5106 struct kvm_run *kvm_run = vcpu->run;
5107
5108 /*
6addfc42
PB		 5109 * rflags is the old, "raw" value of the flags. The new value has
5110 * not been saved yet.
663f4c61
PB		 5111 *
5112 * This is correct even for TF set by the guest, because "the
5113 * processor will not generate this exception after the instruction
5114 * that sets the TF flag".
5115 */
663f4c61
PB		 5116 if (unlikely(rflags & X86_EFLAGS_TF)) {
5117 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5118 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5119 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5120 kvm_run->debug.arch.exception = DB_VECTOR;
5121 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5122 *r = EMULATE_USER_EXIT;
5123 } else {
5124 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5125 /*
5126 * "Certain debug exceptions may clear bit 0-3. The
5127 * remaining contents of the DR6 register are never
5128 * cleared by the processor".
5129 */
5130 vcpu->arch.dr6 &= ~15;
5131 vcpu->arch.dr6 |= DR6_BS;
5132 kvm_queue_exception(vcpu, DB_VECTOR);
5133 }
5134 }
5135}
5136
4a1e10d5
PB		 5137static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5138{
5139 struct kvm_run *kvm_run = vcpu->run;
5140 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5141 u32 dr6 = 0;
5142
5143 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5144 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5145 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5146 vcpu->arch.guest_debug_dr7,
5147 vcpu->arch.eff_db);
5148
5149 if (dr6 != 0) {
5150 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5151 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5152 get_segment_base(vcpu, VCPU_SREG_CS);
5153
5154 kvm_run->debug.arch.exception = DB_VECTOR;
5155 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5156 *r = EMULATE_USER_EXIT;
5157 return true;
5158 }
5159 }
5160
5161 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5162 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5163 vcpu->arch.dr7,
5164 vcpu->arch.db);
5165
5166 if (dr6 != 0) {
5167 vcpu->arch.dr6 &= ~15;
5168 vcpu->arch.dr6 |= dr6;
5169 kvm_queue_exception(vcpu, DB_VECTOR);
5170 *r = EMULATE_DONE;
5171 return true;
5172 }
5173 }
5174
5175 return false;
5176}
5177
51d8b661
AP		 5178int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5179 unsigned long cr2,
dc25e89e
AP		 5180 int emulation_type,
5181 void *insn,
5182 int insn_len)
bbd9b64e 5183{
95cb2295 5184 int r;
9d74191a 5185 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5186 bool writeback = true;
93c05d3e 5187 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5188
93c05d3e
XG		 5189 /*
5190 * Clear write_fault_to_shadow_pgtable here to ensure it is
5191 * never reused.
5192 */
5193 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5194 kvm_clear_exception_queue(vcpu);
8d7d8102 5195
571008da 5196 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5197 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5198
5199 /*
5200 * We will reenter on the same instruction since
5201 * we do not set complete_userspace_io. This does not
5202 * handle watchpoints yet, those would be handled in
5203 * the emulate_ops.
5204 */
5205 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5206 return r;
5207
9d74191a
TY		 5208 ctxt->interruptibility = 0;
5209 ctxt->have_exception = false;
5210 ctxt->perm_ok = false;
bbd9b64e 5211
b51e974f 5212 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5213
9d74191a 5214 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5215
e46479f8 5216 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5217 ++vcpu->stat.insn_emulation;
1d2887e2 5218 if (r != EMULATION_OK) {
4005996e
AK		 5219 if (emulation_type & EMULTYPE_TRAP_UD)
5220 return EMULATE_FAIL;
991eebf9
GN		 5221 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5222 emulation_type))
bbd9b64e 5223 return EMULATE_DONE;
6d77dbfc
GN		 5224 if (emulation_type & EMULTYPE_SKIP)
5225 return EMULATE_FAIL;
5226 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5227 }
5228 }
5229
ba8afb6b 5230 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5231 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5232 return EMULATE_DONE;
5233 }
5234
1cb3f3ae
XG		 5235 if (retry_instruction(ctxt, cr2, emulation_type))
5236 return EMULATE_DONE;
5237
7ae441ea 5238 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5239 changes registers values during IO operation */
7ae441ea
GN		 5240 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5241 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5242 emulator_invalidate_register_cache(ctxt);
7ae441ea 5243 }
4d2179e1 5244
5cd21917 5245restart:
9d74191a 5246 r = x86_emulate_insn(ctxt);
bbd9b64e 5247
775fde86
JR		 5248 if (r == EMULATION_INTERCEPTED)
5249 return EMULATE_DONE;
5250
d2ddd1c4 5251 if (r == EMULATION_FAILED) {
991eebf9
GN		 5252 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5253 emulation_type))
c3cd7ffa
GN		 5254 return EMULATE_DONE;
5255
6d77dbfc 5256 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5257 }
5258
9d74191a 5259 if (ctxt->have_exception) {
54b8486f 5260 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5261 r = EMULATE_DONE;
5262 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5263 if (!vcpu->arch.pio.in) {
5264 /* FIXME: return into emulator if single-stepping. */
3457e419 5265 vcpu->arch.pio.count = 0;
0912c977 5266 } else {
7ae441ea 5267 writeback = false;
716d51ab
GN		 5268 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5269 }
ac0a48c3 5270 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5271 } else if (vcpu->mmio_needed) {
5272 if (!vcpu->mmio_is_write)
5273 writeback = false;
ac0a48c3 5274 r = EMULATE_USER_EXIT;
716d51ab 5275 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5276 } else if (r == EMULATION_RESTART)
5cd21917 5277 goto restart;
d2ddd1c4
GN		 5278 else
5279 r = EMULATE_DONE;
f850e2e6 5280
7ae441ea 5281 if (writeback) {
6addfc42 5282 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5283 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5284 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5285 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5286 if (r == EMULATE_DONE)
6addfc42
PB		 5287 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5288 __kvm_set_rflags(vcpu, ctxt->eflags);
5289
5290 /*
5291 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5292 * do nothing, and it will be requested again as soon as
5293 * the shadow expires. But we still need to check here,
5294 * because POPF has no interrupt shadow.
5295 */
5296 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5297 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5298 } else
5299 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5300
5301 return r;
de7d789a 5302}
51d8b661 5303EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5304
cf8f70bf 5305int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5306{
cf8f70bf 5307 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5308 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5309 size, port, &val, 1);
cf8f70bf 5310 /* do not return to emulator after return from userspace */
7972995b 5311 vcpu->arch.pio.count = 0;
de7d789a
CO		 5312 return ret;
5313}
cf8f70bf 5314EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5315
8cfdc000
ZA		 5316static void tsc_bad(void *info)
5317{
0a3aee0d 5318 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5319}
5320
5321static void tsc_khz_changed(void *data)
c8076604 5322{
8cfdc000
ZA		 5323 struct cpufreq_freqs *freq = data;
5324 unsigned long khz = 0;
5325
5326 if (data)
5327 khz = freq->new;
5328 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5329 khz = cpufreq_quick_get(raw_smp_processor_id());
5330 if (!khz)
5331 khz = tsc_khz;
0a3aee0d 5332 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5333}
5334
c8076604
GH		 5335static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5336 void *data)
5337{
5338 struct cpufreq_freqs *freq = data;
5339 struct kvm *kvm;
5340 struct kvm_vcpu *vcpu;
5341 int i, send_ipi = 0;
5342
8cfdc000
ZA		 5343 /*
5344 * We allow guests to temporarily run on slowing clocks,
5345 * provided we notify them after, or to run on accelerating
5346 * clocks, provided we notify them before. Thus time never
5347 * goes backwards.
5348 *
5349 * However, we have a problem. We can't atomically update
5350 * the frequency of a given CPU from this function; it is
5351 * merely a notifier, which can be called from any CPU.
5352 * Changing the TSC frequency at arbitrary points in time
5353 * requires a recomputation of local variables related to
5354 * the TSC for each VCPU. We must flag these local variables
5355 * to be updated and be sure the update takes place with the
5356 * new frequency before any guests proceed.
5357 *
5358 * Unfortunately, the combination of hotplug CPU and frequency
5359 * change creates an intractable locking scenario; the order
5360 * of when these callouts happen is undefined with respect to
5361 * CPU hotplug, and they can race with each other. As such,
5362 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5363 * undefined; you can actually have a CPU frequency change take
5364 * place in between the computation of X and the setting of the
5365 * variable. To protect against this problem, all updates of
5366 * the per_cpu tsc_khz variable are done in an interrupt
5367 * protected IPI, and all callers wishing to update the value
5368 * must wait for a synchronous IPI to complete (which is trivial
5369 * if the caller is on the CPU already). This establishes the
5370 * necessary total order on variable updates.
5371 *
5372 * Note that because a guest time update may take place
5373 * anytime after the setting of the VCPU's request bit, the
5374 * correct TSC value must be set before the request. However,
5375 * to ensure the update actually makes it to any guest which
5376 * starts running in hardware virtualization between the set
5377 * and the acquisition of the spinlock, we must also ping the
5378 * CPU after setting the request bit.
5379 *
5380 */
5381
c8076604
GH		 5382 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5383 return 0;
5384 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5385 return 0;
8cfdc000
ZA		 5386
5387 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5388
2f303b74 5389 spin_lock(&kvm_lock);
c8076604 5390 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5391 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5392 if (vcpu->cpu != freq->cpu)
5393 continue;
c285545f 5394 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5395 if (vcpu->cpu != smp_processor_id())
8cfdc000 5396 send_ipi = 1;
c8076604
GH		 5397 }
5398 }
2f303b74 5399 spin_unlock(&kvm_lock);
c8076604
GH		 5400
5401 if (freq->old < freq->new && send_ipi) {
5402 /*
5403 * We upscale the frequency. Must make the guest
5404 * doesn't see old kvmclock values while running with
5405 * the new frequency, otherwise we risk the guest sees
5406 * time go backwards.
5407 *
5408 * In case we update the frequency for another cpu
5409 * (which might be in guest context) send an interrupt
5410 * to kick the cpu out of guest context. Next time
5411 * guest context is entered kvmclock will be updated,
5412 * so the guest will not see stale values.
5413 */
8cfdc000 5414 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5415 }
5416 return 0;
5417}
5418
5419static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5420 .notifier_call = kvmclock_cpufreq_notifier
5421};
5422
5423static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5424 unsigned long action, void *hcpu)
5425{
5426 unsigned int cpu = (unsigned long)hcpu;
5427
5428 switch (action) {
5429 case CPU_ONLINE:
5430 case CPU_DOWN_FAILED:
5431 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5432 break;
5433 case CPU_DOWN_PREPARE:
5434 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5435 break;
5436 }
5437 return NOTIFY_OK;
5438}
5439
5440static struct notifier_block kvmclock_cpu_notifier_block = {
5441 .notifier_call = kvmclock_cpu_notifier,
5442 .priority = -INT_MAX
c8076604
GH		 5443};
5444
b820cc0c
ZA		 5445static void kvm_timer_init(void)
5446{
5447 int cpu;
5448
c285545f 5449 max_tsc_khz = tsc_khz;
460dd42e
SB		 5450
5451 cpu_notifier_register_begin();
b820cc0c 5452 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5453#ifdef CONFIG_CPU_FREQ
5454 struct cpufreq_policy policy;
5455 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5456 cpu = get_cpu();
5457 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5458 if (policy.cpuinfo.max_freq)
5459 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5460 put_cpu();
c285545f 5461#endif
b820cc0c
ZA		 5462 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5463 CPUFREQ_TRANSITION_NOTIFIER);
5464 }
c285545f 5465 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5466 for_each_online_cpu(cpu)
5467 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5468
5469 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5470 cpu_notifier_register_done();
5471
b820cc0c
ZA		 5472}
5473
ff9d07a0
ZY		 5474static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5475
f5132b01 5476int kvm_is_in_guest(void)
ff9d07a0 5477{
086c9855 5478 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5479}
5480
5481static int kvm_is_user_mode(void)
5482{
5483 int user_mode = 3;
dcf46b94 5484
086c9855
AS		 5485 if (__this_cpu_read(current_vcpu))
5486 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5487
ff9d07a0
ZY		 5488 return user_mode != 0;
5489}
5490
5491static unsigned long kvm_get_guest_ip(void)
5492{
5493 unsigned long ip = 0;
dcf46b94 5494
086c9855
AS		 5495 if (__this_cpu_read(current_vcpu))
5496 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5497
ff9d07a0
ZY		 5498 return ip;
5499}
5500
5501static struct perf_guest_info_callbacks kvm_guest_cbs = {
5502 .is_in_guest = kvm_is_in_guest,
5503 .is_user_mode = kvm_is_user_mode,
5504 .get_guest_ip = kvm_get_guest_ip,
5505};
5506
5507void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5508{
086c9855 5509 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5510}
5511EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5512
5513void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5514{
086c9855 5515 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5516}
5517EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5518
ce88decf
XG		 5519static void kvm_set_mmio_spte_mask(void)
5520{
5521 u64 mask;
5522 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5523
5524 /*
5525 * Set the reserved bits and the present bit of an paging-structure
5526 * entry to generate page fault with PFER.RSV = 1.
5527 */
885032b9
XG		 5528 /* Mask the reserved physical address bits. */
5529 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5530
5531 /* Bit 62 is always reserved for 32bit host. */
5532 mask |= 0x3ull << 62;
5533
5534 /* Set the present bit. */
ce88decf
XG		 5535 mask |= 1ull;
5536
5537#ifdef CONFIG_X86_64
5538 /*
5539 * If reserved bit is not supported, clear the present bit to disable
5540 * mmio page fault.
5541 */
5542 if (maxphyaddr == 52)
5543 mask &= ~1ull;
5544#endif
5545
5546 kvm_mmu_set_mmio_spte_mask(mask);
5547}
5548
16e8d74d
MT		 5549#ifdef CONFIG_X86_64
5550static void pvclock_gtod_update_fn(struct work_struct *work)
5551{
d828199e
MT		 5552 struct kvm *kvm;
5553
5554 struct kvm_vcpu *vcpu;
5555 int i;
5556
2f303b74 5557 spin_lock(&kvm_lock);
d828199e
MT		 5558 list_for_each_entry(kvm, &vm_list, vm_list)
5559 kvm_for_each_vcpu(i, vcpu, kvm)
5560 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5561 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5562 spin_unlock(&kvm_lock);
16e8d74d
MT		 5563}
5564
5565static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5566
5567/*
5568 * Notification about pvclock gtod data update.
5569 */
5570static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5571 void *priv)
5572{
5573 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5574 struct timekeeper *tk = priv;
5575
5576 update_pvclock_gtod(tk);
5577
5578 /* disable master clock if host does not trust, or does not
5579 * use, TSC clocksource
5580 */
5581 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5582 atomic_read(&kvm_guest_has_master_clock) != 0)
5583 queue_work(system_long_wq, &pvclock_gtod_work);
5584
5585 return 0;
5586}
5587
5588static struct notifier_block pvclock_gtod_notifier = {
5589 .notifier_call = pvclock_gtod_notify,
5590};
5591#endif
5592
f8c16bba 5593int kvm_arch_init(void *opaque)
043405e1 5594{
b820cc0c 5595 int r;
6b61edf7 5596 struct kvm_x86_ops *ops = opaque;
f8c16bba 5597
f8c16bba
ZX		 5598 if (kvm_x86_ops) {
5599 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5600 r = -EEXIST;
5601 goto out;
f8c16bba
ZX		 5602 }
5603
5604 if (!ops->cpu_has_kvm_support()) {
5605 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5606 r = -EOPNOTSUPP;
5607 goto out;
f8c16bba
ZX		 5608 }
5609 if (ops->disabled_by_bios()) {
5610 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5611 r = -EOPNOTSUPP;
5612 goto out;
f8c16bba
ZX		 5613 }
5614
013f6a5d
MT		 5615 r = -ENOMEM;
5616 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5617 if (!shared_msrs) {
5618 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5619 goto out;
5620 }
5621
97db56ce
AK		 5622 r = kvm_mmu_module_init();
5623 if (r)
013f6a5d 5624 goto out_free_percpu;
97db56ce 5625
ce88decf 5626 kvm_set_mmio_spte_mask();
97db56ce 5627
f8c16bba 5628 kvm_x86_ops = ops;
920c8377
PB		 5629 kvm_init_msr_list();
5630
7b52345e 5631 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5632 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5633
b820cc0c 5634 kvm_timer_init();
c8076604 5635
ff9d07a0
ZY		 5636 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5637
2acf923e
DC		 5638 if (cpu_has_xsave)
5639 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5640
c5cc421b 5641 kvm_lapic_init();
16e8d74d
MT		 5642#ifdef CONFIG_X86_64
5643 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5644#endif
5645
f8c16bba 5646 return 0;
56c6d28a 5647
013f6a5d
MT		 5648out_free_percpu:
5649 free_percpu(shared_msrs);
56c6d28a 5650out:
56c6d28a 5651 return r;
043405e1 5652}
8776e519 5653
f8c16bba
ZX		 5654void kvm_arch_exit(void)
5655{
ff9d07a0
ZY		 5656 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5657
888d256e
JK		 5658 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5659 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5660 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5661 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5662#ifdef CONFIG_X86_64
5663 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5664#endif
f8c16bba 5665 kvm_x86_ops = NULL;
56c6d28a 5666 kvm_mmu_module_exit();
013f6a5d 5667 free_percpu(shared_msrs);
56c6d28a 5668}
f8c16bba 5669
8776e519
HB		 5670int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5671{
5672 ++vcpu->stat.halt_exits;
5673 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5674 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5675 return 1;
5676 } else {
5677 vcpu->run->exit_reason = KVM_EXIT_HLT;
5678 return 0;
5679 }
5680}
5681EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5682
55cd8e5a
GN		 5683int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5684{
5685 u64 param, ingpa, outgpa, ret;
5686 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5687 bool fast, longmode;
55cd8e5a
GN		 5688
5689 /*
5690 * hypercall generates UD from non zero cpl and real mode
5691 * per HYPER-V spec
5692 */
3eeb3288 5693 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5694 kvm_queue_exception(vcpu, UD_VECTOR);
5695 return 0;
5696 }
5697
a449c7aa 5698 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5699
5700 if (!longmode) {
ccd46936
GN		 5701 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5702 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5703 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5704 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5705 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5706 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5707 }
5708#ifdef CONFIG_X86_64
5709 else {
5710 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5711 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5712 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5713 }
5714#endif
5715
5716 code = param & 0xffff;
5717 fast = (param >> 16) & 0x1;
5718 rep_cnt = (param >> 32) & 0xfff;
5719 rep_idx = (param >> 48) & 0xfff;
5720
5721 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5722
c25bc163
GN		 5723 switch (code) {
5724 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5725 kvm_vcpu_on_spin(vcpu);
5726 break;
5727 default:
5728 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5729 break;
5730 }
55cd8e5a
GN		 5731
5732 ret = res | (((u64)rep_done & 0xfff) << 32);
5733 if (longmode) {
5734 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5735 } else {
5736 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5737 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5738 }
5739
5740 return 1;
5741}
5742
6aef266c
SV		 5743/*
5744 * kvm_pv_kick_cpu_op: Kick a vcpu.
5745 *
5746 * @apicid - apicid of vcpu to be kicked.
5747 */
5748static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5749{
24d2166b 5750 struct kvm_lapic_irq lapic_irq;
6aef266c 5751
24d2166b
R		 5752 lapic_irq.shorthand = 0;
5753 lapic_irq.dest_mode = 0;
5754 lapic_irq.dest_id = apicid;
6aef266c 5755
24d2166b
R		 5756 lapic_irq.delivery_mode = APIC_DM_REMRD;
5757 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5758}
5759
8776e519
HB		 5760int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5761{
5762 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5763 int op_64_bit, r = 1;
8776e519 5764
55cd8e5a
GN		 5765 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5766 return kvm_hv_hypercall(vcpu);
5767
5fdbf976
MT		 5768 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5769 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5770 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5771 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5772 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5773
229456fc 5774 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5775
a449c7aa
NA		 5776 op_64_bit = is_64_bit_mode(vcpu);
5777 if (!op_64_bit) {
8776e519
HB		 5778 nr &= 0xFFFFFFFF;
5779 a0 &= 0xFFFFFFFF;
5780 a1 &= 0xFFFFFFFF;
5781 a2 &= 0xFFFFFFFF;
5782 a3 &= 0xFFFFFFFF;
5783 }
5784
07708c4a
JK		 5785 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5786 ret = -KVM_EPERM;
5787 goto out;
5788 }
5789
8776e519 5790 switch (nr) {
b93463aa
AK		 5791 case KVM_HC_VAPIC_POLL_IRQ:
5792 ret = 0;
5793 break;
6aef266c
SV		 5794 case KVM_HC_KICK_CPU:
5795 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5796 ret = 0;
5797 break;
8776e519
HB		 5798 default:
5799 ret = -KVM_ENOSYS;
5800 break;
5801 }
07708c4a 5802out:
a449c7aa
NA		 5803 if (!op_64_bit)
5804 ret = (u32)ret;
5fdbf976 5805 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5806 ++vcpu->stat.hypercalls;
2f333bcb 5807 return r;
8776e519
HB		 5808}
5809EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5810
b6785def 5811static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5812{
d6aa1000 5813 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5814 char instruction[3];
5fdbf976 5815 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5816
8776e519 5817 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5818
9d74191a 5819 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5820}
5821
b6c7a5dc
HB		 5822/*
5823 * Check if userspace requested an interrupt window, and that the
5824 * interrupt window is open.
5825 *
5826 * No need to exit to userspace if we already have an interrupt queued.
5827 */
851ba692 5828static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5829{
8061823a 5830 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5831 vcpu->run->request_interrupt_window &&
5df56646 5832 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5833}
5834
851ba692 5835static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5836{
851ba692
AK		 5837 struct kvm_run *kvm_run = vcpu->run;
5838
91586a3b 5839 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5840 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5841 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5842 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5843 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5844 else
b6c7a5dc 5845 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5846 kvm_arch_interrupt_allowed(vcpu) &&
5847 !kvm_cpu_has_interrupt(vcpu) &&
5848 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5849}
5850
95ba8273
GN		 5851static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5852{
5853 int max_irr, tpr;
5854
5855 if (!kvm_x86_ops->update_cr8_intercept)
5856 return;
5857
88c808fd
AK		 5858 if (!vcpu->arch.apic)
5859 return;
5860
8db3baa2
GN		 5861 if (!vcpu->arch.apic->vapic_addr)
5862 max_irr = kvm_lapic_find_highest_irr(vcpu);
5863 else
5864 max_irr = -1;
95ba8273
GN		 5865
5866 if (max_irr != -1)
5867 max_irr >>= 4;
5868
5869 tpr = kvm_lapic_get_cr8(vcpu);
5870
5871 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5872}
5873
b6b8a145 5874static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5875{
b6b8a145
JK		 5876 int r;
5877
95ba8273 5878 /* try to reinject previous events if any */
b59bb7bd 5879 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5880 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5881 vcpu->arch.exception.has_error_code,
5882 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5883 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5884 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5885 vcpu->arch.exception.error_code,
5886 vcpu->arch.exception.reinject);
b6b8a145 5887 return 0;
b59bb7bd
GN		 5888 }
5889
95ba8273
GN		 5890 if (vcpu->arch.nmi_injected) {
5891 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5892 return 0;
95ba8273
GN		 5893 }
5894
5895 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5896 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5897 return 0;
5898 }
5899
5900 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5901 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5902 if (r != 0)
5903 return r;
95ba8273
GN		 5904 }
5905
5906 /* try to inject new event if pending */
5907 if (vcpu->arch.nmi_pending) {
5908 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5909 --vcpu->arch.nmi_pending;
95ba8273
GN		 5910 vcpu->arch.nmi_injected = true;
5911 kvm_x86_ops->set_nmi(vcpu);
5912 }
c7c9c56c 5913 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5914 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5915 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5916 false);
5917 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5918 }
5919 }
b6b8a145 5920 return 0;
95ba8273
GN		 5921}
5922
7460fb4a
AK		 5923static void process_nmi(struct kvm_vcpu *vcpu)
5924{
5925 unsigned limit = 2;
5926
5927 /*
5928 * x86 is limited to one NMI running, and one NMI pending after it.
5929 * If an NMI is already in progress, limit further NMIs to just one.
5930 * Otherwise, allow two (and we'll inject the first one immediately).
5931 */
5932 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5933 limit = 1;
5934
5935 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5936 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5937 kvm_make_request(KVM_REQ_EVENT, vcpu);
5938}
5939
3d81bc7e 5940static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5941{
5942 u64 eoi_exit_bitmap[4];
cf9e65b7 5943 u32 tmr[8];
c7c9c56c 5944
3d81bc7e
YZ		 5945 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5946 return;
c7c9c56c
YZ		 5947
5948 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5949 memset(tmr, 0, 32);
c7c9c56c 5950
cf9e65b7 5951 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5952 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5953 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5954}
5955
9357d939
TY		 5956/*
5957 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5958 * exiting to the userspace. Otherwise, the value will be returned to the
5959 * userspace.
5960 */
851ba692 5961static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5962{
5963 int r;
6a8b1d13 5964 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5965 vcpu->run->request_interrupt_window;
730dca42 5966 bool req_immediate_exit = false;
b6c7a5dc 5967
3e007509 5968 if (vcpu->requests) {
a8eeb04a 5969 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5970 kvm_mmu_unload(vcpu);
a8eeb04a 5971 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5972 __kvm_migrate_timers(vcpu);
d828199e
MT		 5973 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5974 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5975 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5976 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5977 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5978 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5979 if (unlikely(r))
5980 goto out;
5981 }
a8eeb04a 5982 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5983 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5984 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5985 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5986 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5987 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5988 r = 0;
5989 goto out;
5990 }
a8eeb04a 5991 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5992 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5993 r = 0;
5994 goto out;
5995 }
a8eeb04a 5996 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5997 vcpu->fpu_active = 0;
5998 kvm_x86_ops->fpu_deactivate(vcpu);
5999 }
af585b92
GN		 6000 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6001 /* Page is swapped out. Do synthetic halt */
6002 vcpu->arch.apf.halted = true;
6003 r = 1;
6004 goto out;
6005 }
c9aaa895
GC		 6006 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6007 record_steal_time(vcpu);
7460fb4a
AK		 6008 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6009 process_nmi(vcpu);
f5132b01
GN		 6010 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6011 kvm_handle_pmu_event(vcpu);
6012 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6013 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6014 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6015 vcpu_scan_ioapic(vcpu);
2f52d58c 6016 }
b93463aa 6017
b463a6f7 6018 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6019 kvm_apic_accept_events(vcpu);
6020 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6021 r = 1;
6022 goto out;
6023 }
6024
b6b8a145
JK		 6025 if (inject_pending_event(vcpu, req_int_win) != 0)
6026 req_immediate_exit = true;
b463a6f7 6027 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6028 else if (vcpu->arch.nmi_pending)
c9a7953f 6029 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6030 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6031 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6032
6033 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6034 /*
6035 * Update architecture specific hints for APIC
6036 * virtual interrupt delivery.
6037 */
6038 if (kvm_x86_ops->hwapic_irr_update)
6039 kvm_x86_ops->hwapic_irr_update(vcpu,
6040 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6041 update_cr8_intercept(vcpu);
6042 kvm_lapic_sync_to_vapic(vcpu);
6043 }
6044 }
6045
d8368af8
AK		 6046 r = kvm_mmu_reload(vcpu);
6047 if (unlikely(r)) {
d905c069 6048 goto cancel_injection;
d8368af8
AK		 6049 }
6050
b6c7a5dc
HB		 6051 preempt_disable();
6052
6053 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6054 if (vcpu->fpu_active)
6055 kvm_load_guest_fpu(vcpu);
2acf923e 6056 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6057
6b7e2d09
XG		 6058 vcpu->mode = IN_GUEST_MODE;
6059
01b71917
MT		 6060 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6061
6b7e2d09
XG		 6062 /* We should set ->mode before check ->requests,
6063 * see the comment in make_all_cpus_request.
6064 */
01b71917 6065 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6066
d94e1dc9 6067 local_irq_disable();
32f88400 6068
6b7e2d09 6069 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6070 || need_resched() || signal_pending(current)) {
6b7e2d09 6071 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6072 smp_wmb();
6c142801
AK		 6073 local_irq_enable();
6074 preempt_enable();
01b71917 6075 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6076 r = 1;
d905c069 6077 goto cancel_injection;
6c142801
AK		 6078 }
6079
d6185f20
NHE		 6080 if (req_immediate_exit)
6081 smp_send_reschedule(vcpu->cpu);
6082
b6c7a5dc
HB		 6083 kvm_guest_enter();
6084
42dbaa5a 6085 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6086 set_debugreg(0, 7);
6087 set_debugreg(vcpu->arch.eff_db[0], 0);
6088 set_debugreg(vcpu->arch.eff_db[1], 1);
6089 set_debugreg(vcpu->arch.eff_db[2], 2);
6090 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6091 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6092 }
b6c7a5dc 6093
229456fc 6094 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6095 kvm_x86_ops->run(vcpu);
b6c7a5dc 6096
c77fb5fe
PB		 6097 /*
6098 * Do this here before restoring debug registers on the host. And
6099 * since we do this before handling the vmexit, a DR access vmexit
6100 * can (a) read the correct value of the debug registers, (b) set
6101 * KVM_DEBUGREG_WONT_EXIT again.
6102 */
6103 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6104 int i;
6105
6106 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6107 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6108 for (i = 0; i < KVM_NR_DB_REGS; i++)
6109 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6110 }
6111
24f1e32c
FW		 6112 /*
6113 * If the guest has used debug registers, at least dr7
6114 * will be disabled while returning to the host.
6115 * If we don't have active breakpoints in the host, we don't
6116 * care about the messed up debug address registers. But if
6117 * we have some of them active, restore the old state.
6118 */
59d8eb53 6119 if (hw_breakpoint_active())
24f1e32c 6120 hw_breakpoint_restore();
42dbaa5a 6121
886b470c
MT		 6122 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6123 native_read_tsc());
1d5f066e 6124
6b7e2d09 6125 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6126 smp_wmb();
a547c6db
YZ		 6127
6128 /* Interrupt is enabled by handle_external_intr() */
6129 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6130
6131 ++vcpu->stat.exits;
6132
6133 /*
6134 * We must have an instruction between local_irq_enable() and
6135 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6136 * the interrupt shadow. The stat.exits increment will do nicely.
6137 * But we need to prevent reordering, hence this barrier():
6138 */
6139 barrier();
6140
6141 kvm_guest_exit();
6142
6143 preempt_enable();
6144
f656ce01 6145 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6146
b6c7a5dc
HB		 6147 /*
6148 * Profile KVM exit RIPs:
6149 */
6150 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6151 unsigned long rip = kvm_rip_read(vcpu);
6152 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6153 }
6154
cc578287
ZA		 6155 if (unlikely(vcpu->arch.tsc_always_catchup))
6156 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6157
5cfb1d5a
MT		 6158 if (vcpu->arch.apic_attention)
6159 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6160
851ba692 6161 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6162 return r;
6163
6164cancel_injection:
6165 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6166 if (unlikely(vcpu->arch.apic_attention))
6167 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6168out:
6169 return r;
6170}
b6c7a5dc 6171
09cec754 6172
851ba692 6173static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6174{
6175 int r;
f656ce01 6176 struct kvm *kvm = vcpu->kvm;
d7690175 6177
f656ce01 6178 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6179
6180 r = 1;
6181 while (r > 0) {
af585b92
GN		 6182 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6183 !vcpu->arch.apf.halted)
851ba692 6184 r = vcpu_enter_guest(vcpu);
d7690175 6185 else {
f656ce01 6186 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6187 kvm_vcpu_block(vcpu);
f656ce01 6188 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6189 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6190 kvm_apic_accept_events(vcpu);
09cec754
GN		 6191 switch(vcpu->arch.mp_state) {
6192 case KVM_MP_STATE_HALTED:
6aef266c 6193 vcpu->arch.pv.pv_unhalted = false;
d7690175 6194 vcpu->arch.mp_state =
09cec754
GN		 6195 KVM_MP_STATE_RUNNABLE;
6196 case KVM_MP_STATE_RUNNABLE:
af585b92 6197 vcpu->arch.apf.halted = false;
09cec754 6198 break;
66450a21
JK		 6199 case KVM_MP_STATE_INIT_RECEIVED:
6200 break;
09cec754
GN		 6201 default:
6202 r = -EINTR;
6203 break;
6204 }
6205 }
d7690175
MT		 6206 }
6207
09cec754
GN		 6208 if (r <= 0)
6209 break;
6210
6211 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6212 if (kvm_cpu_has_pending_timer(vcpu))
6213 kvm_inject_pending_timer_irqs(vcpu);
6214
851ba692 6215 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6216 r = -EINTR;
851ba692 6217 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6218 ++vcpu->stat.request_irq_exits;
6219 }
af585b92
GN		 6220
6221 kvm_check_async_pf_completion(vcpu);
6222
09cec754
GN		 6223 if (signal_pending(current)) {
6224 r = -EINTR;
851ba692 6225 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6226 ++vcpu->stat.signal_exits;
6227 }
6228 if (need_resched()) {
f656ce01 6229 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6230 cond_resched();
f656ce01 6231 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6232 }
b6c7a5dc
HB		 6233 }
6234
f656ce01 6235 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6236
6237 return r;
6238}
6239
716d51ab
GN		 6240static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6241{
6242 int r;
6243 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6244 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6245 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6246 if (r != EMULATE_DONE)
6247 return 0;
6248 return 1;
6249}
6250
6251static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6252{
6253 BUG_ON(!vcpu->arch.pio.count);
6254
6255 return complete_emulated_io(vcpu);
6256}
6257
f78146b0
AK		 6258/*
6259 * Implements the following, as a state machine:
6260 *
6261 * read:
6262 * for each fragment
87da7e66
XG		 6263 * for each mmio piece in the fragment
6264 * write gpa, len
6265 * exit
6266 * copy data
f78146b0
AK		 6267 * execute insn
6268 *
6269 * write:
6270 * for each fragment
87da7e66
XG		 6271 * for each mmio piece in the fragment
6272 * write gpa, len
6273 * copy data
6274 * exit
f78146b0 6275 */
716d51ab 6276static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6277{
6278 struct kvm_run *run = vcpu->run;
f78146b0 6279 struct kvm_mmio_fragment *frag;
87da7e66 6280 unsigned len;
5287f194 6281
716d51ab 6282 BUG_ON(!vcpu->mmio_needed);
5287f194 6283
716d51ab 6284 /* Complete previous fragment */
87da7e66
XG		 6285 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6286 len = min(8u, frag->len);
716d51ab 6287 if (!vcpu->mmio_is_write)
87da7e66
XG		 6288 memcpy(frag->data, run->mmio.data, len);
6289
6290 if (frag->len <= 8) {
6291 /* Switch to the next fragment. */
6292 frag++;
6293 vcpu->mmio_cur_fragment++;
6294 } else {
6295 /* Go forward to the next mmio piece. */
6296 frag->data += len;
6297 frag->gpa += len;
6298 frag->len -= len;
6299 }
6300
a08d3b3b 6301 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6302 vcpu->mmio_needed = 0;
0912c977
PB		 6303
6304 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6305 if (vcpu->mmio_is_write)
716d51ab
GN		 6306 return 1;
6307 vcpu->mmio_read_completed = 1;
6308 return complete_emulated_io(vcpu);
6309 }
87da7e66 6310
716d51ab
GN		 6311 run->exit_reason = KVM_EXIT_MMIO;
6312 run->mmio.phys_addr = frag->gpa;
6313 if (vcpu->mmio_is_write)
87da7e66
XG		 6314 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6315 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6316 run->mmio.is_write = vcpu->mmio_is_write;
6317 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6318 return 0;
5287f194
AK		 6319}
6320
716d51ab 6321
b6c7a5dc
HB		 6322int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6323{
6324 int r;
6325 sigset_t sigsaved;
6326
e5c30142
AK		 6327 if (!tsk_used_math(current) && init_fpu(current))
6328 return -ENOMEM;
6329
ac9f6dc0
AK		 6330 if (vcpu->sigset_active)
6331 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6332
a4535290 6333 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6334 kvm_vcpu_block(vcpu);
66450a21 6335 kvm_apic_accept_events(vcpu);
d7690175 6336 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6337 r = -EAGAIN;
6338 goto out;
b6c7a5dc
HB		 6339 }
6340
b6c7a5dc 6341 /* re-sync apic's tpr */
eea1cff9
AP		 6342 if (!irqchip_in_kernel(vcpu->kvm)) {
6343 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6344 r = -EINVAL;
6345 goto out;
6346 }
6347 }
b6c7a5dc 6348
716d51ab
GN		 6349 if (unlikely(vcpu->arch.complete_userspace_io)) {
6350 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6351 vcpu->arch.complete_userspace_io = NULL;
6352 r = cui(vcpu);
6353 if (r <= 0)
6354 goto out;
6355 } else
6356 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6357
851ba692 6358 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6359
6360out:
f1d86e46 6361 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6362 if (vcpu->sigset_active)
6363 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6364
b6c7a5dc
HB		 6365 return r;
6366}
6367
6368int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6369{
7ae441ea
GN		 6370 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6371 /*
6372 * We are here if userspace calls get_regs() in the middle of
6373 * instruction emulation. Registers state needs to be copied
4a969980 6374 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6375 * that usually, but some bad designed PV devices (vmware
6376 * backdoor interface) need this to work
6377 */
dd856efa 6378 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6379 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6380 }
5fdbf976
MT		 6381 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6382 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6383 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6384 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6385 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6386 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6387 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6388 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6389#ifdef CONFIG_X86_64
5fdbf976
MT		 6390 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6391 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6392 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6393 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6394 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6395 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6396 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6397 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6398#endif
6399
5fdbf976 6400 regs->rip = kvm_rip_read(vcpu);
91586a3b 6401 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6402
b6c7a5dc
HB		 6403 return 0;
6404}
6405
6406int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6407{
7ae441ea
GN		 6408 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6409 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6410
5fdbf976
MT		 6411 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6412 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6413 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6414 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6415 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6416 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6417 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6418 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6419#ifdef CONFIG_X86_64
5fdbf976
MT		 6420 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6421 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6422 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6423 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6424 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6425 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6426 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6427 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6428#endif
6429
5fdbf976 6430 kvm_rip_write(vcpu, regs->rip);
91586a3b 6431 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6432
b4f14abd
JK		 6433 vcpu->arch.exception.pending = false;
6434
3842d135
AK		 6435 kvm_make_request(KVM_REQ_EVENT, vcpu);
6436
b6c7a5dc
HB		 6437 return 0;
6438}
6439
b6c7a5dc
HB		 6440void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6441{
6442 struct kvm_segment cs;
6443
3e6e0aab 6444 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6445 *db = cs.db;
6446 *l = cs.l;
6447}
6448EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6449
6450int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6451 struct kvm_sregs *sregs)
6452{
89a27f4d 6453 struct desc_ptr dt;
b6c7a5dc 6454
3e6e0aab
GT		 6455 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6456 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6457 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6458 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6459 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6460 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6461
3e6e0aab
GT		 6462 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6463 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6464
6465 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6466 sregs->idt.limit = dt.size;
6467 sregs->idt.base = dt.address;
b6c7a5dc 6468 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6469 sregs->gdt.limit = dt.size;
6470 sregs->gdt.base = dt.address;
b6c7a5dc 6471
4d4ec087 6472 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6473 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6474 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6475 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6476 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6477 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6478 sregs->apic_base = kvm_get_apic_base(vcpu);
6479
923c61bb 6480 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6481
36752c9b 6482 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6483 set_bit(vcpu->arch.interrupt.nr,
6484 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6485
b6c7a5dc
HB		 6486 return 0;
6487}
6488
62d9f0db
MT		 6489int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6490 struct kvm_mp_state *mp_state)
6491{
66450a21 6492 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6493 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6494 vcpu->arch.pv.pv_unhalted)
6495 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6496 else
6497 mp_state->mp_state = vcpu->arch.mp_state;
6498
62d9f0db
MT		 6499 return 0;
6500}
6501
6502int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6503 struct kvm_mp_state *mp_state)
6504{
66450a21
JK		 6505 if (!kvm_vcpu_has_lapic(vcpu) &&
6506 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6507 return -EINVAL;
6508
6509 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6510 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6511 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6512 } else
6513 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6514 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6515 return 0;
6516}
6517
7f3d35fd
KW		 6518int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6519 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6520{
9d74191a 6521 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6522 int ret;
e01c2426 6523
8ec4722d 6524 init_emulate_ctxt(vcpu);
c697518a 6525
7f3d35fd 6526 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6527 has_error_code, error_code);
c697518a 6528
c697518a 6529 if (ret)
19d04437 6530 return EMULATE_FAIL;
37817f29 6531
9d74191a
TY		 6532 kvm_rip_write(vcpu, ctxt->eip);
6533 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6534 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6535 return EMULATE_DONE;
37817f29
IE		 6536}
6537EXPORT_SYMBOL_GPL(kvm_task_switch);
6538
b6c7a5dc
HB		 6539int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6540 struct kvm_sregs *sregs)
6541{
58cb628d 6542 struct msr_data apic_base_msr;
b6c7a5dc 6543 int mmu_reset_needed = 0;
63f42e02 6544 int pending_vec, max_bits, idx;
89a27f4d 6545 struct desc_ptr dt;
b6c7a5dc 6546
6d1068b3
PM		 6547 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6548 return -EINVAL;
6549
89a27f4d
GN		 6550 dt.size = sregs->idt.limit;
6551 dt.address = sregs->idt.base;
b6c7a5dc 6552 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6553 dt.size = sregs->gdt.limit;
6554 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6555 kvm_x86_ops->set_gdt(vcpu, &dt);
6556
ad312c7c 6557 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6558 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6559 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6560 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6561
2d3ad1f4 6562 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6563
f6801dff 6564 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6565 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6566 apic_base_msr.data = sregs->apic_base;
6567 apic_base_msr.host_initiated = true;
6568 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6569
4d4ec087 6570 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6571 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6572 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6573
fc78f519 6574 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6575 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6576 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6577 kvm_update_cpuid(vcpu);
63f42e02
XG		 6578
6579 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6580 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6581 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6582 mmu_reset_needed = 1;
6583 }
63f42e02 6584 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6585
6586 if (mmu_reset_needed)
6587 kvm_mmu_reset_context(vcpu);
6588
a50abc3b 6589 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6590 pending_vec = find_first_bit(
6591 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6592 if (pending_vec < max_bits) {
66fd3f7f 6593 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6594 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6595 }
6596
3e6e0aab
GT		 6597 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6598 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6599 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6600 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6601 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6602 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6603
3e6e0aab
GT		 6604 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6605 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6606
5f0269f5
ME		 6607 update_cr8_intercept(vcpu);
6608
9c3e4aab 6609 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6610 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6611 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6612 !is_protmode(vcpu))
9c3e4aab
MT		 6613 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6614
3842d135
AK		 6615 kvm_make_request(KVM_REQ_EVENT, vcpu);
6616
b6c7a5dc
HB		 6617 return 0;
6618}
6619
d0bfb940
JK		 6620int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6621 struct kvm_guest_debug *dbg)
b6c7a5dc 6622{
355be0b9 6623 unsigned long rflags;
ae675ef0 6624 int i, r;
b6c7a5dc 6625
4f926bf2
JK		 6626 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6627 r = -EBUSY;
6628 if (vcpu->arch.exception.pending)
2122ff5e 6629 goto out;
4f926bf2
JK		 6630 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6631 kvm_queue_exception(vcpu, DB_VECTOR);
6632 else
6633 kvm_queue_exception(vcpu, BP_VECTOR);
6634 }
6635
91586a3b
JK		 6636 /*
6637 * Read rflags as long as potentially injected trace flags are still
6638 * filtered out.
6639 */
6640 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6641
6642 vcpu->guest_debug = dbg->control;
6643 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6644 vcpu->guest_debug = 0;
6645
6646 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6647 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6648 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6649 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6650 } else {
6651 for (i = 0; i < KVM_NR_DB_REGS; i++)
6652 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6653 }
c8639010 6654 kvm_update_dr7(vcpu);
ae675ef0 6655
f92653ee
JK		 6656 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6657 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6658 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6659
91586a3b
JK		 6660 /*
6661 * Trigger an rflags update that will inject or remove the trace
6662 * flags.
6663 */
6664 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6665
c8639010 6666 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6667
4f926bf2 6668 r = 0;
d0bfb940 6669
2122ff5e 6670out:
b6c7a5dc
HB		 6671
6672 return r;
6673}
6674
8b006791
ZX		 6675/*
6676 * Translate a guest virtual address to a guest physical address.
6677 */
6678int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6679 struct kvm_translation *tr)
6680{
6681 unsigned long vaddr = tr->linear_address;
6682 gpa_t gpa;
f656ce01 6683 int idx;
8b006791 6684
f656ce01 6685 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6686 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6687 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6688 tr->physical_address = gpa;
6689 tr->valid = gpa != UNMAPPED_GVA;
6690 tr->writeable = 1;
6691 tr->usermode = 0;
8b006791
ZX		 6692
6693 return 0;
6694}
6695
d0752060
HB		 6696int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6697{
98918833
SY		 6698 struct i387_fxsave_struct *fxsave =
6699 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6700
d0752060
HB		 6701 memcpy(fpu->fpr, fxsave->st_space, 128);
6702 fpu->fcw = fxsave->cwd;
6703 fpu->fsw = fxsave->swd;
6704 fpu->ftwx = fxsave->twd;
6705 fpu->last_opcode = fxsave->fop;
6706 fpu->last_ip = fxsave->rip;
6707 fpu->last_dp = fxsave->rdp;
6708 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6709
d0752060
HB		 6710 return 0;
6711}
6712
6713int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6714{
98918833
SY		 6715 struct i387_fxsave_struct *fxsave =
6716 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6717
d0752060
HB		 6718 memcpy(fxsave->st_space, fpu->fpr, 128);
6719 fxsave->cwd = fpu->fcw;
6720 fxsave->swd = fpu->fsw;
6721 fxsave->twd = fpu->ftwx;
6722 fxsave->fop = fpu->last_opcode;
6723 fxsave->rip = fpu->last_ip;
6724 fxsave->rdp = fpu->last_dp;
6725 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6726
d0752060
HB		 6727 return 0;
6728}
6729
10ab25cd 6730int fx_init(struct kvm_vcpu *vcpu)
d0752060 6731{
10ab25cd
JK		 6732 int err;
6733
6734 err = fpu_alloc(&vcpu->arch.guest_fpu);
6735 if (err)
6736 return err;
6737
98918833 6738 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6739
2acf923e
DC		 6740 /*
6741 * Ensure guest xcr0 is valid for loading
6742 */
6743 vcpu->arch.xcr0 = XSTATE_FP;
6744
ad312c7c 6745 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6746
6747 return 0;
d0752060
HB		 6748}
6749EXPORT_SYMBOL_GPL(fx_init);
6750
98918833
SY		 6751static void fx_free(struct kvm_vcpu *vcpu)
6752{
6753 fpu_free(&vcpu->arch.guest_fpu);
6754}
6755
d0752060
HB		 6756void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6757{
2608d7a1 6758 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6759 return;
6760
2acf923e
DC		 6761 /*
6762 * Restore all possible states in the guest,
6763 * and assume host would use all available bits.
6764 * Guest xcr0 would be loaded later.
6765 */
6766 kvm_put_guest_xcr0(vcpu);
d0752060 6767 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6768 __kernel_fpu_begin();
98918833 6769 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6770 trace_kvm_fpu(1);
d0752060 6771}
d0752060
HB		 6772
6773void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6774{
2acf923e
DC		 6775 kvm_put_guest_xcr0(vcpu);
6776
d0752060
HB		 6777 if (!vcpu->guest_fpu_loaded)
6778 return;
6779
6780 vcpu->guest_fpu_loaded = 0;
98918833 6781 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6782 __kernel_fpu_end();
f096ed85 6783 ++vcpu->stat.fpu_reload;
a8eeb04a 6784 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6785 trace_kvm_fpu(0);
d0752060 6786}
e9b11c17
ZX		 6787
6788void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6789{
12f9a48f 6790 kvmclock_reset(vcpu);
7f1ea208 6791
f5f48ee1 6792 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6793 fx_free(vcpu);
e9b11c17
ZX		 6794 kvm_x86_ops->vcpu_free(vcpu);
6795}
6796
6797struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6798 unsigned int id)
6799{
6755bae8
ZA		 6800 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6801 printk_once(KERN_WARNING
6802 "kvm: SMP vm created on host with unstable TSC; "
6803 "guest TSC will not be reliable\n");
26e5215f
AK		 6804 return kvm_x86_ops->vcpu_create(kvm, id);
6805}
e9b11c17 6806
26e5215f
AK		 6807int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6808{
6809 int r;
e9b11c17 6810
0bed3b56 6811 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6812 r = vcpu_load(vcpu);
6813 if (r)
6814 return r;
57f252f2 6815 kvm_vcpu_reset(vcpu);
8a3c1a33 6816 kvm_mmu_setup(vcpu);
e9b11c17 6817 vcpu_put(vcpu);
e9b11c17 6818
26e5215f 6819 return r;
e9b11c17
ZX		 6820}
6821
42897d86
MT		 6822int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6823{
6824 int r;
8fe8ab46 6825 struct msr_data msr;
332967a3 6826 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6827
6828 r = vcpu_load(vcpu);
6829 if (r)
6830 return r;
8fe8ab46
WA		 6831 msr.data = 0x0;
6832 msr.index = MSR_IA32_TSC;
6833 msr.host_initiated = true;
6834 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6835 vcpu_put(vcpu);
6836
332967a3
AJ		 6837 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6838 KVMCLOCK_SYNC_PERIOD);
6839
42897d86
MT		 6840 return r;
6841}
6842
d40ccc62 6843void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6844{
9fc77441 6845 int r;
344d9588
GN		 6846 vcpu->arch.apf.msr_val = 0;
6847
9fc77441
MT		 6848 r = vcpu_load(vcpu);
6849 BUG_ON(r);
e9b11c17
ZX		 6850 kvm_mmu_unload(vcpu);
6851 vcpu_put(vcpu);
6852
98918833 6853 fx_free(vcpu);
e9b11c17
ZX		 6854 kvm_x86_ops->vcpu_free(vcpu);
6855}
6856
66450a21 6857void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6858{
7460fb4a
AK		 6859 atomic_set(&vcpu->arch.nmi_queued, 0);
6860 vcpu->arch.nmi_pending = 0;
448fa4a9 6861 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6862 kvm_clear_interrupt_queue(vcpu);
6863 kvm_clear_exception_queue(vcpu);
448fa4a9 6864
42dbaa5a
JK		 6865 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6866 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6867 kvm_update_dr6(vcpu);
42dbaa5a 6868 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6869 kvm_update_dr7(vcpu);
42dbaa5a 6870
3842d135 6871 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6872 vcpu->arch.apf.msr_val = 0;
c9aaa895 6873 vcpu->arch.st.msr_val = 0;
3842d135 6874
12f9a48f
GC		 6875 kvmclock_reset(vcpu);
6876
af585b92
GN		 6877 kvm_clear_async_pf_completion_queue(vcpu);
6878 kvm_async_pf_hash_reset(vcpu);
6879 vcpu->arch.apf.halted = false;
3842d135 6880
f5132b01
GN		 6881 kvm_pmu_reset(vcpu);
6882
66f7b72e
JS		 6883 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6884 vcpu->arch.regs_avail = ~0;
6885 vcpu->arch.regs_dirty = ~0;
6886
57f252f2 6887 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6888}
6889
66450a21
JK		 6890void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6891{
6892 struct kvm_segment cs;
6893
6894 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6895 cs.selector = vector << 8;
6896 cs.base = vector << 12;
6897 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6898 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6899}
6900
10474ae8 6901int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6902{
ca84d1a2
ZA		 6903 struct kvm *kvm;
6904 struct kvm_vcpu *vcpu;
6905 int i;
0dd6a6ed
ZA		 6906 int ret;
6907 u64 local_tsc;
6908 u64 max_tsc = 0;
6909 bool stable, backwards_tsc = false;
18863bdd
AK		 6910
6911 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6912 ret = kvm_x86_ops->hardware_enable(garbage);
6913 if (ret != 0)
6914 return ret;
6915
6916 local_tsc = native_read_tsc();
6917 stable = !check_tsc_unstable();
6918 list_for_each_entry(kvm, &vm_list, vm_list) {
6919 kvm_for_each_vcpu(i, vcpu, kvm) {
6920 if (!stable && vcpu->cpu == smp_processor_id())
6921 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6922 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6923 backwards_tsc = true;
6924 if (vcpu->arch.last_host_tsc > max_tsc)
6925 max_tsc = vcpu->arch.last_host_tsc;
6926 }
6927 }
6928 }
6929
6930 /*
6931 * Sometimes, even reliable TSCs go backwards. This happens on
6932 * platforms that reset TSC during suspend or hibernate actions, but
6933 * maintain synchronization. We must compensate. Fortunately, we can
6934 * detect that condition here, which happens early in CPU bringup,
6935 * before any KVM threads can be running. Unfortunately, we can't
6936 * bring the TSCs fully up to date with real time, as we aren't yet far
6937 * enough into CPU bringup that we know how much real time has actually
6938 * elapsed; our helper function, get_kernel_ns() will be using boot
6939 * variables that haven't been updated yet.
6940 *
6941 * So we simply find the maximum observed TSC above, then record the
6942 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6943 * the adjustment will be applied. Note that we accumulate
6944 * adjustments, in case multiple suspend cycles happen before some VCPU
6945 * gets a chance to run again. In the event that no KVM threads get a
6946 * chance to run, we will miss the entire elapsed period, as we'll have
6947 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6948 * loose cycle time. This isn't too big a deal, since the loss will be
6949 * uniform across all VCPUs (not to mention the scenario is extremely
6950 * unlikely). It is possible that a second hibernate recovery happens
6951 * much faster than a first, causing the observed TSC here to be
6952 * smaller; this would require additional padding adjustment, which is
6953 * why we set last_host_tsc to the local tsc observed here.
6954 *
6955 * N.B. - this code below runs only on platforms with reliable TSC,
6956 * as that is the only way backwards_tsc is set above. Also note
6957 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6958 * have the same delta_cyc adjustment applied if backwards_tsc
6959 * is detected. Note further, this adjustment is only done once,
6960 * as we reset last_host_tsc on all VCPUs to stop this from being
6961 * called multiple times (one for each physical CPU bringup).
6962 *
4a969980 6963 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6964 * will be compensated by the logic in vcpu_load, which sets the TSC to
6965 * catchup mode. This will catchup all VCPUs to real time, but cannot
6966 * guarantee that they stay in perfect synchronization.
6967 */
6968 if (backwards_tsc) {
6969 u64 delta_cyc = max_tsc - local_tsc;
16a96021 6970 backwards_tsc_observed = true;
0dd6a6ed
ZA		 6971 list_for_each_entry(kvm, &vm_list, vm_list) {
6972 kvm_for_each_vcpu(i, vcpu, kvm) {
6973 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6974 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6975 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6976 &vcpu->requests);
0dd6a6ed
ZA		 6977 }
6978
6979 /*
6980 * We have to disable TSC offset matching.. if you were
6981 * booting a VM while issuing an S4 host suspend....
6982 * you may have some problem. Solving this issue is
6983 * left as an exercise to the reader.
6984 */
6985 kvm->arch.last_tsc_nsec = 0;
6986 kvm->arch.last_tsc_write = 0;
6987 }
6988
6989 }
6990 return 0;
e9b11c17
ZX		 6991}
6992
6993void kvm_arch_hardware_disable(void *garbage)
6994{
6995 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6996 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6997}
6998
6999int kvm_arch_hardware_setup(void)
7000{
7001 return kvm_x86_ops->hardware_setup();
7002}
7003
7004void kvm_arch_hardware_unsetup(void)
7005{
7006 kvm_x86_ops->hardware_unsetup();
7007}
7008
7009void kvm_arch_check_processor_compat(void *rtn)
7010{
7011 kvm_x86_ops->check_processor_compatibility(rtn);
7012}
7013
3e515705
AK		 7014bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7015{
7016 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7017}
7018
54e9818f
GN		 7019struct static_key kvm_no_apic_vcpu __read_mostly;
7020
e9b11c17
ZX		 7021int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7022{
7023 struct page *page;
7024 struct kvm *kvm;
7025 int r;
7026
7027 BUG_ON(vcpu->kvm == NULL);
7028 kvm = vcpu->kvm;
7029
6aef266c 7030 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7031 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7032 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7033 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7034 else
a4535290 7035 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7036
7037 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7038 if (!page) {
7039 r = -ENOMEM;
7040 goto fail;
7041 }
ad312c7c 7042 vcpu->arch.pio_data = page_address(page);
e9b11c17 7043
cc578287 7044 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7045
e9b11c17
ZX		 7046 r = kvm_mmu_create(vcpu);
7047 if (r < 0)
7048 goto fail_free_pio_data;
7049
7050 if (irqchip_in_kernel(kvm)) {
7051 r = kvm_create_lapic(vcpu);
7052 if (r < 0)
7053 goto fail_mmu_destroy;
54e9818f
GN		 7054 } else
7055 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7056
890ca9ae
HY		 7057 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7058 GFP_KERNEL);
7059 if (!vcpu->arch.mce_banks) {
7060 r = -ENOMEM;
443c39bc 7061 goto fail_free_lapic;
890ca9ae
HY		 7062 }
7063 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7064
f1797359
WY		 7065 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7066 r = -ENOMEM;
f5f48ee1 7067 goto fail_free_mce_banks;
f1797359 7068 }
f5f48ee1 7069
66f7b72e
JS		 7070 r = fx_init(vcpu);
7071 if (r)
7072 goto fail_free_wbinvd_dirty_mask;
7073
ba904635 7074 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7075 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7076
7077 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7078 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7079
af585b92 7080 kvm_async_pf_hash_reset(vcpu);
f5132b01 7081 kvm_pmu_init(vcpu);
af585b92 7082
e9b11c17 7083 return 0;
66f7b72e
JS		 7084fail_free_wbinvd_dirty_mask:
7085 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7086fail_free_mce_banks:
7087 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7088fail_free_lapic:
7089 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7090fail_mmu_destroy:
7091 kvm_mmu_destroy(vcpu);
7092fail_free_pio_data:
ad312c7c 7093 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7094fail:
7095 return r;
7096}
7097
7098void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7099{
f656ce01
MT		 7100 int idx;
7101
f5132b01 7102 kvm_pmu_destroy(vcpu);
36cb93fd 7103 kfree(vcpu->arch.mce_banks);
e9b11c17 7104 kvm_free_lapic(vcpu);
f656ce01 7105 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7106 kvm_mmu_destroy(vcpu);
f656ce01 7107 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7108 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7109 if (!irqchip_in_kernel(vcpu->kvm))
7110 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7111}
d19a9cd2 7112
e08b9637 7113int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7114{
e08b9637
CO		 7115 if (type)
7116 return -EINVAL;
7117
f05e70ac 7118 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7119 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7120 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7121 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7122
5550af4d
SY		 7123 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7124 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7125 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7126 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7127 &kvm->arch.irq_sources_bitmap);
5550af4d 7128
038f8c11 7129 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7130 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7131 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7132
7133 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7134
7e44e449 7135 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7136 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7137
d89f5eff 7138 return 0;
d19a9cd2
ZX		 7139}
7140
7141static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7142{
9fc77441
MT		 7143 int r;
7144 r = vcpu_load(vcpu);
7145 BUG_ON(r);
d19a9cd2
ZX		 7146 kvm_mmu_unload(vcpu);
7147 vcpu_put(vcpu);
7148}
7149
7150static void kvm_free_vcpus(struct kvm *kvm)
7151{
7152 unsigned int i;
988a2cae 7153 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7154
7155 /*
7156 * Unpin any mmu pages first.
7157 */
af585b92
GN		 7158 kvm_for_each_vcpu(i, vcpu, kvm) {
7159 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7160 kvm_unload_vcpu_mmu(vcpu);
af585b92 7161 }
988a2cae
GN		 7162 kvm_for_each_vcpu(i, vcpu, kvm)
7163 kvm_arch_vcpu_free(vcpu);
7164
7165 mutex_lock(&kvm->lock);
7166 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7167 kvm->vcpus[i] = NULL;
d19a9cd2 7168
988a2cae
GN		 7169 atomic_set(&kvm->online_vcpus, 0);
7170 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7171}
7172
ad8ba2cd
SY		 7173void kvm_arch_sync_events(struct kvm *kvm)
7174{
332967a3 7175 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7176 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7177 kvm_free_all_assigned_devices(kvm);
aea924f6 7178 kvm_free_pit(kvm);
ad8ba2cd
SY		 7179}
7180
d19a9cd2
ZX		 7181void kvm_arch_destroy_vm(struct kvm *kvm)
7182{
27469d29
AH		 7183 if (current->mm == kvm->mm) {
7184 /*
7185 * Free memory regions allocated on behalf of userspace,
7186 * unless the the memory map has changed due to process exit
7187 * or fd copying.
7188 */
7189 struct kvm_userspace_memory_region mem;
7190 memset(&mem, 0, sizeof(mem));
7191 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7192 kvm_set_memory_region(kvm, &mem);
7193
7194 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7195 kvm_set_memory_region(kvm, &mem);
7196
7197 mem.slot = TSS_PRIVATE_MEMSLOT;
7198 kvm_set_memory_region(kvm, &mem);
7199 }
6eb55818 7200 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7201 kfree(kvm->arch.vpic);
7202 kfree(kvm->arch.vioapic);
d19a9cd2 7203 kvm_free_vcpus(kvm);
3d45830c
AK		 7204 if (kvm->arch.apic_access_page)
7205 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7206 if (kvm->arch.ept_identity_pagetable)
7207 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7208 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7209}
0de10343 7210
5587027c 7211void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7212 struct kvm_memory_slot *dont)
7213{
7214 int i;
7215
d89cc617
TY		 7216 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7217 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7218 kvm_kvfree(free->arch.rmap[i]);
7219 free->arch.rmap[i] = NULL;
77d11309 7220 }
d89cc617
TY		 7221 if (i == 0)
7222 continue;
7223
7224 if (!dont || free->arch.lpage_info[i - 1] !=
7225 dont->arch.lpage_info[i - 1]) {
7226 kvm_kvfree(free->arch.lpage_info[i - 1]);
7227 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7228 }
7229 }
7230}
7231
5587027c
AK		 7232int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7233 unsigned long npages)
db3fe4eb
TY		 7234{
7235 int i;
7236
d89cc617 7237 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7238 unsigned long ugfn;
7239 int lpages;
d89cc617 7240 int level = i + 1;
db3fe4eb
TY		 7241
7242 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7243 slot->base_gfn, level) + 1;
7244
d89cc617
TY		 7245 slot->arch.rmap[i] =
7246 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7247 if (!slot->arch.rmap[i])
77d11309 7248 goto out_free;
d89cc617
TY		 7249 if (i == 0)
7250 continue;
77d11309 7251
d89cc617
TY		 7252 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7253 sizeof(*slot->arch.lpage_info[i - 1]));
7254 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7255 goto out_free;
7256
7257 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7258 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7259 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7260 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7261 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7262 /*
7263 * If the gfn and userspace address are not aligned wrt each
7264 * other, or if explicitly asked to, disable large page
7265 * support for this slot
7266 */
7267 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7268 !kvm_largepages_enabled()) {
7269 unsigned long j;
7270
7271 for (j = 0; j < lpages; ++j)
d89cc617 7272 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7273 }
7274 }
7275
7276 return 0;
7277
7278out_free:
d89cc617
TY		 7279 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7280 kvm_kvfree(slot->arch.rmap[i]);
7281 slot->arch.rmap[i] = NULL;
7282 if (i == 0)
7283 continue;
7284
7285 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7286 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7287 }
7288 return -ENOMEM;
7289}
7290
e59dbe09
TY		 7291void kvm_arch_memslots_updated(struct kvm *kvm)
7292{
e6dff7d1
TY		 7293 /*
7294 * memslots->generation has been incremented.
7295 * mmio generation may have reached its maximum value.
7296 */
7297 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7298}
7299
f7784b8e
MT		 7300int kvm_arch_prepare_memory_region(struct kvm *kvm,
7301 struct kvm_memory_slot *memslot,
f7784b8e 7302 struct kvm_userspace_memory_region *mem,
7b6195a9 7303 enum kvm_mr_change change)
0de10343 7304{
7a905b14
TY		 7305 /*
7306 * Only private memory slots need to be mapped here since
7307 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7308 */
7b6195a9 7309 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7310 unsigned long userspace_addr;
604b38ac 7311
7a905b14
TY		 7312 /*
7313 * MAP_SHARED to prevent internal slot pages from being moved
7314 * by fork()/COW.
7315 */
7b6195a9 7316 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7317 PROT_READ | PROT_WRITE,
7318 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7319
7a905b14
TY		 7320 if (IS_ERR((void *)userspace_addr))
7321 return PTR_ERR((void *)userspace_addr);
604b38ac 7322
7a905b14 7323 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7324 }
7325
f7784b8e
MT		 7326 return 0;
7327}
7328
7329void kvm_arch_commit_memory_region(struct kvm *kvm,
7330 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7331 const struct kvm_memory_slot *old,
7332 enum kvm_mr_change change)
f7784b8e
MT		 7333{
7334
8482644a 7335 int nr_mmu_pages = 0;
f7784b8e 7336
8482644a 7337 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7338 int ret;
7339
8482644a
TY		 7340 ret = vm_munmap(old->userspace_addr,
7341 old->npages * PAGE_SIZE);
f7784b8e
MT		 7342 if (ret < 0)
7343 printk(KERN_WARNING
7344 "kvm_vm_ioctl_set_memory_region: "
7345 "failed to munmap memory\n");
7346 }
7347
48c0e4e9
XG		 7348 if (!kvm->arch.n_requested_mmu_pages)
7349 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7350
48c0e4e9 7351 if (nr_mmu_pages)
0de10343 7352 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7353 /*
7354 * Write protect all pages for dirty logging.
c126d94f
XG		 7355 *
7356 * All the sptes including the large sptes which point to this
7357 * slot are set to readonly. We can not create any new large
7358 * spte on this slot until the end of the logging.
7359 *
7360 * See the comments in fast_page_fault().
c972f3b1 7361 */
8482644a 7362 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7363 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7364}
1d737c8a 7365
2df72e9b 7366void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7367{
6ca18b69 7368 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7369}
7370
2df72e9b
MT		 7371void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7372 struct kvm_memory_slot *slot)
7373{
6ca18b69 7374 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7375}
7376
1d737c8a
ZX		 7377int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7378{
b6b8a145
JK		 7379 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7380 kvm_x86_ops->check_nested_events(vcpu, false);
7381
af585b92
GN		 7382 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7383 !vcpu->arch.apf.halted)
7384 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7385 || kvm_apic_has_events(vcpu)
6aef266c 7386 || vcpu->arch.pv.pv_unhalted
7460fb4a 7387 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7388 (kvm_arch_interrupt_allowed(vcpu) &&
7389 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7390}
5736199a 7391
b6d33834 7392int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7393{
b6d33834 7394 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7395}
78646121
GN		 7396
7397int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7398{
7399 return kvm_x86_ops->interrupt_allowed(vcpu);
7400}
229456fc 7401
f92653ee
JK		 7402bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7403{
7404 unsigned long current_rip = kvm_rip_read(vcpu) +
7405 get_segment_base(vcpu, VCPU_SREG_CS);
7406
7407 return current_rip == linear_rip;
7408}
7409EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7410
94fe45da
JK		 7411unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7412{
7413 unsigned long rflags;
7414
7415 rflags = kvm_x86_ops->get_rflags(vcpu);
7416 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7417 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7418 return rflags;
7419}
7420EXPORT_SYMBOL_GPL(kvm_get_rflags);
7421
6addfc42 7422static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7423{
7424 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7425 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7426 rflags |= X86_EFLAGS_TF;
94fe45da 7427 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7428}
7429
7430void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7431{
7432 __kvm_set_rflags(vcpu, rflags);
3842d135 7433 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7434}
7435EXPORT_SYMBOL_GPL(kvm_set_rflags);
7436
56028d08
GN		 7437void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7438{
7439 int r;
7440
fb67e14f 7441 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7442 work->wakeup_all)
56028d08
GN		 7443 return;
7444
7445 r = kvm_mmu_reload(vcpu);
7446 if (unlikely(r))
7447 return;
7448
fb67e14f
XG		 7449 if (!vcpu->arch.mmu.direct_map &&
7450 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7451 return;
7452
56028d08
GN		 7453 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7454}
7455
af585b92
GN		 7456static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7457{
7458 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7459}
7460
7461static inline u32 kvm_async_pf_next_probe(u32 key)
7462{
7463 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7464}
7465
7466static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7467{
7468 u32 key = kvm_async_pf_hash_fn(gfn);
7469
7470 while (vcpu->arch.apf.gfns[key] != ~0)
7471 key = kvm_async_pf_next_probe(key);
7472
7473 vcpu->arch.apf.gfns[key] = gfn;
7474}
7475
7476static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7477{
7478 int i;
7479 u32 key = kvm_async_pf_hash_fn(gfn);
7480
7481 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7482 (vcpu->arch.apf.gfns[key] != gfn &&
7483 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7484 key = kvm_async_pf_next_probe(key);
7485
7486 return key;
7487}
7488
7489bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7490{
7491 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7492}
7493
7494static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7495{
7496 u32 i, j, k;
7497
7498 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7499 while (true) {
7500 vcpu->arch.apf.gfns[i] = ~0;
7501 do {
7502 j = kvm_async_pf_next_probe(j);
7503 if (vcpu->arch.apf.gfns[j] == ~0)
7504 return;
7505 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7506 /*
7507 * k lies cyclically in ]i,j]
7508 * | i.k.j |
7509 * |....j i.k.| or |.k..j i...|
7510 */
7511 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7512 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7513 i = j;
7514 }
7515}
7516
7c90705b
GN		 7517static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7518{
7519
7520 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7521 sizeof(val));
7522}
7523
af585b92
GN		 7524void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7525 struct kvm_async_pf *work)
7526{
6389ee94
AK		 7527 struct x86_exception fault;
7528
7c90705b 7529 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7530 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7531
7532 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7533 (vcpu->arch.apf.send_user_only &&
7534 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7535 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7536 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7537 fault.vector = PF_VECTOR;
7538 fault.error_code_valid = true;
7539 fault.error_code = 0;
7540 fault.nested_page_fault = false;
7541 fault.address = work->arch.token;
7542 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7543 }
af585b92
GN		 7544}
7545
7546void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7547 struct kvm_async_pf *work)
7548{
6389ee94
AK		 7549 struct x86_exception fault;
7550
7c90705b 7551 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7552 if (work->wakeup_all)
7c90705b
GN		 7553 work->arch.token = ~0; /* broadcast wakeup */
7554 else
7555 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7556
7557 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7558 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7559 fault.vector = PF_VECTOR;
7560 fault.error_code_valid = true;
7561 fault.error_code = 0;
7562 fault.nested_page_fault = false;
7563 fault.address = work->arch.token;
7564 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7565 }
e6d53e3b 7566 vcpu->arch.apf.halted = false;
a4fa1635 7567 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7568}
7569
7570bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7571{
7572 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7573 return true;
7574 else
7575 return !kvm_event_needs_reinjection(vcpu) &&
7576 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7577}
7578
e0f0bbc5
AW		 7579void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7580{
7581 atomic_inc(&kvm->arch.noncoherent_dma_count);
7582}
7583EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7584
7585void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7586{
7587 atomic_dec(&kvm->arch.noncoherent_dma_count);
7588}
7589EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7590
7591bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7592{
7593 return atomic_read(&kvm->arch.noncoherent_dma_count);
7594}
7595EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7596
229456fc
MT		 7597EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7598EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7599EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7600EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7601EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7602EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7603EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7604EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7605EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7606EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7607EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7608EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7609EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux 6.x block layer and io_uring tree(s)