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KVM: nVMX: Fix conditions for NMI injection
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
af585b92
GN		 165static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166{
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170}
171
18863bdd
AK		 172static void kvm_on_user_return(struct user_return_notifier *urn)
173{
174 unsigned slot;
18863bdd
AK		 175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 177 struct kvm_shared_msr_values *values;
18863bdd
AK		 178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
18863bdd
AK		 184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188}
189
2bf78fa7 190static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 191{
18863bdd 192 u64 value;
013f6a5d
MT		 193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 195
2bf78fa7
SY		 196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205}
206
207void kvm_define_shared_msr(unsigned slot, u32 msr)
208{
18863bdd
AK		 209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
18863bdd
AK		 214}
215EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217static void kvm_shared_msr_cpu_online(void)
218{
219 unsigned i;
18863bdd
AK		 220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 222 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 223}
224
d5696725 225void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 226{
013f6a5d
MT		 227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 229
2bf78fa7 230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 231 return;
2bf78fa7
SY		 232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
238 }
239}
240EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
3548bab5
AK		 242static void drop_user_return_notifiers(void *ignore)
243{
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
e3ba45b8
GL		 264asmlinkage void kvm_spurious_fault(void)
265{
266 /* Fault while not rebooting. We want the trace. */
267 BUG();
268}
269EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
3fd28fce
ED		 271#define EXCPT_BENIGN 0
272#define EXCPT_CONTRIBUTORY 1
273#define EXCPT_PF 2
274
275static int exception_class(int vector)
276{
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290}
291
292static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 293 unsigned nr, bool has_error, u32 error_code,
294 bool reinject)
3fd28fce
ED		 295{
296 u32 prev_nr;
297 int class1, class2;
298
3842d135
AK		 299 kvm_make_request(KVM_REQ_EVENT, vcpu);
300
3fd28fce
ED		 301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
3f0fd292 307 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 308 return;
309 }
310
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
a8eeb04a 315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 316 return;
317 }
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
327 } else
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
330 exception */
331 goto queue;
332}
333
298101da
AK		 334void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
ce7ddec4 336 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 337}
338EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
ce7ddec4
JR		 340void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341{
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
343}
344EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
db8fcefa 346void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 347{
db8fcefa
AP		 348 if (err)
349 kvm_inject_gp(vcpu, 0);
350 else
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
352}
353EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 354
6389ee94 355void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 356{
357 ++vcpu->stat.pf_guest;
6389ee94
AK		 358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 360}
27d6c865 361EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 362
6389ee94 363void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 364{
6389ee94
AK		 365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 367 else
6389ee94 368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 369}
370
3419ffc8
SY		 371void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372{
7460fb4a
AK		 373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 375}
376EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
298101da
AK		 378void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
ce7ddec4 380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 381}
382EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
ce7ddec4
JR		 384void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385{
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
387}
388EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
0a79b009
AK		 390/*
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
393 */
394bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 395{
0a79b009
AK		 396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397 return true;
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399 return false;
298101da 400}
0a79b009 401EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 402
ec92fe44
JR		 403/*
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
407 */
408int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
410 u32 access)
411{
412 gfn_t real_gfn;
413 gpa_t ngpa;
414
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
418 return -EFAULT;
419
420 real_gfn = gpa_to_gfn(real_gfn);
421
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423}
424EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
3d06b8bf
JR		 426int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
428{
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
431}
432
a03490ed
CO		 433/*
434 * Load the pae pdptrs. Return true is they are all valid.
435 */
ff03a073 436int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 437{
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440 int i;
441 int ret;
ff03a073 442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 443
ff03a073
JR		 444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 447 if (ret < 0) {
448 ret = 0;
449 goto out;
450 }
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 452 if (is_present_gpte(pdpte[i]) &&
20c466b5 453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 454 ret = 0;
455 goto out;
456 }
457 }
458 ret = 1;
459
ff03a073 460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 465out:
a03490ed
CO		 466
467 return ret;
468}
cc4b6871 469EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 470
d835dfec
AK		 471static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472{
ff03a073 473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 474 bool changed = true;
3d06b8bf
JR		 475 int offset;
476 gfn_t gfn;
d835dfec
AK		 477 int r;
478
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
480 return false;
481
6de4f3ad
AK		 482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
484 return true;
485
9f8fe504
AK		 486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 490 if (r < 0)
491 goto out;
ff03a073 492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 493out:
d835dfec
AK		 494
495 return changed;
496}
497
49a9b07e 498int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 499{
aad82703
SY		 500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
503
f9a48e6a
AK		 504 cr0 |= X86_CR0_ET;
505
ab344828 506#ifdef CONFIG_X86_64
0f12244f
GN		 507 if (cr0 & 0xffffffff00000000UL)
508 return 1;
ab344828
GN		 509#endif
510
511 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 512
0f12244f
GN		 513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514 return 1;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517 return 1;
a03490ed
CO		 518
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520#ifdef CONFIG_X86_64
f6801dff 521 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 522 int cs_db, cs_l;
523
0f12244f
GN		 524 if (!is_pae(vcpu))
525 return 1;
a03490ed 526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 527 if (cs_l)
528 return 1;
a03490ed
CO		 529 } else
530#endif
ff03a073 531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 532 kvm_read_cr3(vcpu)))
0f12244f 533 return 1;
a03490ed
CO		 534 }
535
ad756a16
MJ		 536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537 return 1;
538
a03490ed 539 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 540
d170c419 541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 542 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 543 kvm_async_pf_hash_reset(vcpu);
544 }
e5f3f027 545
aad82703
SY		 546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 548 return 0;
549}
2d3ad1f4 550EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 551
2d3ad1f4 552void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 553{
49a9b07e 554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 555}
2d3ad1f4 556EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 557
2acf923e
DC		 558int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
559{
560 u64 xcr0;
561
562 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
563 if (index != XCR_XFEATURE_ENABLED_MASK)
564 return 1;
565 xcr0 = xcr;
566 if (kvm_x86_ops->get_cpl(vcpu) != 0)
567 return 1;
568 if (!(xcr0 & XSTATE_FP))
569 return 1;
570 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
571 return 1;
572 if (xcr0 & ~host_xcr0)
573 return 1;
574 vcpu->arch.xcr0 = xcr0;
575 vcpu->guest_xcr0_loaded = 0;
576 return 0;
577}
578
579int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
580{
581 if (__kvm_set_xcr(vcpu, index, xcr)) {
582 kvm_inject_gp(vcpu, 0);
583 return 1;
584 }
585 return 0;
586}
587EXPORT_SYMBOL_GPL(kvm_set_xcr);
588
a83b29c6 589int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 590{
fc78f519 591 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 592 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
593 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 594 if (cr4 & CR4_RESERVED_BITS)
595 return 1;
a03490ed 596
2acf923e
DC		 597 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
598 return 1;
599
c68b734f
YW		 600 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
601 return 1;
602
74dc2b4f
YW		 603 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
604 return 1;
605
a03490ed 606 if (is_long_mode(vcpu)) {
0f12244f
GN		 607 if (!(cr4 & X86_CR4_PAE))
608 return 1;
a2edf57f
AK		 609 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
610 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 611 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
612 kvm_read_cr3(vcpu)))
0f12244f
GN		 613 return 1;
614
ad756a16
MJ		 615 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
616 if (!guest_cpuid_has_pcid(vcpu))
617 return 1;
618
619 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
620 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
621 return 1;
622 }
623
5e1746d6 624 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 625 return 1;
a03490ed 626
ad756a16
MJ		 627 if (((cr4 ^ old_cr4) & pdptr_bits) ||
628 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 629 kvm_mmu_reset_context(vcpu);
0f12244f 630
2acf923e 631 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 632 kvm_update_cpuid(vcpu);
2acf923e 633
0f12244f
GN		 634 return 0;
635}
2d3ad1f4 636EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 637
2390218b 638int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 639{
9f8fe504 640 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 641 kvm_mmu_sync_roots(vcpu);
d835dfec 642 kvm_mmu_flush_tlb(vcpu);
0f12244f 643 return 0;
d835dfec
AK		 644 }
645
a03490ed 646 if (is_long_mode(vcpu)) {
471842ec 647 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 648 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
649 return 1;
650 } else
651 if (cr3 & CR3_L_MODE_RESERVED_BITS)
652 return 1;
a03490ed
CO		 653 } else {
654 if (is_pae(vcpu)) {
0f12244f
GN		 655 if (cr3 & CR3_PAE_RESERVED_BITS)
656 return 1;
ff03a073
JR		 657 if (is_paging(vcpu) &&
658 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 659 return 1;
a03490ed
CO		 660 }
661 /*
662 * We don't check reserved bits in nonpae mode, because
663 * this isn't enforced, and VMware depends on this.
664 */
665 }
666
a03490ed
CO		 667 /*
668 * Does the new cr3 value map to physical memory? (Note, we
669 * catch an invalid cr3 even in real-mode, because it would
670 * cause trouble later on when we turn on paging anyway.)
671 *
672 * A real CPU would silently accept an invalid cr3 and would
673 * attempt to use it - with largely undefined (and often hard
674 * to debug) behavior on the guest side.
675 */
676 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 677 return 1;
678 vcpu->arch.cr3 = cr3;
aff48baa 679 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 680 vcpu->arch.mmu.new_cr3(vcpu);
681 return 0;
682}
2d3ad1f4 683EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 684
eea1cff9 685int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 686{
0f12244f
GN		 687 if (cr8 & CR8_RESERVED_BITS)
688 return 1;
a03490ed
CO		 689 if (irqchip_in_kernel(vcpu->kvm))
690 kvm_lapic_set_tpr(vcpu, cr8);
691 else
ad312c7c 692 vcpu->arch.cr8 = cr8;
0f12244f
GN		 693 return 0;
694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 696
2d3ad1f4 697unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 698{
699 if (irqchip_in_kernel(vcpu->kvm))
700 return kvm_lapic_get_cr8(vcpu);
701 else
ad312c7c 702 return vcpu->arch.cr8;
a03490ed 703}
2d3ad1f4 704EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 705
c8639010
JK		 706static void kvm_update_dr7(struct kvm_vcpu *vcpu)
707{
708 unsigned long dr7;
709
710 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
711 dr7 = vcpu->arch.guest_debug_dr7;
712 else
713 dr7 = vcpu->arch.dr7;
714 kvm_x86_ops->set_dr7(vcpu, dr7);
715 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
716}
717
338dbc97 718static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 719{
720 switch (dr) {
721 case 0 ... 3:
722 vcpu->arch.db[dr] = val;
723 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
724 vcpu->arch.eff_db[dr] = val;
725 break;
726 case 4:
338dbc97
GN		 727 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
728 return 1; /* #UD */
020df079
GN		 729 /* fall through */
730 case 6:
338dbc97
GN		 731 if (val & 0xffffffff00000000ULL)
732 return -1; /* #GP */
020df079
GN		 733 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
734 break;
735 case 5:
338dbc97
GN		 736 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
737 return 1; /* #UD */
020df079
GN		 738 /* fall through */
739 default: /* 7 */
338dbc97
GN		 740 if (val & 0xffffffff00000000ULL)
741 return -1; /* #GP */
020df079 742 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 743 kvm_update_dr7(vcpu);
020df079
GN		 744 break;
745 }
746
747 return 0;
748}
338dbc97
GN		 749
750int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
751{
752 int res;
753
754 res = __kvm_set_dr(vcpu, dr, val);
755 if (res > 0)
756 kvm_queue_exception(vcpu, UD_VECTOR);
757 else if (res < 0)
758 kvm_inject_gp(vcpu, 0);
759
760 return res;
761}
020df079
GN		 762EXPORT_SYMBOL_GPL(kvm_set_dr);
763
338dbc97 764static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 765{
766 switch (dr) {
767 case 0 ... 3:
768 *val = vcpu->arch.db[dr];
769 break;
770 case 4:
338dbc97 771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 772 return 1;
020df079
GN		 773 /* fall through */
774 case 6:
775 *val = vcpu->arch.dr6;
776 break;
777 case 5:
338dbc97 778 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 779 return 1;
020df079
GN		 780 /* fall through */
781 default: /* 7 */
782 *val = vcpu->arch.dr7;
783 break;
784 }
785
786 return 0;
787}
338dbc97
GN		 788
789int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
790{
791 if (_kvm_get_dr(vcpu, dr, val)) {
792 kvm_queue_exception(vcpu, UD_VECTOR);
793 return 1;
794 }
795 return 0;
796}
020df079
GN		 797EXPORT_SYMBOL_GPL(kvm_get_dr);
798
022cd0e8
AK		 799bool kvm_rdpmc(struct kvm_vcpu *vcpu)
800{
801 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
802 u64 data;
803 int err;
804
805 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
806 if (err)
807 return err;
808 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
809 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
810 return err;
811}
812EXPORT_SYMBOL_GPL(kvm_rdpmc);
813
043405e1
CO		 814/*
815 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
816 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
817 *
818 * This list is modified at module load time to reflect the
e3267cbb
GC		 819 * capabilities of the host cpu. This capabilities test skips MSRs that are
820 * kvm-specific. Those are put in the beginning of the list.
043405e1 821 */
e3267cbb 822
439793d4 823#define KVM_SAVE_MSRS_BEGIN 10
043405e1 824static u32 msrs_to_save[] = {
e3267cbb 825 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 826 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 827 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 828 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 829 MSR_KVM_PV_EOI_EN,
043405e1 830 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 831 MSR_STAR,
043405e1
CO		 832#ifdef CONFIG_X86_64
833 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
834#endif
e90aa41e 835 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 836};
837
838static unsigned num_msrs_to_save;
839
f1d24831 840static const u32 emulated_msrs[] = {
ba904635 841 MSR_IA32_TSC_ADJUST,
a3e06bbe 842 MSR_IA32_TSCDEADLINE,
043405e1 843 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 844 MSR_IA32_MCG_STATUS,
845 MSR_IA32_MCG_CTL,
043405e1
CO		 846};
847
b69e8cae 848static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 849{
aad82703
SY		 850 u64 old_efer = vcpu->arch.efer;
851
b69e8cae
RJ		 852 if (efer & efer_reserved_bits)
853 return 1;
15c4a640
CO		 854
855 if (is_paging(vcpu)
b69e8cae
RJ		 856 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
857 return 1;
15c4a640 858
1b2fd70c
AG		 859 if (efer & EFER_FFXSR) {
860 struct kvm_cpuid_entry2 *feat;
861
862 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 863 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
864 return 1;
1b2fd70c
AG		 865 }
866
d8017474
AG		 867 if (efer & EFER_SVME) {
868 struct kvm_cpuid_entry2 *feat;
869
870 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 871 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
872 return 1;
d8017474
AG		 873 }
874
15c4a640 875 efer &= ~EFER_LMA;
f6801dff 876 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 877
a3d204e2
SY		 878 kvm_x86_ops->set_efer(vcpu, efer);
879
aad82703
SY		 880 /* Update reserved bits */
881 if ((efer ^ old_efer) & EFER_NX)
882 kvm_mmu_reset_context(vcpu);
883
b69e8cae 884 return 0;
15c4a640
CO		 885}
886
f2b4b7dd
JR		 887void kvm_enable_efer_bits(u64 mask)
888{
889 efer_reserved_bits &= ~mask;
890}
891EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
892
893
15c4a640
CO		 894/*
895 * Writes msr value into into the appropriate "register".
896 * Returns 0 on success, non-0 otherwise.
897 * Assumes vcpu_load() was already called.
898 */
8fe8ab46 899int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 900{
8fe8ab46 901 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 902}
903
313a3dc7
CO		 904/*
905 * Adapt set_msr() to msr_io()'s calling convention
906 */
907static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
908{
8fe8ab46
WA		 909 struct msr_data msr;
910
911 msr.data = *data;
912 msr.index = index;
913 msr.host_initiated = true;
914 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 915}
916
16e8d74d
MT		 917#ifdef CONFIG_X86_64
918struct pvclock_gtod_data {
919 seqcount_t seq;
920
921 struct { /* extract of a clocksource struct */
922 int vclock_mode;
923 cycle_t cycle_last;
924 cycle_t mask;
925 u32 mult;
926 u32 shift;
927 } clock;
928
929 /* open coded 'struct timespec' */
930 u64 monotonic_time_snsec;
931 time_t monotonic_time_sec;
932};
933
934static struct pvclock_gtod_data pvclock_gtod_data;
935
936static void update_pvclock_gtod(struct timekeeper *tk)
937{
938 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
939
940 write_seqcount_begin(&vdata->seq);
941
942 /* copy pvclock gtod data */
943 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
944 vdata->clock.cycle_last = tk->clock->cycle_last;
945 vdata->clock.mask = tk->clock->mask;
946 vdata->clock.mult = tk->mult;
947 vdata->clock.shift = tk->shift;
948
949 vdata->monotonic_time_sec = tk->xtime_sec
950 + tk->wall_to_monotonic.tv_sec;
951 vdata->monotonic_time_snsec = tk->xtime_nsec
952 + (tk->wall_to_monotonic.tv_nsec
953 << tk->shift);
954 while (vdata->monotonic_time_snsec >=
955 (((u64)NSEC_PER_SEC) << tk->shift)) {
956 vdata->monotonic_time_snsec -=
957 ((u64)NSEC_PER_SEC) << tk->shift;
958 vdata->monotonic_time_sec++;
959 }
960
961 write_seqcount_end(&vdata->seq);
962}
963#endif
964
965
18068523
GOC		 966static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
967{
9ed3c444
AK		 968 int version;
969 int r;
50d0a0f9 970 struct pvclock_wall_clock wc;
923de3cf 971 struct timespec boot;
18068523
GOC		 972
973 if (!wall_clock)
974 return;
975
9ed3c444
AK		 976 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
977 if (r)
978 return;
979
980 if (version & 1)
981 ++version; /* first time write, random junk */
982
983 ++version;
18068523 984
18068523
GOC		 985 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
986
50d0a0f9
GH		 987 /*
988 * The guest calculates current wall clock time by adding
34c238a1 989 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 990 * wall clock specified here. guest system time equals host
991 * system time for us, thus we must fill in host boot time here.
992 */
923de3cf 993 getboottime(&boot);
50d0a0f9 994
4b648665
BR		 995 if (kvm->arch.kvmclock_offset) {
996 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
997 boot = timespec_sub(boot, ts);
998 }
50d0a0f9
GH		 999 wc.sec = boot.tv_sec;
1000 wc.nsec = boot.tv_nsec;
1001 wc.version = version;
18068523
GOC		 1002
1003 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1004
1005 version++;
1006 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1007}
1008
50d0a0f9
GH		 1009static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1010{
1011 uint32_t quotient, remainder;
1012
1013 /* Don't try to replace with do_div(), this one calculates
1014 * "(dividend << 32) / divisor" */
1015 __asm__ ( "divl %4"
1016 : "=a" (quotient), "=d" (remainder)
1017 : "0" (0), "1" (dividend), "r" (divisor) );
1018 return quotient;
1019}
1020
5f4e3f88
ZA		 1021static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1022 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1023{
5f4e3f88 1024 uint64_t scaled64;
50d0a0f9
GH		 1025 int32_t shift = 0;
1026 uint64_t tps64;
1027 uint32_t tps32;
1028
5f4e3f88
ZA		 1029 tps64 = base_khz * 1000LL;
1030 scaled64 = scaled_khz * 1000LL;
50933623 1031 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1032 tps64 >>= 1;
1033 shift--;
1034 }
1035
1036 tps32 = (uint32_t)tps64;
50933623
JK		 1037 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1038 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1039 scaled64 >>= 1;
1040 else
1041 tps32 <<= 1;
50d0a0f9
GH		 1042 shift++;
1043 }
1044
5f4e3f88
ZA		 1045 *pshift = shift;
1046 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1047
5f4e3f88
ZA		 1048 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1049 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1050}
1051
759379dd
ZA		 1052static inline u64 get_kernel_ns(void)
1053{
1054 struct timespec ts;
1055
1056 WARN_ON(preemptible());
1057 ktime_get_ts(&ts);
1058 monotonic_to_bootbased(&ts);
1059 return timespec_to_ns(&ts);
50d0a0f9
GH		 1060}
1061
d828199e 1062#ifdef CONFIG_X86_64
16e8d74d 1063static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1064#endif
16e8d74d 1065
c8076604 1066static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1067unsigned long max_tsc_khz;
c8076604 1068
cc578287 1069static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1070{
cc578287
ZA		 1071 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1072 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1073}
1074
cc578287 1075static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1076{
cc578287
ZA		 1077 u64 v = (u64)khz * (1000000 + ppm);
1078 do_div(v, 1000000);
1079 return v;
1e993611
JR		 1080}
1081
cc578287 1082static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1083{
cc578287
ZA		 1084 u32 thresh_lo, thresh_hi;
1085 int use_scaling = 0;
217fc9cf 1086
03ba32ca
MT		 1087 /* tsc_khz can be zero if TSC calibration fails */
1088 if (this_tsc_khz == 0)
1089 return;
1090
c285545f
ZA		 1091 /* Compute a scale to convert nanoseconds in TSC cycles */
1092 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1093 &vcpu->arch.virtual_tsc_shift,
1094 &vcpu->arch.virtual_tsc_mult);
1095 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1096
1097 /*
1098 * Compute the variation in TSC rate which is acceptable
1099 * within the range of tolerance and decide if the
1100 * rate being applied is within that bounds of the hardware
1101 * rate. If so, no scaling or compensation need be done.
1102 */
1103 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1104 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1105 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1106 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1107 use_scaling = 1;
1108 }
1109 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1110}
1111
1112static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1113{
e26101b1 1114 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1115 vcpu->arch.virtual_tsc_mult,
1116 vcpu->arch.virtual_tsc_shift);
e26101b1 1117 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1118 return tsc;
1119}
1120
b48aa97e
MT		 1121void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1122{
1123#ifdef CONFIG_X86_64
1124 bool vcpus_matched;
1125 bool do_request = false;
1126 struct kvm_arch *ka = &vcpu->kvm->arch;
1127 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1128
1129 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1130 atomic_read(&vcpu->kvm->online_vcpus));
1131
1132 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1133 if (!ka->use_master_clock)
1134 do_request = 1;
1135
1136 if (!vcpus_matched && ka->use_master_clock)
1137 do_request = 1;
1138
1139 if (do_request)
1140 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1141
1142 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1143 atomic_read(&vcpu->kvm->online_vcpus),
1144 ka->use_master_clock, gtod->clock.vclock_mode);
1145#endif
1146}
1147
ba904635
WA		 1148static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1149{
1150 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1151 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1152}
1153
8fe8ab46 1154void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1155{
1156 struct kvm *kvm = vcpu->kvm;
f38e098f 1157 u64 offset, ns, elapsed;
99e3e30a 1158 unsigned long flags;
02626b6a 1159 s64 usdiff;
b48aa97e 1160 bool matched;
8fe8ab46 1161 u64 data = msr->data;
99e3e30a 1162
038f8c11 1163 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1164 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1165 ns = get_kernel_ns();
f38e098f 1166 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1167
03ba32ca
MT		 1168 if (vcpu->arch.virtual_tsc_khz) {
1169 /* n.b - signed multiplication and division required */
1170 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1171#ifdef CONFIG_X86_64
03ba32ca 1172 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1173#else
03ba32ca
MT		 1174 /* do_div() only does unsigned */
1175 asm("idivl %2; xor %%edx, %%edx"
1176 : "=A"(usdiff)
1177 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1178#endif
03ba32ca
MT		 1179 do_div(elapsed, 1000);
1180 usdiff -= elapsed;
1181 if (usdiff < 0)
1182 usdiff = -usdiff;
1183 } else
1184 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1185
1186 /*
5d3cb0f6
ZA		 1187 * Special case: TSC write with a small delta (1 second) of virtual
1188 * cycle time against real time is interpreted as an attempt to
1189 * synchronize the CPU.
1190 *
1191 * For a reliable TSC, we can match TSC offsets, and for an unstable
1192 * TSC, we add elapsed time in this computation. We could let the
1193 * compensation code attempt to catch up if we fall behind, but
1194 * it's better to try to match offsets from the beginning.
1195 */
02626b6a 1196 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1197 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1198 if (!check_tsc_unstable()) {
e26101b1 1199 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1200 pr_debug("kvm: matched tsc offset for %llu\n", data);
1201 } else {
857e4099 1202 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1203 data += delta;
1204 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1205 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1206 }
b48aa97e 1207 matched = true;
e26101b1
ZA		 1208 } else {
1209 /*
1210 * We split periods of matched TSC writes into generations.
1211 * For each generation, we track the original measured
1212 * nanosecond time, offset, and write, so if TSCs are in
1213 * sync, we can match exact offset, and if not, we can match
4a969980 1214 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1215 *
1216 * These values are tracked in kvm->arch.cur_xxx variables.
1217 */
1218 kvm->arch.cur_tsc_generation++;
1219 kvm->arch.cur_tsc_nsec = ns;
1220 kvm->arch.cur_tsc_write = data;
1221 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1222 matched = false;
e26101b1
ZA		 1223 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1224 kvm->arch.cur_tsc_generation, data);
f38e098f 1225 }
e26101b1
ZA		 1226
1227 /*
1228 * We also track th most recent recorded KHZ, write and time to
1229 * allow the matching interval to be extended at each write.
1230 */
f38e098f
ZA		 1231 kvm->arch.last_tsc_nsec = ns;
1232 kvm->arch.last_tsc_write = data;
5d3cb0f6 1233 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1234
1235 /* Reset of TSC must disable overshoot protection below */
1236 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1237 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1238
1239 /* Keep track of which generation this VCPU has synchronized to */
1240 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1241 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1242 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1243
ba904635
WA		 1244 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1245 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1246 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1247 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1248
1249 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1250 if (matched)
1251 kvm->arch.nr_vcpus_matched_tsc++;
1252 else
1253 kvm->arch.nr_vcpus_matched_tsc = 0;
1254
1255 kvm_track_tsc_matching(vcpu);
1256 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1257}
e26101b1 1258
99e3e30a
ZA		 1259EXPORT_SYMBOL_GPL(kvm_write_tsc);
1260
d828199e
MT		 1261#ifdef CONFIG_X86_64
1262
1263static cycle_t read_tsc(void)
1264{
1265 cycle_t ret;
1266 u64 last;
1267
1268 /*
1269 * Empirically, a fence (of type that depends on the CPU)
1270 * before rdtsc is enough to ensure that rdtsc is ordered
1271 * with respect to loads. The various CPU manuals are unclear
1272 * as to whether rdtsc can be reordered with later loads,
1273 * but no one has ever seen it happen.
1274 */
1275 rdtsc_barrier();
1276 ret = (cycle_t)vget_cycles();
1277
1278 last = pvclock_gtod_data.clock.cycle_last;
1279
1280 if (likely(ret >= last))
1281 return ret;
1282
1283 /*
1284 * GCC likes to generate cmov here, but this branch is extremely
1285 * predictable (it's just a funciton of time and the likely is
1286 * very likely) and there's a data dependence, so force GCC
1287 * to generate a branch instead. I don't barrier() because
1288 * we don't actually need a barrier, and if this function
1289 * ever gets inlined it will generate worse code.
1290 */
1291 asm volatile ("");
1292 return last;
1293}
1294
1295static inline u64 vgettsc(cycle_t *cycle_now)
1296{
1297 long v;
1298 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1299
1300 *cycle_now = read_tsc();
1301
1302 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1303 return v * gtod->clock.mult;
1304}
1305
1306static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1307{
1308 unsigned long seq;
1309 u64 ns;
1310 int mode;
1311 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1312
1313 ts->tv_nsec = 0;
1314 do {
1315 seq = read_seqcount_begin(&gtod->seq);
1316 mode = gtod->clock.vclock_mode;
1317 ts->tv_sec = gtod->monotonic_time_sec;
1318 ns = gtod->monotonic_time_snsec;
1319 ns += vgettsc(cycle_now);
1320 ns >>= gtod->clock.shift;
1321 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1322 timespec_add_ns(ts, ns);
1323
1324 return mode;
1325}
1326
1327/* returns true if host is using tsc clocksource */
1328static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1329{
1330 struct timespec ts;
1331
1332 /* checked again under seqlock below */
1333 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1334 return false;
1335
1336 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1337 return false;
1338
1339 monotonic_to_bootbased(&ts);
1340 *kernel_ns = timespec_to_ns(&ts);
1341
1342 return true;
1343}
1344#endif
1345
1346/*
1347 *
b48aa97e
MT		 1348 * Assuming a stable TSC across physical CPUS, and a stable TSC
1349 * across virtual CPUs, the following condition is possible.
1350 * Each numbered line represents an event visible to both
d828199e
MT		 1351 * CPUs at the next numbered event.
1352 *
1353 * "timespecX" represents host monotonic time. "tscX" represents
1354 * RDTSC value.
1355 *
1356 * VCPU0 on CPU0 | VCPU1 on CPU1
1357 *
1358 * 1. read timespec0,tsc0
1359 * 2. | timespec1 = timespec0 + N
1360 * | tsc1 = tsc0 + M
1361 * 3. transition to guest | transition to guest
1362 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1363 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1364 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1365 *
1366 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1367 *
1368 * - ret0 < ret1
1369 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1370 * ...
1371 * - 0 < N - M => M < N
1372 *
1373 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1374 * always the case (the difference between two distinct xtime instances
1375 * might be smaller then the difference between corresponding TSC reads,
1376 * when updating guest vcpus pvclock areas).
1377 *
1378 * To avoid that problem, do not allow visibility of distinct
1379 * system_timestamp/tsc_timestamp values simultaneously: use a master
1380 * copy of host monotonic time values. Update that master copy
1381 * in lockstep.
1382 *
b48aa97e 1383 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1384 *
1385 */
1386
1387static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1388{
1389#ifdef CONFIG_X86_64
1390 struct kvm_arch *ka = &kvm->arch;
1391 int vclock_mode;
b48aa97e
MT		 1392 bool host_tsc_clocksource, vcpus_matched;
1393
1394 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1395 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1396
1397 /*
1398 * If the host uses TSC clock, then passthrough TSC as stable
1399 * to the guest.
1400 */
b48aa97e 1401 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1402 &ka->master_kernel_ns,
1403 &ka->master_cycle_now);
1404
b48aa97e
MT		 1405 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1406
d828199e
MT		 1407 if (ka->use_master_clock)
1408 atomic_set(&kvm_guest_has_master_clock, 1);
1409
1410 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1411 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1412 vcpus_matched);
d828199e
MT		 1413#endif
1414}
1415
34c238a1 1416static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1417{
d828199e 1418 unsigned long flags, this_tsc_khz;
18068523 1419 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1420 struct kvm_arch *ka = &v->kvm->arch;
1d5f066e 1421 s64 kernel_ns, max_kernel_ns;
d828199e 1422 u64 tsc_timestamp, host_tsc;
0b79459b 1423 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1424 u8 pvclock_flags;
d828199e
MT		 1425 bool use_master_clock;
1426
1427 kernel_ns = 0;
1428 host_tsc = 0;
18068523 1429
d828199e
MT		 1430 /*
1431 * If the host uses TSC clock, then passthrough TSC as stable
1432 * to the guest.
1433 */
1434 spin_lock(&ka->pvclock_gtod_sync_lock);
1435 use_master_clock = ka->use_master_clock;
1436 if (use_master_clock) {
1437 host_tsc = ka->master_cycle_now;
1438 kernel_ns = ka->master_kernel_ns;
1439 }
1440 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1441
1442 /* Keep irq disabled to prevent changes to the clock */
1443 local_irq_save(flags);
1444 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1445 if (unlikely(this_tsc_khz == 0)) {
1446 local_irq_restore(flags);
1447 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1448 return 1;
1449 }
d828199e
MT		 1450 if (!use_master_clock) {
1451 host_tsc = native_read_tsc();
1452 kernel_ns = get_kernel_ns();
1453 }
1454
1455 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1456
c285545f
ZA		 1457 /*
1458 * We may have to catch up the TSC to match elapsed wall clock
1459 * time for two reasons, even if kvmclock is used.
1460 * 1) CPU could have been running below the maximum TSC rate
1461 * 2) Broken TSC compensation resets the base at each VCPU
1462 * entry to avoid unknown leaps of TSC even when running
1463 * again on the same CPU. This may cause apparent elapsed
1464 * time to disappear, and the guest to stand still or run
1465 * very slowly.
1466 */
1467 if (vcpu->tsc_catchup) {
1468 u64 tsc = compute_guest_tsc(v, kernel_ns);
1469 if (tsc > tsc_timestamp) {
f1e2b260 1470 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1471 tsc_timestamp = tsc;
1472 }
50d0a0f9
GH		 1473 }
1474
18068523
GOC		 1475 local_irq_restore(flags);
1476
0b79459b 1477 if (!vcpu->pv_time_enabled)
c285545f 1478 return 0;
18068523 1479
1d5f066e
ZA		 1480 /*
1481 * Time as measured by the TSC may go backwards when resetting the base
1482 * tsc_timestamp. The reason for this is that the TSC resolution is
1483 * higher than the resolution of the other clock scales. Thus, many
1484 * possible measurments of the TSC correspond to one measurement of any
1485 * other clock, and so a spread of values is possible. This is not a
1486 * problem for the computation of the nanosecond clock; with TSC rates
1487 * around 1GHZ, there can only be a few cycles which correspond to one
1488 * nanosecond value, and any path through this code will inevitably
1489 * take longer than that. However, with the kernel_ns value itself,
1490 * the precision may be much lower, down to HZ granularity. If the
1491 * first sampling of TSC against kernel_ns ends in the low part of the
1492 * range, and the second in the high end of the range, we can get:
1493 *
1494 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1495 *
1496 * As the sampling errors potentially range in the thousands of cycles,
1497 * it is possible such a time value has already been observed by the
1498 * guest. To protect against this, we must compute the system time as
1499 * observed by the guest and ensure the new system time is greater.
1500 */
1501 max_kernel_ns = 0;
b183aa58 1502 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1503 max_kernel_ns = vcpu->last_guest_tsc -
1504 vcpu->hv_clock.tsc_timestamp;
1505 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1506 vcpu->hv_clock.tsc_to_system_mul,
1507 vcpu->hv_clock.tsc_shift);
1508 max_kernel_ns += vcpu->last_kernel_ns;
1509 }
afbcf7ab 1510
e48672fa 1511 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1512 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1513 &vcpu->hv_clock.tsc_shift,
1514 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1515 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1516 }
1517
d828199e
MT		 1518 /* with a master <monotonic time, tsc value> tuple,
1519 * pvclock clock reads always increase at the (scaled) rate
1520 * of guest TSC - no need to deal with sampling errors.
1521 */
1522 if (!use_master_clock) {
1523 if (max_kernel_ns > kernel_ns)
1524 kernel_ns = max_kernel_ns;
1525 }
8cfdc000 1526 /* With all the info we got, fill in the values */
1d5f066e 1527 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1528 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1529 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1530 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1531
18068523
GOC		 1532 /*
1533 * The interface expects us to write an even number signaling that the
1534 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1535 * state, we just increase by 2 at the end.
18068523 1536 */
50d0a0f9 1537 vcpu->hv_clock.version += 2;
18068523 1538
0b79459b
AH		 1539 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1540 &guest_hv_clock, sizeof(guest_hv_clock))))
1541 return 0;
78c0337a
MT		 1542
1543 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1544 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1545
1546 if (vcpu->pvclock_set_guest_stopped_request) {
1547 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1548 vcpu->pvclock_set_guest_stopped_request = false;
1549 }
1550
d828199e
MT		 1551 /* If the host uses TSC clocksource, then it is stable */
1552 if (use_master_clock)
1553 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1554
78c0337a
MT		 1555 vcpu->hv_clock.flags = pvclock_flags;
1556
0b79459b
AH		 1557 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1558 &vcpu->hv_clock,
1559 sizeof(vcpu->hv_clock));
8cfdc000 1560 return 0;
c8076604
GH		 1561}
1562
9ba075a6
AK		 1563static bool msr_mtrr_valid(unsigned msr)
1564{
1565 switch (msr) {
1566 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1567 case MSR_MTRRfix64K_00000:
1568 case MSR_MTRRfix16K_80000:
1569 case MSR_MTRRfix16K_A0000:
1570 case MSR_MTRRfix4K_C0000:
1571 case MSR_MTRRfix4K_C8000:
1572 case MSR_MTRRfix4K_D0000:
1573 case MSR_MTRRfix4K_D8000:
1574 case MSR_MTRRfix4K_E0000:
1575 case MSR_MTRRfix4K_E8000:
1576 case MSR_MTRRfix4K_F0000:
1577 case MSR_MTRRfix4K_F8000:
1578 case MSR_MTRRdefType:
1579 case MSR_IA32_CR_PAT:
1580 return true;
1581 case 0x2f8:
1582 return true;
1583 }
1584 return false;
1585}
1586
d6289b93
MT		 1587static bool valid_pat_type(unsigned t)
1588{
1589 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1590}
1591
1592static bool valid_mtrr_type(unsigned t)
1593{
1594 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1595}
1596
1597static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1598{
1599 int i;
1600
1601 if (!msr_mtrr_valid(msr))
1602 return false;
1603
1604 if (msr == MSR_IA32_CR_PAT) {
1605 for (i = 0; i < 8; i++)
1606 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1607 return false;
1608 return true;
1609 } else if (msr == MSR_MTRRdefType) {
1610 if (data & ~0xcff)
1611 return false;
1612 return valid_mtrr_type(data & 0xff);
1613 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1614 for (i = 0; i < 8 ; i++)
1615 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1616 return false;
1617 return true;
1618 }
1619
1620 /* variable MTRRs */
1621 return valid_mtrr_type(data & 0xff);
1622}
1623
9ba075a6
AK		 1624static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1625{
0bed3b56
SY		 1626 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1627
d6289b93 1628 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1629 return 1;
1630
0bed3b56
SY		 1631 if (msr == MSR_MTRRdefType) {
1632 vcpu->arch.mtrr_state.def_type = data;
1633 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1634 } else if (msr == MSR_MTRRfix64K_00000)
1635 p[0] = data;
1636 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1637 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1638 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1639 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1640 else if (msr == MSR_IA32_CR_PAT)
1641 vcpu->arch.pat = data;
1642 else { /* Variable MTRRs */
1643 int idx, is_mtrr_mask;
1644 u64 *pt;
1645
1646 idx = (msr - 0x200) / 2;
1647 is_mtrr_mask = msr - 0x200 - 2 * idx;
1648 if (!is_mtrr_mask)
1649 pt =
1650 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1651 else
1652 pt =
1653 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1654 *pt = data;
1655 }
1656
1657 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1658 return 0;
1659}
15c4a640 1660
890ca9ae 1661static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1662{
890ca9ae
HY		 1663 u64 mcg_cap = vcpu->arch.mcg_cap;
1664 unsigned bank_num = mcg_cap & 0xff;
1665
15c4a640 1666 switch (msr) {
15c4a640 1667 case MSR_IA32_MCG_STATUS:
890ca9ae 1668 vcpu->arch.mcg_status = data;
15c4a640 1669 break;
c7ac679c 1670 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1671 if (!(mcg_cap & MCG_CTL_P))
1672 return 1;
1673 if (data != 0 && data != ~(u64)0)
1674 return -1;
1675 vcpu->arch.mcg_ctl = data;
1676 break;
1677 default:
1678 if (msr >= MSR_IA32_MC0_CTL &&
1679 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1680 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1681 /* only 0 or all 1s can be written to IA32_MCi_CTL
1682 * some Linux kernels though clear bit 10 in bank 4 to
1683 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1684 * this to avoid an uncatched #GP in the guest
1685 */
890ca9ae 1686 if ((offset & 0x3) == 0 &&
114be429 1687 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1688 return -1;
1689 vcpu->arch.mce_banks[offset] = data;
1690 break;
1691 }
1692 return 1;
1693 }
1694 return 0;
1695}
1696
ffde22ac
ES		 1697static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1698{
1699 struct kvm *kvm = vcpu->kvm;
1700 int lm = is_long_mode(vcpu);
1701 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1702 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1703 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1704 : kvm->arch.xen_hvm_config.blob_size_32;
1705 u32 page_num = data & ~PAGE_MASK;
1706 u64 page_addr = data & PAGE_MASK;
1707 u8 *page;
1708 int r;
1709
1710 r = -E2BIG;
1711 if (page_num >= blob_size)
1712 goto out;
1713 r = -ENOMEM;
ff5c2c03
SL		 1714 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1715 if (IS_ERR(page)) {
1716 r = PTR_ERR(page);
ffde22ac 1717 goto out;
ff5c2c03 1718 }
ffde22ac
ES		 1719 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1720 goto out_free;
1721 r = 0;
1722out_free:
1723 kfree(page);
1724out:
1725 return r;
1726}
1727
55cd8e5a
GN		 1728static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1729{
1730 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1731}
1732
1733static bool kvm_hv_msr_partition_wide(u32 msr)
1734{
1735 bool r = false;
1736 switch (msr) {
1737 case HV_X64_MSR_GUEST_OS_ID:
1738 case HV_X64_MSR_HYPERCALL:
1739 r = true;
1740 break;
1741 }
1742
1743 return r;
1744}
1745
1746static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1747{
1748 struct kvm *kvm = vcpu->kvm;
1749
1750 switch (msr) {
1751 case HV_X64_MSR_GUEST_OS_ID:
1752 kvm->arch.hv_guest_os_id = data;
1753 /* setting guest os id to zero disables hypercall page */
1754 if (!kvm->arch.hv_guest_os_id)
1755 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1756 break;
1757 case HV_X64_MSR_HYPERCALL: {
1758 u64 gfn;
1759 unsigned long addr;
1760 u8 instructions[4];
1761
1762 /* if guest os id is not set hypercall should remain disabled */
1763 if (!kvm->arch.hv_guest_os_id)
1764 break;
1765 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1766 kvm->arch.hv_hypercall = data;
1767 break;
1768 }
1769 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1770 addr = gfn_to_hva(kvm, gfn);
1771 if (kvm_is_error_hva(addr))
1772 return 1;
1773 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1774 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1775 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1776 return 1;
1777 kvm->arch.hv_hypercall = data;
1778 break;
1779 }
1780 default:
a737f256
CD		 1781 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1782 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1783 return 1;
1784 }
1785 return 0;
1786}
1787
1788static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1789{
10388a07
GN		 1790 switch (msr) {
1791 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1792 unsigned long addr;
55cd8e5a 1793
10388a07
GN		 1794 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1795 vcpu->arch.hv_vapic = data;
1796 break;
1797 }
1798 addr = gfn_to_hva(vcpu->kvm, data >>
1799 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1800 if (kvm_is_error_hva(addr))
1801 return 1;
8b0cedff 1802 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1803 return 1;
1804 vcpu->arch.hv_vapic = data;
1805 break;
1806 }
1807 case HV_X64_MSR_EOI:
1808 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1809 case HV_X64_MSR_ICR:
1810 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1811 case HV_X64_MSR_TPR:
1812 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1813 default:
a737f256
CD		 1814 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1815 "data 0x%llx\n", msr, data);
10388a07
GN		 1816 return 1;
1817 }
1818
1819 return 0;
55cd8e5a
GN		 1820}
1821
344d9588
GN		 1822static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1823{
1824 gpa_t gpa = data & ~0x3f;
1825
4a969980 1826 /* Bits 2:5 are reserved, Should be zero */
6adba527 1827 if (data & 0x3c)
344d9588
GN		 1828 return 1;
1829
1830 vcpu->arch.apf.msr_val = data;
1831
1832 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1833 kvm_clear_async_pf_completion_queue(vcpu);
1834 kvm_async_pf_hash_reset(vcpu);
1835 return 0;
1836 }
1837
1838 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1839 return 1;
1840
6adba527 1841 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1842 kvm_async_pf_wakeup_all(vcpu);
1843 return 0;
1844}
1845
12f9a48f
GC		 1846static void kvmclock_reset(struct kvm_vcpu *vcpu)
1847{
0b79459b 1848 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1849}
1850
c9aaa895
GC		 1851static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1852{
1853 u64 delta;
1854
1855 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1856 return;
1857
1858 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1859 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1860 vcpu->arch.st.accum_steal = delta;
1861}
1862
1863static void record_steal_time(struct kvm_vcpu *vcpu)
1864{
1865 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1866 return;
1867
1868 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1869 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1870 return;
1871
1872 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1873 vcpu->arch.st.steal.version += 2;
1874 vcpu->arch.st.accum_steal = 0;
1875
1876 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1877 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1878}
1879
8fe8ab46 1880int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1881{
5753785f 1882 bool pr = false;
8fe8ab46
WA		 1883 u32 msr = msr_info->index;
1884 u64 data = msr_info->data;
5753785f 1885
15c4a640 1886 switch (msr) {
2e32b719
BP		 1887 case MSR_AMD64_NB_CFG:
1888 case MSR_IA32_UCODE_REV:
1889 case MSR_IA32_UCODE_WRITE:
1890 case MSR_VM_HSAVE_PA:
1891 case MSR_AMD64_PATCH_LOADER:
1892 case MSR_AMD64_BU_CFG2:
1893 break;
1894
15c4a640 1895 case MSR_EFER:
b69e8cae 1896 return set_efer(vcpu, data);
8f1589d9
AP		 1897 case MSR_K7_HWCR:
1898 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1899 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1900 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1901 if (data != 0) {
a737f256
CD		 1902 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1903 data);
8f1589d9
AP		 1904 return 1;
1905 }
15c4a640 1906 break;
f7c6d140
AP		 1907 case MSR_FAM10H_MMIO_CONF_BASE:
1908 if (data != 0) {
a737f256
CD		 1909 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1910 "0x%llx\n", data);
f7c6d140
AP		 1911 return 1;
1912 }
15c4a640 1913 break;
b5e2fec0
AG		 1914 case MSR_IA32_DEBUGCTLMSR:
1915 if (!data) {
1916 /* We support the non-activated case already */
1917 break;
1918 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1919 /* Values other than LBR and BTF are vendor-specific,
1920 thus reserved and should throw a #GP */
1921 return 1;
1922 }
a737f256
CD		 1923 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1924 __func__, data);
b5e2fec0 1925 break;
9ba075a6
AK		 1926 case 0x200 ... 0x2ff:
1927 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1928 case MSR_IA32_APICBASE:
1929 kvm_set_apic_base(vcpu, data);
1930 break;
0105d1a5
GN		 1931 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1932 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1933 case MSR_IA32_TSCDEADLINE:
1934 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1935 break;
ba904635
WA		 1936 case MSR_IA32_TSC_ADJUST:
1937 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1938 if (!msr_info->host_initiated) {
1939 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1940 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1941 }
1942 vcpu->arch.ia32_tsc_adjust_msr = data;
1943 }
1944 break;
15c4a640 1945 case MSR_IA32_MISC_ENABLE:
ad312c7c 1946 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1947 break;
11c6bffa 1948 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1949 case MSR_KVM_WALL_CLOCK:
1950 vcpu->kvm->arch.wall_clock = data;
1951 kvm_write_wall_clock(vcpu->kvm, data);
1952 break;
11c6bffa 1953 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1954 case MSR_KVM_SYSTEM_TIME: {
0b79459b 1955 u64 gpa_offset;
12f9a48f 1956 kvmclock_reset(vcpu);
18068523
GOC		 1957
1958 vcpu->arch.time = data;
c285545f 1959 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1960
1961 /* we verify if the enable bit is set... */
1962 if (!(data & 1))
1963 break;
1964
0b79459b 1965 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 1966
c300aa64 1967 /* Check that the address is 32-byte aligned. */
0b79459b 1968 if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1))
c300aa64 1969 break;
18068523 1970
0b79459b
AH		 1971 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1972 &vcpu->arch.pv_time, data & ~1ULL))
1973 vcpu->arch.pv_time_enabled = false;
1974 else
1975 vcpu->arch.pv_time_enabled = true;
32cad84f 1976
18068523
GOC		 1977 break;
1978 }
344d9588
GN		 1979 case MSR_KVM_ASYNC_PF_EN:
1980 if (kvm_pv_enable_async_pf(vcpu, data))
1981 return 1;
1982 break;
c9aaa895
GC		 1983 case MSR_KVM_STEAL_TIME:
1984
1985 if (unlikely(!sched_info_on()))
1986 return 1;
1987
1988 if (data & KVM_STEAL_RESERVED_MASK)
1989 return 1;
1990
1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1992 data & KVM_STEAL_VALID_BITS))
1993 return 1;
1994
1995 vcpu->arch.st.msr_val = data;
1996
1997 if (!(data & KVM_MSR_ENABLED))
1998 break;
1999
2000 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2001
2002 preempt_disable();
2003 accumulate_steal_time(vcpu);
2004 preempt_enable();
2005
2006 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2007
2008 break;
ae7a2a3f
MT		 2009 case MSR_KVM_PV_EOI_EN:
2010 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2011 return 1;
2012 break;
c9aaa895 2013
890ca9ae
HY		 2014 case MSR_IA32_MCG_CTL:
2015 case MSR_IA32_MCG_STATUS:
2016 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2017 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2018
2019 /* Performance counters are not protected by a CPUID bit,
2020 * so we should check all of them in the generic path for the sake of
2021 * cross vendor migration.
2022 * Writing a zero into the event select MSRs disables them,
2023 * which we perfectly emulate ;-). Any other value should be at least
2024 * reported, some guests depend on them.
2025 */
71db6023
AP		 2026 case MSR_K7_EVNTSEL0:
2027 case MSR_K7_EVNTSEL1:
2028 case MSR_K7_EVNTSEL2:
2029 case MSR_K7_EVNTSEL3:
2030 if (data != 0)
a737f256
CD		 2031 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2032 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2033 break;
2034 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2035 * so we ignore writes to make it happy.
2036 */
71db6023
AP		 2037 case MSR_K7_PERFCTR0:
2038 case MSR_K7_PERFCTR1:
2039 case MSR_K7_PERFCTR2:
2040 case MSR_K7_PERFCTR3:
a737f256
CD		 2041 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2042 "0x%x data 0x%llx\n", msr, data);
71db6023 2043 break;
5753785f
GN		 2044 case MSR_P6_PERFCTR0:
2045 case MSR_P6_PERFCTR1:
2046 pr = true;
2047 case MSR_P6_EVNTSEL0:
2048 case MSR_P6_EVNTSEL1:
2049 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2050 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2051
2052 if (pr || data != 0)
a737f256
CD		 2053 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2054 "0x%x data 0x%llx\n", msr, data);
5753785f 2055 break;
84e0cefa
JS		 2056 case MSR_K7_CLK_CTL:
2057 /*
2058 * Ignore all writes to this no longer documented MSR.
2059 * Writes are only relevant for old K7 processors,
2060 * all pre-dating SVM, but a recommended workaround from
4a969980 2061 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2062 * affected processor models on the command line, hence
2063 * the need to ignore the workaround.
2064 */
2065 break;
55cd8e5a
GN		 2066 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2067 if (kvm_hv_msr_partition_wide(msr)) {
2068 int r;
2069 mutex_lock(&vcpu->kvm->lock);
2070 r = set_msr_hyperv_pw(vcpu, msr, data);
2071 mutex_unlock(&vcpu->kvm->lock);
2072 return r;
2073 } else
2074 return set_msr_hyperv(vcpu, msr, data);
2075 break;
91c9c3ed 2076 case MSR_IA32_BBL_CR_CTL3:
2077 /* Drop writes to this legacy MSR -- see rdmsr
2078 * counterpart for further detail.
2079 */
a737f256 2080 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2081 break;
2b036c6b
BO		 2082 case MSR_AMD64_OSVW_ID_LENGTH:
2083 if (!guest_cpuid_has_osvw(vcpu))
2084 return 1;
2085 vcpu->arch.osvw.length = data;
2086 break;
2087 case MSR_AMD64_OSVW_STATUS:
2088 if (!guest_cpuid_has_osvw(vcpu))
2089 return 1;
2090 vcpu->arch.osvw.status = data;
2091 break;
15c4a640 2092 default:
ffde22ac
ES		 2093 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2094 return xen_hvm_config(vcpu, data);
f5132b01 2095 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2096 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2097 if (!ignore_msrs) {
a737f256
CD		 2098 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2099 msr, data);
ed85c068
AP		 2100 return 1;
2101 } else {
a737f256
CD		 2102 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2103 msr, data);
ed85c068
AP		 2104 break;
2105 }
15c4a640
CO		 2106 }
2107 return 0;
2108}
2109EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2110
2111
2112/*
2113 * Reads an msr value (of 'msr_index') into 'pdata'.
2114 * Returns 0 on success, non-0 otherwise.
2115 * Assumes vcpu_load() was already called.
2116 */
2117int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2118{
2119 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2120}
2121
9ba075a6
AK		 2122static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2123{
0bed3b56
SY		 2124 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2125
9ba075a6
AK		 2126 if (!msr_mtrr_valid(msr))
2127 return 1;
2128
0bed3b56
SY		 2129 if (msr == MSR_MTRRdefType)
2130 *pdata = vcpu->arch.mtrr_state.def_type +
2131 (vcpu->arch.mtrr_state.enabled << 10);
2132 else if (msr == MSR_MTRRfix64K_00000)
2133 *pdata = p[0];
2134 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2135 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2136 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2137 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2138 else if (msr == MSR_IA32_CR_PAT)
2139 *pdata = vcpu->arch.pat;
2140 else { /* Variable MTRRs */
2141 int idx, is_mtrr_mask;
2142 u64 *pt;
2143
2144 idx = (msr - 0x200) / 2;
2145 is_mtrr_mask = msr - 0x200 - 2 * idx;
2146 if (!is_mtrr_mask)
2147 pt =
2148 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2149 else
2150 pt =
2151 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2152 *pdata = *pt;
2153 }
2154
9ba075a6
AK		 2155 return 0;
2156}
2157
890ca9ae 2158static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2159{
2160 u64 data;
890ca9ae
HY		 2161 u64 mcg_cap = vcpu->arch.mcg_cap;
2162 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2163
2164 switch (msr) {
15c4a640
CO		 2165 case MSR_IA32_P5_MC_ADDR:
2166 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2167 data = 0;
2168 break;
15c4a640 2169 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2170 data = vcpu->arch.mcg_cap;
2171 break;
c7ac679c 2172 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2173 if (!(mcg_cap & MCG_CTL_P))
2174 return 1;
2175 data = vcpu->arch.mcg_ctl;
2176 break;
2177 case MSR_IA32_MCG_STATUS:
2178 data = vcpu->arch.mcg_status;
2179 break;
2180 default:
2181 if (msr >= MSR_IA32_MC0_CTL &&
2182 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2183 u32 offset = msr - MSR_IA32_MC0_CTL;
2184 data = vcpu->arch.mce_banks[offset];
2185 break;
2186 }
2187 return 1;
2188 }
2189 *pdata = data;
2190 return 0;
2191}
2192
55cd8e5a
GN		 2193static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2194{
2195 u64 data = 0;
2196 struct kvm *kvm = vcpu->kvm;
2197
2198 switch (msr) {
2199 case HV_X64_MSR_GUEST_OS_ID:
2200 data = kvm->arch.hv_guest_os_id;
2201 break;
2202 case HV_X64_MSR_HYPERCALL:
2203 data = kvm->arch.hv_hypercall;
2204 break;
2205 default:
a737f256 2206 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2207 return 1;
2208 }
2209
2210 *pdata = data;
2211 return 0;
2212}
2213
2214static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2215{
2216 u64 data = 0;
2217
2218 switch (msr) {
2219 case HV_X64_MSR_VP_INDEX: {
2220 int r;
2221 struct kvm_vcpu *v;
2222 kvm_for_each_vcpu(r, v, vcpu->kvm)
2223 if (v == vcpu)
2224 data = r;
2225 break;
2226 }
10388a07
GN		 2227 case HV_X64_MSR_EOI:
2228 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2229 case HV_X64_MSR_ICR:
2230 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2231 case HV_X64_MSR_TPR:
2232 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2233 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2234 data = vcpu->arch.hv_vapic;
2235 break;
55cd8e5a 2236 default:
a737f256 2237 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2238 return 1;
2239 }
2240 *pdata = data;
2241 return 0;
2242}
2243
890ca9ae
HY		 2244int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2245{
2246 u64 data;
2247
2248 switch (msr) {
890ca9ae 2249 case MSR_IA32_PLATFORM_ID:
15c4a640 2250 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2251 case MSR_IA32_DEBUGCTLMSR:
2252 case MSR_IA32_LASTBRANCHFROMIP:
2253 case MSR_IA32_LASTBRANCHTOIP:
2254 case MSR_IA32_LASTINTFROMIP:
2255 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2256 case MSR_K8_SYSCFG:
2257 case MSR_K7_HWCR:
61a6bd67 2258 case MSR_VM_HSAVE_PA:
9e699624 2259 case MSR_K7_EVNTSEL0:
1f3ee616 2260 case MSR_K7_PERFCTR0:
1fdbd48c 2261 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2262 case MSR_AMD64_NB_CFG:
f7c6d140 2263 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2264 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2265 data = 0;
2266 break;
5753785f
GN		 2267 case MSR_P6_PERFCTR0:
2268 case MSR_P6_PERFCTR1:
2269 case MSR_P6_EVNTSEL0:
2270 case MSR_P6_EVNTSEL1:
2271 if (kvm_pmu_msr(vcpu, msr))
2272 return kvm_pmu_get_msr(vcpu, msr, pdata);
2273 data = 0;
2274 break;
742bc670
MT		 2275 case MSR_IA32_UCODE_REV:
2276 data = 0x100000000ULL;
2277 break;
9ba075a6
AK		 2278 case MSR_MTRRcap:
2279 data = 0x500 | KVM_NR_VAR_MTRR;
2280 break;
2281 case 0x200 ... 0x2ff:
2282 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2283 case 0xcd: /* fsb frequency */
2284 data = 3;
2285 break;
7b914098
JS		 2286 /*
2287 * MSR_EBC_FREQUENCY_ID
2288 * Conservative value valid for even the basic CPU models.
2289 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2290 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2291 * and 266MHz for model 3, or 4. Set Core Clock
2292 * Frequency to System Bus Frequency Ratio to 1 (bits
2293 * 31:24) even though these are only valid for CPU
2294 * models > 2, however guests may end up dividing or
2295 * multiplying by zero otherwise.
2296 */
2297 case MSR_EBC_FREQUENCY_ID:
2298 data = 1 << 24;
2299 break;
15c4a640
CO		 2300 case MSR_IA32_APICBASE:
2301 data = kvm_get_apic_base(vcpu);
2302 break;
0105d1a5
GN		 2303 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2304 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2305 break;
a3e06bbe
LJ		 2306 case MSR_IA32_TSCDEADLINE:
2307 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2308 break;
ba904635
WA		 2309 case MSR_IA32_TSC_ADJUST:
2310 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2311 break;
15c4a640 2312 case MSR_IA32_MISC_ENABLE:
ad312c7c 2313 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2314 break;
847f0ad8
AG		 2315 case MSR_IA32_PERF_STATUS:
2316 /* TSC increment by tick */
2317 data = 1000ULL;
2318 /* CPU multiplier */
2319 data |= (((uint64_t)4ULL) << 40);
2320 break;
15c4a640 2321 case MSR_EFER:
f6801dff 2322 data = vcpu->arch.efer;
15c4a640 2323 break;
18068523 2324 case MSR_KVM_WALL_CLOCK:
11c6bffa 2325 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2326 data = vcpu->kvm->arch.wall_clock;
2327 break;
2328 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2329 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2330 data = vcpu->arch.time;
2331 break;
344d9588
GN		 2332 case MSR_KVM_ASYNC_PF_EN:
2333 data = vcpu->arch.apf.msr_val;
2334 break;
c9aaa895
GC		 2335 case MSR_KVM_STEAL_TIME:
2336 data = vcpu->arch.st.msr_val;
2337 break;
1d92128f
MT		 2338 case MSR_KVM_PV_EOI_EN:
2339 data = vcpu->arch.pv_eoi.msr_val;
2340 break;
890ca9ae
HY		 2341 case MSR_IA32_P5_MC_ADDR:
2342 case MSR_IA32_P5_MC_TYPE:
2343 case MSR_IA32_MCG_CAP:
2344 case MSR_IA32_MCG_CTL:
2345 case MSR_IA32_MCG_STATUS:
2346 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2347 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2348 case MSR_K7_CLK_CTL:
2349 /*
2350 * Provide expected ramp-up count for K7. All other
2351 * are set to zero, indicating minimum divisors for
2352 * every field.
2353 *
2354 * This prevents guest kernels on AMD host with CPU
2355 * type 6, model 8 and higher from exploding due to
2356 * the rdmsr failing.
2357 */
2358 data = 0x20000000;
2359 break;
55cd8e5a
GN		 2360 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2361 if (kvm_hv_msr_partition_wide(msr)) {
2362 int r;
2363 mutex_lock(&vcpu->kvm->lock);
2364 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2365 mutex_unlock(&vcpu->kvm->lock);
2366 return r;
2367 } else
2368 return get_msr_hyperv(vcpu, msr, pdata);
2369 break;
91c9c3ed 2370 case MSR_IA32_BBL_CR_CTL3:
2371 /* This legacy MSR exists but isn't fully documented in current
2372 * silicon. It is however accessed by winxp in very narrow
2373 * scenarios where it sets bit #19, itself documented as
2374 * a "reserved" bit. Best effort attempt to source coherent
2375 * read data here should the balance of the register be
2376 * interpreted by the guest:
2377 *
2378 * L2 cache control register 3: 64GB range, 256KB size,
2379 * enabled, latency 0x1, configured
2380 */
2381 data = 0xbe702111;
2382 break;
2b036c6b
BO		 2383 case MSR_AMD64_OSVW_ID_LENGTH:
2384 if (!guest_cpuid_has_osvw(vcpu))
2385 return 1;
2386 data = vcpu->arch.osvw.length;
2387 break;
2388 case MSR_AMD64_OSVW_STATUS:
2389 if (!guest_cpuid_has_osvw(vcpu))
2390 return 1;
2391 data = vcpu->arch.osvw.status;
2392 break;
15c4a640 2393 default:
f5132b01
GN		 2394 if (kvm_pmu_msr(vcpu, msr))
2395 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2396 if (!ignore_msrs) {
a737f256 2397 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2398 return 1;
2399 } else {
a737f256 2400 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2401 data = 0;
2402 }
2403 break;
15c4a640
CO		 2404 }
2405 *pdata = data;
2406 return 0;
2407}
2408EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2409
313a3dc7
CO		 2410/*
2411 * Read or write a bunch of msrs. All parameters are kernel addresses.
2412 *
2413 * @return number of msrs set successfully.
2414 */
2415static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2416 struct kvm_msr_entry *entries,
2417 int (*do_msr)(struct kvm_vcpu *vcpu,
2418 unsigned index, u64 *data))
2419{
f656ce01 2420 int i, idx;
313a3dc7 2421
f656ce01 2422 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2423 for (i = 0; i < msrs->nmsrs; ++i)
2424 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2425 break;
f656ce01 2426 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2427
313a3dc7
CO		 2428 return i;
2429}
2430
2431/*
2432 * Read or write a bunch of msrs. Parameters are user addresses.
2433 *
2434 * @return number of msrs set successfully.
2435 */
2436static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2437 int (*do_msr)(struct kvm_vcpu *vcpu,
2438 unsigned index, u64 *data),
2439 int writeback)
2440{
2441 struct kvm_msrs msrs;
2442 struct kvm_msr_entry *entries;
2443 int r, n;
2444 unsigned size;
2445
2446 r = -EFAULT;
2447 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2448 goto out;
2449
2450 r = -E2BIG;
2451 if (msrs.nmsrs >= MAX_IO_MSRS)
2452 goto out;
2453
313a3dc7 2454 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2455 entries = memdup_user(user_msrs->entries, size);
2456 if (IS_ERR(entries)) {
2457 r = PTR_ERR(entries);
313a3dc7 2458 goto out;
ff5c2c03 2459 }
313a3dc7
CO		 2460
2461 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2462 if (r < 0)
2463 goto out_free;
2464
2465 r = -EFAULT;
2466 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2467 goto out_free;
2468
2469 r = n;
2470
2471out_free:
7a73c028 2472 kfree(entries);
313a3dc7
CO		 2473out:
2474 return r;
2475}
2476
018d00d2
ZX		 2477int kvm_dev_ioctl_check_extension(long ext)
2478{
2479 int r;
2480
2481 switch (ext) {
2482 case KVM_CAP_IRQCHIP:
2483 case KVM_CAP_HLT:
2484 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2485 case KVM_CAP_SET_TSS_ADDR:
07716717 2486 case KVM_CAP_EXT_CPUID:
c8076604 2487 case KVM_CAP_CLOCKSOURCE:
7837699f 2488 case KVM_CAP_PIT:
a28e4f5a 2489 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2490 case KVM_CAP_MP_STATE:
ed848624 2491 case KVM_CAP_SYNC_MMU:
a355c85c 2492 case KVM_CAP_USER_NMI:
52d939a0 2493 case KVM_CAP_REINJECT_CONTROL:
4925663a 2494 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2495 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2496 case KVM_CAP_IRQFD:
d34e6b17 2497 case KVM_CAP_IOEVENTFD:
c5ff41ce 2498 case KVM_CAP_PIT2:
e9f42757 2499 case KVM_CAP_PIT_STATE2:
b927a3ce 2500 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2501 case KVM_CAP_XEN_HVM:
afbcf7ab 2502 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2503 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2504 case KVM_CAP_HYPERV:
10388a07 2505 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2506 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2507 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2508 case KVM_CAP_DEBUGREGS:
d2be1651 2509 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2510 case KVM_CAP_XSAVE:
344d9588 2511 case KVM_CAP_ASYNC_PF:
92a1f12d 2512 case KVM_CAP_GET_TSC_KHZ:
07700a94 2513 case KVM_CAP_PCI_2_3:
1c0b28c2 2514 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2515 case KVM_CAP_READONLY_MEM:
7a84428a 2516 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2517 r = 1;
2518 break;
542472b5
LV		 2519 case KVM_CAP_COALESCED_MMIO:
2520 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2521 break;
774ead3a
AK		 2522 case KVM_CAP_VAPIC:
2523 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2524 break;
f725230a 2525 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2526 r = KVM_SOFT_MAX_VCPUS;
2527 break;
2528 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2529 r = KVM_MAX_VCPUS;
2530 break;
a988b910 2531 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2532 r = KVM_USER_MEM_SLOTS;
a988b910 2533 break;
a68a6a72
MT		 2534 case KVM_CAP_PV_MMU: /* obsolete */
2535 r = 0;
2f333bcb 2536 break;
62c476c7 2537 case KVM_CAP_IOMMU:
a1b60c1c 2538 r = iommu_present(&pci_bus_type);
62c476c7 2539 break;
890ca9ae
HY		 2540 case KVM_CAP_MCE:
2541 r = KVM_MAX_MCE_BANKS;
2542 break;
2d5b5a66
SY		 2543 case KVM_CAP_XCRS:
2544 r = cpu_has_xsave;
2545 break;
92a1f12d
JR		 2546 case KVM_CAP_TSC_CONTROL:
2547 r = kvm_has_tsc_control;
2548 break;
4d25a066
JK		 2549 case KVM_CAP_TSC_DEADLINE_TIMER:
2550 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2551 break;
018d00d2
ZX		 2552 default:
2553 r = 0;
2554 break;
2555 }
2556 return r;
2557
2558}
2559
043405e1
CO		 2560long kvm_arch_dev_ioctl(struct file *filp,
2561 unsigned int ioctl, unsigned long arg)
2562{
2563 void __user *argp = (void __user *)arg;
2564 long r;
2565
2566 switch (ioctl) {
2567 case KVM_GET_MSR_INDEX_LIST: {
2568 struct kvm_msr_list __user *user_msr_list = argp;
2569 struct kvm_msr_list msr_list;
2570 unsigned n;
2571
2572 r = -EFAULT;
2573 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2574 goto out;
2575 n = msr_list.nmsrs;
2576 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2577 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2578 goto out;
2579 r = -E2BIG;
e125e7b6 2580 if (n < msr_list.nmsrs)
043405e1
CO		 2581 goto out;
2582 r = -EFAULT;
2583 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2584 num_msrs_to_save * sizeof(u32)))
2585 goto out;
e125e7b6 2586 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2587 &emulated_msrs,
2588 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2589 goto out;
2590 r = 0;
2591 break;
2592 }
674eea0f
AK		 2593 case KVM_GET_SUPPORTED_CPUID: {
2594 struct kvm_cpuid2 __user *cpuid_arg = argp;
2595 struct kvm_cpuid2 cpuid;
2596
2597 r = -EFAULT;
2598 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2599 goto out;
2600 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2601 cpuid_arg->entries);
674eea0f
AK		 2602 if (r)
2603 goto out;
2604
2605 r = -EFAULT;
2606 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2607 goto out;
2608 r = 0;
2609 break;
2610 }
890ca9ae
HY		 2611 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2612 u64 mce_cap;
2613
2614 mce_cap = KVM_MCE_CAP_SUPPORTED;
2615 r = -EFAULT;
2616 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2617 goto out;
2618 r = 0;
2619 break;
2620 }
043405e1
CO		 2621 default:
2622 r = -EINVAL;
2623 }
2624out:
2625 return r;
2626}
2627
f5f48ee1
SY		 2628static void wbinvd_ipi(void *garbage)
2629{
2630 wbinvd();
2631}
2632
2633static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2634{
2635 return vcpu->kvm->arch.iommu_domain &&
2636 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2637}
2638
313a3dc7
CO		 2639void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2640{
f5f48ee1
SY		 2641 /* Address WBINVD may be executed by guest */
2642 if (need_emulate_wbinvd(vcpu)) {
2643 if (kvm_x86_ops->has_wbinvd_exit())
2644 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2645 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2646 smp_call_function_single(vcpu->cpu,
2647 wbinvd_ipi, NULL, 1);
2648 }
2649
313a3dc7 2650 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2651
0dd6a6ed
ZA		 2652 /* Apply any externally detected TSC adjustments (due to suspend) */
2653 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2654 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2655 vcpu->arch.tsc_offset_adjustment = 0;
2656 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2657 }
8f6055cb 2658
48434c20 2659 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2660 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2661 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2662 if (tsc_delta < 0)
2663 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2664 if (check_tsc_unstable()) {
b183aa58
ZA		 2665 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2666 vcpu->arch.last_guest_tsc);
2667 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2668 vcpu->arch.tsc_catchup = 1;
c285545f 2669 }
d98d07ca
MT		 2670 /*
2671 * On a host with synchronized TSC, there is no need to update
2672 * kvmclock on vcpu->cpu migration
2673 */
2674 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2675 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2676 if (vcpu->cpu != cpu)
2677 kvm_migrate_timers(vcpu);
e48672fa 2678 vcpu->cpu = cpu;
6b7d7e76 2679 }
c9aaa895
GC		 2680
2681 accumulate_steal_time(vcpu);
2682 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2683}
2684
2685void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2686{
02daab21 2687 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2688 kvm_put_guest_fpu(vcpu);
6f526ec5 2689 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2690}
2691
313a3dc7
CO		 2692static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2693 struct kvm_lapic_state *s)
2694{
5a71785d 2695 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2696 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2697
2698 return 0;
2699}
2700
2701static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2702 struct kvm_lapic_state *s)
2703{
64eb0620 2704 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2705 update_cr8_intercept(vcpu);
313a3dc7
CO		 2706
2707 return 0;
2708}
2709
f77bc6a4
ZX		 2710static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2711 struct kvm_interrupt *irq)
2712{
02cdb50f 2713 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2714 return -EINVAL;
2715 if (irqchip_in_kernel(vcpu->kvm))
2716 return -ENXIO;
f77bc6a4 2717
66fd3f7f 2718 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2719 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2720
f77bc6a4
ZX		 2721 return 0;
2722}
2723
c4abb7c9
JK		 2724static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2725{
c4abb7c9 2726 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2727
2728 return 0;
2729}
2730
b209749f
AK		 2731static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2732 struct kvm_tpr_access_ctl *tac)
2733{
2734 if (tac->flags)
2735 return -EINVAL;
2736 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2737 return 0;
2738}
2739
890ca9ae
HY		 2740static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2741 u64 mcg_cap)
2742{
2743 int r;
2744 unsigned bank_num = mcg_cap & 0xff, bank;
2745
2746 r = -EINVAL;
a9e38c3e 2747 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2748 goto out;
2749 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2750 goto out;
2751 r = 0;
2752 vcpu->arch.mcg_cap = mcg_cap;
2753 /* Init IA32_MCG_CTL to all 1s */
2754 if (mcg_cap & MCG_CTL_P)
2755 vcpu->arch.mcg_ctl = ~(u64)0;
2756 /* Init IA32_MCi_CTL to all 1s */
2757 for (bank = 0; bank < bank_num; bank++)
2758 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2759out:
2760 return r;
2761}
2762
2763static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2764 struct kvm_x86_mce *mce)
2765{
2766 u64 mcg_cap = vcpu->arch.mcg_cap;
2767 unsigned bank_num = mcg_cap & 0xff;
2768 u64 *banks = vcpu->arch.mce_banks;
2769
2770 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2771 return -EINVAL;
2772 /*
2773 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2774 * reporting is disabled
2775 */
2776 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2777 vcpu->arch.mcg_ctl != ~(u64)0)
2778 return 0;
2779 banks += 4 * mce->bank;
2780 /*
2781 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2782 * reporting is disabled for the bank
2783 */
2784 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2785 return 0;
2786 if (mce->status & MCI_STATUS_UC) {
2787 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2788 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2789 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2790 return 0;
2791 }
2792 if (banks[1] & MCI_STATUS_VAL)
2793 mce->status |= MCI_STATUS_OVER;
2794 banks[2] = mce->addr;
2795 banks[3] = mce->misc;
2796 vcpu->arch.mcg_status = mce->mcg_status;
2797 banks[1] = mce->status;
2798 kvm_queue_exception(vcpu, MC_VECTOR);
2799 } else if (!(banks[1] & MCI_STATUS_VAL)
2800 || !(banks[1] & MCI_STATUS_UC)) {
2801 if (banks[1] & MCI_STATUS_VAL)
2802 mce->status |= MCI_STATUS_OVER;
2803 banks[2] = mce->addr;
2804 banks[3] = mce->misc;
2805 banks[1] = mce->status;
2806 } else
2807 banks[1] |= MCI_STATUS_OVER;
2808 return 0;
2809}
2810
3cfc3092
JK		 2811static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2812 struct kvm_vcpu_events *events)
2813{
7460fb4a 2814 process_nmi(vcpu);
03b82a30
JK		 2815 events->exception.injected =
2816 vcpu->arch.exception.pending &&
2817 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2818 events->exception.nr = vcpu->arch.exception.nr;
2819 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2820 events->exception.pad = 0;
3cfc3092
JK		 2821 events->exception.error_code = vcpu->arch.exception.error_code;
2822
03b82a30
JK		 2823 events->interrupt.injected =
2824 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2825 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2826 events->interrupt.soft = 0;
48005f64
JK		 2827 events->interrupt.shadow =
2828 kvm_x86_ops->get_interrupt_shadow(vcpu,
2829 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2830
2831 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2832 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2833 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2834 events->nmi.pad = 0;
3cfc3092 2835
66450a21 2836 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2837
dab4b911 2838 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2839 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2840 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2841}
2842
2843static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2844 struct kvm_vcpu_events *events)
2845{
dab4b911 2846 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2847 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2848 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2849 return -EINVAL;
2850
7460fb4a 2851 process_nmi(vcpu);
3cfc3092
JK		 2852 vcpu->arch.exception.pending = events->exception.injected;
2853 vcpu->arch.exception.nr = events->exception.nr;
2854 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2855 vcpu->arch.exception.error_code = events->exception.error_code;
2856
2857 vcpu->arch.interrupt.pending = events->interrupt.injected;
2858 vcpu->arch.interrupt.nr = events->interrupt.nr;
2859 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2860 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2861 kvm_x86_ops->set_interrupt_shadow(vcpu,
2862 events->interrupt.shadow);
3cfc3092
JK		 2863
2864 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2865 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2866 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2867 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2868
66450a21
JK		 2869 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2870 kvm_vcpu_has_lapic(vcpu))
2871 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2872
3842d135
AK		 2873 kvm_make_request(KVM_REQ_EVENT, vcpu);
2874
3cfc3092
JK		 2875 return 0;
2876}
2877
a1efbe77
JK		 2878static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2879 struct kvm_debugregs *dbgregs)
2880{
a1efbe77
JK		 2881 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2882 dbgregs->dr6 = vcpu->arch.dr6;
2883 dbgregs->dr7 = vcpu->arch.dr7;
2884 dbgregs->flags = 0;
97e69aa6 2885 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2886}
2887
2888static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2889 struct kvm_debugregs *dbgregs)
2890{
2891 if (dbgregs->flags)
2892 return -EINVAL;
2893
a1efbe77
JK		 2894 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2895 vcpu->arch.dr6 = dbgregs->dr6;
2896 vcpu->arch.dr7 = dbgregs->dr7;
2897
a1efbe77
JK		 2898 return 0;
2899}
2900
2d5b5a66
SY		 2901static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2902 struct kvm_xsave *guest_xsave)
2903{
2904 if (cpu_has_xsave)
2905 memcpy(guest_xsave->region,
2906 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2907 xstate_size);
2d5b5a66
SY		 2908 else {
2909 memcpy(guest_xsave->region,
2910 &vcpu->arch.guest_fpu.state->fxsave,
2911 sizeof(struct i387_fxsave_struct));
2912 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2913 XSTATE_FPSSE;
2914 }
2915}
2916
2917static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2918 struct kvm_xsave *guest_xsave)
2919{
2920 u64 xstate_bv =
2921 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2922
2923 if (cpu_has_xsave)
2924 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2925 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2926 else {
2927 if (xstate_bv & ~XSTATE_FPSSE)
2928 return -EINVAL;
2929 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2930 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2931 }
2932 return 0;
2933}
2934
2935static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2936 struct kvm_xcrs *guest_xcrs)
2937{
2938 if (!cpu_has_xsave) {
2939 guest_xcrs->nr_xcrs = 0;
2940 return;
2941 }
2942
2943 guest_xcrs->nr_xcrs = 1;
2944 guest_xcrs->flags = 0;
2945 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2946 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2947}
2948
2949static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2950 struct kvm_xcrs *guest_xcrs)
2951{
2952 int i, r = 0;
2953
2954 if (!cpu_has_xsave)
2955 return -EINVAL;
2956
2957 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2958 return -EINVAL;
2959
2960 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2961 /* Only support XCR0 currently */
2962 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2963 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2964 guest_xcrs->xcrs[0].value);
2965 break;
2966 }
2967 if (r)
2968 r = -EINVAL;
2969 return r;
2970}
2971
1c0b28c2
EM		 2972/*
2973 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2974 * stopped by the hypervisor. This function will be called from the host only.
2975 * EINVAL is returned when the host attempts to set the flag for a guest that
2976 * does not support pv clocks.
2977 */
2978static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2979{
0b79459b 2980 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 2981 return -EINVAL;
51d59c6b 2982 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2983 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2984 return 0;
2985}
2986
313a3dc7
CO		 2987long kvm_arch_vcpu_ioctl(struct file *filp,
2988 unsigned int ioctl, unsigned long arg)
2989{
2990 struct kvm_vcpu *vcpu = filp->private_data;
2991 void __user *argp = (void __user *)arg;
2992 int r;
d1ac91d8
AK		 2993 union {
2994 struct kvm_lapic_state *lapic;
2995 struct kvm_xsave *xsave;
2996 struct kvm_xcrs *xcrs;
2997 void *buffer;
2998 } u;
2999
3000 u.buffer = NULL;
313a3dc7
CO		 3001 switch (ioctl) {
3002 case KVM_GET_LAPIC: {
2204ae3c
MT		 3003 r = -EINVAL;
3004 if (!vcpu->arch.apic)
3005 goto out;
d1ac91d8 3006 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3007
b772ff36 3008 r = -ENOMEM;
d1ac91d8 3009 if (!u.lapic)
b772ff36 3010 goto out;
d1ac91d8 3011 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3012 if (r)
3013 goto out;
3014 r = -EFAULT;
d1ac91d8 3015 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3016 goto out;
3017 r = 0;
3018 break;
3019 }
3020 case KVM_SET_LAPIC: {
2204ae3c
MT		 3021 r = -EINVAL;
3022 if (!vcpu->arch.apic)
3023 goto out;
ff5c2c03 3024 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3025 if (IS_ERR(u.lapic))
3026 return PTR_ERR(u.lapic);
ff5c2c03 3027
d1ac91d8 3028 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3029 break;
3030 }
f77bc6a4
ZX		 3031 case KVM_INTERRUPT: {
3032 struct kvm_interrupt irq;
3033
3034 r = -EFAULT;
3035 if (copy_from_user(&irq, argp, sizeof irq))
3036 goto out;
3037 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3038 break;
3039 }
c4abb7c9
JK		 3040 case KVM_NMI: {
3041 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3042 break;
3043 }
313a3dc7
CO		 3044 case KVM_SET_CPUID: {
3045 struct kvm_cpuid __user *cpuid_arg = argp;
3046 struct kvm_cpuid cpuid;
3047
3048 r = -EFAULT;
3049 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3050 goto out;
3051 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3052 break;
3053 }
07716717
DK		 3054 case KVM_SET_CPUID2: {
3055 struct kvm_cpuid2 __user *cpuid_arg = argp;
3056 struct kvm_cpuid2 cpuid;
3057
3058 r = -EFAULT;
3059 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3060 goto out;
3061 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3062 cpuid_arg->entries);
07716717
DK		 3063 break;
3064 }
3065 case KVM_GET_CPUID2: {
3066 struct kvm_cpuid2 __user *cpuid_arg = argp;
3067 struct kvm_cpuid2 cpuid;
3068
3069 r = -EFAULT;
3070 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3071 goto out;
3072 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3073 cpuid_arg->entries);
07716717
DK		 3074 if (r)
3075 goto out;
3076 r = -EFAULT;
3077 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3078 goto out;
3079 r = 0;
3080 break;
3081 }
313a3dc7
CO		 3082 case KVM_GET_MSRS:
3083 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3084 break;
3085 case KVM_SET_MSRS:
3086 r = msr_io(vcpu, argp, do_set_msr, 0);
3087 break;
b209749f
AK		 3088 case KVM_TPR_ACCESS_REPORTING: {
3089 struct kvm_tpr_access_ctl tac;
3090
3091 r = -EFAULT;
3092 if (copy_from_user(&tac, argp, sizeof tac))
3093 goto out;
3094 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3095 if (r)
3096 goto out;
3097 r = -EFAULT;
3098 if (copy_to_user(argp, &tac, sizeof tac))
3099 goto out;
3100 r = 0;
3101 break;
3102 };
b93463aa
AK		 3103 case KVM_SET_VAPIC_ADDR: {
3104 struct kvm_vapic_addr va;
3105
3106 r = -EINVAL;
3107 if (!irqchip_in_kernel(vcpu->kvm))
3108 goto out;
3109 r = -EFAULT;
3110 if (copy_from_user(&va, argp, sizeof va))
3111 goto out;
3112 r = 0;
3113 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3114 break;
3115 }
890ca9ae
HY		 3116 case KVM_X86_SETUP_MCE: {
3117 u64 mcg_cap;
3118
3119 r = -EFAULT;
3120 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3121 goto out;
3122 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3123 break;
3124 }
3125 case KVM_X86_SET_MCE: {
3126 struct kvm_x86_mce mce;
3127
3128 r = -EFAULT;
3129 if (copy_from_user(&mce, argp, sizeof mce))
3130 goto out;
3131 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3132 break;
3133 }
3cfc3092
JK		 3134 case KVM_GET_VCPU_EVENTS: {
3135 struct kvm_vcpu_events events;
3136
3137 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3138
3139 r = -EFAULT;
3140 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3141 break;
3142 r = 0;
3143 break;
3144 }
3145 case KVM_SET_VCPU_EVENTS: {
3146 struct kvm_vcpu_events events;
3147
3148 r = -EFAULT;
3149 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3150 break;
3151
3152 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3153 break;
3154 }
a1efbe77
JK		 3155 case KVM_GET_DEBUGREGS: {
3156 struct kvm_debugregs dbgregs;
3157
3158 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3159
3160 r = -EFAULT;
3161 if (copy_to_user(argp, &dbgregs,
3162 sizeof(struct kvm_debugregs)))
3163 break;
3164 r = 0;
3165 break;
3166 }
3167 case KVM_SET_DEBUGREGS: {
3168 struct kvm_debugregs dbgregs;
3169
3170 r = -EFAULT;
3171 if (copy_from_user(&dbgregs, argp,
3172 sizeof(struct kvm_debugregs)))
3173 break;
3174
3175 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3176 break;
3177 }
2d5b5a66 3178 case KVM_GET_XSAVE: {
d1ac91d8 3179 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3180 r = -ENOMEM;
d1ac91d8 3181 if (!u.xsave)
2d5b5a66
SY		 3182 break;
3183
d1ac91d8 3184 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3185
3186 r = -EFAULT;
d1ac91d8 3187 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3188 break;
3189 r = 0;
3190 break;
3191 }
3192 case KVM_SET_XSAVE: {
ff5c2c03 3193 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3194 if (IS_ERR(u.xsave))
3195 return PTR_ERR(u.xsave);
2d5b5a66 3196
d1ac91d8 3197 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3198 break;
3199 }
3200 case KVM_GET_XCRS: {
d1ac91d8 3201 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3202 r = -ENOMEM;
d1ac91d8 3203 if (!u.xcrs)
2d5b5a66
SY		 3204 break;
3205
d1ac91d8 3206 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3207
3208 r = -EFAULT;
d1ac91d8 3209 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3210 sizeof(struct kvm_xcrs)))
3211 break;
3212 r = 0;
3213 break;
3214 }
3215 case KVM_SET_XCRS: {
ff5c2c03 3216 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3217 if (IS_ERR(u.xcrs))
3218 return PTR_ERR(u.xcrs);
2d5b5a66 3219
d1ac91d8 3220 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3221 break;
3222 }
92a1f12d
JR		 3223 case KVM_SET_TSC_KHZ: {
3224 u32 user_tsc_khz;
3225
3226 r = -EINVAL;
92a1f12d
JR		 3227 user_tsc_khz = (u32)arg;
3228
3229 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3230 goto out;
3231
cc578287
ZA		 3232 if (user_tsc_khz == 0)
3233 user_tsc_khz = tsc_khz;
3234
3235 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3236
3237 r = 0;
3238 goto out;
3239 }
3240 case KVM_GET_TSC_KHZ: {
cc578287 3241 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3242 goto out;
3243 }
1c0b28c2
EM		 3244 case KVM_KVMCLOCK_CTRL: {
3245 r = kvm_set_guest_paused(vcpu);
3246 goto out;
3247 }
313a3dc7
CO		 3248 default:
3249 r = -EINVAL;
3250 }
3251out:
d1ac91d8 3252 kfree(u.buffer);
313a3dc7
CO		 3253 return r;
3254}
3255
5b1c1493
CO		 3256int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3257{
3258 return VM_FAULT_SIGBUS;
3259}
3260
1fe779f8
CO		 3261static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3262{
3263 int ret;
3264
3265 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3266 return -EINVAL;
1fe779f8
CO		 3267 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3268 return ret;
3269}
3270
b927a3ce
SY		 3271static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3272 u64 ident_addr)
3273{
3274 kvm->arch.ept_identity_map_addr = ident_addr;
3275 return 0;
3276}
3277
1fe779f8
CO		 3278static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3279 u32 kvm_nr_mmu_pages)
3280{
3281 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3282 return -EINVAL;
3283
79fac95e 3284 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3285
3286 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3287 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3288
79fac95e 3289 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3290 return 0;
3291}
3292
3293static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3294{
39de71ec 3295 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3296}
3297
1fe779f8
CO		 3298static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3299{
3300 int r;
3301
3302 r = 0;
3303 switch (chip->chip_id) {
3304 case KVM_IRQCHIP_PIC_MASTER:
3305 memcpy(&chip->chip.pic,
3306 &pic_irqchip(kvm)->pics[0],
3307 sizeof(struct kvm_pic_state));
3308 break;
3309 case KVM_IRQCHIP_PIC_SLAVE:
3310 memcpy(&chip->chip.pic,
3311 &pic_irqchip(kvm)->pics[1],
3312 sizeof(struct kvm_pic_state));
3313 break;
3314 case KVM_IRQCHIP_IOAPIC:
eba0226b 3315 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3316 break;
3317 default:
3318 r = -EINVAL;
3319 break;
3320 }
3321 return r;
3322}
3323
3324static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3325{
3326 int r;
3327
3328 r = 0;
3329 switch (chip->chip_id) {
3330 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3331 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3332 memcpy(&pic_irqchip(kvm)->pics[0],
3333 &chip->chip.pic,
3334 sizeof(struct kvm_pic_state));
f4f51050 3335 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3336 break;
3337 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3338 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3339 memcpy(&pic_irqchip(kvm)->pics[1],
3340 &chip->chip.pic,
3341 sizeof(struct kvm_pic_state));
f4f51050 3342 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3343 break;
3344 case KVM_IRQCHIP_IOAPIC:
eba0226b 3345 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3346 break;
3347 default:
3348 r = -EINVAL;
3349 break;
3350 }
3351 kvm_pic_update_irq(pic_irqchip(kvm));
3352 return r;
3353}
3354
e0f63cb9
SY		 3355static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3356{
3357 int r = 0;
3358
894a9c55 3359 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3360 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3361 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3362 return r;
3363}
3364
3365static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3366{
3367 int r = 0;
3368
894a9c55 3369 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3370 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3371 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3372 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3373 return r;
3374}
3375
3376static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3377{
3378 int r = 0;
3379
3380 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3381 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3382 sizeof(ps->channels));
3383 ps->flags = kvm->arch.vpit->pit_state.flags;
3384 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3385 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3386 return r;
3387}
3388
3389static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3390{
3391 int r = 0, start = 0;
3392 u32 prev_legacy, cur_legacy;
3393 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3394 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3395 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3396 if (!prev_legacy && cur_legacy)
3397 start = 1;
3398 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3399 sizeof(kvm->arch.vpit->pit_state.channels));
3400 kvm->arch.vpit->pit_state.flags = ps->flags;
3401 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3402 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3403 return r;
3404}
3405
52d939a0
MT		 3406static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3407 struct kvm_reinject_control *control)
3408{
3409 if (!kvm->arch.vpit)
3410 return -ENXIO;
894a9c55 3411 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3412 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3413 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3414 return 0;
3415}
3416
95d4c16c 3417/**
60c34612
TY		 3418 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3419 * @kvm: kvm instance
3420 * @log: slot id and address to which we copy the log
95d4c16c 3421 *
60c34612
TY		 3422 * We need to keep it in mind that VCPU threads can write to the bitmap
3423 * concurrently. So, to avoid losing data, we keep the following order for
3424 * each bit:
95d4c16c 3425 *
60c34612
TY		 3426 * 1. Take a snapshot of the bit and clear it if needed.
3427 * 2. Write protect the corresponding page.
3428 * 3. Flush TLB's if needed.
3429 * 4. Copy the snapshot to the userspace.
95d4c16c 3430 *
60c34612
TY		 3431 * Between 2 and 3, the guest may write to the page using the remaining TLB
3432 * entry. This is not a problem because the page will be reported dirty at
3433 * step 4 using the snapshot taken before and step 3 ensures that successive
3434 * writes will be logged for the next call.
5bb064dc 3435 */
60c34612 3436int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3437{
7850ac54 3438 int r;
5bb064dc 3439 struct kvm_memory_slot *memslot;
60c34612
TY		 3440 unsigned long n, i;
3441 unsigned long *dirty_bitmap;
3442 unsigned long *dirty_bitmap_buffer;
3443 bool is_dirty = false;
5bb064dc 3444
79fac95e 3445 mutex_lock(&kvm->slots_lock);
5bb064dc 3446
b050b015 3447 r = -EINVAL;
bbacc0c1 3448 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3449 goto out;
3450
28a37544 3451 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3452
3453 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3454 r = -ENOENT;
60c34612 3455 if (!dirty_bitmap)
b050b015
MT		 3456 goto out;
3457
87bf6e7d 3458 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3459
60c34612
TY		 3460 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3461 memset(dirty_bitmap_buffer, 0, n);
b050b015 3462
60c34612 3463 spin_lock(&kvm->mmu_lock);
b050b015 3464
60c34612
TY		 3465 for (i = 0; i < n / sizeof(long); i++) {
3466 unsigned long mask;
3467 gfn_t offset;
cdfca7b3 3468
60c34612
TY		 3469 if (!dirty_bitmap[i])
3470 continue;
b050b015 3471
60c34612 3472 is_dirty = true;
914ebccd 3473
60c34612
TY		 3474 mask = xchg(&dirty_bitmap[i], 0);
3475 dirty_bitmap_buffer[i] = mask;
edde99ce 3476
60c34612
TY		 3477 offset = i * BITS_PER_LONG;
3478 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3479 }
60c34612
TY		 3480 if (is_dirty)
3481 kvm_flush_remote_tlbs(kvm);
3482
3483 spin_unlock(&kvm->mmu_lock);
3484
3485 r = -EFAULT;
3486 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3487 goto out;
b050b015 3488
5bb064dc
ZX		 3489 r = 0;
3490out:
79fac95e 3491 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3492 return r;
3493}
3494
aa2fbe6d
YZ		 3495int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3496 bool line_status)
23d43cf9
CD		 3497{
3498 if (!irqchip_in_kernel(kvm))
3499 return -ENXIO;
3500
3501 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3502 irq_event->irq, irq_event->level,
3503 line_status);
23d43cf9
CD		 3504 return 0;
3505}
3506
1fe779f8
CO		 3507long kvm_arch_vm_ioctl(struct file *filp,
3508 unsigned int ioctl, unsigned long arg)
3509{
3510 struct kvm *kvm = filp->private_data;
3511 void __user *argp = (void __user *)arg;
367e1319 3512 int r = -ENOTTY;
f0d66275
DH		 3513 /*
3514 * This union makes it completely explicit to gcc-3.x
3515 * that these two variables' stack usage should be
3516 * combined, not added together.
3517 */
3518 union {
3519 struct kvm_pit_state ps;
e9f42757 3520 struct kvm_pit_state2 ps2;
c5ff41ce 3521 struct kvm_pit_config pit_config;
f0d66275 3522 } u;
1fe779f8
CO		 3523
3524 switch (ioctl) {
3525 case KVM_SET_TSS_ADDR:
3526 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3527 break;
b927a3ce
SY		 3528 case KVM_SET_IDENTITY_MAP_ADDR: {
3529 u64 ident_addr;
3530
3531 r = -EFAULT;
3532 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3533 goto out;
3534 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3535 break;
3536 }
1fe779f8
CO		 3537 case KVM_SET_NR_MMU_PAGES:
3538 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3539 break;
3540 case KVM_GET_NR_MMU_PAGES:
3541 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3542 break;
3ddea128
MT		 3543 case KVM_CREATE_IRQCHIP: {
3544 struct kvm_pic *vpic;
3545
3546 mutex_lock(&kvm->lock);
3547 r = -EEXIST;
3548 if (kvm->arch.vpic)
3549 goto create_irqchip_unlock;
3e515705
AK		 3550 r = -EINVAL;
3551 if (atomic_read(&kvm->online_vcpus))
3552 goto create_irqchip_unlock;
1fe779f8 3553 r = -ENOMEM;
3ddea128
MT		 3554 vpic = kvm_create_pic(kvm);
3555 if (vpic) {
1fe779f8
CO		 3556 r = kvm_ioapic_init(kvm);
3557 if (r) {
175504cd 3558 mutex_lock(&kvm->slots_lock);
72bb2fcd 3559 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3560 &vpic->dev_master);
3561 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3562 &vpic->dev_slave);
3563 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3564 &vpic->dev_eclr);
175504cd 3565 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3566 kfree(vpic);
3567 goto create_irqchip_unlock;
1fe779f8
CO		 3568 }
3569 } else
3ddea128
MT		 3570 goto create_irqchip_unlock;
3571 smp_wmb();
3572 kvm->arch.vpic = vpic;
3573 smp_wmb();
399ec807
AK		 3574 r = kvm_setup_default_irq_routing(kvm);
3575 if (r) {
175504cd 3576 mutex_lock(&kvm->slots_lock);
3ddea128 3577 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3578 kvm_ioapic_destroy(kvm);
3579 kvm_destroy_pic(kvm);
3ddea128 3580 mutex_unlock(&kvm->irq_lock);
175504cd 3581 mutex_unlock(&kvm->slots_lock);
399ec807 3582 }
3ddea128
MT		 3583 create_irqchip_unlock:
3584 mutex_unlock(&kvm->lock);
1fe779f8 3585 break;
3ddea128 3586 }
7837699f 3587 case KVM_CREATE_PIT:
c5ff41ce
JK		 3588 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3589 goto create_pit;
3590 case KVM_CREATE_PIT2:
3591 r = -EFAULT;
3592 if (copy_from_user(&u.pit_config, argp,
3593 sizeof(struct kvm_pit_config)))
3594 goto out;
3595 create_pit:
79fac95e 3596 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3597 r = -EEXIST;
3598 if (kvm->arch.vpit)
3599 goto create_pit_unlock;
7837699f 3600 r = -ENOMEM;
c5ff41ce 3601 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3602 if (kvm->arch.vpit)
3603 r = 0;
269e05e4 3604 create_pit_unlock:
79fac95e 3605 mutex_unlock(&kvm->slots_lock);
7837699f 3606 break;
1fe779f8
CO		 3607 case KVM_GET_IRQCHIP: {
3608 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3609 struct kvm_irqchip *chip;
1fe779f8 3610
ff5c2c03
SL		 3611 chip = memdup_user(argp, sizeof(*chip));
3612 if (IS_ERR(chip)) {
3613 r = PTR_ERR(chip);
1fe779f8 3614 goto out;
ff5c2c03
SL		 3615 }
3616
1fe779f8
CO		 3617 r = -ENXIO;
3618 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3619 goto get_irqchip_out;
3620 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3621 if (r)
f0d66275 3622 goto get_irqchip_out;
1fe779f8 3623 r = -EFAULT;
f0d66275
DH		 3624 if (copy_to_user(argp, chip, sizeof *chip))
3625 goto get_irqchip_out;
1fe779f8 3626 r = 0;
f0d66275
DH		 3627 get_irqchip_out:
3628 kfree(chip);
1fe779f8
CO		 3629 break;
3630 }
3631 case KVM_SET_IRQCHIP: {
3632 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3633 struct kvm_irqchip *chip;
1fe779f8 3634
ff5c2c03
SL		 3635 chip = memdup_user(argp, sizeof(*chip));
3636 if (IS_ERR(chip)) {
3637 r = PTR_ERR(chip);
1fe779f8 3638 goto out;
ff5c2c03
SL		 3639 }
3640
1fe779f8
CO		 3641 r = -ENXIO;
3642 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3643 goto set_irqchip_out;
3644 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3645 if (r)
f0d66275 3646 goto set_irqchip_out;
1fe779f8 3647 r = 0;
f0d66275
DH		 3648 set_irqchip_out:
3649 kfree(chip);
1fe779f8
CO		 3650 break;
3651 }
e0f63cb9 3652 case KVM_GET_PIT: {
e0f63cb9 3653 r = -EFAULT;
f0d66275 3654 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3655 goto out;
3656 r = -ENXIO;
3657 if (!kvm->arch.vpit)
3658 goto out;
f0d66275 3659 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3660 if (r)
3661 goto out;
3662 r = -EFAULT;
f0d66275 3663 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3664 goto out;
3665 r = 0;
3666 break;
3667 }
3668 case KVM_SET_PIT: {
e0f63cb9 3669 r = -EFAULT;
f0d66275 3670 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3671 goto out;
3672 r = -ENXIO;
3673 if (!kvm->arch.vpit)
3674 goto out;
f0d66275 3675 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3676 break;
3677 }
e9f42757
BK		 3678 case KVM_GET_PIT2: {
3679 r = -ENXIO;
3680 if (!kvm->arch.vpit)
3681 goto out;
3682 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3683 if (r)
3684 goto out;
3685 r = -EFAULT;
3686 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3687 goto out;
3688 r = 0;
3689 break;
3690 }
3691 case KVM_SET_PIT2: {
3692 r = -EFAULT;
3693 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3694 goto out;
3695 r = -ENXIO;
3696 if (!kvm->arch.vpit)
3697 goto out;
3698 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3699 break;
3700 }
52d939a0
MT		 3701 case KVM_REINJECT_CONTROL: {
3702 struct kvm_reinject_control control;
3703 r = -EFAULT;
3704 if (copy_from_user(&control, argp, sizeof(control)))
3705 goto out;
3706 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3707 break;
3708 }
ffde22ac
ES		 3709 case KVM_XEN_HVM_CONFIG: {
3710 r = -EFAULT;
3711 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3712 sizeof(struct kvm_xen_hvm_config)))
3713 goto out;
3714 r = -EINVAL;
3715 if (kvm->arch.xen_hvm_config.flags)
3716 goto out;
3717 r = 0;
3718 break;
3719 }
afbcf7ab 3720 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3721 struct kvm_clock_data user_ns;
3722 u64 now_ns;
3723 s64 delta;
3724
3725 r = -EFAULT;
3726 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3727 goto out;
3728
3729 r = -EINVAL;
3730 if (user_ns.flags)
3731 goto out;
3732
3733 r = 0;
395c6b0a 3734 local_irq_disable();
759379dd 3735 now_ns = get_kernel_ns();
afbcf7ab 3736 delta = user_ns.clock - now_ns;
395c6b0a 3737 local_irq_enable();
afbcf7ab
GC		 3738 kvm->arch.kvmclock_offset = delta;
3739 break;
3740 }
3741 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3742 struct kvm_clock_data user_ns;
3743 u64 now_ns;
3744
395c6b0a 3745 local_irq_disable();
759379dd 3746 now_ns = get_kernel_ns();
afbcf7ab 3747 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3748 local_irq_enable();
afbcf7ab 3749 user_ns.flags = 0;
97e69aa6 3750 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3751
3752 r = -EFAULT;
3753 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3754 goto out;
3755 r = 0;
3756 break;
3757 }
3758
1fe779f8
CO		 3759 default:
3760 ;
3761 }
3762out:
3763 return r;
3764}
3765
a16b043c 3766static void kvm_init_msr_list(void)
043405e1
CO		 3767{
3768 u32 dummy[2];
3769 unsigned i, j;
3770
e3267cbb
GC		 3771 /* skip the first msrs in the list. KVM-specific */
3772 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3773 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3774 continue;
3775 if (j < i)
3776 msrs_to_save[j] = msrs_to_save[i];
3777 j++;
3778 }
3779 num_msrs_to_save = j;
3780}
3781
bda9020e
MT		 3782static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3783 const void *v)
bbd9b64e 3784{
70252a10
AK		 3785 int handled = 0;
3786 int n;
3787
3788 do {
3789 n = min(len, 8);
3790 if (!(vcpu->arch.apic &&
3791 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3792 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3793 break;
3794 handled += n;
3795 addr += n;
3796 len -= n;
3797 v += n;
3798 } while (len);
bbd9b64e 3799
70252a10 3800 return handled;
bbd9b64e
CO		 3801}
3802
bda9020e 3803static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3804{
70252a10
AK		 3805 int handled = 0;
3806 int n;
3807
3808 do {
3809 n = min(len, 8);
3810 if (!(vcpu->arch.apic &&
3811 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3812 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3813 break;
3814 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3815 handled += n;
3816 addr += n;
3817 len -= n;
3818 v += n;
3819 } while (len);
bbd9b64e 3820
70252a10 3821 return handled;
bbd9b64e
CO		 3822}
3823
2dafc6c2
GN		 3824static void kvm_set_segment(struct kvm_vcpu *vcpu,
3825 struct kvm_segment *var, int seg)
3826{
3827 kvm_x86_ops->set_segment(vcpu, var, seg);
3828}
3829
3830void kvm_get_segment(struct kvm_vcpu *vcpu,
3831 struct kvm_segment *var, int seg)
3832{
3833 kvm_x86_ops->get_segment(vcpu, var, seg);
3834}
3835
e459e322 3836gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3837{
3838 gpa_t t_gpa;
ab9ae313 3839 struct x86_exception exception;
02f59dc9
JR		 3840
3841 BUG_ON(!mmu_is_nested(vcpu));
3842
3843 /* NPT walks are always user-walks */
3844 access |= PFERR_USER_MASK;
ab9ae313 3845 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3846
3847 return t_gpa;
3848}
3849
ab9ae313
AK		 3850gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3851 struct x86_exception *exception)
1871c602
GN		 3852{
3853 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3854 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3855}
3856
ab9ae313
AK		 3857 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3858 struct x86_exception *exception)
1871c602
GN		 3859{
3860 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3861 access |= PFERR_FETCH_MASK;
ab9ae313 3862 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3863}
3864
ab9ae313
AK		 3865gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3866 struct x86_exception *exception)
1871c602
GN		 3867{
3868 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3869 access |= PFERR_WRITE_MASK;
ab9ae313 3870 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3871}
3872
3873/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3874gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3875 struct x86_exception *exception)
1871c602 3876{
ab9ae313 3877 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3878}
3879
3880static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3881 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3882 struct x86_exception *exception)
bbd9b64e
CO		 3883{
3884 void *data = val;
10589a46 3885 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3886
3887 while (bytes) {
14dfe855 3888 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3889 exception);
bbd9b64e 3890 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3891 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3892 int ret;
3893
bcc55cba 3894 if (gpa == UNMAPPED_GVA)
ab9ae313 3895 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3896 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3897 if (ret < 0) {
c3cd7ffa 3898 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3899 goto out;
3900 }
bbd9b64e 3901
77c2002e
IE		 3902 bytes -= toread;
3903 data += toread;
3904 addr += toread;
bbd9b64e 3905 }
10589a46 3906out:
10589a46 3907 return r;
bbd9b64e 3908}
77c2002e 3909
1871c602 3910/* used for instruction fetching */
0f65dd70
AK		 3911static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3912 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3913 struct x86_exception *exception)
1871c602 3914{
0f65dd70 3915 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3916 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3917
1871c602 3918 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3919 access | PFERR_FETCH_MASK,
3920 exception);
1871c602
GN		 3921}
3922
064aea77 3923int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3924 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3925 struct x86_exception *exception)
1871c602 3926{
0f65dd70 3927 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3928 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3929
1871c602 3930 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3931 exception);
1871c602 3932}
064aea77 3933EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3934
0f65dd70
AK		 3935static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3936 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3937 struct x86_exception *exception)
1871c602 3938{
0f65dd70 3939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3940 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3941}
3942
6a4d7550 3943int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3944 gva_t addr, void *val,
2dafc6c2 3945 unsigned int bytes,
bcc55cba 3946 struct x86_exception *exception)
77c2002e 3947{
0f65dd70 3948 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3949 void *data = val;
3950 int r = X86EMUL_CONTINUE;
3951
3952 while (bytes) {
14dfe855
JR		 3953 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3954 PFERR_WRITE_MASK,
ab9ae313 3955 exception);
77c2002e
IE		 3956 unsigned offset = addr & (PAGE_SIZE-1);
3957 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3958 int ret;
3959
bcc55cba 3960 if (gpa == UNMAPPED_GVA)
ab9ae313 3961 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3962 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3963 if (ret < 0) {
c3cd7ffa 3964 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3965 goto out;
3966 }
3967
3968 bytes -= towrite;
3969 data += towrite;
3970 addr += towrite;
3971 }
3972out:
3973 return r;
3974}
6a4d7550 3975EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3976
af7cc7d1
XG		 3977static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3978 gpa_t *gpa, struct x86_exception *exception,
3979 bool write)
3980{
97d64b78
AK		 3981 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3982 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3983
97d64b78
AK		 3984 if (vcpu_match_mmio_gva(vcpu, gva)
3985 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3986 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3987 (gva & (PAGE_SIZE - 1));
4f022648 3988 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3989 return 1;
3990 }
3991
af7cc7d1
XG		 3992 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3993
3994 if (*gpa == UNMAPPED_GVA)
3995 return -1;
3996
3997 /* For APIC access vmexit */
3998 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3999 return 1;
4000
4f022648
XG		 4001 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4002 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4003 return 1;
4f022648 4004 }
bebb106a 4005
af7cc7d1
XG		 4006 return 0;
4007}
4008
3200f405 4009int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4010 const void *val, int bytes)
bbd9b64e
CO		 4011{
4012 int ret;
4013
4014 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4015 if (ret < 0)
bbd9b64e 4016 return 0;
f57f2ef5 4017 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4018 return 1;
4019}
4020
77d197b2
XG		 4021struct read_write_emulator_ops {
4022 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4023 int bytes);
4024 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4025 void *val, int bytes);
4026 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4027 int bytes, void *val);
4028 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4029 void *val, int bytes);
4030 bool write;
4031};
4032
4033static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4034{
4035 if (vcpu->mmio_read_completed) {
77d197b2 4036 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4037 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4038 vcpu->mmio_read_completed = 0;
4039 return 1;
4040 }
4041
4042 return 0;
4043}
4044
4045static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4046 void *val, int bytes)
4047{
4048 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4049}
4050
4051static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4052 void *val, int bytes)
4053{
4054 return emulator_write_phys(vcpu, gpa, val, bytes);
4055}
4056
4057static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4058{
4059 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4060 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4061}
4062
4063static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4064 void *val, int bytes)
4065{
4066 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4067 return X86EMUL_IO_NEEDED;
4068}
4069
4070static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4071 void *val, int bytes)
4072{
f78146b0
AK		 4073 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4074
87da7e66 4075 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4076 return X86EMUL_CONTINUE;
4077}
4078
0fbe9b0b 4079static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4080 .read_write_prepare = read_prepare,
4081 .read_write_emulate = read_emulate,
4082 .read_write_mmio = vcpu_mmio_read,
4083 .read_write_exit_mmio = read_exit_mmio,
4084};
4085
0fbe9b0b 4086static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4087 .read_write_emulate = write_emulate,
4088 .read_write_mmio = write_mmio,
4089 .read_write_exit_mmio = write_exit_mmio,
4090 .write = true,
4091};
4092
22388a3c
XG		 4093static int emulator_read_write_onepage(unsigned long addr, void *val,
4094 unsigned int bytes,
4095 struct x86_exception *exception,
4096 struct kvm_vcpu *vcpu,
0fbe9b0b 4097 const struct read_write_emulator_ops *ops)
bbd9b64e 4098{
af7cc7d1
XG		 4099 gpa_t gpa;
4100 int handled, ret;
22388a3c 4101 bool write = ops->write;
f78146b0 4102 struct kvm_mmio_fragment *frag;
10589a46 4103
22388a3c 4104 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4105
af7cc7d1 4106 if (ret < 0)
bbd9b64e 4107 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4108
4109 /* For APIC access vmexit */
af7cc7d1 4110 if (ret)
bbd9b64e
CO		 4111 goto mmio;
4112
22388a3c 4113 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4114 return X86EMUL_CONTINUE;
4115
4116mmio:
4117 /*
4118 * Is this MMIO handled locally?
4119 */
22388a3c 4120 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4121 if (handled == bytes)
bbd9b64e 4122 return X86EMUL_CONTINUE;
bbd9b64e 4123
70252a10
AK		 4124 gpa += handled;
4125 bytes -= handled;
4126 val += handled;
4127
87da7e66
XG		 4128 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4129 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4130 frag->gpa = gpa;
4131 frag->data = val;
4132 frag->len = bytes;
f78146b0 4133 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4134}
4135
22388a3c
XG		 4136int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4137 void *val, unsigned int bytes,
4138 struct x86_exception *exception,
0fbe9b0b 4139 const struct read_write_emulator_ops *ops)
bbd9b64e 4140{
0f65dd70 4141 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4142 gpa_t gpa;
4143 int rc;
4144
4145 if (ops->read_write_prepare &&
4146 ops->read_write_prepare(vcpu, val, bytes))
4147 return X86EMUL_CONTINUE;
4148
4149 vcpu->mmio_nr_fragments = 0;
0f65dd70 4150
bbd9b64e
CO		 4151 /* Crossing a page boundary? */
4152 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4153 int now;
bbd9b64e
CO		 4154
4155 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4156 rc = emulator_read_write_onepage(addr, val, now, exception,
4157 vcpu, ops);
4158
bbd9b64e
CO		 4159 if (rc != X86EMUL_CONTINUE)
4160 return rc;
4161 addr += now;
4162 val += now;
4163 bytes -= now;
4164 }
22388a3c 4165
f78146b0
AK		 4166 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4167 vcpu, ops);
4168 if (rc != X86EMUL_CONTINUE)
4169 return rc;
4170
4171 if (!vcpu->mmio_nr_fragments)
4172 return rc;
4173
4174 gpa = vcpu->mmio_fragments[0].gpa;
4175
4176 vcpu->mmio_needed = 1;
4177 vcpu->mmio_cur_fragment = 0;
4178
87da7e66 4179 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4180 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4181 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4182 vcpu->run->mmio.phys_addr = gpa;
4183
4184 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4185}
4186
4187static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4188 unsigned long addr,
4189 void *val,
4190 unsigned int bytes,
4191 struct x86_exception *exception)
4192{
4193 return emulator_read_write(ctxt, addr, val, bytes,
4194 exception, &read_emultor);
4195}
4196
4197int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4198 unsigned long addr,
4199 const void *val,
4200 unsigned int bytes,
4201 struct x86_exception *exception)
4202{
4203 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4204 exception, &write_emultor);
bbd9b64e 4205}
bbd9b64e 4206
daea3e73
AK		 4207#define CMPXCHG_TYPE(t, ptr, old, new) \
4208 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4209
4210#ifdef CONFIG_X86_64
4211# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4212#else
4213# define CMPXCHG64(ptr, old, new) \
9749a6c0 4214 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4215#endif
4216
0f65dd70
AK		 4217static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4218 unsigned long addr,
bbd9b64e
CO		 4219 const void *old,
4220 const void *new,
4221 unsigned int bytes,
0f65dd70 4222 struct x86_exception *exception)
bbd9b64e 4223{
0f65dd70 4224 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4225 gpa_t gpa;
4226 struct page *page;
4227 char *kaddr;
4228 bool exchanged;
2bacc55c 4229
daea3e73
AK		 4230 /* guests cmpxchg8b have to be emulated atomically */
4231 if (bytes > 8 || (bytes & (bytes - 1)))
4232 goto emul_write;
10589a46 4233
daea3e73 4234 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4235
daea3e73
AK		 4236 if (gpa == UNMAPPED_GVA ||
4237 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4238 goto emul_write;
2bacc55c 4239
daea3e73
AK		 4240 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4241 goto emul_write;
72dc67a6 4242
daea3e73 4243 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4244 if (is_error_page(page))
c19b8bd6 4245 goto emul_write;
72dc67a6 4246
8fd75e12 4247 kaddr = kmap_atomic(page);
daea3e73
AK		 4248 kaddr += offset_in_page(gpa);
4249 switch (bytes) {
4250 case 1:
4251 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4252 break;
4253 case 2:
4254 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4255 break;
4256 case 4:
4257 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4258 break;
4259 case 8:
4260 exchanged = CMPXCHG64(kaddr, old, new);
4261 break;
4262 default:
4263 BUG();
2bacc55c 4264 }
8fd75e12 4265 kunmap_atomic(kaddr);
daea3e73
AK		 4266 kvm_release_page_dirty(page);
4267
4268 if (!exchanged)
4269 return X86EMUL_CMPXCHG_FAILED;
4270
f57f2ef5 4271 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4272
4273 return X86EMUL_CONTINUE;
4a5f48f6 4274
3200f405 4275emul_write:
daea3e73 4276 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4277
0f65dd70 4278 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4279}
4280
cf8f70bf
GN		 4281static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4282{
4283 /* TODO: String I/O for in kernel device */
4284 int r;
4285
4286 if (vcpu->arch.pio.in)
4287 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4288 vcpu->arch.pio.size, pd);
4289 else
4290 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4291 vcpu->arch.pio.port, vcpu->arch.pio.size,
4292 pd);
4293 return r;
4294}
4295
6f6fbe98
XG		 4296static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4297 unsigned short port, void *val,
4298 unsigned int count, bool in)
cf8f70bf 4299{
6f6fbe98 4300 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4301
4302 vcpu->arch.pio.port = port;
6f6fbe98 4303 vcpu->arch.pio.in = in;
7972995b 4304 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4305 vcpu->arch.pio.size = size;
4306
4307 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4308 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4309 return 1;
4310 }
4311
4312 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4313 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4314 vcpu->run->io.size = size;
4315 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4316 vcpu->run->io.count = count;
4317 vcpu->run->io.port = port;
4318
4319 return 0;
4320}
4321
6f6fbe98
XG		 4322static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4323 int size, unsigned short port, void *val,
4324 unsigned int count)
cf8f70bf 4325{
ca1d4a9e 4326 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4327 int ret;
ca1d4a9e 4328
6f6fbe98
XG		 4329 if (vcpu->arch.pio.count)
4330 goto data_avail;
cf8f70bf 4331
6f6fbe98
XG		 4332 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4333 if (ret) {
4334data_avail:
4335 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4336 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4337 return 1;
4338 }
4339
cf8f70bf
GN		 4340 return 0;
4341}
4342
6f6fbe98
XG		 4343static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4344 int size, unsigned short port,
4345 const void *val, unsigned int count)
4346{
4347 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4348
4349 memcpy(vcpu->arch.pio_data, val, size * count);
4350 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4351}
4352
bbd9b64e
CO		 4353static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4354{
4355 return kvm_x86_ops->get_segment_base(vcpu, seg);
4356}
4357
3cb16fe7 4358static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4359{
3cb16fe7 4360 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4361}
4362
f5f48ee1
SY		 4363int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4364{
4365 if (!need_emulate_wbinvd(vcpu))
4366 return X86EMUL_CONTINUE;
4367
4368 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4369 int cpu = get_cpu();
4370
4371 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4372 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4373 wbinvd_ipi, NULL, 1);
2eec7343 4374 put_cpu();
f5f48ee1 4375 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4376 } else
4377 wbinvd();
f5f48ee1
SY		 4378 return X86EMUL_CONTINUE;
4379}
4380EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4381
bcaf5cc5
AK		 4382static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4383{
4384 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4385}
4386
717746e3 4387int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4388{
717746e3 4389 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4390}
4391
717746e3 4392int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4393{
338dbc97 4394
717746e3 4395 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4396}
4397
52a46617 4398static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4399{
52a46617 4400 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4401}
4402
717746e3 4403static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4404{
717746e3 4405 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4406 unsigned long value;
4407
4408 switch (cr) {
4409 case 0:
4410 value = kvm_read_cr0(vcpu);
4411 break;
4412 case 2:
4413 value = vcpu->arch.cr2;
4414 break;
4415 case 3:
9f8fe504 4416 value = kvm_read_cr3(vcpu);
52a46617
GN		 4417 break;
4418 case 4:
4419 value = kvm_read_cr4(vcpu);
4420 break;
4421 case 8:
4422 value = kvm_get_cr8(vcpu);
4423 break;
4424 default:
a737f256 4425 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4426 return 0;
4427 }
4428
4429 return value;
4430}
4431
717746e3 4432static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4433{
717746e3 4434 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4435 int res = 0;
4436
52a46617
GN		 4437 switch (cr) {
4438 case 0:
49a9b07e 4439 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4440 break;
4441 case 2:
4442 vcpu->arch.cr2 = val;
4443 break;
4444 case 3:
2390218b 4445 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4446 break;
4447 case 4:
a83b29c6 4448 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4449 break;
4450 case 8:
eea1cff9 4451 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4452 break;
4453 default:
a737f256 4454 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4455 res = -1;
52a46617 4456 }
0f12244f
GN		 4457
4458 return res;
52a46617
GN		 4459}
4460
4cee4798
KW		 4461static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4462{
4463 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4464}
4465
717746e3 4466static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4467{
717746e3 4468 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4469}
4470
4bff1e86 4471static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4472{
4bff1e86 4473 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4474}
4475
4bff1e86 4476static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4477{
4bff1e86 4478 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4479}
4480
1ac9d0cf
AK		 4481static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4482{
4483 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4484}
4485
4486static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4487{
4488 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4489}
4490
4bff1e86
AK		 4491static unsigned long emulator_get_cached_segment_base(
4492 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4493{
4bff1e86 4494 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4495}
4496
1aa36616
AK		 4497static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4498 struct desc_struct *desc, u32 *base3,
4499 int seg)
2dafc6c2
GN		 4500{
4501 struct kvm_segment var;
4502
4bff1e86 4503 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4504 *selector = var.selector;
2dafc6c2 4505
378a8b09
GN		 4506 if (var.unusable) {
4507 memset(desc, 0, sizeof(*desc));
2dafc6c2 4508 return false;
378a8b09 4509 }
2dafc6c2
GN		 4510
4511 if (var.g)
4512 var.limit >>= 12;
4513 set_desc_limit(desc, var.limit);
4514 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4515#ifdef CONFIG_X86_64
4516 if (base3)
4517 *base3 = var.base >> 32;
4518#endif
2dafc6c2
GN		 4519 desc->type = var.type;
4520 desc->s = var.s;
4521 desc->dpl = var.dpl;
4522 desc->p = var.present;
4523 desc->avl = var.avl;
4524 desc->l = var.l;
4525 desc->d = var.db;
4526 desc->g = var.g;
4527
4528 return true;
4529}
4530
1aa36616
AK		 4531static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4532 struct desc_struct *desc, u32 base3,
4533 int seg)
2dafc6c2 4534{
4bff1e86 4535 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4536 struct kvm_segment var;
4537
1aa36616 4538 var.selector = selector;
2dafc6c2 4539 var.base = get_desc_base(desc);
5601d05b
GN		 4540#ifdef CONFIG_X86_64
4541 var.base |= ((u64)base3) << 32;
4542#endif
2dafc6c2
GN		 4543 var.limit = get_desc_limit(desc);
4544 if (desc->g)
4545 var.limit = (var.limit << 12) | 0xfff;
4546 var.type = desc->type;
4547 var.present = desc->p;
4548 var.dpl = desc->dpl;
4549 var.db = desc->d;
4550 var.s = desc->s;
4551 var.l = desc->l;
4552 var.g = desc->g;
4553 var.avl = desc->avl;
4554 var.present = desc->p;
4555 var.unusable = !var.present;
4556 var.padding = 0;
4557
4558 kvm_set_segment(vcpu, &var, seg);
4559 return;
4560}
4561
717746e3
AK		 4562static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4563 u32 msr_index, u64 *pdata)
4564{
4565 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4566}
4567
4568static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4569 u32 msr_index, u64 data)
4570{
8fe8ab46
WA		 4571 struct msr_data msr;
4572
4573 msr.data = data;
4574 msr.index = msr_index;
4575 msr.host_initiated = false;
4576 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4577}
4578
222d21aa
AK		 4579static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4580 u32 pmc, u64 *pdata)
4581{
4582 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4583}
4584
6c3287f7
AK		 4585static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4586{
4587 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4588}
4589
5037f6f3
AK		 4590static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4591{
4592 preempt_disable();
5197b808 4593 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4594 /*
4595 * CR0.TS may reference the host fpu state, not the guest fpu state,
4596 * so it may be clear at this point.
4597 */
4598 clts();
4599}
4600
4601static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4602{
4603 preempt_enable();
4604}
4605
2953538e 4606static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4607 struct x86_instruction_info *info,
c4f035c6
AK		 4608 enum x86_intercept_stage stage)
4609{
2953538e 4610 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4611}
4612
0017f93a 4613static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4614 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4615{
0017f93a 4616 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4617}
4618
dd856efa
AK		 4619static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4620{
4621 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4622}
4623
4624static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4625{
4626 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4627}
4628
0225fb50 4629static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4630 .read_gpr = emulator_read_gpr,
4631 .write_gpr = emulator_write_gpr,
1871c602 4632 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4633 .write_std = kvm_write_guest_virt_system,
1871c602 4634 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4635 .read_emulated = emulator_read_emulated,
4636 .write_emulated = emulator_write_emulated,
4637 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4638 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4639 .pio_in_emulated = emulator_pio_in_emulated,
4640 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4641 .get_segment = emulator_get_segment,
4642 .set_segment = emulator_set_segment,
5951c442 4643 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4644 .get_gdt = emulator_get_gdt,
160ce1f1 4645 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4646 .set_gdt = emulator_set_gdt,
4647 .set_idt = emulator_set_idt,
52a46617
GN		 4648 .get_cr = emulator_get_cr,
4649 .set_cr = emulator_set_cr,
4cee4798 4650 .set_rflags = emulator_set_rflags,
9c537244 4651 .cpl = emulator_get_cpl,
35aa5375
GN		 4652 .get_dr = emulator_get_dr,
4653 .set_dr = emulator_set_dr,
717746e3
AK		 4654 .set_msr = emulator_set_msr,
4655 .get_msr = emulator_get_msr,
222d21aa 4656 .read_pmc = emulator_read_pmc,
6c3287f7 4657 .halt = emulator_halt,
bcaf5cc5 4658 .wbinvd = emulator_wbinvd,
d6aa1000 4659 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4660 .get_fpu = emulator_get_fpu,
4661 .put_fpu = emulator_put_fpu,
c4f035c6 4662 .intercept = emulator_intercept,
bdb42f5a 4663 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4664};
4665
95cb2295
GN		 4666static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4667{
4668 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4669 /*
4670 * an sti; sti; sequence only disable interrupts for the first
4671 * instruction. So, if the last instruction, be it emulated or
4672 * not, left the system with the INT_STI flag enabled, it
4673 * means that the last instruction is an sti. We should not
4674 * leave the flag on in this case. The same goes for mov ss
4675 */
4676 if (!(int_shadow & mask))
4677 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4678}
4679
54b8486f
GN		 4680static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4681{
4682 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4683 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4684 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4685 else if (ctxt->exception.error_code_valid)
4686 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4687 ctxt->exception.error_code);
54b8486f 4688 else
da9cb575 4689 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4690}
4691
dd856efa 4692static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4693{
9dac77fa 4694 memset(&ctxt->twobyte, 0,
dd856efa 4695 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4696
9dac77fa
AK		 4697 ctxt->fetch.start = 0;
4698 ctxt->fetch.end = 0;
4699 ctxt->io_read.pos = 0;
4700 ctxt->io_read.end = 0;
4701 ctxt->mem_read.pos = 0;
4702 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4703}
4704
8ec4722d
MG		 4705static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4706{
adf52235 4707 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4708 int cs_db, cs_l;
4709
8ec4722d
MG		 4710 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4711
adf52235
TY		 4712 ctxt->eflags = kvm_get_rflags(vcpu);
4713 ctxt->eip = kvm_rip_read(vcpu);
4714 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4715 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4716 cs_l ? X86EMUL_MODE_PROT64 :
4717 cs_db ? X86EMUL_MODE_PROT32 :
4718 X86EMUL_MODE_PROT16;
4719 ctxt->guest_mode = is_guest_mode(vcpu);
4720
dd856efa 4721 init_decode_cache(ctxt);
7ae441ea 4722 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4723}
4724
71f9833b 4725int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4726{
9d74191a 4727 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4728 int ret;
4729
4730 init_emulate_ctxt(vcpu);
4731
9dac77fa
AK		 4732 ctxt->op_bytes = 2;
4733 ctxt->ad_bytes = 2;
4734 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4735 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4736
4737 if (ret != X86EMUL_CONTINUE)
4738 return EMULATE_FAIL;
4739
9dac77fa 4740 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4741 kvm_rip_write(vcpu, ctxt->eip);
4742 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4743
4744 if (irq == NMI_VECTOR)
7460fb4a 4745 vcpu->arch.nmi_pending = 0;
63995653
MG		 4746 else
4747 vcpu->arch.interrupt.pending = false;
4748
4749 return EMULATE_DONE;
4750}
4751EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4752
6d77dbfc
GN		 4753static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4754{
fc3a9157
JR		 4755 int r = EMULATE_DONE;
4756
6d77dbfc
GN		 4757 ++vcpu->stat.insn_emulation_fail;
4758 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4759 if (!is_guest_mode(vcpu)) {
4760 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4761 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4762 vcpu->run->internal.ndata = 0;
4763 r = EMULATE_FAIL;
4764 }
6d77dbfc 4765 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4766
4767 return r;
6d77dbfc
GN		 4768}
4769
93c05d3e 4770static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4771 bool write_fault_to_shadow_pgtable,
4772 int emulation_type)
a6f177ef 4773{
95b3cf69 4774 gpa_t gpa = cr2;
8e3d9d06 4775 pfn_t pfn;
a6f177ef 4776
991eebf9
GN		 4777 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4778 return false;
4779
95b3cf69
XG		 4780 if (!vcpu->arch.mmu.direct_map) {
4781 /*
4782 * Write permission should be allowed since only
4783 * write access need to be emulated.
4784 */
4785 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
22368028 4786
95b3cf69
XG		 4787 /*
4788 * If the mapping is invalid in guest, let cpu retry
4789 * it to generate fault.
4790 */
4791 if (gpa == UNMAPPED_GVA)
4792 return true;
4793 }
a6f177ef 4794
8e3d9d06
XG		 4795 /*
4796 * Do not retry the unhandleable instruction if it faults on the
4797 * readonly host memory, otherwise it will goto a infinite loop:
4798 * retry instruction -> write #PF -> emulation fail -> retry
4799 * instruction -> ...
4800 */
4801 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4802
4803 /*
4804 * If the instruction failed on the error pfn, it can not be fixed,
4805 * report the error to userspace.
4806 */
4807 if (is_error_noslot_pfn(pfn))
4808 return false;
4809
4810 kvm_release_pfn_clean(pfn);
4811
4812 /* The instructions are well-emulated on direct mmu. */
4813 if (vcpu->arch.mmu.direct_map) {
4814 unsigned int indirect_shadow_pages;
4815
4816 spin_lock(&vcpu->kvm->mmu_lock);
4817 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4818 spin_unlock(&vcpu->kvm->mmu_lock);
4819
4820 if (indirect_shadow_pages)
4821 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4822
a6f177ef 4823 return true;
8e3d9d06 4824 }
a6f177ef 4825
95b3cf69
XG		 4826 /*
4827 * if emulation was due to access to shadowed page table
4828 * and it failed try to unshadow page and re-enter the
4829 * guest to let CPU execute the instruction.
4830 */
4831 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4832
4833 /*
4834 * If the access faults on its page table, it can not
4835 * be fixed by unprotecting shadow page and it should
4836 * be reported to userspace.
4837 */
4838 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4839}
4840
1cb3f3ae
XG		 4841static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4842 unsigned long cr2, int emulation_type)
4843{
4844 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4845 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4846
4847 last_retry_eip = vcpu->arch.last_retry_eip;
4848 last_retry_addr = vcpu->arch.last_retry_addr;
4849
4850 /*
4851 * If the emulation is caused by #PF and it is non-page_table
4852 * writing instruction, it means the VM-EXIT is caused by shadow
4853 * page protected, we can zap the shadow page and retry this
4854 * instruction directly.
4855 *
4856 * Note: if the guest uses a non-page-table modifying instruction
4857 * on the PDE that points to the instruction, then we will unmap
4858 * the instruction and go to an infinite loop. So, we cache the
4859 * last retried eip and the last fault address, if we meet the eip
4860 * and the address again, we can break out of the potential infinite
4861 * loop.
4862 */
4863 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4864
4865 if (!(emulation_type & EMULTYPE_RETRY))
4866 return false;
4867
4868 if (x86_page_table_writing_insn(ctxt))
4869 return false;
4870
4871 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4872 return false;
4873
4874 vcpu->arch.last_retry_eip = ctxt->eip;
4875 vcpu->arch.last_retry_addr = cr2;
4876
4877 if (!vcpu->arch.mmu.direct_map)
4878 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4879
22368028 4880 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4881
4882 return true;
4883}
4884
716d51ab
GN		 4885static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4886static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4887
51d8b661
AP		 4888int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4889 unsigned long cr2,
dc25e89e
AP		 4890 int emulation_type,
4891 void *insn,
4892 int insn_len)
bbd9b64e 4893{
95cb2295 4894 int r;
9d74191a 4895 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4896 bool writeback = true;
93c05d3e 4897 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 4898
93c05d3e
XG		 4899 /*
4900 * Clear write_fault_to_shadow_pgtable here to ensure it is
4901 * never reused.
4902 */
4903 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 4904 kvm_clear_exception_queue(vcpu);
8d7d8102 4905
571008da 4906 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4907 init_emulate_ctxt(vcpu);
9d74191a
TY		 4908 ctxt->interruptibility = 0;
4909 ctxt->have_exception = false;
4910 ctxt->perm_ok = false;
bbd9b64e 4911
9d74191a 4912 ctxt->only_vendor_specific_insn
4005996e
AK		 4913 = emulation_type & EMULTYPE_TRAP_UD;
4914
9d74191a 4915 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4916
e46479f8 4917 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4918 ++vcpu->stat.insn_emulation;
1d2887e2 4919 if (r != EMULATION_OK) {
4005996e
AK		 4920 if (emulation_type & EMULTYPE_TRAP_UD)
4921 return EMULATE_FAIL;
991eebf9
GN		 4922 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4923 emulation_type))
bbd9b64e 4924 return EMULATE_DONE;
6d77dbfc
GN		 4925 if (emulation_type & EMULTYPE_SKIP)
4926 return EMULATE_FAIL;
4927 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4928 }
4929 }
4930
ba8afb6b 4931 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4932 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4933 return EMULATE_DONE;
4934 }
4935
1cb3f3ae
XG		 4936 if (retry_instruction(ctxt, cr2, emulation_type))
4937 return EMULATE_DONE;
4938
7ae441ea 4939 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4940 changes registers values during IO operation */
7ae441ea
GN		 4941 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4942 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4943 emulator_invalidate_register_cache(ctxt);
7ae441ea 4944 }
4d2179e1 4945
5cd21917 4946restart:
9d74191a 4947 r = x86_emulate_insn(ctxt);
bbd9b64e 4948
775fde86
JR		 4949 if (r == EMULATION_INTERCEPTED)
4950 return EMULATE_DONE;
4951
d2ddd1c4 4952 if (r == EMULATION_FAILED) {
991eebf9
GN		 4953 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4954 emulation_type))
c3cd7ffa
GN		 4955 return EMULATE_DONE;
4956
6d77dbfc 4957 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4958 }
4959
9d74191a 4960 if (ctxt->have_exception) {
54b8486f 4961 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4962 r = EMULATE_DONE;
4963 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4964 if (!vcpu->arch.pio.in)
4965 vcpu->arch.pio.count = 0;
716d51ab 4966 else {
7ae441ea 4967 writeback = false;
716d51ab
GN		 4968 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4969 }
e85d28f8 4970 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4971 } else if (vcpu->mmio_needed) {
4972 if (!vcpu->mmio_is_write)
4973 writeback = false;
e85d28f8 4974 r = EMULATE_DO_MMIO;
716d51ab 4975 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4976 } else if (r == EMULATION_RESTART)
5cd21917 4977 goto restart;
d2ddd1c4
GN		 4978 else
4979 r = EMULATE_DONE;
f850e2e6 4980
7ae441ea 4981 if (writeback) {
9d74191a
TY		 4982 toggle_interruptibility(vcpu, ctxt->interruptibility);
4983 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4984 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4985 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4986 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4987 } else
4988 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4989
4990 return r;
de7d789a 4991}
51d8b661 4992EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4993
cf8f70bf 4994int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4995{
cf8f70bf 4996 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4997 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4998 size, port, &val, 1);
cf8f70bf 4999 /* do not return to emulator after return from userspace */
7972995b 5000 vcpu->arch.pio.count = 0;
de7d789a
CO		 5001 return ret;
5002}
cf8f70bf 5003EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5004
8cfdc000
ZA		 5005static void tsc_bad(void *info)
5006{
0a3aee0d 5007 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5008}
5009
5010static void tsc_khz_changed(void *data)
c8076604 5011{
8cfdc000
ZA		 5012 struct cpufreq_freqs *freq = data;
5013 unsigned long khz = 0;
5014
5015 if (data)
5016 khz = freq->new;
5017 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5018 khz = cpufreq_quick_get(raw_smp_processor_id());
5019 if (!khz)
5020 khz = tsc_khz;
0a3aee0d 5021 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5022}
5023
c8076604
GH		 5024static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5025 void *data)
5026{
5027 struct cpufreq_freqs *freq = data;
5028 struct kvm *kvm;
5029 struct kvm_vcpu *vcpu;
5030 int i, send_ipi = 0;
5031
8cfdc000
ZA		 5032 /*
5033 * We allow guests to temporarily run on slowing clocks,
5034 * provided we notify them after, or to run on accelerating
5035 * clocks, provided we notify them before. Thus time never
5036 * goes backwards.
5037 *
5038 * However, we have a problem. We can't atomically update
5039 * the frequency of a given CPU from this function; it is
5040 * merely a notifier, which can be called from any CPU.
5041 * Changing the TSC frequency at arbitrary points in time
5042 * requires a recomputation of local variables related to
5043 * the TSC for each VCPU. We must flag these local variables
5044 * to be updated and be sure the update takes place with the
5045 * new frequency before any guests proceed.
5046 *
5047 * Unfortunately, the combination of hotplug CPU and frequency
5048 * change creates an intractable locking scenario; the order
5049 * of when these callouts happen is undefined with respect to
5050 * CPU hotplug, and they can race with each other. As such,
5051 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5052 * undefined; you can actually have a CPU frequency change take
5053 * place in between the computation of X and the setting of the
5054 * variable. To protect against this problem, all updates of
5055 * the per_cpu tsc_khz variable are done in an interrupt
5056 * protected IPI, and all callers wishing to update the value
5057 * must wait for a synchronous IPI to complete (which is trivial
5058 * if the caller is on the CPU already). This establishes the
5059 * necessary total order on variable updates.
5060 *
5061 * Note that because a guest time update may take place
5062 * anytime after the setting of the VCPU's request bit, the
5063 * correct TSC value must be set before the request. However,
5064 * to ensure the update actually makes it to any guest which
5065 * starts running in hardware virtualization between the set
5066 * and the acquisition of the spinlock, we must also ping the
5067 * CPU after setting the request bit.
5068 *
5069 */
5070
c8076604
GH		 5071 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5072 return 0;
5073 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5074 return 0;
8cfdc000
ZA		 5075
5076 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5077
e935b837 5078 raw_spin_lock(&kvm_lock);
c8076604 5079 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5080 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5081 if (vcpu->cpu != freq->cpu)
5082 continue;
c285545f 5083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5084 if (vcpu->cpu != smp_processor_id())
8cfdc000 5085 send_ipi = 1;
c8076604
GH		 5086 }
5087 }
e935b837 5088 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5089
5090 if (freq->old < freq->new && send_ipi) {
5091 /*
5092 * We upscale the frequency. Must make the guest
5093 * doesn't see old kvmclock values while running with
5094 * the new frequency, otherwise we risk the guest sees
5095 * time go backwards.
5096 *
5097 * In case we update the frequency for another cpu
5098 * (which might be in guest context) send an interrupt
5099 * to kick the cpu out of guest context. Next time
5100 * guest context is entered kvmclock will be updated,
5101 * so the guest will not see stale values.
5102 */
8cfdc000 5103 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5104 }
5105 return 0;
5106}
5107
5108static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5109 .notifier_call = kvmclock_cpufreq_notifier
5110};
5111
5112static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5113 unsigned long action, void *hcpu)
5114{
5115 unsigned int cpu = (unsigned long)hcpu;
5116
5117 switch (action) {
5118 case CPU_ONLINE:
5119 case CPU_DOWN_FAILED:
5120 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5121 break;
5122 case CPU_DOWN_PREPARE:
5123 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5124 break;
5125 }
5126 return NOTIFY_OK;
5127}
5128
5129static struct notifier_block kvmclock_cpu_notifier_block = {
5130 .notifier_call = kvmclock_cpu_notifier,
5131 .priority = -INT_MAX
c8076604
GH		 5132};
5133
b820cc0c
ZA		 5134static void kvm_timer_init(void)
5135{
5136 int cpu;
5137
c285545f 5138 max_tsc_khz = tsc_khz;
8cfdc000 5139 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5140 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5141#ifdef CONFIG_CPU_FREQ
5142 struct cpufreq_policy policy;
5143 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5144 cpu = get_cpu();
5145 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5146 if (policy.cpuinfo.max_freq)
5147 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5148 put_cpu();
c285545f 5149#endif
b820cc0c
ZA		 5150 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5151 CPUFREQ_TRANSITION_NOTIFIER);
5152 }
c285545f 5153 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5154 for_each_online_cpu(cpu)
5155 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5156}
5157
ff9d07a0
ZY		 5158static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5159
f5132b01 5160int kvm_is_in_guest(void)
ff9d07a0 5161{
086c9855 5162 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5163}
5164
5165static int kvm_is_user_mode(void)
5166{
5167 int user_mode = 3;
dcf46b94 5168
086c9855
AS		 5169 if (__this_cpu_read(current_vcpu))
5170 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5171
ff9d07a0
ZY		 5172 return user_mode != 0;
5173}
5174
5175static unsigned long kvm_get_guest_ip(void)
5176{
5177 unsigned long ip = 0;
dcf46b94 5178
086c9855
AS		 5179 if (__this_cpu_read(current_vcpu))
5180 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5181
ff9d07a0
ZY		 5182 return ip;
5183}
5184
5185static struct perf_guest_info_callbacks kvm_guest_cbs = {
5186 .is_in_guest = kvm_is_in_guest,
5187 .is_user_mode = kvm_is_user_mode,
5188 .get_guest_ip = kvm_get_guest_ip,
5189};
5190
5191void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5192{
086c9855 5193 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5194}
5195EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5196
5197void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5198{
086c9855 5199 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5200}
5201EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5202
ce88decf
XG		 5203static void kvm_set_mmio_spte_mask(void)
5204{
5205 u64 mask;
5206 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5207
5208 /*
5209 * Set the reserved bits and the present bit of an paging-structure
5210 * entry to generate page fault with PFER.RSV = 1.
5211 */
5212 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5213 mask |= 1ull;
5214
5215#ifdef CONFIG_X86_64
5216 /*
5217 * If reserved bit is not supported, clear the present bit to disable
5218 * mmio page fault.
5219 */
5220 if (maxphyaddr == 52)
5221 mask &= ~1ull;
5222#endif
5223
5224 kvm_mmu_set_mmio_spte_mask(mask);
5225}
5226
16e8d74d
MT		 5227#ifdef CONFIG_X86_64
5228static void pvclock_gtod_update_fn(struct work_struct *work)
5229{
d828199e
MT		 5230 struct kvm *kvm;
5231
5232 struct kvm_vcpu *vcpu;
5233 int i;
5234
5235 raw_spin_lock(&kvm_lock);
5236 list_for_each_entry(kvm, &vm_list, vm_list)
5237 kvm_for_each_vcpu(i, vcpu, kvm)
5238 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5239 atomic_set(&kvm_guest_has_master_clock, 0);
5240 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5241}
5242
5243static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5244
5245/*
5246 * Notification about pvclock gtod data update.
5247 */
5248static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5249 void *priv)
5250{
5251 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5252 struct timekeeper *tk = priv;
5253
5254 update_pvclock_gtod(tk);
5255
5256 /* disable master clock if host does not trust, or does not
5257 * use, TSC clocksource
5258 */
5259 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5260 atomic_read(&kvm_guest_has_master_clock) != 0)
5261 queue_work(system_long_wq, &pvclock_gtod_work);
5262
5263 return 0;
5264}
5265
5266static struct notifier_block pvclock_gtod_notifier = {
5267 .notifier_call = pvclock_gtod_notify,
5268};
5269#endif
5270
f8c16bba 5271int kvm_arch_init(void *opaque)
043405e1 5272{
b820cc0c 5273 int r;
f8c16bba
ZX		 5274 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5275
f8c16bba
ZX		 5276 if (kvm_x86_ops) {
5277 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5278 r = -EEXIST;
5279 goto out;
f8c16bba
ZX		 5280 }
5281
5282 if (!ops->cpu_has_kvm_support()) {
5283 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5284 r = -EOPNOTSUPP;
5285 goto out;
f8c16bba
ZX		 5286 }
5287 if (ops->disabled_by_bios()) {
5288 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5289 r = -EOPNOTSUPP;
5290 goto out;
f8c16bba
ZX		 5291 }
5292
013f6a5d
MT		 5293 r = -ENOMEM;
5294 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5295 if (!shared_msrs) {
5296 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5297 goto out;
5298 }
5299
97db56ce
AK		 5300 r = kvm_mmu_module_init();
5301 if (r)
013f6a5d 5302 goto out_free_percpu;
97db56ce 5303
ce88decf 5304 kvm_set_mmio_spte_mask();
97db56ce
AK		 5305 kvm_init_msr_list();
5306
f8c16bba 5307 kvm_x86_ops = ops;
7b52345e 5308 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5309 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5310
b820cc0c 5311 kvm_timer_init();
c8076604 5312
ff9d07a0
ZY		 5313 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5314
2acf923e
DC		 5315 if (cpu_has_xsave)
5316 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5317
c5cc421b 5318 kvm_lapic_init();
16e8d74d
MT		 5319#ifdef CONFIG_X86_64
5320 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5321#endif
5322
f8c16bba 5323 return 0;
56c6d28a 5324
013f6a5d
MT		 5325out_free_percpu:
5326 free_percpu(shared_msrs);
56c6d28a 5327out:
56c6d28a 5328 return r;
043405e1 5329}
8776e519 5330
f8c16bba
ZX		 5331void kvm_arch_exit(void)
5332{
ff9d07a0
ZY		 5333 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5334
888d256e
JK		 5335 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5336 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5337 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5338 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5339#ifdef CONFIG_X86_64
5340 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5341#endif
f8c16bba 5342 kvm_x86_ops = NULL;
56c6d28a 5343 kvm_mmu_module_exit();
013f6a5d 5344 free_percpu(shared_msrs);
56c6d28a 5345}
f8c16bba 5346
8776e519
HB		 5347int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5348{
5349 ++vcpu->stat.halt_exits;
5350 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5351 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5352 return 1;
5353 } else {
5354 vcpu->run->exit_reason = KVM_EXIT_HLT;
5355 return 0;
5356 }
5357}
5358EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5359
55cd8e5a
GN		 5360int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5361{
5362 u64 param, ingpa, outgpa, ret;
5363 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5364 bool fast, longmode;
5365 int cs_db, cs_l;
5366
5367 /*
5368 * hypercall generates UD from non zero cpl and real mode
5369 * per HYPER-V spec
5370 */
3eeb3288 5371 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5372 kvm_queue_exception(vcpu, UD_VECTOR);
5373 return 0;
5374 }
5375
5376 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5377 longmode = is_long_mode(vcpu) && cs_l == 1;
5378
5379 if (!longmode) {
ccd46936
GN		 5380 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5381 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5382 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5383 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5384 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5385 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5386 }
5387#ifdef CONFIG_X86_64
5388 else {
5389 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5390 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5391 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5392 }
5393#endif
5394
5395 code = param & 0xffff;
5396 fast = (param >> 16) & 0x1;
5397 rep_cnt = (param >> 32) & 0xfff;
5398 rep_idx = (param >> 48) & 0xfff;
5399
5400 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5401
c25bc163
GN		 5402 switch (code) {
5403 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5404 kvm_vcpu_on_spin(vcpu);
5405 break;
5406 default:
5407 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5408 break;
5409 }
55cd8e5a
GN		 5410
5411 ret = res | (((u64)rep_done & 0xfff) << 32);
5412 if (longmode) {
5413 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5414 } else {
5415 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5416 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5417 }
5418
5419 return 1;
5420}
5421
8776e519
HB		 5422int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5423{
5424 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5425 int r = 1;
8776e519 5426
55cd8e5a
GN		 5427 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5428 return kvm_hv_hypercall(vcpu);
5429
5fdbf976
MT		 5430 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5431 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5432 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5433 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5434 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5435
229456fc 5436 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5437
8776e519
HB		 5438 if (!is_long_mode(vcpu)) {
5439 nr &= 0xFFFFFFFF;
5440 a0 &= 0xFFFFFFFF;
5441 a1 &= 0xFFFFFFFF;
5442 a2 &= 0xFFFFFFFF;
5443 a3 &= 0xFFFFFFFF;
5444 }
5445
07708c4a
JK		 5446 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5447 ret = -KVM_EPERM;
5448 goto out;
5449 }
5450
8776e519 5451 switch (nr) {
b93463aa
AK		 5452 case KVM_HC_VAPIC_POLL_IRQ:
5453 ret = 0;
5454 break;
8776e519
HB		 5455 default:
5456 ret = -KVM_ENOSYS;
5457 break;
5458 }
07708c4a 5459out:
5fdbf976 5460 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5461 ++vcpu->stat.hypercalls;
2f333bcb 5462 return r;
8776e519
HB		 5463}
5464EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5465
b6785def 5466static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5467{
d6aa1000 5468 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5469 char instruction[3];
5fdbf976 5470 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5471
8776e519
HB		 5472 /*
5473 * Blow out the MMU to ensure that no other VCPU has an active mapping
5474 * to ensure that the updated hypercall appears atomically across all
5475 * VCPUs.
5476 */
5477 kvm_mmu_zap_all(vcpu->kvm);
5478
8776e519 5479 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5480
9d74191a 5481 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5482}
5483
b6c7a5dc
HB		 5484/*
5485 * Check if userspace requested an interrupt window, and that the
5486 * interrupt window is open.
5487 *
5488 * No need to exit to userspace if we already have an interrupt queued.
5489 */
851ba692 5490static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5491{
8061823a 5492 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5493 vcpu->run->request_interrupt_window &&
5df56646 5494 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5495}
5496
851ba692 5497static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5498{
851ba692
AK		 5499 struct kvm_run *kvm_run = vcpu->run;
5500
91586a3b 5501 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5502 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5503 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5504 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5505 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5506 else
b6c7a5dc 5507 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5508 kvm_arch_interrupt_allowed(vcpu) &&
5509 !kvm_cpu_has_interrupt(vcpu) &&
5510 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5511}
5512
4484141a 5513static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5514{
5515 struct kvm_lapic *apic = vcpu->arch.apic;
5516 struct page *page;
5517
5518 if (!apic || !apic->vapic_addr)
4484141a 5519 return 0;
b93463aa
AK		 5520
5521 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5522 if (is_error_page(page))
5523 return -EFAULT;
72dc67a6
IE		 5524
5525 vcpu->arch.apic->vapic_page = page;
4484141a 5526 return 0;
b93463aa
AK		 5527}
5528
5529static void vapic_exit(struct kvm_vcpu *vcpu)
5530{
5531 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5532 int idx;
b93463aa
AK		 5533
5534 if (!apic || !apic->vapic_addr)
5535 return;
5536
f656ce01 5537 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5538 kvm_release_page_dirty(apic->vapic_page);
5539 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5540 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5541}
5542
95ba8273
GN		 5543static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5544{
5545 int max_irr, tpr;
5546
5547 if (!kvm_x86_ops->update_cr8_intercept)
5548 return;
5549
88c808fd
AK		 5550 if (!vcpu->arch.apic)
5551 return;
5552
8db3baa2
GN		 5553 if (!vcpu->arch.apic->vapic_addr)
5554 max_irr = kvm_lapic_find_highest_irr(vcpu);
5555 else
5556 max_irr = -1;
95ba8273
GN		 5557
5558 if (max_irr != -1)
5559 max_irr >>= 4;
5560
5561 tpr = kvm_lapic_get_cr8(vcpu);
5562
5563 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5564}
5565
851ba692 5566static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5567{
5568 /* try to reinject previous events if any */
b59bb7bd 5569 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5570 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5571 vcpu->arch.exception.has_error_code,
5572 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5573 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5574 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5575 vcpu->arch.exception.error_code,
5576 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5577 return;
5578 }
5579
95ba8273
GN		 5580 if (vcpu->arch.nmi_injected) {
5581 kvm_x86_ops->set_nmi(vcpu);
5582 return;
5583 }
5584
5585 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5586 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5587 return;
5588 }
5589
5590 /* try to inject new event if pending */
5591 if (vcpu->arch.nmi_pending) {
5592 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5593 --vcpu->arch.nmi_pending;
95ba8273
GN		 5594 vcpu->arch.nmi_injected = true;
5595 kvm_x86_ops->set_nmi(vcpu);
5596 }
c7c9c56c 5597 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5598 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5599 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5600 false);
5601 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5602 }
5603 }
5604}
5605
2acf923e
DC		 5606static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5607{
5608 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5609 !vcpu->guest_xcr0_loaded) {
5610 /* kvm_set_xcr() also depends on this */
5611 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5612 vcpu->guest_xcr0_loaded = 1;
5613 }
5614}
5615
5616static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5617{
5618 if (vcpu->guest_xcr0_loaded) {
5619 if (vcpu->arch.xcr0 != host_xcr0)
5620 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5621 vcpu->guest_xcr0_loaded = 0;
5622 }
5623}
5624
7460fb4a
AK		 5625static void process_nmi(struct kvm_vcpu *vcpu)
5626{
5627 unsigned limit = 2;
5628
5629 /*
5630 * x86 is limited to one NMI running, and one NMI pending after it.
5631 * If an NMI is already in progress, limit further NMIs to just one.
5632 * Otherwise, allow two (and we'll inject the first one immediately).
5633 */
5634 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5635 limit = 1;
5636
5637 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5638 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5639 kvm_make_request(KVM_REQ_EVENT, vcpu);
5640}
5641
d828199e
MT		 5642static void kvm_gen_update_masterclock(struct kvm *kvm)
5643{
5644#ifdef CONFIG_X86_64
5645 int i;
5646 struct kvm_vcpu *vcpu;
5647 struct kvm_arch *ka = &kvm->arch;
5648
5649 spin_lock(&ka->pvclock_gtod_sync_lock);
5650 kvm_make_mclock_inprogress_request(kvm);
5651 /* no guest entries from this point */
5652 pvclock_update_vm_gtod_copy(kvm);
5653
5654 kvm_for_each_vcpu(i, vcpu, kvm)
5655 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5656
5657 /* guest entries allowed */
5658 kvm_for_each_vcpu(i, vcpu, kvm)
5659 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5660
5661 spin_unlock(&ka->pvclock_gtod_sync_lock);
5662#endif
5663}
5664
3d81bc7e 5665static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5666{
5667 u64 eoi_exit_bitmap[4];
cf9e65b7 5668 u32 tmr[8];
c7c9c56c 5669
3d81bc7e
YZ		 5670 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5671 return;
5672
c7c9c56c 5673 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5674 memset(tmr, 0, 32);
c7c9c56c 5675
cf9e65b7 5676 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5677 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5678 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5679}
5680
851ba692 5681static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5682{
5683 int r;
6a8b1d13 5684 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5685 vcpu->run->request_interrupt_window;
d6185f20 5686 bool req_immediate_exit = 0;
b6c7a5dc 5687
3e007509 5688 if (vcpu->requests) {
a8eeb04a 5689 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5690 kvm_mmu_unload(vcpu);
a8eeb04a 5691 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5692 __kvm_migrate_timers(vcpu);
d828199e
MT		 5693 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5694 kvm_gen_update_masterclock(vcpu->kvm);
34c238a1
ZA		 5695 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5696 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5697 if (unlikely(r))
5698 goto out;
5699 }
a8eeb04a 5700 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5701 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5702 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5703 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5704 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5705 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5706 r = 0;
5707 goto out;
5708 }
a8eeb04a 5709 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5710 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5711 r = 0;
5712 goto out;
5713 }
a8eeb04a 5714 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5715 vcpu->fpu_active = 0;
5716 kvm_x86_ops->fpu_deactivate(vcpu);
5717 }
af585b92
GN		 5718 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5719 /* Page is swapped out. Do synthetic halt */
5720 vcpu->arch.apf.halted = true;
5721 r = 1;
5722 goto out;
5723 }
c9aaa895
GC		 5724 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5725 record_steal_time(vcpu);
7460fb4a
AK		 5726 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5727 process_nmi(vcpu);
d6185f20
NHE		 5728 req_immediate_exit =
5729 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5730 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5731 kvm_handle_pmu_event(vcpu);
5732 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5733 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5734 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5735 vcpu_scan_ioapic(vcpu);
2f52d58c 5736 }
b93463aa 5737
b463a6f7 5738 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5739 kvm_apic_accept_events(vcpu);
5740 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5741 r = 1;
5742 goto out;
5743 }
5744
b463a6f7
AK		 5745 inject_pending_event(vcpu);
5746
5747 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5748 if (vcpu->arch.nmi_pending)
b463a6f7 5749 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5750 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
b463a6f7
AK		 5751 kvm_x86_ops->enable_irq_window(vcpu);
5752
5753 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5754 /*
5755 * Update architecture specific hints for APIC
5756 * virtual interrupt delivery.
5757 */
5758 if (kvm_x86_ops->hwapic_irr_update)
5759 kvm_x86_ops->hwapic_irr_update(vcpu,
5760 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5761 update_cr8_intercept(vcpu);
5762 kvm_lapic_sync_to_vapic(vcpu);
5763 }
5764 }
5765
d8368af8
AK		 5766 r = kvm_mmu_reload(vcpu);
5767 if (unlikely(r)) {
d905c069 5768 goto cancel_injection;
d8368af8
AK		 5769 }
5770
b6c7a5dc
HB		 5771 preempt_disable();
5772
5773 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5774 if (vcpu->fpu_active)
5775 kvm_load_guest_fpu(vcpu);
2acf923e 5776 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5777
6b7e2d09
XG		 5778 vcpu->mode = IN_GUEST_MODE;
5779
5780 /* We should set ->mode before check ->requests,
5781 * see the comment in make_all_cpus_request.
5782 */
5783 smp_mb();
b6c7a5dc 5784
d94e1dc9 5785 local_irq_disable();
32f88400 5786
6b7e2d09 5787 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5788 || need_resched() || signal_pending(current)) {
6b7e2d09 5789 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5790 smp_wmb();
6c142801
AK		 5791 local_irq_enable();
5792 preempt_enable();
5793 r = 1;
d905c069 5794 goto cancel_injection;
6c142801
AK		 5795 }
5796
f656ce01 5797 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5798
d6185f20
NHE		 5799 if (req_immediate_exit)
5800 smp_send_reschedule(vcpu->cpu);
5801
b6c7a5dc
HB		 5802 kvm_guest_enter();
5803
42dbaa5a 5804 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5805 set_debugreg(0, 7);
5806 set_debugreg(vcpu->arch.eff_db[0], 0);
5807 set_debugreg(vcpu->arch.eff_db[1], 1);
5808 set_debugreg(vcpu->arch.eff_db[2], 2);
5809 set_debugreg(vcpu->arch.eff_db[3], 3);
5810 }
b6c7a5dc 5811
229456fc 5812 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5813 kvm_x86_ops->run(vcpu);
b6c7a5dc 5814
24f1e32c
FW		 5815 /*
5816 * If the guest has used debug registers, at least dr7
5817 * will be disabled while returning to the host.
5818 * If we don't have active breakpoints in the host, we don't
5819 * care about the messed up debug address registers. But if
5820 * we have some of them active, restore the old state.
5821 */
59d8eb53 5822 if (hw_breakpoint_active())
24f1e32c 5823 hw_breakpoint_restore();
42dbaa5a 5824
886b470c
MT		 5825 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5826 native_read_tsc());
1d5f066e 5827
6b7e2d09 5828 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5829 smp_wmb();
a547c6db
YZ		 5830
5831 /* Interrupt is enabled by handle_external_intr() */
5832 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 5833
5834 ++vcpu->stat.exits;
5835
5836 /*
5837 * We must have an instruction between local_irq_enable() and
5838 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5839 * the interrupt shadow. The stat.exits increment will do nicely.
5840 * But we need to prevent reordering, hence this barrier():
5841 */
5842 barrier();
5843
5844 kvm_guest_exit();
5845
5846 preempt_enable();
5847
f656ce01 5848 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5849
b6c7a5dc
HB		 5850 /*
5851 * Profile KVM exit RIPs:
5852 */
5853 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5854 unsigned long rip = kvm_rip_read(vcpu);
5855 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5856 }
5857
cc578287
ZA		 5858 if (unlikely(vcpu->arch.tsc_always_catchup))
5859 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5860
5cfb1d5a
MT		 5861 if (vcpu->arch.apic_attention)
5862 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5863
851ba692 5864 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5865 return r;
5866
5867cancel_injection:
5868 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5869 if (unlikely(vcpu->arch.apic_attention))
5870 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5871out:
5872 return r;
5873}
b6c7a5dc 5874
09cec754 5875
851ba692 5876static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5877{
5878 int r;
f656ce01 5879 struct kvm *kvm = vcpu->kvm;
d7690175 5880
f656ce01 5881 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5882 r = vapic_enter(vcpu);
5883 if (r) {
5884 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5885 return r;
5886 }
d7690175
MT		 5887
5888 r = 1;
5889 while (r > 0) {
af585b92
GN		 5890 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5891 !vcpu->arch.apf.halted)
851ba692 5892 r = vcpu_enter_guest(vcpu);
d7690175 5893 else {
f656ce01 5894 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5895 kvm_vcpu_block(vcpu);
f656ce01 5896 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 5897 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5898 kvm_apic_accept_events(vcpu);
09cec754
GN		 5899 switch(vcpu->arch.mp_state) {
5900 case KVM_MP_STATE_HALTED:
d7690175 5901 vcpu->arch.mp_state =
09cec754
GN		 5902 KVM_MP_STATE_RUNNABLE;
5903 case KVM_MP_STATE_RUNNABLE:
af585b92 5904 vcpu->arch.apf.halted = false;
09cec754 5905 break;
66450a21
JK		 5906 case KVM_MP_STATE_INIT_RECEIVED:
5907 break;
09cec754
GN		 5908 default:
5909 r = -EINTR;
5910 break;
5911 }
5912 }
d7690175
MT		 5913 }
5914
09cec754
GN		 5915 if (r <= 0)
5916 break;
5917
5918 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5919 if (kvm_cpu_has_pending_timer(vcpu))
5920 kvm_inject_pending_timer_irqs(vcpu);
5921
851ba692 5922 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5923 r = -EINTR;
851ba692 5924 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5925 ++vcpu->stat.request_irq_exits;
5926 }
af585b92
GN		 5927
5928 kvm_check_async_pf_completion(vcpu);
5929
09cec754
GN		 5930 if (signal_pending(current)) {
5931 r = -EINTR;
851ba692 5932 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5933 ++vcpu->stat.signal_exits;
5934 }
5935 if (need_resched()) {
f656ce01 5936 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5937 kvm_resched(vcpu);
f656ce01 5938 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5939 }
b6c7a5dc
HB		 5940 }
5941
f656ce01 5942 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5943
b93463aa
AK		 5944 vapic_exit(vcpu);
5945
b6c7a5dc
HB		 5946 return r;
5947}
5948
716d51ab
GN		 5949static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5950{
5951 int r;
5952 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5953 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5954 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5955 if (r != EMULATE_DONE)
5956 return 0;
5957 return 1;
5958}
5959
5960static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5961{
5962 BUG_ON(!vcpu->arch.pio.count);
5963
5964 return complete_emulated_io(vcpu);
5965}
5966
f78146b0
AK		 5967/*
5968 * Implements the following, as a state machine:
5969 *
5970 * read:
5971 * for each fragment
87da7e66
XG		 5972 * for each mmio piece in the fragment
5973 * write gpa, len
5974 * exit
5975 * copy data
f78146b0
AK		 5976 * execute insn
5977 *
5978 * write:
5979 * for each fragment
87da7e66
XG		 5980 * for each mmio piece in the fragment
5981 * write gpa, len
5982 * copy data
5983 * exit
f78146b0 5984 */
716d51ab 5985static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5986{
5987 struct kvm_run *run = vcpu->run;
f78146b0 5988 struct kvm_mmio_fragment *frag;
87da7e66 5989 unsigned len;
5287f194 5990
716d51ab 5991 BUG_ON(!vcpu->mmio_needed);
5287f194 5992
716d51ab 5993 /* Complete previous fragment */
87da7e66
XG		 5994 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
5995 len = min(8u, frag->len);
716d51ab 5996 if (!vcpu->mmio_is_write)
87da7e66
XG		 5997 memcpy(frag->data, run->mmio.data, len);
5998
5999 if (frag->len <= 8) {
6000 /* Switch to the next fragment. */
6001 frag++;
6002 vcpu->mmio_cur_fragment++;
6003 } else {
6004 /* Go forward to the next mmio piece. */
6005 frag->data += len;
6006 frag->gpa += len;
6007 frag->len -= len;
6008 }
6009
716d51ab
GN		 6010 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6011 vcpu->mmio_needed = 0;
cef4dea0 6012 if (vcpu->mmio_is_write)
716d51ab
GN		 6013 return 1;
6014 vcpu->mmio_read_completed = 1;
6015 return complete_emulated_io(vcpu);
6016 }
87da7e66 6017
716d51ab
GN		 6018 run->exit_reason = KVM_EXIT_MMIO;
6019 run->mmio.phys_addr = frag->gpa;
6020 if (vcpu->mmio_is_write)
87da7e66
XG		 6021 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6022 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6023 run->mmio.is_write = vcpu->mmio_is_write;
6024 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6025 return 0;
5287f194
AK		 6026}
6027
716d51ab 6028
b6c7a5dc
HB		 6029int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6030{
6031 int r;
6032 sigset_t sigsaved;
6033
e5c30142
AK		 6034 if (!tsk_used_math(current) && init_fpu(current))
6035 return -ENOMEM;
6036
ac9f6dc0
AK		 6037 if (vcpu->sigset_active)
6038 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6039
a4535290 6040 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6041 kvm_vcpu_block(vcpu);
66450a21 6042 kvm_apic_accept_events(vcpu);
d7690175 6043 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6044 r = -EAGAIN;
6045 goto out;
b6c7a5dc
HB		 6046 }
6047
b6c7a5dc 6048 /* re-sync apic's tpr */
eea1cff9
AP		 6049 if (!irqchip_in_kernel(vcpu->kvm)) {
6050 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6051 r = -EINVAL;
6052 goto out;
6053 }
6054 }
b6c7a5dc 6055
716d51ab
GN		 6056 if (unlikely(vcpu->arch.complete_userspace_io)) {
6057 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6058 vcpu->arch.complete_userspace_io = NULL;
6059 r = cui(vcpu);
6060 if (r <= 0)
6061 goto out;
6062 } else
6063 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6064
851ba692 6065 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6066
6067out:
f1d86e46 6068 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6069 if (vcpu->sigset_active)
6070 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6071
b6c7a5dc
HB		 6072 return r;
6073}
6074
6075int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6076{
7ae441ea
GN		 6077 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6078 /*
6079 * We are here if userspace calls get_regs() in the middle of
6080 * instruction emulation. Registers state needs to be copied
4a969980 6081 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6082 * that usually, but some bad designed PV devices (vmware
6083 * backdoor interface) need this to work
6084 */
dd856efa 6085 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6086 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6087 }
5fdbf976
MT		 6088 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6089 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6090 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6091 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6092 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6093 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6094 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6095 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6096#ifdef CONFIG_X86_64
5fdbf976
MT		 6097 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6098 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6099 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6100 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6101 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6102 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6103 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6104 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6105#endif
6106
5fdbf976 6107 regs->rip = kvm_rip_read(vcpu);
91586a3b 6108 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6109
b6c7a5dc
HB		 6110 return 0;
6111}
6112
6113int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6114{
7ae441ea
GN		 6115 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6116 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6117
5fdbf976
MT		 6118 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6119 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6120 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6121 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6122 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6123 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6124 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6125 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6126#ifdef CONFIG_X86_64
5fdbf976
MT		 6127 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6128 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6129 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6130 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6131 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6132 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6133 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6134 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6135#endif
6136
5fdbf976 6137 kvm_rip_write(vcpu, regs->rip);
91586a3b 6138 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6139
b4f14abd
JK		 6140 vcpu->arch.exception.pending = false;
6141
3842d135
AK		 6142 kvm_make_request(KVM_REQ_EVENT, vcpu);
6143
b6c7a5dc
HB		 6144 return 0;
6145}
6146
b6c7a5dc
HB		 6147void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6148{
6149 struct kvm_segment cs;
6150
3e6e0aab 6151 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6152 *db = cs.db;
6153 *l = cs.l;
6154}
6155EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6156
6157int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6158 struct kvm_sregs *sregs)
6159{
89a27f4d 6160 struct desc_ptr dt;
b6c7a5dc 6161
3e6e0aab
GT		 6162 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6163 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6164 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6165 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6166 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6167 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6168
3e6e0aab
GT		 6169 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6170 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6171
6172 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6173 sregs->idt.limit = dt.size;
6174 sregs->idt.base = dt.address;
b6c7a5dc 6175 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6176 sregs->gdt.limit = dt.size;
6177 sregs->gdt.base = dt.address;
b6c7a5dc 6178
4d4ec087 6179 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6180 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6181 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6182 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6183 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6184 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6185 sregs->apic_base = kvm_get_apic_base(vcpu);
6186
923c61bb 6187 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6188
36752c9b 6189 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6190 set_bit(vcpu->arch.interrupt.nr,
6191 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6192
b6c7a5dc
HB		 6193 return 0;
6194}
6195
62d9f0db
MT		 6196int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6197 struct kvm_mp_state *mp_state)
6198{
66450a21 6199 kvm_apic_accept_events(vcpu);
62d9f0db 6200 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6201 return 0;
6202}
6203
6204int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6205 struct kvm_mp_state *mp_state)
6206{
66450a21
JK		 6207 if (!kvm_vcpu_has_lapic(vcpu) &&
6208 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6209 return -EINVAL;
6210
6211 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6212 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6213 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6214 } else
6215 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6216 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6217 return 0;
6218}
6219
7f3d35fd
KW		 6220int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6221 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6222{
9d74191a 6223 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6224 int ret;
e01c2426 6225
8ec4722d 6226 init_emulate_ctxt(vcpu);
c697518a 6227
7f3d35fd 6228 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6229 has_error_code, error_code);
c697518a 6230
c697518a 6231 if (ret)
19d04437 6232 return EMULATE_FAIL;
37817f29 6233
9d74191a
TY		 6234 kvm_rip_write(vcpu, ctxt->eip);
6235 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6236 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6237 return EMULATE_DONE;
37817f29
IE		 6238}
6239EXPORT_SYMBOL_GPL(kvm_task_switch);
6240
b6c7a5dc
HB		 6241int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6242 struct kvm_sregs *sregs)
6243{
6244 int mmu_reset_needed = 0;
63f42e02 6245 int pending_vec, max_bits, idx;
89a27f4d 6246 struct desc_ptr dt;
b6c7a5dc 6247
6d1068b3
PM		 6248 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6249 return -EINVAL;
6250
89a27f4d
GN		 6251 dt.size = sregs->idt.limit;
6252 dt.address = sregs->idt.base;
b6c7a5dc 6253 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6254 dt.size = sregs->gdt.limit;
6255 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6256 kvm_x86_ops->set_gdt(vcpu, &dt);
6257
ad312c7c 6258 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6259 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6260 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6261 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6262
2d3ad1f4 6263 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6264
f6801dff 6265 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6266 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6267 kvm_set_apic_base(vcpu, sregs->apic_base);
6268
4d4ec087 6269 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6270 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6271 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6272
fc78f519 6273 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6274 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6275 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6276 kvm_update_cpuid(vcpu);
63f42e02
XG		 6277
6278 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6279 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6280 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6281 mmu_reset_needed = 1;
6282 }
63f42e02 6283 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6284
6285 if (mmu_reset_needed)
6286 kvm_mmu_reset_context(vcpu);
6287
a50abc3b 6288 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6289 pending_vec = find_first_bit(
6290 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6291 if (pending_vec < max_bits) {
66fd3f7f 6292 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6293 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6294 }
6295
3e6e0aab
GT		 6296 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6297 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6298 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6299 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6300 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6301 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6302
3e6e0aab
GT		 6303 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6304 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6305
5f0269f5
ME		 6306 update_cr8_intercept(vcpu);
6307
9c3e4aab 6308 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6309 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6310 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6311 !is_protmode(vcpu))
9c3e4aab
MT		 6312 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6313
3842d135
AK		 6314 kvm_make_request(KVM_REQ_EVENT, vcpu);
6315
b6c7a5dc
HB		 6316 return 0;
6317}
6318
d0bfb940
JK		 6319int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6320 struct kvm_guest_debug *dbg)
b6c7a5dc 6321{
355be0b9 6322 unsigned long rflags;
ae675ef0 6323 int i, r;
b6c7a5dc 6324
4f926bf2
JK		 6325 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6326 r = -EBUSY;
6327 if (vcpu->arch.exception.pending)
2122ff5e 6328 goto out;
4f926bf2
JK		 6329 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6330 kvm_queue_exception(vcpu, DB_VECTOR);
6331 else
6332 kvm_queue_exception(vcpu, BP_VECTOR);
6333 }
6334
91586a3b
JK		 6335 /*
6336 * Read rflags as long as potentially injected trace flags are still
6337 * filtered out.
6338 */
6339 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6340
6341 vcpu->guest_debug = dbg->control;
6342 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6343 vcpu->guest_debug = 0;
6344
6345 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6346 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6347 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6348 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6349 } else {
6350 for (i = 0; i < KVM_NR_DB_REGS; i++)
6351 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6352 }
c8639010 6353 kvm_update_dr7(vcpu);
ae675ef0 6354
f92653ee
JK		 6355 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6356 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6357 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6358
91586a3b
JK		 6359 /*
6360 * Trigger an rflags update that will inject or remove the trace
6361 * flags.
6362 */
6363 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6364
c8639010 6365 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6366
4f926bf2 6367 r = 0;
d0bfb940 6368
2122ff5e 6369out:
b6c7a5dc
HB		 6370
6371 return r;
6372}
6373
8b006791
ZX		 6374/*
6375 * Translate a guest virtual address to a guest physical address.
6376 */
6377int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6378 struct kvm_translation *tr)
6379{
6380 unsigned long vaddr = tr->linear_address;
6381 gpa_t gpa;
f656ce01 6382 int idx;
8b006791 6383
f656ce01 6384 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6385 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6386 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6387 tr->physical_address = gpa;
6388 tr->valid = gpa != UNMAPPED_GVA;
6389 tr->writeable = 1;
6390 tr->usermode = 0;
8b006791
ZX		 6391
6392 return 0;
6393}
6394
d0752060
HB		 6395int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6396{
98918833
SY		 6397 struct i387_fxsave_struct *fxsave =
6398 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6399
d0752060
HB		 6400 memcpy(fpu->fpr, fxsave->st_space, 128);
6401 fpu->fcw = fxsave->cwd;
6402 fpu->fsw = fxsave->swd;
6403 fpu->ftwx = fxsave->twd;
6404 fpu->last_opcode = fxsave->fop;
6405 fpu->last_ip = fxsave->rip;
6406 fpu->last_dp = fxsave->rdp;
6407 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6408
d0752060
HB		 6409 return 0;
6410}
6411
6412int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6413{
98918833
SY		 6414 struct i387_fxsave_struct *fxsave =
6415 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6416
d0752060
HB		 6417 memcpy(fxsave->st_space, fpu->fpr, 128);
6418 fxsave->cwd = fpu->fcw;
6419 fxsave->swd = fpu->fsw;
6420 fxsave->twd = fpu->ftwx;
6421 fxsave->fop = fpu->last_opcode;
6422 fxsave->rip = fpu->last_ip;
6423 fxsave->rdp = fpu->last_dp;
6424 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6425
d0752060
HB		 6426 return 0;
6427}
6428
10ab25cd 6429int fx_init(struct kvm_vcpu *vcpu)
d0752060 6430{
10ab25cd
JK		 6431 int err;
6432
6433 err = fpu_alloc(&vcpu->arch.guest_fpu);
6434 if (err)
6435 return err;
6436
98918833 6437 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6438
2acf923e
DC		 6439 /*
6440 * Ensure guest xcr0 is valid for loading
6441 */
6442 vcpu->arch.xcr0 = XSTATE_FP;
6443
ad312c7c 6444 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6445
6446 return 0;
d0752060
HB		 6447}
6448EXPORT_SYMBOL_GPL(fx_init);
6449
98918833
SY		 6450static void fx_free(struct kvm_vcpu *vcpu)
6451{
6452 fpu_free(&vcpu->arch.guest_fpu);
6453}
6454
d0752060
HB		 6455void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6456{
2608d7a1 6457 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6458 return;
6459
2acf923e
DC		 6460 /*
6461 * Restore all possible states in the guest,
6462 * and assume host would use all available bits.
6463 * Guest xcr0 would be loaded later.
6464 */
6465 kvm_put_guest_xcr0(vcpu);
d0752060 6466 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6467 __kernel_fpu_begin();
98918833 6468 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6469 trace_kvm_fpu(1);
d0752060 6470}
d0752060
HB		 6471
6472void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6473{
2acf923e
DC		 6474 kvm_put_guest_xcr0(vcpu);
6475
d0752060
HB		 6476 if (!vcpu->guest_fpu_loaded)
6477 return;
6478
6479 vcpu->guest_fpu_loaded = 0;
98918833 6480 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6481 __kernel_fpu_end();
f096ed85 6482 ++vcpu->stat.fpu_reload;
a8eeb04a 6483 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6484 trace_kvm_fpu(0);
d0752060 6485}
e9b11c17
ZX		 6486
6487void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6488{
12f9a48f 6489 kvmclock_reset(vcpu);
7f1ea208 6490
f5f48ee1 6491 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6492 fx_free(vcpu);
e9b11c17
ZX		 6493 kvm_x86_ops->vcpu_free(vcpu);
6494}
6495
6496struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6497 unsigned int id)
6498{
6755bae8
ZA		 6499 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6500 printk_once(KERN_WARNING
6501 "kvm: SMP vm created on host with unstable TSC; "
6502 "guest TSC will not be reliable\n");
26e5215f
AK		 6503 return kvm_x86_ops->vcpu_create(kvm, id);
6504}
e9b11c17 6505
26e5215f
AK		 6506int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6507{
6508 int r;
e9b11c17 6509
0bed3b56 6510 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6511 r = vcpu_load(vcpu);
6512 if (r)
6513 return r;
57f252f2
JK		 6514 kvm_vcpu_reset(vcpu);
6515 r = kvm_mmu_setup(vcpu);
e9b11c17 6516 vcpu_put(vcpu);
e9b11c17 6517
26e5215f 6518 return r;
e9b11c17
ZX		 6519}
6520
42897d86
MT		 6521int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6522{
6523 int r;
8fe8ab46 6524 struct msr_data msr;
42897d86
MT		 6525
6526 r = vcpu_load(vcpu);
6527 if (r)
6528 return r;
8fe8ab46
WA		 6529 msr.data = 0x0;
6530 msr.index = MSR_IA32_TSC;
6531 msr.host_initiated = true;
6532 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6533 vcpu_put(vcpu);
6534
6535 return r;
6536}
6537
d40ccc62 6538void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6539{
9fc77441 6540 int r;
344d9588
GN		 6541 vcpu->arch.apf.msr_val = 0;
6542
9fc77441
MT		 6543 r = vcpu_load(vcpu);
6544 BUG_ON(r);
e9b11c17
ZX		 6545 kvm_mmu_unload(vcpu);
6546 vcpu_put(vcpu);
6547
98918833 6548 fx_free(vcpu);
e9b11c17
ZX		 6549 kvm_x86_ops->vcpu_free(vcpu);
6550}
6551
66450a21 6552void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6553{
7460fb4a
AK		 6554 atomic_set(&vcpu->arch.nmi_queued, 0);
6555 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6556 vcpu->arch.nmi_injected = false;
6557
42dbaa5a
JK		 6558 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6559 vcpu->arch.dr6 = DR6_FIXED_1;
6560 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6561 kvm_update_dr7(vcpu);
42dbaa5a 6562
3842d135 6563 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6564 vcpu->arch.apf.msr_val = 0;
c9aaa895 6565 vcpu->arch.st.msr_val = 0;
3842d135 6566
12f9a48f
GC		 6567 kvmclock_reset(vcpu);
6568
af585b92
GN		 6569 kvm_clear_async_pf_completion_queue(vcpu);
6570 kvm_async_pf_hash_reset(vcpu);
6571 vcpu->arch.apf.halted = false;
3842d135 6572
f5132b01
GN		 6573 kvm_pmu_reset(vcpu);
6574
66f7b72e
JS		 6575 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6576 vcpu->arch.regs_avail = ~0;
6577 vcpu->arch.regs_dirty = ~0;
6578
57f252f2 6579 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6580}
6581
66450a21
JK		 6582void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6583{
6584 struct kvm_segment cs;
6585
6586 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6587 cs.selector = vector << 8;
6588 cs.base = vector << 12;
6589 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6590 kvm_rip_write(vcpu, 0);
6591}
6592
10474ae8 6593int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6594{
ca84d1a2
ZA		 6595 struct kvm *kvm;
6596 struct kvm_vcpu *vcpu;
6597 int i;
0dd6a6ed
ZA		 6598 int ret;
6599 u64 local_tsc;
6600 u64 max_tsc = 0;
6601 bool stable, backwards_tsc = false;
18863bdd
AK		 6602
6603 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6604 ret = kvm_x86_ops->hardware_enable(garbage);
6605 if (ret != 0)
6606 return ret;
6607
6608 local_tsc = native_read_tsc();
6609 stable = !check_tsc_unstable();
6610 list_for_each_entry(kvm, &vm_list, vm_list) {
6611 kvm_for_each_vcpu(i, vcpu, kvm) {
6612 if (!stable && vcpu->cpu == smp_processor_id())
6613 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6614 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6615 backwards_tsc = true;
6616 if (vcpu->arch.last_host_tsc > max_tsc)
6617 max_tsc = vcpu->arch.last_host_tsc;
6618 }
6619 }
6620 }
6621
6622 /*
6623 * Sometimes, even reliable TSCs go backwards. This happens on
6624 * platforms that reset TSC during suspend or hibernate actions, but
6625 * maintain synchronization. We must compensate. Fortunately, we can
6626 * detect that condition here, which happens early in CPU bringup,
6627 * before any KVM threads can be running. Unfortunately, we can't
6628 * bring the TSCs fully up to date with real time, as we aren't yet far
6629 * enough into CPU bringup that we know how much real time has actually
6630 * elapsed; our helper function, get_kernel_ns() will be using boot
6631 * variables that haven't been updated yet.
6632 *
6633 * So we simply find the maximum observed TSC above, then record the
6634 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6635 * the adjustment will be applied. Note that we accumulate
6636 * adjustments, in case multiple suspend cycles happen before some VCPU
6637 * gets a chance to run again. In the event that no KVM threads get a
6638 * chance to run, we will miss the entire elapsed period, as we'll have
6639 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6640 * loose cycle time. This isn't too big a deal, since the loss will be
6641 * uniform across all VCPUs (not to mention the scenario is extremely
6642 * unlikely). It is possible that a second hibernate recovery happens
6643 * much faster than a first, causing the observed TSC here to be
6644 * smaller; this would require additional padding adjustment, which is
6645 * why we set last_host_tsc to the local tsc observed here.
6646 *
6647 * N.B. - this code below runs only on platforms with reliable TSC,
6648 * as that is the only way backwards_tsc is set above. Also note
6649 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6650 * have the same delta_cyc adjustment applied if backwards_tsc
6651 * is detected. Note further, this adjustment is only done once,
6652 * as we reset last_host_tsc on all VCPUs to stop this from being
6653 * called multiple times (one for each physical CPU bringup).
6654 *
4a969980 6655 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6656 * will be compensated by the logic in vcpu_load, which sets the TSC to
6657 * catchup mode. This will catchup all VCPUs to real time, but cannot
6658 * guarantee that they stay in perfect synchronization.
6659 */
6660 if (backwards_tsc) {
6661 u64 delta_cyc = max_tsc - local_tsc;
6662 list_for_each_entry(kvm, &vm_list, vm_list) {
6663 kvm_for_each_vcpu(i, vcpu, kvm) {
6664 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6665 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6666 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6667 &vcpu->requests);
0dd6a6ed
ZA		 6668 }
6669
6670 /*
6671 * We have to disable TSC offset matching.. if you were
6672 * booting a VM while issuing an S4 host suspend....
6673 * you may have some problem. Solving this issue is
6674 * left as an exercise to the reader.
6675 */
6676 kvm->arch.last_tsc_nsec = 0;
6677 kvm->arch.last_tsc_write = 0;
6678 }
6679
6680 }
6681 return 0;
e9b11c17
ZX		 6682}
6683
6684void kvm_arch_hardware_disable(void *garbage)
6685{
6686 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6687 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6688}
6689
6690int kvm_arch_hardware_setup(void)
6691{
6692 return kvm_x86_ops->hardware_setup();
6693}
6694
6695void kvm_arch_hardware_unsetup(void)
6696{
6697 kvm_x86_ops->hardware_unsetup();
6698}
6699
6700void kvm_arch_check_processor_compat(void *rtn)
6701{
6702 kvm_x86_ops->check_processor_compatibility(rtn);
6703}
6704
3e515705
AK		 6705bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6706{
6707 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6708}
6709
54e9818f
GN		 6710struct static_key kvm_no_apic_vcpu __read_mostly;
6711
e9b11c17
ZX		 6712int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6713{
6714 struct page *page;
6715 struct kvm *kvm;
6716 int r;
6717
6718 BUG_ON(vcpu->kvm == NULL);
6719 kvm = vcpu->kvm;
6720
9aabc88f 6721 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6722 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6723 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6724 else
a4535290 6725 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6726
6727 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6728 if (!page) {
6729 r = -ENOMEM;
6730 goto fail;
6731 }
ad312c7c 6732 vcpu->arch.pio_data = page_address(page);
e9b11c17 6733
cc578287 6734 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6735
e9b11c17
ZX		 6736 r = kvm_mmu_create(vcpu);
6737 if (r < 0)
6738 goto fail_free_pio_data;
6739
6740 if (irqchip_in_kernel(kvm)) {
6741 r = kvm_create_lapic(vcpu);
6742 if (r < 0)
6743 goto fail_mmu_destroy;
54e9818f
GN		 6744 } else
6745 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6746
890ca9ae
HY		 6747 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6748 GFP_KERNEL);
6749 if (!vcpu->arch.mce_banks) {
6750 r = -ENOMEM;
443c39bc 6751 goto fail_free_lapic;
890ca9ae
HY		 6752 }
6753 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6754
f1797359
WY		 6755 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6756 r = -ENOMEM;
f5f48ee1 6757 goto fail_free_mce_banks;
f1797359 6758 }
f5f48ee1 6759
66f7b72e
JS		 6760 r = fx_init(vcpu);
6761 if (r)
6762 goto fail_free_wbinvd_dirty_mask;
6763
ba904635 6764 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6765 vcpu->arch.pv_time_enabled = false;
af585b92 6766 kvm_async_pf_hash_reset(vcpu);
f5132b01 6767 kvm_pmu_init(vcpu);
af585b92 6768
e9b11c17 6769 return 0;
66f7b72e
JS		 6770fail_free_wbinvd_dirty_mask:
6771 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6772fail_free_mce_banks:
6773 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6774fail_free_lapic:
6775 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6776fail_mmu_destroy:
6777 kvm_mmu_destroy(vcpu);
6778fail_free_pio_data:
ad312c7c 6779 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6780fail:
6781 return r;
6782}
6783
6784void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6785{
f656ce01
MT		 6786 int idx;
6787
f5132b01 6788 kvm_pmu_destroy(vcpu);
36cb93fd 6789 kfree(vcpu->arch.mce_banks);
e9b11c17 6790 kvm_free_lapic(vcpu);
f656ce01 6791 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6792 kvm_mmu_destroy(vcpu);
f656ce01 6793 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6794 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6795 if (!irqchip_in_kernel(vcpu->kvm))
6796 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6797}
d19a9cd2 6798
e08b9637 6799int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6800{
e08b9637
CO		 6801 if (type)
6802 return -EINVAL;
6803
f05e70ac 6804 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6805 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6806
5550af4d
SY		 6807 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6808 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6809 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6810 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6811 &kvm->arch.irq_sources_bitmap);
5550af4d 6812
038f8c11 6813 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6814 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6815 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6816
6817 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6818
d89f5eff 6819 return 0;
d19a9cd2
ZX		 6820}
6821
6822static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6823{
9fc77441
MT		 6824 int r;
6825 r = vcpu_load(vcpu);
6826 BUG_ON(r);
d19a9cd2
ZX		 6827 kvm_mmu_unload(vcpu);
6828 vcpu_put(vcpu);
6829}
6830
6831static void kvm_free_vcpus(struct kvm *kvm)
6832{
6833 unsigned int i;
988a2cae 6834 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6835
6836 /*
6837 * Unpin any mmu pages first.
6838 */
af585b92
GN		 6839 kvm_for_each_vcpu(i, vcpu, kvm) {
6840 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6841 kvm_unload_vcpu_mmu(vcpu);
af585b92 6842 }
988a2cae
GN		 6843 kvm_for_each_vcpu(i, vcpu, kvm)
6844 kvm_arch_vcpu_free(vcpu);
6845
6846 mutex_lock(&kvm->lock);
6847 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6848 kvm->vcpus[i] = NULL;
d19a9cd2 6849
988a2cae
GN		 6850 atomic_set(&kvm->online_vcpus, 0);
6851 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6852}
6853
ad8ba2cd
SY		 6854void kvm_arch_sync_events(struct kvm *kvm)
6855{
ba4cef31 6856 kvm_free_all_assigned_devices(kvm);
aea924f6 6857 kvm_free_pit(kvm);
ad8ba2cd
SY		 6858}
6859
d19a9cd2
ZX		 6860void kvm_arch_destroy_vm(struct kvm *kvm)
6861{
27469d29
AH		 6862 if (current->mm == kvm->mm) {
6863 /*
6864 * Free memory regions allocated on behalf of userspace,
6865 * unless the the memory map has changed due to process exit
6866 * or fd copying.
6867 */
6868 struct kvm_userspace_memory_region mem;
6869 memset(&mem, 0, sizeof(mem));
6870 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6871 kvm_set_memory_region(kvm, &mem);
6872
6873 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6874 kvm_set_memory_region(kvm, &mem);
6875
6876 mem.slot = TSS_PRIVATE_MEMSLOT;
6877 kvm_set_memory_region(kvm, &mem);
6878 }
6eb55818 6879 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6880 kfree(kvm->arch.vpic);
6881 kfree(kvm->arch.vioapic);
d19a9cd2 6882 kvm_free_vcpus(kvm);
3d45830c
AK		 6883 if (kvm->arch.apic_access_page)
6884 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6885 if (kvm->arch.ept_identity_pagetable)
6886 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6887 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6888}
0de10343 6889
db3fe4eb
TY		 6890void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6891 struct kvm_memory_slot *dont)
6892{
6893 int i;
6894
d89cc617
TY		 6895 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6896 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6897 kvm_kvfree(free->arch.rmap[i]);
6898 free->arch.rmap[i] = NULL;
77d11309 6899 }
d89cc617
TY		 6900 if (i == 0)
6901 continue;
6902
6903 if (!dont || free->arch.lpage_info[i - 1] !=
6904 dont->arch.lpage_info[i - 1]) {
6905 kvm_kvfree(free->arch.lpage_info[i - 1]);
6906 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6907 }
6908 }
6909}
6910
6911int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6912{
6913 int i;
6914
d89cc617 6915 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6916 unsigned long ugfn;
6917 int lpages;
d89cc617 6918 int level = i + 1;
db3fe4eb
TY		 6919
6920 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6921 slot->base_gfn, level) + 1;
6922
d89cc617
TY		 6923 slot->arch.rmap[i] =
6924 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6925 if (!slot->arch.rmap[i])
77d11309 6926 goto out_free;
d89cc617
TY		 6927 if (i == 0)
6928 continue;
77d11309 6929
d89cc617
TY		 6930 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6931 sizeof(*slot->arch.lpage_info[i - 1]));
6932 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6933 goto out_free;
6934
6935 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6936 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6937 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6938 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6939 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6940 /*
6941 * If the gfn and userspace address are not aligned wrt each
6942 * other, or if explicitly asked to, disable large page
6943 * support for this slot
6944 */
6945 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6946 !kvm_largepages_enabled()) {
6947 unsigned long j;
6948
6949 for (j = 0; j < lpages; ++j)
d89cc617 6950 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6951 }
6952 }
6953
6954 return 0;
6955
6956out_free:
d89cc617
TY		 6957 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6958 kvm_kvfree(slot->arch.rmap[i]);
6959 slot->arch.rmap[i] = NULL;
6960 if (i == 0)
6961 continue;
6962
6963 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6964 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6965 }
6966 return -ENOMEM;
6967}
6968
f7784b8e
MT		 6969int kvm_arch_prepare_memory_region(struct kvm *kvm,
6970 struct kvm_memory_slot *memslot,
7b6195a9
TY		 6971 struct kvm_userspace_memory_region *mem,
6972 enum kvm_mr_change change)
0de10343 6973{
7a905b14
TY		 6974 /*
6975 * Only private memory slots need to be mapped here since
6976 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 6977 */
7b6195a9 6978 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 6979 unsigned long userspace_addr;
604b38ac 6980
7a905b14
TY		 6981 /*
6982 * MAP_SHARED to prevent internal slot pages from being moved
6983 * by fork()/COW.
6984 */
7b6195a9 6985 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 6986 PROT_READ | PROT_WRITE,
6987 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 6988
7a905b14
TY		 6989 if (IS_ERR((void *)userspace_addr))
6990 return PTR_ERR((void *)userspace_addr);
604b38ac 6991
7a905b14 6992 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6993 }
6994
f7784b8e
MT		 6995 return 0;
6996}
6997
6998void kvm_arch_commit_memory_region(struct kvm *kvm,
6999 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7000 const struct kvm_memory_slot *old,
7001 enum kvm_mr_change change)
f7784b8e
MT		 7002{
7003
8482644a 7004 int nr_mmu_pages = 0;
f7784b8e 7005
8482644a 7006 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7007 int ret;
7008
8482644a
TY		 7009 ret = vm_munmap(old->userspace_addr,
7010 old->npages * PAGE_SIZE);
f7784b8e
MT		 7011 if (ret < 0)
7012 printk(KERN_WARNING
7013 "kvm_vm_ioctl_set_memory_region: "
7014 "failed to munmap memory\n");
7015 }
7016
48c0e4e9
XG		 7017 if (!kvm->arch.n_requested_mmu_pages)
7018 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7019
48c0e4e9 7020 if (nr_mmu_pages)
0de10343 7021 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7022 /*
7023 * Write protect all pages for dirty logging.
7024 * Existing largepage mappings are destroyed here and new ones will
7025 * not be created until the end of the logging.
7026 */
8482644a 7027 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7028 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3b4dc3a0
MT		 7029 /*
7030 * If memory slot is created, or moved, we need to clear all
7031 * mmio sptes.
7032 */
8482644a 7033 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
982b3394 7034 kvm_mmu_zap_mmio_sptes(kvm);
3b4dc3a0
MT		 7035 kvm_reload_remote_mmus(kvm);
7036 }
0de10343 7037}
1d737c8a 7038
2df72e9b 7039void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 7040{
7041 kvm_mmu_zap_all(kvm);
8986ecc0 7042 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 7043}
7044
2df72e9b
MT		 7045void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7046 struct kvm_memory_slot *slot)
7047{
7048 kvm_arch_flush_shadow_all(kvm);
7049}
7050
1d737c8a
ZX		 7051int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7052{
af585b92
GN		 7053 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7054 !vcpu->arch.apf.halted)
7055 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7056 || kvm_apic_has_events(vcpu)
7460fb4a 7057 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7058 (kvm_arch_interrupt_allowed(vcpu) &&
7059 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7060}
5736199a 7061
b6d33834 7062int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7063{
b6d33834 7064 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7065}
78646121
GN		 7066
7067int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7068{
7069 return kvm_x86_ops->interrupt_allowed(vcpu);
7070}
229456fc 7071
f92653ee
JK		 7072bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7073{
7074 unsigned long current_rip = kvm_rip_read(vcpu) +
7075 get_segment_base(vcpu, VCPU_SREG_CS);
7076
7077 return current_rip == linear_rip;
7078}
7079EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7080
94fe45da
JK		 7081unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7082{
7083 unsigned long rflags;
7084
7085 rflags = kvm_x86_ops->get_rflags(vcpu);
7086 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7087 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7088 return rflags;
7089}
7090EXPORT_SYMBOL_GPL(kvm_get_rflags);
7091
7092void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7093{
7094 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7095 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7096 rflags |= X86_EFLAGS_TF;
94fe45da 7097 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7098 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7099}
7100EXPORT_SYMBOL_GPL(kvm_set_rflags);
7101
56028d08
GN		 7102void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7103{
7104 int r;
7105
fb67e14f 7106 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7107 is_error_page(work->page))
56028d08
GN		 7108 return;
7109
7110 r = kvm_mmu_reload(vcpu);
7111 if (unlikely(r))
7112 return;
7113
fb67e14f
XG		 7114 if (!vcpu->arch.mmu.direct_map &&
7115 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7116 return;
7117
56028d08
GN		 7118 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7119}
7120
af585b92
GN		 7121static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7122{
7123 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7124}
7125
7126static inline u32 kvm_async_pf_next_probe(u32 key)
7127{
7128 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7129}
7130
7131static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7132{
7133 u32 key = kvm_async_pf_hash_fn(gfn);
7134
7135 while (vcpu->arch.apf.gfns[key] != ~0)
7136 key = kvm_async_pf_next_probe(key);
7137
7138 vcpu->arch.apf.gfns[key] = gfn;
7139}
7140
7141static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7142{
7143 int i;
7144 u32 key = kvm_async_pf_hash_fn(gfn);
7145
7146 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7147 (vcpu->arch.apf.gfns[key] != gfn &&
7148 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7149 key = kvm_async_pf_next_probe(key);
7150
7151 return key;
7152}
7153
7154bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7155{
7156 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7157}
7158
7159static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7160{
7161 u32 i, j, k;
7162
7163 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7164 while (true) {
7165 vcpu->arch.apf.gfns[i] = ~0;
7166 do {
7167 j = kvm_async_pf_next_probe(j);
7168 if (vcpu->arch.apf.gfns[j] == ~0)
7169 return;
7170 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7171 /*
7172 * k lies cyclically in ]i,j]
7173 * | i.k.j |
7174 * |....j i.k.| or |.k..j i...|
7175 */
7176 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7177 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7178 i = j;
7179 }
7180}
7181
7c90705b
GN		 7182static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7183{
7184
7185 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7186 sizeof(val));
7187}
7188
af585b92
GN		 7189void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7190 struct kvm_async_pf *work)
7191{
6389ee94
AK		 7192 struct x86_exception fault;
7193
7c90705b 7194 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7195 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7196
7197 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7198 (vcpu->arch.apf.send_user_only &&
7199 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7200 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7201 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7202 fault.vector = PF_VECTOR;
7203 fault.error_code_valid = true;
7204 fault.error_code = 0;
7205 fault.nested_page_fault = false;
7206 fault.address = work->arch.token;
7207 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7208 }
af585b92
GN		 7209}
7210
7211void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7212 struct kvm_async_pf *work)
7213{
6389ee94
AK		 7214 struct x86_exception fault;
7215
7c90705b
GN		 7216 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7217 if (is_error_page(work->page))
7218 work->arch.token = ~0; /* broadcast wakeup */
7219 else
7220 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7221
7222 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7223 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7224 fault.vector = PF_VECTOR;
7225 fault.error_code_valid = true;
7226 fault.error_code = 0;
7227 fault.nested_page_fault = false;
7228 fault.address = work->arch.token;
7229 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7230 }
e6d53e3b 7231 vcpu->arch.apf.halted = false;
a4fa1635 7232 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7233}
7234
7235bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7236{
7237 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7238 return true;
7239 else
7240 return !kvm_event_needs_reinjection(vcpu) &&
7241 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7242}
7243
229456fc
MT		 7244EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7245EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7246EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7247EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7248EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7249EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7250EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7251EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7252EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7253EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7254EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7255EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)