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add support for Hyper-V reference time counter
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
261{
262 /* TODO: reserve bits check */
8a5a87d9 263 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 264}
265EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266
e3ba45b8
GL		 267asmlinkage void kvm_spurious_fault(void)
268{
269 /* Fault while not rebooting. We want the trace. */
270 BUG();
271}
272EXPORT_SYMBOL_GPL(kvm_spurious_fault);
273
3fd28fce
ED		 274#define EXCPT_BENIGN 0
275#define EXCPT_CONTRIBUTORY 1
276#define EXCPT_PF 2
277
278static int exception_class(int vector)
279{
280 switch (vector) {
281 case PF_VECTOR:
282 return EXCPT_PF;
283 case DE_VECTOR:
284 case TS_VECTOR:
285 case NP_VECTOR:
286 case SS_VECTOR:
287 case GP_VECTOR:
288 return EXCPT_CONTRIBUTORY;
289 default:
290 break;
291 }
292 return EXCPT_BENIGN;
293}
294
295static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 296 unsigned nr, bool has_error, u32 error_code,
297 bool reinject)
3fd28fce
ED		 298{
299 u32 prev_nr;
300 int class1, class2;
301
3842d135
AK		 302 kvm_make_request(KVM_REQ_EVENT, vcpu);
303
3fd28fce
ED		 304 if (!vcpu->arch.exception.pending) {
305 queue:
306 vcpu->arch.exception.pending = true;
307 vcpu->arch.exception.has_error_code = has_error;
308 vcpu->arch.exception.nr = nr;
309 vcpu->arch.exception.error_code = error_code;
3f0fd292 310 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 311 return;
312 }
313
314 /* to check exception */
315 prev_nr = vcpu->arch.exception.nr;
316 if (prev_nr == DF_VECTOR) {
317 /* triple fault -> shutdown */
a8eeb04a 318 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 319 return;
320 }
321 class1 = exception_class(prev_nr);
322 class2 = exception_class(nr);
323 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
324 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
325 /* generate double fault per SDM Table 5-5 */
326 vcpu->arch.exception.pending = true;
327 vcpu->arch.exception.has_error_code = true;
328 vcpu->arch.exception.nr = DF_VECTOR;
329 vcpu->arch.exception.error_code = 0;
330 } else
331 /* replace previous exception with a new one in a hope
332 that instruction re-execution will regenerate lost
333 exception */
334 goto queue;
335}
336
298101da
AK		 337void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
338{
ce7ddec4 339 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 340}
341EXPORT_SYMBOL_GPL(kvm_queue_exception);
342
ce7ddec4
JR		 343void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
344{
345 kvm_multiple_exception(vcpu, nr, false, 0, true);
346}
347EXPORT_SYMBOL_GPL(kvm_requeue_exception);
348
db8fcefa 349void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 350{
db8fcefa
AP		 351 if (err)
352 kvm_inject_gp(vcpu, 0);
353 else
354 kvm_x86_ops->skip_emulated_instruction(vcpu);
355}
356EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 357
6389ee94 358void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 359{
360 ++vcpu->stat.pf_guest;
6389ee94
AK		 361 vcpu->arch.cr2 = fault->address;
362 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 363}
27d6c865 364EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 365
6389ee94 366void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 367{
6389ee94
AK		 368 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
369 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 370 else
6389ee94 371 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 372}
373
3419ffc8
SY		 374void kvm_inject_nmi(struct kvm_vcpu *vcpu)
375{
7460fb4a
AK		 376 atomic_inc(&vcpu->arch.nmi_queued);
377 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 378}
379EXPORT_SYMBOL_GPL(kvm_inject_nmi);
380
298101da
AK		 381void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
382{
ce7ddec4 383 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 384}
385EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
386
ce7ddec4
JR		 387void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
388{
389 kvm_multiple_exception(vcpu, nr, true, error_code, true);
390}
391EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
392
0a79b009
AK		 393/*
394 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
395 * a #GP and return false.
396 */
397bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 398{
0a79b009
AK		 399 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
400 return true;
401 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
402 return false;
298101da 403}
0a79b009 404EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 405
ec92fe44
JR		 406/*
407 * This function will be used to read from the physical memory of the currently
408 * running guest. The difference to kvm_read_guest_page is that this function
409 * can read from guest physical or from the guest's guest physical memory.
410 */
411int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
412 gfn_t ngfn, void *data, int offset, int len,
413 u32 access)
414{
415 gfn_t real_gfn;
416 gpa_t ngpa;
417
418 ngpa = gfn_to_gpa(ngfn);
419 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
420 if (real_gfn == UNMAPPED_GVA)
421 return -EFAULT;
422
423 real_gfn = gpa_to_gfn(real_gfn);
424
425 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
426}
427EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
428
3d06b8bf
JR		 429int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
430 void *data, int offset, int len, u32 access)
431{
432 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
433 data, offset, len, access);
434}
435
a03490ed
CO		 436/*
437 * Load the pae pdptrs. Return true is they are all valid.
438 */
ff03a073 439int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 440{
441 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
442 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
443 int i;
444 int ret;
ff03a073 445 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 446
ff03a073
JR		 447 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
448 offset * sizeof(u64), sizeof(pdpte),
449 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 450 if (ret < 0) {
451 ret = 0;
452 goto out;
453 }
454 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 455 if (is_present_gpte(pdpte[i]) &&
20c466b5 456 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 457 ret = 0;
458 goto out;
459 }
460 }
461 ret = 1;
462
ff03a073 463 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 464 __set_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail);
466 __set_bit(VCPU_EXREG_PDPTR,
467 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 468out:
a03490ed
CO		 469
470 return ret;
471}
cc4b6871 472EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 473
d835dfec
AK		 474static bool pdptrs_changed(struct kvm_vcpu *vcpu)
475{
ff03a073 476 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 477 bool changed = true;
3d06b8bf
JR		 478 int offset;
479 gfn_t gfn;
d835dfec
AK		 480 int r;
481
482 if (is_long_mode(vcpu) || !is_pae(vcpu))
483 return false;
484
6de4f3ad
AK		 485 if (!test_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_avail))
487 return true;
488
9f8fe504
AK		 489 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
490 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 491 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
492 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 493 if (r < 0)
494 goto out;
ff03a073 495 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 496out:
d835dfec
AK		 497
498 return changed;
499}
500
49a9b07e 501int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 502{
aad82703
SY		 503 unsigned long old_cr0 = kvm_read_cr0(vcpu);
504 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
505 X86_CR0_CD | X86_CR0_NW;
506
f9a48e6a
AK		 507 cr0 |= X86_CR0_ET;
508
ab344828 509#ifdef CONFIG_X86_64
0f12244f
GN		 510 if (cr0 & 0xffffffff00000000UL)
511 return 1;
ab344828
GN		 512#endif
513
514 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
517 return 1;
a03490ed 518
0f12244f
GN		 519 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
520 return 1;
a03490ed
CO		 521
522 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
523#ifdef CONFIG_X86_64
f6801dff 524 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 525 int cs_db, cs_l;
526
0f12244f
GN		 527 if (!is_pae(vcpu))
528 return 1;
a03490ed 529 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 530 if (cs_l)
531 return 1;
a03490ed
CO		 532 } else
533#endif
ff03a073 534 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 535 kvm_read_cr3(vcpu)))
0f12244f 536 return 1;
a03490ed
CO		 537 }
538
ad756a16
MJ		 539 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
540 return 1;
541
a03490ed 542 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 543
d170c419 544 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 545 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 546 kvm_async_pf_hash_reset(vcpu);
547 }
e5f3f027 548
aad82703
SY		 549 if ((cr0 ^ old_cr0) & update_bits)
550 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 551 return 0;
552}
2d3ad1f4 553EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 554
2d3ad1f4 555void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 556{
49a9b07e 557 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 558}
2d3ad1f4 559EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 560
42bdf991
MT		 561static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
562{
563 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
564 !vcpu->guest_xcr0_loaded) {
565 /* kvm_set_xcr() also depends on this */
566 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
567 vcpu->guest_xcr0_loaded = 1;
568 }
569}
570
571static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
572{
573 if (vcpu->guest_xcr0_loaded) {
574 if (vcpu->arch.xcr0 != host_xcr0)
575 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
576 vcpu->guest_xcr0_loaded = 0;
577 }
578}
579
2acf923e
DC		 580int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
581{
582 u64 xcr0;
46c34cb0 583 u64 valid_bits;
2acf923e
DC		 584
585 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
586 if (index != XCR_XFEATURE_ENABLED_MASK)
587 return 1;
588 xcr0 = xcr;
2acf923e
DC		 589 if (!(xcr0 & XSTATE_FP))
590 return 1;
591 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
592 return 1;
46c34cb0
PB		 593
594 /*
595 * Do not allow the guest to set bits that we do not support
596 * saving. However, xcr0 bit 0 is always set, even if the
597 * emulated CPU does not support XSAVE (see fx_init).
598 */
599 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
600 if (xcr0 & ~valid_bits)
2acf923e 601 return 1;
46c34cb0 602
42bdf991 603 kvm_put_guest_xcr0(vcpu);
2acf923e 604 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 605 return 0;
606}
607
608int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
609{
764bcbc5
Z		 610 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
611 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 612 kvm_inject_gp(vcpu, 0);
613 return 1;
614 }
615 return 0;
616}
617EXPORT_SYMBOL_GPL(kvm_set_xcr);
618
a83b29c6 619int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 620{
fc78f519 621 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 622 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
623 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 624 if (cr4 & CR4_RESERVED_BITS)
625 return 1;
a03490ed 626
2acf923e
DC		 627 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
628 return 1;
629
c68b734f
YW		 630 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
631 return 1;
632
afcbf13f 633 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 634 return 1;
635
a03490ed 636 if (is_long_mode(vcpu)) {
0f12244f
GN		 637 if (!(cr4 & X86_CR4_PAE))
638 return 1;
a2edf57f
AK		 639 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
640 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 641 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
642 kvm_read_cr3(vcpu)))
0f12244f
GN		 643 return 1;
644
ad756a16
MJ		 645 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
646 if (!guest_cpuid_has_pcid(vcpu))
647 return 1;
648
649 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
650 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
651 return 1;
652 }
653
5e1746d6 654 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 655 return 1;
a03490ed 656
ad756a16
MJ		 657 if (((cr4 ^ old_cr4) & pdptr_bits) ||
658 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 659 kvm_mmu_reset_context(vcpu);
0f12244f 660
2acf923e 661 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 662 kvm_update_cpuid(vcpu);
2acf923e 663
0f12244f
GN		 664 return 0;
665}
2d3ad1f4 666EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 667
2390218b 668int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 669{
9f8fe504 670 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 671 kvm_mmu_sync_roots(vcpu);
d835dfec 672 kvm_mmu_flush_tlb(vcpu);
0f12244f 673 return 0;
d835dfec
AK		 674 }
675
a03490ed 676 if (is_long_mode(vcpu)) {
471842ec 677 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 678 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
679 return 1;
680 } else
681 if (cr3 & CR3_L_MODE_RESERVED_BITS)
682 return 1;
a03490ed
CO		 683 } else {
684 if (is_pae(vcpu)) {
0f12244f
GN		 685 if (cr3 & CR3_PAE_RESERVED_BITS)
686 return 1;
ff03a073
JR		 687 if (is_paging(vcpu) &&
688 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 689 return 1;
a03490ed
CO		 690 }
691 /*
692 * We don't check reserved bits in nonpae mode, because
693 * this isn't enforced, and VMware depends on this.
694 */
695 }
696
0f12244f 697 vcpu->arch.cr3 = cr3;
aff48baa 698 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 699 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 703
eea1cff9 704int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 705{
0f12244f
GN		 706 if (cr8 & CR8_RESERVED_BITS)
707 return 1;
a03490ed
CO		 708 if (irqchip_in_kernel(vcpu->kvm))
709 kvm_lapic_set_tpr(vcpu, cr8);
710 else
ad312c7c 711 vcpu->arch.cr8 = cr8;
0f12244f
GN		 712 return 0;
713}
2d3ad1f4 714EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 715
2d3ad1f4 716unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 717{
718 if (irqchip_in_kernel(vcpu->kvm))
719 return kvm_lapic_get_cr8(vcpu);
720 else
ad312c7c 721 return vcpu->arch.cr8;
a03490ed 722}
2d3ad1f4 723EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 724
c8639010
JK		 725static void kvm_update_dr7(struct kvm_vcpu *vcpu)
726{
727 unsigned long dr7;
728
729 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
730 dr7 = vcpu->arch.guest_debug_dr7;
731 else
732 dr7 = vcpu->arch.dr7;
733 kvm_x86_ops->set_dr7(vcpu, dr7);
734 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
735}
736
338dbc97 737static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 738{
739 switch (dr) {
740 case 0 ... 3:
741 vcpu->arch.db[dr] = val;
742 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
743 vcpu->arch.eff_db[dr] = val;
744 break;
745 case 4:
338dbc97
GN		 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
747 return 1; /* #UD */
020df079
GN		 748 /* fall through */
749 case 6:
338dbc97
GN		 750 if (val & 0xffffffff00000000ULL)
751 return -1; /* #GP */
020df079
GN		 752 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
753 break;
754 case 5:
338dbc97
GN		 755 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
756 return 1; /* #UD */
020df079
GN		 757 /* fall through */
758 default: /* 7 */
338dbc97
GN		 759 if (val & 0xffffffff00000000ULL)
760 return -1; /* #GP */
020df079 761 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 762 kvm_update_dr7(vcpu);
020df079
GN		 763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
770{
771 int res;
772
773 res = __kvm_set_dr(vcpu, dr, val);
774 if (res > 0)
775 kvm_queue_exception(vcpu, UD_VECTOR);
776 else if (res < 0)
777 kvm_inject_gp(vcpu, 0);
778
779 return res;
780}
020df079
GN		 781EXPORT_SYMBOL_GPL(kvm_set_dr);
782
338dbc97 783static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 784{
785 switch (dr) {
786 case 0 ... 3:
787 *val = vcpu->arch.db[dr];
788 break;
789 case 4:
338dbc97 790 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 791 return 1;
020df079
GN		 792 /* fall through */
793 case 6:
794 *val = vcpu->arch.dr6;
795 break;
796 case 5:
338dbc97 797 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 798 return 1;
020df079
GN		 799 /* fall through */
800 default: /* 7 */
801 *val = vcpu->arch.dr7;
802 break;
803 }
804
805 return 0;
806}
338dbc97
GN		 807
808int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809{
810 if (_kvm_get_dr(vcpu, dr, val)) {
811 kvm_queue_exception(vcpu, UD_VECTOR);
812 return 1;
813 }
814 return 0;
815}
020df079
GN		 816EXPORT_SYMBOL_GPL(kvm_get_dr);
817
022cd0e8
AK		 818bool kvm_rdpmc(struct kvm_vcpu *vcpu)
819{
820 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
821 u64 data;
822 int err;
823
824 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
825 if (err)
826 return err;
827 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
828 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
829 return err;
830}
831EXPORT_SYMBOL_GPL(kvm_rdpmc);
832
043405e1
CO		 833/*
834 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
835 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
836 *
837 * This list is modified at module load time to reflect the
e3267cbb
GC		 838 * capabilities of the host cpu. This capabilities test skips MSRs that are
839 * kvm-specific. Those are put in the beginning of the list.
043405e1 840 */
e3267cbb 841
e984097b 842#define KVM_SAVE_MSRS_BEGIN 12
043405e1 843static u32 msrs_to_save[] = {
e3267cbb 844 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 845 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 846 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 847 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 848 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 849 MSR_KVM_PV_EOI_EN,
043405e1 850 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 851 MSR_STAR,
043405e1
CO		 852#ifdef CONFIG_X86_64
853 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
854#endif
b3897a49
NHE		 855 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
856 MSR_IA32_FEATURE_CONTROL
043405e1
CO		 857};
858
859static unsigned num_msrs_to_save;
860
f1d24831 861static const u32 emulated_msrs[] = {
ba904635 862 MSR_IA32_TSC_ADJUST,
a3e06bbe 863 MSR_IA32_TSCDEADLINE,
043405e1 864 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 865 MSR_IA32_MCG_STATUS,
866 MSR_IA32_MCG_CTL,
043405e1
CO		 867};
868
384bb783 869bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 870{
b69e8cae 871 if (efer & efer_reserved_bits)
384bb783 872 return false;
15c4a640 873
1b2fd70c
AG		 874 if (efer & EFER_FFXSR) {
875 struct kvm_cpuid_entry2 *feat;
876
877 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 878 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 879 return false;
1b2fd70c
AG		 880 }
881
d8017474
AG		 882 if (efer & EFER_SVME) {
883 struct kvm_cpuid_entry2 *feat;
884
885 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 886 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 887 return false;
d8017474
AG		 888 }
889
384bb783
JK		 890 return true;
891}
892EXPORT_SYMBOL_GPL(kvm_valid_efer);
893
894static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
895{
896 u64 old_efer = vcpu->arch.efer;
897
898 if (!kvm_valid_efer(vcpu, efer))
899 return 1;
900
901 if (is_paging(vcpu)
902 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
903 return 1;
904
15c4a640 905 efer &= ~EFER_LMA;
f6801dff 906 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 907
a3d204e2
SY		 908 kvm_x86_ops->set_efer(vcpu, efer);
909
aad82703
SY		 910 /* Update reserved bits */
911 if ((efer ^ old_efer) & EFER_NX)
912 kvm_mmu_reset_context(vcpu);
913
b69e8cae 914 return 0;
15c4a640
CO		 915}
916
f2b4b7dd
JR		 917void kvm_enable_efer_bits(u64 mask)
918{
919 efer_reserved_bits &= ~mask;
920}
921EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
922
923
15c4a640
CO		 924/*
925 * Writes msr value into into the appropriate "register".
926 * Returns 0 on success, non-0 otherwise.
927 * Assumes vcpu_load() was already called.
928 */
8fe8ab46 929int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 930{
8fe8ab46 931 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 932}
933
313a3dc7
CO		 934/*
935 * Adapt set_msr() to msr_io()'s calling convention
936 */
937static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
938{
8fe8ab46
WA		 939 struct msr_data msr;
940
941 msr.data = *data;
942 msr.index = index;
943 msr.host_initiated = true;
944 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 945}
946
16e8d74d
MT		 947#ifdef CONFIG_X86_64
948struct pvclock_gtod_data {
949 seqcount_t seq;
950
951 struct { /* extract of a clocksource struct */
952 int vclock_mode;
953 cycle_t cycle_last;
954 cycle_t mask;
955 u32 mult;
956 u32 shift;
957 } clock;
958
959 /* open coded 'struct timespec' */
960 u64 monotonic_time_snsec;
961 time_t monotonic_time_sec;
962};
963
964static struct pvclock_gtod_data pvclock_gtod_data;
965
966static void update_pvclock_gtod(struct timekeeper *tk)
967{
968 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
969
970 write_seqcount_begin(&vdata->seq);
971
972 /* copy pvclock gtod data */
973 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
974 vdata->clock.cycle_last = tk->clock->cycle_last;
975 vdata->clock.mask = tk->clock->mask;
976 vdata->clock.mult = tk->mult;
977 vdata->clock.shift = tk->shift;
978
979 vdata->monotonic_time_sec = tk->xtime_sec
980 + tk->wall_to_monotonic.tv_sec;
981 vdata->monotonic_time_snsec = tk->xtime_nsec
982 + (tk->wall_to_monotonic.tv_nsec
983 << tk->shift);
984 while (vdata->monotonic_time_snsec >=
985 (((u64)NSEC_PER_SEC) << tk->shift)) {
986 vdata->monotonic_time_snsec -=
987 ((u64)NSEC_PER_SEC) << tk->shift;
988 vdata->monotonic_time_sec++;
989 }
990
991 write_seqcount_end(&vdata->seq);
992}
993#endif
994
995
18068523
GOC		 996static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
997{
9ed3c444
AK		 998 int version;
999 int r;
50d0a0f9 1000 struct pvclock_wall_clock wc;
923de3cf 1001 struct timespec boot;
18068523
GOC		 1002
1003 if (!wall_clock)
1004 return;
1005
9ed3c444
AK		 1006 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1007 if (r)
1008 return;
1009
1010 if (version & 1)
1011 ++version; /* first time write, random junk */
1012
1013 ++version;
18068523 1014
18068523
GOC		 1015 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1016
50d0a0f9
GH		 1017 /*
1018 * The guest calculates current wall clock time by adding
34c238a1 1019 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1020 * wall clock specified here. guest system time equals host
1021 * system time for us, thus we must fill in host boot time here.
1022 */
923de3cf 1023 getboottime(&boot);
50d0a0f9 1024
4b648665
BR		 1025 if (kvm->arch.kvmclock_offset) {
1026 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1027 boot = timespec_sub(boot, ts);
1028 }
50d0a0f9
GH		 1029 wc.sec = boot.tv_sec;
1030 wc.nsec = boot.tv_nsec;
1031 wc.version = version;
18068523
GOC		 1032
1033 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1034
1035 version++;
1036 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1037}
1038
50d0a0f9
GH		 1039static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1040{
1041 uint32_t quotient, remainder;
1042
1043 /* Don't try to replace with do_div(), this one calculates
1044 * "(dividend << 32) / divisor" */
1045 __asm__ ( "divl %4"
1046 : "=a" (quotient), "=d" (remainder)
1047 : "0" (0), "1" (dividend), "r" (divisor) );
1048 return quotient;
1049}
1050
5f4e3f88
ZA		 1051static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1052 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1053{
5f4e3f88 1054 uint64_t scaled64;
50d0a0f9
GH		 1055 int32_t shift = 0;
1056 uint64_t tps64;
1057 uint32_t tps32;
1058
5f4e3f88
ZA		 1059 tps64 = base_khz * 1000LL;
1060 scaled64 = scaled_khz * 1000LL;
50933623 1061 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1062 tps64 >>= 1;
1063 shift--;
1064 }
1065
1066 tps32 = (uint32_t)tps64;
50933623
JK		 1067 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1068 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1069 scaled64 >>= 1;
1070 else
1071 tps32 <<= 1;
50d0a0f9
GH		 1072 shift++;
1073 }
1074
5f4e3f88
ZA		 1075 *pshift = shift;
1076 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1077
5f4e3f88
ZA		 1078 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1079 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1080}
1081
759379dd
ZA		 1082static inline u64 get_kernel_ns(void)
1083{
1084 struct timespec ts;
1085
1086 WARN_ON(preemptible());
1087 ktime_get_ts(&ts);
1088 monotonic_to_bootbased(&ts);
1089 return timespec_to_ns(&ts);
50d0a0f9
GH		 1090}
1091
d828199e 1092#ifdef CONFIG_X86_64
16e8d74d 1093static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1094#endif
16e8d74d 1095
c8076604 1096static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1097unsigned long max_tsc_khz;
c8076604 1098
cc578287 1099static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1100{
cc578287
ZA		 1101 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1102 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1103}
1104
cc578287 1105static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1106{
cc578287
ZA		 1107 u64 v = (u64)khz * (1000000 + ppm);
1108 do_div(v, 1000000);
1109 return v;
1e993611
JR		 1110}
1111
cc578287 1112static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1113{
cc578287
ZA		 1114 u32 thresh_lo, thresh_hi;
1115 int use_scaling = 0;
217fc9cf 1116
03ba32ca
MT		 1117 /* tsc_khz can be zero if TSC calibration fails */
1118 if (this_tsc_khz == 0)
1119 return;
1120
c285545f
ZA		 1121 /* Compute a scale to convert nanoseconds in TSC cycles */
1122 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1123 &vcpu->arch.virtual_tsc_shift,
1124 &vcpu->arch.virtual_tsc_mult);
1125 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1126
1127 /*
1128 * Compute the variation in TSC rate which is acceptable
1129 * within the range of tolerance and decide if the
1130 * rate being applied is within that bounds of the hardware
1131 * rate. If so, no scaling or compensation need be done.
1132 */
1133 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1134 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1135 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1136 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1137 use_scaling = 1;
1138 }
1139 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1140}
1141
1142static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1143{
e26101b1 1144 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1145 vcpu->arch.virtual_tsc_mult,
1146 vcpu->arch.virtual_tsc_shift);
e26101b1 1147 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1148 return tsc;
1149}
1150
b48aa97e
MT		 1151void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1152{
1153#ifdef CONFIG_X86_64
1154 bool vcpus_matched;
1155 bool do_request = false;
1156 struct kvm_arch *ka = &vcpu->kvm->arch;
1157 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1158
1159 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1160 atomic_read(&vcpu->kvm->online_vcpus));
1161
1162 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1163 if (!ka->use_master_clock)
1164 do_request = 1;
1165
1166 if (!vcpus_matched && ka->use_master_clock)
1167 do_request = 1;
1168
1169 if (do_request)
1170 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1171
1172 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1173 atomic_read(&vcpu->kvm->online_vcpus),
1174 ka->use_master_clock, gtod->clock.vclock_mode);
1175#endif
1176}
1177
ba904635
WA		 1178static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1179{
1180 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1181 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1182}
1183
8fe8ab46 1184void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1185{
1186 struct kvm *kvm = vcpu->kvm;
f38e098f 1187 u64 offset, ns, elapsed;
99e3e30a 1188 unsigned long flags;
02626b6a 1189 s64 usdiff;
b48aa97e 1190 bool matched;
8fe8ab46 1191 u64 data = msr->data;
99e3e30a 1192
038f8c11 1193 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1194 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1195 ns = get_kernel_ns();
f38e098f 1196 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1197
03ba32ca 1198 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1199 int faulted = 0;
1200
03ba32ca
MT		 1201 /* n.b - signed multiplication and division required */
1202 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1203#ifdef CONFIG_X86_64
03ba32ca 1204 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1205#else
03ba32ca 1206 /* do_div() only does unsigned */
8915aa27
MT		 1207 asm("1: idivl %[divisor]\n"
1208 "2: xor %%edx, %%edx\n"
1209 " movl $0, %[faulted]\n"
1210 "3:\n"
1211 ".section .fixup,\"ax\"\n"
1212 "4: movl $1, %[faulted]\n"
1213 " jmp 3b\n"
1214 ".previous\n"
1215
1216 _ASM_EXTABLE(1b, 4b)
1217
1218 : "=A"(usdiff), [faulted] "=r" (faulted)
1219 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1220
5d3cb0f6 1221#endif
03ba32ca
MT		 1222 do_div(elapsed, 1000);
1223 usdiff -= elapsed;
1224 if (usdiff < 0)
1225 usdiff = -usdiff;
8915aa27
MT		 1226
1227 /* idivl overflow => difference is larger than USEC_PER_SEC */
1228 if (faulted)
1229 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1230 } else
1231 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1232
1233 /*
5d3cb0f6
ZA		 1234 * Special case: TSC write with a small delta (1 second) of virtual
1235 * cycle time against real time is interpreted as an attempt to
1236 * synchronize the CPU.
1237 *
1238 * For a reliable TSC, we can match TSC offsets, and for an unstable
1239 * TSC, we add elapsed time in this computation. We could let the
1240 * compensation code attempt to catch up if we fall behind, but
1241 * it's better to try to match offsets from the beginning.
1242 */
02626b6a 1243 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1244 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1245 if (!check_tsc_unstable()) {
e26101b1 1246 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1247 pr_debug("kvm: matched tsc offset for %llu\n", data);
1248 } else {
857e4099 1249 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1250 data += delta;
1251 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1252 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1253 }
b48aa97e 1254 matched = true;
e26101b1
ZA		 1255 } else {
1256 /*
1257 * We split periods of matched TSC writes into generations.
1258 * For each generation, we track the original measured
1259 * nanosecond time, offset, and write, so if TSCs are in
1260 * sync, we can match exact offset, and if not, we can match
4a969980 1261 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1262 *
1263 * These values are tracked in kvm->arch.cur_xxx variables.
1264 */
1265 kvm->arch.cur_tsc_generation++;
1266 kvm->arch.cur_tsc_nsec = ns;
1267 kvm->arch.cur_tsc_write = data;
1268 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1269 matched = false;
e26101b1
ZA		 1270 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1271 kvm->arch.cur_tsc_generation, data);
f38e098f 1272 }
e26101b1
ZA		 1273
1274 /*
1275 * We also track th most recent recorded KHZ, write and time to
1276 * allow the matching interval to be extended at each write.
1277 */
f38e098f
ZA		 1278 kvm->arch.last_tsc_nsec = ns;
1279 kvm->arch.last_tsc_write = data;
5d3cb0f6 1280 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1281
b183aa58 1282 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1283
1284 /* Keep track of which generation this VCPU has synchronized to */
1285 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1286 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1287 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1288
ba904635
WA		 1289 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1290 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1291 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1292 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1293
1294 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1295 if (matched)
1296 kvm->arch.nr_vcpus_matched_tsc++;
1297 else
1298 kvm->arch.nr_vcpus_matched_tsc = 0;
1299
1300 kvm_track_tsc_matching(vcpu);
1301 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1302}
e26101b1 1303
99e3e30a
ZA		 1304EXPORT_SYMBOL_GPL(kvm_write_tsc);
1305
d828199e
MT		 1306#ifdef CONFIG_X86_64
1307
1308static cycle_t read_tsc(void)
1309{
1310 cycle_t ret;
1311 u64 last;
1312
1313 /*
1314 * Empirically, a fence (of type that depends on the CPU)
1315 * before rdtsc is enough to ensure that rdtsc is ordered
1316 * with respect to loads. The various CPU manuals are unclear
1317 * as to whether rdtsc can be reordered with later loads,
1318 * but no one has ever seen it happen.
1319 */
1320 rdtsc_barrier();
1321 ret = (cycle_t)vget_cycles();
1322
1323 last = pvclock_gtod_data.clock.cycle_last;
1324
1325 if (likely(ret >= last))
1326 return ret;
1327
1328 /*
1329 * GCC likes to generate cmov here, but this branch is extremely
1330 * predictable (it's just a funciton of time and the likely is
1331 * very likely) and there's a data dependence, so force GCC
1332 * to generate a branch instead. I don't barrier() because
1333 * we don't actually need a barrier, and if this function
1334 * ever gets inlined it will generate worse code.
1335 */
1336 asm volatile ("");
1337 return last;
1338}
1339
1340static inline u64 vgettsc(cycle_t *cycle_now)
1341{
1342 long v;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 *cycle_now = read_tsc();
1346
1347 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1348 return v * gtod->clock.mult;
1349}
1350
1351static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1352{
1353 unsigned long seq;
1354 u64 ns;
1355 int mode;
1356 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1357
1358 ts->tv_nsec = 0;
1359 do {
1360 seq = read_seqcount_begin(&gtod->seq);
1361 mode = gtod->clock.vclock_mode;
1362 ts->tv_sec = gtod->monotonic_time_sec;
1363 ns = gtod->monotonic_time_snsec;
1364 ns += vgettsc(cycle_now);
1365 ns >>= gtod->clock.shift;
1366 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1367 timespec_add_ns(ts, ns);
1368
1369 return mode;
1370}
1371
1372/* returns true if host is using tsc clocksource */
1373static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1374{
1375 struct timespec ts;
1376
1377 /* checked again under seqlock below */
1378 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1379 return false;
1380
1381 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1382 return false;
1383
1384 monotonic_to_bootbased(&ts);
1385 *kernel_ns = timespec_to_ns(&ts);
1386
1387 return true;
1388}
1389#endif
1390
1391/*
1392 *
b48aa97e
MT		 1393 * Assuming a stable TSC across physical CPUS, and a stable TSC
1394 * across virtual CPUs, the following condition is possible.
1395 * Each numbered line represents an event visible to both
d828199e
MT		 1396 * CPUs at the next numbered event.
1397 *
1398 * "timespecX" represents host monotonic time. "tscX" represents
1399 * RDTSC value.
1400 *
1401 * VCPU0 on CPU0 | VCPU1 on CPU1
1402 *
1403 * 1. read timespec0,tsc0
1404 * 2. | timespec1 = timespec0 + N
1405 * | tsc1 = tsc0 + M
1406 * 3. transition to guest | transition to guest
1407 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1408 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1409 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1410 *
1411 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1412 *
1413 * - ret0 < ret1
1414 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1415 * ...
1416 * - 0 < N - M => M < N
1417 *
1418 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1419 * always the case (the difference between two distinct xtime instances
1420 * might be smaller then the difference between corresponding TSC reads,
1421 * when updating guest vcpus pvclock areas).
1422 *
1423 * To avoid that problem, do not allow visibility of distinct
1424 * system_timestamp/tsc_timestamp values simultaneously: use a master
1425 * copy of host monotonic time values. Update that master copy
1426 * in lockstep.
1427 *
b48aa97e 1428 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1429 *
1430 */
1431
1432static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1433{
1434#ifdef CONFIG_X86_64
1435 struct kvm_arch *ka = &kvm->arch;
1436 int vclock_mode;
b48aa97e
MT		 1437 bool host_tsc_clocksource, vcpus_matched;
1438
1439 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1440 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1441
1442 /*
1443 * If the host uses TSC clock, then passthrough TSC as stable
1444 * to the guest.
1445 */
b48aa97e 1446 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1447 &ka->master_kernel_ns,
1448 &ka->master_cycle_now);
1449
b48aa97e
MT		 1450 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1451
d828199e
MT		 1452 if (ka->use_master_clock)
1453 atomic_set(&kvm_guest_has_master_clock, 1);
1454
1455 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1456 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1457 vcpus_matched);
d828199e
MT		 1458#endif
1459}
1460
2e762ff7
MT		 1461static void kvm_gen_update_masterclock(struct kvm *kvm)
1462{
1463#ifdef CONFIG_X86_64
1464 int i;
1465 struct kvm_vcpu *vcpu;
1466 struct kvm_arch *ka = &kvm->arch;
1467
1468 spin_lock(&ka->pvclock_gtod_sync_lock);
1469 kvm_make_mclock_inprogress_request(kvm);
1470 /* no guest entries from this point */
1471 pvclock_update_vm_gtod_copy(kvm);
1472
1473 kvm_for_each_vcpu(i, vcpu, kvm)
1474 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1475
1476 /* guest entries allowed */
1477 kvm_for_each_vcpu(i, vcpu, kvm)
1478 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1479
1480 spin_unlock(&ka->pvclock_gtod_sync_lock);
1481#endif
1482}
1483
34c238a1 1484static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1485{
d828199e 1486 unsigned long flags, this_tsc_khz;
18068523 1487 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1488 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1489 s64 kernel_ns;
d828199e 1490 u64 tsc_timestamp, host_tsc;
0b79459b 1491 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1492 u8 pvclock_flags;
d828199e
MT		 1493 bool use_master_clock;
1494
1495 kernel_ns = 0;
1496 host_tsc = 0;
18068523 1497
d828199e
MT		 1498 /*
1499 * If the host uses TSC clock, then passthrough TSC as stable
1500 * to the guest.
1501 */
1502 spin_lock(&ka->pvclock_gtod_sync_lock);
1503 use_master_clock = ka->use_master_clock;
1504 if (use_master_clock) {
1505 host_tsc = ka->master_cycle_now;
1506 kernel_ns = ka->master_kernel_ns;
1507 }
1508 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1509
1510 /* Keep irq disabled to prevent changes to the clock */
1511 local_irq_save(flags);
1512 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1513 if (unlikely(this_tsc_khz == 0)) {
1514 local_irq_restore(flags);
1515 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1516 return 1;
1517 }
d828199e
MT		 1518 if (!use_master_clock) {
1519 host_tsc = native_read_tsc();
1520 kernel_ns = get_kernel_ns();
1521 }
1522
1523 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1524
c285545f
ZA		 1525 /*
1526 * We may have to catch up the TSC to match elapsed wall clock
1527 * time for two reasons, even if kvmclock is used.
1528 * 1) CPU could have been running below the maximum TSC rate
1529 * 2) Broken TSC compensation resets the base at each VCPU
1530 * entry to avoid unknown leaps of TSC even when running
1531 * again on the same CPU. This may cause apparent elapsed
1532 * time to disappear, and the guest to stand still or run
1533 * very slowly.
1534 */
1535 if (vcpu->tsc_catchup) {
1536 u64 tsc = compute_guest_tsc(v, kernel_ns);
1537 if (tsc > tsc_timestamp) {
f1e2b260 1538 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1539 tsc_timestamp = tsc;
1540 }
50d0a0f9
GH		 1541 }
1542
18068523
GOC		 1543 local_irq_restore(flags);
1544
0b79459b 1545 if (!vcpu->pv_time_enabled)
c285545f 1546 return 0;
18068523 1547
e48672fa 1548 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1549 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1550 &vcpu->hv_clock.tsc_shift,
1551 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1552 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1553 }
1554
1555 /* With all the info we got, fill in the values */
1d5f066e 1556 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1557 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1558 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1559 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1560
18068523
GOC		 1561 /*
1562 * The interface expects us to write an even number signaling that the
1563 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1564 * state, we just increase by 2 at the end.
18068523 1565 */
50d0a0f9 1566 vcpu->hv_clock.version += 2;
18068523 1567
0b79459b
AH		 1568 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1569 &guest_hv_clock, sizeof(guest_hv_clock))))
1570 return 0;
78c0337a
MT		 1571
1572 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1573 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1574
1575 if (vcpu->pvclock_set_guest_stopped_request) {
1576 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1577 vcpu->pvclock_set_guest_stopped_request = false;
1578 }
1579
d828199e
MT		 1580 /* If the host uses TSC clocksource, then it is stable */
1581 if (use_master_clock)
1582 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1583
78c0337a
MT		 1584 vcpu->hv_clock.flags = pvclock_flags;
1585
0b79459b
AH		 1586 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1587 &vcpu->hv_clock,
1588 sizeof(vcpu->hv_clock));
8cfdc000 1589 return 0;
c8076604
GH		 1590}
1591
0061d53d
MT		 1592/*
1593 * kvmclock updates which are isolated to a given vcpu, such as
1594 * vcpu->cpu migration, should not allow system_timestamp from
1595 * the rest of the vcpus to remain static. Otherwise ntp frequency
1596 * correction applies to one vcpu's system_timestamp but not
1597 * the others.
1598 *
1599 * So in those cases, request a kvmclock update for all vcpus.
1600 * The worst case for a remote vcpu to update its kvmclock
1601 * is then bounded by maximum nohz sleep latency.
1602 */
1603
1604static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1605{
1606 int i;
1607 struct kvm *kvm = v->kvm;
1608 struct kvm_vcpu *vcpu;
1609
1610 kvm_for_each_vcpu(i, vcpu, kvm) {
1611 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1612 kvm_vcpu_kick(vcpu);
1613 }
1614}
1615
9ba075a6
AK		 1616static bool msr_mtrr_valid(unsigned msr)
1617{
1618 switch (msr) {
1619 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1620 case MSR_MTRRfix64K_00000:
1621 case MSR_MTRRfix16K_80000:
1622 case MSR_MTRRfix16K_A0000:
1623 case MSR_MTRRfix4K_C0000:
1624 case MSR_MTRRfix4K_C8000:
1625 case MSR_MTRRfix4K_D0000:
1626 case MSR_MTRRfix4K_D8000:
1627 case MSR_MTRRfix4K_E0000:
1628 case MSR_MTRRfix4K_E8000:
1629 case MSR_MTRRfix4K_F0000:
1630 case MSR_MTRRfix4K_F8000:
1631 case MSR_MTRRdefType:
1632 case MSR_IA32_CR_PAT:
1633 return true;
1634 case 0x2f8:
1635 return true;
1636 }
1637 return false;
1638}
1639
d6289b93
MT		 1640static bool valid_pat_type(unsigned t)
1641{
1642 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1643}
1644
1645static bool valid_mtrr_type(unsigned t)
1646{
1647 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1648}
1649
1650static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1651{
1652 int i;
1653
1654 if (!msr_mtrr_valid(msr))
1655 return false;
1656
1657 if (msr == MSR_IA32_CR_PAT) {
1658 for (i = 0; i < 8; i++)
1659 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1660 return false;
1661 return true;
1662 } else if (msr == MSR_MTRRdefType) {
1663 if (data & ~0xcff)
1664 return false;
1665 return valid_mtrr_type(data & 0xff);
1666 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1667 for (i = 0; i < 8 ; i++)
1668 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1669 return false;
1670 return true;
1671 }
1672
1673 /* variable MTRRs */
1674 return valid_mtrr_type(data & 0xff);
1675}
1676
9ba075a6
AK		 1677static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1678{
0bed3b56
SY		 1679 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1680
d6289b93 1681 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1682 return 1;
1683
0bed3b56
SY		 1684 if (msr == MSR_MTRRdefType) {
1685 vcpu->arch.mtrr_state.def_type = data;
1686 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1687 } else if (msr == MSR_MTRRfix64K_00000)
1688 p[0] = data;
1689 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1690 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1691 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1692 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1693 else if (msr == MSR_IA32_CR_PAT)
1694 vcpu->arch.pat = data;
1695 else { /* Variable MTRRs */
1696 int idx, is_mtrr_mask;
1697 u64 *pt;
1698
1699 idx = (msr - 0x200) / 2;
1700 is_mtrr_mask = msr - 0x200 - 2 * idx;
1701 if (!is_mtrr_mask)
1702 pt =
1703 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1704 else
1705 pt =
1706 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1707 *pt = data;
1708 }
1709
1710 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1711 return 0;
1712}
15c4a640 1713
890ca9ae 1714static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1715{
890ca9ae
HY		 1716 u64 mcg_cap = vcpu->arch.mcg_cap;
1717 unsigned bank_num = mcg_cap & 0xff;
1718
15c4a640 1719 switch (msr) {
15c4a640 1720 case MSR_IA32_MCG_STATUS:
890ca9ae 1721 vcpu->arch.mcg_status = data;
15c4a640 1722 break;
c7ac679c 1723 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1724 if (!(mcg_cap & MCG_CTL_P))
1725 return 1;
1726 if (data != 0 && data != ~(u64)0)
1727 return -1;
1728 vcpu->arch.mcg_ctl = data;
1729 break;
1730 default:
1731 if (msr >= MSR_IA32_MC0_CTL &&
1732 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1733 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1734 /* only 0 or all 1s can be written to IA32_MCi_CTL
1735 * some Linux kernels though clear bit 10 in bank 4 to
1736 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1737 * this to avoid an uncatched #GP in the guest
1738 */
890ca9ae 1739 if ((offset & 0x3) == 0 &&
114be429 1740 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1741 return -1;
1742 vcpu->arch.mce_banks[offset] = data;
1743 break;
1744 }
1745 return 1;
1746 }
1747 return 0;
1748}
1749
ffde22ac
ES		 1750static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1751{
1752 struct kvm *kvm = vcpu->kvm;
1753 int lm = is_long_mode(vcpu);
1754 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1755 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1756 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1757 : kvm->arch.xen_hvm_config.blob_size_32;
1758 u32 page_num = data & ~PAGE_MASK;
1759 u64 page_addr = data & PAGE_MASK;
1760 u8 *page;
1761 int r;
1762
1763 r = -E2BIG;
1764 if (page_num >= blob_size)
1765 goto out;
1766 r = -ENOMEM;
ff5c2c03
SL		 1767 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1768 if (IS_ERR(page)) {
1769 r = PTR_ERR(page);
ffde22ac 1770 goto out;
ff5c2c03 1771 }
ffde22ac
ES		 1772 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1773 goto out_free;
1774 r = 0;
1775out_free:
1776 kfree(page);
1777out:
1778 return r;
1779}
1780
55cd8e5a
GN		 1781static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1782{
1783 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1784}
1785
1786static bool kvm_hv_msr_partition_wide(u32 msr)
1787{
1788 bool r = false;
1789 switch (msr) {
1790 case HV_X64_MSR_GUEST_OS_ID:
1791 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1792 case HV_X64_MSR_REFERENCE_TSC:
1793 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1794 r = true;
1795 break;
1796 }
1797
1798 return r;
1799}
1800
1801static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1802{
1803 struct kvm *kvm = vcpu->kvm;
1804
1805 switch (msr) {
1806 case HV_X64_MSR_GUEST_OS_ID:
1807 kvm->arch.hv_guest_os_id = data;
1808 /* setting guest os id to zero disables hypercall page */
1809 if (!kvm->arch.hv_guest_os_id)
1810 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1811 break;
1812 case HV_X64_MSR_HYPERCALL: {
1813 u64 gfn;
1814 unsigned long addr;
1815 u8 instructions[4];
1816
1817 /* if guest os id is not set hypercall should remain disabled */
1818 if (!kvm->arch.hv_guest_os_id)
1819 break;
1820 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1821 kvm->arch.hv_hypercall = data;
1822 break;
1823 }
1824 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1825 addr = gfn_to_hva(kvm, gfn);
1826 if (kvm_is_error_hva(addr))
1827 return 1;
1828 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1829 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1830 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1831 return 1;
1832 kvm->arch.hv_hypercall = data;
1833 break;
1834 }
e984097b
VR		 1835 case HV_X64_MSR_REFERENCE_TSC: {
1836 u64 gfn;
1837 HV_REFERENCE_TSC_PAGE tsc_ref;
1838 memset(&tsc_ref, 0, sizeof(tsc_ref));
1839 kvm->arch.hv_tsc_page = data;
1840 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1841 break;
1842 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1843 if (kvm_write_guest(kvm, data,
1844 &tsc_ref, sizeof(tsc_ref)))
1845 return 1;
1846 mark_page_dirty(kvm, gfn);
1847 break;
1848 }
55cd8e5a 1849 default:
a737f256
CD		 1850 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1851 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1852 return 1;
1853 }
1854 return 0;
1855}
1856
1857static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1858{
10388a07
GN		 1859 switch (msr) {
1860 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1861 unsigned long addr;
55cd8e5a 1862
10388a07
GN		 1863 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1864 vcpu->arch.hv_vapic = data;
1865 break;
1866 }
1867 addr = gfn_to_hva(vcpu->kvm, data >>
1868 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1869 if (kvm_is_error_hva(addr))
1870 return 1;
8b0cedff 1871 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1872 return 1;
1873 vcpu->arch.hv_vapic = data;
1874 break;
1875 }
1876 case HV_X64_MSR_EOI:
1877 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1878 case HV_X64_MSR_ICR:
1879 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1880 case HV_X64_MSR_TPR:
1881 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1882 default:
a737f256
CD		 1883 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1884 "data 0x%llx\n", msr, data);
10388a07
GN		 1885 return 1;
1886 }
1887
1888 return 0;
55cd8e5a
GN		 1889}
1890
344d9588
GN		 1891static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1892{
1893 gpa_t gpa = data & ~0x3f;
1894
4a969980 1895 /* Bits 2:5 are reserved, Should be zero */
6adba527 1896 if (data & 0x3c)
344d9588
GN		 1897 return 1;
1898
1899 vcpu->arch.apf.msr_val = data;
1900
1901 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1902 kvm_clear_async_pf_completion_queue(vcpu);
1903 kvm_async_pf_hash_reset(vcpu);
1904 return 0;
1905 }
1906
8f964525
AH		 1907 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1908 sizeof(u32)))
344d9588
GN		 1909 return 1;
1910
6adba527 1911 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1912 kvm_async_pf_wakeup_all(vcpu);
1913 return 0;
1914}
1915
12f9a48f
GC		 1916static void kvmclock_reset(struct kvm_vcpu *vcpu)
1917{
0b79459b 1918 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1919}
1920
c9aaa895
GC		 1921static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1922{
1923 u64 delta;
1924
1925 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1926 return;
1927
1928 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1929 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1930 vcpu->arch.st.accum_steal = delta;
1931}
1932
1933static void record_steal_time(struct kvm_vcpu *vcpu)
1934{
1935 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1936 return;
1937
1938 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1939 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1940 return;
1941
1942 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1943 vcpu->arch.st.steal.version += 2;
1944 vcpu->arch.st.accum_steal = 0;
1945
1946 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1947 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1948}
1949
8fe8ab46 1950int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1951{
5753785f 1952 bool pr = false;
8fe8ab46
WA		 1953 u32 msr = msr_info->index;
1954 u64 data = msr_info->data;
5753785f 1955
15c4a640 1956 switch (msr) {
2e32b719
BP		 1957 case MSR_AMD64_NB_CFG:
1958 case MSR_IA32_UCODE_REV:
1959 case MSR_IA32_UCODE_WRITE:
1960 case MSR_VM_HSAVE_PA:
1961 case MSR_AMD64_PATCH_LOADER:
1962 case MSR_AMD64_BU_CFG2:
1963 break;
1964
15c4a640 1965 case MSR_EFER:
b69e8cae 1966 return set_efer(vcpu, data);
8f1589d9
AP		 1967 case MSR_K7_HWCR:
1968 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1969 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1970 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1971 if (data != 0) {
a737f256
CD		 1972 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1973 data);
8f1589d9
AP		 1974 return 1;
1975 }
15c4a640 1976 break;
f7c6d140
AP		 1977 case MSR_FAM10H_MMIO_CONF_BASE:
1978 if (data != 0) {
a737f256
CD		 1979 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1980 "0x%llx\n", data);
f7c6d140
AP		 1981 return 1;
1982 }
15c4a640 1983 break;
b5e2fec0
AG		 1984 case MSR_IA32_DEBUGCTLMSR:
1985 if (!data) {
1986 /* We support the non-activated case already */
1987 break;
1988 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1989 /* Values other than LBR and BTF are vendor-specific,
1990 thus reserved and should throw a #GP */
1991 return 1;
1992 }
a737f256
CD		 1993 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1994 __func__, data);
b5e2fec0 1995 break;
9ba075a6
AK		 1996 case 0x200 ... 0x2ff:
1997 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1998 case MSR_IA32_APICBASE:
1999 kvm_set_apic_base(vcpu, data);
2000 break;
0105d1a5
GN		 2001 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2002 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2003 case MSR_IA32_TSCDEADLINE:
2004 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2005 break;
ba904635
WA		 2006 case MSR_IA32_TSC_ADJUST:
2007 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2008 if (!msr_info->host_initiated) {
2009 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2010 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2011 }
2012 vcpu->arch.ia32_tsc_adjust_msr = data;
2013 }
2014 break;
15c4a640 2015 case MSR_IA32_MISC_ENABLE:
ad312c7c 2016 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2017 break;
11c6bffa 2018 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2019 case MSR_KVM_WALL_CLOCK:
2020 vcpu->kvm->arch.wall_clock = data;
2021 kvm_write_wall_clock(vcpu->kvm, data);
2022 break;
11c6bffa 2023 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2024 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2025 u64 gpa_offset;
12f9a48f 2026 kvmclock_reset(vcpu);
18068523
GOC		 2027
2028 vcpu->arch.time = data;
0061d53d 2029 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2030
2031 /* we verify if the enable bit is set... */
2032 if (!(data & 1))
2033 break;
2034
0b79459b 2035 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2036
0b79459b 2037 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2038 &vcpu->arch.pv_time, data & ~1ULL,
2039 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2040 vcpu->arch.pv_time_enabled = false;
2041 else
2042 vcpu->arch.pv_time_enabled = true;
32cad84f 2043
18068523
GOC		 2044 break;
2045 }
344d9588
GN		 2046 case MSR_KVM_ASYNC_PF_EN:
2047 if (kvm_pv_enable_async_pf(vcpu, data))
2048 return 1;
2049 break;
c9aaa895
GC		 2050 case MSR_KVM_STEAL_TIME:
2051
2052 if (unlikely(!sched_info_on()))
2053 return 1;
2054
2055 if (data & KVM_STEAL_RESERVED_MASK)
2056 return 1;
2057
2058 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2059 data & KVM_STEAL_VALID_BITS,
2060 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2061 return 1;
2062
2063 vcpu->arch.st.msr_val = data;
2064
2065 if (!(data & KVM_MSR_ENABLED))
2066 break;
2067
2068 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2069
2070 preempt_disable();
2071 accumulate_steal_time(vcpu);
2072 preempt_enable();
2073
2074 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2075
2076 break;
ae7a2a3f
MT		 2077 case MSR_KVM_PV_EOI_EN:
2078 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2079 return 1;
2080 break;
c9aaa895 2081
890ca9ae
HY		 2082 case MSR_IA32_MCG_CTL:
2083 case MSR_IA32_MCG_STATUS:
2084 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2085 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2086
2087 /* Performance counters are not protected by a CPUID bit,
2088 * so we should check all of them in the generic path for the sake of
2089 * cross vendor migration.
2090 * Writing a zero into the event select MSRs disables them,
2091 * which we perfectly emulate ;-). Any other value should be at least
2092 * reported, some guests depend on them.
2093 */
71db6023
AP		 2094 case MSR_K7_EVNTSEL0:
2095 case MSR_K7_EVNTSEL1:
2096 case MSR_K7_EVNTSEL2:
2097 case MSR_K7_EVNTSEL3:
2098 if (data != 0)
a737f256
CD		 2099 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2100 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2101 break;
2102 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2103 * so we ignore writes to make it happy.
2104 */
71db6023
AP		 2105 case MSR_K7_PERFCTR0:
2106 case MSR_K7_PERFCTR1:
2107 case MSR_K7_PERFCTR2:
2108 case MSR_K7_PERFCTR3:
a737f256
CD		 2109 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2110 "0x%x data 0x%llx\n", msr, data);
71db6023 2111 break;
5753785f
GN		 2112 case MSR_P6_PERFCTR0:
2113 case MSR_P6_PERFCTR1:
2114 pr = true;
2115 case MSR_P6_EVNTSEL0:
2116 case MSR_P6_EVNTSEL1:
2117 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2118 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2119
2120 if (pr || data != 0)
a737f256
CD		 2121 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2122 "0x%x data 0x%llx\n", msr, data);
5753785f 2123 break;
84e0cefa
JS		 2124 case MSR_K7_CLK_CTL:
2125 /*
2126 * Ignore all writes to this no longer documented MSR.
2127 * Writes are only relevant for old K7 processors,
2128 * all pre-dating SVM, but a recommended workaround from
4a969980 2129 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2130 * affected processor models on the command line, hence
2131 * the need to ignore the workaround.
2132 */
2133 break;
55cd8e5a
GN		 2134 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2135 if (kvm_hv_msr_partition_wide(msr)) {
2136 int r;
2137 mutex_lock(&vcpu->kvm->lock);
2138 r = set_msr_hyperv_pw(vcpu, msr, data);
2139 mutex_unlock(&vcpu->kvm->lock);
2140 return r;
2141 } else
2142 return set_msr_hyperv(vcpu, msr, data);
2143 break;
91c9c3ed 2144 case MSR_IA32_BBL_CR_CTL3:
2145 /* Drop writes to this legacy MSR -- see rdmsr
2146 * counterpart for further detail.
2147 */
a737f256 2148 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2149 break;
2b036c6b
BO		 2150 case MSR_AMD64_OSVW_ID_LENGTH:
2151 if (!guest_cpuid_has_osvw(vcpu))
2152 return 1;
2153 vcpu->arch.osvw.length = data;
2154 break;
2155 case MSR_AMD64_OSVW_STATUS:
2156 if (!guest_cpuid_has_osvw(vcpu))
2157 return 1;
2158 vcpu->arch.osvw.status = data;
2159 break;
15c4a640 2160 default:
ffde22ac
ES		 2161 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2162 return xen_hvm_config(vcpu, data);
f5132b01 2163 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2164 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2165 if (!ignore_msrs) {
a737f256
CD		 2166 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2167 msr, data);
ed85c068
AP		 2168 return 1;
2169 } else {
a737f256
CD		 2170 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2171 msr, data);
ed85c068
AP		 2172 break;
2173 }
15c4a640
CO		 2174 }
2175 return 0;
2176}
2177EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2178
2179
2180/*
2181 * Reads an msr value (of 'msr_index') into 'pdata'.
2182 * Returns 0 on success, non-0 otherwise.
2183 * Assumes vcpu_load() was already called.
2184 */
2185int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2186{
2187 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2188}
2189
9ba075a6
AK		 2190static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2191{
0bed3b56
SY		 2192 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2193
9ba075a6
AK		 2194 if (!msr_mtrr_valid(msr))
2195 return 1;
2196
0bed3b56
SY		 2197 if (msr == MSR_MTRRdefType)
2198 *pdata = vcpu->arch.mtrr_state.def_type +
2199 (vcpu->arch.mtrr_state.enabled << 10);
2200 else if (msr == MSR_MTRRfix64K_00000)
2201 *pdata = p[0];
2202 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2203 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2204 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2205 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2206 else if (msr == MSR_IA32_CR_PAT)
2207 *pdata = vcpu->arch.pat;
2208 else { /* Variable MTRRs */
2209 int idx, is_mtrr_mask;
2210 u64 *pt;
2211
2212 idx = (msr - 0x200) / 2;
2213 is_mtrr_mask = msr - 0x200 - 2 * idx;
2214 if (!is_mtrr_mask)
2215 pt =
2216 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2217 else
2218 pt =
2219 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2220 *pdata = *pt;
2221 }
2222
9ba075a6
AK		 2223 return 0;
2224}
2225
890ca9ae 2226static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2227{
2228 u64 data;
890ca9ae
HY		 2229 u64 mcg_cap = vcpu->arch.mcg_cap;
2230 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2231
2232 switch (msr) {
15c4a640
CO		 2233 case MSR_IA32_P5_MC_ADDR:
2234 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2235 data = 0;
2236 break;
15c4a640 2237 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2238 data = vcpu->arch.mcg_cap;
2239 break;
c7ac679c 2240 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2241 if (!(mcg_cap & MCG_CTL_P))
2242 return 1;
2243 data = vcpu->arch.mcg_ctl;
2244 break;
2245 case MSR_IA32_MCG_STATUS:
2246 data = vcpu->arch.mcg_status;
2247 break;
2248 default:
2249 if (msr >= MSR_IA32_MC0_CTL &&
2250 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2251 u32 offset = msr - MSR_IA32_MC0_CTL;
2252 data = vcpu->arch.mce_banks[offset];
2253 break;
2254 }
2255 return 1;
2256 }
2257 *pdata = data;
2258 return 0;
2259}
2260
55cd8e5a
GN		 2261static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2262{
2263 u64 data = 0;
2264 struct kvm *kvm = vcpu->kvm;
2265
2266 switch (msr) {
2267 case HV_X64_MSR_GUEST_OS_ID:
2268 data = kvm->arch.hv_guest_os_id;
2269 break;
2270 case HV_X64_MSR_HYPERCALL:
2271 data = kvm->arch.hv_hypercall;
2272 break;
e984097b
VR		 2273 case HV_X64_MSR_TIME_REF_COUNT: {
2274 data =
2275 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2276 break;
2277 }
2278 case HV_X64_MSR_REFERENCE_TSC:
2279 data = kvm->arch.hv_tsc_page;
2280 break;
55cd8e5a 2281 default:
a737f256 2282 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2283 return 1;
2284 }
2285
2286 *pdata = data;
2287 return 0;
2288}
2289
2290static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2291{
2292 u64 data = 0;
2293
2294 switch (msr) {
2295 case HV_X64_MSR_VP_INDEX: {
2296 int r;
2297 struct kvm_vcpu *v;
2298 kvm_for_each_vcpu(r, v, vcpu->kvm)
2299 if (v == vcpu)
2300 data = r;
2301 break;
2302 }
10388a07
GN		 2303 case HV_X64_MSR_EOI:
2304 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2305 case HV_X64_MSR_ICR:
2306 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2307 case HV_X64_MSR_TPR:
2308 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2309 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2310 data = vcpu->arch.hv_vapic;
2311 break;
55cd8e5a 2312 default:
a737f256 2313 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2314 return 1;
2315 }
2316 *pdata = data;
2317 return 0;
2318}
2319
890ca9ae
HY		 2320int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2321{
2322 u64 data;
2323
2324 switch (msr) {
890ca9ae 2325 case MSR_IA32_PLATFORM_ID:
15c4a640 2326 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2327 case MSR_IA32_DEBUGCTLMSR:
2328 case MSR_IA32_LASTBRANCHFROMIP:
2329 case MSR_IA32_LASTBRANCHTOIP:
2330 case MSR_IA32_LASTINTFROMIP:
2331 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2332 case MSR_K8_SYSCFG:
2333 case MSR_K7_HWCR:
61a6bd67 2334 case MSR_VM_HSAVE_PA:
9e699624 2335 case MSR_K7_EVNTSEL0:
1f3ee616 2336 case MSR_K7_PERFCTR0:
1fdbd48c 2337 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2338 case MSR_AMD64_NB_CFG:
f7c6d140 2339 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2340 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2341 data = 0;
2342 break;
5753785f
GN		 2343 case MSR_P6_PERFCTR0:
2344 case MSR_P6_PERFCTR1:
2345 case MSR_P6_EVNTSEL0:
2346 case MSR_P6_EVNTSEL1:
2347 if (kvm_pmu_msr(vcpu, msr))
2348 return kvm_pmu_get_msr(vcpu, msr, pdata);
2349 data = 0;
2350 break;
742bc670
MT		 2351 case MSR_IA32_UCODE_REV:
2352 data = 0x100000000ULL;
2353 break;
9ba075a6
AK		 2354 case MSR_MTRRcap:
2355 data = 0x500 | KVM_NR_VAR_MTRR;
2356 break;
2357 case 0x200 ... 0x2ff:
2358 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2359 case 0xcd: /* fsb frequency */
2360 data = 3;
2361 break;
7b914098
JS		 2362 /*
2363 * MSR_EBC_FREQUENCY_ID
2364 * Conservative value valid for even the basic CPU models.
2365 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2366 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2367 * and 266MHz for model 3, or 4. Set Core Clock
2368 * Frequency to System Bus Frequency Ratio to 1 (bits
2369 * 31:24) even though these are only valid for CPU
2370 * models > 2, however guests may end up dividing or
2371 * multiplying by zero otherwise.
2372 */
2373 case MSR_EBC_FREQUENCY_ID:
2374 data = 1 << 24;
2375 break;
15c4a640
CO		 2376 case MSR_IA32_APICBASE:
2377 data = kvm_get_apic_base(vcpu);
2378 break;
0105d1a5
GN		 2379 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2380 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2381 break;
a3e06bbe
LJ		 2382 case MSR_IA32_TSCDEADLINE:
2383 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2384 break;
ba904635
WA		 2385 case MSR_IA32_TSC_ADJUST:
2386 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2387 break;
15c4a640 2388 case MSR_IA32_MISC_ENABLE:
ad312c7c 2389 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2390 break;
847f0ad8
AG		 2391 case MSR_IA32_PERF_STATUS:
2392 /* TSC increment by tick */
2393 data = 1000ULL;
2394 /* CPU multiplier */
2395 data |= (((uint64_t)4ULL) << 40);
2396 break;
15c4a640 2397 case MSR_EFER:
f6801dff 2398 data = vcpu->arch.efer;
15c4a640 2399 break;
18068523 2400 case MSR_KVM_WALL_CLOCK:
11c6bffa 2401 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2402 data = vcpu->kvm->arch.wall_clock;
2403 break;
2404 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2405 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2406 data = vcpu->arch.time;
2407 break;
344d9588
GN		 2408 case MSR_KVM_ASYNC_PF_EN:
2409 data = vcpu->arch.apf.msr_val;
2410 break;
c9aaa895
GC		 2411 case MSR_KVM_STEAL_TIME:
2412 data = vcpu->arch.st.msr_val;
2413 break;
1d92128f
MT		 2414 case MSR_KVM_PV_EOI_EN:
2415 data = vcpu->arch.pv_eoi.msr_val;
2416 break;
890ca9ae
HY		 2417 case MSR_IA32_P5_MC_ADDR:
2418 case MSR_IA32_P5_MC_TYPE:
2419 case MSR_IA32_MCG_CAP:
2420 case MSR_IA32_MCG_CTL:
2421 case MSR_IA32_MCG_STATUS:
2422 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2423 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2424 case MSR_K7_CLK_CTL:
2425 /*
2426 * Provide expected ramp-up count for K7. All other
2427 * are set to zero, indicating minimum divisors for
2428 * every field.
2429 *
2430 * This prevents guest kernels on AMD host with CPU
2431 * type 6, model 8 and higher from exploding due to
2432 * the rdmsr failing.
2433 */
2434 data = 0x20000000;
2435 break;
55cd8e5a
GN		 2436 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2437 if (kvm_hv_msr_partition_wide(msr)) {
2438 int r;
2439 mutex_lock(&vcpu->kvm->lock);
2440 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2441 mutex_unlock(&vcpu->kvm->lock);
2442 return r;
2443 } else
2444 return get_msr_hyperv(vcpu, msr, pdata);
2445 break;
91c9c3ed 2446 case MSR_IA32_BBL_CR_CTL3:
2447 /* This legacy MSR exists but isn't fully documented in current
2448 * silicon. It is however accessed by winxp in very narrow
2449 * scenarios where it sets bit #19, itself documented as
2450 * a "reserved" bit. Best effort attempt to source coherent
2451 * read data here should the balance of the register be
2452 * interpreted by the guest:
2453 *
2454 * L2 cache control register 3: 64GB range, 256KB size,
2455 * enabled, latency 0x1, configured
2456 */
2457 data = 0xbe702111;
2458 break;
2b036c6b
BO		 2459 case MSR_AMD64_OSVW_ID_LENGTH:
2460 if (!guest_cpuid_has_osvw(vcpu))
2461 return 1;
2462 data = vcpu->arch.osvw.length;
2463 break;
2464 case MSR_AMD64_OSVW_STATUS:
2465 if (!guest_cpuid_has_osvw(vcpu))
2466 return 1;
2467 data = vcpu->arch.osvw.status;
2468 break;
15c4a640 2469 default:
f5132b01
GN		 2470 if (kvm_pmu_msr(vcpu, msr))
2471 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2472 if (!ignore_msrs) {
a737f256 2473 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2474 return 1;
2475 } else {
a737f256 2476 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2477 data = 0;
2478 }
2479 break;
15c4a640
CO		 2480 }
2481 *pdata = data;
2482 return 0;
2483}
2484EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2485
313a3dc7
CO		 2486/*
2487 * Read or write a bunch of msrs. All parameters are kernel addresses.
2488 *
2489 * @return number of msrs set successfully.
2490 */
2491static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2492 struct kvm_msr_entry *entries,
2493 int (*do_msr)(struct kvm_vcpu *vcpu,
2494 unsigned index, u64 *data))
2495{
f656ce01 2496 int i, idx;
313a3dc7 2497
f656ce01 2498 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2499 for (i = 0; i < msrs->nmsrs; ++i)
2500 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2501 break;
f656ce01 2502 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2503
313a3dc7
CO		 2504 return i;
2505}
2506
2507/*
2508 * Read or write a bunch of msrs. Parameters are user addresses.
2509 *
2510 * @return number of msrs set successfully.
2511 */
2512static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2513 int (*do_msr)(struct kvm_vcpu *vcpu,
2514 unsigned index, u64 *data),
2515 int writeback)
2516{
2517 struct kvm_msrs msrs;
2518 struct kvm_msr_entry *entries;
2519 int r, n;
2520 unsigned size;
2521
2522 r = -EFAULT;
2523 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2524 goto out;
2525
2526 r = -E2BIG;
2527 if (msrs.nmsrs >= MAX_IO_MSRS)
2528 goto out;
2529
313a3dc7 2530 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2531 entries = memdup_user(user_msrs->entries, size);
2532 if (IS_ERR(entries)) {
2533 r = PTR_ERR(entries);
313a3dc7 2534 goto out;
ff5c2c03 2535 }
313a3dc7
CO		 2536
2537 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2538 if (r < 0)
2539 goto out_free;
2540
2541 r = -EFAULT;
2542 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2543 goto out_free;
2544
2545 r = n;
2546
2547out_free:
7a73c028 2548 kfree(entries);
313a3dc7
CO		 2549out:
2550 return r;
2551}
2552
018d00d2
ZX		 2553int kvm_dev_ioctl_check_extension(long ext)
2554{
2555 int r;
2556
2557 switch (ext) {
2558 case KVM_CAP_IRQCHIP:
2559 case KVM_CAP_HLT:
2560 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2561 case KVM_CAP_SET_TSS_ADDR:
07716717 2562 case KVM_CAP_EXT_CPUID:
9c15bb1d 2563 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2564 case KVM_CAP_CLOCKSOURCE:
7837699f 2565 case KVM_CAP_PIT:
a28e4f5a 2566 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2567 case KVM_CAP_MP_STATE:
ed848624 2568 case KVM_CAP_SYNC_MMU:
a355c85c 2569 case KVM_CAP_USER_NMI:
52d939a0 2570 case KVM_CAP_REINJECT_CONTROL:
4925663a 2571 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2572 case KVM_CAP_IRQFD:
d34e6b17 2573 case KVM_CAP_IOEVENTFD:
c5ff41ce 2574 case KVM_CAP_PIT2:
e9f42757 2575 case KVM_CAP_PIT_STATE2:
b927a3ce 2576 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2577 case KVM_CAP_XEN_HVM:
afbcf7ab 2578 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2579 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2580 case KVM_CAP_HYPERV:
10388a07 2581 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2582 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2583 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2584 case KVM_CAP_DEBUGREGS:
d2be1651 2585 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2586 case KVM_CAP_XSAVE:
344d9588 2587 case KVM_CAP_ASYNC_PF:
92a1f12d 2588 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2589 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2590 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2591#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2592 case KVM_CAP_ASSIGN_DEV_IRQ:
2593 case KVM_CAP_PCI_2_3:
e984097b 2594 case KVM_CAP_HYPERV_TIME:
2a5bab10 2595#endif
018d00d2
ZX		 2596 r = 1;
2597 break;
542472b5
LV		 2598 case KVM_CAP_COALESCED_MMIO:
2599 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2600 break;
774ead3a
AK		 2601 case KVM_CAP_VAPIC:
2602 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2603 break;
f725230a 2604 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2605 r = KVM_SOFT_MAX_VCPUS;
2606 break;
2607 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2608 r = KVM_MAX_VCPUS;
2609 break;
a988b910 2610 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2611 r = KVM_USER_MEM_SLOTS;
a988b910 2612 break;
a68a6a72
MT		 2613 case KVM_CAP_PV_MMU: /* obsolete */
2614 r = 0;
2f333bcb 2615 break;
4cee4b72 2616#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2617 case KVM_CAP_IOMMU:
a1b60c1c 2618 r = iommu_present(&pci_bus_type);
62c476c7 2619 break;
4cee4b72 2620#endif
890ca9ae
HY		 2621 case KVM_CAP_MCE:
2622 r = KVM_MAX_MCE_BANKS;
2623 break;
2d5b5a66
SY		 2624 case KVM_CAP_XCRS:
2625 r = cpu_has_xsave;
2626 break;
92a1f12d
JR		 2627 case KVM_CAP_TSC_CONTROL:
2628 r = kvm_has_tsc_control;
2629 break;
4d25a066
JK		 2630 case KVM_CAP_TSC_DEADLINE_TIMER:
2631 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2632 break;
018d00d2
ZX		 2633 default:
2634 r = 0;
2635 break;
2636 }
2637 return r;
2638
2639}
2640
043405e1
CO		 2641long kvm_arch_dev_ioctl(struct file *filp,
2642 unsigned int ioctl, unsigned long arg)
2643{
2644 void __user *argp = (void __user *)arg;
2645 long r;
2646
2647 switch (ioctl) {
2648 case KVM_GET_MSR_INDEX_LIST: {
2649 struct kvm_msr_list __user *user_msr_list = argp;
2650 struct kvm_msr_list msr_list;
2651 unsigned n;
2652
2653 r = -EFAULT;
2654 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2655 goto out;
2656 n = msr_list.nmsrs;
2657 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2658 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2659 goto out;
2660 r = -E2BIG;
e125e7b6 2661 if (n < msr_list.nmsrs)
043405e1
CO		 2662 goto out;
2663 r = -EFAULT;
2664 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2665 num_msrs_to_save * sizeof(u32)))
2666 goto out;
e125e7b6 2667 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2668 &emulated_msrs,
2669 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2670 goto out;
2671 r = 0;
2672 break;
2673 }
9c15bb1d
BP		 2674 case KVM_GET_SUPPORTED_CPUID:
2675 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2676 struct kvm_cpuid2 __user *cpuid_arg = argp;
2677 struct kvm_cpuid2 cpuid;
2678
2679 r = -EFAULT;
2680 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2681 goto out;
9c15bb1d
BP		 2682
2683 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2684 ioctl);
674eea0f
AK		 2685 if (r)
2686 goto out;
2687
2688 r = -EFAULT;
2689 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2690 goto out;
2691 r = 0;
2692 break;
2693 }
890ca9ae
HY		 2694 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2695 u64 mce_cap;
2696
2697 mce_cap = KVM_MCE_CAP_SUPPORTED;
2698 r = -EFAULT;
2699 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2700 goto out;
2701 r = 0;
2702 break;
2703 }
043405e1
CO		 2704 default:
2705 r = -EINVAL;
2706 }
2707out:
2708 return r;
2709}
2710
f5f48ee1
SY		 2711static void wbinvd_ipi(void *garbage)
2712{
2713 wbinvd();
2714}
2715
2716static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2717{
e0f0bbc5 2718 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2719}
2720
313a3dc7
CO		 2721void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2722{
f5f48ee1
SY		 2723 /* Address WBINVD may be executed by guest */
2724 if (need_emulate_wbinvd(vcpu)) {
2725 if (kvm_x86_ops->has_wbinvd_exit())
2726 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2727 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2728 smp_call_function_single(vcpu->cpu,
2729 wbinvd_ipi, NULL, 1);
2730 }
2731
313a3dc7 2732 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2733
0dd6a6ed
ZA		 2734 /* Apply any externally detected TSC adjustments (due to suspend) */
2735 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2736 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2737 vcpu->arch.tsc_offset_adjustment = 0;
2738 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2739 }
8f6055cb 2740
48434c20 2741 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2742 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2743 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2744 if (tsc_delta < 0)
2745 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2746 if (check_tsc_unstable()) {
b183aa58
ZA		 2747 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2748 vcpu->arch.last_guest_tsc);
2749 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2750 vcpu->arch.tsc_catchup = 1;
c285545f 2751 }
d98d07ca
MT		 2752 /*
2753 * On a host with synchronized TSC, there is no need to update
2754 * kvmclock on vcpu->cpu migration
2755 */
2756 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2757 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2758 if (vcpu->cpu != cpu)
2759 kvm_migrate_timers(vcpu);
e48672fa 2760 vcpu->cpu = cpu;
6b7d7e76 2761 }
c9aaa895
GC		 2762
2763 accumulate_steal_time(vcpu);
2764 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2765}
2766
2767void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2768{
02daab21 2769 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2770 kvm_put_guest_fpu(vcpu);
6f526ec5 2771 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2772}
2773
313a3dc7
CO		 2774static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2775 struct kvm_lapic_state *s)
2776{
5a71785d 2777 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2778 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2779
2780 return 0;
2781}
2782
2783static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2784 struct kvm_lapic_state *s)
2785{
64eb0620 2786 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2787 update_cr8_intercept(vcpu);
313a3dc7
CO		 2788
2789 return 0;
2790}
2791
f77bc6a4
ZX		 2792static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2793 struct kvm_interrupt *irq)
2794{
02cdb50f 2795 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2796 return -EINVAL;
2797 if (irqchip_in_kernel(vcpu->kvm))
2798 return -ENXIO;
f77bc6a4 2799
66fd3f7f 2800 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2801 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2802
f77bc6a4
ZX		 2803 return 0;
2804}
2805
c4abb7c9
JK		 2806static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2807{
c4abb7c9 2808 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2809
2810 return 0;
2811}
2812
b209749f
AK		 2813static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2814 struct kvm_tpr_access_ctl *tac)
2815{
2816 if (tac->flags)
2817 return -EINVAL;
2818 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2819 return 0;
2820}
2821
890ca9ae
HY		 2822static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2823 u64 mcg_cap)
2824{
2825 int r;
2826 unsigned bank_num = mcg_cap & 0xff, bank;
2827
2828 r = -EINVAL;
a9e38c3e 2829 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2830 goto out;
2831 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2832 goto out;
2833 r = 0;
2834 vcpu->arch.mcg_cap = mcg_cap;
2835 /* Init IA32_MCG_CTL to all 1s */
2836 if (mcg_cap & MCG_CTL_P)
2837 vcpu->arch.mcg_ctl = ~(u64)0;
2838 /* Init IA32_MCi_CTL to all 1s */
2839 for (bank = 0; bank < bank_num; bank++)
2840 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2841out:
2842 return r;
2843}
2844
2845static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2846 struct kvm_x86_mce *mce)
2847{
2848 u64 mcg_cap = vcpu->arch.mcg_cap;
2849 unsigned bank_num = mcg_cap & 0xff;
2850 u64 *banks = vcpu->arch.mce_banks;
2851
2852 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2853 return -EINVAL;
2854 /*
2855 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2856 * reporting is disabled
2857 */
2858 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2859 vcpu->arch.mcg_ctl != ~(u64)0)
2860 return 0;
2861 banks += 4 * mce->bank;
2862 /*
2863 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2864 * reporting is disabled for the bank
2865 */
2866 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2867 return 0;
2868 if (mce->status & MCI_STATUS_UC) {
2869 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2870 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2871 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2872 return 0;
2873 }
2874 if (banks[1] & MCI_STATUS_VAL)
2875 mce->status |= MCI_STATUS_OVER;
2876 banks[2] = mce->addr;
2877 banks[3] = mce->misc;
2878 vcpu->arch.mcg_status = mce->mcg_status;
2879 banks[1] = mce->status;
2880 kvm_queue_exception(vcpu, MC_VECTOR);
2881 } else if (!(banks[1] & MCI_STATUS_VAL)
2882 || !(banks[1] & MCI_STATUS_UC)) {
2883 if (banks[1] & MCI_STATUS_VAL)
2884 mce->status |= MCI_STATUS_OVER;
2885 banks[2] = mce->addr;
2886 banks[3] = mce->misc;
2887 banks[1] = mce->status;
2888 } else
2889 banks[1] |= MCI_STATUS_OVER;
2890 return 0;
2891}
2892
3cfc3092
JK		 2893static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2894 struct kvm_vcpu_events *events)
2895{
7460fb4a 2896 process_nmi(vcpu);
03b82a30
JK		 2897 events->exception.injected =
2898 vcpu->arch.exception.pending &&
2899 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2900 events->exception.nr = vcpu->arch.exception.nr;
2901 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2902 events->exception.pad = 0;
3cfc3092
JK		 2903 events->exception.error_code = vcpu->arch.exception.error_code;
2904
03b82a30
JK		 2905 events->interrupt.injected =
2906 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2907 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2908 events->interrupt.soft = 0;
48005f64
JK		 2909 events->interrupt.shadow =
2910 kvm_x86_ops->get_interrupt_shadow(vcpu,
2911 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2912
2913 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2914 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2915 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2916 events->nmi.pad = 0;
3cfc3092 2917
66450a21 2918 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2919
dab4b911 2920 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2921 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2922 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2923}
2924
2925static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2926 struct kvm_vcpu_events *events)
2927{
dab4b911 2928 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2929 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2930 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2931 return -EINVAL;
2932
7460fb4a 2933 process_nmi(vcpu);
3cfc3092
JK		 2934 vcpu->arch.exception.pending = events->exception.injected;
2935 vcpu->arch.exception.nr = events->exception.nr;
2936 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2937 vcpu->arch.exception.error_code = events->exception.error_code;
2938
2939 vcpu->arch.interrupt.pending = events->interrupt.injected;
2940 vcpu->arch.interrupt.nr = events->interrupt.nr;
2941 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2942 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2943 kvm_x86_ops->set_interrupt_shadow(vcpu,
2944 events->interrupt.shadow);
3cfc3092
JK		 2945
2946 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2947 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2948 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2949 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2950
66450a21
JK		 2951 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2952 kvm_vcpu_has_lapic(vcpu))
2953 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2954
3842d135
AK		 2955 kvm_make_request(KVM_REQ_EVENT, vcpu);
2956
3cfc3092
JK		 2957 return 0;
2958}
2959
a1efbe77
JK		 2960static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2961 struct kvm_debugregs *dbgregs)
2962{
a1efbe77
JK		 2963 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2964 dbgregs->dr6 = vcpu->arch.dr6;
2965 dbgregs->dr7 = vcpu->arch.dr7;
2966 dbgregs->flags = 0;
97e69aa6 2967 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2968}
2969
2970static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2971 struct kvm_debugregs *dbgregs)
2972{
2973 if (dbgregs->flags)
2974 return -EINVAL;
2975
a1efbe77
JK		 2976 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2977 vcpu->arch.dr6 = dbgregs->dr6;
2978 vcpu->arch.dr7 = dbgregs->dr7;
2979
a1efbe77
JK		 2980 return 0;
2981}
2982
2d5b5a66
SY		 2983static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2984 struct kvm_xsave *guest_xsave)
2985{
4344ee98 2986 if (cpu_has_xsave) {
2d5b5a66
SY		 2987 memcpy(guest_xsave->region,
2988 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 2989 vcpu->arch.guest_xstate_size);
2990 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
2991 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
2992 } else {
2d5b5a66
SY		 2993 memcpy(guest_xsave->region,
2994 &vcpu->arch.guest_fpu.state->fxsave,
2995 sizeof(struct i387_fxsave_struct));
2996 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2997 XSTATE_FPSSE;
2998 }
2999}
3000
3001static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3002 struct kvm_xsave *guest_xsave)
3003{
3004 u64 xstate_bv =
3005 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3006
d7876f1b
PB		 3007 if (cpu_has_xsave) {
3008 /*
3009 * Here we allow setting states that are not present in
3010 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3011 * with old userspace.
3012 */
3013 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3014 return -EINVAL;
3015 if (xstate_bv & ~host_xcr0)
3016 return -EINVAL;
2d5b5a66 3017 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3018 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3019 } else {
2d5b5a66
SY		 3020 if (xstate_bv & ~XSTATE_FPSSE)
3021 return -EINVAL;
3022 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3023 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3024 }
3025 return 0;
3026}
3027
3028static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3029 struct kvm_xcrs *guest_xcrs)
3030{
3031 if (!cpu_has_xsave) {
3032 guest_xcrs->nr_xcrs = 0;
3033 return;
3034 }
3035
3036 guest_xcrs->nr_xcrs = 1;
3037 guest_xcrs->flags = 0;
3038 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3039 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3040}
3041
3042static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3043 struct kvm_xcrs *guest_xcrs)
3044{
3045 int i, r = 0;
3046
3047 if (!cpu_has_xsave)
3048 return -EINVAL;
3049
3050 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3051 return -EINVAL;
3052
3053 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3054 /* Only support XCR0 currently */
c67a04cb 3055 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3056 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3057 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3058 break;
3059 }
3060 if (r)
3061 r = -EINVAL;
3062 return r;
3063}
3064
1c0b28c2
EM		 3065/*
3066 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3067 * stopped by the hypervisor. This function will be called from the host only.
3068 * EINVAL is returned when the host attempts to set the flag for a guest that
3069 * does not support pv clocks.
3070 */
3071static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3072{
0b79459b 3073 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3074 return -EINVAL;
51d59c6b 3075 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3077 return 0;
3078}
3079
313a3dc7
CO		 3080long kvm_arch_vcpu_ioctl(struct file *filp,
3081 unsigned int ioctl, unsigned long arg)
3082{
3083 struct kvm_vcpu *vcpu = filp->private_data;
3084 void __user *argp = (void __user *)arg;
3085 int r;
d1ac91d8
AK		 3086 union {
3087 struct kvm_lapic_state *lapic;
3088 struct kvm_xsave *xsave;
3089 struct kvm_xcrs *xcrs;
3090 void *buffer;
3091 } u;
3092
3093 u.buffer = NULL;
313a3dc7
CO		 3094 switch (ioctl) {
3095 case KVM_GET_LAPIC: {
2204ae3c
MT		 3096 r = -EINVAL;
3097 if (!vcpu->arch.apic)
3098 goto out;
d1ac91d8 3099 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3100
b772ff36 3101 r = -ENOMEM;
d1ac91d8 3102 if (!u.lapic)
b772ff36 3103 goto out;
d1ac91d8 3104 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3105 if (r)
3106 goto out;
3107 r = -EFAULT;
d1ac91d8 3108 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3109 goto out;
3110 r = 0;
3111 break;
3112 }
3113 case KVM_SET_LAPIC: {
2204ae3c
MT		 3114 r = -EINVAL;
3115 if (!vcpu->arch.apic)
3116 goto out;
ff5c2c03 3117 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3118 if (IS_ERR(u.lapic))
3119 return PTR_ERR(u.lapic);
ff5c2c03 3120
d1ac91d8 3121 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3122 break;
3123 }
f77bc6a4
ZX		 3124 case KVM_INTERRUPT: {
3125 struct kvm_interrupt irq;
3126
3127 r = -EFAULT;
3128 if (copy_from_user(&irq, argp, sizeof irq))
3129 goto out;
3130 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3131 break;
3132 }
c4abb7c9
JK		 3133 case KVM_NMI: {
3134 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3135 break;
3136 }
313a3dc7
CO		 3137 case KVM_SET_CPUID: {
3138 struct kvm_cpuid __user *cpuid_arg = argp;
3139 struct kvm_cpuid cpuid;
3140
3141 r = -EFAULT;
3142 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3143 goto out;
3144 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3145 break;
3146 }
07716717
DK		 3147 case KVM_SET_CPUID2: {
3148 struct kvm_cpuid2 __user *cpuid_arg = argp;
3149 struct kvm_cpuid2 cpuid;
3150
3151 r = -EFAULT;
3152 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3153 goto out;
3154 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3155 cpuid_arg->entries);
07716717
DK		 3156 break;
3157 }
3158 case KVM_GET_CPUID2: {
3159 struct kvm_cpuid2 __user *cpuid_arg = argp;
3160 struct kvm_cpuid2 cpuid;
3161
3162 r = -EFAULT;
3163 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3164 goto out;
3165 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3166 cpuid_arg->entries);
07716717
DK		 3167 if (r)
3168 goto out;
3169 r = -EFAULT;
3170 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3171 goto out;
3172 r = 0;
3173 break;
3174 }
313a3dc7
CO		 3175 case KVM_GET_MSRS:
3176 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3177 break;
3178 case KVM_SET_MSRS:
3179 r = msr_io(vcpu, argp, do_set_msr, 0);
3180 break;
b209749f
AK		 3181 case KVM_TPR_ACCESS_REPORTING: {
3182 struct kvm_tpr_access_ctl tac;
3183
3184 r = -EFAULT;
3185 if (copy_from_user(&tac, argp, sizeof tac))
3186 goto out;
3187 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3188 if (r)
3189 goto out;
3190 r = -EFAULT;
3191 if (copy_to_user(argp, &tac, sizeof tac))
3192 goto out;
3193 r = 0;
3194 break;
3195 };
b93463aa
AK		 3196 case KVM_SET_VAPIC_ADDR: {
3197 struct kvm_vapic_addr va;
3198
3199 r = -EINVAL;
3200 if (!irqchip_in_kernel(vcpu->kvm))
3201 goto out;
3202 r = -EFAULT;
3203 if (copy_from_user(&va, argp, sizeof va))
3204 goto out;
3205 r = 0;
3206 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3207 break;
3208 }
890ca9ae
HY		 3209 case KVM_X86_SETUP_MCE: {
3210 u64 mcg_cap;
3211
3212 r = -EFAULT;
3213 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3214 goto out;
3215 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3216 break;
3217 }
3218 case KVM_X86_SET_MCE: {
3219 struct kvm_x86_mce mce;
3220
3221 r = -EFAULT;
3222 if (copy_from_user(&mce, argp, sizeof mce))
3223 goto out;
3224 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3225 break;
3226 }
3cfc3092
JK		 3227 case KVM_GET_VCPU_EVENTS: {
3228 struct kvm_vcpu_events events;
3229
3230 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3231
3232 r = -EFAULT;
3233 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3234 break;
3235 r = 0;
3236 break;
3237 }
3238 case KVM_SET_VCPU_EVENTS: {
3239 struct kvm_vcpu_events events;
3240
3241 r = -EFAULT;
3242 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3243 break;
3244
3245 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3246 break;
3247 }
a1efbe77
JK		 3248 case KVM_GET_DEBUGREGS: {
3249 struct kvm_debugregs dbgregs;
3250
3251 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3252
3253 r = -EFAULT;
3254 if (copy_to_user(argp, &dbgregs,
3255 sizeof(struct kvm_debugregs)))
3256 break;
3257 r = 0;
3258 break;
3259 }
3260 case KVM_SET_DEBUGREGS: {
3261 struct kvm_debugregs dbgregs;
3262
3263 r = -EFAULT;
3264 if (copy_from_user(&dbgregs, argp,
3265 sizeof(struct kvm_debugregs)))
3266 break;
3267
3268 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3269 break;
3270 }
2d5b5a66 3271 case KVM_GET_XSAVE: {
d1ac91d8 3272 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3273 r = -ENOMEM;
d1ac91d8 3274 if (!u.xsave)
2d5b5a66
SY		 3275 break;
3276
d1ac91d8 3277 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3278
3279 r = -EFAULT;
d1ac91d8 3280 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3281 break;
3282 r = 0;
3283 break;
3284 }
3285 case KVM_SET_XSAVE: {
ff5c2c03 3286 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3287 if (IS_ERR(u.xsave))
3288 return PTR_ERR(u.xsave);
2d5b5a66 3289
d1ac91d8 3290 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3291 break;
3292 }
3293 case KVM_GET_XCRS: {
d1ac91d8 3294 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3295 r = -ENOMEM;
d1ac91d8 3296 if (!u.xcrs)
2d5b5a66
SY		 3297 break;
3298
d1ac91d8 3299 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3300
3301 r = -EFAULT;
d1ac91d8 3302 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3303 sizeof(struct kvm_xcrs)))
3304 break;
3305 r = 0;
3306 break;
3307 }
3308 case KVM_SET_XCRS: {
ff5c2c03 3309 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3310 if (IS_ERR(u.xcrs))
3311 return PTR_ERR(u.xcrs);
2d5b5a66 3312
d1ac91d8 3313 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3314 break;
3315 }
92a1f12d
JR		 3316 case KVM_SET_TSC_KHZ: {
3317 u32 user_tsc_khz;
3318
3319 r = -EINVAL;
92a1f12d
JR		 3320 user_tsc_khz = (u32)arg;
3321
3322 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3323 goto out;
3324
cc578287
ZA		 3325 if (user_tsc_khz == 0)
3326 user_tsc_khz = tsc_khz;
3327
3328 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3329
3330 r = 0;
3331 goto out;
3332 }
3333 case KVM_GET_TSC_KHZ: {
cc578287 3334 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3335 goto out;
3336 }
1c0b28c2
EM		 3337 case KVM_KVMCLOCK_CTRL: {
3338 r = kvm_set_guest_paused(vcpu);
3339 goto out;
3340 }
313a3dc7
CO		 3341 default:
3342 r = -EINVAL;
3343 }
3344out:
d1ac91d8 3345 kfree(u.buffer);
313a3dc7
CO		 3346 return r;
3347}
3348
5b1c1493
CO		 3349int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3350{
3351 return VM_FAULT_SIGBUS;
3352}
3353
1fe779f8
CO		 3354static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3355{
3356 int ret;
3357
3358 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3359 return -EINVAL;
1fe779f8
CO		 3360 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3361 return ret;
3362}
3363
b927a3ce
SY		 3364static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3365 u64 ident_addr)
3366{
3367 kvm->arch.ept_identity_map_addr = ident_addr;
3368 return 0;
3369}
3370
1fe779f8
CO		 3371static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3372 u32 kvm_nr_mmu_pages)
3373{
3374 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3375 return -EINVAL;
3376
79fac95e 3377 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3378
3379 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3380 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3381
79fac95e 3382 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3383 return 0;
3384}
3385
3386static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3387{
39de71ec 3388 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3389}
3390
1fe779f8
CO		 3391static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3392{
3393 int r;
3394
3395 r = 0;
3396 switch (chip->chip_id) {
3397 case KVM_IRQCHIP_PIC_MASTER:
3398 memcpy(&chip->chip.pic,
3399 &pic_irqchip(kvm)->pics[0],
3400 sizeof(struct kvm_pic_state));
3401 break;
3402 case KVM_IRQCHIP_PIC_SLAVE:
3403 memcpy(&chip->chip.pic,
3404 &pic_irqchip(kvm)->pics[1],
3405 sizeof(struct kvm_pic_state));
3406 break;
3407 case KVM_IRQCHIP_IOAPIC:
eba0226b 3408 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3409 break;
3410 default:
3411 r = -EINVAL;
3412 break;
3413 }
3414 return r;
3415}
3416
3417static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3418{
3419 int r;
3420
3421 r = 0;
3422 switch (chip->chip_id) {
3423 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3424 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3425 memcpy(&pic_irqchip(kvm)->pics[0],
3426 &chip->chip.pic,
3427 sizeof(struct kvm_pic_state));
f4f51050 3428 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3429 break;
3430 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3431 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3432 memcpy(&pic_irqchip(kvm)->pics[1],
3433 &chip->chip.pic,
3434 sizeof(struct kvm_pic_state));
f4f51050 3435 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3436 break;
3437 case KVM_IRQCHIP_IOAPIC:
eba0226b 3438 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3439 break;
3440 default:
3441 r = -EINVAL;
3442 break;
3443 }
3444 kvm_pic_update_irq(pic_irqchip(kvm));
3445 return r;
3446}
3447
e0f63cb9
SY		 3448static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3449{
3450 int r = 0;
3451
894a9c55 3452 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3453 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3454 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3455 return r;
3456}
3457
3458static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3459{
3460 int r = 0;
3461
894a9c55 3462 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3463 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3464 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3465 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3466 return r;
3467}
3468
3469static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3470{
3471 int r = 0;
3472
3473 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3474 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3475 sizeof(ps->channels));
3476 ps->flags = kvm->arch.vpit->pit_state.flags;
3477 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3478 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3479 return r;
3480}
3481
3482static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3483{
3484 int r = 0, start = 0;
3485 u32 prev_legacy, cur_legacy;
3486 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3487 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3488 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3489 if (!prev_legacy && cur_legacy)
3490 start = 1;
3491 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3492 sizeof(kvm->arch.vpit->pit_state.channels));
3493 kvm->arch.vpit->pit_state.flags = ps->flags;
3494 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3495 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3496 return r;
3497}
3498
52d939a0
MT		 3499static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3500 struct kvm_reinject_control *control)
3501{
3502 if (!kvm->arch.vpit)
3503 return -ENXIO;
894a9c55 3504 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3505 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3506 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3507 return 0;
3508}
3509
95d4c16c 3510/**
60c34612
TY		 3511 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3512 * @kvm: kvm instance
3513 * @log: slot id and address to which we copy the log
95d4c16c 3514 *
60c34612
TY		 3515 * We need to keep it in mind that VCPU threads can write to the bitmap
3516 * concurrently. So, to avoid losing data, we keep the following order for
3517 * each bit:
95d4c16c 3518 *
60c34612
TY		 3519 * 1. Take a snapshot of the bit and clear it if needed.
3520 * 2. Write protect the corresponding page.
3521 * 3. Flush TLB's if needed.
3522 * 4. Copy the snapshot to the userspace.
95d4c16c 3523 *
60c34612
TY		 3524 * Between 2 and 3, the guest may write to the page using the remaining TLB
3525 * entry. This is not a problem because the page will be reported dirty at
3526 * step 4 using the snapshot taken before and step 3 ensures that successive
3527 * writes will be logged for the next call.
5bb064dc 3528 */
60c34612 3529int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3530{
7850ac54 3531 int r;
5bb064dc 3532 struct kvm_memory_slot *memslot;
60c34612
TY		 3533 unsigned long n, i;
3534 unsigned long *dirty_bitmap;
3535 unsigned long *dirty_bitmap_buffer;
3536 bool is_dirty = false;
5bb064dc 3537
79fac95e 3538 mutex_lock(&kvm->slots_lock);
5bb064dc 3539
b050b015 3540 r = -EINVAL;
bbacc0c1 3541 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3542 goto out;
3543
28a37544 3544 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3545
3546 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3547 r = -ENOENT;
60c34612 3548 if (!dirty_bitmap)
b050b015
MT		 3549 goto out;
3550
87bf6e7d 3551 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3552
60c34612
TY		 3553 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3554 memset(dirty_bitmap_buffer, 0, n);
b050b015 3555
60c34612 3556 spin_lock(&kvm->mmu_lock);
b050b015 3557
60c34612
TY		 3558 for (i = 0; i < n / sizeof(long); i++) {
3559 unsigned long mask;
3560 gfn_t offset;
cdfca7b3 3561
60c34612
TY		 3562 if (!dirty_bitmap[i])
3563 continue;
b050b015 3564
60c34612 3565 is_dirty = true;
914ebccd 3566
60c34612
TY		 3567 mask = xchg(&dirty_bitmap[i], 0);
3568 dirty_bitmap_buffer[i] = mask;
edde99ce 3569
60c34612
TY		 3570 offset = i * BITS_PER_LONG;
3571 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3572 }
60c34612
TY		 3573 if (is_dirty)
3574 kvm_flush_remote_tlbs(kvm);
3575
3576 spin_unlock(&kvm->mmu_lock);
3577
3578 r = -EFAULT;
3579 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3580 goto out;
b050b015 3581
5bb064dc
ZX		 3582 r = 0;
3583out:
79fac95e 3584 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3585 return r;
3586}
3587
aa2fbe6d
YZ		 3588int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3589 bool line_status)
23d43cf9
CD		 3590{
3591 if (!irqchip_in_kernel(kvm))
3592 return -ENXIO;
3593
3594 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3595 irq_event->irq, irq_event->level,
3596 line_status);
23d43cf9
CD		 3597 return 0;
3598}
3599
1fe779f8
CO		 3600long kvm_arch_vm_ioctl(struct file *filp,
3601 unsigned int ioctl, unsigned long arg)
3602{
3603 struct kvm *kvm = filp->private_data;
3604 void __user *argp = (void __user *)arg;
367e1319 3605 int r = -ENOTTY;
f0d66275
DH		 3606 /*
3607 * This union makes it completely explicit to gcc-3.x
3608 * that these two variables' stack usage should be
3609 * combined, not added together.
3610 */
3611 union {
3612 struct kvm_pit_state ps;
e9f42757 3613 struct kvm_pit_state2 ps2;
c5ff41ce 3614 struct kvm_pit_config pit_config;
f0d66275 3615 } u;
1fe779f8
CO		 3616
3617 switch (ioctl) {
3618 case KVM_SET_TSS_ADDR:
3619 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3620 break;
b927a3ce
SY		 3621 case KVM_SET_IDENTITY_MAP_ADDR: {
3622 u64 ident_addr;
3623
3624 r = -EFAULT;
3625 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3626 goto out;
3627 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3628 break;
3629 }
1fe779f8
CO		 3630 case KVM_SET_NR_MMU_PAGES:
3631 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3632 break;
3633 case KVM_GET_NR_MMU_PAGES:
3634 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3635 break;
3ddea128
MT		 3636 case KVM_CREATE_IRQCHIP: {
3637 struct kvm_pic *vpic;
3638
3639 mutex_lock(&kvm->lock);
3640 r = -EEXIST;
3641 if (kvm->arch.vpic)
3642 goto create_irqchip_unlock;
3e515705
AK		 3643 r = -EINVAL;
3644 if (atomic_read(&kvm->online_vcpus))
3645 goto create_irqchip_unlock;
1fe779f8 3646 r = -ENOMEM;
3ddea128
MT		 3647 vpic = kvm_create_pic(kvm);
3648 if (vpic) {
1fe779f8
CO		 3649 r = kvm_ioapic_init(kvm);
3650 if (r) {
175504cd 3651 mutex_lock(&kvm->slots_lock);
72bb2fcd 3652 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3653 &vpic->dev_master);
3654 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3655 &vpic->dev_slave);
3656 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3657 &vpic->dev_eclr);
175504cd 3658 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3659 kfree(vpic);
3660 goto create_irqchip_unlock;
1fe779f8
CO		 3661 }
3662 } else
3ddea128
MT		 3663 goto create_irqchip_unlock;
3664 smp_wmb();
3665 kvm->arch.vpic = vpic;
3666 smp_wmb();
399ec807
AK		 3667 r = kvm_setup_default_irq_routing(kvm);
3668 if (r) {
175504cd 3669 mutex_lock(&kvm->slots_lock);
3ddea128 3670 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3671 kvm_ioapic_destroy(kvm);
3672 kvm_destroy_pic(kvm);
3ddea128 3673 mutex_unlock(&kvm->irq_lock);
175504cd 3674 mutex_unlock(&kvm->slots_lock);
399ec807 3675 }
3ddea128
MT		 3676 create_irqchip_unlock:
3677 mutex_unlock(&kvm->lock);
1fe779f8 3678 break;
3ddea128 3679 }
7837699f 3680 case KVM_CREATE_PIT:
c5ff41ce
JK		 3681 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3682 goto create_pit;
3683 case KVM_CREATE_PIT2:
3684 r = -EFAULT;
3685 if (copy_from_user(&u.pit_config, argp,
3686 sizeof(struct kvm_pit_config)))
3687 goto out;
3688 create_pit:
79fac95e 3689 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3690 r = -EEXIST;
3691 if (kvm->arch.vpit)
3692 goto create_pit_unlock;
7837699f 3693 r = -ENOMEM;
c5ff41ce 3694 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3695 if (kvm->arch.vpit)
3696 r = 0;
269e05e4 3697 create_pit_unlock:
79fac95e 3698 mutex_unlock(&kvm->slots_lock);
7837699f 3699 break;
1fe779f8
CO		 3700 case KVM_GET_IRQCHIP: {
3701 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3702 struct kvm_irqchip *chip;
1fe779f8 3703
ff5c2c03
SL		 3704 chip = memdup_user(argp, sizeof(*chip));
3705 if (IS_ERR(chip)) {
3706 r = PTR_ERR(chip);
1fe779f8 3707 goto out;
ff5c2c03
SL		 3708 }
3709
1fe779f8
CO		 3710 r = -ENXIO;
3711 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3712 goto get_irqchip_out;
3713 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3714 if (r)
f0d66275 3715 goto get_irqchip_out;
1fe779f8 3716 r = -EFAULT;
f0d66275
DH		 3717 if (copy_to_user(argp, chip, sizeof *chip))
3718 goto get_irqchip_out;
1fe779f8 3719 r = 0;
f0d66275
DH		 3720 get_irqchip_out:
3721 kfree(chip);
1fe779f8
CO		 3722 break;
3723 }
3724 case KVM_SET_IRQCHIP: {
3725 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3726 struct kvm_irqchip *chip;
1fe779f8 3727
ff5c2c03
SL		 3728 chip = memdup_user(argp, sizeof(*chip));
3729 if (IS_ERR(chip)) {
3730 r = PTR_ERR(chip);
1fe779f8 3731 goto out;
ff5c2c03
SL		 3732 }
3733
1fe779f8
CO		 3734 r = -ENXIO;
3735 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3736 goto set_irqchip_out;
3737 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3738 if (r)
f0d66275 3739 goto set_irqchip_out;
1fe779f8 3740 r = 0;
f0d66275
DH		 3741 set_irqchip_out:
3742 kfree(chip);
1fe779f8
CO		 3743 break;
3744 }
e0f63cb9 3745 case KVM_GET_PIT: {
e0f63cb9 3746 r = -EFAULT;
f0d66275 3747 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3748 goto out;
3749 r = -ENXIO;
3750 if (!kvm->arch.vpit)
3751 goto out;
f0d66275 3752 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3753 if (r)
3754 goto out;
3755 r = -EFAULT;
f0d66275 3756 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3757 goto out;
3758 r = 0;
3759 break;
3760 }
3761 case KVM_SET_PIT: {
e0f63cb9 3762 r = -EFAULT;
f0d66275 3763 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3764 goto out;
3765 r = -ENXIO;
3766 if (!kvm->arch.vpit)
3767 goto out;
f0d66275 3768 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3769 break;
3770 }
e9f42757
BK		 3771 case KVM_GET_PIT2: {
3772 r = -ENXIO;
3773 if (!kvm->arch.vpit)
3774 goto out;
3775 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3776 if (r)
3777 goto out;
3778 r = -EFAULT;
3779 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3780 goto out;
3781 r = 0;
3782 break;
3783 }
3784 case KVM_SET_PIT2: {
3785 r = -EFAULT;
3786 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3787 goto out;
3788 r = -ENXIO;
3789 if (!kvm->arch.vpit)
3790 goto out;
3791 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3792 break;
3793 }
52d939a0
MT		 3794 case KVM_REINJECT_CONTROL: {
3795 struct kvm_reinject_control control;
3796 r = -EFAULT;
3797 if (copy_from_user(&control, argp, sizeof(control)))
3798 goto out;
3799 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3800 break;
3801 }
ffde22ac
ES		 3802 case KVM_XEN_HVM_CONFIG: {
3803 r = -EFAULT;
3804 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3805 sizeof(struct kvm_xen_hvm_config)))
3806 goto out;
3807 r = -EINVAL;
3808 if (kvm->arch.xen_hvm_config.flags)
3809 goto out;
3810 r = 0;
3811 break;
3812 }
afbcf7ab 3813 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3814 struct kvm_clock_data user_ns;
3815 u64 now_ns;
3816 s64 delta;
3817
3818 r = -EFAULT;
3819 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3820 goto out;
3821
3822 r = -EINVAL;
3823 if (user_ns.flags)
3824 goto out;
3825
3826 r = 0;
395c6b0a 3827 local_irq_disable();
759379dd 3828 now_ns = get_kernel_ns();
afbcf7ab 3829 delta = user_ns.clock - now_ns;
395c6b0a 3830 local_irq_enable();
afbcf7ab 3831 kvm->arch.kvmclock_offset = delta;
2e762ff7 3832 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3833 break;
3834 }
3835 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3836 struct kvm_clock_data user_ns;
3837 u64 now_ns;
3838
395c6b0a 3839 local_irq_disable();
759379dd 3840 now_ns = get_kernel_ns();
afbcf7ab 3841 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3842 local_irq_enable();
afbcf7ab 3843 user_ns.flags = 0;
97e69aa6 3844 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3845
3846 r = -EFAULT;
3847 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3848 goto out;
3849 r = 0;
3850 break;
3851 }
3852
1fe779f8
CO		 3853 default:
3854 ;
3855 }
3856out:
3857 return r;
3858}
3859
a16b043c 3860static void kvm_init_msr_list(void)
043405e1
CO		 3861{
3862 u32 dummy[2];
3863 unsigned i, j;
3864
e3267cbb
GC		 3865 /* skip the first msrs in the list. KVM-specific */
3866 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3867 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3868 continue;
3869 if (j < i)
3870 msrs_to_save[j] = msrs_to_save[i];
3871 j++;
3872 }
3873 num_msrs_to_save = j;
3874}
3875
bda9020e
MT		 3876static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3877 const void *v)
bbd9b64e 3878{
70252a10
AK		 3879 int handled = 0;
3880 int n;
3881
3882 do {
3883 n = min(len, 8);
3884 if (!(vcpu->arch.apic &&
3885 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3886 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3887 break;
3888 handled += n;
3889 addr += n;
3890 len -= n;
3891 v += n;
3892 } while (len);
bbd9b64e 3893
70252a10 3894 return handled;
bbd9b64e
CO		 3895}
3896
bda9020e 3897static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3898{
70252a10
AK		 3899 int handled = 0;
3900 int n;
3901
3902 do {
3903 n = min(len, 8);
3904 if (!(vcpu->arch.apic &&
3905 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3906 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3907 break;
3908 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3909 handled += n;
3910 addr += n;
3911 len -= n;
3912 v += n;
3913 } while (len);
bbd9b64e 3914
70252a10 3915 return handled;
bbd9b64e
CO		 3916}
3917
2dafc6c2
GN		 3918static void kvm_set_segment(struct kvm_vcpu *vcpu,
3919 struct kvm_segment *var, int seg)
3920{
3921 kvm_x86_ops->set_segment(vcpu, var, seg);
3922}
3923
3924void kvm_get_segment(struct kvm_vcpu *vcpu,
3925 struct kvm_segment *var, int seg)
3926{
3927 kvm_x86_ops->get_segment(vcpu, var, seg);
3928}
3929
e459e322 3930gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3931{
3932 gpa_t t_gpa;
ab9ae313 3933 struct x86_exception exception;
02f59dc9
JR		 3934
3935 BUG_ON(!mmu_is_nested(vcpu));
3936
3937 /* NPT walks are always user-walks */
3938 access |= PFERR_USER_MASK;
ab9ae313 3939 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3940
3941 return t_gpa;
3942}
3943
ab9ae313
AK		 3944gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3945 struct x86_exception *exception)
1871c602
GN		 3946{
3947 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3948 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3949}
3950
ab9ae313
AK		 3951 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3952 struct x86_exception *exception)
1871c602
GN		 3953{
3954 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3955 access |= PFERR_FETCH_MASK;
ab9ae313 3956 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3957}
3958
ab9ae313
AK		 3959gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3960 struct x86_exception *exception)
1871c602
GN		 3961{
3962 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3963 access |= PFERR_WRITE_MASK;
ab9ae313 3964 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3965}
3966
3967/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3968gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3969 struct x86_exception *exception)
1871c602 3970{
ab9ae313 3971 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3972}
3973
3974static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3975 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3976 struct x86_exception *exception)
bbd9b64e
CO		 3977{
3978 void *data = val;
10589a46 3979 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3980
3981 while (bytes) {
14dfe855 3982 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3983 exception);
bbd9b64e 3984 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3985 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3986 int ret;
3987
bcc55cba 3988 if (gpa == UNMAPPED_GVA)
ab9ae313 3989 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3990 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3991 if (ret < 0) {
c3cd7ffa 3992 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3993 goto out;
3994 }
bbd9b64e 3995
77c2002e
IE		 3996 bytes -= toread;
3997 data += toread;
3998 addr += toread;
bbd9b64e 3999 }
10589a46 4000out:
10589a46 4001 return r;
bbd9b64e 4002}
77c2002e 4003
1871c602 4004/* used for instruction fetching */
0f65dd70
AK		 4005static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4006 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4007 struct x86_exception *exception)
1871c602 4008{
0f65dd70 4009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4010 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4011
1871c602 4012 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4013 access | PFERR_FETCH_MASK,
4014 exception);
1871c602
GN		 4015}
4016
064aea77 4017int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4018 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4019 struct x86_exception *exception)
1871c602 4020{
0f65dd70 4021 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4022 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4023
1871c602 4024 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4025 exception);
1871c602 4026}
064aea77 4027EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4028
0f65dd70
AK		 4029static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4030 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4031 struct x86_exception *exception)
1871c602 4032{
0f65dd70 4033 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4034 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4035}
4036
6a4d7550 4037int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4038 gva_t addr, void *val,
2dafc6c2 4039 unsigned int bytes,
bcc55cba 4040 struct x86_exception *exception)
77c2002e 4041{
0f65dd70 4042 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4043 void *data = val;
4044 int r = X86EMUL_CONTINUE;
4045
4046 while (bytes) {
14dfe855
JR		 4047 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4048 PFERR_WRITE_MASK,
ab9ae313 4049 exception);
77c2002e
IE		 4050 unsigned offset = addr & (PAGE_SIZE-1);
4051 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4052 int ret;
4053
bcc55cba 4054 if (gpa == UNMAPPED_GVA)
ab9ae313 4055 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4056 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4057 if (ret < 0) {
c3cd7ffa 4058 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4059 goto out;
4060 }
4061
4062 bytes -= towrite;
4063 data += towrite;
4064 addr += towrite;
4065 }
4066out:
4067 return r;
4068}
6a4d7550 4069EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4070
af7cc7d1
XG		 4071static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4072 gpa_t *gpa, struct x86_exception *exception,
4073 bool write)
4074{
97d64b78
AK		 4075 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4076 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4077
97d64b78
AK		 4078 if (vcpu_match_mmio_gva(vcpu, gva)
4079 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4080 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4081 (gva & (PAGE_SIZE - 1));
4f022648 4082 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4083 return 1;
4084 }
4085
af7cc7d1
XG		 4086 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4087
4088 if (*gpa == UNMAPPED_GVA)
4089 return -1;
4090
4091 /* For APIC access vmexit */
4092 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4093 return 1;
4094
4f022648
XG		 4095 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4096 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4097 return 1;
4f022648 4098 }
bebb106a 4099
af7cc7d1
XG		 4100 return 0;
4101}
4102
3200f405 4103int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4104 const void *val, int bytes)
bbd9b64e
CO		 4105{
4106 int ret;
4107
4108 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4109 if (ret < 0)
bbd9b64e 4110 return 0;
f57f2ef5 4111 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4112 return 1;
4113}
4114
77d197b2
XG		 4115struct read_write_emulator_ops {
4116 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4117 int bytes);
4118 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4119 void *val, int bytes);
4120 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4121 int bytes, void *val);
4122 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4123 void *val, int bytes);
4124 bool write;
4125};
4126
4127static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4128{
4129 if (vcpu->mmio_read_completed) {
77d197b2 4130 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4131 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4132 vcpu->mmio_read_completed = 0;
4133 return 1;
4134 }
4135
4136 return 0;
4137}
4138
4139static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4140 void *val, int bytes)
4141{
4142 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4143}
4144
4145static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4146 void *val, int bytes)
4147{
4148 return emulator_write_phys(vcpu, gpa, val, bytes);
4149}
4150
4151static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4152{
4153 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4154 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4155}
4156
4157static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4158 void *val, int bytes)
4159{
4160 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4161 return X86EMUL_IO_NEEDED;
4162}
4163
4164static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4165 void *val, int bytes)
4166{
f78146b0
AK		 4167 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4168
87da7e66 4169 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4170 return X86EMUL_CONTINUE;
4171}
4172
0fbe9b0b 4173static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4174 .read_write_prepare = read_prepare,
4175 .read_write_emulate = read_emulate,
4176 .read_write_mmio = vcpu_mmio_read,
4177 .read_write_exit_mmio = read_exit_mmio,
4178};
4179
0fbe9b0b 4180static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4181 .read_write_emulate = write_emulate,
4182 .read_write_mmio = write_mmio,
4183 .read_write_exit_mmio = write_exit_mmio,
4184 .write = true,
4185};
4186
22388a3c
XG		 4187static int emulator_read_write_onepage(unsigned long addr, void *val,
4188 unsigned int bytes,
4189 struct x86_exception *exception,
4190 struct kvm_vcpu *vcpu,
0fbe9b0b 4191 const struct read_write_emulator_ops *ops)
bbd9b64e 4192{
af7cc7d1
XG		 4193 gpa_t gpa;
4194 int handled, ret;
22388a3c 4195 bool write = ops->write;
f78146b0 4196 struct kvm_mmio_fragment *frag;
10589a46 4197
22388a3c 4198 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4199
af7cc7d1 4200 if (ret < 0)
bbd9b64e 4201 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4202
4203 /* For APIC access vmexit */
af7cc7d1 4204 if (ret)
bbd9b64e
CO		 4205 goto mmio;
4206
22388a3c 4207 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4208 return X86EMUL_CONTINUE;
4209
4210mmio:
4211 /*
4212 * Is this MMIO handled locally?
4213 */
22388a3c 4214 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4215 if (handled == bytes)
bbd9b64e 4216 return X86EMUL_CONTINUE;
bbd9b64e 4217
70252a10
AK		 4218 gpa += handled;
4219 bytes -= handled;
4220 val += handled;
4221
87da7e66
XG		 4222 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4223 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4224 frag->gpa = gpa;
4225 frag->data = val;
4226 frag->len = bytes;
f78146b0 4227 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4228}
4229
22388a3c
XG		 4230int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4231 void *val, unsigned int bytes,
4232 struct x86_exception *exception,
0fbe9b0b 4233 const struct read_write_emulator_ops *ops)
bbd9b64e 4234{
0f65dd70 4235 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4236 gpa_t gpa;
4237 int rc;
4238
4239 if (ops->read_write_prepare &&
4240 ops->read_write_prepare(vcpu, val, bytes))
4241 return X86EMUL_CONTINUE;
4242
4243 vcpu->mmio_nr_fragments = 0;
0f65dd70 4244
bbd9b64e
CO		 4245 /* Crossing a page boundary? */
4246 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4247 int now;
bbd9b64e
CO		 4248
4249 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4250 rc = emulator_read_write_onepage(addr, val, now, exception,
4251 vcpu, ops);
4252
bbd9b64e
CO		 4253 if (rc != X86EMUL_CONTINUE)
4254 return rc;
4255 addr += now;
4256 val += now;
4257 bytes -= now;
4258 }
22388a3c 4259
f78146b0
AK		 4260 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4261 vcpu, ops);
4262 if (rc != X86EMUL_CONTINUE)
4263 return rc;
4264
4265 if (!vcpu->mmio_nr_fragments)
4266 return rc;
4267
4268 gpa = vcpu->mmio_fragments[0].gpa;
4269
4270 vcpu->mmio_needed = 1;
4271 vcpu->mmio_cur_fragment = 0;
4272
87da7e66 4273 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4274 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4275 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4276 vcpu->run->mmio.phys_addr = gpa;
4277
4278 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4279}
4280
4281static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4282 unsigned long addr,
4283 void *val,
4284 unsigned int bytes,
4285 struct x86_exception *exception)
4286{
4287 return emulator_read_write(ctxt, addr, val, bytes,
4288 exception, &read_emultor);
4289}
4290
4291int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4292 unsigned long addr,
4293 const void *val,
4294 unsigned int bytes,
4295 struct x86_exception *exception)
4296{
4297 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4298 exception, &write_emultor);
bbd9b64e 4299}
bbd9b64e 4300
daea3e73
AK		 4301#define CMPXCHG_TYPE(t, ptr, old, new) \
4302 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4303
4304#ifdef CONFIG_X86_64
4305# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4306#else
4307# define CMPXCHG64(ptr, old, new) \
9749a6c0 4308 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4309#endif
4310
0f65dd70
AK		 4311static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4312 unsigned long addr,
bbd9b64e
CO		 4313 const void *old,
4314 const void *new,
4315 unsigned int bytes,
0f65dd70 4316 struct x86_exception *exception)
bbd9b64e 4317{
0f65dd70 4318 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4319 gpa_t gpa;
4320 struct page *page;
4321 char *kaddr;
4322 bool exchanged;
2bacc55c 4323
daea3e73
AK		 4324 /* guests cmpxchg8b have to be emulated atomically */
4325 if (bytes > 8 || (bytes & (bytes - 1)))
4326 goto emul_write;
10589a46 4327
daea3e73 4328 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4329
daea3e73
AK		 4330 if (gpa == UNMAPPED_GVA ||
4331 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4332 goto emul_write;
2bacc55c 4333
daea3e73
AK		 4334 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4335 goto emul_write;
72dc67a6 4336
daea3e73 4337 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4338 if (is_error_page(page))
c19b8bd6 4339 goto emul_write;
72dc67a6 4340
8fd75e12 4341 kaddr = kmap_atomic(page);
daea3e73
AK		 4342 kaddr += offset_in_page(gpa);
4343 switch (bytes) {
4344 case 1:
4345 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4346 break;
4347 case 2:
4348 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4349 break;
4350 case 4:
4351 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4352 break;
4353 case 8:
4354 exchanged = CMPXCHG64(kaddr, old, new);
4355 break;
4356 default:
4357 BUG();
2bacc55c 4358 }
8fd75e12 4359 kunmap_atomic(kaddr);
daea3e73
AK		 4360 kvm_release_page_dirty(page);
4361
4362 if (!exchanged)
4363 return X86EMUL_CMPXCHG_FAILED;
4364
f57f2ef5 4365 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4366
4367 return X86EMUL_CONTINUE;
4a5f48f6 4368
3200f405 4369emul_write:
daea3e73 4370 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4371
0f65dd70 4372 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4373}
4374
cf8f70bf
GN		 4375static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4376{
4377 /* TODO: String I/O for in kernel device */
4378 int r;
4379
4380 if (vcpu->arch.pio.in)
4381 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4382 vcpu->arch.pio.size, pd);
4383 else
4384 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4385 vcpu->arch.pio.port, vcpu->arch.pio.size,
4386 pd);
4387 return r;
4388}
4389
6f6fbe98
XG		 4390static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4391 unsigned short port, void *val,
4392 unsigned int count, bool in)
cf8f70bf 4393{
6f6fbe98 4394 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4395
4396 vcpu->arch.pio.port = port;
6f6fbe98 4397 vcpu->arch.pio.in = in;
7972995b 4398 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4399 vcpu->arch.pio.size = size;
4400
4401 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4402 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4403 return 1;
4404 }
4405
4406 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4407 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4408 vcpu->run->io.size = size;
4409 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4410 vcpu->run->io.count = count;
4411 vcpu->run->io.port = port;
4412
4413 return 0;
4414}
4415
6f6fbe98
XG		 4416static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4417 int size, unsigned short port, void *val,
4418 unsigned int count)
cf8f70bf 4419{
ca1d4a9e 4420 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4421 int ret;
ca1d4a9e 4422
6f6fbe98
XG		 4423 if (vcpu->arch.pio.count)
4424 goto data_avail;
cf8f70bf 4425
6f6fbe98
XG		 4426 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4427 if (ret) {
4428data_avail:
4429 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4430 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4431 return 1;
4432 }
4433
cf8f70bf
GN		 4434 return 0;
4435}
4436
6f6fbe98
XG		 4437static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4438 int size, unsigned short port,
4439 const void *val, unsigned int count)
4440{
4441 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4442
4443 memcpy(vcpu->arch.pio_data, val, size * count);
4444 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4445}
4446
bbd9b64e
CO		 4447static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4448{
4449 return kvm_x86_ops->get_segment_base(vcpu, seg);
4450}
4451
3cb16fe7 4452static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4453{
3cb16fe7 4454 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4455}
4456
f5f48ee1
SY		 4457int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4458{
4459 if (!need_emulate_wbinvd(vcpu))
4460 return X86EMUL_CONTINUE;
4461
4462 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4463 int cpu = get_cpu();
4464
4465 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4466 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4467 wbinvd_ipi, NULL, 1);
2eec7343 4468 put_cpu();
f5f48ee1 4469 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4470 } else
4471 wbinvd();
f5f48ee1
SY		 4472 return X86EMUL_CONTINUE;
4473}
4474EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4475
bcaf5cc5
AK		 4476static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4477{
4478 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4479}
4480
717746e3 4481int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4482{
717746e3 4483 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4484}
4485
717746e3 4486int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4487{
338dbc97 4488
717746e3 4489 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4490}
4491
52a46617 4492static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4493{
52a46617 4494 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4495}
4496
717746e3 4497static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4498{
717746e3 4499 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4500 unsigned long value;
4501
4502 switch (cr) {
4503 case 0:
4504 value = kvm_read_cr0(vcpu);
4505 break;
4506 case 2:
4507 value = vcpu->arch.cr2;
4508 break;
4509 case 3:
9f8fe504 4510 value = kvm_read_cr3(vcpu);
52a46617
GN		 4511 break;
4512 case 4:
4513 value = kvm_read_cr4(vcpu);
4514 break;
4515 case 8:
4516 value = kvm_get_cr8(vcpu);
4517 break;
4518 default:
a737f256 4519 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4520 return 0;
4521 }
4522
4523 return value;
4524}
4525
717746e3 4526static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4527{
717746e3 4528 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4529 int res = 0;
4530
52a46617
GN		 4531 switch (cr) {
4532 case 0:
49a9b07e 4533 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4534 break;
4535 case 2:
4536 vcpu->arch.cr2 = val;
4537 break;
4538 case 3:
2390218b 4539 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4540 break;
4541 case 4:
a83b29c6 4542 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4543 break;
4544 case 8:
eea1cff9 4545 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4546 break;
4547 default:
a737f256 4548 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4549 res = -1;
52a46617 4550 }
0f12244f
GN		 4551
4552 return res;
52a46617
GN		 4553}
4554
4cee4798
KW		 4555static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4556{
4557 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4558}
4559
717746e3 4560static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4561{
717746e3 4562 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4563}
4564
4bff1e86 4565static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4566{
4bff1e86 4567 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4568}
4569
4bff1e86 4570static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4571{
4bff1e86 4572 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4573}
4574
1ac9d0cf
AK		 4575static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4576{
4577 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4578}
4579
4580static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4581{
4582 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4583}
4584
4bff1e86
AK		 4585static unsigned long emulator_get_cached_segment_base(
4586 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4587{
4bff1e86 4588 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4589}
4590
1aa36616
AK		 4591static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4592 struct desc_struct *desc, u32 *base3,
4593 int seg)
2dafc6c2
GN		 4594{
4595 struct kvm_segment var;
4596
4bff1e86 4597 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4598 *selector = var.selector;
2dafc6c2 4599
378a8b09
GN		 4600 if (var.unusable) {
4601 memset(desc, 0, sizeof(*desc));
2dafc6c2 4602 return false;
378a8b09 4603 }
2dafc6c2
GN		 4604
4605 if (var.g)
4606 var.limit >>= 12;
4607 set_desc_limit(desc, var.limit);
4608 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4609#ifdef CONFIG_X86_64
4610 if (base3)
4611 *base3 = var.base >> 32;
4612#endif
2dafc6c2
GN		 4613 desc->type = var.type;
4614 desc->s = var.s;
4615 desc->dpl = var.dpl;
4616 desc->p = var.present;
4617 desc->avl = var.avl;
4618 desc->l = var.l;
4619 desc->d = var.db;
4620 desc->g = var.g;
4621
4622 return true;
4623}
4624
1aa36616
AK		 4625static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4626 struct desc_struct *desc, u32 base3,
4627 int seg)
2dafc6c2 4628{
4bff1e86 4629 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4630 struct kvm_segment var;
4631
1aa36616 4632 var.selector = selector;
2dafc6c2 4633 var.base = get_desc_base(desc);
5601d05b
GN		 4634#ifdef CONFIG_X86_64
4635 var.base |= ((u64)base3) << 32;
4636#endif
2dafc6c2
GN		 4637 var.limit = get_desc_limit(desc);
4638 if (desc->g)
4639 var.limit = (var.limit << 12) | 0xfff;
4640 var.type = desc->type;
4641 var.present = desc->p;
4642 var.dpl = desc->dpl;
4643 var.db = desc->d;
4644 var.s = desc->s;
4645 var.l = desc->l;
4646 var.g = desc->g;
4647 var.avl = desc->avl;
4648 var.present = desc->p;
4649 var.unusable = !var.present;
4650 var.padding = 0;
4651
4652 kvm_set_segment(vcpu, &var, seg);
4653 return;
4654}
4655
717746e3
AK		 4656static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4657 u32 msr_index, u64 *pdata)
4658{
4659 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4660}
4661
4662static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4663 u32 msr_index, u64 data)
4664{
8fe8ab46
WA		 4665 struct msr_data msr;
4666
4667 msr.data = data;
4668 msr.index = msr_index;
4669 msr.host_initiated = false;
4670 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4671}
4672
222d21aa
AK		 4673static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4674 u32 pmc, u64 *pdata)
4675{
4676 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4677}
4678
6c3287f7
AK		 4679static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4680{
4681 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4682}
4683
5037f6f3
AK		 4684static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4685{
4686 preempt_disable();
5197b808 4687 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4688 /*
4689 * CR0.TS may reference the host fpu state, not the guest fpu state,
4690 * so it may be clear at this point.
4691 */
4692 clts();
4693}
4694
4695static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4696{
4697 preempt_enable();
4698}
4699
2953538e 4700static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4701 struct x86_instruction_info *info,
c4f035c6
AK		 4702 enum x86_intercept_stage stage)
4703{
2953538e 4704 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4705}
4706
0017f93a 4707static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4708 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4709{
0017f93a 4710 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4711}
4712
dd856efa
AK		 4713static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4714{
4715 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4716}
4717
4718static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4719{
4720 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4721}
4722
0225fb50 4723static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4724 .read_gpr = emulator_read_gpr,
4725 .write_gpr = emulator_write_gpr,
1871c602 4726 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4727 .write_std = kvm_write_guest_virt_system,
1871c602 4728 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4729 .read_emulated = emulator_read_emulated,
4730 .write_emulated = emulator_write_emulated,
4731 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4732 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4733 .pio_in_emulated = emulator_pio_in_emulated,
4734 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4735 .get_segment = emulator_get_segment,
4736 .set_segment = emulator_set_segment,
5951c442 4737 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4738 .get_gdt = emulator_get_gdt,
160ce1f1 4739 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4740 .set_gdt = emulator_set_gdt,
4741 .set_idt = emulator_set_idt,
52a46617
GN		 4742 .get_cr = emulator_get_cr,
4743 .set_cr = emulator_set_cr,
4cee4798 4744 .set_rflags = emulator_set_rflags,
9c537244 4745 .cpl = emulator_get_cpl,
35aa5375
GN		 4746 .get_dr = emulator_get_dr,
4747 .set_dr = emulator_set_dr,
717746e3
AK		 4748 .set_msr = emulator_set_msr,
4749 .get_msr = emulator_get_msr,
222d21aa 4750 .read_pmc = emulator_read_pmc,
6c3287f7 4751 .halt = emulator_halt,
bcaf5cc5 4752 .wbinvd = emulator_wbinvd,
d6aa1000 4753 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4754 .get_fpu = emulator_get_fpu,
4755 .put_fpu = emulator_put_fpu,
c4f035c6 4756 .intercept = emulator_intercept,
bdb42f5a 4757 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4758};
4759
95cb2295
GN		 4760static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4761{
4762 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4763 /*
4764 * an sti; sti; sequence only disable interrupts for the first
4765 * instruction. So, if the last instruction, be it emulated or
4766 * not, left the system with the INT_STI flag enabled, it
4767 * means that the last instruction is an sti. We should not
4768 * leave the flag on in this case. The same goes for mov ss
4769 */
4770 if (!(int_shadow & mask))
4771 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4772}
4773
54b8486f
GN		 4774static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4775{
4776 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4777 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4778 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4779 else if (ctxt->exception.error_code_valid)
4780 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4781 ctxt->exception.error_code);
54b8486f 4782 else
da9cb575 4783 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4784}
4785
dd856efa 4786static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4787{
1ce19dc1
BP		 4788 memset(&ctxt->opcode_len, 0,
4789 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4790
9dac77fa
AK		 4791 ctxt->fetch.start = 0;
4792 ctxt->fetch.end = 0;
4793 ctxt->io_read.pos = 0;
4794 ctxt->io_read.end = 0;
4795 ctxt->mem_read.pos = 0;
4796 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4797}
4798
8ec4722d
MG		 4799static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4800{
adf52235 4801 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4802 int cs_db, cs_l;
4803
8ec4722d
MG		 4804 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4805
adf52235
TY		 4806 ctxt->eflags = kvm_get_rflags(vcpu);
4807 ctxt->eip = kvm_rip_read(vcpu);
4808 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4809 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4810 cs_l ? X86EMUL_MODE_PROT64 :
4811 cs_db ? X86EMUL_MODE_PROT32 :
4812 X86EMUL_MODE_PROT16;
4813 ctxt->guest_mode = is_guest_mode(vcpu);
4814
dd856efa 4815 init_decode_cache(ctxt);
7ae441ea 4816 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4817}
4818
71f9833b 4819int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4820{
9d74191a 4821 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4822 int ret;
4823
4824 init_emulate_ctxt(vcpu);
4825
9dac77fa
AK		 4826 ctxt->op_bytes = 2;
4827 ctxt->ad_bytes = 2;
4828 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4829 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4830
4831 if (ret != X86EMUL_CONTINUE)
4832 return EMULATE_FAIL;
4833
9dac77fa 4834 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4835 kvm_rip_write(vcpu, ctxt->eip);
4836 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4837
4838 if (irq == NMI_VECTOR)
7460fb4a 4839 vcpu->arch.nmi_pending = 0;
63995653
MG		 4840 else
4841 vcpu->arch.interrupt.pending = false;
4842
4843 return EMULATE_DONE;
4844}
4845EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4846
6d77dbfc
GN		 4847static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4848{
fc3a9157
JR		 4849 int r = EMULATE_DONE;
4850
6d77dbfc
GN		 4851 ++vcpu->stat.insn_emulation_fail;
4852 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4853 if (!is_guest_mode(vcpu)) {
4854 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4855 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4856 vcpu->run->internal.ndata = 0;
4857 r = EMULATE_FAIL;
4858 }
6d77dbfc 4859 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4860
4861 return r;
6d77dbfc
GN		 4862}
4863
93c05d3e 4864static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4865 bool write_fault_to_shadow_pgtable,
4866 int emulation_type)
a6f177ef 4867{
95b3cf69 4868 gpa_t gpa = cr2;
8e3d9d06 4869 pfn_t pfn;
a6f177ef 4870
991eebf9
GN		 4871 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4872 return false;
4873
95b3cf69
XG		 4874 if (!vcpu->arch.mmu.direct_map) {
4875 /*
4876 * Write permission should be allowed since only
4877 * write access need to be emulated.
4878 */
4879 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4880
95b3cf69
XG		 4881 /*
4882 * If the mapping is invalid in guest, let cpu retry
4883 * it to generate fault.
4884 */
4885 if (gpa == UNMAPPED_GVA)
4886 return true;
4887 }
a6f177ef 4888
8e3d9d06
XG		 4889 /*
4890 * Do not retry the unhandleable instruction if it faults on the
4891 * readonly host memory, otherwise it will goto a infinite loop:
4892 * retry instruction -> write #PF -> emulation fail -> retry
4893 * instruction -> ...
4894 */
4895 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4896
4897 /*
4898 * If the instruction failed on the error pfn, it can not be fixed,
4899 * report the error to userspace.
4900 */
4901 if (is_error_noslot_pfn(pfn))
4902 return false;
4903
4904 kvm_release_pfn_clean(pfn);
4905
4906 /* The instructions are well-emulated on direct mmu. */
4907 if (vcpu->arch.mmu.direct_map) {
4908 unsigned int indirect_shadow_pages;
4909
4910 spin_lock(&vcpu->kvm->mmu_lock);
4911 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4912 spin_unlock(&vcpu->kvm->mmu_lock);
4913
4914 if (indirect_shadow_pages)
4915 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4916
a6f177ef 4917 return true;
8e3d9d06 4918 }
a6f177ef 4919
95b3cf69
XG		 4920 /*
4921 * if emulation was due to access to shadowed page table
4922 * and it failed try to unshadow page and re-enter the
4923 * guest to let CPU execute the instruction.
4924 */
4925 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4926
4927 /*
4928 * If the access faults on its page table, it can not
4929 * be fixed by unprotecting shadow page and it should
4930 * be reported to userspace.
4931 */
4932 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4933}
4934
1cb3f3ae
XG		 4935static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4936 unsigned long cr2, int emulation_type)
4937{
4938 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4939 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4940
4941 last_retry_eip = vcpu->arch.last_retry_eip;
4942 last_retry_addr = vcpu->arch.last_retry_addr;
4943
4944 /*
4945 * If the emulation is caused by #PF and it is non-page_table
4946 * writing instruction, it means the VM-EXIT is caused by shadow
4947 * page protected, we can zap the shadow page and retry this
4948 * instruction directly.
4949 *
4950 * Note: if the guest uses a non-page-table modifying instruction
4951 * on the PDE that points to the instruction, then we will unmap
4952 * the instruction and go to an infinite loop. So, we cache the
4953 * last retried eip and the last fault address, if we meet the eip
4954 * and the address again, we can break out of the potential infinite
4955 * loop.
4956 */
4957 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4958
4959 if (!(emulation_type & EMULTYPE_RETRY))
4960 return false;
4961
4962 if (x86_page_table_writing_insn(ctxt))
4963 return false;
4964
4965 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4966 return false;
4967
4968 vcpu->arch.last_retry_eip = ctxt->eip;
4969 vcpu->arch.last_retry_addr = cr2;
4970
4971 if (!vcpu->arch.mmu.direct_map)
4972 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4973
22368028 4974 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4975
4976 return true;
4977}
4978
716d51ab
GN		 4979static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4980static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4981
4a1e10d5
PB		 4982static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
4983 unsigned long *db)
4984{
4985 u32 dr6 = 0;
4986 int i;
4987 u32 enable, rwlen;
4988
4989 enable = dr7;
4990 rwlen = dr7 >> 16;
4991 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
4992 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
4993 dr6 |= (1 << i);
4994 return dr6;
4995}
4996
663f4c61
PB		 4997static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
4998{
4999 struct kvm_run *kvm_run = vcpu->run;
5000
5001 /*
5002 * Use the "raw" value to see if TF was passed to the processor.
5003 * Note that the new value of the flags has not been saved yet.
5004 *
5005 * This is correct even for TF set by the guest, because "the
5006 * processor will not generate this exception after the instruction
5007 * that sets the TF flag".
5008 */
5009 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5010
5011 if (unlikely(rflags & X86_EFLAGS_TF)) {
5012 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5013 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5014 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5015 kvm_run->debug.arch.exception = DB_VECTOR;
5016 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5017 *r = EMULATE_USER_EXIT;
5018 } else {
5019 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5020 /*
5021 * "Certain debug exceptions may clear bit 0-3. The
5022 * remaining contents of the DR6 register are never
5023 * cleared by the processor".
5024 */
5025 vcpu->arch.dr6 &= ~15;
5026 vcpu->arch.dr6 |= DR6_BS;
5027 kvm_queue_exception(vcpu, DB_VECTOR);
5028 }
5029 }
5030}
5031
4a1e10d5
PB		 5032static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5033{
5034 struct kvm_run *kvm_run = vcpu->run;
5035 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5036 u32 dr6 = 0;
5037
5038 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5039 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5040 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5041 vcpu->arch.guest_debug_dr7,
5042 vcpu->arch.eff_db);
5043
5044 if (dr6 != 0) {
5045 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5046 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5047 get_segment_base(vcpu, VCPU_SREG_CS);
5048
5049 kvm_run->debug.arch.exception = DB_VECTOR;
5050 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5051 *r = EMULATE_USER_EXIT;
5052 return true;
5053 }
5054 }
5055
5056 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5057 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5058 vcpu->arch.dr7,
5059 vcpu->arch.db);
5060
5061 if (dr6 != 0) {
5062 vcpu->arch.dr6 &= ~15;
5063 vcpu->arch.dr6 |= dr6;
5064 kvm_queue_exception(vcpu, DB_VECTOR);
5065 *r = EMULATE_DONE;
5066 return true;
5067 }
5068 }
5069
5070 return false;
5071}
5072
51d8b661
AP		 5073int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5074 unsigned long cr2,
dc25e89e
AP		 5075 int emulation_type,
5076 void *insn,
5077 int insn_len)
bbd9b64e 5078{
95cb2295 5079 int r;
9d74191a 5080 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5081 bool writeback = true;
93c05d3e 5082 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5083
93c05d3e
XG		 5084 /*
5085 * Clear write_fault_to_shadow_pgtable here to ensure it is
5086 * never reused.
5087 */
5088 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5089 kvm_clear_exception_queue(vcpu);
8d7d8102 5090
571008da 5091 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5092 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5093
5094 /*
5095 * We will reenter on the same instruction since
5096 * we do not set complete_userspace_io. This does not
5097 * handle watchpoints yet, those would be handled in
5098 * the emulate_ops.
5099 */
5100 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5101 return r;
5102
9d74191a
TY		 5103 ctxt->interruptibility = 0;
5104 ctxt->have_exception = false;
5105 ctxt->perm_ok = false;
bbd9b64e 5106
b51e974f 5107 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5108
9d74191a 5109 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5110
e46479f8 5111 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5112 ++vcpu->stat.insn_emulation;
1d2887e2 5113 if (r != EMULATION_OK) {
4005996e
AK		 5114 if (emulation_type & EMULTYPE_TRAP_UD)
5115 return EMULATE_FAIL;
991eebf9
GN		 5116 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5117 emulation_type))
bbd9b64e 5118 return EMULATE_DONE;
6d77dbfc
GN		 5119 if (emulation_type & EMULTYPE_SKIP)
5120 return EMULATE_FAIL;
5121 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5122 }
5123 }
5124
ba8afb6b 5125 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5126 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5127 return EMULATE_DONE;
5128 }
5129
1cb3f3ae
XG		 5130 if (retry_instruction(ctxt, cr2, emulation_type))
5131 return EMULATE_DONE;
5132
7ae441ea 5133 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5134 changes registers values during IO operation */
7ae441ea
GN		 5135 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5136 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5137 emulator_invalidate_register_cache(ctxt);
7ae441ea 5138 }
4d2179e1 5139
5cd21917 5140restart:
9d74191a 5141 r = x86_emulate_insn(ctxt);
bbd9b64e 5142
775fde86
JR		 5143 if (r == EMULATION_INTERCEPTED)
5144 return EMULATE_DONE;
5145
d2ddd1c4 5146 if (r == EMULATION_FAILED) {
991eebf9
GN		 5147 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5148 emulation_type))
c3cd7ffa
GN		 5149 return EMULATE_DONE;
5150
6d77dbfc 5151 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5152 }
5153
9d74191a 5154 if (ctxt->have_exception) {
54b8486f 5155 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5156 r = EMULATE_DONE;
5157 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5158 if (!vcpu->arch.pio.in) {
5159 /* FIXME: return into emulator if single-stepping. */
3457e419 5160 vcpu->arch.pio.count = 0;
0912c977 5161 } else {
7ae441ea 5162 writeback = false;
716d51ab
GN		 5163 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5164 }
ac0a48c3 5165 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5166 } else if (vcpu->mmio_needed) {
5167 if (!vcpu->mmio_is_write)
5168 writeback = false;
ac0a48c3 5169 r = EMULATE_USER_EXIT;
716d51ab 5170 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5171 } else if (r == EMULATION_RESTART)
5cd21917 5172 goto restart;
d2ddd1c4
GN		 5173 else
5174 r = EMULATE_DONE;
f850e2e6 5175
7ae441ea 5176 if (writeback) {
9d74191a 5177 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5178 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5179 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5180 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5181 if (r == EMULATE_DONE)
5182 kvm_vcpu_check_singlestep(vcpu, &r);
5183 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5184 } else
5185 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5186
5187 return r;
de7d789a 5188}
51d8b661 5189EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5190
cf8f70bf 5191int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5192{
cf8f70bf 5193 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5194 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5195 size, port, &val, 1);
cf8f70bf 5196 /* do not return to emulator after return from userspace */
7972995b 5197 vcpu->arch.pio.count = 0;
de7d789a
CO		 5198 return ret;
5199}
cf8f70bf 5200EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5201
8cfdc000
ZA		 5202static void tsc_bad(void *info)
5203{
0a3aee0d 5204 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5205}
5206
5207static void tsc_khz_changed(void *data)
c8076604 5208{
8cfdc000
ZA		 5209 struct cpufreq_freqs *freq = data;
5210 unsigned long khz = 0;
5211
5212 if (data)
5213 khz = freq->new;
5214 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5215 khz = cpufreq_quick_get(raw_smp_processor_id());
5216 if (!khz)
5217 khz = tsc_khz;
0a3aee0d 5218 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5219}
5220
c8076604
GH		 5221static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5222 void *data)
5223{
5224 struct cpufreq_freqs *freq = data;
5225 struct kvm *kvm;
5226 struct kvm_vcpu *vcpu;
5227 int i, send_ipi = 0;
5228
8cfdc000
ZA		 5229 /*
5230 * We allow guests to temporarily run on slowing clocks,
5231 * provided we notify them after, or to run on accelerating
5232 * clocks, provided we notify them before. Thus time never
5233 * goes backwards.
5234 *
5235 * However, we have a problem. We can't atomically update
5236 * the frequency of a given CPU from this function; it is
5237 * merely a notifier, which can be called from any CPU.
5238 * Changing the TSC frequency at arbitrary points in time
5239 * requires a recomputation of local variables related to
5240 * the TSC for each VCPU. We must flag these local variables
5241 * to be updated and be sure the update takes place with the
5242 * new frequency before any guests proceed.
5243 *
5244 * Unfortunately, the combination of hotplug CPU and frequency
5245 * change creates an intractable locking scenario; the order
5246 * of when these callouts happen is undefined with respect to
5247 * CPU hotplug, and they can race with each other. As such,
5248 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5249 * undefined; you can actually have a CPU frequency change take
5250 * place in between the computation of X and the setting of the
5251 * variable. To protect against this problem, all updates of
5252 * the per_cpu tsc_khz variable are done in an interrupt
5253 * protected IPI, and all callers wishing to update the value
5254 * must wait for a synchronous IPI to complete (which is trivial
5255 * if the caller is on the CPU already). This establishes the
5256 * necessary total order on variable updates.
5257 *
5258 * Note that because a guest time update may take place
5259 * anytime after the setting of the VCPU's request bit, the
5260 * correct TSC value must be set before the request. However,
5261 * to ensure the update actually makes it to any guest which
5262 * starts running in hardware virtualization between the set
5263 * and the acquisition of the spinlock, we must also ping the
5264 * CPU after setting the request bit.
5265 *
5266 */
5267
c8076604
GH		 5268 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5269 return 0;
5270 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5271 return 0;
8cfdc000
ZA		 5272
5273 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5274
2f303b74 5275 spin_lock(&kvm_lock);
c8076604 5276 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5277 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5278 if (vcpu->cpu != freq->cpu)
5279 continue;
c285545f 5280 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5281 if (vcpu->cpu != smp_processor_id())
8cfdc000 5282 send_ipi = 1;
c8076604
GH		 5283 }
5284 }
2f303b74 5285 spin_unlock(&kvm_lock);
c8076604
GH		 5286
5287 if (freq->old < freq->new && send_ipi) {
5288 /*
5289 * We upscale the frequency. Must make the guest
5290 * doesn't see old kvmclock values while running with
5291 * the new frequency, otherwise we risk the guest sees
5292 * time go backwards.
5293 *
5294 * In case we update the frequency for another cpu
5295 * (which might be in guest context) send an interrupt
5296 * to kick the cpu out of guest context. Next time
5297 * guest context is entered kvmclock will be updated,
5298 * so the guest will not see stale values.
5299 */
8cfdc000 5300 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5301 }
5302 return 0;
5303}
5304
5305static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5306 .notifier_call = kvmclock_cpufreq_notifier
5307};
5308
5309static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5310 unsigned long action, void *hcpu)
5311{
5312 unsigned int cpu = (unsigned long)hcpu;
5313
5314 switch (action) {
5315 case CPU_ONLINE:
5316 case CPU_DOWN_FAILED:
5317 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5318 break;
5319 case CPU_DOWN_PREPARE:
5320 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5321 break;
5322 }
5323 return NOTIFY_OK;
5324}
5325
5326static struct notifier_block kvmclock_cpu_notifier_block = {
5327 .notifier_call = kvmclock_cpu_notifier,
5328 .priority = -INT_MAX
c8076604
GH		 5329};
5330
b820cc0c
ZA		 5331static void kvm_timer_init(void)
5332{
5333 int cpu;
5334
c285545f 5335 max_tsc_khz = tsc_khz;
8cfdc000 5336 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5337 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5338#ifdef CONFIG_CPU_FREQ
5339 struct cpufreq_policy policy;
5340 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5341 cpu = get_cpu();
5342 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5343 if (policy.cpuinfo.max_freq)
5344 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5345 put_cpu();
c285545f 5346#endif
b820cc0c
ZA		 5347 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5348 CPUFREQ_TRANSITION_NOTIFIER);
5349 }
c285545f 5350 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5351 for_each_online_cpu(cpu)
5352 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5353}
5354
ff9d07a0
ZY		 5355static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5356
f5132b01 5357int kvm_is_in_guest(void)
ff9d07a0 5358{
086c9855 5359 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5360}
5361
5362static int kvm_is_user_mode(void)
5363{
5364 int user_mode = 3;
dcf46b94 5365
086c9855
AS		 5366 if (__this_cpu_read(current_vcpu))
5367 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5368
ff9d07a0
ZY		 5369 return user_mode != 0;
5370}
5371
5372static unsigned long kvm_get_guest_ip(void)
5373{
5374 unsigned long ip = 0;
dcf46b94 5375
086c9855
AS		 5376 if (__this_cpu_read(current_vcpu))
5377 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5378
ff9d07a0
ZY		 5379 return ip;
5380}
5381
5382static struct perf_guest_info_callbacks kvm_guest_cbs = {
5383 .is_in_guest = kvm_is_in_guest,
5384 .is_user_mode = kvm_is_user_mode,
5385 .get_guest_ip = kvm_get_guest_ip,
5386};
5387
5388void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5389{
086c9855 5390 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5391}
5392EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5393
5394void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5395{
086c9855 5396 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5397}
5398EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5399
ce88decf
XG		 5400static void kvm_set_mmio_spte_mask(void)
5401{
5402 u64 mask;
5403 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5404
5405 /*
5406 * Set the reserved bits and the present bit of an paging-structure
5407 * entry to generate page fault with PFER.RSV = 1.
5408 */
885032b9
XG		 5409 /* Mask the reserved physical address bits. */
5410 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5411
5412 /* Bit 62 is always reserved for 32bit host. */
5413 mask |= 0x3ull << 62;
5414
5415 /* Set the present bit. */
ce88decf
XG		 5416 mask |= 1ull;
5417
5418#ifdef CONFIG_X86_64
5419 /*
5420 * If reserved bit is not supported, clear the present bit to disable
5421 * mmio page fault.
5422 */
5423 if (maxphyaddr == 52)
5424 mask &= ~1ull;
5425#endif
5426
5427 kvm_mmu_set_mmio_spte_mask(mask);
5428}
5429
16e8d74d
MT		 5430#ifdef CONFIG_X86_64
5431static void pvclock_gtod_update_fn(struct work_struct *work)
5432{
d828199e
MT		 5433 struct kvm *kvm;
5434
5435 struct kvm_vcpu *vcpu;
5436 int i;
5437
2f303b74 5438 spin_lock(&kvm_lock);
d828199e
MT		 5439 list_for_each_entry(kvm, &vm_list, vm_list)
5440 kvm_for_each_vcpu(i, vcpu, kvm)
5441 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5442 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5443 spin_unlock(&kvm_lock);
16e8d74d
MT		 5444}
5445
5446static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5447
5448/*
5449 * Notification about pvclock gtod data update.
5450 */
5451static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5452 void *priv)
5453{
5454 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5455 struct timekeeper *tk = priv;
5456
5457 update_pvclock_gtod(tk);
5458
5459 /* disable master clock if host does not trust, or does not
5460 * use, TSC clocksource
5461 */
5462 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5463 atomic_read(&kvm_guest_has_master_clock) != 0)
5464 queue_work(system_long_wq, &pvclock_gtod_work);
5465
5466 return 0;
5467}
5468
5469static struct notifier_block pvclock_gtod_notifier = {
5470 .notifier_call = pvclock_gtod_notify,
5471};
5472#endif
5473
f8c16bba 5474int kvm_arch_init(void *opaque)
043405e1 5475{
b820cc0c 5476 int r;
6b61edf7 5477 struct kvm_x86_ops *ops = opaque;
f8c16bba 5478
f8c16bba
ZX		 5479 if (kvm_x86_ops) {
5480 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5481 r = -EEXIST;
5482 goto out;
f8c16bba
ZX		 5483 }
5484
5485 if (!ops->cpu_has_kvm_support()) {
5486 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5487 r = -EOPNOTSUPP;
5488 goto out;
f8c16bba
ZX		 5489 }
5490 if (ops->disabled_by_bios()) {
5491 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5492 r = -EOPNOTSUPP;
5493 goto out;
f8c16bba
ZX		 5494 }
5495
013f6a5d
MT		 5496 r = -ENOMEM;
5497 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5498 if (!shared_msrs) {
5499 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5500 goto out;
5501 }
5502
97db56ce
AK		 5503 r = kvm_mmu_module_init();
5504 if (r)
013f6a5d 5505 goto out_free_percpu;
97db56ce 5506
ce88decf 5507 kvm_set_mmio_spte_mask();
97db56ce
AK		 5508 kvm_init_msr_list();
5509
f8c16bba 5510 kvm_x86_ops = ops;
7b52345e 5511 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5512 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5513
b820cc0c 5514 kvm_timer_init();
c8076604 5515
ff9d07a0
ZY		 5516 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5517
2acf923e
DC		 5518 if (cpu_has_xsave)
5519 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5520
c5cc421b 5521 kvm_lapic_init();
16e8d74d
MT		 5522#ifdef CONFIG_X86_64
5523 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5524#endif
5525
f8c16bba 5526 return 0;
56c6d28a 5527
013f6a5d
MT		 5528out_free_percpu:
5529 free_percpu(shared_msrs);
56c6d28a 5530out:
56c6d28a 5531 return r;
043405e1 5532}
8776e519 5533
f8c16bba
ZX		 5534void kvm_arch_exit(void)
5535{
ff9d07a0
ZY		 5536 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5537
888d256e
JK		 5538 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5539 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5540 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5541 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5542#ifdef CONFIG_X86_64
5543 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5544#endif
f8c16bba 5545 kvm_x86_ops = NULL;
56c6d28a 5546 kvm_mmu_module_exit();
013f6a5d 5547 free_percpu(shared_msrs);
56c6d28a 5548}
f8c16bba 5549
8776e519
HB		 5550int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5551{
5552 ++vcpu->stat.halt_exits;
5553 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5554 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5555 return 1;
5556 } else {
5557 vcpu->run->exit_reason = KVM_EXIT_HLT;
5558 return 0;
5559 }
5560}
5561EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5562
55cd8e5a
GN		 5563int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5564{
5565 u64 param, ingpa, outgpa, ret;
5566 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5567 bool fast, longmode;
5568 int cs_db, cs_l;
5569
5570 /*
5571 * hypercall generates UD from non zero cpl and real mode
5572 * per HYPER-V spec
5573 */
3eeb3288 5574 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5575 kvm_queue_exception(vcpu, UD_VECTOR);
5576 return 0;
5577 }
5578
5579 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5580 longmode = is_long_mode(vcpu) && cs_l == 1;
5581
5582 if (!longmode) {
ccd46936
GN		 5583 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5584 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5585 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5586 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5587 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5588 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5589 }
5590#ifdef CONFIG_X86_64
5591 else {
5592 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5593 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5594 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5595 }
5596#endif
5597
5598 code = param & 0xffff;
5599 fast = (param >> 16) & 0x1;
5600 rep_cnt = (param >> 32) & 0xfff;
5601 rep_idx = (param >> 48) & 0xfff;
5602
5603 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5604
c25bc163
GN		 5605 switch (code) {
5606 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5607 kvm_vcpu_on_spin(vcpu);
5608 break;
5609 default:
5610 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5611 break;
5612 }
55cd8e5a
GN		 5613
5614 ret = res | (((u64)rep_done & 0xfff) << 32);
5615 if (longmode) {
5616 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5617 } else {
5618 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5619 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5620 }
5621
5622 return 1;
5623}
5624
6aef266c
SV		 5625/*
5626 * kvm_pv_kick_cpu_op: Kick a vcpu.
5627 *
5628 * @apicid - apicid of vcpu to be kicked.
5629 */
5630static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5631{
24d2166b 5632 struct kvm_lapic_irq lapic_irq;
6aef266c 5633
24d2166b
R		 5634 lapic_irq.shorthand = 0;
5635 lapic_irq.dest_mode = 0;
5636 lapic_irq.dest_id = apicid;
6aef266c 5637
24d2166b
R		 5638 lapic_irq.delivery_mode = APIC_DM_REMRD;
5639 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5640}
5641
8776e519
HB		 5642int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5643{
5644 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5645 int r = 1;
8776e519 5646
55cd8e5a
GN		 5647 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5648 return kvm_hv_hypercall(vcpu);
5649
5fdbf976
MT		 5650 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5651 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5652 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5653 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5654 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5655
229456fc 5656 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5657
8776e519
HB		 5658 if (!is_long_mode(vcpu)) {
5659 nr &= 0xFFFFFFFF;
5660 a0 &= 0xFFFFFFFF;
5661 a1 &= 0xFFFFFFFF;
5662 a2 &= 0xFFFFFFFF;
5663 a3 &= 0xFFFFFFFF;
5664 }
5665
07708c4a
JK		 5666 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5667 ret = -KVM_EPERM;
5668 goto out;
5669 }
5670
8776e519 5671 switch (nr) {
b93463aa
AK		 5672 case KVM_HC_VAPIC_POLL_IRQ:
5673 ret = 0;
5674 break;
6aef266c
SV		 5675 case KVM_HC_KICK_CPU:
5676 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5677 ret = 0;
5678 break;
8776e519
HB		 5679 default:
5680 ret = -KVM_ENOSYS;
5681 break;
5682 }
07708c4a 5683out:
5fdbf976 5684 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5685 ++vcpu->stat.hypercalls;
2f333bcb 5686 return r;
8776e519
HB		 5687}
5688EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5689
b6785def 5690static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5691{
d6aa1000 5692 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5693 char instruction[3];
5fdbf976 5694 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5695
8776e519 5696 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5697
9d74191a 5698 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5699}
5700
b6c7a5dc
HB		 5701/*
5702 * Check if userspace requested an interrupt window, and that the
5703 * interrupt window is open.
5704 *
5705 * No need to exit to userspace if we already have an interrupt queued.
5706 */
851ba692 5707static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5708{
8061823a 5709 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5710 vcpu->run->request_interrupt_window &&
5df56646 5711 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5712}
5713
851ba692 5714static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5715{
851ba692
AK		 5716 struct kvm_run *kvm_run = vcpu->run;
5717
91586a3b 5718 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5719 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5720 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5721 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5722 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5723 else
b6c7a5dc 5724 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5725 kvm_arch_interrupt_allowed(vcpu) &&
5726 !kvm_cpu_has_interrupt(vcpu) &&
5727 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5728}
5729
4484141a 5730static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5731{
5732 struct kvm_lapic *apic = vcpu->arch.apic;
5733 struct page *page;
5734
5735 if (!apic || !apic->vapic_addr)
4484141a 5736 return 0;
b93463aa
AK		 5737
5738 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5739 if (is_error_page(page))
5740 return -EFAULT;
72dc67a6
IE		 5741
5742 vcpu->arch.apic->vapic_page = page;
4484141a 5743 return 0;
b93463aa
AK		 5744}
5745
5746static void vapic_exit(struct kvm_vcpu *vcpu)
5747{
5748 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5749 int idx;
b93463aa
AK		 5750
5751 if (!apic || !apic->vapic_addr)
5752 return;
5753
f656ce01 5754 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5755 kvm_release_page_dirty(apic->vapic_page);
5756 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5757 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5758}
5759
95ba8273
GN		 5760static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5761{
5762 int max_irr, tpr;
5763
5764 if (!kvm_x86_ops->update_cr8_intercept)
5765 return;
5766
88c808fd
AK		 5767 if (!vcpu->arch.apic)
5768 return;
5769
8db3baa2
GN		 5770 if (!vcpu->arch.apic->vapic_addr)
5771 max_irr = kvm_lapic_find_highest_irr(vcpu);
5772 else
5773 max_irr = -1;
95ba8273
GN		 5774
5775 if (max_irr != -1)
5776 max_irr >>= 4;
5777
5778 tpr = kvm_lapic_get_cr8(vcpu);
5779
5780 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5781}
5782
851ba692 5783static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5784{
5785 /* try to reinject previous events if any */
b59bb7bd 5786 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5787 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5788 vcpu->arch.exception.has_error_code,
5789 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5790 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5791 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5792 vcpu->arch.exception.error_code,
5793 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5794 return;
5795 }
5796
95ba8273
GN		 5797 if (vcpu->arch.nmi_injected) {
5798 kvm_x86_ops->set_nmi(vcpu);
5799 return;
5800 }
5801
5802 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5803 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5804 return;
5805 }
5806
5807 /* try to inject new event if pending */
5808 if (vcpu->arch.nmi_pending) {
5809 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5810 --vcpu->arch.nmi_pending;
95ba8273
GN		 5811 vcpu->arch.nmi_injected = true;
5812 kvm_x86_ops->set_nmi(vcpu);
5813 }
c7c9c56c 5814 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5815 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5816 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5817 false);
5818 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5819 }
5820 }
5821}
5822
7460fb4a
AK		 5823static void process_nmi(struct kvm_vcpu *vcpu)
5824{
5825 unsigned limit = 2;
5826
5827 /*
5828 * x86 is limited to one NMI running, and one NMI pending after it.
5829 * If an NMI is already in progress, limit further NMIs to just one.
5830 * Otherwise, allow two (and we'll inject the first one immediately).
5831 */
5832 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5833 limit = 1;
5834
5835 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5836 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5837 kvm_make_request(KVM_REQ_EVENT, vcpu);
5838}
5839
3d81bc7e 5840static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5841{
5842 u64 eoi_exit_bitmap[4];
cf9e65b7 5843 u32 tmr[8];
c7c9c56c 5844
3d81bc7e
YZ		 5845 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5846 return;
c7c9c56c
YZ		 5847
5848 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5849 memset(tmr, 0, 32);
c7c9c56c 5850
cf9e65b7 5851 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5852 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5853 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5854}
5855
9357d939
TY		 5856/*
5857 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5858 * exiting to the userspace. Otherwise, the value will be returned to the
5859 * userspace.
5860 */
851ba692 5861static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5862{
5863 int r;
6a8b1d13 5864 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5865 vcpu->run->request_interrupt_window;
730dca42 5866 bool req_immediate_exit = false;
b6c7a5dc 5867
3e007509 5868 if (vcpu->requests) {
a8eeb04a 5869 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5870 kvm_mmu_unload(vcpu);
a8eeb04a 5871 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5872 __kvm_migrate_timers(vcpu);
d828199e
MT		 5873 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5874 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5875 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5876 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5877 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5878 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5879 if (unlikely(r))
5880 goto out;
5881 }
a8eeb04a 5882 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5883 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5884 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5885 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5886 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5887 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5888 r = 0;
5889 goto out;
5890 }
a8eeb04a 5891 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5892 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5893 r = 0;
5894 goto out;
5895 }
a8eeb04a 5896 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5897 vcpu->fpu_active = 0;
5898 kvm_x86_ops->fpu_deactivate(vcpu);
5899 }
af585b92
GN		 5900 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5901 /* Page is swapped out. Do synthetic halt */
5902 vcpu->arch.apf.halted = true;
5903 r = 1;
5904 goto out;
5905 }
c9aaa895
GC		 5906 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5907 record_steal_time(vcpu);
7460fb4a
AK		 5908 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5909 process_nmi(vcpu);
f5132b01
GN		 5910 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5911 kvm_handle_pmu_event(vcpu);
5912 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5913 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5914 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5915 vcpu_scan_ioapic(vcpu);
2f52d58c 5916 }
b93463aa 5917
b463a6f7 5918 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5919 kvm_apic_accept_events(vcpu);
5920 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5921 r = 1;
5922 goto out;
5923 }
5924
b463a6f7
AK		 5925 inject_pending_event(vcpu);
5926
5927 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5928 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5929 req_immediate_exit =
5930 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5931 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5932 req_immediate_exit =
5933 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5934
5935 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5936 /*
5937 * Update architecture specific hints for APIC
5938 * virtual interrupt delivery.
5939 */
5940 if (kvm_x86_ops->hwapic_irr_update)
5941 kvm_x86_ops->hwapic_irr_update(vcpu,
5942 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5943 update_cr8_intercept(vcpu);
5944 kvm_lapic_sync_to_vapic(vcpu);
5945 }
5946 }
5947
d8368af8
AK		 5948 r = kvm_mmu_reload(vcpu);
5949 if (unlikely(r)) {
d905c069 5950 goto cancel_injection;
d8368af8
AK		 5951 }
5952
b6c7a5dc
HB		 5953 preempt_disable();
5954
5955 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5956 if (vcpu->fpu_active)
5957 kvm_load_guest_fpu(vcpu);
2acf923e 5958 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5959
6b7e2d09
XG		 5960 vcpu->mode = IN_GUEST_MODE;
5961
01b71917
MT		 5962 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5963
6b7e2d09
XG		 5964 /* We should set ->mode before check ->requests,
5965 * see the comment in make_all_cpus_request.
5966 */
01b71917 5967 smp_mb__after_srcu_read_unlock();
b6c7a5dc 5968
d94e1dc9 5969 local_irq_disable();
32f88400 5970
6b7e2d09 5971 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5972 || need_resched() || signal_pending(current)) {
6b7e2d09 5973 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5974 smp_wmb();
6c142801
AK		 5975 local_irq_enable();
5976 preempt_enable();
01b71917 5977 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 5978 r = 1;
d905c069 5979 goto cancel_injection;
6c142801
AK		 5980 }
5981
d6185f20
NHE		 5982 if (req_immediate_exit)
5983 smp_send_reschedule(vcpu->cpu);
5984
b6c7a5dc
HB		 5985 kvm_guest_enter();
5986
42dbaa5a 5987 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5988 set_debugreg(0, 7);
5989 set_debugreg(vcpu->arch.eff_db[0], 0);
5990 set_debugreg(vcpu->arch.eff_db[1], 1);
5991 set_debugreg(vcpu->arch.eff_db[2], 2);
5992 set_debugreg(vcpu->arch.eff_db[3], 3);
5993 }
b6c7a5dc 5994
229456fc 5995 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5996 kvm_x86_ops->run(vcpu);
b6c7a5dc 5997
24f1e32c
FW		 5998 /*
5999 * If the guest has used debug registers, at least dr7
6000 * will be disabled while returning to the host.
6001 * If we don't have active breakpoints in the host, we don't
6002 * care about the messed up debug address registers. But if
6003 * we have some of them active, restore the old state.
6004 */
59d8eb53 6005 if (hw_breakpoint_active())
24f1e32c 6006 hw_breakpoint_restore();
42dbaa5a 6007
886b470c
MT		 6008 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6009 native_read_tsc());
1d5f066e 6010
6b7e2d09 6011 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6012 smp_wmb();
a547c6db
YZ		 6013
6014 /* Interrupt is enabled by handle_external_intr() */
6015 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6016
6017 ++vcpu->stat.exits;
6018
6019 /*
6020 * We must have an instruction between local_irq_enable() and
6021 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6022 * the interrupt shadow. The stat.exits increment will do nicely.
6023 * But we need to prevent reordering, hence this barrier():
6024 */
6025 barrier();
6026
6027 kvm_guest_exit();
6028
6029 preempt_enable();
6030
f656ce01 6031 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6032
b6c7a5dc
HB		 6033 /*
6034 * Profile KVM exit RIPs:
6035 */
6036 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6037 unsigned long rip = kvm_rip_read(vcpu);
6038 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6039 }
6040
cc578287
ZA		 6041 if (unlikely(vcpu->arch.tsc_always_catchup))
6042 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6043
5cfb1d5a
MT		 6044 if (vcpu->arch.apic_attention)
6045 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6046
851ba692 6047 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6048 return r;
6049
6050cancel_injection:
6051 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6052 if (unlikely(vcpu->arch.apic_attention))
6053 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6054out:
6055 return r;
6056}
b6c7a5dc 6057
09cec754 6058
851ba692 6059static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6060{
6061 int r;
f656ce01 6062 struct kvm *kvm = vcpu->kvm;
d7690175 6063
f656ce01 6064 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 6065 r = vapic_enter(vcpu);
6066 if (r) {
6067 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6068 return r;
6069 }
d7690175
MT		 6070
6071 r = 1;
6072 while (r > 0) {
af585b92
GN		 6073 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6074 !vcpu->arch.apf.halted)
851ba692 6075 r = vcpu_enter_guest(vcpu);
d7690175 6076 else {
f656ce01 6077 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6078 kvm_vcpu_block(vcpu);
f656ce01 6079 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6080 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6081 kvm_apic_accept_events(vcpu);
09cec754
GN		 6082 switch(vcpu->arch.mp_state) {
6083 case KVM_MP_STATE_HALTED:
6aef266c 6084 vcpu->arch.pv.pv_unhalted = false;
d7690175 6085 vcpu->arch.mp_state =
09cec754
GN		 6086 KVM_MP_STATE_RUNNABLE;
6087 case KVM_MP_STATE_RUNNABLE:
af585b92 6088 vcpu->arch.apf.halted = false;
09cec754 6089 break;
66450a21
JK		 6090 case KVM_MP_STATE_INIT_RECEIVED:
6091 break;
09cec754
GN		 6092 default:
6093 r = -EINTR;
6094 break;
6095 }
6096 }
d7690175
MT		 6097 }
6098
09cec754
GN		 6099 if (r <= 0)
6100 break;
6101
6102 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6103 if (kvm_cpu_has_pending_timer(vcpu))
6104 kvm_inject_pending_timer_irqs(vcpu);
6105
851ba692 6106 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6107 r = -EINTR;
851ba692 6108 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6109 ++vcpu->stat.request_irq_exits;
6110 }
af585b92
GN		 6111
6112 kvm_check_async_pf_completion(vcpu);
6113
09cec754
GN		 6114 if (signal_pending(current)) {
6115 r = -EINTR;
851ba692 6116 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6117 ++vcpu->stat.signal_exits;
6118 }
6119 if (need_resched()) {
f656ce01 6120 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6121 cond_resched();
f656ce01 6122 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6123 }
b6c7a5dc
HB		 6124 }
6125
f656ce01 6126 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 6127
b93463aa
AK		 6128 vapic_exit(vcpu);
6129
b6c7a5dc
HB		 6130 return r;
6131}
6132
716d51ab
GN		 6133static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6134{
6135 int r;
6136 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6137 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6138 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6139 if (r != EMULATE_DONE)
6140 return 0;
6141 return 1;
6142}
6143
6144static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6145{
6146 BUG_ON(!vcpu->arch.pio.count);
6147
6148 return complete_emulated_io(vcpu);
6149}
6150
f78146b0
AK		 6151/*
6152 * Implements the following, as a state machine:
6153 *
6154 * read:
6155 * for each fragment
87da7e66
XG		 6156 * for each mmio piece in the fragment
6157 * write gpa, len
6158 * exit
6159 * copy data
f78146b0
AK		 6160 * execute insn
6161 *
6162 * write:
6163 * for each fragment
87da7e66
XG		 6164 * for each mmio piece in the fragment
6165 * write gpa, len
6166 * copy data
6167 * exit
f78146b0 6168 */
716d51ab 6169static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6170{
6171 struct kvm_run *run = vcpu->run;
f78146b0 6172 struct kvm_mmio_fragment *frag;
87da7e66 6173 unsigned len;
5287f194 6174
716d51ab 6175 BUG_ON(!vcpu->mmio_needed);
5287f194 6176
716d51ab 6177 /* Complete previous fragment */
87da7e66
XG		 6178 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6179 len = min(8u, frag->len);
716d51ab 6180 if (!vcpu->mmio_is_write)
87da7e66
XG		 6181 memcpy(frag->data, run->mmio.data, len);
6182
6183 if (frag->len <= 8) {
6184 /* Switch to the next fragment. */
6185 frag++;
6186 vcpu->mmio_cur_fragment++;
6187 } else {
6188 /* Go forward to the next mmio piece. */
6189 frag->data += len;
6190 frag->gpa += len;
6191 frag->len -= len;
6192 }
6193
716d51ab
GN		 6194 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6195 vcpu->mmio_needed = 0;
0912c977
PB		 6196
6197 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6198 if (vcpu->mmio_is_write)
716d51ab
GN		 6199 return 1;
6200 vcpu->mmio_read_completed = 1;
6201 return complete_emulated_io(vcpu);
6202 }
87da7e66 6203
716d51ab
GN		 6204 run->exit_reason = KVM_EXIT_MMIO;
6205 run->mmio.phys_addr = frag->gpa;
6206 if (vcpu->mmio_is_write)
87da7e66
XG		 6207 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6208 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6209 run->mmio.is_write = vcpu->mmio_is_write;
6210 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6211 return 0;
5287f194
AK		 6212}
6213
716d51ab 6214
b6c7a5dc
HB		 6215int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6216{
6217 int r;
6218 sigset_t sigsaved;
6219
e5c30142
AK		 6220 if (!tsk_used_math(current) && init_fpu(current))
6221 return -ENOMEM;
6222
ac9f6dc0
AK		 6223 if (vcpu->sigset_active)
6224 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6225
a4535290 6226 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6227 kvm_vcpu_block(vcpu);
66450a21 6228 kvm_apic_accept_events(vcpu);
d7690175 6229 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6230 r = -EAGAIN;
6231 goto out;
b6c7a5dc
HB		 6232 }
6233
b6c7a5dc 6234 /* re-sync apic's tpr */
eea1cff9
AP		 6235 if (!irqchip_in_kernel(vcpu->kvm)) {
6236 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6237 r = -EINVAL;
6238 goto out;
6239 }
6240 }
b6c7a5dc 6241
716d51ab
GN		 6242 if (unlikely(vcpu->arch.complete_userspace_io)) {
6243 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6244 vcpu->arch.complete_userspace_io = NULL;
6245 r = cui(vcpu);
6246 if (r <= 0)
6247 goto out;
6248 } else
6249 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6250
851ba692 6251 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6252
6253out:
f1d86e46 6254 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6255 if (vcpu->sigset_active)
6256 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6257
b6c7a5dc
HB		 6258 return r;
6259}
6260
6261int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6262{
7ae441ea
GN		 6263 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6264 /*
6265 * We are here if userspace calls get_regs() in the middle of
6266 * instruction emulation. Registers state needs to be copied
4a969980 6267 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6268 * that usually, but some bad designed PV devices (vmware
6269 * backdoor interface) need this to work
6270 */
dd856efa 6271 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6272 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6273 }
5fdbf976
MT		 6274 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6275 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6276 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6277 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6278 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6279 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6280 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6281 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6282#ifdef CONFIG_X86_64
5fdbf976
MT		 6283 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6284 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6285 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6286 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6287 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6288 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6289 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6290 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6291#endif
6292
5fdbf976 6293 regs->rip = kvm_rip_read(vcpu);
91586a3b 6294 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6295
b6c7a5dc
HB		 6296 return 0;
6297}
6298
6299int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6300{
7ae441ea
GN		 6301 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6302 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6303
5fdbf976
MT		 6304 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6305 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6306 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6307 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6308 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6309 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6310 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6311 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6312#ifdef CONFIG_X86_64
5fdbf976
MT		 6313 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6314 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6315 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6316 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6317 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6318 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6319 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6320 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6321#endif
6322
5fdbf976 6323 kvm_rip_write(vcpu, regs->rip);
91586a3b 6324 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6325
b4f14abd
JK		 6326 vcpu->arch.exception.pending = false;
6327
3842d135
AK		 6328 kvm_make_request(KVM_REQ_EVENT, vcpu);
6329
b6c7a5dc
HB		 6330 return 0;
6331}
6332
b6c7a5dc
HB		 6333void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6334{
6335 struct kvm_segment cs;
6336
3e6e0aab 6337 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6338 *db = cs.db;
6339 *l = cs.l;
6340}
6341EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6342
6343int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6344 struct kvm_sregs *sregs)
6345{
89a27f4d 6346 struct desc_ptr dt;
b6c7a5dc 6347
3e6e0aab
GT		 6348 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6349 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6350 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6351 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6352 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6353 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6354
3e6e0aab
GT		 6355 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6356 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6357
6358 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6359 sregs->idt.limit = dt.size;
6360 sregs->idt.base = dt.address;
b6c7a5dc 6361 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6362 sregs->gdt.limit = dt.size;
6363 sregs->gdt.base = dt.address;
b6c7a5dc 6364
4d4ec087 6365 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6366 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6367 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6368 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6369 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6370 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6371 sregs->apic_base = kvm_get_apic_base(vcpu);
6372
923c61bb 6373 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6374
36752c9b 6375 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6376 set_bit(vcpu->arch.interrupt.nr,
6377 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6378
b6c7a5dc
HB		 6379 return 0;
6380}
6381
62d9f0db
MT		 6382int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6383 struct kvm_mp_state *mp_state)
6384{
66450a21 6385 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6386 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6387 vcpu->arch.pv.pv_unhalted)
6388 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6389 else
6390 mp_state->mp_state = vcpu->arch.mp_state;
6391
62d9f0db
MT		 6392 return 0;
6393}
6394
6395int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6396 struct kvm_mp_state *mp_state)
6397{
66450a21
JK		 6398 if (!kvm_vcpu_has_lapic(vcpu) &&
6399 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6400 return -EINVAL;
6401
6402 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6403 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6404 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6405 } else
6406 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6407 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6408 return 0;
6409}
6410
7f3d35fd
KW		 6411int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6412 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6413{
9d74191a 6414 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6415 int ret;
e01c2426 6416
8ec4722d 6417 init_emulate_ctxt(vcpu);
c697518a 6418
7f3d35fd 6419 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6420 has_error_code, error_code);
c697518a 6421
c697518a 6422 if (ret)
19d04437 6423 return EMULATE_FAIL;
37817f29 6424
9d74191a
TY		 6425 kvm_rip_write(vcpu, ctxt->eip);
6426 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6427 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6428 return EMULATE_DONE;
37817f29
IE		 6429}
6430EXPORT_SYMBOL_GPL(kvm_task_switch);
6431
b6c7a5dc
HB		 6432int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6433 struct kvm_sregs *sregs)
6434{
6435 int mmu_reset_needed = 0;
63f42e02 6436 int pending_vec, max_bits, idx;
89a27f4d 6437 struct desc_ptr dt;
b6c7a5dc 6438
6d1068b3
PM		 6439 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6440 return -EINVAL;
6441
89a27f4d
GN		 6442 dt.size = sregs->idt.limit;
6443 dt.address = sregs->idt.base;
b6c7a5dc 6444 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6445 dt.size = sregs->gdt.limit;
6446 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6447 kvm_x86_ops->set_gdt(vcpu, &dt);
6448
ad312c7c 6449 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6450 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6451 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6452 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6453
2d3ad1f4 6454 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6455
f6801dff 6456 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6457 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6458 kvm_set_apic_base(vcpu, sregs->apic_base);
6459
4d4ec087 6460 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6461 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6462 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6463
fc78f519 6464 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6465 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6466 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6467 kvm_update_cpuid(vcpu);
63f42e02
XG		 6468
6469 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6470 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6471 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6472 mmu_reset_needed = 1;
6473 }
63f42e02 6474 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6475
6476 if (mmu_reset_needed)
6477 kvm_mmu_reset_context(vcpu);
6478
a50abc3b 6479 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6480 pending_vec = find_first_bit(
6481 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6482 if (pending_vec < max_bits) {
66fd3f7f 6483 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6484 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6485 }
6486
3e6e0aab
GT		 6487 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6488 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6489 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6490 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6491 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6492 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6493
3e6e0aab
GT		 6494 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6495 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6496
5f0269f5
ME		 6497 update_cr8_intercept(vcpu);
6498
9c3e4aab 6499 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6500 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6501 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6502 !is_protmode(vcpu))
9c3e4aab
MT		 6503 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6504
3842d135
AK		 6505 kvm_make_request(KVM_REQ_EVENT, vcpu);
6506
b6c7a5dc
HB		 6507 return 0;
6508}
6509
d0bfb940
JK		 6510int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6511 struct kvm_guest_debug *dbg)
b6c7a5dc 6512{
355be0b9 6513 unsigned long rflags;
ae675ef0 6514 int i, r;
b6c7a5dc 6515
4f926bf2
JK		 6516 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6517 r = -EBUSY;
6518 if (vcpu->arch.exception.pending)
2122ff5e 6519 goto out;
4f926bf2
JK		 6520 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6521 kvm_queue_exception(vcpu, DB_VECTOR);
6522 else
6523 kvm_queue_exception(vcpu, BP_VECTOR);
6524 }
6525
91586a3b
JK		 6526 /*
6527 * Read rflags as long as potentially injected trace flags are still
6528 * filtered out.
6529 */
6530 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6531
6532 vcpu->guest_debug = dbg->control;
6533 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6534 vcpu->guest_debug = 0;
6535
6536 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6537 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6538 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6539 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6540 } else {
6541 for (i = 0; i < KVM_NR_DB_REGS; i++)
6542 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6543 }
c8639010 6544 kvm_update_dr7(vcpu);
ae675ef0 6545
f92653ee
JK		 6546 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6547 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6548 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6549
91586a3b
JK		 6550 /*
6551 * Trigger an rflags update that will inject or remove the trace
6552 * flags.
6553 */
6554 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6555
c8639010 6556 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6557
4f926bf2 6558 r = 0;
d0bfb940 6559
2122ff5e 6560out:
b6c7a5dc
HB		 6561
6562 return r;
6563}
6564
8b006791
ZX		 6565/*
6566 * Translate a guest virtual address to a guest physical address.
6567 */
6568int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6569 struct kvm_translation *tr)
6570{
6571 unsigned long vaddr = tr->linear_address;
6572 gpa_t gpa;
f656ce01 6573 int idx;
8b006791 6574
f656ce01 6575 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6576 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6577 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6578 tr->physical_address = gpa;
6579 tr->valid = gpa != UNMAPPED_GVA;
6580 tr->writeable = 1;
6581 tr->usermode = 0;
8b006791
ZX		 6582
6583 return 0;
6584}
6585
d0752060
HB		 6586int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6587{
98918833
SY		 6588 struct i387_fxsave_struct *fxsave =
6589 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6590
d0752060
HB		 6591 memcpy(fpu->fpr, fxsave->st_space, 128);
6592 fpu->fcw = fxsave->cwd;
6593 fpu->fsw = fxsave->swd;
6594 fpu->ftwx = fxsave->twd;
6595 fpu->last_opcode = fxsave->fop;
6596 fpu->last_ip = fxsave->rip;
6597 fpu->last_dp = fxsave->rdp;
6598 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6599
d0752060
HB		 6600 return 0;
6601}
6602
6603int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6604{
98918833
SY		 6605 struct i387_fxsave_struct *fxsave =
6606 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6607
d0752060
HB		 6608 memcpy(fxsave->st_space, fpu->fpr, 128);
6609 fxsave->cwd = fpu->fcw;
6610 fxsave->swd = fpu->fsw;
6611 fxsave->twd = fpu->ftwx;
6612 fxsave->fop = fpu->last_opcode;
6613 fxsave->rip = fpu->last_ip;
6614 fxsave->rdp = fpu->last_dp;
6615 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6616
d0752060
HB		 6617 return 0;
6618}
6619
10ab25cd 6620int fx_init(struct kvm_vcpu *vcpu)
d0752060 6621{
10ab25cd
JK		 6622 int err;
6623
6624 err = fpu_alloc(&vcpu->arch.guest_fpu);
6625 if (err)
6626 return err;
6627
98918833 6628 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6629
2acf923e
DC		 6630 /*
6631 * Ensure guest xcr0 is valid for loading
6632 */
6633 vcpu->arch.xcr0 = XSTATE_FP;
6634
ad312c7c 6635 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6636
6637 return 0;
d0752060
HB		 6638}
6639EXPORT_SYMBOL_GPL(fx_init);
6640
98918833
SY		 6641static void fx_free(struct kvm_vcpu *vcpu)
6642{
6643 fpu_free(&vcpu->arch.guest_fpu);
6644}
6645
d0752060
HB		 6646void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6647{
2608d7a1 6648 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6649 return;
6650
2acf923e
DC		 6651 /*
6652 * Restore all possible states in the guest,
6653 * and assume host would use all available bits.
6654 * Guest xcr0 would be loaded later.
6655 */
6656 kvm_put_guest_xcr0(vcpu);
d0752060 6657 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6658 __kernel_fpu_begin();
98918833 6659 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6660 trace_kvm_fpu(1);
d0752060 6661}
d0752060
HB		 6662
6663void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6664{
2acf923e
DC		 6665 kvm_put_guest_xcr0(vcpu);
6666
d0752060
HB		 6667 if (!vcpu->guest_fpu_loaded)
6668 return;
6669
6670 vcpu->guest_fpu_loaded = 0;
98918833 6671 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6672 __kernel_fpu_end();
f096ed85 6673 ++vcpu->stat.fpu_reload;
a8eeb04a 6674 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6675 trace_kvm_fpu(0);
d0752060 6676}
e9b11c17
ZX		 6677
6678void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6679{
12f9a48f 6680 kvmclock_reset(vcpu);
7f1ea208 6681
f5f48ee1 6682 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6683 fx_free(vcpu);
e9b11c17
ZX		 6684 kvm_x86_ops->vcpu_free(vcpu);
6685}
6686
6687struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6688 unsigned int id)
6689{
6755bae8
ZA		 6690 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6691 printk_once(KERN_WARNING
6692 "kvm: SMP vm created on host with unstable TSC; "
6693 "guest TSC will not be reliable\n");
26e5215f
AK		 6694 return kvm_x86_ops->vcpu_create(kvm, id);
6695}
e9b11c17 6696
26e5215f
AK		 6697int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6698{
6699 int r;
e9b11c17 6700
0bed3b56 6701 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6702 r = vcpu_load(vcpu);
6703 if (r)
6704 return r;
57f252f2 6705 kvm_vcpu_reset(vcpu);
8a3c1a33 6706 kvm_mmu_setup(vcpu);
e9b11c17 6707 vcpu_put(vcpu);
e9b11c17 6708
26e5215f 6709 return r;
e9b11c17
ZX		 6710}
6711
42897d86
MT		 6712int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6713{
6714 int r;
8fe8ab46 6715 struct msr_data msr;
42897d86
MT		 6716
6717 r = vcpu_load(vcpu);
6718 if (r)
6719 return r;
8fe8ab46
WA		 6720 msr.data = 0x0;
6721 msr.index = MSR_IA32_TSC;
6722 msr.host_initiated = true;
6723 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6724 vcpu_put(vcpu);
6725
6726 return r;
6727}
6728
d40ccc62 6729void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6730{
9fc77441 6731 int r;
344d9588
GN		 6732 vcpu->arch.apf.msr_val = 0;
6733
9fc77441
MT		 6734 r = vcpu_load(vcpu);
6735 BUG_ON(r);
e9b11c17
ZX		 6736 kvm_mmu_unload(vcpu);
6737 vcpu_put(vcpu);
6738
98918833 6739 fx_free(vcpu);
e9b11c17
ZX		 6740 kvm_x86_ops->vcpu_free(vcpu);
6741}
6742
66450a21 6743void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6744{
7460fb4a
AK		 6745 atomic_set(&vcpu->arch.nmi_queued, 0);
6746 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6747 vcpu->arch.nmi_injected = false;
6748
42dbaa5a
JK		 6749 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6750 vcpu->arch.dr6 = DR6_FIXED_1;
6751 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6752 kvm_update_dr7(vcpu);
42dbaa5a 6753
3842d135 6754 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6755 vcpu->arch.apf.msr_val = 0;
c9aaa895 6756 vcpu->arch.st.msr_val = 0;
3842d135 6757
12f9a48f
GC		 6758 kvmclock_reset(vcpu);
6759
af585b92
GN		 6760 kvm_clear_async_pf_completion_queue(vcpu);
6761 kvm_async_pf_hash_reset(vcpu);
6762 vcpu->arch.apf.halted = false;
3842d135 6763
f5132b01
GN		 6764 kvm_pmu_reset(vcpu);
6765
66f7b72e
JS		 6766 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6767 vcpu->arch.regs_avail = ~0;
6768 vcpu->arch.regs_dirty = ~0;
6769
57f252f2 6770 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6771}
6772
66450a21
JK		 6773void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6774{
6775 struct kvm_segment cs;
6776
6777 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6778 cs.selector = vector << 8;
6779 cs.base = vector << 12;
6780 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6781 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6782}
6783
10474ae8 6784int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6785{
ca84d1a2
ZA		 6786 struct kvm *kvm;
6787 struct kvm_vcpu *vcpu;
6788 int i;
0dd6a6ed
ZA		 6789 int ret;
6790 u64 local_tsc;
6791 u64 max_tsc = 0;
6792 bool stable, backwards_tsc = false;
18863bdd
AK		 6793
6794 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6795 ret = kvm_x86_ops->hardware_enable(garbage);
6796 if (ret != 0)
6797 return ret;
6798
6799 local_tsc = native_read_tsc();
6800 stable = !check_tsc_unstable();
6801 list_for_each_entry(kvm, &vm_list, vm_list) {
6802 kvm_for_each_vcpu(i, vcpu, kvm) {
6803 if (!stable && vcpu->cpu == smp_processor_id())
6804 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6805 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6806 backwards_tsc = true;
6807 if (vcpu->arch.last_host_tsc > max_tsc)
6808 max_tsc = vcpu->arch.last_host_tsc;
6809 }
6810 }
6811 }
6812
6813 /*
6814 * Sometimes, even reliable TSCs go backwards. This happens on
6815 * platforms that reset TSC during suspend or hibernate actions, but
6816 * maintain synchronization. We must compensate. Fortunately, we can
6817 * detect that condition here, which happens early in CPU bringup,
6818 * before any KVM threads can be running. Unfortunately, we can't
6819 * bring the TSCs fully up to date with real time, as we aren't yet far
6820 * enough into CPU bringup that we know how much real time has actually
6821 * elapsed; our helper function, get_kernel_ns() will be using boot
6822 * variables that haven't been updated yet.
6823 *
6824 * So we simply find the maximum observed TSC above, then record the
6825 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6826 * the adjustment will be applied. Note that we accumulate
6827 * adjustments, in case multiple suspend cycles happen before some VCPU
6828 * gets a chance to run again. In the event that no KVM threads get a
6829 * chance to run, we will miss the entire elapsed period, as we'll have
6830 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6831 * loose cycle time. This isn't too big a deal, since the loss will be
6832 * uniform across all VCPUs (not to mention the scenario is extremely
6833 * unlikely). It is possible that a second hibernate recovery happens
6834 * much faster than a first, causing the observed TSC here to be
6835 * smaller; this would require additional padding adjustment, which is
6836 * why we set last_host_tsc to the local tsc observed here.
6837 *
6838 * N.B. - this code below runs only on platforms with reliable TSC,
6839 * as that is the only way backwards_tsc is set above. Also note
6840 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6841 * have the same delta_cyc adjustment applied if backwards_tsc
6842 * is detected. Note further, this adjustment is only done once,
6843 * as we reset last_host_tsc on all VCPUs to stop this from being
6844 * called multiple times (one for each physical CPU bringup).
6845 *
4a969980 6846 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6847 * will be compensated by the logic in vcpu_load, which sets the TSC to
6848 * catchup mode. This will catchup all VCPUs to real time, but cannot
6849 * guarantee that they stay in perfect synchronization.
6850 */
6851 if (backwards_tsc) {
6852 u64 delta_cyc = max_tsc - local_tsc;
6853 list_for_each_entry(kvm, &vm_list, vm_list) {
6854 kvm_for_each_vcpu(i, vcpu, kvm) {
6855 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6856 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6857 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6858 &vcpu->requests);
0dd6a6ed
ZA		 6859 }
6860
6861 /*
6862 * We have to disable TSC offset matching.. if you were
6863 * booting a VM while issuing an S4 host suspend....
6864 * you may have some problem. Solving this issue is
6865 * left as an exercise to the reader.
6866 */
6867 kvm->arch.last_tsc_nsec = 0;
6868 kvm->arch.last_tsc_write = 0;
6869 }
6870
6871 }
6872 return 0;
e9b11c17
ZX		 6873}
6874
6875void kvm_arch_hardware_disable(void *garbage)
6876{
6877 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6878 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6879}
6880
6881int kvm_arch_hardware_setup(void)
6882{
6883 return kvm_x86_ops->hardware_setup();
6884}
6885
6886void kvm_arch_hardware_unsetup(void)
6887{
6888 kvm_x86_ops->hardware_unsetup();
6889}
6890
6891void kvm_arch_check_processor_compat(void *rtn)
6892{
6893 kvm_x86_ops->check_processor_compatibility(rtn);
6894}
6895
3e515705
AK		 6896bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6897{
6898 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6899}
6900
54e9818f
GN		 6901struct static_key kvm_no_apic_vcpu __read_mostly;
6902
e9b11c17
ZX		 6903int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6904{
6905 struct page *page;
6906 struct kvm *kvm;
6907 int r;
6908
6909 BUG_ON(vcpu->kvm == NULL);
6910 kvm = vcpu->kvm;
6911
6aef266c 6912 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6913 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6914 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6915 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6916 else
a4535290 6917 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6918
6919 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6920 if (!page) {
6921 r = -ENOMEM;
6922 goto fail;
6923 }
ad312c7c 6924 vcpu->arch.pio_data = page_address(page);
e9b11c17 6925
cc578287 6926 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6927
e9b11c17
ZX		 6928 r = kvm_mmu_create(vcpu);
6929 if (r < 0)
6930 goto fail_free_pio_data;
6931
6932 if (irqchip_in_kernel(kvm)) {
6933 r = kvm_create_lapic(vcpu);
6934 if (r < 0)
6935 goto fail_mmu_destroy;
54e9818f
GN		 6936 } else
6937 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6938
890ca9ae
HY		 6939 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6940 GFP_KERNEL);
6941 if (!vcpu->arch.mce_banks) {
6942 r = -ENOMEM;
443c39bc 6943 goto fail_free_lapic;
890ca9ae
HY		 6944 }
6945 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6946
f1797359
WY		 6947 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6948 r = -ENOMEM;
f5f48ee1 6949 goto fail_free_mce_banks;
f1797359 6950 }
f5f48ee1 6951
66f7b72e
JS		 6952 r = fx_init(vcpu);
6953 if (r)
6954 goto fail_free_wbinvd_dirty_mask;
6955
ba904635 6956 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6957 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6958
6959 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6960 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6961
af585b92 6962 kvm_async_pf_hash_reset(vcpu);
f5132b01 6963 kvm_pmu_init(vcpu);
af585b92 6964
e9b11c17 6965 return 0;
66f7b72e
JS		 6966fail_free_wbinvd_dirty_mask:
6967 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6968fail_free_mce_banks:
6969 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6970fail_free_lapic:
6971 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6972fail_mmu_destroy:
6973 kvm_mmu_destroy(vcpu);
6974fail_free_pio_data:
ad312c7c 6975 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6976fail:
6977 return r;
6978}
6979
6980void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6981{
f656ce01
MT		 6982 int idx;
6983
f5132b01 6984 kvm_pmu_destroy(vcpu);
36cb93fd 6985 kfree(vcpu->arch.mce_banks);
e9b11c17 6986 kvm_free_lapic(vcpu);
f656ce01 6987 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6988 kvm_mmu_destroy(vcpu);
f656ce01 6989 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6990 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6991 if (!irqchip_in_kernel(vcpu->kvm))
6992 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6993}
d19a9cd2 6994
e08b9637 6995int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6996{
e08b9637
CO		 6997 if (type)
6998 return -EINVAL;
6999
f05e70ac 7000 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7001 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7002 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7003 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7004
5550af4d
SY		 7005 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7006 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7007 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7008 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7009 &kvm->arch.irq_sources_bitmap);
5550af4d 7010
038f8c11 7011 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7012 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7013 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7014
7015 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7016
d89f5eff 7017 return 0;
d19a9cd2
ZX		 7018}
7019
7020static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7021{
9fc77441
MT		 7022 int r;
7023 r = vcpu_load(vcpu);
7024 BUG_ON(r);
d19a9cd2
ZX		 7025 kvm_mmu_unload(vcpu);
7026 vcpu_put(vcpu);
7027}
7028
7029static void kvm_free_vcpus(struct kvm *kvm)
7030{
7031 unsigned int i;
988a2cae 7032 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7033
7034 /*
7035 * Unpin any mmu pages first.
7036 */
af585b92
GN		 7037 kvm_for_each_vcpu(i, vcpu, kvm) {
7038 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7039 kvm_unload_vcpu_mmu(vcpu);
af585b92 7040 }
988a2cae
GN		 7041 kvm_for_each_vcpu(i, vcpu, kvm)
7042 kvm_arch_vcpu_free(vcpu);
7043
7044 mutex_lock(&kvm->lock);
7045 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7046 kvm->vcpus[i] = NULL;
d19a9cd2 7047
988a2cae
GN		 7048 atomic_set(&kvm->online_vcpus, 0);
7049 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7050}
7051
ad8ba2cd
SY		 7052void kvm_arch_sync_events(struct kvm *kvm)
7053{
ba4cef31 7054 kvm_free_all_assigned_devices(kvm);
aea924f6 7055 kvm_free_pit(kvm);
ad8ba2cd
SY		 7056}
7057
d19a9cd2
ZX		 7058void kvm_arch_destroy_vm(struct kvm *kvm)
7059{
27469d29
AH		 7060 if (current->mm == kvm->mm) {
7061 /*
7062 * Free memory regions allocated on behalf of userspace,
7063 * unless the the memory map has changed due to process exit
7064 * or fd copying.
7065 */
7066 struct kvm_userspace_memory_region mem;
7067 memset(&mem, 0, sizeof(mem));
7068 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7069 kvm_set_memory_region(kvm, &mem);
7070
7071 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7072 kvm_set_memory_region(kvm, &mem);
7073
7074 mem.slot = TSS_PRIVATE_MEMSLOT;
7075 kvm_set_memory_region(kvm, &mem);
7076 }
6eb55818 7077 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7078 kfree(kvm->arch.vpic);
7079 kfree(kvm->arch.vioapic);
d19a9cd2 7080 kvm_free_vcpus(kvm);
3d45830c
AK		 7081 if (kvm->arch.apic_access_page)
7082 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7083 if (kvm->arch.ept_identity_pagetable)
7084 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7085 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7086}
0de10343 7087
5587027c 7088void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7089 struct kvm_memory_slot *dont)
7090{
7091 int i;
7092
d89cc617
TY		 7093 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7094 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7095 kvm_kvfree(free->arch.rmap[i]);
7096 free->arch.rmap[i] = NULL;
77d11309 7097 }
d89cc617
TY		 7098 if (i == 0)
7099 continue;
7100
7101 if (!dont || free->arch.lpage_info[i - 1] !=
7102 dont->arch.lpage_info[i - 1]) {
7103 kvm_kvfree(free->arch.lpage_info[i - 1]);
7104 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7105 }
7106 }
7107}
7108
5587027c
AK		 7109int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7110 unsigned long npages)
db3fe4eb
TY		 7111{
7112 int i;
7113
d89cc617 7114 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7115 unsigned long ugfn;
7116 int lpages;
d89cc617 7117 int level = i + 1;
db3fe4eb
TY		 7118
7119 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7120 slot->base_gfn, level) + 1;
7121
d89cc617
TY		 7122 slot->arch.rmap[i] =
7123 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7124 if (!slot->arch.rmap[i])
77d11309 7125 goto out_free;
d89cc617
TY		 7126 if (i == 0)
7127 continue;
77d11309 7128
d89cc617
TY		 7129 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7130 sizeof(*slot->arch.lpage_info[i - 1]));
7131 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7132 goto out_free;
7133
7134 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7135 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7136 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7137 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7138 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7139 /*
7140 * If the gfn and userspace address are not aligned wrt each
7141 * other, or if explicitly asked to, disable large page
7142 * support for this slot
7143 */
7144 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7145 !kvm_largepages_enabled()) {
7146 unsigned long j;
7147
7148 for (j = 0; j < lpages; ++j)
d89cc617 7149 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7150 }
7151 }
7152
7153 return 0;
7154
7155out_free:
d89cc617
TY		 7156 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7157 kvm_kvfree(slot->arch.rmap[i]);
7158 slot->arch.rmap[i] = NULL;
7159 if (i == 0)
7160 continue;
7161
7162 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7163 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7164 }
7165 return -ENOMEM;
7166}
7167
e59dbe09
TY		 7168void kvm_arch_memslots_updated(struct kvm *kvm)
7169{
e6dff7d1
TY		 7170 /*
7171 * memslots->generation has been incremented.
7172 * mmio generation may have reached its maximum value.
7173 */
7174 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7175}
7176
f7784b8e
MT		 7177int kvm_arch_prepare_memory_region(struct kvm *kvm,
7178 struct kvm_memory_slot *memslot,
f7784b8e 7179 struct kvm_userspace_memory_region *mem,
7b6195a9 7180 enum kvm_mr_change change)
0de10343 7181{
7a905b14
TY		 7182 /*
7183 * Only private memory slots need to be mapped here since
7184 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7185 */
7b6195a9 7186 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7187 unsigned long userspace_addr;
604b38ac 7188
7a905b14
TY		 7189 /*
7190 * MAP_SHARED to prevent internal slot pages from being moved
7191 * by fork()/COW.
7192 */
7b6195a9 7193 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7194 PROT_READ | PROT_WRITE,
7195 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7196
7a905b14
TY		 7197 if (IS_ERR((void *)userspace_addr))
7198 return PTR_ERR((void *)userspace_addr);
604b38ac 7199
7a905b14 7200 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7201 }
7202
f7784b8e
MT		 7203 return 0;
7204}
7205
7206void kvm_arch_commit_memory_region(struct kvm *kvm,
7207 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7208 const struct kvm_memory_slot *old,
7209 enum kvm_mr_change change)
f7784b8e
MT		 7210{
7211
8482644a 7212 int nr_mmu_pages = 0;
f7784b8e 7213
8482644a 7214 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7215 int ret;
7216
8482644a
TY		 7217 ret = vm_munmap(old->userspace_addr,
7218 old->npages * PAGE_SIZE);
f7784b8e
MT		 7219 if (ret < 0)
7220 printk(KERN_WARNING
7221 "kvm_vm_ioctl_set_memory_region: "
7222 "failed to munmap memory\n");
7223 }
7224
48c0e4e9
XG		 7225 if (!kvm->arch.n_requested_mmu_pages)
7226 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7227
48c0e4e9 7228 if (nr_mmu_pages)
0de10343 7229 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7230 /*
7231 * Write protect all pages for dirty logging.
7232 * Existing largepage mappings are destroyed here and new ones will
7233 * not be created until the end of the logging.
7234 */
8482644a 7235 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7236 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7237}
1d737c8a 7238
2df72e9b 7239void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7240{
6ca18b69 7241 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7242}
7243
2df72e9b
MT		 7244void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7245 struct kvm_memory_slot *slot)
7246{
6ca18b69 7247 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7248}
7249
1d737c8a
ZX		 7250int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7251{
af585b92
GN		 7252 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7253 !vcpu->arch.apf.halted)
7254 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7255 || kvm_apic_has_events(vcpu)
6aef266c 7256 || vcpu->arch.pv.pv_unhalted
7460fb4a 7257 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7258 (kvm_arch_interrupt_allowed(vcpu) &&
7259 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7260}
5736199a 7261
b6d33834 7262int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7263{
b6d33834 7264 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7265}
78646121
GN		 7266
7267int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7268{
7269 return kvm_x86_ops->interrupt_allowed(vcpu);
7270}
229456fc 7271
f92653ee
JK		 7272bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7273{
7274 unsigned long current_rip = kvm_rip_read(vcpu) +
7275 get_segment_base(vcpu, VCPU_SREG_CS);
7276
7277 return current_rip == linear_rip;
7278}
7279EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7280
94fe45da
JK		 7281unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7282{
7283 unsigned long rflags;
7284
7285 rflags = kvm_x86_ops->get_rflags(vcpu);
7286 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7287 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7288 return rflags;
7289}
7290EXPORT_SYMBOL_GPL(kvm_get_rflags);
7291
7292void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7293{
7294 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7295 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7296 rflags |= X86_EFLAGS_TF;
94fe45da 7297 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7298 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7299}
7300EXPORT_SYMBOL_GPL(kvm_set_rflags);
7301
56028d08
GN		 7302void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7303{
7304 int r;
7305
fb67e14f 7306 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7307 work->wakeup_all)
56028d08
GN		 7308 return;
7309
7310 r = kvm_mmu_reload(vcpu);
7311 if (unlikely(r))
7312 return;
7313
fb67e14f
XG		 7314 if (!vcpu->arch.mmu.direct_map &&
7315 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7316 return;
7317
56028d08
GN		 7318 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7319}
7320
af585b92
GN		 7321static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7322{
7323 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7324}
7325
7326static inline u32 kvm_async_pf_next_probe(u32 key)
7327{
7328 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7329}
7330
7331static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7332{
7333 u32 key = kvm_async_pf_hash_fn(gfn);
7334
7335 while (vcpu->arch.apf.gfns[key] != ~0)
7336 key = kvm_async_pf_next_probe(key);
7337
7338 vcpu->arch.apf.gfns[key] = gfn;
7339}
7340
7341static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7342{
7343 int i;
7344 u32 key = kvm_async_pf_hash_fn(gfn);
7345
7346 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7347 (vcpu->arch.apf.gfns[key] != gfn &&
7348 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7349 key = kvm_async_pf_next_probe(key);
7350
7351 return key;
7352}
7353
7354bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7355{
7356 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7357}
7358
7359static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7360{
7361 u32 i, j, k;
7362
7363 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7364 while (true) {
7365 vcpu->arch.apf.gfns[i] = ~0;
7366 do {
7367 j = kvm_async_pf_next_probe(j);
7368 if (vcpu->arch.apf.gfns[j] == ~0)
7369 return;
7370 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7371 /*
7372 * k lies cyclically in ]i,j]
7373 * | i.k.j |
7374 * |....j i.k.| or |.k..j i...|
7375 */
7376 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7377 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7378 i = j;
7379 }
7380}
7381
7c90705b
GN		 7382static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7383{
7384
7385 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7386 sizeof(val));
7387}
7388
af585b92
GN		 7389void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7390 struct kvm_async_pf *work)
7391{
6389ee94
AK		 7392 struct x86_exception fault;
7393
7c90705b 7394 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7395 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7396
7397 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7398 (vcpu->arch.apf.send_user_only &&
7399 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7400 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7401 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7402 fault.vector = PF_VECTOR;
7403 fault.error_code_valid = true;
7404 fault.error_code = 0;
7405 fault.nested_page_fault = false;
7406 fault.address = work->arch.token;
7407 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7408 }
af585b92
GN		 7409}
7410
7411void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7412 struct kvm_async_pf *work)
7413{
6389ee94
AK		 7414 struct x86_exception fault;
7415
7c90705b 7416 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7417 if (work->wakeup_all)
7c90705b
GN		 7418 work->arch.token = ~0; /* broadcast wakeup */
7419 else
7420 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7421
7422 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7423 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7424 fault.vector = PF_VECTOR;
7425 fault.error_code_valid = true;
7426 fault.error_code = 0;
7427 fault.nested_page_fault = false;
7428 fault.address = work->arch.token;
7429 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7430 }
e6d53e3b 7431 vcpu->arch.apf.halted = false;
a4fa1635 7432 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7433}
7434
7435bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7436{
7437 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7438 return true;
7439 else
7440 return !kvm_event_needs_reinjection(vcpu) &&
7441 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7442}
7443
e0f0bbc5
AW		 7444void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7445{
7446 atomic_inc(&kvm->arch.noncoherent_dma_count);
7447}
7448EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7449
7450void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7451{
7452 atomic_dec(&kvm->arch.noncoherent_dma_count);
7453}
7454EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7455
7456bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7457{
7458 return atomic_read(&kvm->arch.noncoherent_dma_count);
7459}
7460EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7461
229456fc
MT		 7462EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7468EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7469EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7470EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7471EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7472EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7473EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7474EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux 6.x block layer and io_uring tree(s)