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kvm: x86: Defer setting of CR2 until #PF delivery
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 139unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b6785def 216static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 217
af585b92
GN		 218static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
219{
220 int i;
221 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
222 vcpu->arch.apf.gfns[i] = ~0;
223}
224
18863bdd
AK		 225static void kvm_on_user_return(struct user_return_notifier *urn)
226{
227 unsigned slot;
18863bdd
AK		 228 struct kvm_shared_msrs *locals
229 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 230 struct kvm_shared_msr_values *values;
1650b4eb
IA		 231 unsigned long flags;
232
233 /*
234 * Disabling irqs at this point since the following code could be
235 * interrupted and executed through kvm_arch_hardware_disable()
236 */
237 local_irq_save(flags);
238 if (locals->registered) {
239 locals->registered = false;
240 user_return_notifier_unregister(urn);
241 }
242 local_irq_restore(flags);
18863bdd 243 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 244 values = &locals->values[slot];
245 if (values->host != values->curr) {
246 wrmsrl(shared_msrs_global.msrs[slot], values->host);
247 values->curr = values->host;
18863bdd
AK		 248 }
249 }
18863bdd
AK		 250}
251
2bf78fa7 252static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 253{
18863bdd 254 u64 value;
013f6a5d
MT		 255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 257
2bf78fa7
SY		 258 /* only read, and nobody should modify it at this time,
259 * so don't need lock */
260 if (slot >= shared_msrs_global.nr) {
261 printk(KERN_ERR "kvm: invalid MSR slot!");
262 return;
263 }
264 rdmsrl_safe(msr, &value);
265 smsr->values[slot].host = value;
266 smsr->values[slot].curr = value;
267}
268
269void kvm_define_shared_msr(unsigned slot, u32 msr)
270{
0123be42 271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 272 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 275}
276EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278static void kvm_shared_msr_cpu_online(void)
279{
280 unsigned i;
18863bdd
AK		 281
282 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 283 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 284}
285
8b3c3104 286int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 287{
013f6a5d
MT		 288 unsigned int cpu = smp_processor_id();
289 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 290 int err;
18863bdd 291
2bf78fa7 292 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 293 return 0;
2bf78fa7 294 smsr->values[slot].curr = value;
8b3c3104
AH		 295 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
296 if (err)
297 return 1;
298
18863bdd
AK		 299 if (!smsr->registered) {
300 smsr->urn.on_user_return = kvm_on_user_return;
301 user_return_notifier_register(&smsr->urn);
302 smsr->registered = true;
303 }
8b3c3104 304 return 0;
18863bdd
AK		 305}
306EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
307
13a34e06 308static void drop_user_return_notifiers(void)
3548bab5 309{
013f6a5d
MT		 310 unsigned int cpu = smp_processor_id();
311 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 312
313 if (smsr->registered)
314 kvm_on_user_return(&smsr->urn);
315}
316
6866b83e
CO		 317u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
318{
8a5a87d9 319 return vcpu->arch.apic_base;
6866b83e
CO		 320}
321EXPORT_SYMBOL_GPL(kvm_get_apic_base);
322
58871649
JM		 323enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
324{
325 return kvm_apic_mode(kvm_get_apic_base(vcpu));
326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
328
58cb628d
JK		 329int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
330{
58871649
JM		 331 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
332 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 333 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
334 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 335
58871649 336 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 337 return 1;
58871649
JM		 338 if (!msr_info->host_initiated) {
339 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
340 return 1;
341 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
342 return 1;
343 }
58cb628d
JK		 344
345 kvm_lapic_set_base(vcpu, msr_info->data);
346 return 0;
6866b83e
CO		 347}
348EXPORT_SYMBOL_GPL(kvm_set_apic_base);
349
2605fc21 350asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 351{
352 /* Fault while not rebooting. We want the trace. */
353 BUG();
354}
355EXPORT_SYMBOL_GPL(kvm_spurious_fault);
356
3fd28fce
ED		 357#define EXCPT_BENIGN 0
358#define EXCPT_CONTRIBUTORY 1
359#define EXCPT_PF 2
360
361static int exception_class(int vector)
362{
363 switch (vector) {
364 case PF_VECTOR:
365 return EXCPT_PF;
366 case DE_VECTOR:
367 case TS_VECTOR:
368 case NP_VECTOR:
369 case SS_VECTOR:
370 case GP_VECTOR:
371 return EXCPT_CONTRIBUTORY;
372 default:
373 break;
374 }
375 return EXCPT_BENIGN;
376}
377
d6e8c854
NA		 378#define EXCPT_FAULT 0
379#define EXCPT_TRAP 1
380#define EXCPT_ABORT 2
381#define EXCPT_INTERRUPT 3
382
383static int exception_type(int vector)
384{
385 unsigned int mask;
386
387 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
388 return EXCPT_INTERRUPT;
389
390 mask = 1 << vector;
391
392 /* #DB is trap, as instruction watchpoints are handled elsewhere */
393 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
394 return EXCPT_TRAP;
395
396 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
397 return EXCPT_ABORT;
398
399 /* Reserved exceptions will result in fault */
400 return EXCPT_FAULT;
401}
402
da998b46
JM		 403void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
404{
405 unsigned nr = vcpu->arch.exception.nr;
406 bool has_payload = vcpu->arch.exception.has_payload;
407 unsigned long payload = vcpu->arch.exception.payload;
408
409 if (!has_payload)
410 return;
411
412 switch (nr) {
413 case PF_VECTOR:
414 vcpu->arch.cr2 = payload;
415 break;
416 }
417
418 vcpu->arch.exception.has_payload = false;
419 vcpu->arch.exception.payload = 0;
420}
421EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
422
3fd28fce 423static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 424 unsigned nr, bool has_error, u32 error_code,
91e86d22 425 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 426{
427 u32 prev_nr;
428 int class1, class2;
429
3842d135
AK		 430 kvm_make_request(KVM_REQ_EVENT, vcpu);
431
664f8e26 432 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 433 queue:
3ffb2468
NA		 434 if (has_error && !is_protmode(vcpu))
435 has_error = false;
664f8e26
WL		 436 if (reinject) {
437 /*
438 * On vmentry, vcpu->arch.exception.pending is only
439 * true if an event injection was blocked by
440 * nested_run_pending. In that case, however,
441 * vcpu_enter_guest requests an immediate exit,
442 * and the guest shouldn't proceed far enough to
443 * need reinjection.
444 */
445 WARN_ON_ONCE(vcpu->arch.exception.pending);
446 vcpu->arch.exception.injected = true;
91e86d22
JM		 447 if (WARN_ON_ONCE(has_payload)) {
448 /*
449 * A reinjected event has already
450 * delivered its payload.
451 */
452 has_payload = false;
453 payload = 0;
454 }
664f8e26
WL		 455 } else {
456 vcpu->arch.exception.pending = true;
457 vcpu->arch.exception.injected = false;
458 }
3fd28fce
ED		 459 vcpu->arch.exception.has_error_code = has_error;
460 vcpu->arch.exception.nr = nr;
461 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 462 vcpu->arch.exception.has_payload = has_payload;
463 vcpu->arch.exception.payload = payload;
da998b46
JM		 464 /*
465 * In guest mode, payload delivery should be deferred,
466 * so that the L1 hypervisor can intercept #PF before
467 * CR2 is modified. However, for ABI compatibility
468 * with KVM_GET_VCPU_EVENTS and KVM_SET_VCPU_EVENTS,
469 * we can't delay payload delivery unless userspace
470 * has enabled this functionality via the per-VM
471 * capability, KVM_CAP_EXCEPTION_PAYLOAD.
472 */
473 if (!vcpu->kvm->arch.exception_payload_enabled ||
474 !is_guest_mode(vcpu))
475 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 476 return;
477 }
478
479 /* to check exception */
480 prev_nr = vcpu->arch.exception.nr;
481 if (prev_nr == DF_VECTOR) {
482 /* triple fault -> shutdown */
a8eeb04a 483 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 484 return;
485 }
486 class1 = exception_class(prev_nr);
487 class2 = exception_class(nr);
488 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
489 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 490 /*
491 * Generate double fault per SDM Table 5-5. Set
492 * exception.pending = true so that the double fault
493 * can trigger a nested vmexit.
494 */
3fd28fce 495 vcpu->arch.exception.pending = true;
664f8e26 496 vcpu->arch.exception.injected = false;
3fd28fce
ED		 497 vcpu->arch.exception.has_error_code = true;
498 vcpu->arch.exception.nr = DF_VECTOR;
499 vcpu->arch.exception.error_code = 0;
c851436a
JM		 500 vcpu->arch.exception.has_payload = false;
501 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 502 } else
503 /* replace previous exception with a new one in a hope
504 that instruction re-execution will regenerate lost
505 exception */
506 goto queue;
507}
508
298101da
AK		 509void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
510{
91e86d22 511 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 512}
513EXPORT_SYMBOL_GPL(kvm_queue_exception);
514
ce7ddec4
JR		 515void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
516{
91e86d22 517 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 518}
519EXPORT_SYMBOL_GPL(kvm_requeue_exception);
520
da998b46
JM		 521static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
522 u32 error_code, unsigned long payload)
523{
524 kvm_multiple_exception(vcpu, nr, true, error_code,
525 true, payload, false);
526}
527
6affcbed 528int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 529{
db8fcefa
AP		 530 if (err)
531 kvm_inject_gp(vcpu, 0);
532 else
6affcbed
KH		 533 return kvm_skip_emulated_instruction(vcpu);
534
535 return 1;
db8fcefa
AP		 536}
537EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 538
6389ee94 539void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 540{
541 ++vcpu->stat.pf_guest;
adfe20fb
WL		 542 vcpu->arch.exception.nested_apf =
543 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 544 if (vcpu->arch.exception.nested_apf) {
adfe20fb 545 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 546 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
547 } else {
548 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
549 fault->address);
550 }
c3c91fee 551}
27d6c865 552EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 553
ef54bcfe 554static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 555{
6389ee94
AK		 556 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
557 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 558 else
44dd3ffa 559 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 560
561 return fault->nested_page_fault;
d4f8cf66
JR		 562}
563
3419ffc8
SY		 564void kvm_inject_nmi(struct kvm_vcpu *vcpu)
565{
7460fb4a
AK		 566 atomic_inc(&vcpu->arch.nmi_queued);
567 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 568}
569EXPORT_SYMBOL_GPL(kvm_inject_nmi);
570
298101da
AK		 571void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
572{
91e86d22 573 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 574}
575EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
576
ce7ddec4
JR		 577void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
578{
91e86d22 579 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 580}
581EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
582
0a79b009
AK		 583/*
584 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
585 * a #GP and return false.
586 */
587bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 588{
0a79b009
AK		 589 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
590 return true;
591 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
592 return false;
298101da 593}
0a79b009 594EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 595
16f8a6f9
NA		 596bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
597{
598 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
599 return true;
600
601 kvm_queue_exception(vcpu, UD_VECTOR);
602 return false;
603}
604EXPORT_SYMBOL_GPL(kvm_require_dr);
605
ec92fe44
JR		 606/*
607 * This function will be used to read from the physical memory of the currently
54bf36aa 608 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 609 * can read from guest physical or from the guest's guest physical memory.
610 */
611int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
612 gfn_t ngfn, void *data, int offset, int len,
613 u32 access)
614{
54987b7a 615 struct x86_exception exception;
ec92fe44
JR		 616 gfn_t real_gfn;
617 gpa_t ngpa;
618
619 ngpa = gfn_to_gpa(ngfn);
54987b7a 620 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 621 if (real_gfn == UNMAPPED_GVA)
622 return -EFAULT;
623
624 real_gfn = gpa_to_gfn(real_gfn);
625
54bf36aa 626 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 627}
628EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
629
69b0049a 630static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 631 void *data, int offset, int len, u32 access)
632{
633 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
634 data, offset, len, access);
635}
636
a03490ed
CO		 637/*
638 * Load the pae pdptrs. Return true is they are all valid.
639 */
ff03a073 640int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 641{
642 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
643 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
644 int i;
645 int ret;
ff03a073 646 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 647
ff03a073
JR		 648 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
649 offset * sizeof(u64), sizeof(pdpte),
650 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 651 if (ret < 0) {
652 ret = 0;
653 goto out;
654 }
655 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 656 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 657 (pdpte[i] &
44dd3ffa 658 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 659 ret = 0;
660 goto out;
661 }
662 }
663 ret = 1;
664
ff03a073 665 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 666 __set_bit(VCPU_EXREG_PDPTR,
667 (unsigned long *)&vcpu->arch.regs_avail);
668 __set_bit(VCPU_EXREG_PDPTR,
669 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 670out:
a03490ed
CO		 671
672 return ret;
673}
cc4b6871 674EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 675
9ed38ffa 676bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 677{
ff03a073 678 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 679 bool changed = true;
3d06b8bf
JR		 680 int offset;
681 gfn_t gfn;
d835dfec
AK		 682 int r;
683
d35b34a9 684 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 685 return false;
686
6de4f3ad
AK		 687 if (!test_bit(VCPU_EXREG_PDPTR,
688 (unsigned long *)&vcpu->arch.regs_avail))
689 return true;
690
a512177e
PB		 691 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
692 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 693 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
694 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 695 if (r < 0)
696 goto out;
ff03a073 697 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 698out:
d835dfec
AK		 699
700 return changed;
701}
9ed38ffa 702EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 703
49a9b07e 704int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 705{
aad82703 706 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 707 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 708
f9a48e6a
AK		 709 cr0 |= X86_CR0_ET;
710
ab344828 711#ifdef CONFIG_X86_64
0f12244f
GN		 712 if (cr0 & 0xffffffff00000000UL)
713 return 1;
ab344828
GN		 714#endif
715
716 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 717
0f12244f
GN		 718 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
719 return 1;
a03490ed 720
0f12244f
GN		 721 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
722 return 1;
a03490ed
CO		 723
724 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
725#ifdef CONFIG_X86_64
f6801dff 726 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 727 int cs_db, cs_l;
728
0f12244f
GN		 729 if (!is_pae(vcpu))
730 return 1;
a03490ed 731 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 732 if (cs_l)
733 return 1;
a03490ed
CO		 734 } else
735#endif
ff03a073 736 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 737 kvm_read_cr3(vcpu)))
0f12244f 738 return 1;
a03490ed
CO		 739 }
740
ad756a16
MJ		 741 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
742 return 1;
743
a03490ed 744 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 745
d170c419 746 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 747 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 748 kvm_async_pf_hash_reset(vcpu);
749 }
e5f3f027 750
aad82703
SY		 751 if ((cr0 ^ old_cr0) & update_bits)
752 kvm_mmu_reset_context(vcpu);
b18d5431 753
879ae188
LE		 754 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
755 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
756 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 757 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
758
0f12244f
GN		 759 return 0;
760}
2d3ad1f4 761EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 762
2d3ad1f4 763void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 764{
49a9b07e 765 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 766}
2d3ad1f4 767EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 768
42bdf991
MT		 769static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
770{
771 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
772 !vcpu->guest_xcr0_loaded) {
773 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 774 if (vcpu->arch.xcr0 != host_xcr0)
775 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 776 vcpu->guest_xcr0_loaded = 1;
777 }
778}
779
780static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
781{
782 if (vcpu->guest_xcr0_loaded) {
783 if (vcpu->arch.xcr0 != host_xcr0)
784 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
785 vcpu->guest_xcr0_loaded = 0;
786 }
787}
788
69b0049a 789static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 790{
56c103ec
LJ		 791 u64 xcr0 = xcr;
792 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 793 u64 valid_bits;
2acf923e
DC		 794
795 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
796 if (index != XCR_XFEATURE_ENABLED_MASK)
797 return 1;
d91cab78 798 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 799 return 1;
d91cab78 800 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 801 return 1;
46c34cb0
PB		 802
803 /*
804 * Do not allow the guest to set bits that we do not support
805 * saving. However, xcr0 bit 0 is always set, even if the
806 * emulated CPU does not support XSAVE (see fx_init).
807 */
d91cab78 808 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 809 if (xcr0 & ~valid_bits)
2acf923e 810 return 1;
46c34cb0 811
d91cab78
DH		 812 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
813 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 814 return 1;
815
d91cab78
DH		 816 if (xcr0 & XFEATURE_MASK_AVX512) {
817 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 818 return 1;
d91cab78 819 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 820 return 1;
821 }
2acf923e 822 vcpu->arch.xcr0 = xcr0;
56c103ec 823
d91cab78 824 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 825 kvm_update_cpuid(vcpu);
2acf923e
DC		 826 return 0;
827}
828
829int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
830{
764bcbc5
Z		 831 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
832 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 833 kvm_inject_gp(vcpu, 0);
834 return 1;
835 }
836 return 0;
837}
838EXPORT_SYMBOL_GPL(kvm_set_xcr);
839
a83b29c6 840int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 841{
fc78f519 842 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 843 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 844 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 845
0f12244f
GN		 846 if (cr4 & CR4_RESERVED_BITS)
847 return 1;
a03490ed 848
d6321d49 849 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 850 return 1;
851
d6321d49 852 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 853 return 1;
854
d6321d49 855 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 856 return 1;
857
d6321d49 858 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 859 return 1;
860
d6321d49 861 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 862 return 1;
863
fd8cb433 864 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 865 return 1;
866
ae3e61e1
PB		 867 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
868 return 1;
869
a03490ed 870 if (is_long_mode(vcpu)) {
0f12244f
GN		 871 if (!(cr4 & X86_CR4_PAE))
872 return 1;
a2edf57f
AK		 873 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
874 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 875 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
876 kvm_read_cr3(vcpu)))
0f12244f
GN		 877 return 1;
878
ad756a16 879 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 880 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 881 return 1;
882
883 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
884 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
885 return 1;
886 }
887
5e1746d6 888 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 889 return 1;
a03490ed 890
ad756a16
MJ		 891 if (((cr4 ^ old_cr4) & pdptr_bits) ||
892 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 893 kvm_mmu_reset_context(vcpu);
0f12244f 894
b9baba86 895 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 896 kvm_update_cpuid(vcpu);
2acf923e 897
0f12244f
GN		 898 return 0;
899}
2d3ad1f4 900EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 901
2390218b 902int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 903{
ade61e28 904 bool skip_tlb_flush = false;
ac146235 905#ifdef CONFIG_X86_64
c19986fe
JS		 906 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
907
ade61e28 908 if (pcid_enabled) {
208320ba
JS		 909 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
910 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 911 }
ac146235 912#endif
9d88fca7 913
9f8fe504 914 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 915 if (!skip_tlb_flush) {
916 kvm_mmu_sync_roots(vcpu);
ade61e28 917 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 918 }
0f12244f 919 return 0;
d835dfec
AK		 920 }
921
d1cd3ce9 922 if (is_long_mode(vcpu) &&
a780a3ea 923 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 924 return 1;
925 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 926 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 927 return 1;
a03490ed 928
ade61e28 929 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 930 vcpu->arch.cr3 = cr3;
aff48baa 931 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 932
0f12244f
GN		 933 return 0;
934}
2d3ad1f4 935EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 936
eea1cff9 937int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 938{
0f12244f
GN		 939 if (cr8 & CR8_RESERVED_BITS)
940 return 1;
35754c98 941 if (lapic_in_kernel(vcpu))
a03490ed
CO		 942 kvm_lapic_set_tpr(vcpu, cr8);
943 else
ad312c7c 944 vcpu->arch.cr8 = cr8;
0f12244f
GN		 945 return 0;
946}
2d3ad1f4 947EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 948
2d3ad1f4 949unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 950{
35754c98 951 if (lapic_in_kernel(vcpu))
a03490ed
CO		 952 return kvm_lapic_get_cr8(vcpu);
953 else
ad312c7c 954 return vcpu->arch.cr8;
a03490ed 955}
2d3ad1f4 956EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 957
ae561ede
NA		 958static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
959{
960 int i;
961
962 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
963 for (i = 0; i < KVM_NR_DB_REGS; i++)
964 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
965 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
966 }
967}
968
73aaf249
JK		 969static void kvm_update_dr6(struct kvm_vcpu *vcpu)
970{
971 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
972 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
973}
974
c8639010
JK		 975static void kvm_update_dr7(struct kvm_vcpu *vcpu)
976{
977 unsigned long dr7;
978
979 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
980 dr7 = vcpu->arch.guest_debug_dr7;
981 else
982 dr7 = vcpu->arch.dr7;
983 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 984 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
985 if (dr7 & DR7_BP_EN_MASK)
986 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 987}
988
6f43ed01
NA		 989static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
990{
991 u64 fixed = DR6_FIXED_1;
992
d6321d49 993 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 994 fixed |= DR6_RTM;
995 return fixed;
996}
997
338dbc97 998static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 999{
1000 switch (dr) {
1001 case 0 ... 3:
1002 vcpu->arch.db[dr] = val;
1003 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1004 vcpu->arch.eff_db[dr] = val;
1005 break;
1006 case 4:
020df079
GN		 1007 /* fall through */
1008 case 6:
338dbc97
GN		 1009 if (val & 0xffffffff00000000ULL)
1010 return -1; /* #GP */
6f43ed01 1011 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1012 kvm_update_dr6(vcpu);
020df079
GN		 1013 break;
1014 case 5:
020df079
GN		 1015 /* fall through */
1016 default: /* 7 */
338dbc97
GN		 1017 if (val & 0xffffffff00000000ULL)
1018 return -1; /* #GP */
020df079 1019 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1020 kvm_update_dr7(vcpu);
020df079
GN		 1021 break;
1022 }
1023
1024 return 0;
1025}
338dbc97
GN		 1026
1027int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1028{
16f8a6f9 1029 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1030 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1031 return 1;
1032 }
1033 return 0;
338dbc97 1034}
020df079
GN		 1035EXPORT_SYMBOL_GPL(kvm_set_dr);
1036
16f8a6f9 1037int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1038{
1039 switch (dr) {
1040 case 0 ... 3:
1041 *val = vcpu->arch.db[dr];
1042 break;
1043 case 4:
020df079
GN		 1044 /* fall through */
1045 case 6:
73aaf249
JK		 1046 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1047 *val = vcpu->arch.dr6;
1048 else
1049 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1050 break;
1051 case 5:
020df079
GN		 1052 /* fall through */
1053 default: /* 7 */
1054 *val = vcpu->arch.dr7;
1055 break;
1056 }
338dbc97
GN		 1057 return 0;
1058}
020df079
GN		 1059EXPORT_SYMBOL_GPL(kvm_get_dr);
1060
022cd0e8
AK		 1061bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1062{
1063 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1064 u64 data;
1065 int err;
1066
c6702c9d 1067 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1068 if (err)
1069 return err;
1070 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1071 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1072 return err;
1073}
1074EXPORT_SYMBOL_GPL(kvm_rdpmc);
1075
043405e1
CO		 1076/*
1077 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1078 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1079 *
1080 * This list is modified at module load time to reflect the
e3267cbb 1081 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1082 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1083 * may depend on host virtualization features rather than host cpu features.
043405e1 1084 */
e3267cbb 1085
043405e1
CO		 1086static u32 msrs_to_save[] = {
1087 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1088 MSR_STAR,
043405e1
CO		 1089#ifdef CONFIG_X86_64
1090 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1091#endif
b3897a49 1092 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1093 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1094 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1095};
1096
1097static unsigned num_msrs_to_save;
1098
62ef68bb
PB		 1099static u32 emulated_msrs[] = {
1100 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1101 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1102 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1103 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1104 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1105 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1106 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1107 HV_X64_MSR_RESET,
11c4b1ca 1108 HV_X64_MSR_VP_INDEX,
9eec50b8 1109 HV_X64_MSR_VP_RUNTIME,
5c919412 1110 HV_X64_MSR_SCONTROL,
1f4b34f8 1111 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1112 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1113 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1114 HV_X64_MSR_TSC_EMULATION_STATUS,
1115
1116 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1117 MSR_KVM_PV_EOI_EN,
1118
ba904635 1119 MSR_IA32_TSC_ADJUST,
a3e06bbe 1120 MSR_IA32_TSCDEADLINE,
043405e1 1121 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1122 MSR_IA32_MCG_STATUS,
1123 MSR_IA32_MCG_CTL,
c45dcc71 1124 MSR_IA32_MCG_EXT_CTL,
64d60670 1125 MSR_IA32_SMBASE,
52797bf9 1126 MSR_SMI_COUNT,
db2336a8
KH		 1127 MSR_PLATFORM_INFO,
1128 MSR_MISC_FEATURES_ENABLES,
bc226f07 1129 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1130};
1131
62ef68bb
PB		 1132static unsigned num_emulated_msrs;
1133
801e459a
TL		 1134/*
1135 * List of msr numbers which are used to expose MSR-based features that
1136 * can be used by a hypervisor to validate requested CPU features.
1137 */
1138static u32 msr_based_features[] = {
1389309c
PB		 1139 MSR_IA32_VMX_BASIC,
1140 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1141 MSR_IA32_VMX_PINBASED_CTLS,
1142 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1143 MSR_IA32_VMX_PROCBASED_CTLS,
1144 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1145 MSR_IA32_VMX_EXIT_CTLS,
1146 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1147 MSR_IA32_VMX_ENTRY_CTLS,
1148 MSR_IA32_VMX_MISC,
1149 MSR_IA32_VMX_CR0_FIXED0,
1150 MSR_IA32_VMX_CR0_FIXED1,
1151 MSR_IA32_VMX_CR4_FIXED0,
1152 MSR_IA32_VMX_CR4_FIXED1,
1153 MSR_IA32_VMX_VMCS_ENUM,
1154 MSR_IA32_VMX_PROCBASED_CTLS2,
1155 MSR_IA32_VMX_EPT_VPID_CAP,
1156 MSR_IA32_VMX_VMFUNC,
1157
d1d93fa9 1158 MSR_F10H_DECFG,
518e7b94 1159 MSR_IA32_UCODE_REV,
cd283252 1160 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1161};
1162
1163static unsigned int num_msr_based_features;
1164
5b76a3cf
PB		 1165u64 kvm_get_arch_capabilities(void)
1166{
1167 u64 data;
1168
1169 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1170
1171 /*
1172 * If we're doing cache flushes (either "always" or "cond")
1173 * we will do one whenever the guest does a vmlaunch/vmresume.
1174 * If an outer hypervisor is doing the cache flush for us
1175 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1176 * capability to the guest too, and if EPT is disabled we're not
1177 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1178 * require a nested hypervisor to do a flush of its own.
1179 */
1180 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1181 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1182
1183 return data;
1184}
1185EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1186
66421c1e
WL		 1187static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1188{
1189 switch (msr->index) {
cd283252 1190 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1191 msr->data = kvm_get_arch_capabilities();
1192 break;
1193 case MSR_IA32_UCODE_REV:
cd283252 1194 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1195 break;
66421c1e
WL		 1196 default:
1197 if (kvm_x86_ops->get_msr_feature(msr))
1198 return 1;
1199 }
1200 return 0;
1201}
1202
801e459a
TL		 1203static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1204{
1205 struct kvm_msr_entry msr;
66421c1e 1206 int r;
801e459a
TL		 1207
1208 msr.index = index;
66421c1e
WL		 1209 r = kvm_get_msr_feature(&msr);
1210 if (r)
1211 return r;
801e459a
TL		 1212
1213 *data = msr.data;
1214
1215 return 0;
1216}
1217
384bb783 1218bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1219{
b69e8cae 1220 if (efer & efer_reserved_bits)
384bb783 1221 return false;
15c4a640 1222
1b4d56b8 1223 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1224 return false;
1b2fd70c 1225
1b4d56b8 1226 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1227 return false;
d8017474 1228
384bb783
JK		 1229 return true;
1230}
1231EXPORT_SYMBOL_GPL(kvm_valid_efer);
1232
1233static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1234{
1235 u64 old_efer = vcpu->arch.efer;
1236
1237 if (!kvm_valid_efer(vcpu, efer))
1238 return 1;
1239
1240 if (is_paging(vcpu)
1241 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1242 return 1;
1243
15c4a640 1244 efer &= ~EFER_LMA;
f6801dff 1245 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1246
a3d204e2
SY		 1247 kvm_x86_ops->set_efer(vcpu, efer);
1248
aad82703
SY		 1249 /* Update reserved bits */
1250 if ((efer ^ old_efer) & EFER_NX)
1251 kvm_mmu_reset_context(vcpu);
1252
b69e8cae 1253 return 0;
15c4a640
CO		 1254}
1255
f2b4b7dd
JR		 1256void kvm_enable_efer_bits(u64 mask)
1257{
1258 efer_reserved_bits &= ~mask;
1259}
1260EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1261
15c4a640
CO		 1262/*
1263 * Writes msr value into into the appropriate "register".
1264 * Returns 0 on success, non-0 otherwise.
1265 * Assumes vcpu_load() was already called.
1266 */
8fe8ab46 1267int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1268{
854e8bb1
NA		 1269 switch (msr->index) {
1270 case MSR_FS_BASE:
1271 case MSR_GS_BASE:
1272 case MSR_KERNEL_GS_BASE:
1273 case MSR_CSTAR:
1274 case MSR_LSTAR:
fd8cb433 1275 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1276 return 1;
1277 break;
1278 case MSR_IA32_SYSENTER_EIP:
1279 case MSR_IA32_SYSENTER_ESP:
1280 /*
1281 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1282 * non-canonical address is written on Intel but not on
1283 * AMD (which ignores the top 32-bits, because it does
1284 * not implement 64-bit SYSENTER).
1285 *
1286 * 64-bit code should hence be able to write a non-canonical
1287 * value on AMD. Making the address canonical ensures that
1288 * vmentry does not fail on Intel after writing a non-canonical
1289 * value, and that something deterministic happens if the guest
1290 * invokes 64-bit SYSENTER.
1291 */
fd8cb433 1292 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1293 }
8fe8ab46 1294 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1295}
854e8bb1 1296EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1297
313a3dc7
CO		 1298/*
1299 * Adapt set_msr() to msr_io()'s calling convention
1300 */
609e36d3
PB		 1301static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1302{
1303 struct msr_data msr;
1304 int r;
1305
1306 msr.index = index;
1307 msr.host_initiated = true;
1308 r = kvm_get_msr(vcpu, &msr);
1309 if (r)
1310 return r;
1311
1312 *data = msr.data;
1313 return 0;
1314}
1315
313a3dc7
CO		 1316static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1317{
8fe8ab46
WA		 1318 struct msr_data msr;
1319
1320 msr.data = *data;
1321 msr.index = index;
1322 msr.host_initiated = true;
1323 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1324}
1325
16e8d74d
MT		 1326#ifdef CONFIG_X86_64
1327struct pvclock_gtod_data {
1328 seqcount_t seq;
1329
1330 struct { /* extract of a clocksource struct */
1331 int vclock_mode;
a5a1d1c2
TG		 1332 u64 cycle_last;
1333 u64 mask;
16e8d74d
MT		 1334 u32 mult;
1335 u32 shift;
1336 } clock;
1337
cbcf2dd3
TG		 1338 u64 boot_ns;
1339 u64 nsec_base;
55dd00a7 1340 u64 wall_time_sec;
16e8d74d
MT		 1341};
1342
1343static struct pvclock_gtod_data pvclock_gtod_data;
1344
1345static void update_pvclock_gtod(struct timekeeper *tk)
1346{
1347 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1348 u64 boot_ns;
1349
876e7881 1350 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1351
1352 write_seqcount_begin(&vdata->seq);
1353
1354 /* copy pvclock gtod data */
876e7881
PZ		 1355 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1356 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1357 vdata->clock.mask = tk->tkr_mono.mask;
1358 vdata->clock.mult = tk->tkr_mono.mult;
1359 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1360
cbcf2dd3 1361 vdata->boot_ns = boot_ns;
876e7881 1362 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1363
55dd00a7
MT		 1364 vdata->wall_time_sec = tk->xtime_sec;
1365
16e8d74d
MT		 1366 write_seqcount_end(&vdata->seq);
1367}
1368#endif
1369
bab5bb39
NK		 1370void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1371{
1372 /*
1373 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1374 * vcpu_enter_guest. This function is only called from
1375 * the physical CPU that is running vcpu.
1376 */
1377 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1378}
16e8d74d 1379
18068523
GOC		 1380static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1381{
9ed3c444
AK		 1382 int version;
1383 int r;
50d0a0f9 1384 struct pvclock_wall_clock wc;
87aeb54f 1385 struct timespec64 boot;
18068523
GOC		 1386
1387 if (!wall_clock)
1388 return;
1389
9ed3c444
AK		 1390 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1391 if (r)
1392 return;
1393
1394 if (version & 1)
1395 ++version; /* first time write, random junk */
1396
1397 ++version;
18068523 1398
1dab1345
NK		 1399 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1400 return;
18068523 1401
50d0a0f9
GH		 1402 /*
1403 * The guest calculates current wall clock time by adding
34c238a1 1404 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1405 * wall clock specified here. guest system time equals host
1406 * system time for us, thus we must fill in host boot time here.
1407 */
87aeb54f 1408 getboottime64(&boot);
50d0a0f9 1409
4b648665 1410 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1411 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1412 boot = timespec64_sub(boot, ts);
4b648665 1413 }
87aeb54f 1414 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1415 wc.nsec = boot.tv_nsec;
1416 wc.version = version;
18068523
GOC		 1417
1418 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1419
1420 version++;
1421 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1422}
1423
50d0a0f9
GH		 1424static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1425{
b51012de
PB		 1426 do_shl32_div32(dividend, divisor);
1427 return dividend;
50d0a0f9
GH		 1428}
1429
3ae13faa 1430static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1431 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1432{
5f4e3f88 1433 uint64_t scaled64;
50d0a0f9
GH		 1434 int32_t shift = 0;
1435 uint64_t tps64;
1436 uint32_t tps32;
1437
3ae13faa
PB		 1438 tps64 = base_hz;
1439 scaled64 = scaled_hz;
50933623 1440 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1441 tps64 >>= 1;
1442 shift--;
1443 }
1444
1445 tps32 = (uint32_t)tps64;
50933623
JK		 1446 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1447 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1448 scaled64 >>= 1;
1449 else
1450 tps32 <<= 1;
50d0a0f9
GH		 1451 shift++;
1452 }
1453
5f4e3f88
ZA		 1454 *pshift = shift;
1455 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1456
3ae13faa
PB		 1457 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1458 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1459}
1460
d828199e 1461#ifdef CONFIG_X86_64
16e8d74d 1462static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1463#endif
16e8d74d 1464
c8076604 1465static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1466static unsigned long max_tsc_khz;
c8076604 1467
cc578287 1468static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1469{
cc578287
ZA		 1470 u64 v = (u64)khz * (1000000 + ppm);
1471 do_div(v, 1000000);
1472 return v;
1e993611
JR		 1473}
1474
381d585c
HZ		 1475static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1476{
1477 u64 ratio;
1478
1479 /* Guest TSC same frequency as host TSC? */
1480 if (!scale) {
1481 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1482 return 0;
1483 }
1484
1485 /* TSC scaling supported? */
1486 if (!kvm_has_tsc_control) {
1487 if (user_tsc_khz > tsc_khz) {
1488 vcpu->arch.tsc_catchup = 1;
1489 vcpu->arch.tsc_always_catchup = 1;
1490 return 0;
1491 } else {
1492 WARN(1, "user requested TSC rate below hardware speed\n");
1493 return -1;
1494 }
1495 }
1496
1497 /* TSC scaling required - calculate ratio */
1498 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1499 user_tsc_khz, tsc_khz);
1500
1501 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1502 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1503 user_tsc_khz);
1504 return -1;
1505 }
1506
1507 vcpu->arch.tsc_scaling_ratio = ratio;
1508 return 0;
1509}
1510
4941b8cb 1511static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1512{
cc578287
ZA		 1513 u32 thresh_lo, thresh_hi;
1514 int use_scaling = 0;
217fc9cf 1515
03ba32ca 1516 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1517 if (user_tsc_khz == 0) {
ad721883
HZ		 1518 /* set tsc_scaling_ratio to a safe value */
1519 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1520 return -1;
ad721883 1521 }
03ba32ca 1522
c285545f 1523 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1524 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1525 &vcpu->arch.virtual_tsc_shift,
1526 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1527 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1528
1529 /*
1530 * Compute the variation in TSC rate which is acceptable
1531 * within the range of tolerance and decide if the
1532 * rate being applied is within that bounds of the hardware
1533 * rate. If so, no scaling or compensation need be done.
1534 */
1535 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1536 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1537 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1538 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1539 use_scaling = 1;
1540 }
4941b8cb 1541 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1542}
1543
1544static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1545{
e26101b1 1546 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1547 vcpu->arch.virtual_tsc_mult,
1548 vcpu->arch.virtual_tsc_shift);
e26101b1 1549 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1550 return tsc;
1551}
1552
b0c39dc6
VK		 1553static inline int gtod_is_based_on_tsc(int mode)
1554{
1555 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1556}
1557
69b0049a 1558static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1559{
1560#ifdef CONFIG_X86_64
1561 bool vcpus_matched;
b48aa97e
MT		 1562 struct kvm_arch *ka = &vcpu->kvm->arch;
1563 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1564
1565 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1566 atomic_read(&vcpu->kvm->online_vcpus));
1567
7f187922
MT		 1568 /*
1569 * Once the masterclock is enabled, always perform request in
1570 * order to update it.
1571 *
1572 * In order to enable masterclock, the host clocksource must be TSC
1573 * and the vcpus need to have matched TSCs. When that happens,
1574 * perform request to enable masterclock.
1575 */
1576 if (ka->use_master_clock ||
b0c39dc6 1577 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1578 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1579
1580 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1581 atomic_read(&vcpu->kvm->online_vcpus),
1582 ka->use_master_clock, gtod->clock.vclock_mode);
1583#endif
1584}
1585
ba904635
WA		 1586static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1587{
e79f245d 1588 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1589 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1590}
1591
35181e86
HZ		 1592/*
1593 * Multiply tsc by a fixed point number represented by ratio.
1594 *
1595 * The most significant 64-N bits (mult) of ratio represent the
1596 * integral part of the fixed point number; the remaining N bits
1597 * (frac) represent the fractional part, ie. ratio represents a fixed
1598 * point number (mult + frac * 2^(-N)).
1599 *
1600 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1601 */
1602static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1603{
1604 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1605}
1606
1607u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1608{
1609 u64 _tsc = tsc;
1610 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1611
1612 if (ratio != kvm_default_tsc_scaling_ratio)
1613 _tsc = __scale_tsc(ratio, tsc);
1614
1615 return _tsc;
1616}
1617EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1618
07c1419a
HZ		 1619static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1620{
1621 u64 tsc;
1622
1623 tsc = kvm_scale_tsc(vcpu, rdtsc());
1624
1625 return target_tsc - tsc;
1626}
1627
4ba76538
HZ		 1628u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1629{
e79f245d
KA		 1630 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1631
1632 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1633}
1634EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1635
a545ab6a
LC		 1636static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1637{
1638 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1639 vcpu->arch.tsc_offset = offset;
1640}
1641
b0c39dc6
VK		 1642static inline bool kvm_check_tsc_unstable(void)
1643{
1644#ifdef CONFIG_X86_64
1645 /*
1646 * TSC is marked unstable when we're running on Hyper-V,
1647 * 'TSC page' clocksource is good.
1648 */
1649 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1650 return false;
1651#endif
1652 return check_tsc_unstable();
1653}
1654
8fe8ab46 1655void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1656{
1657 struct kvm *kvm = vcpu->kvm;
f38e098f 1658 u64 offset, ns, elapsed;
99e3e30a 1659 unsigned long flags;
b48aa97e 1660 bool matched;
0d3da0d2 1661 bool already_matched;
8fe8ab46 1662 u64 data = msr->data;
c5e8ec8e 1663 bool synchronizing = false;
99e3e30a 1664
038f8c11 1665 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1666 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1667 ns = ktime_get_boot_ns();
f38e098f 1668 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1669
03ba32ca 1670 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1671 if (data == 0 && msr->host_initiated) {
1672 /*
1673 * detection of vcpu initialization -- need to sync
1674 * with other vCPUs. This particularly helps to keep
1675 * kvm_clock stable after CPU hotplug
1676 */
1677 synchronizing = true;
1678 } else {
1679 u64 tsc_exp = kvm->arch.last_tsc_write +
1680 nsec_to_cycles(vcpu, elapsed);
1681 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1682 /*
1683 * Special case: TSC write with a small delta (1 second)
1684 * of virtual cycle time against real time is
1685 * interpreted as an attempt to synchronize the CPU.
1686 */
1687 synchronizing = data < tsc_exp + tsc_hz &&
1688 data + tsc_hz > tsc_exp;
1689 }
c5e8ec8e 1690 }
f38e098f
ZA		 1691
1692 /*
5d3cb0f6
ZA		 1693 * For a reliable TSC, we can match TSC offsets, and for an unstable
1694 * TSC, we add elapsed time in this computation. We could let the
1695 * compensation code attempt to catch up if we fall behind, but
1696 * it's better to try to match offsets from the beginning.
1697 */
c5e8ec8e 1698 if (synchronizing &&
5d3cb0f6 1699 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1700 if (!kvm_check_tsc_unstable()) {
e26101b1 1701 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1702 pr_debug("kvm: matched tsc offset for %llu\n", data);
1703 } else {
857e4099 1704 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1705 data += delta;
07c1419a 1706 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1707 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1708 }
b48aa97e 1709 matched = true;
0d3da0d2 1710 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1711 } else {
1712 /*
1713 * We split periods of matched TSC writes into generations.
1714 * For each generation, we track the original measured
1715 * nanosecond time, offset, and write, so if TSCs are in
1716 * sync, we can match exact offset, and if not, we can match
4a969980 1717 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1718 *
1719 * These values are tracked in kvm->arch.cur_xxx variables.
1720 */
1721 kvm->arch.cur_tsc_generation++;
1722 kvm->arch.cur_tsc_nsec = ns;
1723 kvm->arch.cur_tsc_write = data;
1724 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1725 matched = false;
0d3da0d2 1726 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1727 kvm->arch.cur_tsc_generation, data);
f38e098f 1728 }
e26101b1
ZA		 1729
1730 /*
1731 * We also track th most recent recorded KHZ, write and time to
1732 * allow the matching interval to be extended at each write.
1733 */
f38e098f
ZA		 1734 kvm->arch.last_tsc_nsec = ns;
1735 kvm->arch.last_tsc_write = data;
5d3cb0f6 1736 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1737
b183aa58 1738 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1739
1740 /* Keep track of which generation this VCPU has synchronized to */
1741 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1742 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1743 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1744
d6321d49 1745 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1746 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1747
a545ab6a 1748 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1749 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1750
1751 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1752 if (!matched) {
b48aa97e 1753 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1754 } else if (!already_matched) {
1755 kvm->arch.nr_vcpus_matched_tsc++;
1756 }
b48aa97e
MT		 1757
1758 kvm_track_tsc_matching(vcpu);
1759 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1760}
e26101b1 1761
99e3e30a
ZA		 1762EXPORT_SYMBOL_GPL(kvm_write_tsc);
1763
58ea6767
HZ		 1764static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1765 s64 adjustment)
1766{
ea26e4ec 1767 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1768}
1769
1770static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1771{
1772 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1773 WARN_ON(adjustment < 0);
1774 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1775 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1776}
1777
d828199e
MT		 1778#ifdef CONFIG_X86_64
1779
a5a1d1c2 1780static u64 read_tsc(void)
d828199e 1781{
a5a1d1c2 1782 u64 ret = (u64)rdtsc_ordered();
03b9730b 1783 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1784
1785 if (likely(ret >= last))
1786 return ret;
1787
1788 /*
1789 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1790 * predictable (it's just a function of time and the likely is
d828199e
MT		 1791 * very likely) and there's a data dependence, so force GCC
1792 * to generate a branch instead. I don't barrier() because
1793 * we don't actually need a barrier, and if this function
1794 * ever gets inlined it will generate worse code.
1795 */
1796 asm volatile ("");
1797 return last;
1798}
1799
b0c39dc6 1800static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1801{
1802 long v;
1803 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1804 u64 tsc_pg_val;
1805
1806 switch (gtod->clock.vclock_mode) {
1807 case VCLOCK_HVCLOCK:
1808 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1809 tsc_timestamp);
1810 if (tsc_pg_val != U64_MAX) {
1811 /* TSC page valid */
1812 *mode = VCLOCK_HVCLOCK;
1813 v = (tsc_pg_val - gtod->clock.cycle_last) &
1814 gtod->clock.mask;
1815 } else {
1816 /* TSC page invalid */
1817 *mode = VCLOCK_NONE;
1818 }
1819 break;
1820 case VCLOCK_TSC:
1821 *mode = VCLOCK_TSC;
1822 *tsc_timestamp = read_tsc();
1823 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1824 gtod->clock.mask;
1825 break;
1826 default:
1827 *mode = VCLOCK_NONE;
1828 }
d828199e 1829
b0c39dc6
VK		 1830 if (*mode == VCLOCK_NONE)
1831 *tsc_timestamp = v = 0;
d828199e 1832
d828199e
MT		 1833 return v * gtod->clock.mult;
1834}
1835
b0c39dc6 1836static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1837{
cbcf2dd3 1838 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1839 unsigned long seq;
d828199e 1840 int mode;
cbcf2dd3 1841 u64 ns;
d828199e 1842
d828199e
MT		 1843 do {
1844 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1845 ns = gtod->nsec_base;
b0c39dc6 1846 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1847 ns >>= gtod->clock.shift;
cbcf2dd3 1848 ns += gtod->boot_ns;
d828199e 1849 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1850 *t = ns;
d828199e
MT		 1851
1852 return mode;
1853}
1854
899a31f5 1855static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1856{
1857 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1858 unsigned long seq;
1859 int mode;
1860 u64 ns;
1861
1862 do {
1863 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1864 ts->tv_sec = gtod->wall_time_sec;
1865 ns = gtod->nsec_base;
b0c39dc6 1866 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1867 ns >>= gtod->clock.shift;
1868 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1869
1870 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1871 ts->tv_nsec = ns;
1872
1873 return mode;
1874}
1875
b0c39dc6
VK		 1876/* returns true if host is using TSC based clocksource */
1877static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1878{
d828199e 1879 /* checked again under seqlock below */
b0c39dc6 1880 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1881 return false;
1882
b0c39dc6
VK		 1883 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1884 tsc_timestamp));
d828199e 1885}
55dd00a7 1886
b0c39dc6 1887/* returns true if host is using TSC based clocksource */
899a31f5 1888static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1889 u64 *tsc_timestamp)
55dd00a7
MT		 1890{
1891 /* checked again under seqlock below */
b0c39dc6 1892 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1893 return false;
1894
b0c39dc6 1895 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1896}
d828199e
MT		 1897#endif
1898
1899/*
1900 *
b48aa97e
MT		 1901 * Assuming a stable TSC across physical CPUS, and a stable TSC
1902 * across virtual CPUs, the following condition is possible.
1903 * Each numbered line represents an event visible to both
d828199e
MT		 1904 * CPUs at the next numbered event.
1905 *
1906 * "timespecX" represents host monotonic time. "tscX" represents
1907 * RDTSC value.
1908 *
1909 * VCPU0 on CPU0 | VCPU1 on CPU1
1910 *
1911 * 1. read timespec0,tsc0
1912 * 2. | timespec1 = timespec0 + N
1913 * | tsc1 = tsc0 + M
1914 * 3. transition to guest | transition to guest
1915 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1916 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1917 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1918 *
1919 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1920 *
1921 * - ret0 < ret1
1922 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1923 * ...
1924 * - 0 < N - M => M < N
1925 *
1926 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1927 * always the case (the difference between two distinct xtime instances
1928 * might be smaller then the difference between corresponding TSC reads,
1929 * when updating guest vcpus pvclock areas).
1930 *
1931 * To avoid that problem, do not allow visibility of distinct
1932 * system_timestamp/tsc_timestamp values simultaneously: use a master
1933 * copy of host monotonic time values. Update that master copy
1934 * in lockstep.
1935 *
b48aa97e 1936 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1937 *
1938 */
1939
1940static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1941{
1942#ifdef CONFIG_X86_64
1943 struct kvm_arch *ka = &kvm->arch;
1944 int vclock_mode;
b48aa97e
MT		 1945 bool host_tsc_clocksource, vcpus_matched;
1946
1947 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1948 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1949
1950 /*
1951 * If the host uses TSC clock, then passthrough TSC as stable
1952 * to the guest.
1953 */
b48aa97e 1954 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1955 &ka->master_kernel_ns,
1956 &ka->master_cycle_now);
1957
16a96021 1958 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1959 && !ka->backwards_tsc_observed
54750f2c 1960 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1961
d828199e
MT		 1962 if (ka->use_master_clock)
1963 atomic_set(&kvm_guest_has_master_clock, 1);
1964
1965 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1966 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1967 vcpus_matched);
d828199e
MT		 1968#endif
1969}
1970
2860c4b1
PB		 1971void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1972{
1973 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1974}
1975
2e762ff7
MT		 1976static void kvm_gen_update_masterclock(struct kvm *kvm)
1977{
1978#ifdef CONFIG_X86_64
1979 int i;
1980 struct kvm_vcpu *vcpu;
1981 struct kvm_arch *ka = &kvm->arch;
1982
1983 spin_lock(&ka->pvclock_gtod_sync_lock);
1984 kvm_make_mclock_inprogress_request(kvm);
1985 /* no guest entries from this point */
1986 pvclock_update_vm_gtod_copy(kvm);
1987
1988 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1989 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1990
1991 /* guest entries allowed */
1992 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1993 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1994
1995 spin_unlock(&ka->pvclock_gtod_sync_lock);
1996#endif
1997}
1998
e891a32e 1999u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2000{
108b249c 2001 struct kvm_arch *ka = &kvm->arch;
8b953440 2002 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2003 u64 ret;
108b249c 2004
8b953440
PB		 2005 spin_lock(&ka->pvclock_gtod_sync_lock);
2006 if (!ka->use_master_clock) {
2007 spin_unlock(&ka->pvclock_gtod_sync_lock);
2008 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 2009 }
2010
8b953440
PB		 2011 hv_clock.tsc_timestamp = ka->master_cycle_now;
2012 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2013 spin_unlock(&ka->pvclock_gtod_sync_lock);
2014
e2c2206a
WL		 2015 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2016 get_cpu();
2017
e70b57a6
WL		 2018 if (__this_cpu_read(cpu_tsc_khz)) {
2019 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2020 &hv_clock.tsc_shift,
2021 &hv_clock.tsc_to_system_mul);
2022 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2023 } else
2024 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2025
2026 put_cpu();
2027
2028 return ret;
108b249c
PB		 2029}
2030
0d6dd2ff
PB		 2031static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2032{
2033 struct kvm_vcpu_arch *vcpu = &v->arch;
2034 struct pvclock_vcpu_time_info guest_hv_clock;
2035
4e335d9e 2036 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2037 &guest_hv_clock, sizeof(guest_hv_clock))))
2038 return;
2039
2040 /* This VCPU is paused, but it's legal for a guest to read another
2041 * VCPU's kvmclock, so we really have to follow the specification where
2042 * it says that version is odd if data is being modified, and even after
2043 * it is consistent.
2044 *
2045 * Version field updates must be kept separate. This is because
2046 * kvm_write_guest_cached might use a "rep movs" instruction, and
2047 * writes within a string instruction are weakly ordered. So there
2048 * are three writes overall.
2049 *
2050 * As a small optimization, only write the version field in the first
2051 * and third write. The vcpu->pv_time cache is still valid, because the
2052 * version field is the first in the struct.
2053 */
2054 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2055
51c4b8bb
LA		 2056 if (guest_hv_clock.version & 1)
2057 ++guest_hv_clock.version; /* first time write, random junk */
2058
0d6dd2ff 2059 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2060 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2061 &vcpu->hv_clock,
2062 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2063
2064 smp_wmb();
2065
2066 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2067 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2068
2069 if (vcpu->pvclock_set_guest_stopped_request) {
2070 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2071 vcpu->pvclock_set_guest_stopped_request = false;
2072 }
2073
2074 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2075
4e335d9e
PB		 2076 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2077 &vcpu->hv_clock,
2078 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2079
2080 smp_wmb();
2081
2082 vcpu->hv_clock.version++;
4e335d9e
PB		 2083 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2084 &vcpu->hv_clock,
2085 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2086}
2087
34c238a1 2088static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2089{
78db6a50 2090 unsigned long flags, tgt_tsc_khz;
18068523 2091 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2092 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2093 s64 kernel_ns;
d828199e 2094 u64 tsc_timestamp, host_tsc;
51d59c6b 2095 u8 pvclock_flags;
d828199e
MT		 2096 bool use_master_clock;
2097
2098 kernel_ns = 0;
2099 host_tsc = 0;
18068523 2100
d828199e
MT		 2101 /*
2102 * If the host uses TSC clock, then passthrough TSC as stable
2103 * to the guest.
2104 */
2105 spin_lock(&ka->pvclock_gtod_sync_lock);
2106 use_master_clock = ka->use_master_clock;
2107 if (use_master_clock) {
2108 host_tsc = ka->master_cycle_now;
2109 kernel_ns = ka->master_kernel_ns;
2110 }
2111 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2112
2113 /* Keep irq disabled to prevent changes to the clock */
2114 local_irq_save(flags);
78db6a50
PB		 2115 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2116 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2117 local_irq_restore(flags);
2118 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2119 return 1;
2120 }
d828199e 2121 if (!use_master_clock) {
4ea1636b 2122 host_tsc = rdtsc();
108b249c 2123 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2124 }
2125
4ba76538 2126 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2127
c285545f
ZA		 2128 /*
2129 * We may have to catch up the TSC to match elapsed wall clock
2130 * time for two reasons, even if kvmclock is used.
2131 * 1) CPU could have been running below the maximum TSC rate
2132 * 2) Broken TSC compensation resets the base at each VCPU
2133 * entry to avoid unknown leaps of TSC even when running
2134 * again on the same CPU. This may cause apparent elapsed
2135 * time to disappear, and the guest to stand still or run
2136 * very slowly.
2137 */
2138 if (vcpu->tsc_catchup) {
2139 u64 tsc = compute_guest_tsc(v, kernel_ns);
2140 if (tsc > tsc_timestamp) {
f1e2b260 2141 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2142 tsc_timestamp = tsc;
2143 }
50d0a0f9
GH		 2144 }
2145
18068523
GOC		 2146 local_irq_restore(flags);
2147
0d6dd2ff 2148 /* With all the info we got, fill in the values */
18068523 2149
78db6a50
PB		 2150 if (kvm_has_tsc_control)
2151 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2152
2153 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2154 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2155 &vcpu->hv_clock.tsc_shift,
2156 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2157 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2158 }
2159
1d5f066e 2160 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2161 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2162 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2163
d828199e 2164 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2165 pvclock_flags = 0;
d828199e
MT		 2166 if (use_master_clock)
2167 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2168
78c0337a
MT		 2169 vcpu->hv_clock.flags = pvclock_flags;
2170
095cf55d
PB		 2171 if (vcpu->pv_time_enabled)
2172 kvm_setup_pvclock_page(v);
2173 if (v == kvm_get_vcpu(v->kvm, 0))
2174 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2175 return 0;
c8076604
GH		 2176}
2177
0061d53d
MT		 2178/*
2179 * kvmclock updates which are isolated to a given vcpu, such as
2180 * vcpu->cpu migration, should not allow system_timestamp from
2181 * the rest of the vcpus to remain static. Otherwise ntp frequency
2182 * correction applies to one vcpu's system_timestamp but not
2183 * the others.
2184 *
2185 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2186 * We need to rate-limit these requests though, as they can
2187 * considerably slow guests that have a large number of vcpus.
2188 * The time for a remote vcpu to update its kvmclock is bound
2189 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2190 */
2191
7e44e449
AJ		 2192#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2193
2194static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2195{
2196 int i;
7e44e449
AJ		 2197 struct delayed_work *dwork = to_delayed_work(work);
2198 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2199 kvmclock_update_work);
2200 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2201 struct kvm_vcpu *vcpu;
2202
2203 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2204 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2205 kvm_vcpu_kick(vcpu);
2206 }
2207}
2208
7e44e449
AJ		 2209static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2210{
2211 struct kvm *kvm = v->kvm;
2212
105b21bb 2213 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2214 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2215 KVMCLOCK_UPDATE_DELAY);
2216}
2217
332967a3
AJ		 2218#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2219
2220static void kvmclock_sync_fn(struct work_struct *work)
2221{
2222 struct delayed_work *dwork = to_delayed_work(work);
2223 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2224 kvmclock_sync_work);
2225 struct kvm *kvm = container_of(ka, struct kvm, arch);
2226
630994b3
MT		 2227 if (!kvmclock_periodic_sync)
2228 return;
2229
332967a3
AJ		 2230 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2231 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2232 KVMCLOCK_SYNC_PERIOD);
2233}
2234
9ffd986c 2235static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2236{
890ca9ae
HY		 2237 u64 mcg_cap = vcpu->arch.mcg_cap;
2238 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2239 u32 msr = msr_info->index;
2240 u64 data = msr_info->data;
890ca9ae 2241
15c4a640 2242 switch (msr) {
15c4a640 2243 case MSR_IA32_MCG_STATUS:
890ca9ae 2244 vcpu->arch.mcg_status = data;
15c4a640 2245 break;
c7ac679c 2246 case MSR_IA32_MCG_CTL:
44883f01
PB		 2247 if (!(mcg_cap & MCG_CTL_P) &&
2248 (data || !msr_info->host_initiated))
890ca9ae
HY		 2249 return 1;
2250 if (data != 0 && data != ~(u64)0)
44883f01 2251 return 1;
890ca9ae
HY		 2252 vcpu->arch.mcg_ctl = data;
2253 break;
2254 default:
2255 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2256 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2257 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2258 /* only 0 or all 1s can be written to IA32_MCi_CTL
2259 * some Linux kernels though clear bit 10 in bank 4 to
2260 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2261 * this to avoid an uncatched #GP in the guest
2262 */
890ca9ae 2263 if ((offset & 0x3) == 0 &&
114be429 2264 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2265 return -1;
9ffd986c
WL		 2266 if (!msr_info->host_initiated &&
2267 (offset & 0x3) == 1 && data != 0)
2268 return -1;
890ca9ae
HY		 2269 vcpu->arch.mce_banks[offset] = data;
2270 break;
2271 }
2272 return 1;
2273 }
2274 return 0;
2275}
2276
ffde22ac
ES		 2277static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2278{
2279 struct kvm *kvm = vcpu->kvm;
2280 int lm = is_long_mode(vcpu);
2281 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2282 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2283 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2284 : kvm->arch.xen_hvm_config.blob_size_32;
2285 u32 page_num = data & ~PAGE_MASK;
2286 u64 page_addr = data & PAGE_MASK;
2287 u8 *page;
2288 int r;
2289
2290 r = -E2BIG;
2291 if (page_num >= blob_size)
2292 goto out;
2293 r = -ENOMEM;
ff5c2c03
SL		 2294 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2295 if (IS_ERR(page)) {
2296 r = PTR_ERR(page);
ffde22ac 2297 goto out;
ff5c2c03 2298 }
54bf36aa 2299 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2300 goto out_free;
2301 r = 0;
2302out_free:
2303 kfree(page);
2304out:
2305 return r;
2306}
2307
344d9588
GN		 2308static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2309{
2310 gpa_t gpa = data & ~0x3f;
2311
52a5c155
WL		 2312 /* Bits 3:5 are reserved, Should be zero */
2313 if (data & 0x38)
344d9588
GN		 2314 return 1;
2315
2316 vcpu->arch.apf.msr_val = data;
2317
2318 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2319 kvm_clear_async_pf_completion_queue(vcpu);
2320 kvm_async_pf_hash_reset(vcpu);
2321 return 0;
2322 }
2323
4e335d9e 2324 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2325 sizeof(u32)))
344d9588
GN		 2326 return 1;
2327
6adba527 2328 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2329 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2330 kvm_async_pf_wakeup_all(vcpu);
2331 return 0;
2332}
2333
12f9a48f
GC		 2334static void kvmclock_reset(struct kvm_vcpu *vcpu)
2335{
0b79459b 2336 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2337}
2338
f38a7b75
WL		 2339static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2340{
2341 ++vcpu->stat.tlb_flush;
2342 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2343}
2344
c9aaa895
GC		 2345static void record_steal_time(struct kvm_vcpu *vcpu)
2346{
2347 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2348 return;
2349
4e335d9e 2350 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2351 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2352 return;
2353
f38a7b75
WL		 2354 /*
2355 * Doing a TLB flush here, on the guest's behalf, can avoid
2356 * expensive IPIs.
2357 */
2358 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2359 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2360
35f3fae1
WL		 2361 if (vcpu->arch.st.steal.version & 1)
2362 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2363
2364 vcpu->arch.st.steal.version += 1;
2365
4e335d9e 2366 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2367 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2368
2369 smp_wmb();
2370
c54cdf14
LC		 2371 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2372 vcpu->arch.st.last_steal;
2373 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2374
4e335d9e 2375 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2376 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2377
2378 smp_wmb();
2379
2380 vcpu->arch.st.steal.version += 1;
c9aaa895 2381
4e335d9e 2382 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2383 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2384}
2385
8fe8ab46 2386int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2387{
5753785f 2388 bool pr = false;
8fe8ab46
WA		 2389 u32 msr = msr_info->index;
2390 u64 data = msr_info->data;
5753785f 2391
15c4a640 2392 switch (msr) {
2e32b719 2393 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2394 case MSR_IA32_UCODE_WRITE:
2395 case MSR_VM_HSAVE_PA:
2396 case MSR_AMD64_PATCH_LOADER:
2397 case MSR_AMD64_BU_CFG2:
405a353a 2398 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2399 break;
2400
518e7b94
WL		 2401 case MSR_IA32_UCODE_REV:
2402 if (msr_info->host_initiated)
2403 vcpu->arch.microcode_version = data;
2404 break;
15c4a640 2405 case MSR_EFER:
b69e8cae 2406 return set_efer(vcpu, data);
8f1589d9
AP		 2407 case MSR_K7_HWCR:
2408 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2409 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2410 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2411 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2412 if (data != 0) {
a737f256
CD		 2413 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2414 data);
8f1589d9
AP		 2415 return 1;
2416 }
15c4a640 2417 break;
f7c6d140
AP		 2418 case MSR_FAM10H_MMIO_CONF_BASE:
2419 if (data != 0) {
a737f256
CD		 2420 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2421 "0x%llx\n", data);
f7c6d140
AP		 2422 return 1;
2423 }
15c4a640 2424 break;
b5e2fec0
AG		 2425 case MSR_IA32_DEBUGCTLMSR:
2426 if (!data) {
2427 /* We support the non-activated case already */
2428 break;
2429 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2430 /* Values other than LBR and BTF are vendor-specific,
2431 thus reserved and should throw a #GP */
2432 return 1;
2433 }
a737f256
CD		 2434 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2435 __func__, data);
b5e2fec0 2436 break;
9ba075a6 2437 case 0x200 ... 0x2ff:
ff53604b 2438 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2439 case MSR_IA32_APICBASE:
58cb628d 2440 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2441 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2442 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2443 case MSR_IA32_TSCDEADLINE:
2444 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2445 break;
ba904635 2446 case MSR_IA32_TSC_ADJUST:
d6321d49 2447 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2448 if (!msr_info->host_initiated) {
d913b904 2449 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2450 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2451 }
2452 vcpu->arch.ia32_tsc_adjust_msr = data;
2453 }
2454 break;
15c4a640 2455 case MSR_IA32_MISC_ENABLE:
ad312c7c 2456 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2457 break;
64d60670
PB		 2458 case MSR_IA32_SMBASE:
2459 if (!msr_info->host_initiated)
2460 return 1;
2461 vcpu->arch.smbase = data;
2462 break;
dd259935
PB		 2463 case MSR_IA32_TSC:
2464 kvm_write_tsc(vcpu, msr_info);
2465 break;
52797bf9
LA		 2466 case MSR_SMI_COUNT:
2467 if (!msr_info->host_initiated)
2468 return 1;
2469 vcpu->arch.smi_count = data;
2470 break;
11c6bffa 2471 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2472 case MSR_KVM_WALL_CLOCK:
2473 vcpu->kvm->arch.wall_clock = data;
2474 kvm_write_wall_clock(vcpu->kvm, data);
2475 break;
11c6bffa 2476 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2477 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2478 struct kvm_arch *ka = &vcpu->kvm->arch;
2479
12f9a48f 2480 kvmclock_reset(vcpu);
18068523 2481
54750f2c
MT		 2482 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2483 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2484
2485 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2486 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2487
2488 ka->boot_vcpu_runs_old_kvmclock = tmp;
2489 }
2490
18068523 2491 vcpu->arch.time = data;
0061d53d 2492 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2493
2494 /* we verify if the enable bit is set... */
2495 if (!(data & 1))
2496 break;
2497
4e335d9e 2498 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2499 &vcpu->arch.pv_time, data & ~1ULL,
2500 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2501 vcpu->arch.pv_time_enabled = false;
2502 else
2503 vcpu->arch.pv_time_enabled = true;
32cad84f 2504
18068523
GOC		 2505 break;
2506 }
344d9588
GN		 2507 case MSR_KVM_ASYNC_PF_EN:
2508 if (kvm_pv_enable_async_pf(vcpu, data))
2509 return 1;
2510 break;
c9aaa895
GC		 2511 case MSR_KVM_STEAL_TIME:
2512
2513 if (unlikely(!sched_info_on()))
2514 return 1;
2515
2516 if (data & KVM_STEAL_RESERVED_MASK)
2517 return 1;
2518
4e335d9e 2519 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2520 data & KVM_STEAL_VALID_BITS,
2521 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2522 return 1;
2523
2524 vcpu->arch.st.msr_val = data;
2525
2526 if (!(data & KVM_MSR_ENABLED))
2527 break;
2528
c9aaa895
GC		 2529 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2530
2531 break;
ae7a2a3f 2532 case MSR_KVM_PV_EOI_EN:
72bbf935 2533 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2534 return 1;
2535 break;
c9aaa895 2536
890ca9ae
HY		 2537 case MSR_IA32_MCG_CTL:
2538 case MSR_IA32_MCG_STATUS:
81760dcc 2539 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2540 return set_msr_mce(vcpu, msr_info);
71db6023 2541
6912ac32
WH		 2542 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2543 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2544 pr = true; /* fall through */
2545 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2546 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2547 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2548 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2549
2550 if (pr || data != 0)
a737f256
CD		 2551 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2552 "0x%x data 0x%llx\n", msr, data);
5753785f 2553 break;
84e0cefa
JS		 2554 case MSR_K7_CLK_CTL:
2555 /*
2556 * Ignore all writes to this no longer documented MSR.
2557 * Writes are only relevant for old K7 processors,
2558 * all pre-dating SVM, but a recommended workaround from
4a969980 2559 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2560 * affected processor models on the command line, hence
2561 * the need to ignore the workaround.
2562 */
2563 break;
55cd8e5a 2564 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2565 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2566 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2567 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2568 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2569 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2570 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2571 return kvm_hv_set_msr_common(vcpu, msr, data,
2572 msr_info->host_initiated);
91c9c3ed 2573 case MSR_IA32_BBL_CR_CTL3:
2574 /* Drop writes to this legacy MSR -- see rdmsr
2575 * counterpart for further detail.
2576 */
fab0aa3b
EM		 2577 if (report_ignored_msrs)
2578 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2579 msr, data);
91c9c3ed 2580 break;
2b036c6b 2581 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2582 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2583 return 1;
2584 vcpu->arch.osvw.length = data;
2585 break;
2586 case MSR_AMD64_OSVW_STATUS:
d6321d49 2587 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2588 return 1;
2589 vcpu->arch.osvw.status = data;
2590 break;
db2336a8
KH		 2591 case MSR_PLATFORM_INFO:
2592 if (!msr_info->host_initiated ||
db2336a8
KH		 2593 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2594 cpuid_fault_enabled(vcpu)))
2595 return 1;
2596 vcpu->arch.msr_platform_info = data;
2597 break;
2598 case MSR_MISC_FEATURES_ENABLES:
2599 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2600 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2601 !supports_cpuid_fault(vcpu)))
2602 return 1;
2603 vcpu->arch.msr_misc_features_enables = data;
2604 break;
15c4a640 2605 default:
ffde22ac
ES		 2606 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2607 return xen_hvm_config(vcpu, data);
c6702c9d 2608 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2609 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2610 if (!ignore_msrs) {
ae0f5499 2611 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2612 msr, data);
ed85c068
AP		 2613 return 1;
2614 } else {
fab0aa3b
EM		 2615 if (report_ignored_msrs)
2616 vcpu_unimpl(vcpu,
2617 "ignored wrmsr: 0x%x data 0x%llx\n",
2618 msr, data);
ed85c068
AP		 2619 break;
2620 }
15c4a640
CO		 2621 }
2622 return 0;
2623}
2624EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2625
2626
2627/*
2628 * Reads an msr value (of 'msr_index') into 'pdata'.
2629 * Returns 0 on success, non-0 otherwise.
2630 * Assumes vcpu_load() was already called.
2631 */
609e36d3 2632int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2633{
609e36d3 2634 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2635}
ff651cb6 2636EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2637
44883f01 2638static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2639{
2640 u64 data;
890ca9ae
HY		 2641 u64 mcg_cap = vcpu->arch.mcg_cap;
2642 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2643
2644 switch (msr) {
15c4a640
CO		 2645 case MSR_IA32_P5_MC_ADDR:
2646 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2647 data = 0;
2648 break;
15c4a640 2649 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2650 data = vcpu->arch.mcg_cap;
2651 break;
c7ac679c 2652 case MSR_IA32_MCG_CTL:
44883f01 2653 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2654 return 1;
2655 data = vcpu->arch.mcg_ctl;
2656 break;
2657 case MSR_IA32_MCG_STATUS:
2658 data = vcpu->arch.mcg_status;
2659 break;
2660 default:
2661 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2662 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2663 u32 offset = msr - MSR_IA32_MC0_CTL;
2664 data = vcpu->arch.mce_banks[offset];
2665 break;
2666 }
2667 return 1;
2668 }
2669 *pdata = data;
2670 return 0;
2671}
2672
609e36d3 2673int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2674{
609e36d3 2675 switch (msr_info->index) {
890ca9ae 2676 case MSR_IA32_PLATFORM_ID:
15c4a640 2677 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2678 case MSR_IA32_DEBUGCTLMSR:
2679 case MSR_IA32_LASTBRANCHFROMIP:
2680 case MSR_IA32_LASTBRANCHTOIP:
2681 case MSR_IA32_LASTINTFROMIP:
2682 case MSR_IA32_LASTINTTOIP:
60af2ecd 2683 case MSR_K8_SYSCFG:
3afb1121
PB		 2684 case MSR_K8_TSEG_ADDR:
2685 case MSR_K8_TSEG_MASK:
60af2ecd 2686 case MSR_K7_HWCR:
61a6bd67 2687 case MSR_VM_HSAVE_PA:
1fdbd48c 2688 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2689 case MSR_AMD64_NB_CFG:
f7c6d140 2690 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2691 case MSR_AMD64_BU_CFG2:
0c2df2a1 2692 case MSR_IA32_PERF_CTL:
405a353a 2693 case MSR_AMD64_DC_CFG:
609e36d3 2694 msr_info->data = 0;
15c4a640 2695 break;
c51eb52b 2696 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2697 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2698 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2699 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2700 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2701 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2702 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2703 msr_info->data = 0;
5753785f 2704 break;
742bc670 2705 case MSR_IA32_UCODE_REV:
518e7b94 2706 msr_info->data = vcpu->arch.microcode_version;
742bc670 2707 break;
dd259935
PB		 2708 case MSR_IA32_TSC:
2709 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2710 break;
9ba075a6 2711 case MSR_MTRRcap:
9ba075a6 2712 case 0x200 ... 0x2ff:
ff53604b 2713 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2714 case 0xcd: /* fsb frequency */
609e36d3 2715 msr_info->data = 3;
15c4a640 2716 break;
7b914098
JS		 2717 /*
2718 * MSR_EBC_FREQUENCY_ID
2719 * Conservative value valid for even the basic CPU models.
2720 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2721 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2722 * and 266MHz for model 3, or 4. Set Core Clock
2723 * Frequency to System Bus Frequency Ratio to 1 (bits
2724 * 31:24) even though these are only valid for CPU
2725 * models > 2, however guests may end up dividing or
2726 * multiplying by zero otherwise.
2727 */
2728 case MSR_EBC_FREQUENCY_ID:
609e36d3 2729 msr_info->data = 1 << 24;
7b914098 2730 break;
15c4a640 2731 case MSR_IA32_APICBASE:
609e36d3 2732 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2733 break;
0105d1a5 2734 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2735 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2736 break;
a3e06bbe 2737 case MSR_IA32_TSCDEADLINE:
609e36d3 2738 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2739 break;
ba904635 2740 case MSR_IA32_TSC_ADJUST:
609e36d3 2741 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2742 break;
15c4a640 2743 case MSR_IA32_MISC_ENABLE:
609e36d3 2744 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2745 break;
64d60670
PB		 2746 case MSR_IA32_SMBASE:
2747 if (!msr_info->host_initiated)
2748 return 1;
2749 msr_info->data = vcpu->arch.smbase;
15c4a640 2750 break;
52797bf9
LA		 2751 case MSR_SMI_COUNT:
2752 msr_info->data = vcpu->arch.smi_count;
2753 break;
847f0ad8
AG		 2754 case MSR_IA32_PERF_STATUS:
2755 /* TSC increment by tick */
609e36d3 2756 msr_info->data = 1000ULL;
847f0ad8 2757 /* CPU multiplier */
b0996ae4 2758 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2759 break;
15c4a640 2760 case MSR_EFER:
609e36d3 2761 msr_info->data = vcpu->arch.efer;
15c4a640 2762 break;
18068523 2763 case MSR_KVM_WALL_CLOCK:
11c6bffa 2764 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2765 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2766 break;
2767 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2768 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2769 msr_info->data = vcpu->arch.time;
18068523 2770 break;
344d9588 2771 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2772 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2773 break;
c9aaa895 2774 case MSR_KVM_STEAL_TIME:
609e36d3 2775 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2776 break;
1d92128f 2777 case MSR_KVM_PV_EOI_EN:
609e36d3 2778 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2779 break;
890ca9ae
HY		 2780 case MSR_IA32_P5_MC_ADDR:
2781 case MSR_IA32_P5_MC_TYPE:
2782 case MSR_IA32_MCG_CAP:
2783 case MSR_IA32_MCG_CTL:
2784 case MSR_IA32_MCG_STATUS:
81760dcc 2785 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2786 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2787 msr_info->host_initiated);
84e0cefa
JS		 2788 case MSR_K7_CLK_CTL:
2789 /*
2790 * Provide expected ramp-up count for K7. All other
2791 * are set to zero, indicating minimum divisors for
2792 * every field.
2793 *
2794 * This prevents guest kernels on AMD host with CPU
2795 * type 6, model 8 and higher from exploding due to
2796 * the rdmsr failing.
2797 */
609e36d3 2798 msr_info->data = 0x20000000;
84e0cefa 2799 break;
55cd8e5a 2800 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2801 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2802 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2803 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2804 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2805 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2806 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2807 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2808 msr_info->index, &msr_info->data,
2809 msr_info->host_initiated);
55cd8e5a 2810 break;
91c9c3ed 2811 case MSR_IA32_BBL_CR_CTL3:
2812 /* This legacy MSR exists but isn't fully documented in current
2813 * silicon. It is however accessed by winxp in very narrow
2814 * scenarios where it sets bit #19, itself documented as
2815 * a "reserved" bit. Best effort attempt to source coherent
2816 * read data here should the balance of the register be
2817 * interpreted by the guest:
2818 *
2819 * L2 cache control register 3: 64GB range, 256KB size,
2820 * enabled, latency 0x1, configured
2821 */
609e36d3 2822 msr_info->data = 0xbe702111;
91c9c3ed 2823 break;
2b036c6b 2824 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2825 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2826 return 1;
609e36d3 2827 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2828 break;
2829 case MSR_AMD64_OSVW_STATUS:
d6321d49 2830 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2831 return 1;
609e36d3 2832 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2833 break;
db2336a8 2834 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2835 if (!msr_info->host_initiated &&
2836 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2837 return 1;
db2336a8
KH		 2838 msr_info->data = vcpu->arch.msr_platform_info;
2839 break;
2840 case MSR_MISC_FEATURES_ENABLES:
2841 msr_info->data = vcpu->arch.msr_misc_features_enables;
2842 break;
15c4a640 2843 default:
c6702c9d 2844 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2845 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2846 if (!ignore_msrs) {
ae0f5499
BD		 2847 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2848 msr_info->index);
ed85c068
AP		 2849 return 1;
2850 } else {
fab0aa3b
EM		 2851 if (report_ignored_msrs)
2852 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2853 msr_info->index);
609e36d3 2854 msr_info->data = 0;
ed85c068
AP		 2855 }
2856 break;
15c4a640 2857 }
15c4a640
CO		 2858 return 0;
2859}
2860EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2861
313a3dc7
CO		 2862/*
2863 * Read or write a bunch of msrs. All parameters are kernel addresses.
2864 *
2865 * @return number of msrs set successfully.
2866 */
2867static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2868 struct kvm_msr_entry *entries,
2869 int (*do_msr)(struct kvm_vcpu *vcpu,
2870 unsigned index, u64 *data))
2871{
801e459a 2872 int i;
313a3dc7 2873
313a3dc7
CO		 2874 for (i = 0; i < msrs->nmsrs; ++i)
2875 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2876 break;
2877
313a3dc7
CO		 2878 return i;
2879}
2880
2881/*
2882 * Read or write a bunch of msrs. Parameters are user addresses.
2883 *
2884 * @return number of msrs set successfully.
2885 */
2886static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2887 int (*do_msr)(struct kvm_vcpu *vcpu,
2888 unsigned index, u64 *data),
2889 int writeback)
2890{
2891 struct kvm_msrs msrs;
2892 struct kvm_msr_entry *entries;
2893 int r, n;
2894 unsigned size;
2895
2896 r = -EFAULT;
2897 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2898 goto out;
2899
2900 r = -E2BIG;
2901 if (msrs.nmsrs >= MAX_IO_MSRS)
2902 goto out;
2903
313a3dc7 2904 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2905 entries = memdup_user(user_msrs->entries, size);
2906 if (IS_ERR(entries)) {
2907 r = PTR_ERR(entries);
313a3dc7 2908 goto out;
ff5c2c03 2909 }
313a3dc7
CO		 2910
2911 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2912 if (r < 0)
2913 goto out_free;
2914
2915 r = -EFAULT;
2916 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2917 goto out_free;
2918
2919 r = n;
2920
2921out_free:
7a73c028 2922 kfree(entries);
313a3dc7
CO		 2923out:
2924 return r;
2925}
2926
4d5422ce
WL		 2927static inline bool kvm_can_mwait_in_guest(void)
2928{
2929 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2930 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2931 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2932}
2933
784aa3d7 2934int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2935{
4d5422ce 2936 int r = 0;
018d00d2
ZX		 2937
2938 switch (ext) {
2939 case KVM_CAP_IRQCHIP:
2940 case KVM_CAP_HLT:
2941 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2942 case KVM_CAP_SET_TSS_ADDR:
07716717 2943 case KVM_CAP_EXT_CPUID:
9c15bb1d 2944 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2945 case KVM_CAP_CLOCKSOURCE:
7837699f 2946 case KVM_CAP_PIT:
a28e4f5a 2947 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2948 case KVM_CAP_MP_STATE:
ed848624 2949 case KVM_CAP_SYNC_MMU:
a355c85c 2950 case KVM_CAP_USER_NMI:
52d939a0 2951 case KVM_CAP_REINJECT_CONTROL:
4925663a 2952 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2953 case KVM_CAP_IOEVENTFD:
f848a5a8 2954 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2955 case KVM_CAP_PIT2:
e9f42757 2956 case KVM_CAP_PIT_STATE2:
b927a3ce 2957 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2958 case KVM_CAP_XEN_HVM:
3cfc3092 2959 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2960 case KVM_CAP_HYPERV:
10388a07 2961 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2962 case KVM_CAP_HYPERV_SPIN:
5c919412 2963 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2964 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2965 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2966 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2967 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 2968 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 2969 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
ab9f4ecb 2970 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2971 case KVM_CAP_DEBUGREGS:
d2be1651 2972 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2973 case KVM_CAP_XSAVE:
344d9588 2974 case KVM_CAP_ASYNC_PF:
92a1f12d 2975 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2976 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2977 case KVM_CAP_READONLY_MEM:
5f66b620 2978 case KVM_CAP_HYPERV_TIME:
100943c5 2979 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2980 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2981 case KVM_CAP_ENABLE_CAP_VM:
2982 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2983 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2984 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2985 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2986 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 2987 case KVM_CAP_MSR_PLATFORM_INFO:
018d00d2
ZX		 2988 r = 1;
2989 break;
01643c51
KH		 2990 case KVM_CAP_SYNC_REGS:
2991 r = KVM_SYNC_X86_VALID_FIELDS;
2992 break;
e3fd9a93
PB		 2993 case KVM_CAP_ADJUST_CLOCK:
2994 r = KVM_CLOCK_TSC_STABLE;
2995 break;
4d5422ce 2996 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 2997 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2998 if(kvm_can_mwait_in_guest())
2999 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3000 break;
6d396b55
PB		 3001 case KVM_CAP_X86_SMM:
3002 /* SMBASE is usually relocated above 1M on modern chipsets,
3003 * and SMM handlers might indeed rely on 4G segment limits,
3004 * so do not report SMM to be available if real mode is
3005 * emulated via vm86 mode. Still, do not go to great lengths
3006 * to avoid userspace's usage of the feature, because it is a
3007 * fringe case that is not enabled except via specific settings
3008 * of the module parameters.
3009 */
bc226f07 3010 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3011 break;
774ead3a
AK		 3012 case KVM_CAP_VAPIC:
3013 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3014 break;
f725230a 3015 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3016 r = KVM_SOFT_MAX_VCPUS;
3017 break;
3018 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3019 r = KVM_MAX_VCPUS;
3020 break;
a988b910 3021 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 3022 r = KVM_USER_MEM_SLOTS;
a988b910 3023 break;
a68a6a72
MT		 3024 case KVM_CAP_PV_MMU: /* obsolete */
3025 r = 0;
2f333bcb 3026 break;
890ca9ae
HY		 3027 case KVM_CAP_MCE:
3028 r = KVM_MAX_MCE_BANKS;
3029 break;
2d5b5a66 3030 case KVM_CAP_XCRS:
d366bf7e 3031 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3032 break;
92a1f12d
JR		 3033 case KVM_CAP_TSC_CONTROL:
3034 r = kvm_has_tsc_control;
3035 break;
37131313
RK		 3036 case KVM_CAP_X2APIC_API:
3037 r = KVM_X2APIC_API_VALID_FLAGS;
3038 break;
8fcc4b59
JM		 3039 case KVM_CAP_NESTED_STATE:
3040 r = kvm_x86_ops->get_nested_state ?
3041 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
3042 break;
018d00d2 3043 default:
018d00d2
ZX		 3044 break;
3045 }
3046 return r;
3047
3048}
3049
043405e1
CO		 3050long kvm_arch_dev_ioctl(struct file *filp,
3051 unsigned int ioctl, unsigned long arg)
3052{
3053 void __user *argp = (void __user *)arg;
3054 long r;
3055
3056 switch (ioctl) {
3057 case KVM_GET_MSR_INDEX_LIST: {
3058 struct kvm_msr_list __user *user_msr_list = argp;
3059 struct kvm_msr_list msr_list;
3060 unsigned n;
3061
3062 r = -EFAULT;
3063 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
3064 goto out;
3065 n = msr_list.nmsrs;
62ef68bb 3066 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 3067 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
3068 goto out;
3069 r = -E2BIG;
e125e7b6 3070 if (n < msr_list.nmsrs)
043405e1
CO		 3071 goto out;
3072 r = -EFAULT;
3073 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3074 num_msrs_to_save * sizeof(u32)))
3075 goto out;
e125e7b6 3076 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3077 &emulated_msrs,
62ef68bb 3078 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3079 goto out;
3080 r = 0;
3081 break;
3082 }
9c15bb1d
BP		 3083 case KVM_GET_SUPPORTED_CPUID:
3084 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3085 struct kvm_cpuid2 __user *cpuid_arg = argp;
3086 struct kvm_cpuid2 cpuid;
3087
3088 r = -EFAULT;
3089 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3090 goto out;
9c15bb1d
BP		 3091
3092 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3093 ioctl);
674eea0f
AK		 3094 if (r)
3095 goto out;
3096
3097 r = -EFAULT;
3098 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3099 goto out;
3100 r = 0;
3101 break;
3102 }
890ca9ae 3103 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3104 r = -EFAULT;
c45dcc71
AR		 3105 if (copy_to_user(argp, &kvm_mce_cap_supported,
3106 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3107 goto out;
3108 r = 0;
3109 break;
801e459a
TL		 3110 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3111 struct kvm_msr_list __user *user_msr_list = argp;
3112 struct kvm_msr_list msr_list;
3113 unsigned int n;
3114
3115 r = -EFAULT;
3116 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3117 goto out;
3118 n = msr_list.nmsrs;
3119 msr_list.nmsrs = num_msr_based_features;
3120 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3121 goto out;
3122 r = -E2BIG;
3123 if (n < msr_list.nmsrs)
3124 goto out;
3125 r = -EFAULT;
3126 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3127 num_msr_based_features * sizeof(u32)))
3128 goto out;
3129 r = 0;
3130 break;
3131 }
3132 case KVM_GET_MSRS:
3133 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3134 break;
890ca9ae 3135 }
043405e1
CO		 3136 default:
3137 r = -EINVAL;
3138 }
3139out:
3140 return r;
3141}
3142
f5f48ee1
SY		 3143static void wbinvd_ipi(void *garbage)
3144{
3145 wbinvd();
3146}
3147
3148static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3149{
e0f0bbc5 3150 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3151}
3152
313a3dc7
CO		 3153void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3154{
f5f48ee1
SY		 3155 /* Address WBINVD may be executed by guest */
3156 if (need_emulate_wbinvd(vcpu)) {
3157 if (kvm_x86_ops->has_wbinvd_exit())
3158 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3159 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3160 smp_call_function_single(vcpu->cpu,
3161 wbinvd_ipi, NULL, 1);
3162 }
3163
313a3dc7 3164 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3165
0dd6a6ed
ZA		 3166 /* Apply any externally detected TSC adjustments (due to suspend) */
3167 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3168 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3169 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3170 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3171 }
8f6055cb 3172
b0c39dc6 3173 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3174 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3175 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3176 if (tsc_delta < 0)
3177 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3178
b0c39dc6 3179 if (kvm_check_tsc_unstable()) {
07c1419a 3180 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3181 vcpu->arch.last_guest_tsc);
a545ab6a 3182 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3183 vcpu->arch.tsc_catchup = 1;
c285545f 3184 }
a749e247
PB		 3185
3186 if (kvm_lapic_hv_timer_in_use(vcpu))
3187 kvm_lapic_restart_hv_timer(vcpu);
3188
d98d07ca
MT		 3189 /*
3190 * On a host with synchronized TSC, there is no need to update
3191 * kvmclock on vcpu->cpu migration
3192 */
3193 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3194 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3195 if (vcpu->cpu != cpu)
1bd2009e 3196 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3197 vcpu->cpu = cpu;
6b7d7e76 3198 }
c9aaa895 3199
c9aaa895 3200 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3201}
3202
0b9f6c46
PX		 3203static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3204{
3205 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3206 return;
3207
fa55eedd 3208 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3209
4e335d9e 3210 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3211 &vcpu->arch.st.steal.preempted,
3212 offsetof(struct kvm_steal_time, preempted),
3213 sizeof(vcpu->arch.st.steal.preempted));
3214}
3215
313a3dc7
CO		 3216void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3217{
cc0d907c 3218 int idx;
de63ad4c
LM		 3219
3220 if (vcpu->preempted)
3221 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3222
931f261b
AA		 3223 /*
3224 * Disable page faults because we're in atomic context here.
3225 * kvm_write_guest_offset_cached() would call might_fault()
3226 * that relies on pagefault_disable() to tell if there's a
3227 * bug. NOTE: the write to guest memory may not go through if
3228 * during postcopy live migration or if there's heavy guest
3229 * paging.
3230 */
3231 pagefault_disable();
cc0d907c
AA		 3232 /*
3233 * kvm_memslots() will be called by
3234 * kvm_write_guest_offset_cached() so take the srcu lock.
3235 */
3236 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3237 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3238 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3239 pagefault_enable();
02daab21 3240 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3241 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3242 /*
0e0a53c5
PB		 3243 * Here dr6 is either zero or, if the guest has run and userspace
3244 * has not set any breakpoints or watchpoints, it can be set to
3245 * the guest dr6 (stored in vcpu->arch.dr6). do_debug expects dr6
3246 * to be cleared after it runs, so clear the host register. However,
3247 * MOV to DR can be expensive when running nested, omit it if
3248 * vcpu->arch.dr6 is already zero: in that case, the host dr6 cannot
3249 * currently be nonzero.
efdab992 3250 */
0e0a53c5
PB		 3251 if (vcpu->arch.dr6)
3252 set_debugreg(0, 6);
313a3dc7
CO		 3253}
3254
313a3dc7
CO		 3255static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3256 struct kvm_lapic_state *s)
3257{
fa59cc00 3258 if (vcpu->arch.apicv_active)
d62caabb
AS		 3259 kvm_x86_ops->sync_pir_to_irr(vcpu);
3260
a92e2543 3261 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3262}
3263
3264static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3265 struct kvm_lapic_state *s)
3266{
a92e2543
RK		 3267 int r;
3268
3269 r = kvm_apic_set_state(vcpu, s);
3270 if (r)
3271 return r;
cb142eb7 3272 update_cr8_intercept(vcpu);
313a3dc7
CO		 3273
3274 return 0;
3275}
3276
127a457a
MG		 3277static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3278{
3279 return (!lapic_in_kernel(vcpu) ||
3280 kvm_apic_accept_pic_intr(vcpu));
3281}
3282
782d422b
MG		 3283/*
3284 * if userspace requested an interrupt window, check that the
3285 * interrupt window is open.
3286 *
3287 * No need to exit to userspace if we already have an interrupt queued.
3288 */
3289static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3290{
3291 return kvm_arch_interrupt_allowed(vcpu) &&
3292 !kvm_cpu_has_interrupt(vcpu) &&
3293 !kvm_event_needs_reinjection(vcpu) &&
3294 kvm_cpu_accept_dm_intr(vcpu);
3295}
3296
f77bc6a4
ZX		 3297static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3298 struct kvm_interrupt *irq)
3299{
02cdb50f 3300 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3301 return -EINVAL;
1c1a9ce9
SR		 3302
3303 if (!irqchip_in_kernel(vcpu->kvm)) {
3304 kvm_queue_interrupt(vcpu, irq->irq, false);
3305 kvm_make_request(KVM_REQ_EVENT, vcpu);
3306 return 0;
3307 }
3308
3309 /*
3310 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3311 * fail for in-kernel 8259.
3312 */
3313 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3314 return -ENXIO;
f77bc6a4 3315
1c1a9ce9
SR		 3316 if (vcpu->arch.pending_external_vector != -1)
3317 return -EEXIST;
f77bc6a4 3318
1c1a9ce9 3319 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3320 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3321 return 0;
3322}
3323
c4abb7c9
JK		 3324static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3325{
c4abb7c9 3326 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3327
3328 return 0;
3329}
3330
f077825a
PB		 3331static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3332{
64d60670
PB		 3333 kvm_make_request(KVM_REQ_SMI, vcpu);
3334
f077825a
PB		 3335 return 0;
3336}
3337
b209749f
AK		 3338static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3339 struct kvm_tpr_access_ctl *tac)
3340{
3341 if (tac->flags)
3342 return -EINVAL;
3343 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3344 return 0;
3345}
3346
890ca9ae
HY		 3347static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3348 u64 mcg_cap)
3349{
3350 int r;
3351 unsigned bank_num = mcg_cap & 0xff, bank;
3352
3353 r = -EINVAL;
a9e38c3e 3354 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3355 goto out;
c45dcc71 3356 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3357 goto out;
3358 r = 0;
3359 vcpu->arch.mcg_cap = mcg_cap;
3360 /* Init IA32_MCG_CTL to all 1s */
3361 if (mcg_cap & MCG_CTL_P)
3362 vcpu->arch.mcg_ctl = ~(u64)0;
3363 /* Init IA32_MCi_CTL to all 1s */
3364 for (bank = 0; bank < bank_num; bank++)
3365 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3366
3367 if (kvm_x86_ops->setup_mce)
3368 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3369out:
3370 return r;
3371}
3372
3373static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3374 struct kvm_x86_mce *mce)
3375{
3376 u64 mcg_cap = vcpu->arch.mcg_cap;
3377 unsigned bank_num = mcg_cap & 0xff;
3378 u64 *banks = vcpu->arch.mce_banks;
3379
3380 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3381 return -EINVAL;
3382 /*
3383 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3384 * reporting is disabled
3385 */
3386 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3387 vcpu->arch.mcg_ctl != ~(u64)0)
3388 return 0;
3389 banks += 4 * mce->bank;
3390 /*
3391 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3392 * reporting is disabled for the bank
3393 */
3394 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3395 return 0;
3396 if (mce->status & MCI_STATUS_UC) {
3397 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3398 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3399 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3400 return 0;
3401 }
3402 if (banks[1] & MCI_STATUS_VAL)
3403 mce->status |= MCI_STATUS_OVER;
3404 banks[2] = mce->addr;
3405 banks[3] = mce->misc;
3406 vcpu->arch.mcg_status = mce->mcg_status;
3407 banks[1] = mce->status;
3408 kvm_queue_exception(vcpu, MC_VECTOR);
3409 } else if (!(banks[1] & MCI_STATUS_VAL)
3410 || !(banks[1] & MCI_STATUS_UC)) {
3411 if (banks[1] & MCI_STATUS_VAL)
3412 mce->status |= MCI_STATUS_OVER;
3413 banks[2] = mce->addr;
3414 banks[3] = mce->misc;
3415 banks[1] = mce->status;
3416 } else
3417 banks[1] |= MCI_STATUS_OVER;
3418 return 0;
3419}
3420
3cfc3092
JK		 3421static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3422 struct kvm_vcpu_events *events)
3423{
7460fb4a 3424 process_nmi(vcpu);
59073aaf 3425
664f8e26 3426 /*
59073aaf
JM		 3427 * The API doesn't provide the instruction length for software
3428 * exceptions, so don't report them. As long as the guest RIP
3429 * isn't advanced, we should expect to encounter the exception
3430 * again.
664f8e26 3431 */
59073aaf
JM		 3432 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3433 events->exception.injected = 0;
3434 events->exception.pending = 0;
3435 } else {
3436 events->exception.injected = vcpu->arch.exception.injected;
3437 events->exception.pending = vcpu->arch.exception.pending;
3438 /*
3439 * For ABI compatibility, deliberately conflate
3440 * pending and injected exceptions when
3441 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3442 */
3443 if (!vcpu->kvm->arch.exception_payload_enabled)
3444 events->exception.injected |=
3445 vcpu->arch.exception.pending;
3446 }
3cfc3092
JK		 3447 events->exception.nr = vcpu->arch.exception.nr;
3448 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3449 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3450 events->exception_has_payload = vcpu->arch.exception.has_payload;
3451 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3452
03b82a30 3453 events->interrupt.injected =
04140b41 3454 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3455 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3456 events->interrupt.soft = 0;
37ccdcbe 3457 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3458
3459 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3460 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3461 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3462 events->nmi.pad = 0;
3cfc3092 3463
66450a21 3464 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3465
f077825a
PB		 3466 events->smi.smm = is_smm(vcpu);
3467 events->smi.pending = vcpu->arch.smi_pending;
3468 events->smi.smm_inside_nmi =
3469 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3470 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3471
dab4b911 3472 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3473 | KVM_VCPUEVENT_VALID_SHADOW
3474 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3475 if (vcpu->kvm->arch.exception_payload_enabled)
3476 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3477
97e69aa6 3478 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3479}
3480
6ef4e07e
XG		 3481static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3482
3cfc3092
JK		 3483static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3484 struct kvm_vcpu_events *events)
3485{
dab4b911 3486 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3487 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3488 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3489 | KVM_VCPUEVENT_VALID_SMM
3490 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3491 return -EINVAL;
3492
59073aaf
JM		 3493 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3494 if (!vcpu->kvm->arch.exception_payload_enabled)
3495 return -EINVAL;
3496 if (events->exception.pending)
3497 events->exception.injected = 0;
3498 else
3499 events->exception_has_payload = 0;
3500 } else {
3501 events->exception.pending = 0;
3502 events->exception_has_payload = 0;
3503 }
3504
3505 if ((events->exception.injected || events->exception.pending) &&
3506 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3507 return -EINVAL;
3508
28bf2888
DH		 3509 /* INITs are latched while in SMM */
3510 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3511 (events->smi.smm || events->smi.pending) &&
3512 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3513 return -EINVAL;
3514
7460fb4a 3515 process_nmi(vcpu);
59073aaf
JM		 3516 vcpu->arch.exception.injected = events->exception.injected;
3517 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3518 vcpu->arch.exception.nr = events->exception.nr;
3519 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3520 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3521 vcpu->arch.exception.has_payload = events->exception_has_payload;
3522 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3523
04140b41 3524 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3525 vcpu->arch.interrupt.nr = events->interrupt.nr;
3526 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3527 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3528 kvm_x86_ops->set_interrupt_shadow(vcpu,
3529 events->interrupt.shadow);
3cfc3092
JK		 3530
3531 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3532 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3533 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3534 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3535
66450a21 3536 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3537 lapic_in_kernel(vcpu))
66450a21 3538 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3539
f077825a 3540 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3541 u32 hflags = vcpu->arch.hflags;
f077825a 3542 if (events->smi.smm)
6ef4e07e 3543 hflags |= HF_SMM_MASK;
f077825a 3544 else
6ef4e07e
XG		 3545 hflags &= ~HF_SMM_MASK;
3546 kvm_set_hflags(vcpu, hflags);
3547
f077825a 3548 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3549
3550 if (events->smi.smm) {
3551 if (events->smi.smm_inside_nmi)
3552 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3553 else
f4ef1910
WL		 3554 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3555 if (lapic_in_kernel(vcpu)) {
3556 if (events->smi.latched_init)
3557 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3558 else
3559 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3560 }
f077825a
PB		 3561 }
3562 }
3563
3842d135
AK		 3564 kvm_make_request(KVM_REQ_EVENT, vcpu);
3565
3cfc3092
JK		 3566 return 0;
3567}
3568
a1efbe77
JK		 3569static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3570 struct kvm_debugregs *dbgregs)
3571{
73aaf249
JK		 3572 unsigned long val;
3573
a1efbe77 3574 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3575 kvm_get_dr(vcpu, 6, &val);
73aaf249 3576 dbgregs->dr6 = val;
a1efbe77
JK		 3577 dbgregs->dr7 = vcpu->arch.dr7;
3578 dbgregs->flags = 0;
97e69aa6 3579 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3580}
3581
3582static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3583 struct kvm_debugregs *dbgregs)
3584{
3585 if (dbgregs->flags)
3586 return -EINVAL;
3587
d14bdb55
PB		 3588 if (dbgregs->dr6 & ~0xffffffffull)
3589 return -EINVAL;
3590 if (dbgregs->dr7 & ~0xffffffffull)
3591 return -EINVAL;
3592
a1efbe77 3593 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3594 kvm_update_dr0123(vcpu);
a1efbe77 3595 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3596 kvm_update_dr6(vcpu);
a1efbe77 3597 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3598 kvm_update_dr7(vcpu);
a1efbe77 3599
a1efbe77
JK		 3600 return 0;
3601}
3602
df1daba7
PB		 3603#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3604
3605static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3606{
c47ada30 3607 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3608 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3609 u64 valid;
3610
3611 /*
3612 * Copy legacy XSAVE area, to avoid complications with CPUID
3613 * leaves 0 and 1 in the loop below.
3614 */
3615 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3616
3617 /* Set XSTATE_BV */
00c87e9a 3618 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3619 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3620
3621 /*
3622 * Copy each region from the possibly compacted offset to the
3623 * non-compacted offset.
3624 */
d91cab78 3625 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3626 while (valid) {
3627 u64 feature = valid & -valid;
3628 int index = fls64(feature) - 1;
3629 void *src = get_xsave_addr(xsave, feature);
3630
3631 if (src) {
3632 u32 size, offset, ecx, edx;
3633 cpuid_count(XSTATE_CPUID, index,
3634 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3635 if (feature == XFEATURE_MASK_PKRU)
3636 memcpy(dest + offset, &vcpu->arch.pkru,
3637 sizeof(vcpu->arch.pkru));
3638 else
3639 memcpy(dest + offset, src, size);
3640
df1daba7
PB		 3641 }
3642
3643 valid -= feature;
3644 }
3645}
3646
3647static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3648{
c47ada30 3649 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3650 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3651 u64 valid;
3652
3653 /*
3654 * Copy legacy XSAVE area, to avoid complications with CPUID
3655 * leaves 0 and 1 in the loop below.
3656 */
3657 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3658
3659 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3660 xsave->header.xfeatures = xstate_bv;
782511b0 3661 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3662 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3663
3664 /*
3665 * Copy each region from the non-compacted offset to the
3666 * possibly compacted offset.
3667 */
d91cab78 3668 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3669 while (valid) {
3670 u64 feature = valid & -valid;
3671 int index = fls64(feature) - 1;
3672 void *dest = get_xsave_addr(xsave, feature);
3673
3674 if (dest) {
3675 u32 size, offset, ecx, edx;
3676 cpuid_count(XSTATE_CPUID, index,
3677 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3678 if (feature == XFEATURE_MASK_PKRU)
3679 memcpy(&vcpu->arch.pkru, src + offset,
3680 sizeof(vcpu->arch.pkru));
3681 else
3682 memcpy(dest, src + offset, size);
ee4100da 3683 }
df1daba7
PB		 3684
3685 valid -= feature;
3686 }
3687}
3688
2d5b5a66
SY		 3689static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3690 struct kvm_xsave *guest_xsave)
3691{
d366bf7e 3692 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3693 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3694 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3695 } else {
2d5b5a66 3696 memcpy(guest_xsave->region,
7366ed77 3697 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3698 sizeof(struct fxregs_state));
2d5b5a66 3699 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3700 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3701 }
3702}
3703
a575813b
WL		 3704#define XSAVE_MXCSR_OFFSET 24
3705
2d5b5a66
SY		 3706static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3707 struct kvm_xsave *guest_xsave)
3708{
3709 u64 xstate_bv =
3710 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3711 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3712
d366bf7e 3713 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3714 /*
3715 * Here we allow setting states that are not present in
3716 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3717 * with old userspace.
3718 */
a575813b
WL		 3719 if (xstate_bv & ~kvm_supported_xcr0() ||
3720 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3721 return -EINVAL;
df1daba7 3722 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3723 } else {
a575813b
WL		 3724 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3725 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3726 return -EINVAL;
7366ed77 3727 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3728 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3729 }
3730 return 0;
3731}
3732
3733static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3734 struct kvm_xcrs *guest_xcrs)
3735{
d366bf7e 3736 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3737 guest_xcrs->nr_xcrs = 0;
3738 return;
3739 }
3740
3741 guest_xcrs->nr_xcrs = 1;
3742 guest_xcrs->flags = 0;
3743 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3744 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3745}
3746
3747static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3748 struct kvm_xcrs *guest_xcrs)
3749{
3750 int i, r = 0;
3751
d366bf7e 3752 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3753 return -EINVAL;
3754
3755 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3756 return -EINVAL;
3757
3758 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3759 /* Only support XCR0 currently */
c67a04cb 3760 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3761 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3762 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3763 break;
3764 }
3765 if (r)
3766 r = -EINVAL;
3767 return r;
3768}
3769
1c0b28c2
EM		 3770/*
3771 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3772 * stopped by the hypervisor. This function will be called from the host only.
3773 * EINVAL is returned when the host attempts to set the flag for a guest that
3774 * does not support pv clocks.
3775 */
3776static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3777{
0b79459b 3778 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3779 return -EINVAL;
51d59c6b 3780 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3781 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3782 return 0;
3783}
3784
5c919412
AS		 3785static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3786 struct kvm_enable_cap *cap)
3787{
57b119da
VK		 3788 int r;
3789 uint16_t vmcs_version;
3790 void __user *user_ptr;
3791
5c919412
AS		 3792 if (cap->flags)
3793 return -EINVAL;
3794
3795 switch (cap->cap) {
efc479e6
RK		 3796 case KVM_CAP_HYPERV_SYNIC2:
3797 if (cap->args[0])
3798 return -EINVAL;
5c919412 3799 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3800 if (!irqchip_in_kernel(vcpu->kvm))
3801 return -EINVAL;
efc479e6
RK		 3802 return kvm_hv_activate_synic(vcpu, cap->cap ==
3803 KVM_CAP_HYPERV_SYNIC2);
57b119da
VK		 3804 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3805 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3806 if (!r) {
3807 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3808 if (copy_to_user(user_ptr, &vmcs_version,
3809 sizeof(vmcs_version)))
3810 r = -EFAULT;
3811 }
3812 return r;
3813
5c919412
AS		 3814 default:
3815 return -EINVAL;
3816 }
3817}
3818
313a3dc7
CO		 3819long kvm_arch_vcpu_ioctl(struct file *filp,
3820 unsigned int ioctl, unsigned long arg)
3821{
3822 struct kvm_vcpu *vcpu = filp->private_data;
3823 void __user *argp = (void __user *)arg;
3824 int r;
d1ac91d8
AK		 3825 union {
3826 struct kvm_lapic_state *lapic;
3827 struct kvm_xsave *xsave;
3828 struct kvm_xcrs *xcrs;
3829 void *buffer;
3830 } u;
3831
9b062471
CD		 3832 vcpu_load(vcpu);
3833
d1ac91d8 3834 u.buffer = NULL;
313a3dc7
CO		 3835 switch (ioctl) {
3836 case KVM_GET_LAPIC: {
2204ae3c 3837 r = -EINVAL;
bce87cce 3838 if (!lapic_in_kernel(vcpu))
2204ae3c 3839 goto out;
d1ac91d8 3840 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3841
b772ff36 3842 r = -ENOMEM;
d1ac91d8 3843 if (!u.lapic)
b772ff36 3844 goto out;
d1ac91d8 3845 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3846 if (r)
3847 goto out;
3848 r = -EFAULT;
d1ac91d8 3849 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3850 goto out;
3851 r = 0;
3852 break;
3853 }
3854 case KVM_SET_LAPIC: {
2204ae3c 3855 r = -EINVAL;
bce87cce 3856 if (!lapic_in_kernel(vcpu))
2204ae3c 3857 goto out;
ff5c2c03 3858 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3859 if (IS_ERR(u.lapic)) {
3860 r = PTR_ERR(u.lapic);
3861 goto out_nofree;
3862 }
ff5c2c03 3863
d1ac91d8 3864 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3865 break;
3866 }
f77bc6a4
ZX		 3867 case KVM_INTERRUPT: {
3868 struct kvm_interrupt irq;
3869
3870 r = -EFAULT;
3871 if (copy_from_user(&irq, argp, sizeof irq))
3872 goto out;
3873 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3874 break;
3875 }
c4abb7c9
JK		 3876 case KVM_NMI: {
3877 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3878 break;
3879 }
f077825a
PB		 3880 case KVM_SMI: {
3881 r = kvm_vcpu_ioctl_smi(vcpu);
3882 break;
3883 }
313a3dc7
CO		 3884 case KVM_SET_CPUID: {
3885 struct kvm_cpuid __user *cpuid_arg = argp;
3886 struct kvm_cpuid cpuid;
3887
3888 r = -EFAULT;
3889 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3890 goto out;
3891 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3892 break;
3893 }
07716717
DK		 3894 case KVM_SET_CPUID2: {
3895 struct kvm_cpuid2 __user *cpuid_arg = argp;
3896 struct kvm_cpuid2 cpuid;
3897
3898 r = -EFAULT;
3899 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3900 goto out;
3901 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3902 cpuid_arg->entries);
07716717
DK		 3903 break;
3904 }
3905 case KVM_GET_CPUID2: {
3906 struct kvm_cpuid2 __user *cpuid_arg = argp;
3907 struct kvm_cpuid2 cpuid;
3908
3909 r = -EFAULT;
3910 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3911 goto out;
3912 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3913 cpuid_arg->entries);
07716717
DK		 3914 if (r)
3915 goto out;
3916 r = -EFAULT;
3917 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3918 goto out;
3919 r = 0;
3920 break;
3921 }
801e459a
TL		 3922 case KVM_GET_MSRS: {
3923 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3924 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3925 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3926 break;
801e459a
TL		 3927 }
3928 case KVM_SET_MSRS: {
3929 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3930 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3931 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3932 break;
801e459a 3933 }
b209749f
AK		 3934 case KVM_TPR_ACCESS_REPORTING: {
3935 struct kvm_tpr_access_ctl tac;
3936
3937 r = -EFAULT;
3938 if (copy_from_user(&tac, argp, sizeof tac))
3939 goto out;
3940 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3941 if (r)
3942 goto out;
3943 r = -EFAULT;
3944 if (copy_to_user(argp, &tac, sizeof tac))
3945 goto out;
3946 r = 0;
3947 break;
3948 };
b93463aa
AK		 3949 case KVM_SET_VAPIC_ADDR: {
3950 struct kvm_vapic_addr va;
7301d6ab 3951 int idx;
b93463aa
AK		 3952
3953 r = -EINVAL;
35754c98 3954 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3955 goto out;
3956 r = -EFAULT;
3957 if (copy_from_user(&va, argp, sizeof va))
3958 goto out;
7301d6ab 3959 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3960 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3961 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3962 break;
3963 }
890ca9ae
HY		 3964 case KVM_X86_SETUP_MCE: {
3965 u64 mcg_cap;
3966
3967 r = -EFAULT;
3968 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3969 goto out;
3970 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3971 break;
3972 }
3973 case KVM_X86_SET_MCE: {
3974 struct kvm_x86_mce mce;
3975
3976 r = -EFAULT;
3977 if (copy_from_user(&mce, argp, sizeof mce))
3978 goto out;
3979 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3980 break;
3981 }
3cfc3092
JK		 3982 case KVM_GET_VCPU_EVENTS: {
3983 struct kvm_vcpu_events events;
3984
3985 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3986
3987 r = -EFAULT;
3988 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3989 break;
3990 r = 0;
3991 break;
3992 }
3993 case KVM_SET_VCPU_EVENTS: {
3994 struct kvm_vcpu_events events;
3995
3996 r = -EFAULT;
3997 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3998 break;
3999
4000 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4001 break;
4002 }
a1efbe77
JK		 4003 case KVM_GET_DEBUGREGS: {
4004 struct kvm_debugregs dbgregs;
4005
4006 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4007
4008 r = -EFAULT;
4009 if (copy_to_user(argp, &dbgregs,
4010 sizeof(struct kvm_debugregs)))
4011 break;
4012 r = 0;
4013 break;
4014 }
4015 case KVM_SET_DEBUGREGS: {
4016 struct kvm_debugregs dbgregs;
4017
4018 r = -EFAULT;
4019 if (copy_from_user(&dbgregs, argp,
4020 sizeof(struct kvm_debugregs)))
4021 break;
4022
4023 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4024 break;
4025 }
2d5b5a66 4026 case KVM_GET_XSAVE: {
d1ac91d8 4027 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 4028 r = -ENOMEM;
d1ac91d8 4029 if (!u.xsave)
2d5b5a66
SY		 4030 break;
4031
d1ac91d8 4032 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4033
4034 r = -EFAULT;
d1ac91d8 4035 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4036 break;
4037 r = 0;
4038 break;
4039 }
4040 case KVM_SET_XSAVE: {
ff5c2c03 4041 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4042 if (IS_ERR(u.xsave)) {
4043 r = PTR_ERR(u.xsave);
4044 goto out_nofree;
4045 }
2d5b5a66 4046
d1ac91d8 4047 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4048 break;
4049 }
4050 case KVM_GET_XCRS: {
d1ac91d8 4051 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 4052 r = -ENOMEM;
d1ac91d8 4053 if (!u.xcrs)
2d5b5a66
SY		 4054 break;
4055
d1ac91d8 4056 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4057
4058 r = -EFAULT;
d1ac91d8 4059 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4060 sizeof(struct kvm_xcrs)))
4061 break;
4062 r = 0;
4063 break;
4064 }
4065 case KVM_SET_XCRS: {
ff5c2c03 4066 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4067 if (IS_ERR(u.xcrs)) {
4068 r = PTR_ERR(u.xcrs);
4069 goto out_nofree;
4070 }
2d5b5a66 4071
d1ac91d8 4072 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4073 break;
4074 }
92a1f12d
JR		 4075 case KVM_SET_TSC_KHZ: {
4076 u32 user_tsc_khz;
4077
4078 r = -EINVAL;
92a1f12d
JR		 4079 user_tsc_khz = (u32)arg;
4080
4081 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4082 goto out;
4083
cc578287
ZA		 4084 if (user_tsc_khz == 0)
4085 user_tsc_khz = tsc_khz;
4086
381d585c
HZ		 4087 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4088 r = 0;
92a1f12d 4089
92a1f12d
JR		 4090 goto out;
4091 }
4092 case KVM_GET_TSC_KHZ: {
cc578287 4093 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4094 goto out;
4095 }
1c0b28c2
EM		 4096 case KVM_KVMCLOCK_CTRL: {
4097 r = kvm_set_guest_paused(vcpu);
4098 goto out;
4099 }
5c919412
AS		 4100 case KVM_ENABLE_CAP: {
4101 struct kvm_enable_cap cap;
4102
4103 r = -EFAULT;
4104 if (copy_from_user(&cap, argp, sizeof(cap)))
4105 goto out;
4106 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4107 break;
4108 }
8fcc4b59
JM		 4109 case KVM_GET_NESTED_STATE: {
4110 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4111 u32 user_data_size;
4112
4113 r = -EINVAL;
4114 if (!kvm_x86_ops->get_nested_state)
4115 break;
4116
4117 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4118 r = -EFAULT;
8fcc4b59 4119 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4120 break;
8fcc4b59
JM		 4121
4122 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4123 user_data_size);
4124 if (r < 0)
26b471c7 4125 break;
8fcc4b59
JM		 4126
4127 if (r > user_data_size) {
4128 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4129 r = -EFAULT;
4130 else
4131 r = -E2BIG;
4132 break;
8fcc4b59 4133 }
26b471c7 4134
8fcc4b59
JM		 4135 r = 0;
4136 break;
4137 }
4138 case KVM_SET_NESTED_STATE: {
4139 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4140 struct kvm_nested_state kvm_state;
4141
4142 r = -EINVAL;
4143 if (!kvm_x86_ops->set_nested_state)
4144 break;
4145
26b471c7 4146 r = -EFAULT;
8fcc4b59 4147 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4148 break;
8fcc4b59 4149
26b471c7 4150 r = -EINVAL;
8fcc4b59 4151 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4152 break;
8fcc4b59
JM		 4153
4154 if (kvm_state.flags &
8cab6507
VK		 4155 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4156 | KVM_STATE_NESTED_EVMCS))
26b471c7 4157 break;
8fcc4b59
JM		 4158
4159 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4160 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4161 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4162 break;
8fcc4b59
JM		 4163
4164 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4165 break;
4166 }
313a3dc7
CO		 4167 default:
4168 r = -EINVAL;
4169 }
4170out:
d1ac91d8 4171 kfree(u.buffer);
9b062471
CD		 4172out_nofree:
4173 vcpu_put(vcpu);
313a3dc7
CO		 4174 return r;
4175}
4176
1499fa80 4177vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4178{
4179 return VM_FAULT_SIGBUS;
4180}
4181
1fe779f8
CO		 4182static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4183{
4184 int ret;
4185
4186 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4187 return -EINVAL;
1fe779f8
CO		 4188 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4189 return ret;
4190}
4191
b927a3ce
SY		 4192static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4193 u64 ident_addr)
4194{
2ac52ab8 4195 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4196}
4197
1fe779f8
CO		 4198static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4199 u32 kvm_nr_mmu_pages)
4200{
4201 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4202 return -EINVAL;
4203
79fac95e 4204 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4205
4206 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4207 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4208
79fac95e 4209 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4210 return 0;
4211}
4212
4213static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4214{
39de71ec 4215 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4216}
4217
1fe779f8
CO		 4218static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4219{
90bca052 4220 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4221 int r;
4222
4223 r = 0;
4224 switch (chip->chip_id) {
4225 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4226 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4227 sizeof(struct kvm_pic_state));
4228 break;
4229 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4230 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4231 sizeof(struct kvm_pic_state));
4232 break;
4233 case KVM_IRQCHIP_IOAPIC:
33392b49 4234 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4235 break;
4236 default:
4237 r = -EINVAL;
4238 break;
4239 }
4240 return r;
4241}
4242
4243static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4244{
90bca052 4245 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4246 int r;
4247
4248 r = 0;
4249 switch (chip->chip_id) {
4250 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4251 spin_lock(&pic->lock);
4252 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4253 sizeof(struct kvm_pic_state));
90bca052 4254 spin_unlock(&pic->lock);
1fe779f8
CO		 4255 break;
4256 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4257 spin_lock(&pic->lock);
4258 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4259 sizeof(struct kvm_pic_state));
90bca052 4260 spin_unlock(&pic->lock);
1fe779f8
CO		 4261 break;
4262 case KVM_IRQCHIP_IOAPIC:
33392b49 4263 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4264 break;
4265 default:
4266 r = -EINVAL;
4267 break;
4268 }
90bca052 4269 kvm_pic_update_irq(pic);
1fe779f8
CO		 4270 return r;
4271}
4272
e0f63cb9
SY		 4273static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4274{
34f3941c
RK		 4275 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4276
4277 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4278
4279 mutex_lock(&kps->lock);
4280 memcpy(ps, &kps->channels, sizeof(*ps));
4281 mutex_unlock(&kps->lock);
2da29bcc 4282 return 0;
e0f63cb9
SY		 4283}
4284
4285static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4286{
0185604c 4287 int i;
09edea72
RK		 4288 struct kvm_pit *pit = kvm->arch.vpit;
4289
4290 mutex_lock(&pit->pit_state.lock);
34f3941c 4291 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4292 for (i = 0; i < 3; i++)
09edea72
RK		 4293 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4294 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4295 return 0;
e9f42757
BK		 4296}
4297
4298static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4299{
e9f42757
BK		 4300 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4301 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4302 sizeof(ps->channels));
4303 ps->flags = kvm->arch.vpit->pit_state.flags;
4304 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4305 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4306 return 0;
e9f42757
BK		 4307}
4308
4309static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4310{
2da29bcc 4311 int start = 0;
0185604c 4312 int i;
e9f42757 4313 u32 prev_legacy, cur_legacy;
09edea72
RK		 4314 struct kvm_pit *pit = kvm->arch.vpit;
4315
4316 mutex_lock(&pit->pit_state.lock);
4317 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4318 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4319 if (!prev_legacy && cur_legacy)
4320 start = 1;
09edea72
RK		 4321 memcpy(&pit->pit_state.channels, &ps->channels,
4322 sizeof(pit->pit_state.channels));
4323 pit->pit_state.flags = ps->flags;
0185604c 4324 for (i = 0; i < 3; i++)
09edea72 4325 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4326 start && i == 0);
09edea72 4327 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4328 return 0;
e0f63cb9
SY		 4329}
4330
52d939a0
MT		 4331static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4332 struct kvm_reinject_control *control)
4333{
71474e2f
RK		 4334 struct kvm_pit *pit = kvm->arch.vpit;
4335
4336 if (!pit)
52d939a0 4337 return -ENXIO;
b39c90b6 4338
71474e2f
RK		 4339 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4340 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4341 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4342 */
4343 mutex_lock(&pit->pit_state.lock);
4344 kvm_pit_set_reinject(pit, control->pit_reinject);
4345 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4346
52d939a0
MT		 4347 return 0;
4348}
4349
95d4c16c 4350/**
60c34612
TY		 4351 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4352 * @kvm: kvm instance
4353 * @log: slot id and address to which we copy the log
95d4c16c 4354 *
e108ff2f
PB		 4355 * Steps 1-4 below provide general overview of dirty page logging. See
4356 * kvm_get_dirty_log_protect() function description for additional details.
4357 *
4358 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4359 * always flush the TLB (step 4) even if previous step failed and the dirty
4360 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4361 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4362 * writes will be marked dirty for next log read.
95d4c16c 4363 *
60c34612
TY		 4364 * 1. Take a snapshot of the bit and clear it if needed.
4365 * 2. Write protect the corresponding page.
e108ff2f
PB		 4366 * 3. Copy the snapshot to the userspace.
4367 * 4. Flush TLB's if needed.
5bb064dc 4368 */
60c34612 4369int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4370{
60c34612 4371 bool is_dirty = false;
e108ff2f 4372 int r;
5bb064dc 4373
79fac95e 4374 mutex_lock(&kvm->slots_lock);
5bb064dc 4375
88178fd4
KH		 4376 /*
4377 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4378 */
4379 if (kvm_x86_ops->flush_log_dirty)
4380 kvm_x86_ops->flush_log_dirty(kvm);
4381
e108ff2f 4382 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4383
4384 /*
4385 * All the TLBs can be flushed out of mmu lock, see the comments in
4386 * kvm_mmu_slot_remove_write_access().
4387 */
e108ff2f 4388 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4389 if (is_dirty)
4390 kvm_flush_remote_tlbs(kvm);
4391
79fac95e 4392 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4393 return r;
4394}
4395
aa2fbe6d
YZ		 4396int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4397 bool line_status)
23d43cf9
CD		 4398{
4399 if (!irqchip_in_kernel(kvm))
4400 return -ENXIO;
4401
4402 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4403 irq_event->irq, irq_event->level,
4404 line_status);
23d43cf9
CD		 4405 return 0;
4406}
4407
90de4a18
NA		 4408static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4409 struct kvm_enable_cap *cap)
4410{
4411 int r;
4412
4413 if (cap->flags)
4414 return -EINVAL;
4415
4416 switch (cap->cap) {
4417 case KVM_CAP_DISABLE_QUIRKS:
4418 kvm->arch.disabled_quirks = cap->args[0];
4419 r = 0;
4420 break;
49df6397
SR		 4421 case KVM_CAP_SPLIT_IRQCHIP: {
4422 mutex_lock(&kvm->lock);
b053b2ae
SR		 4423 r = -EINVAL;
4424 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4425 goto split_irqchip_unlock;
49df6397
SR		 4426 r = -EEXIST;
4427 if (irqchip_in_kernel(kvm))
4428 goto split_irqchip_unlock;
557abc40 4429 if (kvm->created_vcpus)
49df6397
SR		 4430 goto split_irqchip_unlock;
4431 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4432 if (r)
49df6397
SR		 4433 goto split_irqchip_unlock;
4434 /* Pairs with irqchip_in_kernel. */
4435 smp_wmb();
49776faf 4436 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4437 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4438 r = 0;
4439split_irqchip_unlock:
4440 mutex_unlock(&kvm->lock);
4441 break;
4442 }
37131313
RK		 4443 case KVM_CAP_X2APIC_API:
4444 r = -EINVAL;
4445 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4446 break;
4447
4448 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4449 kvm->arch.x2apic_format = true;
c519265f
RK		 4450 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4451 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4452
4453 r = 0;
4454 break;
4d5422ce
WL		 4455 case KVM_CAP_X86_DISABLE_EXITS:
4456 r = -EINVAL;
4457 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4458 break;
4459
4460 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4461 kvm_can_mwait_in_guest())
4462 kvm->arch.mwait_in_guest = true;
766d3571 4463 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4464 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4465 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4466 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4467 r = 0;
4468 break;
6fbbde9a
DS		 4469 case KVM_CAP_MSR_PLATFORM_INFO:
4470 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4471 r = 0;
4472 break;
90de4a18
NA		 4473 default:
4474 r = -EINVAL;
4475 break;
4476 }
4477 return r;
4478}
4479
1fe779f8
CO		 4480long kvm_arch_vm_ioctl(struct file *filp,
4481 unsigned int ioctl, unsigned long arg)
4482{
4483 struct kvm *kvm = filp->private_data;
4484 void __user *argp = (void __user *)arg;
367e1319 4485 int r = -ENOTTY;
f0d66275
DH		 4486 /*
4487 * This union makes it completely explicit to gcc-3.x
4488 * that these two variables' stack usage should be
4489 * combined, not added together.
4490 */
4491 union {
4492 struct kvm_pit_state ps;
e9f42757 4493 struct kvm_pit_state2 ps2;
c5ff41ce 4494 struct kvm_pit_config pit_config;
f0d66275 4495 } u;
1fe779f8
CO		 4496
4497 switch (ioctl) {
4498 case KVM_SET_TSS_ADDR:
4499 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4500 break;
b927a3ce
SY		 4501 case KVM_SET_IDENTITY_MAP_ADDR: {
4502 u64 ident_addr;
4503
1af1ac91
DH		 4504 mutex_lock(&kvm->lock);
4505 r = -EINVAL;
4506 if (kvm->created_vcpus)
4507 goto set_identity_unlock;
b927a3ce
SY		 4508 r = -EFAULT;
4509 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4510 goto set_identity_unlock;
b927a3ce 4511 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4512set_identity_unlock:
4513 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4514 break;
4515 }
1fe779f8
CO		 4516 case KVM_SET_NR_MMU_PAGES:
4517 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4518 break;
4519 case KVM_GET_NR_MMU_PAGES:
4520 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4521 break;
3ddea128 4522 case KVM_CREATE_IRQCHIP: {
3ddea128 4523 mutex_lock(&kvm->lock);
09941366 4524
3ddea128 4525 r = -EEXIST;
35e6eaa3 4526 if (irqchip_in_kernel(kvm))
3ddea128 4527 goto create_irqchip_unlock;
09941366 4528
3e515705 4529 r = -EINVAL;
557abc40 4530 if (kvm->created_vcpus)
3e515705 4531 goto create_irqchip_unlock;
09941366
RK		 4532
4533 r = kvm_pic_init(kvm);
4534 if (r)
3ddea128 4535 goto create_irqchip_unlock;
09941366
RK		 4536
4537 r = kvm_ioapic_init(kvm);
4538 if (r) {
09941366 4539 kvm_pic_destroy(kvm);
3ddea128 4540 goto create_irqchip_unlock;
09941366
RK		 4541 }
4542
399ec807
AK		 4543 r = kvm_setup_default_irq_routing(kvm);
4544 if (r) {
72bb2fcd 4545 kvm_ioapic_destroy(kvm);
09941366 4546 kvm_pic_destroy(kvm);
71ba994c 4547 goto create_irqchip_unlock;
399ec807 4548 }
49776faf 4549 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4550 smp_wmb();
49776faf 4551 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4552 create_irqchip_unlock:
4553 mutex_unlock(&kvm->lock);
1fe779f8 4554 break;
3ddea128 4555 }
7837699f 4556 case KVM_CREATE_PIT:
c5ff41ce
JK		 4557 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4558 goto create_pit;
4559 case KVM_CREATE_PIT2:
4560 r = -EFAULT;
4561 if (copy_from_user(&u.pit_config, argp,
4562 sizeof(struct kvm_pit_config)))
4563 goto out;
4564 create_pit:
250715a6 4565 mutex_lock(&kvm->lock);
269e05e4
AK		 4566 r = -EEXIST;
4567 if (kvm->arch.vpit)
4568 goto create_pit_unlock;
7837699f 4569 r = -ENOMEM;
c5ff41ce 4570 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4571 if (kvm->arch.vpit)
4572 r = 0;
269e05e4 4573 create_pit_unlock:
250715a6 4574 mutex_unlock(&kvm->lock);
7837699f 4575 break;
1fe779f8
CO		 4576 case KVM_GET_IRQCHIP: {
4577 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4578 struct kvm_irqchip *chip;
1fe779f8 4579
ff5c2c03
SL		 4580 chip = memdup_user(argp, sizeof(*chip));
4581 if (IS_ERR(chip)) {
4582 r = PTR_ERR(chip);
1fe779f8 4583 goto out;
ff5c2c03
SL		 4584 }
4585
1fe779f8 4586 r = -ENXIO;
826da321 4587 if (!irqchip_kernel(kvm))
f0d66275
DH		 4588 goto get_irqchip_out;
4589 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4590 if (r)
f0d66275 4591 goto get_irqchip_out;
1fe779f8 4592 r = -EFAULT;
f0d66275
DH		 4593 if (copy_to_user(argp, chip, sizeof *chip))
4594 goto get_irqchip_out;
1fe779f8 4595 r = 0;
f0d66275
DH		 4596 get_irqchip_out:
4597 kfree(chip);
1fe779f8
CO		 4598 break;
4599 }
4600 case KVM_SET_IRQCHIP: {
4601 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4602 struct kvm_irqchip *chip;
1fe779f8 4603
ff5c2c03
SL		 4604 chip = memdup_user(argp, sizeof(*chip));
4605 if (IS_ERR(chip)) {
4606 r = PTR_ERR(chip);
1fe779f8 4607 goto out;
ff5c2c03
SL		 4608 }
4609
1fe779f8 4610 r = -ENXIO;
826da321 4611 if (!irqchip_kernel(kvm))
f0d66275
DH		 4612 goto set_irqchip_out;
4613 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4614 if (r)
f0d66275 4615 goto set_irqchip_out;
1fe779f8 4616 r = 0;
f0d66275
DH		 4617 set_irqchip_out:
4618 kfree(chip);
1fe779f8
CO		 4619 break;
4620 }
e0f63cb9 4621 case KVM_GET_PIT: {
e0f63cb9 4622 r = -EFAULT;
f0d66275 4623 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4624 goto out;
4625 r = -ENXIO;
4626 if (!kvm->arch.vpit)
4627 goto out;
f0d66275 4628 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4629 if (r)
4630 goto out;
4631 r = -EFAULT;
f0d66275 4632 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4633 goto out;
4634 r = 0;
4635 break;
4636 }
4637 case KVM_SET_PIT: {
e0f63cb9 4638 r = -EFAULT;
f0d66275 4639 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4640 goto out;
4641 r = -ENXIO;
4642 if (!kvm->arch.vpit)
4643 goto out;
f0d66275 4644 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4645 break;
4646 }
e9f42757
BK		 4647 case KVM_GET_PIT2: {
4648 r = -ENXIO;
4649 if (!kvm->arch.vpit)
4650 goto out;
4651 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4652 if (r)
4653 goto out;
4654 r = -EFAULT;
4655 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4656 goto out;
4657 r = 0;
4658 break;
4659 }
4660 case KVM_SET_PIT2: {
4661 r = -EFAULT;
4662 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4663 goto out;
4664 r = -ENXIO;
4665 if (!kvm->arch.vpit)
4666 goto out;
4667 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4668 break;
4669 }
52d939a0
MT		 4670 case KVM_REINJECT_CONTROL: {
4671 struct kvm_reinject_control control;
4672 r = -EFAULT;
4673 if (copy_from_user(&control, argp, sizeof(control)))
4674 goto out;
4675 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4676 break;
4677 }
d71ba788
PB		 4678 case KVM_SET_BOOT_CPU_ID:
4679 r = 0;
4680 mutex_lock(&kvm->lock);
557abc40 4681 if (kvm->created_vcpus)
d71ba788
PB		 4682 r = -EBUSY;
4683 else
4684 kvm->arch.bsp_vcpu_id = arg;
4685 mutex_unlock(&kvm->lock);
4686 break;
ffde22ac 4687 case KVM_XEN_HVM_CONFIG: {
51776043 4688 struct kvm_xen_hvm_config xhc;
ffde22ac 4689 r = -EFAULT;
51776043 4690 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4691 goto out;
4692 r = -EINVAL;
51776043 4693 if (xhc.flags)
ffde22ac 4694 goto out;
51776043 4695 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4696 r = 0;
4697 break;
4698 }
afbcf7ab 4699 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4700 struct kvm_clock_data user_ns;
4701 u64 now_ns;
afbcf7ab
GC		 4702
4703 r = -EFAULT;
4704 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4705 goto out;
4706
4707 r = -EINVAL;
4708 if (user_ns.flags)
4709 goto out;
4710
4711 r = 0;
0bc48bea
RK		 4712 /*
4713 * TODO: userspace has to take care of races with VCPU_RUN, so
4714 * kvm_gen_update_masterclock() can be cut down to locked
4715 * pvclock_update_vm_gtod_copy().
4716 */
4717 kvm_gen_update_masterclock(kvm);
e891a32e 4718 now_ns = get_kvmclock_ns(kvm);
108b249c 4719 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4720 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4721 break;
4722 }
4723 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4724 struct kvm_clock_data user_ns;
4725 u64 now_ns;
4726
e891a32e 4727 now_ns = get_kvmclock_ns(kvm);
108b249c 4728 user_ns.clock = now_ns;
e3fd9a93 4729 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4730 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4731
4732 r = -EFAULT;
4733 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4734 goto out;
4735 r = 0;
4736 break;
4737 }
90de4a18
NA		 4738 case KVM_ENABLE_CAP: {
4739 struct kvm_enable_cap cap;
afbcf7ab 4740
90de4a18
NA		 4741 r = -EFAULT;
4742 if (copy_from_user(&cap, argp, sizeof(cap)))
4743 goto out;
4744 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4745 break;
4746 }
5acc5c06
BS		 4747 case KVM_MEMORY_ENCRYPT_OP: {
4748 r = -ENOTTY;
4749 if (kvm_x86_ops->mem_enc_op)
4750 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4751 break;
4752 }
69eaedee
BS		 4753 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4754 struct kvm_enc_region region;
4755
4756 r = -EFAULT;
4757 if (copy_from_user(&region, argp, sizeof(region)))
4758 goto out;
4759
4760 r = -ENOTTY;
4761 if (kvm_x86_ops->mem_enc_reg_region)
4762 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4763 break;
4764 }
4765 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4766 struct kvm_enc_region region;
4767
4768 r = -EFAULT;
4769 if (copy_from_user(&region, argp, sizeof(region)))
4770 goto out;
4771
4772 r = -ENOTTY;
4773 if (kvm_x86_ops->mem_enc_unreg_region)
4774 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4775 break;
4776 }
faeb7833
RK		 4777 case KVM_HYPERV_EVENTFD: {
4778 struct kvm_hyperv_eventfd hvevfd;
4779
4780 r = -EFAULT;
4781 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4782 goto out;
4783 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4784 break;
4785 }
1fe779f8 4786 default:
ad6260da 4787 r = -ENOTTY;
1fe779f8
CO		 4788 }
4789out:
4790 return r;
4791}
4792
a16b043c 4793static void kvm_init_msr_list(void)
043405e1
CO		 4794{
4795 u32 dummy[2];
4796 unsigned i, j;
4797
62ef68bb 4798 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4799 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4800 continue;
93c4adc7
PB		 4801
4802 /*
4803 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4804 * to the guests in some cases.
93c4adc7
PB		 4805 */
4806 switch (msrs_to_save[i]) {
4807 case MSR_IA32_BNDCFGS:
503234b3 4808 if (!kvm_mpx_supported())
93c4adc7
PB		 4809 continue;
4810 break;
9dbe6cf9
PB		 4811 case MSR_TSC_AUX:
4812 if (!kvm_x86_ops->rdtscp_supported())
4813 continue;
4814 break;
93c4adc7
PB		 4815 default:
4816 break;
4817 }
4818
043405e1
CO		 4819 if (j < i)
4820 msrs_to_save[j] = msrs_to_save[i];
4821 j++;
4822 }
4823 num_msrs_to_save = j;
62ef68bb
PB		 4824
4825 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4826 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4827 continue;
62ef68bb
PB		 4828
4829 if (j < i)
4830 emulated_msrs[j] = emulated_msrs[i];
4831 j++;
4832 }
4833 num_emulated_msrs = j;
801e459a
TL		 4834
4835 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4836 struct kvm_msr_entry msr;
4837
4838 msr.index = msr_based_features[i];
66421c1e 4839 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4840 continue;
4841
4842 if (j < i)
4843 msr_based_features[j] = msr_based_features[i];
4844 j++;
4845 }
4846 num_msr_based_features = j;
043405e1
CO		 4847}
4848
bda9020e
MT		 4849static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4850 const void *v)
bbd9b64e 4851{
70252a10
AK		 4852 int handled = 0;
4853 int n;
4854
4855 do {
4856 n = min(len, 8);
bce87cce 4857 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4858 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4859 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4860 break;
4861 handled += n;
4862 addr += n;
4863 len -= n;
4864 v += n;
4865 } while (len);
bbd9b64e 4866
70252a10 4867 return handled;
bbd9b64e
CO		 4868}
4869
bda9020e 4870static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4871{
70252a10
AK		 4872 int handled = 0;
4873 int n;
4874
4875 do {
4876 n = min(len, 8);
bce87cce 4877 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4878 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4879 addr, n, v))
4880 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4881 break;
e39d200f 4882 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4883 handled += n;
4884 addr += n;
4885 len -= n;
4886 v += n;
4887 } while (len);
bbd9b64e 4888
70252a10 4889 return handled;
bbd9b64e
CO		 4890}
4891
2dafc6c2
GN		 4892static void kvm_set_segment(struct kvm_vcpu *vcpu,
4893 struct kvm_segment *var, int seg)
4894{
4895 kvm_x86_ops->set_segment(vcpu, var, seg);
4896}
4897
4898void kvm_get_segment(struct kvm_vcpu *vcpu,
4899 struct kvm_segment *var, int seg)
4900{
4901 kvm_x86_ops->get_segment(vcpu, var, seg);
4902}
4903
54987b7a
PB		 4904gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4905 struct x86_exception *exception)
02f59dc9
JR		 4906{
4907 gpa_t t_gpa;
02f59dc9
JR		 4908
4909 BUG_ON(!mmu_is_nested(vcpu));
4910
4911 /* NPT walks are always user-walks */
4912 access |= PFERR_USER_MASK;
44dd3ffa 4913 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4914
4915 return t_gpa;
4916}
4917
ab9ae313
AK		 4918gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4919 struct x86_exception *exception)
1871c602
GN		 4920{
4921 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4922 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4923}
4924
ab9ae313
AK		 4925 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4926 struct x86_exception *exception)
1871c602
GN		 4927{
4928 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4929 access |= PFERR_FETCH_MASK;
ab9ae313 4930 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4931}
4932
ab9ae313
AK		 4933gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4934 struct x86_exception *exception)
1871c602
GN		 4935{
4936 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4937 access |= PFERR_WRITE_MASK;
ab9ae313 4938 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4939}
4940
4941/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4942gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4943 struct x86_exception *exception)
1871c602 4944{
ab9ae313 4945 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4946}
4947
4948static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4949 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4950 struct x86_exception *exception)
bbd9b64e
CO		 4951{
4952 void *data = val;
10589a46 4953 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4954
4955 while (bytes) {
14dfe855 4956 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4957 exception);
bbd9b64e 4958 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4959 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4960 int ret;
4961
bcc55cba 4962 if (gpa == UNMAPPED_GVA)
ab9ae313 4963 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4964 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4965 offset, toread);
10589a46 4966 if (ret < 0) {
c3cd7ffa 4967 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4968 goto out;
4969 }
bbd9b64e 4970
77c2002e
IE		 4971 bytes -= toread;
4972 data += toread;
4973 addr += toread;
bbd9b64e 4974 }
10589a46 4975out:
10589a46 4976 return r;
bbd9b64e 4977}
77c2002e 4978
1871c602 4979/* used for instruction fetching */
0f65dd70
AK		 4980static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4981 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4982 struct x86_exception *exception)
1871c602 4983{
0f65dd70 4984 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4985 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4986 unsigned offset;
4987 int ret;
0f65dd70 4988
44583cba
PB		 4989 /* Inline kvm_read_guest_virt_helper for speed. */
4990 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4991 exception);
4992 if (unlikely(gpa == UNMAPPED_GVA))
4993 return X86EMUL_PROPAGATE_FAULT;
4994
4995 offset = addr & (PAGE_SIZE-1);
4996 if (WARN_ON(offset + bytes > PAGE_SIZE))
4997 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4998 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4999 offset, bytes);
44583cba
PB		 5000 if (unlikely(ret < 0))
5001 return X86EMUL_IO_NEEDED;
5002
5003 return X86EMUL_CONTINUE;
1871c602
GN		 5004}
5005
ce14e868 5006int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5007 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5008 struct x86_exception *exception)
1871c602
GN		 5009{
5010 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5011
1871c602 5012 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5013 exception);
1871c602 5014}
064aea77 5015EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5016
ce14e868
PB		 5017static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5018 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5019 struct x86_exception *exception, bool system)
1871c602 5020{
0f65dd70 5021 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5022 u32 access = 0;
5023
5024 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5025 access |= PFERR_USER_MASK;
5026
5027 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5028}
5029
7a036a6f
RK		 5030static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5031 unsigned long addr, void *val, unsigned int bytes)
5032{
5033 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5034 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5035
5036 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5037}
5038
ce14e868
PB		 5039static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5040 struct kvm_vcpu *vcpu, u32 access,
5041 struct x86_exception *exception)
77c2002e
IE		 5042{
5043 void *data = val;
5044 int r = X86EMUL_CONTINUE;
5045
5046 while (bytes) {
14dfe855 5047 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5048 access,
ab9ae313 5049 exception);
77c2002e
IE		 5050 unsigned offset = addr & (PAGE_SIZE-1);
5051 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5052 int ret;
5053
bcc55cba 5054 if (gpa == UNMAPPED_GVA)
ab9ae313 5055 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5056 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5057 if (ret < 0) {
c3cd7ffa 5058 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5059 goto out;
5060 }
5061
5062 bytes -= towrite;
5063 data += towrite;
5064 addr += towrite;
5065 }
5066out:
5067 return r;
5068}
ce14e868
PB		 5069
5070static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5071 unsigned int bytes, struct x86_exception *exception,
5072 bool system)
ce14e868
PB		 5073{
5074 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5075 u32 access = PFERR_WRITE_MASK;
5076
5077 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5078 access |= PFERR_USER_MASK;
ce14e868
PB		 5079
5080 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5081 access, exception);
ce14e868
PB		 5082}
5083
5084int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5085 unsigned int bytes, struct x86_exception *exception)
5086{
c595ceee
PB		 5087 /* kvm_write_guest_virt_system can pull in tons of pages. */
5088 vcpu->arch.l1tf_flush_l1d = true;
5089
ce14e868
PB		 5090 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5091 PFERR_WRITE_MASK, exception);
5092}
6a4d7550 5093EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5094
082d06ed
WL		 5095int handle_ud(struct kvm_vcpu *vcpu)
5096{
6c86eedc 5097 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5098 enum emulation_result er;
6c86eedc
WL		 5099 char sig[5]; /* ud2; .ascii "kvm" */
5100 struct x86_exception e;
5101
5102 if (force_emulation_prefix &&
3c9fa24c
PB		 5103 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5104 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5105 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5106 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5107 emul_type = 0;
5108 }
082d06ed 5109
0ce97a2b 5110 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5111 if (er == EMULATE_USER_EXIT)
5112 return 0;
5113 if (er != EMULATE_DONE)
5114 kvm_queue_exception(vcpu, UD_VECTOR);
5115 return 1;
5116}
5117EXPORT_SYMBOL_GPL(handle_ud);
5118
0f89b207
TL		 5119static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5120 gpa_t gpa, bool write)
5121{
5122 /* For APIC access vmexit */
5123 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5124 return 1;
5125
5126 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5127 trace_vcpu_match_mmio(gva, gpa, write, true);
5128 return 1;
5129 }
5130
5131 return 0;
5132}
5133
af7cc7d1
XG		 5134static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5135 gpa_t *gpa, struct x86_exception *exception,
5136 bool write)
5137{
97d64b78
AK		 5138 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5139 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5140
be94f6b7
HH		 5141 /*
5142 * currently PKRU is only applied to ept enabled guest so
5143 * there is no pkey in EPT page table for L1 guest or EPT
5144 * shadow page table for L2 guest.
5145 */
97d64b78 5146 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5147 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5148 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5149 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5150 (gva & (PAGE_SIZE - 1));
4f022648 5151 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5152 return 1;
5153 }
5154
af7cc7d1
XG		 5155 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5156
5157 if (*gpa == UNMAPPED_GVA)
5158 return -1;
5159
0f89b207 5160 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5161}
5162
3200f405 5163int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5164 const void *val, int bytes)
bbd9b64e
CO		 5165{
5166 int ret;
5167
54bf36aa 5168 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5169 if (ret < 0)
bbd9b64e 5170 return 0;
0eb05bf2 5171 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5172 return 1;
5173}
5174
77d197b2
XG		 5175struct read_write_emulator_ops {
5176 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5177 int bytes);
5178 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5179 void *val, int bytes);
5180 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5181 int bytes, void *val);
5182 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5183 void *val, int bytes);
5184 bool write;
5185};
5186
5187static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5188{
5189 if (vcpu->mmio_read_completed) {
77d197b2 5190 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5191 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5192 vcpu->mmio_read_completed = 0;
5193 return 1;
5194 }
5195
5196 return 0;
5197}
5198
5199static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5200 void *val, int bytes)
5201{
54bf36aa 5202 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5203}
5204
5205static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5206 void *val, int bytes)
5207{
5208 return emulator_write_phys(vcpu, gpa, val, bytes);
5209}
5210
5211static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5212{
e39d200f 5213 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5214 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5215}
5216
5217static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5218 void *val, int bytes)
5219{
e39d200f 5220 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5221 return X86EMUL_IO_NEEDED;
5222}
5223
5224static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5225 void *val, int bytes)
5226{
f78146b0
AK		 5227 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5228
87da7e66 5229 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5230 return X86EMUL_CONTINUE;
5231}
5232
0fbe9b0b 5233static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5234 .read_write_prepare = read_prepare,
5235 .read_write_emulate = read_emulate,
5236 .read_write_mmio = vcpu_mmio_read,
5237 .read_write_exit_mmio = read_exit_mmio,
5238};
5239
0fbe9b0b 5240static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5241 .read_write_emulate = write_emulate,
5242 .read_write_mmio = write_mmio,
5243 .read_write_exit_mmio = write_exit_mmio,
5244 .write = true,
5245};
5246
22388a3c
XG		 5247static int emulator_read_write_onepage(unsigned long addr, void *val,
5248 unsigned int bytes,
5249 struct x86_exception *exception,
5250 struct kvm_vcpu *vcpu,
0fbe9b0b 5251 const struct read_write_emulator_ops *ops)
bbd9b64e 5252{
af7cc7d1
XG		 5253 gpa_t gpa;
5254 int handled, ret;
22388a3c 5255 bool write = ops->write;
f78146b0 5256 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5257 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5258
5259 /*
5260 * If the exit was due to a NPF we may already have a GPA.
5261 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5262 * Note, this cannot be used on string operations since string
5263 * operation using rep will only have the initial GPA from the NPF
5264 * occurred.
5265 */
5266 if (vcpu->arch.gpa_available &&
5267 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5268 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5269 gpa = vcpu->arch.gpa_val;
5270 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5271 } else {
5272 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5273 if (ret < 0)
5274 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5275 }
10589a46 5276
618232e2 5277 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5278 return X86EMUL_CONTINUE;
5279
bbd9b64e
CO		 5280 /*
5281 * Is this MMIO handled locally?
5282 */
22388a3c 5283 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5284 if (handled == bytes)
bbd9b64e 5285 return X86EMUL_CONTINUE;
bbd9b64e 5286
70252a10
AK		 5287 gpa += handled;
5288 bytes -= handled;
5289 val += handled;
5290
87da7e66
XG		 5291 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5292 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5293 frag->gpa = gpa;
5294 frag->data = val;
5295 frag->len = bytes;
f78146b0 5296 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5297}
5298
52eb5a6d
XL		 5299static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5300 unsigned long addr,
22388a3c
XG		 5301 void *val, unsigned int bytes,
5302 struct x86_exception *exception,
0fbe9b0b 5303 const struct read_write_emulator_ops *ops)
bbd9b64e 5304{
0f65dd70 5305 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5306 gpa_t gpa;
5307 int rc;
5308
5309 if (ops->read_write_prepare &&
5310 ops->read_write_prepare(vcpu, val, bytes))
5311 return X86EMUL_CONTINUE;
5312
5313 vcpu->mmio_nr_fragments = 0;
0f65dd70 5314
bbd9b64e
CO		 5315 /* Crossing a page boundary? */
5316 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5317 int now;
bbd9b64e
CO		 5318
5319 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5320 rc = emulator_read_write_onepage(addr, val, now, exception,
5321 vcpu, ops);
5322
bbd9b64e
CO		 5323 if (rc != X86EMUL_CONTINUE)
5324 return rc;
5325 addr += now;
bac15531
NA		 5326 if (ctxt->mode != X86EMUL_MODE_PROT64)
5327 addr = (u32)addr;
bbd9b64e
CO		 5328 val += now;
5329 bytes -= now;
5330 }
22388a3c 5331
f78146b0
AK		 5332 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5333 vcpu, ops);
5334 if (rc != X86EMUL_CONTINUE)
5335 return rc;
5336
5337 if (!vcpu->mmio_nr_fragments)
5338 return rc;
5339
5340 gpa = vcpu->mmio_fragments[0].gpa;
5341
5342 vcpu->mmio_needed = 1;
5343 vcpu->mmio_cur_fragment = 0;
5344
87da7e66 5345 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5346 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5347 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5348 vcpu->run->mmio.phys_addr = gpa;
5349
5350 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5351}
5352
5353static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5354 unsigned long addr,
5355 void *val,
5356 unsigned int bytes,
5357 struct x86_exception *exception)
5358{
5359 return emulator_read_write(ctxt, addr, val, bytes,
5360 exception, &read_emultor);
5361}
5362
52eb5a6d 5363static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5364 unsigned long addr,
5365 const void *val,
5366 unsigned int bytes,
5367 struct x86_exception *exception)
5368{
5369 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5370 exception, &write_emultor);
bbd9b64e 5371}
bbd9b64e 5372
daea3e73
AK		 5373#define CMPXCHG_TYPE(t, ptr, old, new) \
5374 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5375
5376#ifdef CONFIG_X86_64
5377# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5378#else
5379# define CMPXCHG64(ptr, old, new) \
9749a6c0 5380 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5381#endif
5382
0f65dd70
AK		 5383static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5384 unsigned long addr,
bbd9b64e
CO		 5385 const void *old,
5386 const void *new,
5387 unsigned int bytes,
0f65dd70 5388 struct x86_exception *exception)
bbd9b64e 5389{
0f65dd70 5390 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5391 gpa_t gpa;
5392 struct page *page;
5393 char *kaddr;
5394 bool exchanged;
2bacc55c 5395
daea3e73
AK		 5396 /* guests cmpxchg8b have to be emulated atomically */
5397 if (bytes > 8 || (bytes & (bytes - 1)))
5398 goto emul_write;
10589a46 5399
daea3e73 5400 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5401
daea3e73
AK		 5402 if (gpa == UNMAPPED_GVA ||
5403 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5404 goto emul_write;
2bacc55c 5405
daea3e73
AK		 5406 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5407 goto emul_write;
72dc67a6 5408
54bf36aa 5409 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5410 if (is_error_page(page))
c19b8bd6 5411 goto emul_write;
72dc67a6 5412
8fd75e12 5413 kaddr = kmap_atomic(page);
daea3e73
AK		 5414 kaddr += offset_in_page(gpa);
5415 switch (bytes) {
5416 case 1:
5417 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5418 break;
5419 case 2:
5420 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5421 break;
5422 case 4:
5423 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5424 break;
5425 case 8:
5426 exchanged = CMPXCHG64(kaddr, old, new);
5427 break;
5428 default:
5429 BUG();
2bacc55c 5430 }
8fd75e12 5431 kunmap_atomic(kaddr);
daea3e73
AK		 5432 kvm_release_page_dirty(page);
5433
5434 if (!exchanged)
5435 return X86EMUL_CMPXCHG_FAILED;
5436
54bf36aa 5437 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5438 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5439
5440 return X86EMUL_CONTINUE;
4a5f48f6 5441
3200f405 5442emul_write:
daea3e73 5443 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5444
0f65dd70 5445 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5446}
5447
cf8f70bf
GN		 5448static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5449{
cbfc6c91 5450 int r = 0, i;
cf8f70bf 5451
cbfc6c91
WL		 5452 for (i = 0; i < vcpu->arch.pio.count; i++) {
5453 if (vcpu->arch.pio.in)
5454 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5455 vcpu->arch.pio.size, pd);
5456 else
5457 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5458 vcpu->arch.pio.port, vcpu->arch.pio.size,
5459 pd);
5460 if (r)
5461 break;
5462 pd += vcpu->arch.pio.size;
5463 }
cf8f70bf
GN		 5464 return r;
5465}
5466
6f6fbe98
XG		 5467static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5468 unsigned short port, void *val,
5469 unsigned int count, bool in)
cf8f70bf 5470{
cf8f70bf 5471 vcpu->arch.pio.port = port;
6f6fbe98 5472 vcpu->arch.pio.in = in;
7972995b 5473 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5474 vcpu->arch.pio.size = size;
5475
5476 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5477 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5478 return 1;
5479 }
5480
5481 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5482 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5483 vcpu->run->io.size = size;
5484 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5485 vcpu->run->io.count = count;
5486 vcpu->run->io.port = port;
5487
5488 return 0;
5489}
5490
6f6fbe98
XG		 5491static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5492 int size, unsigned short port, void *val,
5493 unsigned int count)
cf8f70bf 5494{
ca1d4a9e 5495 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5496 int ret;
ca1d4a9e 5497
6f6fbe98
XG		 5498 if (vcpu->arch.pio.count)
5499 goto data_avail;
cf8f70bf 5500
cbfc6c91
WL		 5501 memset(vcpu->arch.pio_data, 0, size * count);
5502
6f6fbe98
XG		 5503 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5504 if (ret) {
5505data_avail:
5506 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5507 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5508 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5509 return 1;
5510 }
5511
cf8f70bf
GN		 5512 return 0;
5513}
5514
6f6fbe98
XG		 5515static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5516 int size, unsigned short port,
5517 const void *val, unsigned int count)
5518{
5519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5520
5521 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5522 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5523 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5524}
5525
bbd9b64e
CO		 5526static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5527{
5528 return kvm_x86_ops->get_segment_base(vcpu, seg);
5529}
5530
3cb16fe7 5531static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5532{
3cb16fe7 5533 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5534}
5535
ae6a2375 5536static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5537{
5538 if (!need_emulate_wbinvd(vcpu))
5539 return X86EMUL_CONTINUE;
5540
5541 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5542 int cpu = get_cpu();
5543
5544 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5545 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5546 wbinvd_ipi, NULL, 1);
2eec7343 5547 put_cpu();
f5f48ee1 5548 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5549 } else
5550 wbinvd();
f5f48ee1
SY		 5551 return X86EMUL_CONTINUE;
5552}
5cb56059
JS		 5553
5554int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5555{
6affcbed
KH		 5556 kvm_emulate_wbinvd_noskip(vcpu);
5557 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5558}
f5f48ee1
SY		 5559EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5560
5cb56059
JS		 5561
5562
bcaf5cc5
AK		 5563static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5564{
5cb56059 5565 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5566}
5567
52eb5a6d
XL		 5568static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5569 unsigned long *dest)
bbd9b64e 5570{
16f8a6f9 5571 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5572}
5573
52eb5a6d
XL		 5574static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5575 unsigned long value)
bbd9b64e 5576{
338dbc97 5577
717746e3 5578 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5579}
5580
52a46617 5581static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5582{
52a46617 5583 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5584}
5585
717746e3 5586static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5587{
717746e3 5588 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5589 unsigned long value;
5590
5591 switch (cr) {
5592 case 0:
5593 value = kvm_read_cr0(vcpu);
5594 break;
5595 case 2:
5596 value = vcpu->arch.cr2;
5597 break;
5598 case 3:
9f8fe504 5599 value = kvm_read_cr3(vcpu);
52a46617
GN		 5600 break;
5601 case 4:
5602 value = kvm_read_cr4(vcpu);
5603 break;
5604 case 8:
5605 value = kvm_get_cr8(vcpu);
5606 break;
5607 default:
a737f256 5608 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5609 return 0;
5610 }
5611
5612 return value;
5613}
5614
717746e3 5615static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5616{
717746e3 5617 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5618 int res = 0;
5619
52a46617
GN		 5620 switch (cr) {
5621 case 0:
49a9b07e 5622 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5623 break;
5624 case 2:
5625 vcpu->arch.cr2 = val;
5626 break;
5627 case 3:
2390218b 5628 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5629 break;
5630 case 4:
a83b29c6 5631 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5632 break;
5633 case 8:
eea1cff9 5634 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5635 break;
5636 default:
a737f256 5637 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5638 res = -1;
52a46617 5639 }
0f12244f
GN		 5640
5641 return res;
52a46617
GN		 5642}
5643
717746e3 5644static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5645{
717746e3 5646 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5647}
5648
4bff1e86 5649static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5650{
4bff1e86 5651 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5652}
5653
4bff1e86 5654static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5655{
4bff1e86 5656 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5657}
5658
1ac9d0cf
AK		 5659static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5660{
5661 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5662}
5663
5664static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5665{
5666 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5667}
5668
4bff1e86
AK		 5669static unsigned long emulator_get_cached_segment_base(
5670 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5671{
4bff1e86 5672 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5673}
5674
1aa36616
AK		 5675static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5676 struct desc_struct *desc, u32 *base3,
5677 int seg)
2dafc6c2
GN		 5678{
5679 struct kvm_segment var;
5680
4bff1e86 5681 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5682 *selector = var.selector;
2dafc6c2 5683
378a8b09
GN		 5684 if (var.unusable) {
5685 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5686 if (base3)
5687 *base3 = 0;
2dafc6c2 5688 return false;
378a8b09 5689 }
2dafc6c2
GN		 5690
5691 if (var.g)
5692 var.limit >>= 12;
5693 set_desc_limit(desc, var.limit);
5694 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5695#ifdef CONFIG_X86_64
5696 if (base3)
5697 *base3 = var.base >> 32;
5698#endif
2dafc6c2
GN		 5699 desc->type = var.type;
5700 desc->s = var.s;
5701 desc->dpl = var.dpl;
5702 desc->p = var.present;
5703 desc->avl = var.avl;
5704 desc->l = var.l;
5705 desc->d = var.db;
5706 desc->g = var.g;
5707
5708 return true;
5709}
5710
1aa36616
AK		 5711static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5712 struct desc_struct *desc, u32 base3,
5713 int seg)
2dafc6c2 5714{
4bff1e86 5715 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5716 struct kvm_segment var;
5717
1aa36616 5718 var.selector = selector;
2dafc6c2 5719 var.base = get_desc_base(desc);
5601d05b
GN		 5720#ifdef CONFIG_X86_64
5721 var.base |= ((u64)base3) << 32;
5722#endif
2dafc6c2
GN		 5723 var.limit = get_desc_limit(desc);
5724 if (desc->g)
5725 var.limit = (var.limit << 12) | 0xfff;
5726 var.type = desc->type;
2dafc6c2
GN		 5727 var.dpl = desc->dpl;
5728 var.db = desc->d;
5729 var.s = desc->s;
5730 var.l = desc->l;
5731 var.g = desc->g;
5732 var.avl = desc->avl;
5733 var.present = desc->p;
5734 var.unusable = !var.present;
5735 var.padding = 0;
5736
5737 kvm_set_segment(vcpu, &var, seg);
5738 return;
5739}
5740
717746e3
AK		 5741static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5742 u32 msr_index, u64 *pdata)
5743{
609e36d3
PB		 5744 struct msr_data msr;
5745 int r;
5746
5747 msr.index = msr_index;
5748 msr.host_initiated = false;
5749 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5750 if (r)
5751 return r;
5752
5753 *pdata = msr.data;
5754 return 0;
717746e3
AK		 5755}
5756
5757static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5758 u32 msr_index, u64 data)
5759{
8fe8ab46
WA		 5760 struct msr_data msr;
5761
5762 msr.data = data;
5763 msr.index = msr_index;
5764 msr.host_initiated = false;
5765 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5766}
5767
64d60670
PB		 5768static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5769{
5770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5771
5772 return vcpu->arch.smbase;
5773}
5774
5775static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5776{
5777 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5778
5779 vcpu->arch.smbase = smbase;
5780}
5781
67f4d428
NA		 5782static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5783 u32 pmc)
5784{
c6702c9d 5785 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5786}
5787
222d21aa
AK		 5788static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5789 u32 pmc, u64 *pdata)
5790{
c6702c9d 5791 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5792}
5793
6c3287f7
AK		 5794static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5795{
5796 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5797}
5798
2953538e 5799static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5800 struct x86_instruction_info *info,
c4f035c6
AK		 5801 enum x86_intercept_stage stage)
5802{
2953538e 5803 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5804}
5805
e911eb3b
YZ		 5806static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5807 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5808{
e911eb3b 5809 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5810}
5811
dd856efa
AK		 5812static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5813{
5814 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5815}
5816
5817static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5818{
5819 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5820}
5821
801806d9
NA		 5822static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5823{
5824 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5825}
5826
6ed071f0
LP		 5827static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5828{
5829 return emul_to_vcpu(ctxt)->arch.hflags;
5830}
5831
5832static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5833{
5834 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5835}
5836
0234bf88
LP		 5837static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5838{
5839 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5840}
5841
0225fb50 5842static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5843 .read_gpr = emulator_read_gpr,
5844 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5845 .read_std = emulator_read_std,
5846 .write_std = emulator_write_std,
7a036a6f 5847 .read_phys = kvm_read_guest_phys_system,
1871c602 5848 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5849 .read_emulated = emulator_read_emulated,
5850 .write_emulated = emulator_write_emulated,
5851 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5852 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5853 .pio_in_emulated = emulator_pio_in_emulated,
5854 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5855 .get_segment = emulator_get_segment,
5856 .set_segment = emulator_set_segment,
5951c442 5857 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5858 .get_gdt = emulator_get_gdt,
160ce1f1 5859 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5860 .set_gdt = emulator_set_gdt,
5861 .set_idt = emulator_set_idt,
52a46617
GN		 5862 .get_cr = emulator_get_cr,
5863 .set_cr = emulator_set_cr,
9c537244 5864 .cpl = emulator_get_cpl,
35aa5375
GN		 5865 .get_dr = emulator_get_dr,
5866 .set_dr = emulator_set_dr,
64d60670
PB		 5867 .get_smbase = emulator_get_smbase,
5868 .set_smbase = emulator_set_smbase,
717746e3
AK		 5869 .set_msr = emulator_set_msr,
5870 .get_msr = emulator_get_msr,
67f4d428 5871 .check_pmc = emulator_check_pmc,
222d21aa 5872 .read_pmc = emulator_read_pmc,
6c3287f7 5873 .halt = emulator_halt,
bcaf5cc5 5874 .wbinvd = emulator_wbinvd,
d6aa1000 5875 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5876 .intercept = emulator_intercept,
bdb42f5a 5877 .get_cpuid = emulator_get_cpuid,
801806d9 5878 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5879 .get_hflags = emulator_get_hflags,
5880 .set_hflags = emulator_set_hflags,
0234bf88 5881 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5882};
5883
95cb2295
GN		 5884static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5885{
37ccdcbe 5886 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5887 /*
5888 * an sti; sti; sequence only disable interrupts for the first
5889 * instruction. So, if the last instruction, be it emulated or
5890 * not, left the system with the INT_STI flag enabled, it
5891 * means that the last instruction is an sti. We should not
5892 * leave the flag on in this case. The same goes for mov ss
5893 */
37ccdcbe
PB		 5894 if (int_shadow & mask)
5895 mask = 0;
6addfc42 5896 if (unlikely(int_shadow || mask)) {
95cb2295 5897 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5898 if (!mask)
5899 kvm_make_request(KVM_REQ_EVENT, vcpu);
5900 }
95cb2295
GN		 5901}
5902
ef54bcfe 5903static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5904{
5905 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5906 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5907 return kvm_propagate_fault(vcpu, &ctxt->exception);
5908
5909 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5910 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5911 ctxt->exception.error_code);
54b8486f 5912 else
da9cb575 5913 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5914 return false;
54b8486f
GN		 5915}
5916
8ec4722d
MG		 5917static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5918{
adf52235 5919 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5920 int cs_db, cs_l;
5921
8ec4722d
MG		 5922 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5923
adf52235 5924 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5925 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5926
adf52235
TY		 5927 ctxt->eip = kvm_rip_read(vcpu);
5928 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5929 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5930 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5931 cs_db ? X86EMUL_MODE_PROT32 :
5932 X86EMUL_MODE_PROT16;
a584539b 5933 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5934 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5935 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5936
dd856efa 5937 init_decode_cache(ctxt);
7ae441ea 5938 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5939}
5940
71f9833b 5941int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5942{
9d74191a 5943 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5944 int ret;
5945
5946 init_emulate_ctxt(vcpu);
5947
9dac77fa
AK		 5948 ctxt->op_bytes = 2;
5949 ctxt->ad_bytes = 2;
5950 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5951 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5952
5953 if (ret != X86EMUL_CONTINUE)
5954 return EMULATE_FAIL;
5955
9dac77fa 5956 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5957 kvm_rip_write(vcpu, ctxt->eip);
5958 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5959
63995653
MG		 5960 return EMULATE_DONE;
5961}
5962EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5963
e2366171 5964static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5965{
fc3a9157
JR		 5966 int r = EMULATE_DONE;
5967
6d77dbfc
GN		 5968 ++vcpu->stat.insn_emulation_fail;
5969 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5970
5971 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5972 return EMULATE_FAIL;
5973
a2b9e6c1 5974 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5975 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5976 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5977 vcpu->run->internal.ndata = 0;
1f4dcb3b 5978 r = EMULATE_USER_EXIT;
fc3a9157 5979 }
e2366171 5980
6d77dbfc 5981 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5982
5983 return r;
6d77dbfc
GN		 5984}
5985
93c05d3e 5986static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5987 bool write_fault_to_shadow_pgtable,
5988 int emulation_type)
a6f177ef 5989{
95b3cf69 5990 gpa_t gpa = cr2;
ba049e93 5991 kvm_pfn_t pfn;
a6f177ef 5992
384bf221 5993 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 5994 return false;
5995
6c3dfeb6
SC		 5996 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
5997 return false;
5998
44dd3ffa 5999 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6000 /*
6001 * Write permission should be allowed since only
6002 * write access need to be emulated.
6003 */
6004 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6005
95b3cf69
XG		 6006 /*
6007 * If the mapping is invalid in guest, let cpu retry
6008 * it to generate fault.
6009 */
6010 if (gpa == UNMAPPED_GVA)
6011 return true;
6012 }
a6f177ef 6013
8e3d9d06
XG		 6014 /*
6015 * Do not retry the unhandleable instruction if it faults on the
6016 * readonly host memory, otherwise it will goto a infinite loop:
6017 * retry instruction -> write #PF -> emulation fail -> retry
6018 * instruction -> ...
6019 */
6020 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6021
6022 /*
6023 * If the instruction failed on the error pfn, it can not be fixed,
6024 * report the error to userspace.
6025 */
6026 if (is_error_noslot_pfn(pfn))
6027 return false;
6028
6029 kvm_release_pfn_clean(pfn);
6030
6031 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6032 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6033 unsigned int indirect_shadow_pages;
6034
6035 spin_lock(&vcpu->kvm->mmu_lock);
6036 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6037 spin_unlock(&vcpu->kvm->mmu_lock);
6038
6039 if (indirect_shadow_pages)
6040 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6041
a6f177ef 6042 return true;
8e3d9d06 6043 }
a6f177ef 6044
95b3cf69
XG		 6045 /*
6046 * if emulation was due to access to shadowed page table
6047 * and it failed try to unshadow page and re-enter the
6048 * guest to let CPU execute the instruction.
6049 */
6050 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6051
6052 /*
6053 * If the access faults on its page table, it can not
6054 * be fixed by unprotecting shadow page and it should
6055 * be reported to userspace.
6056 */
6057 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6058}
6059
1cb3f3ae
XG		 6060static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6061 unsigned long cr2, int emulation_type)
6062{
6063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6064 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6065
6066 last_retry_eip = vcpu->arch.last_retry_eip;
6067 last_retry_addr = vcpu->arch.last_retry_addr;
6068
6069 /*
6070 * If the emulation is caused by #PF and it is non-page_table
6071 * writing instruction, it means the VM-EXIT is caused by shadow
6072 * page protected, we can zap the shadow page and retry this
6073 * instruction directly.
6074 *
6075 * Note: if the guest uses a non-page-table modifying instruction
6076 * on the PDE that points to the instruction, then we will unmap
6077 * the instruction and go to an infinite loop. So, we cache the
6078 * last retried eip and the last fault address, if we meet the eip
6079 * and the address again, we can break out of the potential infinite
6080 * loop.
6081 */
6082 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6083
384bf221 6084 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6085 return false;
6086
6c3dfeb6
SC		 6087 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6088 return false;
6089
1cb3f3ae
XG		 6090 if (x86_page_table_writing_insn(ctxt))
6091 return false;
6092
6093 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6094 return false;
6095
6096 vcpu->arch.last_retry_eip = ctxt->eip;
6097 vcpu->arch.last_retry_addr = cr2;
6098
44dd3ffa 6099 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6100 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6101
22368028 6102 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6103
6104 return true;
6105}
6106
716d51ab
GN		 6107static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6108static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6109
64d60670 6110static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6111{
64d60670 6112 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6113 /* This is a good place to trace that we are exiting SMM. */
6114 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6115
c43203ca
PB		 6116 /* Process a latched INIT or SMI, if any. */
6117 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6118 }
699023e2
PB		 6119
6120 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6121}
6122
6123static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6124{
6125 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6126
a584539b 6127 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6128
6129 if (changed & HF_SMM_MASK)
6130 kvm_smm_changed(vcpu);
a584539b
PB		 6131}
6132
4a1e10d5
PB		 6133static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6134 unsigned long *db)
6135{
6136 u32 dr6 = 0;
6137 int i;
6138 u32 enable, rwlen;
6139
6140 enable = dr7;
6141 rwlen = dr7 >> 16;
6142 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6143 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6144 dr6 |= (1 << i);
6145 return dr6;
6146}
6147
c8401dda 6148static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6149{
6150 struct kvm_run *kvm_run = vcpu->run;
6151
c8401dda
PB		 6152 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6153 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6154 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6155 kvm_run->debug.arch.exception = DB_VECTOR;
6156 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6157 *r = EMULATE_USER_EXIT;
6158 } else {
6159 /*
6160 * "Certain debug exceptions may clear bit 0-3. The
6161 * remaining contents of the DR6 register are never
6162 * cleared by the processor".
6163 */
6164 vcpu->arch.dr6 &= ~15;
6165 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
6166 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 6167 }
6168}
6169
6affcbed
KH		 6170int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6171{
6172 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6173 int r = EMULATE_DONE;
6174
6175 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6176
6177 /*
6178 * rflags is the old, "raw" value of the flags. The new value has
6179 * not been saved yet.
6180 *
6181 * This is correct even for TF set by the guest, because "the
6182 * processor will not generate this exception after the instruction
6183 * that sets the TF flag".
6184 */
6185 if (unlikely(rflags & X86_EFLAGS_TF))
6186 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6187 return r == EMULATE_DONE;
6188}
6189EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6190
4a1e10d5
PB		 6191static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6192{
4a1e10d5
PB		 6193 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6194 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6195 struct kvm_run *kvm_run = vcpu->run;
6196 unsigned long eip = kvm_get_linear_rip(vcpu);
6197 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6198 vcpu->arch.guest_debug_dr7,
6199 vcpu->arch.eff_db);
6200
6201 if (dr6 != 0) {
6f43ed01 6202 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6203 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6204 kvm_run->debug.arch.exception = DB_VECTOR;
6205 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6206 *r = EMULATE_USER_EXIT;
6207 return true;
6208 }
6209 }
6210
4161a569
NA		 6211 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6212 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6213 unsigned long eip = kvm_get_linear_rip(vcpu);
6214 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6215 vcpu->arch.dr7,
6216 vcpu->arch.db);
6217
6218 if (dr6 != 0) {
6219 vcpu->arch.dr6 &= ~15;
6f43ed01 6220 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6221 kvm_queue_exception(vcpu, DB_VECTOR);
6222 *r = EMULATE_DONE;
6223 return true;
6224 }
6225 }
6226
6227 return false;
6228}
6229
04789b66
LA		 6230static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6231{
2d7921c4
AM		 6232 switch (ctxt->opcode_len) {
6233 case 1:
6234 switch (ctxt->b) {
6235 case 0xe4: /* IN */
6236 case 0xe5:
6237 case 0xec:
6238 case 0xed:
6239 case 0xe6: /* OUT */
6240 case 0xe7:
6241 case 0xee:
6242 case 0xef:
6243 case 0x6c: /* INS */
6244 case 0x6d:
6245 case 0x6e: /* OUTS */
6246 case 0x6f:
6247 return true;
6248 }
6249 break;
6250 case 2:
6251 switch (ctxt->b) {
6252 case 0x33: /* RDPMC */
6253 return true;
6254 }
6255 break;
04789b66
LA		 6256 }
6257
6258 return false;
6259}
6260
51d8b661
AP		 6261int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6262 unsigned long cr2,
dc25e89e
AP		 6263 int emulation_type,
6264 void *insn,
6265 int insn_len)
bbd9b64e 6266{
95cb2295 6267 int r;
9d74191a 6268 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6269 bool writeback = true;
93c05d3e 6270 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6271
c595ceee
PB		 6272 vcpu->arch.l1tf_flush_l1d = true;
6273
93c05d3e
XG		 6274 /*
6275 * Clear write_fault_to_shadow_pgtable here to ensure it is
6276 * never reused.
6277 */
6278 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6279 kvm_clear_exception_queue(vcpu);
8d7d8102 6280
571008da 6281 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6282 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6283
6284 /*
6285 * We will reenter on the same instruction since
6286 * we do not set complete_userspace_io. This does not
6287 * handle watchpoints yet, those would be handled in
6288 * the emulate_ops.
6289 */
d391f120
VK		 6290 if (!(emulation_type & EMULTYPE_SKIP) &&
6291 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6292 return r;
6293
9d74191a
TY		 6294 ctxt->interruptibility = 0;
6295 ctxt->have_exception = false;
e0ad0b47 6296 ctxt->exception.vector = -1;
9d74191a 6297 ctxt->perm_ok = false;
bbd9b64e 6298
b51e974f 6299 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6300
9d74191a 6301 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6302
e46479f8 6303 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6304 ++vcpu->stat.insn_emulation;
1d2887e2 6305 if (r != EMULATION_OK) {
4005996e
AK		 6306 if (emulation_type & EMULTYPE_TRAP_UD)
6307 return EMULATE_FAIL;
991eebf9
GN		 6308 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6309 emulation_type))
bbd9b64e 6310 return EMULATE_DONE;
6ea6e843
PB		 6311 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6312 return EMULATE_DONE;
6d77dbfc
GN		 6313 if (emulation_type & EMULTYPE_SKIP)
6314 return EMULATE_FAIL;
e2366171 6315 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6316 }
6317 }
6318
04789b66
LA		 6319 if ((emulation_type & EMULTYPE_VMWARE) &&
6320 !is_vmware_backdoor_opcode(ctxt))
6321 return EMULATE_FAIL;
6322
ba8afb6b 6323 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6324 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6325 if (ctxt->eflags & X86_EFLAGS_RF)
6326 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6327 return EMULATE_DONE;
6328 }
6329
1cb3f3ae
XG		 6330 if (retry_instruction(ctxt, cr2, emulation_type))
6331 return EMULATE_DONE;
6332
7ae441ea 6333 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6334 changes registers values during IO operation */
7ae441ea
GN		 6335 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6336 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6337 emulator_invalidate_register_cache(ctxt);
7ae441ea 6338 }
4d2179e1 6339
5cd21917 6340restart:
0f89b207
TL		 6341 /* Save the faulting GPA (cr2) in the address field */
6342 ctxt->exception.address = cr2;
6343
9d74191a 6344 r = x86_emulate_insn(ctxt);
bbd9b64e 6345
775fde86
JR		 6346 if (r == EMULATION_INTERCEPTED)
6347 return EMULATE_DONE;
6348
d2ddd1c4 6349 if (r == EMULATION_FAILED) {
991eebf9
GN		 6350 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6351 emulation_type))
c3cd7ffa
GN		 6352 return EMULATE_DONE;
6353
e2366171 6354 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6355 }
6356
9d74191a 6357 if (ctxt->have_exception) {
d2ddd1c4 6358 r = EMULATE_DONE;
ef54bcfe
PB		 6359 if (inject_emulated_exception(vcpu))
6360 return r;
d2ddd1c4 6361 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6362 if (!vcpu->arch.pio.in) {
6363 /* FIXME: return into emulator if single-stepping. */
3457e419 6364 vcpu->arch.pio.count = 0;
0912c977 6365 } else {
7ae441ea 6366 writeback = false;
716d51ab
GN		 6367 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6368 }
ac0a48c3 6369 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6370 } else if (vcpu->mmio_needed) {
6371 if (!vcpu->mmio_is_write)
6372 writeback = false;
ac0a48c3 6373 r = EMULATE_USER_EXIT;
716d51ab 6374 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6375 } else if (r == EMULATION_RESTART)
5cd21917 6376 goto restart;
d2ddd1c4
GN		 6377 else
6378 r = EMULATE_DONE;
f850e2e6 6379
7ae441ea 6380 if (writeback) {
6addfc42 6381 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6382 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6383 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6384 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6385 if (r == EMULATE_DONE &&
6386 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6387 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6388 if (!ctxt->have_exception ||
6389 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6390 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6391
6392 /*
6393 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6394 * do nothing, and it will be requested again as soon as
6395 * the shadow expires. But we still need to check here,
6396 * because POPF has no interrupt shadow.
6397 */
6398 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6399 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6400 } else
6401 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6402
6403 return r;
de7d789a 6404}
c60658d1
SC		 6405
6406int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6407{
6408 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6409}
6410EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6411
6412int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6413 void *insn, int insn_len)
6414{
6415 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6416}
6417EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6418
dca7f128
SC		 6419static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6420 unsigned short port)
de7d789a 6421{
cf8f70bf 6422 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6423 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6424 size, port, &val, 1);
cf8f70bf 6425 /* do not return to emulator after return from userspace */
7972995b 6426 vcpu->arch.pio.count = 0;
de7d789a
CO		 6427 return ret;
6428}
de7d789a 6429
8370c3d0
TL		 6430static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6431{
6432 unsigned long val;
6433
6434 /* We should only ever be called with arch.pio.count equal to 1 */
6435 BUG_ON(vcpu->arch.pio.count != 1);
6436
6437 /* For size less than 4 we merge, else we zero extend */
6438 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6439 : 0;
6440
6441 /*
6442 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6443 * the copy and tracing
6444 */
6445 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6446 vcpu->arch.pio.port, &val, 1);
6447 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6448
6449 return 1;
6450}
6451
dca7f128
SC		 6452static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6453 unsigned short port)
8370c3d0
TL		 6454{
6455 unsigned long val;
6456 int ret;
6457
6458 /* For size less than 4 we merge, else we zero extend */
6459 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6460
6461 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6462 &val, 1);
6463 if (ret) {
6464 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6465 return ret;
6466 }
6467
6468 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6469
6470 return 0;
6471}
dca7f128
SC		 6472
6473int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6474{
6475 int ret = kvm_skip_emulated_instruction(vcpu);
6476
6477 /*
6478 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6479 * KVM_EXIT_DEBUG here.
6480 */
6481 if (in)
6482 return kvm_fast_pio_in(vcpu, size, port) && ret;
6483 else
6484 return kvm_fast_pio_out(vcpu, size, port) && ret;
6485}
6486EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6487
251a5fd6 6488static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6489{
0a3aee0d 6490 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6491 return 0;
8cfdc000
ZA		 6492}
6493
6494static void tsc_khz_changed(void *data)
c8076604 6495{
8cfdc000
ZA		 6496 struct cpufreq_freqs *freq = data;
6497 unsigned long khz = 0;
6498
6499 if (data)
6500 khz = freq->new;
6501 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6502 khz = cpufreq_quick_get(raw_smp_processor_id());
6503 if (!khz)
6504 khz = tsc_khz;
0a3aee0d 6505 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6506}
6507
5fa4ec9c 6508#ifdef CONFIG_X86_64
0092e434
VK		 6509static void kvm_hyperv_tsc_notifier(void)
6510{
0092e434
VK		 6511 struct kvm *kvm;
6512 struct kvm_vcpu *vcpu;
6513 int cpu;
6514
6515 spin_lock(&kvm_lock);
6516 list_for_each_entry(kvm, &vm_list, vm_list)
6517 kvm_make_mclock_inprogress_request(kvm);
6518
6519 hyperv_stop_tsc_emulation();
6520
6521 /* TSC frequency always matches when on Hyper-V */
6522 for_each_present_cpu(cpu)
6523 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6524 kvm_max_guest_tsc_khz = tsc_khz;
6525
6526 list_for_each_entry(kvm, &vm_list, vm_list) {
6527 struct kvm_arch *ka = &kvm->arch;
6528
6529 spin_lock(&ka->pvclock_gtod_sync_lock);
6530
6531 pvclock_update_vm_gtod_copy(kvm);
6532
6533 kvm_for_each_vcpu(cpu, vcpu, kvm)
6534 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6535
6536 kvm_for_each_vcpu(cpu, vcpu, kvm)
6537 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6538
6539 spin_unlock(&ka->pvclock_gtod_sync_lock);
6540 }
6541 spin_unlock(&kvm_lock);
0092e434 6542}
5fa4ec9c 6543#endif
0092e434 6544
c8076604
GH		 6545static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6546 void *data)
6547{
6548 struct cpufreq_freqs *freq = data;
6549 struct kvm *kvm;
6550 struct kvm_vcpu *vcpu;
6551 int i, send_ipi = 0;
6552
8cfdc000
ZA		 6553 /*
6554 * We allow guests to temporarily run on slowing clocks,
6555 * provided we notify them after, or to run on accelerating
6556 * clocks, provided we notify them before. Thus time never
6557 * goes backwards.
6558 *
6559 * However, we have a problem. We can't atomically update
6560 * the frequency of a given CPU from this function; it is
6561 * merely a notifier, which can be called from any CPU.
6562 * Changing the TSC frequency at arbitrary points in time
6563 * requires a recomputation of local variables related to
6564 * the TSC for each VCPU. We must flag these local variables
6565 * to be updated and be sure the update takes place with the
6566 * new frequency before any guests proceed.
6567 *
6568 * Unfortunately, the combination of hotplug CPU and frequency
6569 * change creates an intractable locking scenario; the order
6570 * of when these callouts happen is undefined with respect to
6571 * CPU hotplug, and they can race with each other. As such,
6572 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6573 * undefined; you can actually have a CPU frequency change take
6574 * place in between the computation of X and the setting of the
6575 * variable. To protect against this problem, all updates of
6576 * the per_cpu tsc_khz variable are done in an interrupt
6577 * protected IPI, and all callers wishing to update the value
6578 * must wait for a synchronous IPI to complete (which is trivial
6579 * if the caller is on the CPU already). This establishes the
6580 * necessary total order on variable updates.
6581 *
6582 * Note that because a guest time update may take place
6583 * anytime after the setting of the VCPU's request bit, the
6584 * correct TSC value must be set before the request. However,
6585 * to ensure the update actually makes it to any guest which
6586 * starts running in hardware virtualization between the set
6587 * and the acquisition of the spinlock, we must also ping the
6588 * CPU after setting the request bit.
6589 *
6590 */
6591
c8076604
GH		 6592 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6593 return 0;
6594 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6595 return 0;
8cfdc000
ZA		 6596
6597 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6598
2f303b74 6599 spin_lock(&kvm_lock);
c8076604 6600 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6601 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6602 if (vcpu->cpu != freq->cpu)
6603 continue;
c285545f 6604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6605 if (vcpu->cpu != smp_processor_id())
8cfdc000 6606 send_ipi = 1;
c8076604
GH		 6607 }
6608 }
2f303b74 6609 spin_unlock(&kvm_lock);
c8076604
GH		 6610
6611 if (freq->old < freq->new && send_ipi) {
6612 /*
6613 * We upscale the frequency. Must make the guest
6614 * doesn't see old kvmclock values while running with
6615 * the new frequency, otherwise we risk the guest sees
6616 * time go backwards.
6617 *
6618 * In case we update the frequency for another cpu
6619 * (which might be in guest context) send an interrupt
6620 * to kick the cpu out of guest context. Next time
6621 * guest context is entered kvmclock will be updated,
6622 * so the guest will not see stale values.
6623 */
8cfdc000 6624 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6625 }
6626 return 0;
6627}
6628
6629static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6630 .notifier_call = kvmclock_cpufreq_notifier
6631};
6632
251a5fd6 6633static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6634{
251a5fd6
SAS		 6635 tsc_khz_changed(NULL);
6636 return 0;
8cfdc000
ZA		 6637}
6638
b820cc0c
ZA		 6639static void kvm_timer_init(void)
6640{
c285545f 6641 max_tsc_khz = tsc_khz;
460dd42e 6642
b820cc0c 6643 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6644#ifdef CONFIG_CPU_FREQ
6645 struct cpufreq_policy policy;
758f588d
BP		 6646 int cpu;
6647
c285545f 6648 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6649 cpu = get_cpu();
6650 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6651 if (policy.cpuinfo.max_freq)
6652 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6653 put_cpu();
c285545f 6654#endif
b820cc0c
ZA		 6655 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6656 CPUFREQ_TRANSITION_NOTIFIER);
6657 }
c285545f 6658 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6659
73c1b41e 6660 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6661 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6662}
6663
dd60d217
AK		 6664DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6665EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6666
f5132b01 6667int kvm_is_in_guest(void)
ff9d07a0 6668{
086c9855 6669 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6670}
6671
6672static int kvm_is_user_mode(void)
6673{
6674 int user_mode = 3;
dcf46b94 6675
086c9855
AS		 6676 if (__this_cpu_read(current_vcpu))
6677 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6678
ff9d07a0
ZY		 6679 return user_mode != 0;
6680}
6681
6682static unsigned long kvm_get_guest_ip(void)
6683{
6684 unsigned long ip = 0;
dcf46b94 6685
086c9855
AS		 6686 if (__this_cpu_read(current_vcpu))
6687 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6688
ff9d07a0
ZY		 6689 return ip;
6690}
6691
6692static struct perf_guest_info_callbacks kvm_guest_cbs = {
6693 .is_in_guest = kvm_is_in_guest,
6694 .is_user_mode = kvm_is_user_mode,
6695 .get_guest_ip = kvm_get_guest_ip,
6696};
6697
ce88decf
XG		 6698static void kvm_set_mmio_spte_mask(void)
6699{
6700 u64 mask;
6701 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6702
6703 /*
6704 * Set the reserved bits and the present bit of an paging-structure
6705 * entry to generate page fault with PFER.RSV = 1.
6706 */
28a1f3ac
JS		 6707
6708 /*
6709 * Mask the uppermost physical address bit, which would be reserved as
6710 * long as the supported physical address width is less than 52.
6711 */
6712 mask = 1ull << 51;
885032b9 6713
885032b9 6714 /* Set the present bit. */
ce88decf
XG		 6715 mask |= 1ull;
6716
ce88decf
XG		 6717 /*
6718 * If reserved bit is not supported, clear the present bit to disable
6719 * mmio page fault.
6720 */
7288bde1 6721 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6722 mask &= ~1ull;
ce88decf 6723
dcdca5fe 6724 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6725}
6726
16e8d74d
MT		 6727#ifdef CONFIG_X86_64
6728static void pvclock_gtod_update_fn(struct work_struct *work)
6729{
d828199e
MT		 6730 struct kvm *kvm;
6731
6732 struct kvm_vcpu *vcpu;
6733 int i;
6734
2f303b74 6735 spin_lock(&kvm_lock);
d828199e
MT		 6736 list_for_each_entry(kvm, &vm_list, vm_list)
6737 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6738 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6739 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6740 spin_unlock(&kvm_lock);
16e8d74d
MT		 6741}
6742
6743static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6744
6745/*
6746 * Notification about pvclock gtod data update.
6747 */
6748static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6749 void *priv)
6750{
6751 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6752 struct timekeeper *tk = priv;
6753
6754 update_pvclock_gtod(tk);
6755
6756 /* disable master clock if host does not trust, or does not
b0c39dc6 6757 * use, TSC based clocksource.
16e8d74d 6758 */
b0c39dc6 6759 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6760 atomic_read(&kvm_guest_has_master_clock) != 0)
6761 queue_work(system_long_wq, &pvclock_gtod_work);
6762
6763 return 0;
6764}
6765
6766static struct notifier_block pvclock_gtod_notifier = {
6767 .notifier_call = pvclock_gtod_notify,
6768};
6769#endif
6770
f8c16bba 6771int kvm_arch_init(void *opaque)
043405e1 6772{
b820cc0c 6773 int r;
6b61edf7 6774 struct kvm_x86_ops *ops = opaque;
f8c16bba 6775
f8c16bba
ZX		 6776 if (kvm_x86_ops) {
6777 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6778 r = -EEXIST;
6779 goto out;
f8c16bba
ZX		 6780 }
6781
6782 if (!ops->cpu_has_kvm_support()) {
6783 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6784 r = -EOPNOTSUPP;
6785 goto out;
f8c16bba
ZX		 6786 }
6787 if (ops->disabled_by_bios()) {
6788 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6789 r = -EOPNOTSUPP;
6790 goto out;
f8c16bba
ZX		 6791 }
6792
013f6a5d
MT		 6793 r = -ENOMEM;
6794 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6795 if (!shared_msrs) {
6796 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6797 goto out;
6798 }
6799
97db56ce
AK		 6800 r = kvm_mmu_module_init();
6801 if (r)
013f6a5d 6802 goto out_free_percpu;
97db56ce 6803
ce88decf 6804 kvm_set_mmio_spte_mask();
97db56ce 6805
f8c16bba 6806 kvm_x86_ops = ops;
920c8377 6807
7b52345e 6808 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6809 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6810 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6811 kvm_timer_init();
c8076604 6812
ff9d07a0
ZY		 6813 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6814
d366bf7e 6815 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6816 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6817
c5cc421b 6818 kvm_lapic_init();
16e8d74d
MT		 6819#ifdef CONFIG_X86_64
6820 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6821
5fa4ec9c 6822 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6823 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6824#endif
6825
f8c16bba 6826 return 0;
56c6d28a 6827
013f6a5d
MT		 6828out_free_percpu:
6829 free_percpu(shared_msrs);
56c6d28a 6830out:
56c6d28a 6831 return r;
043405e1 6832}
8776e519 6833
f8c16bba
ZX		 6834void kvm_arch_exit(void)
6835{
0092e434 6836#ifdef CONFIG_X86_64
5fa4ec9c 6837 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6838 clear_hv_tscchange_cb();
6839#endif
cef84c30 6840 kvm_lapic_exit();
ff9d07a0
ZY		 6841 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6842
888d256e
JK		 6843 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6844 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6845 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6846 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6847#ifdef CONFIG_X86_64
6848 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6849#endif
f8c16bba 6850 kvm_x86_ops = NULL;
56c6d28a 6851 kvm_mmu_module_exit();
013f6a5d 6852 free_percpu(shared_msrs);
56c6d28a 6853}
f8c16bba 6854
5cb56059 6855int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6856{
6857 ++vcpu->stat.halt_exits;
35754c98 6858 if (lapic_in_kernel(vcpu)) {
a4535290 6859 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6860 return 1;
6861 } else {
6862 vcpu->run->exit_reason = KVM_EXIT_HLT;
6863 return 0;
6864 }
6865}
5cb56059
JS		 6866EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6867
6868int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6869{
6affcbed
KH		 6870 int ret = kvm_skip_emulated_instruction(vcpu);
6871 /*
6872 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6873 * KVM_EXIT_DEBUG here.
6874 */
6875 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6876}
8776e519
HB		 6877EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6878
8ef81a9a 6879#ifdef CONFIG_X86_64
55dd00a7
MT		 6880static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6881 unsigned long clock_type)
6882{
6883 struct kvm_clock_pairing clock_pairing;
899a31f5 6884 struct timespec64 ts;
80fbd89c 6885 u64 cycle;
55dd00a7
MT		 6886 int ret;
6887
6888 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6889 return -KVM_EOPNOTSUPP;
6890
6891 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6892 return -KVM_EOPNOTSUPP;
6893
6894 clock_pairing.sec = ts.tv_sec;
6895 clock_pairing.nsec = ts.tv_nsec;
6896 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6897 clock_pairing.flags = 0;
6898
6899 ret = 0;
6900 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6901 sizeof(struct kvm_clock_pairing)))
6902 ret = -KVM_EFAULT;
6903
6904 return ret;
6905}
8ef81a9a 6906#endif
55dd00a7 6907
6aef266c
SV		 6908/*
6909 * kvm_pv_kick_cpu_op: Kick a vcpu.
6910 *
6911 * @apicid - apicid of vcpu to be kicked.
6912 */
6913static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6914{
24d2166b 6915 struct kvm_lapic_irq lapic_irq;
6aef266c 6916
24d2166b
R		 6917 lapic_irq.shorthand = 0;
6918 lapic_irq.dest_mode = 0;
ebd28fcb 6919 lapic_irq.level = 0;
24d2166b 6920 lapic_irq.dest_id = apicid;
93bbf0b8 6921 lapic_irq.msi_redir_hint = false;
6aef266c 6922
24d2166b 6923 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6924 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6925}
6926
d62caabb
AS		 6927void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6928{
6929 vcpu->arch.apicv_active = false;
6930 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6931}
6932
8776e519
HB		 6933int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6934{
6935 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6936 int op_64_bit;
8776e519 6937
696ca779
RK		 6938 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6939 return kvm_hv_hypercall(vcpu);
55cd8e5a 6940
5fdbf976
MT		 6941 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6942 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6943 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6944 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6945 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6946
229456fc 6947 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6948
a449c7aa
NA		 6949 op_64_bit = is_64_bit_mode(vcpu);
6950 if (!op_64_bit) {
8776e519
HB		 6951 nr &= 0xFFFFFFFF;
6952 a0 &= 0xFFFFFFFF;
6953 a1 &= 0xFFFFFFFF;
6954 a2 &= 0xFFFFFFFF;
6955 a3 &= 0xFFFFFFFF;
6956 }
6957
07708c4a
JK		 6958 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6959 ret = -KVM_EPERM;
696ca779 6960 goto out;
07708c4a
JK		 6961 }
6962
8776e519 6963 switch (nr) {
b93463aa
AK		 6964 case KVM_HC_VAPIC_POLL_IRQ:
6965 ret = 0;
6966 break;
6aef266c
SV		 6967 case KVM_HC_KICK_CPU:
6968 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6969 ret = 0;
6970 break;
8ef81a9a 6971#ifdef CONFIG_X86_64
55dd00a7
MT		 6972 case KVM_HC_CLOCK_PAIRING:
6973 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6974 break;
4180bf1b
WL		 6975 case KVM_HC_SEND_IPI:
6976 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
6977 break;
8ef81a9a 6978#endif
8776e519
HB		 6979 default:
6980 ret = -KVM_ENOSYS;
6981 break;
6982 }
696ca779 6983out:
a449c7aa
NA		 6984 if (!op_64_bit)
6985 ret = (u32)ret;
5fdbf976 6986 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 6987
f11c3a8d 6988 ++vcpu->stat.hypercalls;
6356ee0c 6989 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6990}
6991EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6992
b6785def 6993static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6994{
d6aa1000 6995 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6996 char instruction[3];
5fdbf976 6997 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6998
8776e519 6999 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7000
ce2e852e
DV		 7001 return emulator_write_emulated(ctxt, rip, instruction, 3,
7002 &ctxt->exception);
8776e519
HB		 7003}
7004
851ba692 7005static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7006{
782d422b
MG		 7007 return vcpu->run->request_interrupt_window &&
7008 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7009}
7010
851ba692 7011static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7012{
851ba692
AK		 7013 struct kvm_run *kvm_run = vcpu->run;
7014
91586a3b 7015 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7016 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7017 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7018 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7019 kvm_run->ready_for_interrupt_injection =
7020 pic_in_kernel(vcpu->kvm) ||
782d422b 7021 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7022}
7023
95ba8273
GN		 7024static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7025{
7026 int max_irr, tpr;
7027
7028 if (!kvm_x86_ops->update_cr8_intercept)
7029 return;
7030
bce87cce 7031 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7032 return;
7033
d62caabb
AS		 7034 if (vcpu->arch.apicv_active)
7035 return;
7036
8db3baa2
GN		 7037 if (!vcpu->arch.apic->vapic_addr)
7038 max_irr = kvm_lapic_find_highest_irr(vcpu);
7039 else
7040 max_irr = -1;
95ba8273
GN		 7041
7042 if (max_irr != -1)
7043 max_irr >>= 4;
7044
7045 tpr = kvm_lapic_get_cr8(vcpu);
7046
7047 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7048}
7049
b6b8a145 7050static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7051{
b6b8a145
JK		 7052 int r;
7053
95ba8273 7054 /* try to reinject previous events if any */
664f8e26 7055
1a680e35
LA		 7056 if (vcpu->arch.exception.injected)
7057 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7058 /*
a042c26f
LA		 7059 * Do not inject an NMI or interrupt if there is a pending
7060 * exception. Exceptions and interrupts are recognized at
7061 * instruction boundaries, i.e. the start of an instruction.
7062 * Trap-like exceptions, e.g. #DB, have higher priority than
7063 * NMIs and interrupts, i.e. traps are recognized before an
7064 * NMI/interrupt that's pending on the same instruction.
7065 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7066 * priority, but are only generated (pended) during instruction
7067 * execution, i.e. a pending fault-like exception means the
7068 * fault occurred on the *previous* instruction and must be
7069 * serviced prior to recognizing any new events in order to
7070 * fully complete the previous instruction.
664f8e26 7071 */
1a680e35
LA		 7072 else if (!vcpu->arch.exception.pending) {
7073 if (vcpu->arch.nmi_injected)
664f8e26 7074 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7075 else if (vcpu->arch.interrupt.injected)
664f8e26 7076 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7077 }
7078
1a680e35
LA		 7079 /*
7080 * Call check_nested_events() even if we reinjected a previous event
7081 * in order for caller to determine if it should require immediate-exit
7082 * from L2 to L1 due to pending L1 events which require exit
7083 * from L2 to L1.
7084 */
664f8e26
WL		 7085 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7086 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7087 if (r != 0)
7088 return r;
7089 }
7090
7091 /* try to inject new event if pending */
b59bb7bd 7092 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7093 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7094 vcpu->arch.exception.has_error_code,
7095 vcpu->arch.exception.error_code);
d6e8c854 7096
1a680e35 7097 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7098 vcpu->arch.exception.pending = false;
7099 vcpu->arch.exception.injected = true;
7100
d6e8c854
NA		 7101 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7102 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7103 X86_EFLAGS_RF);
7104
6bdf0662
NA		 7105 if (vcpu->arch.exception.nr == DB_VECTOR &&
7106 (vcpu->arch.dr7 & DR7_GD)) {
7107 vcpu->arch.dr7 &= ~DR7_GD;
7108 kvm_update_dr7(vcpu);
7109 }
7110
cfcd20e5 7111 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7112 }
7113
7114 /* Don't consider new event if we re-injected an event */
7115 if (kvm_event_needs_reinjection(vcpu))
7116 return 0;
7117
7118 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7119 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7120 vcpu->arch.smi_pending = false;
52797bf9 7121 ++vcpu->arch.smi_count;
ee2cd4b7 7122 enter_smm(vcpu);
c43203ca 7123 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7124 --vcpu->arch.nmi_pending;
7125 vcpu->arch.nmi_injected = true;
7126 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7127 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7128 /*
7129 * Because interrupts can be injected asynchronously, we are
7130 * calling check_nested_events again here to avoid a race condition.
7131 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7132 * proposal and current concerns. Perhaps we should be setting
7133 * KVM_REQ_EVENT only on certain events and not unconditionally?
7134 */
7135 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7136 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7137 if (r != 0)
7138 return r;
7139 }
95ba8273 7140 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7141 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7142 false);
7143 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7144 }
7145 }
ee2cd4b7 7146
b6b8a145 7147 return 0;
95ba8273
GN		 7148}
7149
7460fb4a
AK		 7150static void process_nmi(struct kvm_vcpu *vcpu)
7151{
7152 unsigned limit = 2;
7153
7154 /*
7155 * x86 is limited to one NMI running, and one NMI pending after it.
7156 * If an NMI is already in progress, limit further NMIs to just one.
7157 * Otherwise, allow two (and we'll inject the first one immediately).
7158 */
7159 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7160 limit = 1;
7161
7162 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7163 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7164 kvm_make_request(KVM_REQ_EVENT, vcpu);
7165}
7166
ee2cd4b7 7167static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7168{
7169 u32 flags = 0;
7170 flags |= seg->g << 23;
7171 flags |= seg->db << 22;
7172 flags |= seg->l << 21;
7173 flags |= seg->avl << 20;
7174 flags |= seg->present << 15;
7175 flags |= seg->dpl << 13;
7176 flags |= seg->s << 12;
7177 flags |= seg->type << 8;
7178 return flags;
7179}
7180
ee2cd4b7 7181static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7182{
7183 struct kvm_segment seg;
7184 int offset;
7185
7186 kvm_get_segment(vcpu, &seg, n);
7187 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7188
7189 if (n < 3)
7190 offset = 0x7f84 + n * 12;
7191 else
7192 offset = 0x7f2c + (n - 3) * 12;
7193
7194 put_smstate(u32, buf, offset + 8, seg.base);
7195 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7196 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7197}
7198
efbb288a 7199#ifdef CONFIG_X86_64
ee2cd4b7 7200static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7201{
7202 struct kvm_segment seg;
7203 int offset;
7204 u16 flags;
7205
7206 kvm_get_segment(vcpu, &seg, n);
7207 offset = 0x7e00 + n * 16;
7208
ee2cd4b7 7209 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7210 put_smstate(u16, buf, offset, seg.selector);
7211 put_smstate(u16, buf, offset + 2, flags);
7212 put_smstate(u32, buf, offset + 4, seg.limit);
7213 put_smstate(u64, buf, offset + 8, seg.base);
7214}
efbb288a 7215#endif
660a5d51 7216
ee2cd4b7 7217static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7218{
7219 struct desc_ptr dt;
7220 struct kvm_segment seg;
7221 unsigned long val;
7222 int i;
7223
7224 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7225 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7226 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7227 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7228
7229 for (i = 0; i < 8; i++)
7230 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7231
7232 kvm_get_dr(vcpu, 6, &val);
7233 put_smstate(u32, buf, 0x7fcc, (u32)val);
7234 kvm_get_dr(vcpu, 7, &val);
7235 put_smstate(u32, buf, 0x7fc8, (u32)val);
7236
7237 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7238 put_smstate(u32, buf, 0x7fc4, seg.selector);
7239 put_smstate(u32, buf, 0x7f64, seg.base);
7240 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7241 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7242
7243 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7244 put_smstate(u32, buf, 0x7fc0, seg.selector);
7245 put_smstate(u32, buf, 0x7f80, seg.base);
7246 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7247 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7248
7249 kvm_x86_ops->get_gdt(vcpu, &dt);
7250 put_smstate(u32, buf, 0x7f74, dt.address);
7251 put_smstate(u32, buf, 0x7f70, dt.size);
7252
7253 kvm_x86_ops->get_idt(vcpu, &dt);
7254 put_smstate(u32, buf, 0x7f58, dt.address);
7255 put_smstate(u32, buf, 0x7f54, dt.size);
7256
7257 for (i = 0; i < 6; i++)
ee2cd4b7 7258 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7259
7260 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7261
7262 /* revision id */
7263 put_smstate(u32, buf, 0x7efc, 0x00020000);
7264 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7265}
7266
ee2cd4b7 7267static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7268{
7269#ifdef CONFIG_X86_64
7270 struct desc_ptr dt;
7271 struct kvm_segment seg;
7272 unsigned long val;
7273 int i;
7274
7275 for (i = 0; i < 16; i++)
7276 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7277
7278 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7279 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7280
7281 kvm_get_dr(vcpu, 6, &val);
7282 put_smstate(u64, buf, 0x7f68, val);
7283 kvm_get_dr(vcpu, 7, &val);
7284 put_smstate(u64, buf, 0x7f60, val);
7285
7286 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7287 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7288 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7289
7290 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7291
7292 /* revision id */
7293 put_smstate(u32, buf, 0x7efc, 0x00020064);
7294
7295 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7296
7297 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7298 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7299 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7300 put_smstate(u32, buf, 0x7e94, seg.limit);
7301 put_smstate(u64, buf, 0x7e98, seg.base);
7302
7303 kvm_x86_ops->get_idt(vcpu, &dt);
7304 put_smstate(u32, buf, 0x7e84, dt.size);
7305 put_smstate(u64, buf, 0x7e88, dt.address);
7306
7307 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7308 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7309 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7310 put_smstate(u32, buf, 0x7e74, seg.limit);
7311 put_smstate(u64, buf, 0x7e78, seg.base);
7312
7313 kvm_x86_ops->get_gdt(vcpu, &dt);
7314 put_smstate(u32, buf, 0x7e64, dt.size);
7315 put_smstate(u64, buf, 0x7e68, dt.address);
7316
7317 for (i = 0; i < 6; i++)
ee2cd4b7 7318 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7319#else
7320 WARN_ON_ONCE(1);
7321#endif
7322}
7323
ee2cd4b7 7324static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7325{
660a5d51 7326 struct kvm_segment cs, ds;
18c3626e 7327 struct desc_ptr dt;
660a5d51
PB		 7328 char buf[512];
7329 u32 cr0;
7330
660a5d51 7331 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7332 memset(buf, 0, 512);
d6321d49 7333 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7334 enter_smm_save_state_64(vcpu, buf);
660a5d51 7335 else
ee2cd4b7 7336 enter_smm_save_state_32(vcpu, buf);
660a5d51 7337
0234bf88
LP		 7338 /*
7339 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7340 * vCPU state (e.g. leave guest mode) after we've saved the state into
7341 * the SMM state-save area.
7342 */
7343 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7344
7345 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7346 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7347
7348 if (kvm_x86_ops->get_nmi_mask(vcpu))
7349 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7350 else
7351 kvm_x86_ops->set_nmi_mask(vcpu, true);
7352
7353 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7354 kvm_rip_write(vcpu, 0x8000);
7355
7356 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7357 kvm_x86_ops->set_cr0(vcpu, cr0);
7358 vcpu->arch.cr0 = cr0;
7359
7360 kvm_x86_ops->set_cr4(vcpu, 0);
7361
18c3626e
PB		 7362 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7363 dt.address = dt.size = 0;
7364 kvm_x86_ops->set_idt(vcpu, &dt);
7365
660a5d51
PB		 7366 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7367
7368 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7369 cs.base = vcpu->arch.smbase;
7370
7371 ds.selector = 0;
7372 ds.base = 0;
7373
7374 cs.limit = ds.limit = 0xffffffff;
7375 cs.type = ds.type = 0x3;
7376 cs.dpl = ds.dpl = 0;
7377 cs.db = ds.db = 0;
7378 cs.s = ds.s = 1;
7379 cs.l = ds.l = 0;
7380 cs.g = ds.g = 1;
7381 cs.avl = ds.avl = 0;
7382 cs.present = ds.present = 1;
7383 cs.unusable = ds.unusable = 0;
7384 cs.padding = ds.padding = 0;
7385
7386 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7387 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7388 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7389 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7390 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7391 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7392
d6321d49 7393 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7394 kvm_x86_ops->set_efer(vcpu, 0);
7395
7396 kvm_update_cpuid(vcpu);
7397 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7398}
7399
ee2cd4b7 7400static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7401{
7402 vcpu->arch.smi_pending = true;
7403 kvm_make_request(KVM_REQ_EVENT, vcpu);
7404}
7405
2860c4b1
PB		 7406void kvm_make_scan_ioapic_request(struct kvm *kvm)
7407{
7408 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7409}
7410
3d81bc7e 7411static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7412{
3d81bc7e
YZ		 7413 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7414 return;
c7c9c56c 7415
6308630b 7416 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7417
b053b2ae 7418 if (irqchip_split(vcpu->kvm))
6308630b 7419 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7420 else {
fa59cc00 7421 if (vcpu->arch.apicv_active)
d62caabb 7422 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7423 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7424 }
e40ff1d6
LA		 7425
7426 if (is_guest_mode(vcpu))
7427 vcpu->arch.load_eoi_exitmap_pending = true;
7428 else
7429 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7430}
7431
7432static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7433{
7434 u64 eoi_exit_bitmap[4];
7435
7436 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7437 return;
7438
5c919412
AS		 7439 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7440 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7441 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7442}
7443
93065ac7
MH		 7444int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7445 unsigned long start, unsigned long end,
7446 bool blockable)
b1394e74
RK		 7447{
7448 unsigned long apic_address;
7449
7450 /*
7451 * The physical address of apic access page is stored in the VMCS.
7452 * Update it when it becomes invalid.
7453 */
7454 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7455 if (start <= apic_address && apic_address < end)
7456 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7457
7458 return 0;
b1394e74
RK		 7459}
7460
4256f43f
TC		 7461void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7462{
c24ae0dc
TC		 7463 struct page *page = NULL;
7464
35754c98 7465 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7466 return;
7467
4256f43f
TC		 7468 if (!kvm_x86_ops->set_apic_access_page_addr)
7469 return;
7470
c24ae0dc 7471 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7472 if (is_error_page(page))
7473 return;
c24ae0dc
TC		 7474 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7475
7476 /*
7477 * Do not pin apic access page in memory, the MMU notifier
7478 * will call us again if it is migrated or swapped out.
7479 */
7480 put_page(page);
4256f43f
TC		 7481}
7482EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7483
d264ee0c
SC		 7484void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7485{
7486 smp_send_reschedule(vcpu->cpu);
7487}
7488EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7489
9357d939 7490/*
362c698f 7491 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7492 * exiting to the userspace. Otherwise, the value will be returned to the
7493 * userspace.
7494 */
851ba692 7495static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7496{
7497 int r;
62a193ed
MG		 7498 bool req_int_win =
7499 dm_request_for_irq_injection(vcpu) &&
7500 kvm_cpu_accept_dm_intr(vcpu);
7501
730dca42 7502 bool req_immediate_exit = false;
b6c7a5dc 7503
2fa6e1e1 7504 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7505 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7506 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7507 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7508 kvm_mmu_unload(vcpu);
a8eeb04a 7509 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7510 __kvm_migrate_timers(vcpu);
d828199e
MT		 7511 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7512 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7513 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7514 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7515 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7516 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7517 if (unlikely(r))
7518 goto out;
7519 }
a8eeb04a 7520 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7521 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7522 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7523 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7524 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7525 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7526 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7527 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7528 r = 0;
7529 goto out;
7530 }
a8eeb04a 7531 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7532 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7533 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7534 r = 0;
7535 goto out;
7536 }
af585b92
GN		 7537 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7538 /* Page is swapped out. Do synthetic halt */
7539 vcpu->arch.apf.halted = true;
7540 r = 1;
7541 goto out;
7542 }
c9aaa895
GC		 7543 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7544 record_steal_time(vcpu);
64d60670
PB		 7545 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7546 process_smi(vcpu);
7460fb4a
AK		 7547 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7548 process_nmi(vcpu);
f5132b01 7549 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7550 kvm_pmu_handle_event(vcpu);
f5132b01 7551 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7552 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7553 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7554 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7555 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7556 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7557 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7558 vcpu->run->eoi.vector =
7559 vcpu->arch.pending_ioapic_eoi;
7560 r = 0;
7561 goto out;
7562 }
7563 }
3d81bc7e
YZ		 7564 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7565 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7566 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7567 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7568 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7569 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7570 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7571 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7572 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7573 r = 0;
7574 goto out;
7575 }
e516cebb
AS		 7576 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7577 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7578 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7579 r = 0;
7580 goto out;
7581 }
db397571
AS		 7582 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7583 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7584 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7585 r = 0;
7586 goto out;
7587 }
f3b138c5
AS		 7588
7589 /*
7590 * KVM_REQ_HV_STIMER has to be processed after
7591 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7592 * depend on the guest clock being up-to-date
7593 */
1f4b34f8
AS		 7594 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7595 kvm_hv_process_stimers(vcpu);
2f52d58c 7596 }
b93463aa 7597
b463a6f7 7598 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7599 ++vcpu->stat.req_event;
66450a21
JK		 7600 kvm_apic_accept_events(vcpu);
7601 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7602 r = 1;
7603 goto out;
7604 }
7605
b6b8a145
JK		 7606 if (inject_pending_event(vcpu, req_int_win) != 0)
7607 req_immediate_exit = true;
321c5658 7608 else {
cc3d967f 7609 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7610 *
cc3d967f
LP		 7611 * SMIs have three cases:
7612 * 1) They can be nested, and then there is nothing to
7613 * do here because RSM will cause a vmexit anyway.
7614 * 2) There is an ISA-specific reason why SMI cannot be
7615 * injected, and the moment when this changes can be
7616 * intercepted.
7617 * 3) Or the SMI can be pending because
7618 * inject_pending_event has completed the injection
7619 * of an IRQ or NMI from the previous vmexit, and
7620 * then we request an immediate exit to inject the
7621 * SMI.
c43203ca
PB		 7622 */
7623 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7624 if (!kvm_x86_ops->enable_smi_window(vcpu))
7625 req_immediate_exit = true;
321c5658
YS		 7626 if (vcpu->arch.nmi_pending)
7627 kvm_x86_ops->enable_nmi_window(vcpu);
7628 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7629 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7630 WARN_ON(vcpu->arch.exception.pending);
321c5658 7631 }
b463a6f7
AK		 7632
7633 if (kvm_lapic_enabled(vcpu)) {
7634 update_cr8_intercept(vcpu);
7635 kvm_lapic_sync_to_vapic(vcpu);
7636 }
7637 }
7638
d8368af8
AK		 7639 r = kvm_mmu_reload(vcpu);
7640 if (unlikely(r)) {
d905c069 7641 goto cancel_injection;
d8368af8
AK		 7642 }
7643
b6c7a5dc
HB		 7644 preempt_disable();
7645
7646 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7647
7648 /*
7649 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7650 * IPI are then delayed after guest entry, which ensures that they
7651 * result in virtual interrupt delivery.
7652 */
7653 local_irq_disable();
6b7e2d09
XG		 7654 vcpu->mode = IN_GUEST_MODE;
7655
01b71917
MT		 7656 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7657
0f127d12 7658 /*
b95234c8 7659 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7660 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7661 *
7662 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7663 * pairs with the memory barrier implicit in pi_test_and_set_on
7664 * (see vmx_deliver_posted_interrupt).
7665 *
7666 * 3) This also orders the write to mode from any reads to the page
7667 * tables done while the VCPU is running. Please see the comment
7668 * in kvm_flush_remote_tlbs.
6b7e2d09 7669 */
01b71917 7670 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7671
b95234c8
PB		 7672 /*
7673 * This handles the case where a posted interrupt was
7674 * notified with kvm_vcpu_kick.
7675 */
fa59cc00
LA		 7676 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7677 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7678
2fa6e1e1 7679 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7680 || need_resched() || signal_pending(current)) {
6b7e2d09 7681 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7682 smp_wmb();
6c142801
AK		 7683 local_irq_enable();
7684 preempt_enable();
01b71917 7685 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7686 r = 1;
d905c069 7687 goto cancel_injection;
6c142801
AK		 7688 }
7689
fc5b7f3b
DM		 7690 kvm_load_guest_xcr0(vcpu);
7691
c43203ca
PB		 7692 if (req_immediate_exit) {
7693 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7694 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7695 }
d6185f20 7696
8b89fe1f 7697 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7698 if (lapic_timer_advance_ns)
7699 wait_lapic_expire(vcpu);
6edaa530 7700 guest_enter_irqoff();
b6c7a5dc 7701
42dbaa5a 7702 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7703 set_debugreg(0, 7);
7704 set_debugreg(vcpu->arch.eff_db[0], 0);
7705 set_debugreg(vcpu->arch.eff_db[1], 1);
7706 set_debugreg(vcpu->arch.eff_db[2], 2);
7707 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7708 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7709 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7710 }
b6c7a5dc 7711
851ba692 7712 kvm_x86_ops->run(vcpu);
b6c7a5dc 7713
c77fb5fe
PB		 7714 /*
7715 * Do this here before restoring debug registers on the host. And
7716 * since we do this before handling the vmexit, a DR access vmexit
7717 * can (a) read the correct value of the debug registers, (b) set
7718 * KVM_DEBUGREG_WONT_EXIT again.
7719 */
7720 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7721 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7722 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7723 kvm_update_dr0123(vcpu);
7724 kvm_update_dr6(vcpu);
7725 kvm_update_dr7(vcpu);
7726 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7727 }
7728
24f1e32c
FW		 7729 /*
7730 * If the guest has used debug registers, at least dr7
7731 * will be disabled while returning to the host.
7732 * If we don't have active breakpoints in the host, we don't
7733 * care about the messed up debug address registers. But if
7734 * we have some of them active, restore the old state.
7735 */
59d8eb53 7736 if (hw_breakpoint_active())
24f1e32c 7737 hw_breakpoint_restore();
42dbaa5a 7738
4ba76538 7739 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7740
6b7e2d09 7741 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7742 smp_wmb();
a547c6db 7743
fc5b7f3b
DM		 7744 kvm_put_guest_xcr0(vcpu);
7745
dd60d217 7746 kvm_before_interrupt(vcpu);
a547c6db 7747 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7748 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7749
7750 ++vcpu->stat.exits;
7751
f2485b3e 7752 guest_exit_irqoff();
b6c7a5dc 7753
f2485b3e 7754 local_irq_enable();
b6c7a5dc
HB		 7755 preempt_enable();
7756
f656ce01 7757 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7758
b6c7a5dc
HB		 7759 /*
7760 * Profile KVM exit RIPs:
7761 */
7762 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7763 unsigned long rip = kvm_rip_read(vcpu);
7764 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7765 }
7766
cc578287
ZA		 7767 if (unlikely(vcpu->arch.tsc_always_catchup))
7768 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7769
5cfb1d5a
MT		 7770 if (vcpu->arch.apic_attention)
7771 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7772
618232e2 7773 vcpu->arch.gpa_available = false;
851ba692 7774 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7775 return r;
7776
7777cancel_injection:
7778 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7779 if (unlikely(vcpu->arch.apic_attention))
7780 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7781out:
7782 return r;
7783}
b6c7a5dc 7784
362c698f
PB		 7785static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7786{
bf9f6ac8
FW		 7787 if (!kvm_arch_vcpu_runnable(vcpu) &&
7788 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7789 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7790 kvm_vcpu_block(vcpu);
7791 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7792
7793 if (kvm_x86_ops->post_block)
7794 kvm_x86_ops->post_block(vcpu);
7795
9c8fd1ba
PB		 7796 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7797 return 1;
7798 }
362c698f
PB		 7799
7800 kvm_apic_accept_events(vcpu);
7801 switch(vcpu->arch.mp_state) {
7802 case KVM_MP_STATE_HALTED:
7803 vcpu->arch.pv.pv_unhalted = false;
7804 vcpu->arch.mp_state =
7805 KVM_MP_STATE_RUNNABLE;
7806 case KVM_MP_STATE_RUNNABLE:
7807 vcpu->arch.apf.halted = false;
7808 break;
7809 case KVM_MP_STATE_INIT_RECEIVED:
7810 break;
7811 default:
7812 return -EINTR;
7813 break;
7814 }
7815 return 1;
7816}
09cec754 7817
5d9bc648
PB		 7818static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7819{
0ad3bed6
PB		 7820 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7821 kvm_x86_ops->check_nested_events(vcpu, false);
7822
5d9bc648
PB		 7823 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7824 !vcpu->arch.apf.halted);
7825}
7826
362c698f 7827static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7828{
7829 int r;
f656ce01 7830 struct kvm *kvm = vcpu->kvm;
d7690175 7831
f656ce01 7832 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7833 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7834
362c698f 7835 for (;;) {
58f800d5 7836 if (kvm_vcpu_running(vcpu)) {
851ba692 7837 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7838 } else {
362c698f 7839 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7840 }
7841
09cec754
GN		 7842 if (r <= 0)
7843 break;
7844
72875d8a 7845 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7846 if (kvm_cpu_has_pending_timer(vcpu))
7847 kvm_inject_pending_timer_irqs(vcpu);
7848
782d422b
MG		 7849 if (dm_request_for_irq_injection(vcpu) &&
7850 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7851 r = 0;
7852 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7853 ++vcpu->stat.request_irq_exits;
362c698f 7854 break;
09cec754 7855 }
af585b92
GN		 7856
7857 kvm_check_async_pf_completion(vcpu);
7858
09cec754
GN		 7859 if (signal_pending(current)) {
7860 r = -EINTR;
851ba692 7861 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7862 ++vcpu->stat.signal_exits;
362c698f 7863 break;
09cec754
GN		 7864 }
7865 if (need_resched()) {
f656ce01 7866 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7867 cond_resched();
f656ce01 7868 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7869 }
b6c7a5dc
HB		 7870 }
7871
f656ce01 7872 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7873
7874 return r;
7875}
7876
716d51ab
GN		 7877static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7878{
7879 int r;
7880 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 7881 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 7882 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7883 if (r != EMULATE_DONE)
7884 return 0;
7885 return 1;
7886}
7887
7888static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7889{
7890 BUG_ON(!vcpu->arch.pio.count);
7891
7892 return complete_emulated_io(vcpu);
7893}
7894
f78146b0
AK		 7895/*
7896 * Implements the following, as a state machine:
7897 *
7898 * read:
7899 * for each fragment
87da7e66
XG		 7900 * for each mmio piece in the fragment
7901 * write gpa, len
7902 * exit
7903 * copy data
f78146b0
AK		 7904 * execute insn
7905 *
7906 * write:
7907 * for each fragment
87da7e66
XG		 7908 * for each mmio piece in the fragment
7909 * write gpa, len
7910 * copy data
7911 * exit
f78146b0 7912 */
716d51ab 7913static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7914{
7915 struct kvm_run *run = vcpu->run;
f78146b0 7916 struct kvm_mmio_fragment *frag;
87da7e66 7917 unsigned len;
5287f194 7918
716d51ab 7919 BUG_ON(!vcpu->mmio_needed);
5287f194 7920
716d51ab 7921 /* Complete previous fragment */
87da7e66
XG		 7922 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7923 len = min(8u, frag->len);
716d51ab 7924 if (!vcpu->mmio_is_write)
87da7e66
XG		 7925 memcpy(frag->data, run->mmio.data, len);
7926
7927 if (frag->len <= 8) {
7928 /* Switch to the next fragment. */
7929 frag++;
7930 vcpu->mmio_cur_fragment++;
7931 } else {
7932 /* Go forward to the next mmio piece. */
7933 frag->data += len;
7934 frag->gpa += len;
7935 frag->len -= len;
7936 }
7937
a08d3b3b 7938 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7939 vcpu->mmio_needed = 0;
0912c977
PB		 7940
7941 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7942 if (vcpu->mmio_is_write)
716d51ab
GN		 7943 return 1;
7944 vcpu->mmio_read_completed = 1;
7945 return complete_emulated_io(vcpu);
7946 }
87da7e66 7947
716d51ab
GN		 7948 run->exit_reason = KVM_EXIT_MMIO;
7949 run->mmio.phys_addr = frag->gpa;
7950 if (vcpu->mmio_is_write)
87da7e66
XG		 7951 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7952 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7953 run->mmio.is_write = vcpu->mmio_is_write;
7954 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7955 return 0;
5287f194
AK		 7956}
7957
822f312d
SAS		 7958/* Swap (qemu) user FPU context for the guest FPU context. */
7959static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7960{
7961 preempt_disable();
7962 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7963 /* PKRU is separately restored in kvm_x86_ops->run. */
7964 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7965 ~XFEATURE_MASK_PKRU);
7966 preempt_enable();
7967 trace_kvm_fpu(1);
7968}
7969
7970/* When vcpu_run ends, restore user space FPU context. */
7971static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7972{
7973 preempt_disable();
7974 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7975 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7976 preempt_enable();
7977 ++vcpu->stat.fpu_reload;
7978 trace_kvm_fpu(0);
7979}
7980
b6c7a5dc
HB		 7981int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7982{
7983 int r;
b6c7a5dc 7984
accb757d 7985 vcpu_load(vcpu);
20b7035c 7986 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7987 kvm_load_guest_fpu(vcpu);
7988
a4535290 7989 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7990 if (kvm_run->immediate_exit) {
7991 r = -EINTR;
7992 goto out;
7993 }
b6c7a5dc 7994 kvm_vcpu_block(vcpu);
66450a21 7995 kvm_apic_accept_events(vcpu);
72875d8a 7996 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7997 r = -EAGAIN;
a0595000
JS		 7998 if (signal_pending(current)) {
7999 r = -EINTR;
8000 vcpu->run->exit_reason = KVM_EXIT_INTR;
8001 ++vcpu->stat.signal_exits;
8002 }
ac9f6dc0 8003 goto out;
b6c7a5dc
HB		 8004 }
8005
01643c51
KH		 8006 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8007 r = -EINVAL;
8008 goto out;
8009 }
8010
8011 if (vcpu->run->kvm_dirty_regs) {
8012 r = sync_regs(vcpu);
8013 if (r != 0)
8014 goto out;
8015 }
8016
b6c7a5dc 8017 /* re-sync apic's tpr */
35754c98 8018 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8019 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8020 r = -EINVAL;
8021 goto out;
8022 }
8023 }
b6c7a5dc 8024
716d51ab
GN		 8025 if (unlikely(vcpu->arch.complete_userspace_io)) {
8026 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8027 vcpu->arch.complete_userspace_io = NULL;
8028 r = cui(vcpu);
8029 if (r <= 0)
5663d8f9 8030 goto out;
716d51ab
GN		 8031 } else
8032 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8033
460df4c1
PB		 8034 if (kvm_run->immediate_exit)
8035 r = -EINTR;
8036 else
8037 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8038
8039out:
5663d8f9 8040 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8041 if (vcpu->run->kvm_valid_regs)
8042 store_regs(vcpu);
f1d86e46 8043 post_kvm_run_save(vcpu);
20b7035c 8044 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8045
accb757d 8046 vcpu_put(vcpu);
b6c7a5dc
HB		 8047 return r;
8048}
8049
01643c51 8050static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8051{
7ae441ea
GN		 8052 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8053 /*
8054 * We are here if userspace calls get_regs() in the middle of
8055 * instruction emulation. Registers state needs to be copied
4a969980 8056 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8057 * that usually, but some bad designed PV devices (vmware
8058 * backdoor interface) need this to work
8059 */
dd856efa 8060 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8061 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8062 }
5fdbf976
MT		 8063 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8064 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8065 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8066 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8067 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8068 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8069 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8070 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 8071#ifdef CONFIG_X86_64
5fdbf976
MT		 8072 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8073 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8074 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8075 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8076 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8077 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8078 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8079 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8080#endif
8081
5fdbf976 8082 regs->rip = kvm_rip_read(vcpu);
91586a3b 8083 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8084}
b6c7a5dc 8085
01643c51
KH		 8086int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8087{
8088 vcpu_load(vcpu);
8089 __get_regs(vcpu, regs);
1fc9b76b 8090 vcpu_put(vcpu);
b6c7a5dc
HB		 8091 return 0;
8092}
8093
01643c51 8094static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8095{
7ae441ea
GN		 8096 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8097 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8098
5fdbf976
MT		 8099 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8100 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8101 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8102 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8103 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8104 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8105 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8106 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8107#ifdef CONFIG_X86_64
5fdbf976
MT		 8108 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8109 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8110 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8111 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8112 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8113 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8114 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8115 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8116#endif
8117
5fdbf976 8118 kvm_rip_write(vcpu, regs->rip);
d73235d1 8119 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8120
b4f14abd
JK		 8121 vcpu->arch.exception.pending = false;
8122
3842d135 8123 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8124}
3842d135 8125
01643c51
KH		 8126int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8127{
8128 vcpu_load(vcpu);
8129 __set_regs(vcpu, regs);
875656fe 8130 vcpu_put(vcpu);
b6c7a5dc
HB		 8131 return 0;
8132}
8133
b6c7a5dc
HB		 8134void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8135{
8136 struct kvm_segment cs;
8137
3e6e0aab 8138 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8139 *db = cs.db;
8140 *l = cs.l;
8141}
8142EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8143
01643c51 8144static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8145{
89a27f4d 8146 struct desc_ptr dt;
b6c7a5dc 8147
3e6e0aab
GT		 8148 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8149 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8150 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8151 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8152 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8153 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8154
3e6e0aab
GT		 8155 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8156 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8157
8158 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8159 sregs->idt.limit = dt.size;
8160 sregs->idt.base = dt.address;
b6c7a5dc 8161 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8162 sregs->gdt.limit = dt.size;
8163 sregs->gdt.base = dt.address;
b6c7a5dc 8164
4d4ec087 8165 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8166 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8167 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8168 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8169 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8170 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8171 sregs->apic_base = kvm_get_apic_base(vcpu);
8172
923c61bb 8173 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 8174
04140b41 8175 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8176 set_bit(vcpu->arch.interrupt.nr,
8177 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8178}
16d7a191 8179
01643c51
KH		 8180int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8181 struct kvm_sregs *sregs)
8182{
8183 vcpu_load(vcpu);
8184 __get_sregs(vcpu, sregs);
bcdec41c 8185 vcpu_put(vcpu);
b6c7a5dc
HB		 8186 return 0;
8187}
8188
62d9f0db
MT		 8189int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8190 struct kvm_mp_state *mp_state)
8191{
fd232561
CD		 8192 vcpu_load(vcpu);
8193
66450a21 8194 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8195 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8196 vcpu->arch.pv.pv_unhalted)
8197 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8198 else
8199 mp_state->mp_state = vcpu->arch.mp_state;
8200
fd232561 8201 vcpu_put(vcpu);
62d9f0db
MT		 8202 return 0;
8203}
8204
8205int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8206 struct kvm_mp_state *mp_state)
8207{
e83dff5e
CD		 8208 int ret = -EINVAL;
8209
8210 vcpu_load(vcpu);
8211
bce87cce 8212 if (!lapic_in_kernel(vcpu) &&
66450a21 8213 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8214 goto out;
66450a21 8215
28bf2888
DH		 8216 /* INITs are latched while in SMM */
8217 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8218 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8219 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8220 goto out;
28bf2888 8221
66450a21
JK		 8222 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8223 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8224 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8225 } else
8226 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8227 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8228
8229 ret = 0;
8230out:
8231 vcpu_put(vcpu);
8232 return ret;
62d9f0db
MT		 8233}
8234
7f3d35fd
KW		 8235int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8236 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8237{
9d74191a 8238 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8239 int ret;
e01c2426 8240
8ec4722d 8241 init_emulate_ctxt(vcpu);
c697518a 8242
7f3d35fd 8243 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8244 has_error_code, error_code);
c697518a 8245
c697518a 8246 if (ret)
19d04437 8247 return EMULATE_FAIL;
37817f29 8248
9d74191a
TY		 8249 kvm_rip_write(vcpu, ctxt->eip);
8250 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8251 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8252 return EMULATE_DONE;
37817f29
IE		 8253}
8254EXPORT_SYMBOL_GPL(kvm_task_switch);
8255
3140c156 8256static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8257{
74fec5b9
TL		 8258 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8259 (sregs->cr4 & X86_CR4_OSXSAVE))
8260 return -EINVAL;
8261
37b95951 8262 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8263 /*
8264 * When EFER.LME and CR0.PG are set, the processor is in
8265 * 64-bit mode (though maybe in a 32-bit code segment).
8266 * CR4.PAE and EFER.LMA must be set.
8267 */
37b95951 8268 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8269 || !(sregs->efer & EFER_LMA))
8270 return -EINVAL;
8271 } else {
8272 /*
8273 * Not in 64-bit mode: EFER.LMA is clear and the code
8274 * segment cannot be 64-bit.
8275 */
8276 if (sregs->efer & EFER_LMA || sregs->cs.l)
8277 return -EINVAL;
8278 }
8279
8280 return 0;
8281}
8282
01643c51 8283static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8284{
58cb628d 8285 struct msr_data apic_base_msr;
b6c7a5dc 8286 int mmu_reset_needed = 0;
c4d21882 8287 int cpuid_update_needed = 0;
63f42e02 8288 int pending_vec, max_bits, idx;
89a27f4d 8289 struct desc_ptr dt;
b4ef9d4e
CD		 8290 int ret = -EINVAL;
8291
f2981033 8292 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8293 goto out;
f2981033 8294
d3802286
JM		 8295 apic_base_msr.data = sregs->apic_base;
8296 apic_base_msr.host_initiated = true;
8297 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8298 goto out;
6d1068b3 8299
89a27f4d
GN		 8300 dt.size = sregs->idt.limit;
8301 dt.address = sregs->idt.base;
b6c7a5dc 8302 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8303 dt.size = sregs->gdt.limit;
8304 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8305 kvm_x86_ops->set_gdt(vcpu, &dt);
8306
ad312c7c 8307 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8308 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8309 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8310 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8311
2d3ad1f4 8312 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8313
f6801dff 8314 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8315 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8316
4d4ec087 8317 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8318 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8319 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8320
fc78f519 8321 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8322 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8323 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8324 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8325 if (cpuid_update_needed)
00b27a3e 8326 kvm_update_cpuid(vcpu);
63f42e02
XG		 8327
8328 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8329 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8330 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8331 mmu_reset_needed = 1;
8332 }
63f42e02 8333 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8334
8335 if (mmu_reset_needed)
8336 kvm_mmu_reset_context(vcpu);
8337
a50abc3b 8338 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8339 pending_vec = find_first_bit(
8340 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8341 if (pending_vec < max_bits) {
66fd3f7f 8342 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8343 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8344 }
8345
3e6e0aab
GT		 8346 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8347 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8348 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8349 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8350 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8351 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8352
3e6e0aab
GT		 8353 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8354 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8355
5f0269f5
ME		 8356 update_cr8_intercept(vcpu);
8357
9c3e4aab 8358 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8359 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8360 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8361 !is_protmode(vcpu))
9c3e4aab
MT		 8362 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8363
3842d135
AK		 8364 kvm_make_request(KVM_REQ_EVENT, vcpu);
8365
b4ef9d4e
CD		 8366 ret = 0;
8367out:
01643c51
KH		 8368 return ret;
8369}
8370
8371int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8372 struct kvm_sregs *sregs)
8373{
8374 int ret;
8375
8376 vcpu_load(vcpu);
8377 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8378 vcpu_put(vcpu);
8379 return ret;
b6c7a5dc
HB		 8380}
8381
d0bfb940
JK		 8382int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8383 struct kvm_guest_debug *dbg)
b6c7a5dc 8384{
355be0b9 8385 unsigned long rflags;
ae675ef0 8386 int i, r;
b6c7a5dc 8387
66b56562
CD		 8388 vcpu_load(vcpu);
8389
4f926bf2
JK		 8390 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8391 r = -EBUSY;
8392 if (vcpu->arch.exception.pending)
2122ff5e 8393 goto out;
4f926bf2
JK		 8394 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8395 kvm_queue_exception(vcpu, DB_VECTOR);
8396 else
8397 kvm_queue_exception(vcpu, BP_VECTOR);
8398 }
8399
91586a3b
JK		 8400 /*
8401 * Read rflags as long as potentially injected trace flags are still
8402 * filtered out.
8403 */
8404 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8405
8406 vcpu->guest_debug = dbg->control;
8407 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8408 vcpu->guest_debug = 0;
8409
8410 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8411 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8412 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8413 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8414 } else {
8415 for (i = 0; i < KVM_NR_DB_REGS; i++)
8416 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8417 }
c8639010 8418 kvm_update_dr7(vcpu);
ae675ef0 8419
f92653ee
JK		 8420 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8421 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8422 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8423
91586a3b
JK		 8424 /*
8425 * Trigger an rflags update that will inject or remove the trace
8426 * flags.
8427 */
8428 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8429
a96036b8 8430 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8431
4f926bf2 8432 r = 0;
d0bfb940 8433
2122ff5e 8434out:
66b56562 8435 vcpu_put(vcpu);
b6c7a5dc
HB		 8436 return r;
8437}
8438
8b006791
ZX		 8439/*
8440 * Translate a guest virtual address to a guest physical address.
8441 */
8442int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8443 struct kvm_translation *tr)
8444{
8445 unsigned long vaddr = tr->linear_address;
8446 gpa_t gpa;
f656ce01 8447 int idx;
8b006791 8448
1da5b61d
CD		 8449 vcpu_load(vcpu);
8450
f656ce01 8451 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8452 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8453 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8454 tr->physical_address = gpa;
8455 tr->valid = gpa != UNMAPPED_GVA;
8456 tr->writeable = 1;
8457 tr->usermode = 0;
8b006791 8458
1da5b61d 8459 vcpu_put(vcpu);
8b006791
ZX		 8460 return 0;
8461}
8462
d0752060
HB		 8463int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8464{
1393123e 8465 struct fxregs_state *fxsave;
d0752060 8466
1393123e 8467 vcpu_load(vcpu);
d0752060 8468
1393123e 8469 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8470 memcpy(fpu->fpr, fxsave->st_space, 128);
8471 fpu->fcw = fxsave->cwd;
8472 fpu->fsw = fxsave->swd;
8473 fpu->ftwx = fxsave->twd;
8474 fpu->last_opcode = fxsave->fop;
8475 fpu->last_ip = fxsave->rip;
8476 fpu->last_dp = fxsave->rdp;
8477 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8478
1393123e 8479 vcpu_put(vcpu);
d0752060
HB		 8480 return 0;
8481}
8482
8483int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8484{
6a96bc7f
CD		 8485 struct fxregs_state *fxsave;
8486
8487 vcpu_load(vcpu);
8488
8489 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8490
d0752060
HB		 8491 memcpy(fxsave->st_space, fpu->fpr, 128);
8492 fxsave->cwd = fpu->fcw;
8493 fxsave->swd = fpu->fsw;
8494 fxsave->twd = fpu->ftwx;
8495 fxsave->fop = fpu->last_opcode;
8496 fxsave->rip = fpu->last_ip;
8497 fxsave->rdp = fpu->last_dp;
8498 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8499
6a96bc7f 8500 vcpu_put(vcpu);
d0752060
HB		 8501 return 0;
8502}
8503
01643c51
KH		 8504static void store_regs(struct kvm_vcpu *vcpu)
8505{
8506 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8507
8508 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8509 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8510
8511 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8512 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8513
8514 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8515 kvm_vcpu_ioctl_x86_get_vcpu_events(
8516 vcpu, &vcpu->run->s.regs.events);
8517}
8518
8519static int sync_regs(struct kvm_vcpu *vcpu)
8520{
8521 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8522 return -EINVAL;
8523
8524 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8525 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8526 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8527 }
8528 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8529 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8530 return -EINVAL;
8531 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8532 }
8533 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8534 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8535 vcpu, &vcpu->run->s.regs.events))
8536 return -EINVAL;
8537 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8538 }
8539
8540 return 0;
8541}
8542
0ee6a517 8543static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8544{
bf935b0b 8545 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8546 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8547 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8548 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8549
2acf923e
DC		 8550 /*
8551 * Ensure guest xcr0 is valid for loading
8552 */
d91cab78 8553 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8554
ad312c7c 8555 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8556}
d0752060 8557
e9b11c17
ZX		 8558void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8559{
bd768e14
IY		 8560 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8561
12f9a48f 8562 kvmclock_reset(vcpu);
7f1ea208 8563
e9b11c17 8564 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8565 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8566}
8567
8568struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8569 unsigned int id)
8570{
c447e76b
LL		 8571 struct kvm_vcpu *vcpu;
8572
b0c39dc6 8573 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8574 printk_once(KERN_WARNING
8575 "kvm: SMP vm created on host with unstable TSC; "
8576 "guest TSC will not be reliable\n");
c447e76b
LL		 8577
8578 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8579
c447e76b 8580 return vcpu;
26e5215f 8581}
e9b11c17 8582
26e5215f
AK		 8583int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8584{
19efffa2 8585 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8586 vcpu_load(vcpu);
d28bc9dd 8587 kvm_vcpu_reset(vcpu, false);
e1732991 8588 kvm_init_mmu(vcpu, false);
e9b11c17 8589 vcpu_put(vcpu);
ec7660cc 8590 return 0;
e9b11c17
ZX		 8591}
8592
31928aa5 8593void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8594{
8fe8ab46 8595 struct msr_data msr;
332967a3 8596 struct kvm *kvm = vcpu->kvm;
42897d86 8597
d3457c87
RK		 8598 kvm_hv_vcpu_postcreate(vcpu);
8599
ec7660cc 8600 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8601 return;
ec7660cc 8602 vcpu_load(vcpu);
8fe8ab46
WA		 8603 msr.data = 0x0;
8604 msr.index = MSR_IA32_TSC;
8605 msr.host_initiated = true;
8606 kvm_write_tsc(vcpu, &msr);
42897d86 8607 vcpu_put(vcpu);
ec7660cc 8608 mutex_unlock(&vcpu->mutex);
42897d86 8609
630994b3
MT		 8610 if (!kvmclock_periodic_sync)
8611 return;
8612
332967a3
AJ		 8613 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8614 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8615}
8616
d40ccc62 8617void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8618{
344d9588
GN		 8619 vcpu->arch.apf.msr_val = 0;
8620
ec7660cc 8621 vcpu_load(vcpu);
e9b11c17
ZX		 8622 kvm_mmu_unload(vcpu);
8623 vcpu_put(vcpu);
8624
8625 kvm_x86_ops->vcpu_free(vcpu);
8626}
8627
d28bc9dd 8628void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8629{
b7e31be3
RK		 8630 kvm_lapic_reset(vcpu, init_event);
8631
e69fab5d
PB		 8632 vcpu->arch.hflags = 0;
8633
c43203ca 8634 vcpu->arch.smi_pending = 0;
52797bf9 8635 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8636 atomic_set(&vcpu->arch.nmi_queued, 0);
8637 vcpu->arch.nmi_pending = 0;
448fa4a9 8638 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8639 kvm_clear_interrupt_queue(vcpu);
8640 kvm_clear_exception_queue(vcpu);
664f8e26 8641 vcpu->arch.exception.pending = false;
448fa4a9 8642
42dbaa5a 8643 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8644 kvm_update_dr0123(vcpu);
6f43ed01 8645 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8646 kvm_update_dr6(vcpu);
42dbaa5a 8647 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8648 kvm_update_dr7(vcpu);
42dbaa5a 8649
1119022c
NA		 8650 vcpu->arch.cr2 = 0;
8651
3842d135 8652 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8653 vcpu->arch.apf.msr_val = 0;
c9aaa895 8654 vcpu->arch.st.msr_val = 0;
3842d135 8655
12f9a48f
GC		 8656 kvmclock_reset(vcpu);
8657
af585b92
GN		 8658 kvm_clear_async_pf_completion_queue(vcpu);
8659 kvm_async_pf_hash_reset(vcpu);
8660 vcpu->arch.apf.halted = false;
3842d135 8661
a554d207
WL		 8662 if (kvm_mpx_supported()) {
8663 void *mpx_state_buffer;
8664
8665 /*
8666 * To avoid have the INIT path from kvm_apic_has_events() that be
8667 * called with loaded FPU and does not let userspace fix the state.
8668 */
f775b13e
RR		 8669 if (init_event)
8670 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8671 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8672 XFEATURE_MASK_BNDREGS);
8673 if (mpx_state_buffer)
8674 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8675 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8676 XFEATURE_MASK_BNDCSR);
8677 if (mpx_state_buffer)
8678 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8679 if (init_event)
8680 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8681 }
8682
64d60670 8683 if (!init_event) {
d28bc9dd 8684 kvm_pmu_reset(vcpu);
64d60670 8685 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8686
8687 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8688 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8689
8690 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8691 }
f5132b01 8692
66f7b72e
JS		 8693 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8694 vcpu->arch.regs_avail = ~0;
8695 vcpu->arch.regs_dirty = ~0;
8696
a554d207
WL		 8697 vcpu->arch.ia32_xss = 0;
8698
d28bc9dd 8699 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8700}
8701
2b4a273b 8702void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8703{
8704 struct kvm_segment cs;
8705
8706 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8707 cs.selector = vector << 8;
8708 cs.base = vector << 12;
8709 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8710 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8711}
8712
13a34e06 8713int kvm_arch_hardware_enable(void)
e9b11c17 8714{
ca84d1a2
ZA		 8715 struct kvm *kvm;
8716 struct kvm_vcpu *vcpu;
8717 int i;
0dd6a6ed
ZA		 8718 int ret;
8719 u64 local_tsc;
8720 u64 max_tsc = 0;
8721 bool stable, backwards_tsc = false;
18863bdd
AK		 8722
8723 kvm_shared_msr_cpu_online();
13a34e06 8724 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8725 if (ret != 0)
8726 return ret;
8727
4ea1636b 8728 local_tsc = rdtsc();
b0c39dc6 8729 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8730 list_for_each_entry(kvm, &vm_list, vm_list) {
8731 kvm_for_each_vcpu(i, vcpu, kvm) {
8732 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8733 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8734 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8735 backwards_tsc = true;
8736 if (vcpu->arch.last_host_tsc > max_tsc)
8737 max_tsc = vcpu->arch.last_host_tsc;
8738 }
8739 }
8740 }
8741
8742 /*
8743 * Sometimes, even reliable TSCs go backwards. This happens on
8744 * platforms that reset TSC during suspend or hibernate actions, but
8745 * maintain synchronization. We must compensate. Fortunately, we can
8746 * detect that condition here, which happens early in CPU bringup,
8747 * before any KVM threads can be running. Unfortunately, we can't
8748 * bring the TSCs fully up to date with real time, as we aren't yet far
8749 * enough into CPU bringup that we know how much real time has actually
108b249c 8750 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8751 * variables that haven't been updated yet.
8752 *
8753 * So we simply find the maximum observed TSC above, then record the
8754 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8755 * the adjustment will be applied. Note that we accumulate
8756 * adjustments, in case multiple suspend cycles happen before some VCPU
8757 * gets a chance to run again. In the event that no KVM threads get a
8758 * chance to run, we will miss the entire elapsed period, as we'll have
8759 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8760 * loose cycle time. This isn't too big a deal, since the loss will be
8761 * uniform across all VCPUs (not to mention the scenario is extremely
8762 * unlikely). It is possible that a second hibernate recovery happens
8763 * much faster than a first, causing the observed TSC here to be
8764 * smaller; this would require additional padding adjustment, which is
8765 * why we set last_host_tsc to the local tsc observed here.
8766 *
8767 * N.B. - this code below runs only on platforms with reliable TSC,
8768 * as that is the only way backwards_tsc is set above. Also note
8769 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8770 * have the same delta_cyc adjustment applied if backwards_tsc
8771 * is detected. Note further, this adjustment is only done once,
8772 * as we reset last_host_tsc on all VCPUs to stop this from being
8773 * called multiple times (one for each physical CPU bringup).
8774 *
4a969980 8775 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8776 * will be compensated by the logic in vcpu_load, which sets the TSC to
8777 * catchup mode. This will catchup all VCPUs to real time, but cannot
8778 * guarantee that they stay in perfect synchronization.
8779 */
8780 if (backwards_tsc) {
8781 u64 delta_cyc = max_tsc - local_tsc;
8782 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8783 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8784 kvm_for_each_vcpu(i, vcpu, kvm) {
8785 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8786 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8787 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8788 }
8789
8790 /*
8791 * We have to disable TSC offset matching.. if you were
8792 * booting a VM while issuing an S4 host suspend....
8793 * you may have some problem. Solving this issue is
8794 * left as an exercise to the reader.
8795 */
8796 kvm->arch.last_tsc_nsec = 0;
8797 kvm->arch.last_tsc_write = 0;
8798 }
8799
8800 }
8801 return 0;
e9b11c17
ZX		 8802}
8803
13a34e06 8804void kvm_arch_hardware_disable(void)
e9b11c17 8805{
13a34e06
RK		 8806 kvm_x86_ops->hardware_disable();
8807 drop_user_return_notifiers();
e9b11c17
ZX		 8808}
8809
8810int kvm_arch_hardware_setup(void)
8811{
9e9c3fe4
NA		 8812 int r;
8813
8814 r = kvm_x86_ops->hardware_setup();
8815 if (r != 0)
8816 return r;
8817
35181e86
HZ		 8818 if (kvm_has_tsc_control) {
8819 /*
8820 * Make sure the user can only configure tsc_khz values that
8821 * fit into a signed integer.
273ba457 8822 * A min value is not calculated because it will always
35181e86
HZ		 8823 * be 1 on all machines.
8824 */
8825 u64 max = min(0x7fffffffULL,
8826 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8827 kvm_max_guest_tsc_khz = max;
8828
ad721883 8829 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8830 }
ad721883 8831
9e9c3fe4
NA		 8832 kvm_init_msr_list();
8833 return 0;
e9b11c17
ZX		 8834}
8835
8836void kvm_arch_hardware_unsetup(void)
8837{
8838 kvm_x86_ops->hardware_unsetup();
8839}
8840
8841void kvm_arch_check_processor_compat(void *rtn)
8842{
8843 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8844}
8845
8846bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8847{
8848 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8849}
8850EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8851
8852bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8853{
8854 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8855}
8856
54e9818f 8857struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8858EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8859
e9b11c17
ZX		 8860int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8861{
8862 struct page *page;
e9b11c17
ZX		 8863 int r;
8864
b2a05fef 8865 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8866 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8867 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8868 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8869 else
a4535290 8870 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8871
8872 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8873 if (!page) {
8874 r = -ENOMEM;
8875 goto fail;
8876 }
ad312c7c 8877 vcpu->arch.pio_data = page_address(page);
e9b11c17 8878
cc578287 8879 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8880
e9b11c17
ZX		 8881 r = kvm_mmu_create(vcpu);
8882 if (r < 0)
8883 goto fail_free_pio_data;
8884
26de7988 8885 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8886 r = kvm_create_lapic(vcpu);
8887 if (r < 0)
8888 goto fail_mmu_destroy;
54e9818f
GN		 8889 } else
8890 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8891
890ca9ae
HY		 8892 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8893 GFP_KERNEL);
8894 if (!vcpu->arch.mce_banks) {
8895 r = -ENOMEM;
443c39bc 8896 goto fail_free_lapic;
890ca9ae
HY		 8897 }
8898 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8899
f1797359
WY		 8900 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8901 r = -ENOMEM;
f5f48ee1 8902 goto fail_free_mce_banks;
f1797359 8903 }
f5f48ee1 8904
0ee6a517 8905 fx_init(vcpu);
66f7b72e 8906
4344ee98 8907 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8908
5a4f55cd
EK		 8909 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8910
74545705
RK		 8911 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8912
af585b92 8913 kvm_async_pf_hash_reset(vcpu);
f5132b01 8914 kvm_pmu_init(vcpu);
af585b92 8915
1c1a9ce9 8916 vcpu->arch.pending_external_vector = -1;
de63ad4c 8917 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8918
5c919412
AS		 8919 kvm_hv_vcpu_init(vcpu);
8920
e9b11c17 8921 return 0;
0ee6a517 8922
f5f48ee1
SY		 8923fail_free_mce_banks:
8924 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8925fail_free_lapic:
8926 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8927fail_mmu_destroy:
8928 kvm_mmu_destroy(vcpu);
8929fail_free_pio_data:
ad312c7c 8930 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8931fail:
8932 return r;
8933}
8934
8935void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8936{
f656ce01
MT		 8937 int idx;
8938
1f4b34f8 8939 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8940 kvm_pmu_destroy(vcpu);
36cb93fd 8941 kfree(vcpu->arch.mce_banks);
e9b11c17 8942 kvm_free_lapic(vcpu);
f656ce01 8943 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8944 kvm_mmu_destroy(vcpu);
f656ce01 8945 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8946 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8947 if (!lapic_in_kernel(vcpu))
54e9818f 8948 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8949}
d19a9cd2 8950
e790d9ef
RK		 8951void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8952{
c595ceee 8953 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8954 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8955}
8956
e08b9637 8957int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8958{
e08b9637
CO		 8959 if (type)
8960 return -EINVAL;
8961
6ef768fa 8962 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8963 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8964 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8965 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8966 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8967
5550af4d
SY		 8968 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8969 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8970 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8971 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8972 &kvm->arch.irq_sources_bitmap);
5550af4d 8973
038f8c11 8974 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8975 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8976 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8977
108b249c 8978 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8979 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8980
6fbbde9a
DS		 8981 kvm->arch.guest_can_read_msr_platform_info = true;
8982
7e44e449 8983 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8984 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8985
cbc0236a 8986 kvm_hv_init_vm(kvm);
0eb05bf2 8987 kvm_page_track_init(kvm);
13d268ca 8988 kvm_mmu_init_vm(kvm);
0eb05bf2 8989
03543133
SS		 8990 if (kvm_x86_ops->vm_init)
8991 return kvm_x86_ops->vm_init(kvm);
8992
d89f5eff 8993 return 0;
d19a9cd2
ZX		 8994}
8995
8996static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8997{
ec7660cc 8998 vcpu_load(vcpu);
d19a9cd2
ZX		 8999 kvm_mmu_unload(vcpu);
9000 vcpu_put(vcpu);
9001}
9002
9003static void kvm_free_vcpus(struct kvm *kvm)
9004{
9005 unsigned int i;
988a2cae 9006 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9007
9008 /*
9009 * Unpin any mmu pages first.
9010 */
af585b92
GN		 9011 kvm_for_each_vcpu(i, vcpu, kvm) {
9012 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9013 kvm_unload_vcpu_mmu(vcpu);
af585b92 9014 }
988a2cae
GN		 9015 kvm_for_each_vcpu(i, vcpu, kvm)
9016 kvm_arch_vcpu_free(vcpu);
9017
9018 mutex_lock(&kvm->lock);
9019 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9020 kvm->vcpus[i] = NULL;
d19a9cd2 9021
988a2cae
GN		 9022 atomic_set(&kvm->online_vcpus, 0);
9023 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9024}
9025
ad8ba2cd
SY		 9026void kvm_arch_sync_events(struct kvm *kvm)
9027{
332967a3 9028 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9029 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9030 kvm_free_pit(kvm);
ad8ba2cd
SY		 9031}
9032
1d8007bd 9033int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9034{
9035 int i, r;
25188b99 9036 unsigned long hva;
f0d648bd
PB		 9037 struct kvm_memslots *slots = kvm_memslots(kvm);
9038 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9039
9040 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9041 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9042 return -EINVAL;
9da0e4d5 9043
f0d648bd
PB		 9044 slot = id_to_memslot(slots, id);
9045 if (size) {
b21629da 9046 if (slot->npages)
f0d648bd
PB		 9047 return -EEXIST;
9048
9049 /*
9050 * MAP_SHARED to prevent internal slot pages from being moved
9051 * by fork()/COW.
9052 */
9053 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9054 MAP_SHARED | MAP_ANONYMOUS, 0);
9055 if (IS_ERR((void *)hva))
9056 return PTR_ERR((void *)hva);
9057 } else {
9058 if (!slot->npages)
9059 return 0;
9060
9061 hva = 0;
9062 }
9063
9064 old = *slot;
9da0e4d5 9065 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9066 struct kvm_userspace_memory_region m;
9da0e4d5 9067
1d8007bd
PB		 9068 m.slot = id | (i << 16);
9069 m.flags = 0;
9070 m.guest_phys_addr = gpa;
f0d648bd 9071 m.userspace_addr = hva;
1d8007bd 9072 m.memory_size = size;
9da0e4d5
PB		 9073 r = __kvm_set_memory_region(kvm, &m);
9074 if (r < 0)
9075 return r;
9076 }
9077
103c763c
EB		 9078 if (!size)
9079 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9080
9da0e4d5
PB		 9081 return 0;
9082}
9083EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9084
1d8007bd 9085int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9086{
9087 int r;
9088
9089 mutex_lock(&kvm->slots_lock);
1d8007bd 9090 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9091 mutex_unlock(&kvm->slots_lock);
9092
9093 return r;
9094}
9095EXPORT_SYMBOL_GPL(x86_set_memory_region);
9096
d19a9cd2
ZX		 9097void kvm_arch_destroy_vm(struct kvm *kvm)
9098{
27469d29
AH		 9099 if (current->mm == kvm->mm) {
9100 /*
9101 * Free memory regions allocated on behalf of userspace,
9102 * unless the the memory map has changed due to process exit
9103 * or fd copying.
9104 */
1d8007bd
PB		 9105 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9106 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9107 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9108 }
03543133
SS		 9109 if (kvm_x86_ops->vm_destroy)
9110 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9111 kvm_pic_destroy(kvm);
9112 kvm_ioapic_destroy(kvm);
d19a9cd2 9113 kvm_free_vcpus(kvm);
af1bae54 9114 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9115 kvm_mmu_uninit_vm(kvm);
2beb6dad 9116 kvm_page_track_cleanup(kvm);
cbc0236a 9117 kvm_hv_destroy_vm(kvm);
d19a9cd2 9118}
0de10343 9119
5587027c 9120void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9121 struct kvm_memory_slot *dont)
9122{
9123 int i;
9124
d89cc617
TY		 9125 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9126 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9127 kvfree(free->arch.rmap[i]);
d89cc617 9128 free->arch.rmap[i] = NULL;
77d11309 9129 }
d89cc617
TY		 9130 if (i == 0)
9131 continue;
9132
9133 if (!dont || free->arch.lpage_info[i - 1] !=
9134 dont->arch.lpage_info[i - 1]) {
548ef284 9135 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9136 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9137 }
9138 }
21ebbeda
XG		 9139
9140 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9141}
9142
5587027c
AK		 9143int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9144 unsigned long npages)
db3fe4eb
TY		 9145{
9146 int i;
9147
d89cc617 9148 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9149 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9150 unsigned long ugfn;
9151 int lpages;
d89cc617 9152 int level = i + 1;
db3fe4eb
TY		 9153
9154 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9155 slot->base_gfn, level) + 1;
9156
d89cc617 9157 slot->arch.rmap[i] =
778e1cdd
KC		 9158 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9159 GFP_KERNEL);
d89cc617 9160 if (!slot->arch.rmap[i])
77d11309 9161 goto out_free;
d89cc617
TY		 9162 if (i == 0)
9163 continue;
77d11309 9164
778e1cdd 9165 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 9166 if (!linfo)
db3fe4eb
TY		 9167 goto out_free;
9168
92f94f1e
XG		 9169 slot->arch.lpage_info[i - 1] = linfo;
9170
db3fe4eb 9171 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9172 linfo[0].disallow_lpage = 1;
db3fe4eb 9173 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9174 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9175 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9176 /*
9177 * If the gfn and userspace address are not aligned wrt each
9178 * other, or if explicitly asked to, disable large page
9179 * support for this slot
9180 */
9181 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9182 !kvm_largepages_enabled()) {
9183 unsigned long j;
9184
9185 for (j = 0; j < lpages; ++j)
92f94f1e 9186 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9187 }
9188 }
9189
21ebbeda
XG		 9190 if (kvm_page_track_create_memslot(slot, npages))
9191 goto out_free;
9192
db3fe4eb
TY		 9193 return 0;
9194
9195out_free:
d89cc617 9196 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9197 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9198 slot->arch.rmap[i] = NULL;
9199 if (i == 0)
9200 continue;
9201
548ef284 9202 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9203 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9204 }
9205 return -ENOMEM;
9206}
9207
15f46015 9208void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9209{
e6dff7d1
TY		 9210 /*
9211 * memslots->generation has been incremented.
9212 * mmio generation may have reached its maximum value.
9213 */
54bf36aa 9214 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9215}
9216
f7784b8e
MT		 9217int kvm_arch_prepare_memory_region(struct kvm *kvm,
9218 struct kvm_memory_slot *memslot,
09170a49 9219 const struct kvm_userspace_memory_region *mem,
7b6195a9 9220 enum kvm_mr_change change)
0de10343 9221{
f7784b8e
MT		 9222 return 0;
9223}
9224
88178fd4
KH		 9225static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9226 struct kvm_memory_slot *new)
9227{
9228 /* Still write protect RO slot */
9229 if (new->flags & KVM_MEM_READONLY) {
9230 kvm_mmu_slot_remove_write_access(kvm, new);
9231 return;
9232 }
9233
9234 /*
9235 * Call kvm_x86_ops dirty logging hooks when they are valid.
9236 *
9237 * kvm_x86_ops->slot_disable_log_dirty is called when:
9238 *
9239 * - KVM_MR_CREATE with dirty logging is disabled
9240 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9241 *
9242 * The reason is, in case of PML, we need to set D-bit for any slots
9243 * with dirty logging disabled in order to eliminate unnecessary GPA
9244 * logging in PML buffer (and potential PML buffer full VMEXT). This
9245 * guarantees leaving PML enabled during guest's lifetime won't have
9246 * any additonal overhead from PML when guest is running with dirty
9247 * logging disabled for memory slots.
9248 *
9249 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9250 * to dirty logging mode.
9251 *
9252 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9253 *
9254 * In case of write protect:
9255 *
9256 * Write protect all pages for dirty logging.
9257 *
9258 * All the sptes including the large sptes which point to this
9259 * slot are set to readonly. We can not create any new large
9260 * spte on this slot until the end of the logging.
9261 *
9262 * See the comments in fast_page_fault().
9263 */
9264 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9265 if (kvm_x86_ops->slot_enable_log_dirty)
9266 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9267 else
9268 kvm_mmu_slot_remove_write_access(kvm, new);
9269 } else {
9270 if (kvm_x86_ops->slot_disable_log_dirty)
9271 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9272 }
9273}
9274
f7784b8e 9275void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9276 const struct kvm_userspace_memory_region *mem,
8482644a 9277 const struct kvm_memory_slot *old,
f36f3f28 9278 const struct kvm_memory_slot *new,
8482644a 9279 enum kvm_mr_change change)
f7784b8e 9280{
8482644a 9281 int nr_mmu_pages = 0;
f7784b8e 9282
48c0e4e9
XG		 9283 if (!kvm->arch.n_requested_mmu_pages)
9284 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9285
48c0e4e9 9286 if (nr_mmu_pages)
0de10343 9287 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9288
3ea3b7fa
WL		 9289 /*
9290 * Dirty logging tracks sptes in 4k granularity, meaning that large
9291 * sptes have to be split. If live migration is successful, the guest
9292 * in the source machine will be destroyed and large sptes will be
9293 * created in the destination. However, if the guest continues to run
9294 * in the source machine (for example if live migration fails), small
9295 * sptes will remain around and cause bad performance.
9296 *
9297 * Scan sptes if dirty logging has been stopped, dropping those
9298 * which can be collapsed into a single large-page spte. Later
9299 * page faults will create the large-page sptes.
9300 */
9301 if ((change != KVM_MR_DELETE) &&
9302 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9303 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9304 kvm_mmu_zap_collapsible_sptes(kvm, new);
9305
c972f3b1 9306 /*
88178fd4 9307 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9308 *
88178fd4
KH		 9309 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9310 * been zapped so no dirty logging staff is needed for old slot. For
9311 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9312 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9313 *
9314 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9315 */
88178fd4 9316 if (change != KVM_MR_DELETE)
f36f3f28 9317 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9318}
1d737c8a 9319
2df72e9b 9320void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9321{
6ca18b69 9322 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9323}
9324
2df72e9b
MT		 9325void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9326 struct kvm_memory_slot *slot)
9327{
ae7cd873 9328 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9329}
9330
e6c67d8c
LA		 9331static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9332{
9333 return (is_guest_mode(vcpu) &&
9334 kvm_x86_ops->guest_apic_has_interrupt &&
9335 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9336}
9337
5d9bc648
PB		 9338static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9339{
9340 if (!list_empty_careful(&vcpu->async_pf.done))
9341 return true;
9342
9343 if (kvm_apic_has_events(vcpu))
9344 return true;
9345
9346 if (vcpu->arch.pv.pv_unhalted)
9347 return true;
9348
a5f01f8e
WL		 9349 if (vcpu->arch.exception.pending)
9350 return true;
9351
47a66eed
Z		 9352 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9353 (vcpu->arch.nmi_pending &&
9354 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9355 return true;
9356
47a66eed
Z		 9357 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9358 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9359 return true;
9360
5d9bc648 9361 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9362 (kvm_cpu_has_interrupt(vcpu) ||
9363 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9364 return true;
9365
1f4b34f8
AS		 9366 if (kvm_hv_has_stimer_pending(vcpu))
9367 return true;
9368
5d9bc648
PB		 9369 return false;
9370}
9371
1d737c8a
ZX		 9372int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9373{
5d9bc648 9374 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9375}
5736199a 9376
199b5763
LM		 9377bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9378{
de63ad4c 9379 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9380}
9381
b6d33834 9382int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9383{
b6d33834 9384 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9385}
78646121
GN		 9386
9387int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9388{
9389 return kvm_x86_ops->interrupt_allowed(vcpu);
9390}
229456fc 9391
82b32774 9392unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9393{
82b32774
NA		 9394 if (is_64_bit_mode(vcpu))
9395 return kvm_rip_read(vcpu);
9396 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9397 kvm_rip_read(vcpu));
9398}
9399EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9400
82b32774
NA		 9401bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9402{
9403 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9404}
9405EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9406
94fe45da
JK		 9407unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9408{
9409 unsigned long rflags;
9410
9411 rflags = kvm_x86_ops->get_rflags(vcpu);
9412 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9413 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9414 return rflags;
9415}
9416EXPORT_SYMBOL_GPL(kvm_get_rflags);
9417
6addfc42 9418static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9419{
9420 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9421 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9422 rflags |= X86_EFLAGS_TF;
94fe45da 9423 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9424}
9425
9426void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9427{
9428 __kvm_set_rflags(vcpu, rflags);
3842d135 9429 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9430}
9431EXPORT_SYMBOL_GPL(kvm_set_rflags);
9432
56028d08
GN		 9433void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9434{
9435 int r;
9436
44dd3ffa 9437 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9438 work->wakeup_all)
56028d08
GN		 9439 return;
9440
9441 r = kvm_mmu_reload(vcpu);
9442 if (unlikely(r))
9443 return;
9444
44dd3ffa
VK		 9445 if (!vcpu->arch.mmu->direct_map &&
9446 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9447 return;
9448
44dd3ffa 9449 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9450}
9451
af585b92
GN		 9452static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9453{
9454 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9455}
9456
9457static inline u32 kvm_async_pf_next_probe(u32 key)
9458{
9459 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9460}
9461
9462static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9463{
9464 u32 key = kvm_async_pf_hash_fn(gfn);
9465
9466 while (vcpu->arch.apf.gfns[key] != ~0)
9467 key = kvm_async_pf_next_probe(key);
9468
9469 vcpu->arch.apf.gfns[key] = gfn;
9470}
9471
9472static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9473{
9474 int i;
9475 u32 key = kvm_async_pf_hash_fn(gfn);
9476
9477 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9478 (vcpu->arch.apf.gfns[key] != gfn &&
9479 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9480 key = kvm_async_pf_next_probe(key);
9481
9482 return key;
9483}
9484
9485bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9486{
9487 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9488}
9489
9490static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9491{
9492 u32 i, j, k;
9493
9494 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9495 while (true) {
9496 vcpu->arch.apf.gfns[i] = ~0;
9497 do {
9498 j = kvm_async_pf_next_probe(j);
9499 if (vcpu->arch.apf.gfns[j] == ~0)
9500 return;
9501 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9502 /*
9503 * k lies cyclically in ]i,j]
9504 * | i.k.j |
9505 * |....j i.k.| or |.k..j i...|
9506 */
9507 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9508 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9509 i = j;
9510 }
9511}
9512
7c90705b
GN		 9513static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9514{
4e335d9e
PB		 9515
9516 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9517 sizeof(val));
7c90705b
GN		 9518}
9519
9a6e7c39
WL		 9520static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9521{
9522
9523 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9524 sizeof(u32));
9525}
9526
af585b92
GN		 9527void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9528 struct kvm_async_pf *work)
9529{
6389ee94
AK		 9530 struct x86_exception fault;
9531
7c90705b 9532 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9533 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9534
9535 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9536 (vcpu->arch.apf.send_user_only &&
9537 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9538 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9539 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9540 fault.vector = PF_VECTOR;
9541 fault.error_code_valid = true;
9542 fault.error_code = 0;
9543 fault.nested_page_fault = false;
9544 fault.address = work->arch.token;
adfe20fb 9545 fault.async_page_fault = true;
6389ee94 9546 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9547 }
af585b92
GN		 9548}
9549
9550void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9551 struct kvm_async_pf *work)
9552{
6389ee94 9553 struct x86_exception fault;
9a6e7c39 9554 u32 val;
6389ee94 9555
f2e10669 9556 if (work->wakeup_all)
7c90705b
GN		 9557 work->arch.token = ~0; /* broadcast wakeup */
9558 else
9559 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9560 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9561
9a6e7c39
WL		 9562 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9563 !apf_get_user(vcpu, &val)) {
9564 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9565 vcpu->arch.exception.pending &&
9566 vcpu->arch.exception.nr == PF_VECTOR &&
9567 !apf_put_user(vcpu, 0)) {
9568 vcpu->arch.exception.injected = false;
9569 vcpu->arch.exception.pending = false;
9570 vcpu->arch.exception.nr = 0;
9571 vcpu->arch.exception.has_error_code = false;
9572 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9573 vcpu->arch.exception.has_payload = false;
9574 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9575 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9576 fault.vector = PF_VECTOR;
9577 fault.error_code_valid = true;
9578 fault.error_code = 0;
9579 fault.nested_page_fault = false;
9580 fault.address = work->arch.token;
9581 fault.async_page_fault = true;
9582 kvm_inject_page_fault(vcpu, &fault);
9583 }
7c90705b 9584 }
e6d53e3b 9585 vcpu->arch.apf.halted = false;
a4fa1635 9586 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9587}
9588
9589bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9590{
9591 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9592 return true;
9593 else
9bc1f09f 9594 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9595}
9596
5544eb9b
PB		 9597void kvm_arch_start_assignment(struct kvm *kvm)
9598{
9599 atomic_inc(&kvm->arch.assigned_device_count);
9600}
9601EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9602
9603void kvm_arch_end_assignment(struct kvm *kvm)
9604{
9605 atomic_dec(&kvm->arch.assigned_device_count);
9606}
9607EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9608
9609bool kvm_arch_has_assigned_device(struct kvm *kvm)
9610{
9611 return atomic_read(&kvm->arch.assigned_device_count);
9612}
9613EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9614
e0f0bbc5
AW		 9615void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9616{
9617 atomic_inc(&kvm->arch.noncoherent_dma_count);
9618}
9619EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9620
9621void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9622{
9623 atomic_dec(&kvm->arch.noncoherent_dma_count);
9624}
9625EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9626
9627bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9628{
9629 return atomic_read(&kvm->arch.noncoherent_dma_count);
9630}
9631EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9632
14717e20
AW		 9633bool kvm_arch_has_irq_bypass(void)
9634{
9635 return kvm_x86_ops->update_pi_irte != NULL;
9636}
9637
87276880
FW		 9638int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9639 struct irq_bypass_producer *prod)
9640{
9641 struct kvm_kernel_irqfd *irqfd =
9642 container_of(cons, struct kvm_kernel_irqfd, consumer);
9643
14717e20 9644 irqfd->producer = prod;
87276880 9645
14717e20
AW		 9646 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9647 prod->irq, irqfd->gsi, 1);
87276880
FW		 9648}
9649
9650void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9651 struct irq_bypass_producer *prod)
9652{
9653 int ret;
9654 struct kvm_kernel_irqfd *irqfd =
9655 container_of(cons, struct kvm_kernel_irqfd, consumer);
9656
87276880
FW		 9657 WARN_ON(irqfd->producer != prod);
9658 irqfd->producer = NULL;
9659
9660 /*
9661 * When producer of consumer is unregistered, we change back to
9662 * remapped mode, so we can re-use the current implementation
bb3541f1 9663 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9664 * int this case doesn't want to receive the interrupts.
9665 */
9666 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9667 if (ret)
9668 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9669 " fails: %d\n", irqfd->consumer.token, ret);
9670}
9671
9672int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9673 uint32_t guest_irq, bool set)
9674{
9675 if (!kvm_x86_ops->update_pi_irte)
9676 return -EINVAL;
9677
9678 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9679}
9680
52004014
FW		 9681bool kvm_vector_hashing_enabled(void)
9682{
9683 return vector_hashing;
9684}
9685EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9686
229456fc 9687EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9689EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9691EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9692EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9693EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9694EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9695EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9696EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9697EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9698EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9699EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9700EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9701EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9702EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9703EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9704EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9705EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)