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Merge tag 'kvm-s390-next-4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
c4ae60e4
LA		 145bool __read_mostly enable_vmware_backdoor = false;
146module_param(enable_vmware_backdoor, bool, S_IRUGO);
147EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
148
6c86eedc
WL		 149static bool __read_mostly force_emulation_prefix = false;
150module_param(force_emulation_prefix, bool, S_IRUGO);
151
18863bdd
AK		 152#define KVM_NR_SHARED_MSRS 16
153
154struct kvm_shared_msrs_global {
155 int nr;
2bf78fa7 156 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 157};
158
159struct kvm_shared_msrs {
160 struct user_return_notifier urn;
161 bool registered;
2bf78fa7
SY		 162 struct kvm_shared_msr_values {
163 u64 host;
164 u64 curr;
165 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 166};
167
168static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 169static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 170
417bc304 171struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 172 { "pf_fixed", VCPU_STAT(pf_fixed) },
173 { "pf_guest", VCPU_STAT(pf_guest) },
174 { "tlb_flush", VCPU_STAT(tlb_flush) },
175 { "invlpg", VCPU_STAT(invlpg) },
176 { "exits", VCPU_STAT(exits) },
177 { "io_exits", VCPU_STAT(io_exits) },
178 { "mmio_exits", VCPU_STAT(mmio_exits) },
179 { "signal_exits", VCPU_STAT(signal_exits) },
180 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 181 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 182 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 183 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 184 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 185 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 186 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 187 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 188 { "request_irq", VCPU_STAT(request_irq_exits) },
189 { "irq_exits", VCPU_STAT(irq_exits) },
190 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 191 { "fpu_reload", VCPU_STAT(fpu_reload) },
192 { "insn_emulation", VCPU_STAT(insn_emulation) },
193 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 194 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 195 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 196 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 197 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
198 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
199 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
200 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
201 { "mmu_flooded", VM_STAT(mmu_flooded) },
202 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 203 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 204 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 205 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 206 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 207 { "max_mmu_page_hash_collisions",
208 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 209 { NULL }
210};
211
2acf923e
DC		 212u64 __read_mostly host_xcr0;
213
b6785def 214static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 215
af585b92
GN		 216static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
217{
218 int i;
219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
220 vcpu->arch.apf.gfns[i] = ~0;
221}
222
18863bdd
AK		 223static void kvm_on_user_return(struct user_return_notifier *urn)
224{
225 unsigned slot;
18863bdd
AK		 226 struct kvm_shared_msrs *locals
227 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 228 struct kvm_shared_msr_values *values;
1650b4eb
IA		 229 unsigned long flags;
230
231 /*
232 * Disabling irqs at this point since the following code could be
233 * interrupted and executed through kvm_arch_hardware_disable()
234 */
235 local_irq_save(flags);
236 if (locals->registered) {
237 locals->registered = false;
238 user_return_notifier_unregister(urn);
239 }
240 local_irq_restore(flags);
18863bdd 241 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 242 values = &locals->values[slot];
243 if (values->host != values->curr) {
244 wrmsrl(shared_msrs_global.msrs[slot], values->host);
245 values->curr = values->host;
18863bdd
AK		 246 }
247 }
18863bdd
AK		 248}
249
2bf78fa7 250static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 251{
18863bdd 252 u64 value;
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 255
2bf78fa7
SY		 256 /* only read, and nobody should modify it at this time,
257 * so don't need lock */
258 if (slot >= shared_msrs_global.nr) {
259 printk(KERN_ERR "kvm: invalid MSR slot!");
260 return;
261 }
262 rdmsrl_safe(msr, &value);
263 smsr->values[slot].host = value;
264 smsr->values[slot].curr = value;
265}
266
267void kvm_define_shared_msr(unsigned slot, u32 msr)
268{
0123be42 269 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 270 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 271 if (slot >= shared_msrs_global.nr)
272 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 273}
274EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
275
276static void kvm_shared_msr_cpu_online(void)
277{
278 unsigned i;
18863bdd
AK		 279
280 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 281 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 282}
283
8b3c3104 284int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 285{
013f6a5d
MT		 286 unsigned int cpu = smp_processor_id();
287 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 288 int err;
18863bdd 289
2bf78fa7 290 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 291 return 0;
2bf78fa7 292 smsr->values[slot].curr = value;
8b3c3104
AH		 293 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
294 if (err)
295 return 1;
296
18863bdd
AK		 297 if (!smsr->registered) {
298 smsr->urn.on_user_return = kvm_on_user_return;
299 user_return_notifier_register(&smsr->urn);
300 smsr->registered = true;
301 }
8b3c3104 302 return 0;
18863bdd
AK		 303}
304EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
305
13a34e06 306static void drop_user_return_notifiers(void)
3548bab5 307{
013f6a5d
MT		 308 unsigned int cpu = smp_processor_id();
309 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 310
311 if (smsr->registered)
312 kvm_on_user_return(&smsr->urn);
313}
314
6866b83e
CO		 315u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
316{
8a5a87d9 317 return vcpu->arch.apic_base;
6866b83e
CO		 318}
319EXPORT_SYMBOL_GPL(kvm_get_apic_base);
320
58871649
JM		 321enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
322{
323 return kvm_apic_mode(kvm_get_apic_base(vcpu));
324}
325EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
326
58cb628d
JK		 327int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
328{
58871649
JM		 329 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
330 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 331 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
332 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 333
58871649 334 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 335 return 1;
58871649
JM		 336 if (!msr_info->host_initiated) {
337 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
338 return 1;
339 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
340 return 1;
341 }
58cb628d
JK		 342
343 kvm_lapic_set_base(vcpu, msr_info->data);
344 return 0;
6866b83e
CO		 345}
346EXPORT_SYMBOL_GPL(kvm_set_apic_base);
347
2605fc21 348asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 349{
350 /* Fault while not rebooting. We want the trace. */
351 BUG();
352}
353EXPORT_SYMBOL_GPL(kvm_spurious_fault);
354
3fd28fce
ED		 355#define EXCPT_BENIGN 0
356#define EXCPT_CONTRIBUTORY 1
357#define EXCPT_PF 2
358
359static int exception_class(int vector)
360{
361 switch (vector) {
362 case PF_VECTOR:
363 return EXCPT_PF;
364 case DE_VECTOR:
365 case TS_VECTOR:
366 case NP_VECTOR:
367 case SS_VECTOR:
368 case GP_VECTOR:
369 return EXCPT_CONTRIBUTORY;
370 default:
371 break;
372 }
373 return EXCPT_BENIGN;
374}
375
d6e8c854
NA		 376#define EXCPT_FAULT 0
377#define EXCPT_TRAP 1
378#define EXCPT_ABORT 2
379#define EXCPT_INTERRUPT 3
380
381static int exception_type(int vector)
382{
383 unsigned int mask;
384
385 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
386 return EXCPT_INTERRUPT;
387
388 mask = 1 << vector;
389
390 /* #DB is trap, as instruction watchpoints are handled elsewhere */
391 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
392 return EXCPT_TRAP;
393
394 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
395 return EXCPT_ABORT;
396
397 /* Reserved exceptions will result in fault */
398 return EXCPT_FAULT;
399}
400
3fd28fce 401static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 402 unsigned nr, bool has_error, u32 error_code,
403 bool reinject)
3fd28fce
ED		 404{
405 u32 prev_nr;
406 int class1, class2;
407
3842d135
AK		 408 kvm_make_request(KVM_REQ_EVENT, vcpu);
409
664f8e26 410 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 411 queue:
3ffb2468
NA		 412 if (has_error && !is_protmode(vcpu))
413 has_error = false;
664f8e26
WL		 414 if (reinject) {
415 /*
416 * On vmentry, vcpu->arch.exception.pending is only
417 * true if an event injection was blocked by
418 * nested_run_pending. In that case, however,
419 * vcpu_enter_guest requests an immediate exit,
420 * and the guest shouldn't proceed far enough to
421 * need reinjection.
422 */
423 WARN_ON_ONCE(vcpu->arch.exception.pending);
424 vcpu->arch.exception.injected = true;
425 } else {
426 vcpu->arch.exception.pending = true;
427 vcpu->arch.exception.injected = false;
428 }
3fd28fce
ED		 429 vcpu->arch.exception.has_error_code = has_error;
430 vcpu->arch.exception.nr = nr;
431 vcpu->arch.exception.error_code = error_code;
432 return;
433 }
434
435 /* to check exception */
436 prev_nr = vcpu->arch.exception.nr;
437 if (prev_nr == DF_VECTOR) {
438 /* triple fault -> shutdown */
a8eeb04a 439 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 440 return;
441 }
442 class1 = exception_class(prev_nr);
443 class2 = exception_class(nr);
444 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
445 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 446 /*
447 * Generate double fault per SDM Table 5-5. Set
448 * exception.pending = true so that the double fault
449 * can trigger a nested vmexit.
450 */
3fd28fce 451 vcpu->arch.exception.pending = true;
664f8e26 452 vcpu->arch.exception.injected = false;
3fd28fce
ED		 453 vcpu->arch.exception.has_error_code = true;
454 vcpu->arch.exception.nr = DF_VECTOR;
455 vcpu->arch.exception.error_code = 0;
456 } else
457 /* replace previous exception with a new one in a hope
458 that instruction re-execution will regenerate lost
459 exception */
460 goto queue;
461}
462
298101da
AK		 463void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
464{
ce7ddec4 465 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 466}
467EXPORT_SYMBOL_GPL(kvm_queue_exception);
468
ce7ddec4
JR		 469void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
470{
471 kvm_multiple_exception(vcpu, nr, false, 0, true);
472}
473EXPORT_SYMBOL_GPL(kvm_requeue_exception);
474
6affcbed 475int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 476{
db8fcefa
AP		 477 if (err)
478 kvm_inject_gp(vcpu, 0);
479 else
6affcbed
KH		 480 return kvm_skip_emulated_instruction(vcpu);
481
482 return 1;
db8fcefa
AP		 483}
484EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 485
6389ee94 486void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 487{
488 ++vcpu->stat.pf_guest;
adfe20fb
WL		 489 vcpu->arch.exception.nested_apf =
490 is_guest_mode(vcpu) && fault->async_page_fault;
491 if (vcpu->arch.exception.nested_apf)
492 vcpu->arch.apf.nested_apf_token = fault->address;
493 else
494 vcpu->arch.cr2 = fault->address;
6389ee94 495 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 496}
27d6c865 497EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 498
ef54bcfe 499static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 500{
6389ee94
AK		 501 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
502 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 503 else
6389ee94 504 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 505
506 return fault->nested_page_fault;
d4f8cf66
JR		 507}
508
3419ffc8
SY		 509void kvm_inject_nmi(struct kvm_vcpu *vcpu)
510{
7460fb4a
AK		 511 atomic_inc(&vcpu->arch.nmi_queued);
512 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 513}
514EXPORT_SYMBOL_GPL(kvm_inject_nmi);
515
298101da
AK		 516void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
517{
ce7ddec4 518 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 519}
520EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
521
ce7ddec4
JR		 522void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
523{
524 kvm_multiple_exception(vcpu, nr, true, error_code, true);
525}
526EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
527
0a79b009
AK		 528/*
529 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
530 * a #GP and return false.
531 */
532bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 533{
0a79b009
AK		 534 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
535 return true;
536 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
537 return false;
298101da 538}
0a79b009 539EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 540
16f8a6f9
NA		 541bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
542{
543 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
544 return true;
545
546 kvm_queue_exception(vcpu, UD_VECTOR);
547 return false;
548}
549EXPORT_SYMBOL_GPL(kvm_require_dr);
550
ec92fe44
JR		 551/*
552 * This function will be used to read from the physical memory of the currently
54bf36aa 553 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 554 * can read from guest physical or from the guest's guest physical memory.
555 */
556int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
557 gfn_t ngfn, void *data, int offset, int len,
558 u32 access)
559{
54987b7a 560 struct x86_exception exception;
ec92fe44
JR		 561 gfn_t real_gfn;
562 gpa_t ngpa;
563
564 ngpa = gfn_to_gpa(ngfn);
54987b7a 565 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 566 if (real_gfn == UNMAPPED_GVA)
567 return -EFAULT;
568
569 real_gfn = gpa_to_gfn(real_gfn);
570
54bf36aa 571 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 572}
573EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
574
69b0049a 575static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 576 void *data, int offset, int len, u32 access)
577{
578 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
579 data, offset, len, access);
580}
581
a03490ed
CO		 582/*
583 * Load the pae pdptrs. Return true is they are all valid.
584 */
ff03a073 585int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 586{
587 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
588 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
589 int i;
590 int ret;
ff03a073 591 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 592
ff03a073
JR		 593 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
594 offset * sizeof(u64), sizeof(pdpte),
595 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 596 if (ret < 0) {
597 ret = 0;
598 goto out;
599 }
600 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 601 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 602 (pdpte[i] &
603 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 604 ret = 0;
605 goto out;
606 }
607 }
608 ret = 1;
609
ff03a073 610 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 611 __set_bit(VCPU_EXREG_PDPTR,
612 (unsigned long *)&vcpu->arch.regs_avail);
613 __set_bit(VCPU_EXREG_PDPTR,
614 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 615out:
a03490ed
CO		 616
617 return ret;
618}
cc4b6871 619EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 620
9ed38ffa 621bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 622{
ff03a073 623 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 624 bool changed = true;
3d06b8bf
JR		 625 int offset;
626 gfn_t gfn;
d835dfec
AK		 627 int r;
628
629 if (is_long_mode(vcpu) || !is_pae(vcpu))
630 return false;
631
6de4f3ad
AK		 632 if (!test_bit(VCPU_EXREG_PDPTR,
633 (unsigned long *)&vcpu->arch.regs_avail))
634 return true;
635
a512177e
PB		 636 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
637 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 638 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
639 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 640 if (r < 0)
641 goto out;
ff03a073 642 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 643out:
d835dfec
AK		 644
645 return changed;
646}
9ed38ffa 647EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 648
49a9b07e 649int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 650{
aad82703 651 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 652 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 653
f9a48e6a
AK		 654 cr0 |= X86_CR0_ET;
655
ab344828 656#ifdef CONFIG_X86_64
0f12244f
GN		 657 if (cr0 & 0xffffffff00000000UL)
658 return 1;
ab344828
GN		 659#endif
660
661 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 662
0f12244f
GN		 663 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
664 return 1;
a03490ed 665
0f12244f
GN		 666 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
667 return 1;
a03490ed
CO		 668
669 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
670#ifdef CONFIG_X86_64
f6801dff 671 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 672 int cs_db, cs_l;
673
0f12244f
GN		 674 if (!is_pae(vcpu))
675 return 1;
a03490ed 676 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 677 if (cs_l)
678 return 1;
a03490ed
CO		 679 } else
680#endif
ff03a073 681 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 682 kvm_read_cr3(vcpu)))
0f12244f 683 return 1;
a03490ed
CO		 684 }
685
ad756a16
MJ		 686 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
687 return 1;
688
a03490ed 689 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 690
d170c419 691 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 692 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 693 kvm_async_pf_hash_reset(vcpu);
694 }
e5f3f027 695
aad82703
SY		 696 if ((cr0 ^ old_cr0) & update_bits)
697 kvm_mmu_reset_context(vcpu);
b18d5431 698
879ae188
LE		 699 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
700 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
701 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 702 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
703
0f12244f
GN		 704 return 0;
705}
2d3ad1f4 706EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 707
2d3ad1f4 708void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 709{
49a9b07e 710 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 711}
2d3ad1f4 712EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 713
42bdf991
MT		 714static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
715{
716 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
717 !vcpu->guest_xcr0_loaded) {
718 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 719 if (vcpu->arch.xcr0 != host_xcr0)
720 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 721 vcpu->guest_xcr0_loaded = 1;
722 }
723}
724
725static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
726{
727 if (vcpu->guest_xcr0_loaded) {
728 if (vcpu->arch.xcr0 != host_xcr0)
729 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
730 vcpu->guest_xcr0_loaded = 0;
731 }
732}
733
69b0049a 734static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 735{
56c103ec
LJ		 736 u64 xcr0 = xcr;
737 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 738 u64 valid_bits;
2acf923e
DC		 739
740 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
741 if (index != XCR_XFEATURE_ENABLED_MASK)
742 return 1;
d91cab78 743 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 744 return 1;
d91cab78 745 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 746 return 1;
46c34cb0
PB		 747
748 /*
749 * Do not allow the guest to set bits that we do not support
750 * saving. However, xcr0 bit 0 is always set, even if the
751 * emulated CPU does not support XSAVE (see fx_init).
752 */
d91cab78 753 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 754 if (xcr0 & ~valid_bits)
2acf923e 755 return 1;
46c34cb0 756
d91cab78
DH		 757 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
758 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 759 return 1;
760
d91cab78
DH		 761 if (xcr0 & XFEATURE_MASK_AVX512) {
762 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 763 return 1;
d91cab78 764 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 765 return 1;
766 }
2acf923e 767 vcpu->arch.xcr0 = xcr0;
56c103ec 768
d91cab78 769 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 770 kvm_update_cpuid(vcpu);
2acf923e
DC		 771 return 0;
772}
773
774int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
775{
764bcbc5
Z		 776 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
777 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 778 kvm_inject_gp(vcpu, 0);
779 return 1;
780 }
781 return 0;
782}
783EXPORT_SYMBOL_GPL(kvm_set_xcr);
784
a83b29c6 785int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 786{
fc78f519 787 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 788 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 789 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 790
0f12244f
GN		 791 if (cr4 & CR4_RESERVED_BITS)
792 return 1;
a03490ed 793
d6321d49 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 795 return 1;
796
d6321d49 797 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 798 return 1;
799
d6321d49 800 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 801 return 1;
802
d6321d49 803 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 804 return 1;
805
d6321d49 806 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 807 return 1;
808
fd8cb433 809 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 810 return 1;
811
ae3e61e1
PB		 812 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
813 return 1;
814
a03490ed 815 if (is_long_mode(vcpu)) {
0f12244f
GN		 816 if (!(cr4 & X86_CR4_PAE))
817 return 1;
a2edf57f
AK		 818 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
819 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 820 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
821 kvm_read_cr3(vcpu)))
0f12244f
GN		 822 return 1;
823
ad756a16 824 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 825 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 826 return 1;
827
828 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
829 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
830 return 1;
831 }
832
5e1746d6 833 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 834 return 1;
a03490ed 835
ad756a16
MJ		 836 if (((cr4 ^ old_cr4) & pdptr_bits) ||
837 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 838 kvm_mmu_reset_context(vcpu);
0f12244f 839
b9baba86 840 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 841 kvm_update_cpuid(vcpu);
2acf923e 842
0f12244f
GN		 843 return 0;
844}
2d3ad1f4 845EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 846
2390218b 847int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 848{
ac146235 849#ifdef CONFIG_X86_64
c19986fe
JS		 850 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
851
852 if (pcid_enabled)
853 cr3 &= ~CR3_PCID_INVD;
ac146235 854#endif
9d88fca7 855
9f8fe504 856 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 857 kvm_mmu_sync_roots(vcpu);
77c3913b 858 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 859 return 0;
d835dfec
AK		 860 }
861
d1cd3ce9 862 if (is_long_mode(vcpu) &&
a780a3ea 863 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 864 return 1;
865 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 866 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 867 return 1;
a03490ed 868
0f12244f 869 vcpu->arch.cr3 = cr3;
aff48baa 870 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 871 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 872 return 0;
873}
2d3ad1f4 874EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 875
eea1cff9 876int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 877{
0f12244f
GN		 878 if (cr8 & CR8_RESERVED_BITS)
879 return 1;
35754c98 880 if (lapic_in_kernel(vcpu))
a03490ed
CO		 881 kvm_lapic_set_tpr(vcpu, cr8);
882 else
ad312c7c 883 vcpu->arch.cr8 = cr8;
0f12244f
GN		 884 return 0;
885}
2d3ad1f4 886EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 887
2d3ad1f4 888unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 889{
35754c98 890 if (lapic_in_kernel(vcpu))
a03490ed
CO		 891 return kvm_lapic_get_cr8(vcpu);
892 else
ad312c7c 893 return vcpu->arch.cr8;
a03490ed 894}
2d3ad1f4 895EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 896
ae561ede
NA		 897static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
898{
899 int i;
900
901 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
902 for (i = 0; i < KVM_NR_DB_REGS; i++)
903 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
904 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
905 }
906}
907
73aaf249
JK		 908static void kvm_update_dr6(struct kvm_vcpu *vcpu)
909{
910 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
911 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
912}
913
c8639010
JK		 914static void kvm_update_dr7(struct kvm_vcpu *vcpu)
915{
916 unsigned long dr7;
917
918 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
919 dr7 = vcpu->arch.guest_debug_dr7;
920 else
921 dr7 = vcpu->arch.dr7;
922 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 923 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
924 if (dr7 & DR7_BP_EN_MASK)
925 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 926}
927
6f43ed01
NA		 928static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
929{
930 u64 fixed = DR6_FIXED_1;
931
d6321d49 932 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 933 fixed |= DR6_RTM;
934 return fixed;
935}
936
338dbc97 937static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 938{
939 switch (dr) {
940 case 0 ... 3:
941 vcpu->arch.db[dr] = val;
942 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
943 vcpu->arch.eff_db[dr] = val;
944 break;
945 case 4:
020df079
GN		 946 /* fall through */
947 case 6:
338dbc97
GN		 948 if (val & 0xffffffff00000000ULL)
949 return -1; /* #GP */
6f43ed01 950 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 951 kvm_update_dr6(vcpu);
020df079
GN		 952 break;
953 case 5:
020df079
GN		 954 /* fall through */
955 default: /* 7 */
338dbc97
GN		 956 if (val & 0xffffffff00000000ULL)
957 return -1; /* #GP */
020df079 958 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 959 kvm_update_dr7(vcpu);
020df079
GN		 960 break;
961 }
962
963 return 0;
964}
338dbc97
GN		 965
966int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
967{
16f8a6f9 968 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 969 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 970 return 1;
971 }
972 return 0;
338dbc97 973}
020df079
GN		 974EXPORT_SYMBOL_GPL(kvm_set_dr);
975
16f8a6f9 976int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 977{
978 switch (dr) {
979 case 0 ... 3:
980 *val = vcpu->arch.db[dr];
981 break;
982 case 4:
020df079
GN		 983 /* fall through */
984 case 6:
73aaf249
JK		 985 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
986 *val = vcpu->arch.dr6;
987 else
988 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 989 break;
990 case 5:
020df079
GN		 991 /* fall through */
992 default: /* 7 */
993 *val = vcpu->arch.dr7;
994 break;
995 }
338dbc97
GN		 996 return 0;
997}
020df079
GN		 998EXPORT_SYMBOL_GPL(kvm_get_dr);
999
022cd0e8
AK		 1000bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1001{
1002 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1003 u64 data;
1004 int err;
1005
c6702c9d 1006 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1007 if (err)
1008 return err;
1009 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1010 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1011 return err;
1012}
1013EXPORT_SYMBOL_GPL(kvm_rdpmc);
1014
043405e1
CO		 1015/*
1016 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1017 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1018 *
1019 * This list is modified at module load time to reflect the
e3267cbb 1020 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1021 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1022 * may depend on host virtualization features rather than host cpu features.
043405e1 1023 */
e3267cbb 1024
043405e1
CO		 1025static u32 msrs_to_save[] = {
1026 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1027 MSR_STAR,
043405e1
CO		 1028#ifdef CONFIG_X86_64
1029 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1030#endif
b3897a49 1031 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1032 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1033 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1034};
1035
1036static unsigned num_msrs_to_save;
1037
62ef68bb
PB		 1038static u32 emulated_msrs[] = {
1039 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1040 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1041 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1042 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1043 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1044 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1045 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1046 HV_X64_MSR_RESET,
11c4b1ca 1047 HV_X64_MSR_VP_INDEX,
9eec50b8 1048 HV_X64_MSR_VP_RUNTIME,
5c919412 1049 HV_X64_MSR_SCONTROL,
1f4b34f8 1050 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1051 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1052 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1053 HV_X64_MSR_TSC_EMULATION_STATUS,
1054
1055 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1056 MSR_KVM_PV_EOI_EN,
1057
ba904635 1058 MSR_IA32_TSC_ADJUST,
a3e06bbe 1059 MSR_IA32_TSCDEADLINE,
043405e1 1060 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1061 MSR_IA32_MCG_STATUS,
1062 MSR_IA32_MCG_CTL,
c45dcc71 1063 MSR_IA32_MCG_EXT_CTL,
64d60670 1064 MSR_IA32_SMBASE,
52797bf9 1065 MSR_SMI_COUNT,
db2336a8
KH		 1066 MSR_PLATFORM_INFO,
1067 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1068};
1069
62ef68bb
PB		 1070static unsigned num_emulated_msrs;
1071
801e459a
TL		 1072/*
1073 * List of msr numbers which are used to expose MSR-based features that
1074 * can be used by a hypervisor to validate requested CPU features.
1075 */
1076static u32 msr_based_features[] = {
1389309c
PB		 1077 MSR_IA32_VMX_BASIC,
1078 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1079 MSR_IA32_VMX_PINBASED_CTLS,
1080 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1081 MSR_IA32_VMX_PROCBASED_CTLS,
1082 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1083 MSR_IA32_VMX_EXIT_CTLS,
1084 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1085 MSR_IA32_VMX_ENTRY_CTLS,
1086 MSR_IA32_VMX_MISC,
1087 MSR_IA32_VMX_CR0_FIXED0,
1088 MSR_IA32_VMX_CR0_FIXED1,
1089 MSR_IA32_VMX_CR4_FIXED0,
1090 MSR_IA32_VMX_CR4_FIXED1,
1091 MSR_IA32_VMX_VMCS_ENUM,
1092 MSR_IA32_VMX_PROCBASED_CTLS2,
1093 MSR_IA32_VMX_EPT_VPID_CAP,
1094 MSR_IA32_VMX_VMFUNC,
1095
d1d93fa9 1096 MSR_F10H_DECFG,
518e7b94 1097 MSR_IA32_UCODE_REV,
801e459a
TL		 1098};
1099
1100static unsigned int num_msr_based_features;
1101
66421c1e
WL		 1102static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1103{
1104 switch (msr->index) {
518e7b94
WL		 1105 case MSR_IA32_UCODE_REV:
1106 rdmsrl(msr->index, msr->data);
1107 break;
66421c1e
WL		 1108 default:
1109 if (kvm_x86_ops->get_msr_feature(msr))
1110 return 1;
1111 }
1112 return 0;
1113}
1114
801e459a
TL		 1115static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1116{
1117 struct kvm_msr_entry msr;
66421c1e 1118 int r;
801e459a
TL		 1119
1120 msr.index = index;
66421c1e
WL		 1121 r = kvm_get_msr_feature(&msr);
1122 if (r)
1123 return r;
801e459a
TL		 1124
1125 *data = msr.data;
1126
1127 return 0;
1128}
1129
384bb783 1130bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1131{
b69e8cae 1132 if (efer & efer_reserved_bits)
384bb783 1133 return false;
15c4a640 1134
1b4d56b8 1135 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1136 return false;
1b2fd70c 1137
1b4d56b8 1138 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1139 return false;
d8017474 1140
384bb783
JK		 1141 return true;
1142}
1143EXPORT_SYMBOL_GPL(kvm_valid_efer);
1144
1145static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1146{
1147 u64 old_efer = vcpu->arch.efer;
1148
1149 if (!kvm_valid_efer(vcpu, efer))
1150 return 1;
1151
1152 if (is_paging(vcpu)
1153 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1154 return 1;
1155
15c4a640 1156 efer &= ~EFER_LMA;
f6801dff 1157 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1158
a3d204e2
SY		 1159 kvm_x86_ops->set_efer(vcpu, efer);
1160
aad82703
SY		 1161 /* Update reserved bits */
1162 if ((efer ^ old_efer) & EFER_NX)
1163 kvm_mmu_reset_context(vcpu);
1164
b69e8cae 1165 return 0;
15c4a640
CO		 1166}
1167
f2b4b7dd
JR		 1168void kvm_enable_efer_bits(u64 mask)
1169{
1170 efer_reserved_bits &= ~mask;
1171}
1172EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1173
15c4a640
CO		 1174/*
1175 * Writes msr value into into the appropriate "register".
1176 * Returns 0 on success, non-0 otherwise.
1177 * Assumes vcpu_load() was already called.
1178 */
8fe8ab46 1179int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1180{
854e8bb1
NA		 1181 switch (msr->index) {
1182 case MSR_FS_BASE:
1183 case MSR_GS_BASE:
1184 case MSR_KERNEL_GS_BASE:
1185 case MSR_CSTAR:
1186 case MSR_LSTAR:
fd8cb433 1187 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1188 return 1;
1189 break;
1190 case MSR_IA32_SYSENTER_EIP:
1191 case MSR_IA32_SYSENTER_ESP:
1192 /*
1193 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1194 * non-canonical address is written on Intel but not on
1195 * AMD (which ignores the top 32-bits, because it does
1196 * not implement 64-bit SYSENTER).
1197 *
1198 * 64-bit code should hence be able to write a non-canonical
1199 * value on AMD. Making the address canonical ensures that
1200 * vmentry does not fail on Intel after writing a non-canonical
1201 * value, and that something deterministic happens if the guest
1202 * invokes 64-bit SYSENTER.
1203 */
fd8cb433 1204 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1205 }
8fe8ab46 1206 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1207}
854e8bb1 1208EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1209
313a3dc7
CO		 1210/*
1211 * Adapt set_msr() to msr_io()'s calling convention
1212 */
609e36d3
PB		 1213static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1214{
1215 struct msr_data msr;
1216 int r;
1217
1218 msr.index = index;
1219 msr.host_initiated = true;
1220 r = kvm_get_msr(vcpu, &msr);
1221 if (r)
1222 return r;
1223
1224 *data = msr.data;
1225 return 0;
1226}
1227
313a3dc7
CO		 1228static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1229{
8fe8ab46
WA		 1230 struct msr_data msr;
1231
1232 msr.data = *data;
1233 msr.index = index;
1234 msr.host_initiated = true;
1235 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1236}
1237
16e8d74d
MT		 1238#ifdef CONFIG_X86_64
1239struct pvclock_gtod_data {
1240 seqcount_t seq;
1241
1242 struct { /* extract of a clocksource struct */
1243 int vclock_mode;
a5a1d1c2
TG		 1244 u64 cycle_last;
1245 u64 mask;
16e8d74d
MT		 1246 u32 mult;
1247 u32 shift;
1248 } clock;
1249
cbcf2dd3
TG		 1250 u64 boot_ns;
1251 u64 nsec_base;
55dd00a7 1252 u64 wall_time_sec;
16e8d74d
MT		 1253};
1254
1255static struct pvclock_gtod_data pvclock_gtod_data;
1256
1257static void update_pvclock_gtod(struct timekeeper *tk)
1258{
1259 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1260 u64 boot_ns;
1261
876e7881 1262 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1263
1264 write_seqcount_begin(&vdata->seq);
1265
1266 /* copy pvclock gtod data */
876e7881
PZ		 1267 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1268 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1269 vdata->clock.mask = tk->tkr_mono.mask;
1270 vdata->clock.mult = tk->tkr_mono.mult;
1271 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1272
cbcf2dd3 1273 vdata->boot_ns = boot_ns;
876e7881 1274 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1275
55dd00a7
MT		 1276 vdata->wall_time_sec = tk->xtime_sec;
1277
16e8d74d
MT		 1278 write_seqcount_end(&vdata->seq);
1279}
1280#endif
1281
bab5bb39
NK		 1282void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1283{
1284 /*
1285 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1286 * vcpu_enter_guest. This function is only called from
1287 * the physical CPU that is running vcpu.
1288 */
1289 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1290}
16e8d74d 1291
18068523
GOC		 1292static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1293{
9ed3c444
AK		 1294 int version;
1295 int r;
50d0a0f9 1296 struct pvclock_wall_clock wc;
87aeb54f 1297 struct timespec64 boot;
18068523
GOC		 1298
1299 if (!wall_clock)
1300 return;
1301
9ed3c444
AK		 1302 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1303 if (r)
1304 return;
1305
1306 if (version & 1)
1307 ++version; /* first time write, random junk */
1308
1309 ++version;
18068523 1310
1dab1345
NK		 1311 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1312 return;
18068523 1313
50d0a0f9
GH		 1314 /*
1315 * The guest calculates current wall clock time by adding
34c238a1 1316 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1317 * wall clock specified here. guest system time equals host
1318 * system time for us, thus we must fill in host boot time here.
1319 */
87aeb54f 1320 getboottime64(&boot);
50d0a0f9 1321
4b648665 1322 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1323 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1324 boot = timespec64_sub(boot, ts);
4b648665 1325 }
87aeb54f 1326 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1327 wc.nsec = boot.tv_nsec;
1328 wc.version = version;
18068523
GOC		 1329
1330 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1331
1332 version++;
1333 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1334}
1335
50d0a0f9
GH		 1336static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1337{
b51012de
PB		 1338 do_shl32_div32(dividend, divisor);
1339 return dividend;
50d0a0f9
GH		 1340}
1341
3ae13faa 1342static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1343 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1344{
5f4e3f88 1345 uint64_t scaled64;
50d0a0f9
GH		 1346 int32_t shift = 0;
1347 uint64_t tps64;
1348 uint32_t tps32;
1349
3ae13faa
PB		 1350 tps64 = base_hz;
1351 scaled64 = scaled_hz;
50933623 1352 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1353 tps64 >>= 1;
1354 shift--;
1355 }
1356
1357 tps32 = (uint32_t)tps64;
50933623
JK		 1358 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1359 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1360 scaled64 >>= 1;
1361 else
1362 tps32 <<= 1;
50d0a0f9
GH		 1363 shift++;
1364 }
1365
5f4e3f88
ZA		 1366 *pshift = shift;
1367 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1368
3ae13faa
PB		 1369 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1370 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1371}
1372
d828199e 1373#ifdef CONFIG_X86_64
16e8d74d 1374static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1375#endif
16e8d74d 1376
c8076604 1377static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1378static unsigned long max_tsc_khz;
c8076604 1379
cc578287 1380static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1381{
cc578287
ZA		 1382 u64 v = (u64)khz * (1000000 + ppm);
1383 do_div(v, 1000000);
1384 return v;
1e993611
JR		 1385}
1386
381d585c
HZ		 1387static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1388{
1389 u64 ratio;
1390
1391 /* Guest TSC same frequency as host TSC? */
1392 if (!scale) {
1393 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1394 return 0;
1395 }
1396
1397 /* TSC scaling supported? */
1398 if (!kvm_has_tsc_control) {
1399 if (user_tsc_khz > tsc_khz) {
1400 vcpu->arch.tsc_catchup = 1;
1401 vcpu->arch.tsc_always_catchup = 1;
1402 return 0;
1403 } else {
1404 WARN(1, "user requested TSC rate below hardware speed\n");
1405 return -1;
1406 }
1407 }
1408
1409 /* TSC scaling required - calculate ratio */
1410 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1411 user_tsc_khz, tsc_khz);
1412
1413 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1414 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1415 user_tsc_khz);
1416 return -1;
1417 }
1418
1419 vcpu->arch.tsc_scaling_ratio = ratio;
1420 return 0;
1421}
1422
4941b8cb 1423static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1424{
cc578287
ZA		 1425 u32 thresh_lo, thresh_hi;
1426 int use_scaling = 0;
217fc9cf 1427
03ba32ca 1428 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1429 if (user_tsc_khz == 0) {
ad721883
HZ		 1430 /* set tsc_scaling_ratio to a safe value */
1431 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1432 return -1;
ad721883 1433 }
03ba32ca 1434
c285545f 1435 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1436 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1437 &vcpu->arch.virtual_tsc_shift,
1438 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1439 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1440
1441 /*
1442 * Compute the variation in TSC rate which is acceptable
1443 * within the range of tolerance and decide if the
1444 * rate being applied is within that bounds of the hardware
1445 * rate. If so, no scaling or compensation need be done.
1446 */
1447 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1448 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1449 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1450 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1451 use_scaling = 1;
1452 }
4941b8cb 1453 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1454}
1455
1456static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1457{
e26101b1 1458 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1459 vcpu->arch.virtual_tsc_mult,
1460 vcpu->arch.virtual_tsc_shift);
e26101b1 1461 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1462 return tsc;
1463}
1464
b0c39dc6
VK		 1465static inline int gtod_is_based_on_tsc(int mode)
1466{
1467 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1468}
1469
69b0049a 1470static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1471{
1472#ifdef CONFIG_X86_64
1473 bool vcpus_matched;
b48aa97e
MT		 1474 struct kvm_arch *ka = &vcpu->kvm->arch;
1475 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1476
1477 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1478 atomic_read(&vcpu->kvm->online_vcpus));
1479
7f187922
MT		 1480 /*
1481 * Once the masterclock is enabled, always perform request in
1482 * order to update it.
1483 *
1484 * In order to enable masterclock, the host clocksource must be TSC
1485 * and the vcpus need to have matched TSCs. When that happens,
1486 * perform request to enable masterclock.
1487 */
1488 if (ka->use_master_clock ||
b0c39dc6 1489 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1490 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1491
1492 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1493 atomic_read(&vcpu->kvm->online_vcpus),
1494 ka->use_master_clock, gtod->clock.vclock_mode);
1495#endif
1496}
1497
ba904635
WA		 1498static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1499{
e79f245d 1500 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1501 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1502}
1503
35181e86
HZ		 1504/*
1505 * Multiply tsc by a fixed point number represented by ratio.
1506 *
1507 * The most significant 64-N bits (mult) of ratio represent the
1508 * integral part of the fixed point number; the remaining N bits
1509 * (frac) represent the fractional part, ie. ratio represents a fixed
1510 * point number (mult + frac * 2^(-N)).
1511 *
1512 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1513 */
1514static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1515{
1516 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1517}
1518
1519u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1520{
1521 u64 _tsc = tsc;
1522 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1523
1524 if (ratio != kvm_default_tsc_scaling_ratio)
1525 _tsc = __scale_tsc(ratio, tsc);
1526
1527 return _tsc;
1528}
1529EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1530
07c1419a
HZ		 1531static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1532{
1533 u64 tsc;
1534
1535 tsc = kvm_scale_tsc(vcpu, rdtsc());
1536
1537 return target_tsc - tsc;
1538}
1539
4ba76538
HZ		 1540u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1541{
e79f245d
KA		 1542 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1543
1544 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1545}
1546EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1547
a545ab6a
LC		 1548static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1549{
1550 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1551 vcpu->arch.tsc_offset = offset;
1552}
1553
b0c39dc6
VK		 1554static inline bool kvm_check_tsc_unstable(void)
1555{
1556#ifdef CONFIG_X86_64
1557 /*
1558 * TSC is marked unstable when we're running on Hyper-V,
1559 * 'TSC page' clocksource is good.
1560 */
1561 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1562 return false;
1563#endif
1564 return check_tsc_unstable();
1565}
1566
8fe8ab46 1567void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1568{
1569 struct kvm *kvm = vcpu->kvm;
f38e098f 1570 u64 offset, ns, elapsed;
99e3e30a 1571 unsigned long flags;
b48aa97e 1572 bool matched;
0d3da0d2 1573 bool already_matched;
8fe8ab46 1574 u64 data = msr->data;
c5e8ec8e 1575 bool synchronizing = false;
99e3e30a 1576
038f8c11 1577 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1578 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1579 ns = ktime_get_boot_ns();
f38e098f 1580 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1581
03ba32ca 1582 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1583 if (data == 0 && msr->host_initiated) {
1584 /*
1585 * detection of vcpu initialization -- need to sync
1586 * with other vCPUs. This particularly helps to keep
1587 * kvm_clock stable after CPU hotplug
1588 */
1589 synchronizing = true;
1590 } else {
1591 u64 tsc_exp = kvm->arch.last_tsc_write +
1592 nsec_to_cycles(vcpu, elapsed);
1593 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1594 /*
1595 * Special case: TSC write with a small delta (1 second)
1596 * of virtual cycle time against real time is
1597 * interpreted as an attempt to synchronize the CPU.
1598 */
1599 synchronizing = data < tsc_exp + tsc_hz &&
1600 data + tsc_hz > tsc_exp;
1601 }
c5e8ec8e 1602 }
f38e098f
ZA		 1603
1604 /*
5d3cb0f6
ZA		 1605 * For a reliable TSC, we can match TSC offsets, and for an unstable
1606 * TSC, we add elapsed time in this computation. We could let the
1607 * compensation code attempt to catch up if we fall behind, but
1608 * it's better to try to match offsets from the beginning.
1609 */
c5e8ec8e 1610 if (synchronizing &&
5d3cb0f6 1611 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1612 if (!kvm_check_tsc_unstable()) {
e26101b1 1613 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1614 pr_debug("kvm: matched tsc offset for %llu\n", data);
1615 } else {
857e4099 1616 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1617 data += delta;
07c1419a 1618 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1619 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1620 }
b48aa97e 1621 matched = true;
0d3da0d2 1622 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1623 } else {
1624 /*
1625 * We split periods of matched TSC writes into generations.
1626 * For each generation, we track the original measured
1627 * nanosecond time, offset, and write, so if TSCs are in
1628 * sync, we can match exact offset, and if not, we can match
4a969980 1629 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1630 *
1631 * These values are tracked in kvm->arch.cur_xxx variables.
1632 */
1633 kvm->arch.cur_tsc_generation++;
1634 kvm->arch.cur_tsc_nsec = ns;
1635 kvm->arch.cur_tsc_write = data;
1636 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1637 matched = false;
0d3da0d2 1638 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1639 kvm->arch.cur_tsc_generation, data);
f38e098f 1640 }
e26101b1
ZA		 1641
1642 /*
1643 * We also track th most recent recorded KHZ, write and time to
1644 * allow the matching interval to be extended at each write.
1645 */
f38e098f
ZA		 1646 kvm->arch.last_tsc_nsec = ns;
1647 kvm->arch.last_tsc_write = data;
5d3cb0f6 1648 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1649
b183aa58 1650 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1651
1652 /* Keep track of which generation this VCPU has synchronized to */
1653 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1654 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1655 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1656
d6321d49 1657 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1658 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1659
a545ab6a 1660 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1661 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1662
1663 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1664 if (!matched) {
b48aa97e 1665 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1666 } else if (!already_matched) {
1667 kvm->arch.nr_vcpus_matched_tsc++;
1668 }
b48aa97e
MT		 1669
1670 kvm_track_tsc_matching(vcpu);
1671 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1672}
e26101b1 1673
99e3e30a
ZA		 1674EXPORT_SYMBOL_GPL(kvm_write_tsc);
1675
58ea6767
HZ		 1676static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1677 s64 adjustment)
1678{
ea26e4ec 1679 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1680}
1681
1682static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1683{
1684 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1685 WARN_ON(adjustment < 0);
1686 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1687 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1688}
1689
d828199e
MT		 1690#ifdef CONFIG_X86_64
1691
a5a1d1c2 1692static u64 read_tsc(void)
d828199e 1693{
a5a1d1c2 1694 u64 ret = (u64)rdtsc_ordered();
03b9730b 1695 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1696
1697 if (likely(ret >= last))
1698 return ret;
1699
1700 /*
1701 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1702 * predictable (it's just a function of time and the likely is
d828199e
MT		 1703 * very likely) and there's a data dependence, so force GCC
1704 * to generate a branch instead. I don't barrier() because
1705 * we don't actually need a barrier, and if this function
1706 * ever gets inlined it will generate worse code.
1707 */
1708 asm volatile ("");
1709 return last;
1710}
1711
b0c39dc6 1712static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1713{
1714 long v;
1715 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1716 u64 tsc_pg_val;
1717
1718 switch (gtod->clock.vclock_mode) {
1719 case VCLOCK_HVCLOCK:
1720 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1721 tsc_timestamp);
1722 if (tsc_pg_val != U64_MAX) {
1723 /* TSC page valid */
1724 *mode = VCLOCK_HVCLOCK;
1725 v = (tsc_pg_val - gtod->clock.cycle_last) &
1726 gtod->clock.mask;
1727 } else {
1728 /* TSC page invalid */
1729 *mode = VCLOCK_NONE;
1730 }
1731 break;
1732 case VCLOCK_TSC:
1733 *mode = VCLOCK_TSC;
1734 *tsc_timestamp = read_tsc();
1735 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1736 gtod->clock.mask;
1737 break;
1738 default:
1739 *mode = VCLOCK_NONE;
1740 }
d828199e 1741
b0c39dc6
VK		 1742 if (*mode == VCLOCK_NONE)
1743 *tsc_timestamp = v = 0;
d828199e 1744
d828199e
MT		 1745 return v * gtod->clock.mult;
1746}
1747
b0c39dc6 1748static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1749{
cbcf2dd3 1750 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1751 unsigned long seq;
d828199e 1752 int mode;
cbcf2dd3 1753 u64 ns;
d828199e 1754
d828199e
MT		 1755 do {
1756 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1757 ns = gtod->nsec_base;
b0c39dc6 1758 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1759 ns >>= gtod->clock.shift;
cbcf2dd3 1760 ns += gtod->boot_ns;
d828199e 1761 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1762 *t = ns;
d828199e
MT		 1763
1764 return mode;
1765}
1766
899a31f5 1767static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1768{
1769 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1770 unsigned long seq;
1771 int mode;
1772 u64 ns;
1773
1774 do {
1775 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1776 ts->tv_sec = gtod->wall_time_sec;
1777 ns = gtod->nsec_base;
b0c39dc6 1778 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1779 ns >>= gtod->clock.shift;
1780 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1781
1782 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1783 ts->tv_nsec = ns;
1784
1785 return mode;
1786}
1787
b0c39dc6
VK		 1788/* returns true if host is using TSC based clocksource */
1789static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1790{
d828199e 1791 /* checked again under seqlock below */
b0c39dc6 1792 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1793 return false;
1794
b0c39dc6
VK		 1795 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1796 tsc_timestamp));
d828199e 1797}
55dd00a7 1798
b0c39dc6 1799/* returns true if host is using TSC based clocksource */
899a31f5 1800static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1801 u64 *tsc_timestamp)
55dd00a7
MT		 1802{
1803 /* checked again under seqlock below */
b0c39dc6 1804 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1805 return false;
1806
b0c39dc6 1807 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1808}
d828199e
MT		 1809#endif
1810
1811/*
1812 *
b48aa97e
MT		 1813 * Assuming a stable TSC across physical CPUS, and a stable TSC
1814 * across virtual CPUs, the following condition is possible.
1815 * Each numbered line represents an event visible to both
d828199e
MT		 1816 * CPUs at the next numbered event.
1817 *
1818 * "timespecX" represents host monotonic time. "tscX" represents
1819 * RDTSC value.
1820 *
1821 * VCPU0 on CPU0 | VCPU1 on CPU1
1822 *
1823 * 1. read timespec0,tsc0
1824 * 2. | timespec1 = timespec0 + N
1825 * | tsc1 = tsc0 + M
1826 * 3. transition to guest | transition to guest
1827 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1828 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1829 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1830 *
1831 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1832 *
1833 * - ret0 < ret1
1834 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1835 * ...
1836 * - 0 < N - M => M < N
1837 *
1838 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1839 * always the case (the difference between two distinct xtime instances
1840 * might be smaller then the difference between corresponding TSC reads,
1841 * when updating guest vcpus pvclock areas).
1842 *
1843 * To avoid that problem, do not allow visibility of distinct
1844 * system_timestamp/tsc_timestamp values simultaneously: use a master
1845 * copy of host monotonic time values. Update that master copy
1846 * in lockstep.
1847 *
b48aa97e 1848 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1849 *
1850 */
1851
1852static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1853{
1854#ifdef CONFIG_X86_64
1855 struct kvm_arch *ka = &kvm->arch;
1856 int vclock_mode;
b48aa97e
MT		 1857 bool host_tsc_clocksource, vcpus_matched;
1858
1859 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1860 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1861
1862 /*
1863 * If the host uses TSC clock, then passthrough TSC as stable
1864 * to the guest.
1865 */
b48aa97e 1866 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1867 &ka->master_kernel_ns,
1868 &ka->master_cycle_now);
1869
16a96021 1870 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1871 && !ka->backwards_tsc_observed
54750f2c 1872 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1873
d828199e
MT		 1874 if (ka->use_master_clock)
1875 atomic_set(&kvm_guest_has_master_clock, 1);
1876
1877 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1878 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1879 vcpus_matched);
d828199e
MT		 1880#endif
1881}
1882
2860c4b1
PB		 1883void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1884{
1885 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1886}
1887
2e762ff7
MT		 1888static void kvm_gen_update_masterclock(struct kvm *kvm)
1889{
1890#ifdef CONFIG_X86_64
1891 int i;
1892 struct kvm_vcpu *vcpu;
1893 struct kvm_arch *ka = &kvm->arch;
1894
1895 spin_lock(&ka->pvclock_gtod_sync_lock);
1896 kvm_make_mclock_inprogress_request(kvm);
1897 /* no guest entries from this point */
1898 pvclock_update_vm_gtod_copy(kvm);
1899
1900 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1901 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1902
1903 /* guest entries allowed */
1904 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1905 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1906
1907 spin_unlock(&ka->pvclock_gtod_sync_lock);
1908#endif
1909}
1910
e891a32e 1911u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1912{
108b249c 1913 struct kvm_arch *ka = &kvm->arch;
8b953440 1914 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1915 u64 ret;
108b249c 1916
8b953440
PB		 1917 spin_lock(&ka->pvclock_gtod_sync_lock);
1918 if (!ka->use_master_clock) {
1919 spin_unlock(&ka->pvclock_gtod_sync_lock);
1920 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1921 }
1922
8b953440
PB		 1923 hv_clock.tsc_timestamp = ka->master_cycle_now;
1924 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1925 spin_unlock(&ka->pvclock_gtod_sync_lock);
1926
e2c2206a
WL		 1927 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1928 get_cpu();
1929
e70b57a6
WL		 1930 if (__this_cpu_read(cpu_tsc_khz)) {
1931 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1932 &hv_clock.tsc_shift,
1933 &hv_clock.tsc_to_system_mul);
1934 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1935 } else
1936 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1937
1938 put_cpu();
1939
1940 return ret;
108b249c
PB		 1941}
1942
0d6dd2ff
PB		 1943static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1944{
1945 struct kvm_vcpu_arch *vcpu = &v->arch;
1946 struct pvclock_vcpu_time_info guest_hv_clock;
1947
4e335d9e 1948 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1949 &guest_hv_clock, sizeof(guest_hv_clock))))
1950 return;
1951
1952 /* This VCPU is paused, but it's legal for a guest to read another
1953 * VCPU's kvmclock, so we really have to follow the specification where
1954 * it says that version is odd if data is being modified, and even after
1955 * it is consistent.
1956 *
1957 * Version field updates must be kept separate. This is because
1958 * kvm_write_guest_cached might use a "rep movs" instruction, and
1959 * writes within a string instruction are weakly ordered. So there
1960 * are three writes overall.
1961 *
1962 * As a small optimization, only write the version field in the first
1963 * and third write. The vcpu->pv_time cache is still valid, because the
1964 * version field is the first in the struct.
1965 */
1966 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1967
51c4b8bb
LA		 1968 if (guest_hv_clock.version & 1)
1969 ++guest_hv_clock.version; /* first time write, random junk */
1970
0d6dd2ff 1971 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1972 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1973 &vcpu->hv_clock,
1974 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1975
1976 smp_wmb();
1977
1978 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1979 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1980
1981 if (vcpu->pvclock_set_guest_stopped_request) {
1982 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1983 vcpu->pvclock_set_guest_stopped_request = false;
1984 }
1985
1986 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1987
4e335d9e
PB		 1988 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1989 &vcpu->hv_clock,
1990 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1991
1992 smp_wmb();
1993
1994 vcpu->hv_clock.version++;
4e335d9e
PB		 1995 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1996 &vcpu->hv_clock,
1997 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1998}
1999
34c238a1 2000static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2001{
78db6a50 2002 unsigned long flags, tgt_tsc_khz;
18068523 2003 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2004 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2005 s64 kernel_ns;
d828199e 2006 u64 tsc_timestamp, host_tsc;
51d59c6b 2007 u8 pvclock_flags;
d828199e
MT		 2008 bool use_master_clock;
2009
2010 kernel_ns = 0;
2011 host_tsc = 0;
18068523 2012
d828199e
MT		 2013 /*
2014 * If the host uses TSC clock, then passthrough TSC as stable
2015 * to the guest.
2016 */
2017 spin_lock(&ka->pvclock_gtod_sync_lock);
2018 use_master_clock = ka->use_master_clock;
2019 if (use_master_clock) {
2020 host_tsc = ka->master_cycle_now;
2021 kernel_ns = ka->master_kernel_ns;
2022 }
2023 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2024
2025 /* Keep irq disabled to prevent changes to the clock */
2026 local_irq_save(flags);
78db6a50
PB		 2027 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2028 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2029 local_irq_restore(flags);
2030 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2031 return 1;
2032 }
d828199e 2033 if (!use_master_clock) {
4ea1636b 2034 host_tsc = rdtsc();
108b249c 2035 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2036 }
2037
4ba76538 2038 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2039
c285545f
ZA		 2040 /*
2041 * We may have to catch up the TSC to match elapsed wall clock
2042 * time for two reasons, even if kvmclock is used.
2043 * 1) CPU could have been running below the maximum TSC rate
2044 * 2) Broken TSC compensation resets the base at each VCPU
2045 * entry to avoid unknown leaps of TSC even when running
2046 * again on the same CPU. This may cause apparent elapsed
2047 * time to disappear, and the guest to stand still or run
2048 * very slowly.
2049 */
2050 if (vcpu->tsc_catchup) {
2051 u64 tsc = compute_guest_tsc(v, kernel_ns);
2052 if (tsc > tsc_timestamp) {
f1e2b260 2053 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2054 tsc_timestamp = tsc;
2055 }
50d0a0f9
GH		 2056 }
2057
18068523
GOC		 2058 local_irq_restore(flags);
2059
0d6dd2ff 2060 /* With all the info we got, fill in the values */
18068523 2061
78db6a50
PB		 2062 if (kvm_has_tsc_control)
2063 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2064
2065 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2066 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2067 &vcpu->hv_clock.tsc_shift,
2068 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2069 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2070 }
2071
1d5f066e 2072 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2073 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2074 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2075
d828199e 2076 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2077 pvclock_flags = 0;
d828199e
MT		 2078 if (use_master_clock)
2079 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2080
78c0337a
MT		 2081 vcpu->hv_clock.flags = pvclock_flags;
2082
095cf55d
PB		 2083 if (vcpu->pv_time_enabled)
2084 kvm_setup_pvclock_page(v);
2085 if (v == kvm_get_vcpu(v->kvm, 0))
2086 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2087 return 0;
c8076604
GH		 2088}
2089
0061d53d
MT		 2090/*
2091 * kvmclock updates which are isolated to a given vcpu, such as
2092 * vcpu->cpu migration, should not allow system_timestamp from
2093 * the rest of the vcpus to remain static. Otherwise ntp frequency
2094 * correction applies to one vcpu's system_timestamp but not
2095 * the others.
2096 *
2097 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2098 * We need to rate-limit these requests though, as they can
2099 * considerably slow guests that have a large number of vcpus.
2100 * The time for a remote vcpu to update its kvmclock is bound
2101 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2102 */
2103
7e44e449
AJ		 2104#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2105
2106static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2107{
2108 int i;
7e44e449
AJ		 2109 struct delayed_work *dwork = to_delayed_work(work);
2110 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2111 kvmclock_update_work);
2112 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2113 struct kvm_vcpu *vcpu;
2114
2115 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2116 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2117 kvm_vcpu_kick(vcpu);
2118 }
2119}
2120
7e44e449
AJ		 2121static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2122{
2123 struct kvm *kvm = v->kvm;
2124
105b21bb 2125 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2126 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2127 KVMCLOCK_UPDATE_DELAY);
2128}
2129
332967a3
AJ		 2130#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2131
2132static void kvmclock_sync_fn(struct work_struct *work)
2133{
2134 struct delayed_work *dwork = to_delayed_work(work);
2135 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2136 kvmclock_sync_work);
2137 struct kvm *kvm = container_of(ka, struct kvm, arch);
2138
630994b3
MT		 2139 if (!kvmclock_periodic_sync)
2140 return;
2141
332967a3
AJ		 2142 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2143 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2144 KVMCLOCK_SYNC_PERIOD);
2145}
2146
9ffd986c 2147static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2148{
890ca9ae
HY		 2149 u64 mcg_cap = vcpu->arch.mcg_cap;
2150 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2151 u32 msr = msr_info->index;
2152 u64 data = msr_info->data;
890ca9ae 2153
15c4a640 2154 switch (msr) {
15c4a640 2155 case MSR_IA32_MCG_STATUS:
890ca9ae 2156 vcpu->arch.mcg_status = data;
15c4a640 2157 break;
c7ac679c 2158 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2159 if (!(mcg_cap & MCG_CTL_P))
2160 return 1;
2161 if (data != 0 && data != ~(u64)0)
2162 return -1;
2163 vcpu->arch.mcg_ctl = data;
2164 break;
2165 default:
2166 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2167 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2168 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2169 /* only 0 or all 1s can be written to IA32_MCi_CTL
2170 * some Linux kernels though clear bit 10 in bank 4 to
2171 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2172 * this to avoid an uncatched #GP in the guest
2173 */
890ca9ae 2174 if ((offset & 0x3) == 0 &&
114be429 2175 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2176 return -1;
9ffd986c
WL		 2177 if (!msr_info->host_initiated &&
2178 (offset & 0x3) == 1 && data != 0)
2179 return -1;
890ca9ae
HY		 2180 vcpu->arch.mce_banks[offset] = data;
2181 break;
2182 }
2183 return 1;
2184 }
2185 return 0;
2186}
2187
ffde22ac
ES		 2188static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2189{
2190 struct kvm *kvm = vcpu->kvm;
2191 int lm = is_long_mode(vcpu);
2192 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2193 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2194 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2195 : kvm->arch.xen_hvm_config.blob_size_32;
2196 u32 page_num = data & ~PAGE_MASK;
2197 u64 page_addr = data & PAGE_MASK;
2198 u8 *page;
2199 int r;
2200
2201 r = -E2BIG;
2202 if (page_num >= blob_size)
2203 goto out;
2204 r = -ENOMEM;
ff5c2c03
SL		 2205 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2206 if (IS_ERR(page)) {
2207 r = PTR_ERR(page);
ffde22ac 2208 goto out;
ff5c2c03 2209 }
54bf36aa 2210 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2211 goto out_free;
2212 r = 0;
2213out_free:
2214 kfree(page);
2215out:
2216 return r;
2217}
2218
344d9588
GN		 2219static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2220{
2221 gpa_t gpa = data & ~0x3f;
2222
52a5c155
WL		 2223 /* Bits 3:5 are reserved, Should be zero */
2224 if (data & 0x38)
344d9588
GN		 2225 return 1;
2226
2227 vcpu->arch.apf.msr_val = data;
2228
2229 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2230 kvm_clear_async_pf_completion_queue(vcpu);
2231 kvm_async_pf_hash_reset(vcpu);
2232 return 0;
2233 }
2234
4e335d9e 2235 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2236 sizeof(u32)))
344d9588
GN		 2237 return 1;
2238
6adba527 2239 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2240 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2241 kvm_async_pf_wakeup_all(vcpu);
2242 return 0;
2243}
2244
12f9a48f
GC		 2245static void kvmclock_reset(struct kvm_vcpu *vcpu)
2246{
0b79459b 2247 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2248}
2249
f38a7b75
WL		 2250static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2251{
2252 ++vcpu->stat.tlb_flush;
2253 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2254}
2255
c9aaa895
GC		 2256static void record_steal_time(struct kvm_vcpu *vcpu)
2257{
2258 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2259 return;
2260
4e335d9e 2261 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2262 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2263 return;
2264
f38a7b75
WL		 2265 /*
2266 * Doing a TLB flush here, on the guest's behalf, can avoid
2267 * expensive IPIs.
2268 */
2269 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2270 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2271
35f3fae1
WL		 2272 if (vcpu->arch.st.steal.version & 1)
2273 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2274
2275 vcpu->arch.st.steal.version += 1;
2276
4e335d9e 2277 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2278 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2279
2280 smp_wmb();
2281
c54cdf14
LC		 2282 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2283 vcpu->arch.st.last_steal;
2284 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2285
4e335d9e 2286 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2287 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2288
2289 smp_wmb();
2290
2291 vcpu->arch.st.steal.version += 1;
c9aaa895 2292
4e335d9e 2293 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2294 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2295}
2296
8fe8ab46 2297int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2298{
5753785f 2299 bool pr = false;
8fe8ab46
WA		 2300 u32 msr = msr_info->index;
2301 u64 data = msr_info->data;
5753785f 2302
15c4a640 2303 switch (msr) {
2e32b719 2304 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2305 case MSR_IA32_UCODE_WRITE:
2306 case MSR_VM_HSAVE_PA:
2307 case MSR_AMD64_PATCH_LOADER:
2308 case MSR_AMD64_BU_CFG2:
405a353a 2309 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2310 break;
2311
518e7b94
WL		 2312 case MSR_IA32_UCODE_REV:
2313 if (msr_info->host_initiated)
2314 vcpu->arch.microcode_version = data;
2315 break;
15c4a640 2316 case MSR_EFER:
b69e8cae 2317 return set_efer(vcpu, data);
8f1589d9
AP		 2318 case MSR_K7_HWCR:
2319 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2320 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2321 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2322 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2323 if (data != 0) {
a737f256
CD		 2324 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2325 data);
8f1589d9
AP		 2326 return 1;
2327 }
15c4a640 2328 break;
f7c6d140
AP		 2329 case MSR_FAM10H_MMIO_CONF_BASE:
2330 if (data != 0) {
a737f256
CD		 2331 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2332 "0x%llx\n", data);
f7c6d140
AP		 2333 return 1;
2334 }
15c4a640 2335 break;
b5e2fec0
AG		 2336 case MSR_IA32_DEBUGCTLMSR:
2337 if (!data) {
2338 /* We support the non-activated case already */
2339 break;
2340 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2341 /* Values other than LBR and BTF are vendor-specific,
2342 thus reserved and should throw a #GP */
2343 return 1;
2344 }
a737f256
CD		 2345 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2346 __func__, data);
b5e2fec0 2347 break;
9ba075a6 2348 case 0x200 ... 0x2ff:
ff53604b 2349 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2350 case MSR_IA32_APICBASE:
58cb628d 2351 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2352 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2353 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2354 case MSR_IA32_TSCDEADLINE:
2355 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2356 break;
ba904635 2357 case MSR_IA32_TSC_ADJUST:
d6321d49 2358 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2359 if (!msr_info->host_initiated) {
d913b904 2360 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2361 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2362 }
2363 vcpu->arch.ia32_tsc_adjust_msr = data;
2364 }
2365 break;
15c4a640 2366 case MSR_IA32_MISC_ENABLE:
ad312c7c 2367 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2368 break;
64d60670
PB		 2369 case MSR_IA32_SMBASE:
2370 if (!msr_info->host_initiated)
2371 return 1;
2372 vcpu->arch.smbase = data;
2373 break;
dd259935
PB		 2374 case MSR_IA32_TSC:
2375 kvm_write_tsc(vcpu, msr_info);
2376 break;
52797bf9
LA		 2377 case MSR_SMI_COUNT:
2378 if (!msr_info->host_initiated)
2379 return 1;
2380 vcpu->arch.smi_count = data;
2381 break;
11c6bffa 2382 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2383 case MSR_KVM_WALL_CLOCK:
2384 vcpu->kvm->arch.wall_clock = data;
2385 kvm_write_wall_clock(vcpu->kvm, data);
2386 break;
11c6bffa 2387 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2388 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2389 struct kvm_arch *ka = &vcpu->kvm->arch;
2390
12f9a48f 2391 kvmclock_reset(vcpu);
18068523 2392
54750f2c
MT		 2393 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2394 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2395
2396 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2397 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2398
2399 ka->boot_vcpu_runs_old_kvmclock = tmp;
2400 }
2401
18068523 2402 vcpu->arch.time = data;
0061d53d 2403 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2404
2405 /* we verify if the enable bit is set... */
2406 if (!(data & 1))
2407 break;
2408
4e335d9e 2409 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2410 &vcpu->arch.pv_time, data & ~1ULL,
2411 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2412 vcpu->arch.pv_time_enabled = false;
2413 else
2414 vcpu->arch.pv_time_enabled = true;
32cad84f 2415
18068523
GOC		 2416 break;
2417 }
344d9588
GN		 2418 case MSR_KVM_ASYNC_PF_EN:
2419 if (kvm_pv_enable_async_pf(vcpu, data))
2420 return 1;
2421 break;
c9aaa895
GC		 2422 case MSR_KVM_STEAL_TIME:
2423
2424 if (unlikely(!sched_info_on()))
2425 return 1;
2426
2427 if (data & KVM_STEAL_RESERVED_MASK)
2428 return 1;
2429
4e335d9e 2430 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2431 data & KVM_STEAL_VALID_BITS,
2432 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2433 return 1;
2434
2435 vcpu->arch.st.msr_val = data;
2436
2437 if (!(data & KVM_MSR_ENABLED))
2438 break;
2439
c9aaa895
GC		 2440 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2441
2442 break;
ae7a2a3f
MT		 2443 case MSR_KVM_PV_EOI_EN:
2444 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2445 return 1;
2446 break;
c9aaa895 2447
890ca9ae
HY		 2448 case MSR_IA32_MCG_CTL:
2449 case MSR_IA32_MCG_STATUS:
81760dcc 2450 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2451 return set_msr_mce(vcpu, msr_info);
71db6023 2452
6912ac32
WH		 2453 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2454 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2455 pr = true; /* fall through */
2456 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2457 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2458 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2459 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2460
2461 if (pr || data != 0)
a737f256
CD		 2462 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2463 "0x%x data 0x%llx\n", msr, data);
5753785f 2464 break;
84e0cefa
JS		 2465 case MSR_K7_CLK_CTL:
2466 /*
2467 * Ignore all writes to this no longer documented MSR.
2468 * Writes are only relevant for old K7 processors,
2469 * all pre-dating SVM, but a recommended workaround from
4a969980 2470 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2471 * affected processor models on the command line, hence
2472 * the need to ignore the workaround.
2473 */
2474 break;
55cd8e5a 2475 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2476 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2477 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2478 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2479 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2480 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2481 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2482 return kvm_hv_set_msr_common(vcpu, msr, data,
2483 msr_info->host_initiated);
91c9c3ed 2484 case MSR_IA32_BBL_CR_CTL3:
2485 /* Drop writes to this legacy MSR -- see rdmsr
2486 * counterpart for further detail.
2487 */
fab0aa3b
EM		 2488 if (report_ignored_msrs)
2489 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2490 msr, data);
91c9c3ed 2491 break;
2b036c6b 2492 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2493 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2494 return 1;
2495 vcpu->arch.osvw.length = data;
2496 break;
2497 case MSR_AMD64_OSVW_STATUS:
d6321d49 2498 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2499 return 1;
2500 vcpu->arch.osvw.status = data;
2501 break;
db2336a8
KH		 2502 case MSR_PLATFORM_INFO:
2503 if (!msr_info->host_initiated ||
2504 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2505 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2506 cpuid_fault_enabled(vcpu)))
2507 return 1;
2508 vcpu->arch.msr_platform_info = data;
2509 break;
2510 case MSR_MISC_FEATURES_ENABLES:
2511 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2512 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2513 !supports_cpuid_fault(vcpu)))
2514 return 1;
2515 vcpu->arch.msr_misc_features_enables = data;
2516 break;
15c4a640 2517 default:
ffde22ac
ES		 2518 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2519 return xen_hvm_config(vcpu, data);
c6702c9d 2520 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2521 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2522 if (!ignore_msrs) {
ae0f5499 2523 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2524 msr, data);
ed85c068
AP		 2525 return 1;
2526 } else {
fab0aa3b
EM		 2527 if (report_ignored_msrs)
2528 vcpu_unimpl(vcpu,
2529 "ignored wrmsr: 0x%x data 0x%llx\n",
2530 msr, data);
ed85c068
AP		 2531 break;
2532 }
15c4a640
CO		 2533 }
2534 return 0;
2535}
2536EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2537
2538
2539/*
2540 * Reads an msr value (of 'msr_index') into 'pdata'.
2541 * Returns 0 on success, non-0 otherwise.
2542 * Assumes vcpu_load() was already called.
2543 */
609e36d3 2544int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2545{
609e36d3 2546 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2547}
ff651cb6 2548EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2549
890ca9ae 2550static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2551{
2552 u64 data;
890ca9ae
HY		 2553 u64 mcg_cap = vcpu->arch.mcg_cap;
2554 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2555
2556 switch (msr) {
15c4a640
CO		 2557 case MSR_IA32_P5_MC_ADDR:
2558 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2559 data = 0;
2560 break;
15c4a640 2561 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2562 data = vcpu->arch.mcg_cap;
2563 break;
c7ac679c 2564 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2565 if (!(mcg_cap & MCG_CTL_P))
2566 return 1;
2567 data = vcpu->arch.mcg_ctl;
2568 break;
2569 case MSR_IA32_MCG_STATUS:
2570 data = vcpu->arch.mcg_status;
2571 break;
2572 default:
2573 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2574 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2575 u32 offset = msr - MSR_IA32_MC0_CTL;
2576 data = vcpu->arch.mce_banks[offset];
2577 break;
2578 }
2579 return 1;
2580 }
2581 *pdata = data;
2582 return 0;
2583}
2584
609e36d3 2585int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2586{
609e36d3 2587 switch (msr_info->index) {
890ca9ae 2588 case MSR_IA32_PLATFORM_ID:
15c4a640 2589 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2590 case MSR_IA32_DEBUGCTLMSR:
2591 case MSR_IA32_LASTBRANCHFROMIP:
2592 case MSR_IA32_LASTBRANCHTOIP:
2593 case MSR_IA32_LASTINTFROMIP:
2594 case MSR_IA32_LASTINTTOIP:
60af2ecd 2595 case MSR_K8_SYSCFG:
3afb1121
PB		 2596 case MSR_K8_TSEG_ADDR:
2597 case MSR_K8_TSEG_MASK:
60af2ecd 2598 case MSR_K7_HWCR:
61a6bd67 2599 case MSR_VM_HSAVE_PA:
1fdbd48c 2600 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2601 case MSR_AMD64_NB_CFG:
f7c6d140 2602 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2603 case MSR_AMD64_BU_CFG2:
0c2df2a1 2604 case MSR_IA32_PERF_CTL:
405a353a 2605 case MSR_AMD64_DC_CFG:
609e36d3 2606 msr_info->data = 0;
15c4a640 2607 break;
c51eb52b 2608 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2609 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2610 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2611 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2612 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2613 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2614 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2615 msr_info->data = 0;
5753785f 2616 break;
742bc670 2617 case MSR_IA32_UCODE_REV:
518e7b94 2618 msr_info->data = vcpu->arch.microcode_version;
742bc670 2619 break;
dd259935
PB		 2620 case MSR_IA32_TSC:
2621 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2622 break;
9ba075a6 2623 case MSR_MTRRcap:
9ba075a6 2624 case 0x200 ... 0x2ff:
ff53604b 2625 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2626 case 0xcd: /* fsb frequency */
609e36d3 2627 msr_info->data = 3;
15c4a640 2628 break;
7b914098
JS		 2629 /*
2630 * MSR_EBC_FREQUENCY_ID
2631 * Conservative value valid for even the basic CPU models.
2632 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2633 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2634 * and 266MHz for model 3, or 4. Set Core Clock
2635 * Frequency to System Bus Frequency Ratio to 1 (bits
2636 * 31:24) even though these are only valid for CPU
2637 * models > 2, however guests may end up dividing or
2638 * multiplying by zero otherwise.
2639 */
2640 case MSR_EBC_FREQUENCY_ID:
609e36d3 2641 msr_info->data = 1 << 24;
7b914098 2642 break;
15c4a640 2643 case MSR_IA32_APICBASE:
609e36d3 2644 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2645 break;
0105d1a5 2646 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2647 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2648 break;
a3e06bbe 2649 case MSR_IA32_TSCDEADLINE:
609e36d3 2650 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2651 break;
ba904635 2652 case MSR_IA32_TSC_ADJUST:
609e36d3 2653 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2654 break;
15c4a640 2655 case MSR_IA32_MISC_ENABLE:
609e36d3 2656 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2657 break;
64d60670
PB		 2658 case MSR_IA32_SMBASE:
2659 if (!msr_info->host_initiated)
2660 return 1;
2661 msr_info->data = vcpu->arch.smbase;
15c4a640 2662 break;
52797bf9
LA		 2663 case MSR_SMI_COUNT:
2664 msr_info->data = vcpu->arch.smi_count;
2665 break;
847f0ad8
AG		 2666 case MSR_IA32_PERF_STATUS:
2667 /* TSC increment by tick */
609e36d3 2668 msr_info->data = 1000ULL;
847f0ad8 2669 /* CPU multiplier */
b0996ae4 2670 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2671 break;
15c4a640 2672 case MSR_EFER:
609e36d3 2673 msr_info->data = vcpu->arch.efer;
15c4a640 2674 break;
18068523 2675 case MSR_KVM_WALL_CLOCK:
11c6bffa 2676 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2677 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2678 break;
2679 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2680 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2681 msr_info->data = vcpu->arch.time;
18068523 2682 break;
344d9588 2683 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2684 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2685 break;
c9aaa895 2686 case MSR_KVM_STEAL_TIME:
609e36d3 2687 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2688 break;
1d92128f 2689 case MSR_KVM_PV_EOI_EN:
609e36d3 2690 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2691 break;
890ca9ae
HY		 2692 case MSR_IA32_P5_MC_ADDR:
2693 case MSR_IA32_P5_MC_TYPE:
2694 case MSR_IA32_MCG_CAP:
2695 case MSR_IA32_MCG_CTL:
2696 case MSR_IA32_MCG_STATUS:
81760dcc 2697 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2698 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2699 case MSR_K7_CLK_CTL:
2700 /*
2701 * Provide expected ramp-up count for K7. All other
2702 * are set to zero, indicating minimum divisors for
2703 * every field.
2704 *
2705 * This prevents guest kernels on AMD host with CPU
2706 * type 6, model 8 and higher from exploding due to
2707 * the rdmsr failing.
2708 */
609e36d3 2709 msr_info->data = 0x20000000;
84e0cefa 2710 break;
55cd8e5a 2711 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2712 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2713 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2714 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2715 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2716 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2717 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2718 return kvm_hv_get_msr_common(vcpu,
2719 msr_info->index, &msr_info->data);
55cd8e5a 2720 break;
91c9c3ed 2721 case MSR_IA32_BBL_CR_CTL3:
2722 /* This legacy MSR exists but isn't fully documented in current
2723 * silicon. It is however accessed by winxp in very narrow
2724 * scenarios where it sets bit #19, itself documented as
2725 * a "reserved" bit. Best effort attempt to source coherent
2726 * read data here should the balance of the register be
2727 * interpreted by the guest:
2728 *
2729 * L2 cache control register 3: 64GB range, 256KB size,
2730 * enabled, latency 0x1, configured
2731 */
609e36d3 2732 msr_info->data = 0xbe702111;
91c9c3ed 2733 break;
2b036c6b 2734 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2735 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2736 return 1;
609e36d3 2737 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2738 break;
2739 case MSR_AMD64_OSVW_STATUS:
d6321d49 2740 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2741 return 1;
609e36d3 2742 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2743 break;
db2336a8
KH		 2744 case MSR_PLATFORM_INFO:
2745 msr_info->data = vcpu->arch.msr_platform_info;
2746 break;
2747 case MSR_MISC_FEATURES_ENABLES:
2748 msr_info->data = vcpu->arch.msr_misc_features_enables;
2749 break;
15c4a640 2750 default:
c6702c9d 2751 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2752 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2753 if (!ignore_msrs) {
ae0f5499
BD		 2754 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2755 msr_info->index);
ed85c068
AP		 2756 return 1;
2757 } else {
fab0aa3b
EM		 2758 if (report_ignored_msrs)
2759 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2760 msr_info->index);
609e36d3 2761 msr_info->data = 0;
ed85c068
AP		 2762 }
2763 break;
15c4a640 2764 }
15c4a640
CO		 2765 return 0;
2766}
2767EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2768
313a3dc7
CO		 2769/*
2770 * Read or write a bunch of msrs. All parameters are kernel addresses.
2771 *
2772 * @return number of msrs set successfully.
2773 */
2774static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2775 struct kvm_msr_entry *entries,
2776 int (*do_msr)(struct kvm_vcpu *vcpu,
2777 unsigned index, u64 *data))
2778{
801e459a 2779 int i;
313a3dc7 2780
313a3dc7
CO		 2781 for (i = 0; i < msrs->nmsrs; ++i)
2782 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2783 break;
2784
313a3dc7
CO		 2785 return i;
2786}
2787
2788/*
2789 * Read or write a bunch of msrs. Parameters are user addresses.
2790 *
2791 * @return number of msrs set successfully.
2792 */
2793static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2794 int (*do_msr)(struct kvm_vcpu *vcpu,
2795 unsigned index, u64 *data),
2796 int writeback)
2797{
2798 struct kvm_msrs msrs;
2799 struct kvm_msr_entry *entries;
2800 int r, n;
2801 unsigned size;
2802
2803 r = -EFAULT;
2804 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2805 goto out;
2806
2807 r = -E2BIG;
2808 if (msrs.nmsrs >= MAX_IO_MSRS)
2809 goto out;
2810
313a3dc7 2811 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2812 entries = memdup_user(user_msrs->entries, size);
2813 if (IS_ERR(entries)) {
2814 r = PTR_ERR(entries);
313a3dc7 2815 goto out;
ff5c2c03 2816 }
313a3dc7
CO		 2817
2818 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2819 if (r < 0)
2820 goto out_free;
2821
2822 r = -EFAULT;
2823 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2824 goto out_free;
2825
2826 r = n;
2827
2828out_free:
7a73c028 2829 kfree(entries);
313a3dc7
CO		 2830out:
2831 return r;
2832}
2833
4d5422ce
WL		 2834static inline bool kvm_can_mwait_in_guest(void)
2835{
2836 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2837 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2838 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2839}
2840
784aa3d7 2841int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2842{
4d5422ce 2843 int r = 0;
018d00d2
ZX		 2844
2845 switch (ext) {
2846 case KVM_CAP_IRQCHIP:
2847 case KVM_CAP_HLT:
2848 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2849 case KVM_CAP_SET_TSS_ADDR:
07716717 2850 case KVM_CAP_EXT_CPUID:
9c15bb1d 2851 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2852 case KVM_CAP_CLOCKSOURCE:
7837699f 2853 case KVM_CAP_PIT:
a28e4f5a 2854 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2855 case KVM_CAP_MP_STATE:
ed848624 2856 case KVM_CAP_SYNC_MMU:
a355c85c 2857 case KVM_CAP_USER_NMI:
52d939a0 2858 case KVM_CAP_REINJECT_CONTROL:
4925663a 2859 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2860 case KVM_CAP_IOEVENTFD:
f848a5a8 2861 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2862 case KVM_CAP_PIT2:
e9f42757 2863 case KVM_CAP_PIT_STATE2:
b927a3ce 2864 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2865 case KVM_CAP_XEN_HVM:
3cfc3092 2866 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2867 case KVM_CAP_HYPERV:
10388a07 2868 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2869 case KVM_CAP_HYPERV_SPIN:
5c919412 2870 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2871 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2872 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2873 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2874 case KVM_CAP_HYPERV_TLBFLUSH:
ab9f4ecb 2875 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2876 case KVM_CAP_DEBUGREGS:
d2be1651 2877 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2878 case KVM_CAP_XSAVE:
344d9588 2879 case KVM_CAP_ASYNC_PF:
92a1f12d 2880 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2881 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2882 case KVM_CAP_READONLY_MEM:
5f66b620 2883 case KVM_CAP_HYPERV_TIME:
100943c5 2884 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2885 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2886 case KVM_CAP_ENABLE_CAP_VM:
2887 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2888 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2889 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2890 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2891 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2892 r = 1;
2893 break;
01643c51
KH		 2894 case KVM_CAP_SYNC_REGS:
2895 r = KVM_SYNC_X86_VALID_FIELDS;
2896 break;
e3fd9a93
PB		 2897 case KVM_CAP_ADJUST_CLOCK:
2898 r = KVM_CLOCK_TSC_STABLE;
2899 break;
4d5422ce 2900 case KVM_CAP_X86_DISABLE_EXITS:
b31c114b 2901 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2902 if(kvm_can_mwait_in_guest())
2903 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2904 break;
6d396b55
PB		 2905 case KVM_CAP_X86_SMM:
2906 /* SMBASE is usually relocated above 1M on modern chipsets,
2907 * and SMM handlers might indeed rely on 4G segment limits,
2908 * so do not report SMM to be available if real mode is
2909 * emulated via vm86 mode. Still, do not go to great lengths
2910 * to avoid userspace's usage of the feature, because it is a
2911 * fringe case that is not enabled except via specific settings
2912 * of the module parameters.
2913 */
2914 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2915 break;
774ead3a
AK		 2916 case KVM_CAP_VAPIC:
2917 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2918 break;
f725230a 2919 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2920 r = KVM_SOFT_MAX_VCPUS;
2921 break;
2922 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2923 r = KVM_MAX_VCPUS;
2924 break;
a988b910 2925 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2926 r = KVM_USER_MEM_SLOTS;
a988b910 2927 break;
a68a6a72
MT		 2928 case KVM_CAP_PV_MMU: /* obsolete */
2929 r = 0;
2f333bcb 2930 break;
890ca9ae
HY		 2931 case KVM_CAP_MCE:
2932 r = KVM_MAX_MCE_BANKS;
2933 break;
2d5b5a66 2934 case KVM_CAP_XCRS:
d366bf7e 2935 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2936 break;
92a1f12d
JR		 2937 case KVM_CAP_TSC_CONTROL:
2938 r = kvm_has_tsc_control;
2939 break;
37131313
RK		 2940 case KVM_CAP_X2APIC_API:
2941 r = KVM_X2APIC_API_VALID_FLAGS;
2942 break;
018d00d2 2943 default:
018d00d2
ZX		 2944 break;
2945 }
2946 return r;
2947
2948}
2949
043405e1
CO		 2950long kvm_arch_dev_ioctl(struct file *filp,
2951 unsigned int ioctl, unsigned long arg)
2952{
2953 void __user *argp = (void __user *)arg;
2954 long r;
2955
2956 switch (ioctl) {
2957 case KVM_GET_MSR_INDEX_LIST: {
2958 struct kvm_msr_list __user *user_msr_list = argp;
2959 struct kvm_msr_list msr_list;
2960 unsigned n;
2961
2962 r = -EFAULT;
2963 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2964 goto out;
2965 n = msr_list.nmsrs;
62ef68bb 2966 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2967 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2968 goto out;
2969 r = -E2BIG;
e125e7b6 2970 if (n < msr_list.nmsrs)
043405e1
CO		 2971 goto out;
2972 r = -EFAULT;
2973 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2974 num_msrs_to_save * sizeof(u32)))
2975 goto out;
e125e7b6 2976 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2977 &emulated_msrs,
62ef68bb 2978 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2979 goto out;
2980 r = 0;
2981 break;
2982 }
9c15bb1d
BP		 2983 case KVM_GET_SUPPORTED_CPUID:
2984 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2985 struct kvm_cpuid2 __user *cpuid_arg = argp;
2986 struct kvm_cpuid2 cpuid;
2987
2988 r = -EFAULT;
2989 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2990 goto out;
9c15bb1d
BP		 2991
2992 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2993 ioctl);
674eea0f
AK		 2994 if (r)
2995 goto out;
2996
2997 r = -EFAULT;
2998 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2999 goto out;
3000 r = 0;
3001 break;
3002 }
890ca9ae 3003 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3004 r = -EFAULT;
c45dcc71
AR		 3005 if (copy_to_user(argp, &kvm_mce_cap_supported,
3006 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3007 goto out;
3008 r = 0;
3009 break;
801e459a
TL		 3010 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3011 struct kvm_msr_list __user *user_msr_list = argp;
3012 struct kvm_msr_list msr_list;
3013 unsigned int n;
3014
3015 r = -EFAULT;
3016 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3017 goto out;
3018 n = msr_list.nmsrs;
3019 msr_list.nmsrs = num_msr_based_features;
3020 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3021 goto out;
3022 r = -E2BIG;
3023 if (n < msr_list.nmsrs)
3024 goto out;
3025 r = -EFAULT;
3026 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3027 num_msr_based_features * sizeof(u32)))
3028 goto out;
3029 r = 0;
3030 break;
3031 }
3032 case KVM_GET_MSRS:
3033 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3034 break;
890ca9ae 3035 }
043405e1
CO		 3036 default:
3037 r = -EINVAL;
3038 }
3039out:
3040 return r;
3041}
3042
f5f48ee1
SY		 3043static void wbinvd_ipi(void *garbage)
3044{
3045 wbinvd();
3046}
3047
3048static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3049{
e0f0bbc5 3050 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3051}
3052
313a3dc7
CO		 3053void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3054{
f5f48ee1
SY		 3055 /* Address WBINVD may be executed by guest */
3056 if (need_emulate_wbinvd(vcpu)) {
3057 if (kvm_x86_ops->has_wbinvd_exit())
3058 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3059 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3060 smp_call_function_single(vcpu->cpu,
3061 wbinvd_ipi, NULL, 1);
3062 }
3063
313a3dc7 3064 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3065
0dd6a6ed
ZA		 3066 /* Apply any externally detected TSC adjustments (due to suspend) */
3067 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3068 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3069 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3070 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3071 }
8f6055cb 3072
b0c39dc6 3073 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3074 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3075 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3076 if (tsc_delta < 0)
3077 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3078
b0c39dc6 3079 if (kvm_check_tsc_unstable()) {
07c1419a 3080 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3081 vcpu->arch.last_guest_tsc);
a545ab6a 3082 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3083 vcpu->arch.tsc_catchup = 1;
c285545f 3084 }
a749e247
PB		 3085
3086 if (kvm_lapic_hv_timer_in_use(vcpu))
3087 kvm_lapic_restart_hv_timer(vcpu);
3088
d98d07ca
MT		 3089 /*
3090 * On a host with synchronized TSC, there is no need to update
3091 * kvmclock on vcpu->cpu migration
3092 */
3093 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3094 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3095 if (vcpu->cpu != cpu)
1bd2009e 3096 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3097 vcpu->cpu = cpu;
6b7d7e76 3098 }
c9aaa895 3099
c9aaa895 3100 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3101}
3102
0b9f6c46
PX		 3103static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3104{
3105 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3106 return;
3107
fa55eedd 3108 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3109
4e335d9e 3110 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3111 &vcpu->arch.st.steal.preempted,
3112 offsetof(struct kvm_steal_time, preempted),
3113 sizeof(vcpu->arch.st.steal.preempted));
3114}
3115
313a3dc7
CO		 3116void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3117{
cc0d907c 3118 int idx;
de63ad4c
LM		 3119
3120 if (vcpu->preempted)
3121 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3122
931f261b
AA		 3123 /*
3124 * Disable page faults because we're in atomic context here.
3125 * kvm_write_guest_offset_cached() would call might_fault()
3126 * that relies on pagefault_disable() to tell if there's a
3127 * bug. NOTE: the write to guest memory may not go through if
3128 * during postcopy live migration or if there's heavy guest
3129 * paging.
3130 */
3131 pagefault_disable();
cc0d907c
AA		 3132 /*
3133 * kvm_memslots() will be called by
3134 * kvm_write_guest_offset_cached() so take the srcu lock.
3135 */
3136 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3137 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3138 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3139 pagefault_enable();
02daab21 3140 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3141 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3142 /*
3143 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3144 * on every vmexit, but if not, we might have a stale dr6 from the
3145 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3146 */
3147 set_debugreg(0, 6);
313a3dc7
CO		 3148}
3149
313a3dc7
CO		 3150static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3151 struct kvm_lapic_state *s)
3152{
fa59cc00 3153 if (vcpu->arch.apicv_active)
d62caabb
AS		 3154 kvm_x86_ops->sync_pir_to_irr(vcpu);
3155
a92e2543 3156 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3157}
3158
3159static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3160 struct kvm_lapic_state *s)
3161{
a92e2543
RK		 3162 int r;
3163
3164 r = kvm_apic_set_state(vcpu, s);
3165 if (r)
3166 return r;
cb142eb7 3167 update_cr8_intercept(vcpu);
313a3dc7
CO		 3168
3169 return 0;
3170}
3171
127a457a
MG		 3172static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3173{
3174 return (!lapic_in_kernel(vcpu) ||
3175 kvm_apic_accept_pic_intr(vcpu));
3176}
3177
782d422b
MG		 3178/*
3179 * if userspace requested an interrupt window, check that the
3180 * interrupt window is open.
3181 *
3182 * No need to exit to userspace if we already have an interrupt queued.
3183 */
3184static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3185{
3186 return kvm_arch_interrupt_allowed(vcpu) &&
3187 !kvm_cpu_has_interrupt(vcpu) &&
3188 !kvm_event_needs_reinjection(vcpu) &&
3189 kvm_cpu_accept_dm_intr(vcpu);
3190}
3191
f77bc6a4
ZX		 3192static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3193 struct kvm_interrupt *irq)
3194{
02cdb50f 3195 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3196 return -EINVAL;
1c1a9ce9
SR		 3197
3198 if (!irqchip_in_kernel(vcpu->kvm)) {
3199 kvm_queue_interrupt(vcpu, irq->irq, false);
3200 kvm_make_request(KVM_REQ_EVENT, vcpu);
3201 return 0;
3202 }
3203
3204 /*
3205 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3206 * fail for in-kernel 8259.
3207 */
3208 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3209 return -ENXIO;
f77bc6a4 3210
1c1a9ce9
SR		 3211 if (vcpu->arch.pending_external_vector != -1)
3212 return -EEXIST;
f77bc6a4 3213
1c1a9ce9 3214 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3215 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3216 return 0;
3217}
3218
c4abb7c9
JK		 3219static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3220{
c4abb7c9 3221 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3222
3223 return 0;
3224}
3225
f077825a
PB		 3226static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3227{
64d60670
PB		 3228 kvm_make_request(KVM_REQ_SMI, vcpu);
3229
f077825a
PB		 3230 return 0;
3231}
3232
b209749f
AK		 3233static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3234 struct kvm_tpr_access_ctl *tac)
3235{
3236 if (tac->flags)
3237 return -EINVAL;
3238 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3239 return 0;
3240}
3241
890ca9ae
HY		 3242static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3243 u64 mcg_cap)
3244{
3245 int r;
3246 unsigned bank_num = mcg_cap & 0xff, bank;
3247
3248 r = -EINVAL;
a9e38c3e 3249 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3250 goto out;
c45dcc71 3251 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3252 goto out;
3253 r = 0;
3254 vcpu->arch.mcg_cap = mcg_cap;
3255 /* Init IA32_MCG_CTL to all 1s */
3256 if (mcg_cap & MCG_CTL_P)
3257 vcpu->arch.mcg_ctl = ~(u64)0;
3258 /* Init IA32_MCi_CTL to all 1s */
3259 for (bank = 0; bank < bank_num; bank++)
3260 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3261
3262 if (kvm_x86_ops->setup_mce)
3263 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3264out:
3265 return r;
3266}
3267
3268static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3269 struct kvm_x86_mce *mce)
3270{
3271 u64 mcg_cap = vcpu->arch.mcg_cap;
3272 unsigned bank_num = mcg_cap & 0xff;
3273 u64 *banks = vcpu->arch.mce_banks;
3274
3275 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3276 return -EINVAL;
3277 /*
3278 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3279 * reporting is disabled
3280 */
3281 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3282 vcpu->arch.mcg_ctl != ~(u64)0)
3283 return 0;
3284 banks += 4 * mce->bank;
3285 /*
3286 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3287 * reporting is disabled for the bank
3288 */
3289 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3290 return 0;
3291 if (mce->status & MCI_STATUS_UC) {
3292 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3293 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3294 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3295 return 0;
3296 }
3297 if (banks[1] & MCI_STATUS_VAL)
3298 mce->status |= MCI_STATUS_OVER;
3299 banks[2] = mce->addr;
3300 banks[3] = mce->misc;
3301 vcpu->arch.mcg_status = mce->mcg_status;
3302 banks[1] = mce->status;
3303 kvm_queue_exception(vcpu, MC_VECTOR);
3304 } else if (!(banks[1] & MCI_STATUS_VAL)
3305 || !(banks[1] & MCI_STATUS_UC)) {
3306 if (banks[1] & MCI_STATUS_VAL)
3307 mce->status |= MCI_STATUS_OVER;
3308 banks[2] = mce->addr;
3309 banks[3] = mce->misc;
3310 banks[1] = mce->status;
3311 } else
3312 banks[1] |= MCI_STATUS_OVER;
3313 return 0;
3314}
3315
3cfc3092
JK		 3316static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3317 struct kvm_vcpu_events *events)
3318{
7460fb4a 3319 process_nmi(vcpu);
664f8e26
WL		 3320 /*
3321 * FIXME: pass injected and pending separately. This is only
3322 * needed for nested virtualization, whose state cannot be
3323 * migrated yet. For now we can combine them.
3324 */
03b82a30 3325 events->exception.injected =
664f8e26
WL		 3326 (vcpu->arch.exception.pending ||
3327 vcpu->arch.exception.injected) &&
03b82a30 3328 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3329 events->exception.nr = vcpu->arch.exception.nr;
3330 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3331 events->exception.pad = 0;
3cfc3092
JK		 3332 events->exception.error_code = vcpu->arch.exception.error_code;
3333
03b82a30 3334 events->interrupt.injected =
04140b41 3335 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3336 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3337 events->interrupt.soft = 0;
37ccdcbe 3338 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3339
3340 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3341 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3342 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3343 events->nmi.pad = 0;
3cfc3092 3344
66450a21 3345 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3346
f077825a
PB		 3347 events->smi.smm = is_smm(vcpu);
3348 events->smi.pending = vcpu->arch.smi_pending;
3349 events->smi.smm_inside_nmi =
3350 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3351 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3352
dab4b911 3353 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3354 | KVM_VCPUEVENT_VALID_SHADOW
3355 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3356 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3357}
3358
6ef4e07e
XG		 3359static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3360
3cfc3092
JK		 3361static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3362 struct kvm_vcpu_events *events)
3363{
dab4b911 3364 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3365 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3366 | KVM_VCPUEVENT_VALID_SHADOW
3367 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3368 return -EINVAL;
3369
78e546c8 3370 if (events->exception.injected &&
28d06353
JM		 3371 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3372 is_guest_mode(vcpu)))
78e546c8
PB		 3373 return -EINVAL;
3374
28bf2888
DH		 3375 /* INITs are latched while in SMM */
3376 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3377 (events->smi.smm || events->smi.pending) &&
3378 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3379 return -EINVAL;
3380
7460fb4a 3381 process_nmi(vcpu);
664f8e26 3382 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3383 vcpu->arch.exception.pending = events->exception.injected;
3384 vcpu->arch.exception.nr = events->exception.nr;
3385 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3386 vcpu->arch.exception.error_code = events->exception.error_code;
3387
04140b41 3388 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3389 vcpu->arch.interrupt.nr = events->interrupt.nr;
3390 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3391 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3392 kvm_x86_ops->set_interrupt_shadow(vcpu,
3393 events->interrupt.shadow);
3cfc3092
JK		 3394
3395 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3396 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3397 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3398 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3399
66450a21 3400 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3401 lapic_in_kernel(vcpu))
66450a21 3402 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3403
f077825a 3404 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3405 u32 hflags = vcpu->arch.hflags;
f077825a 3406 if (events->smi.smm)
6ef4e07e 3407 hflags |= HF_SMM_MASK;
f077825a 3408 else
6ef4e07e
XG		 3409 hflags &= ~HF_SMM_MASK;
3410 kvm_set_hflags(vcpu, hflags);
3411
f077825a 3412 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3413
3414 if (events->smi.smm) {
3415 if (events->smi.smm_inside_nmi)
3416 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3417 else
f4ef1910
WL		 3418 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3419 if (lapic_in_kernel(vcpu)) {
3420 if (events->smi.latched_init)
3421 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3422 else
3423 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3424 }
f077825a
PB		 3425 }
3426 }
3427
3842d135
AK		 3428 kvm_make_request(KVM_REQ_EVENT, vcpu);
3429
3cfc3092
JK		 3430 return 0;
3431}
3432
a1efbe77
JK		 3433static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3434 struct kvm_debugregs *dbgregs)
3435{
73aaf249
JK		 3436 unsigned long val;
3437
a1efbe77 3438 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3439 kvm_get_dr(vcpu, 6, &val);
73aaf249 3440 dbgregs->dr6 = val;
a1efbe77
JK		 3441 dbgregs->dr7 = vcpu->arch.dr7;
3442 dbgregs->flags = 0;
97e69aa6 3443 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3444}
3445
3446static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3447 struct kvm_debugregs *dbgregs)
3448{
3449 if (dbgregs->flags)
3450 return -EINVAL;
3451
d14bdb55
PB		 3452 if (dbgregs->dr6 & ~0xffffffffull)
3453 return -EINVAL;
3454 if (dbgregs->dr7 & ~0xffffffffull)
3455 return -EINVAL;
3456
a1efbe77 3457 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3458 kvm_update_dr0123(vcpu);
a1efbe77 3459 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3460 kvm_update_dr6(vcpu);
a1efbe77 3461 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3462 kvm_update_dr7(vcpu);
a1efbe77 3463
a1efbe77
JK		 3464 return 0;
3465}
3466
df1daba7
PB		 3467#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3468
3469static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3470{
c47ada30 3471 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3472 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3473 u64 valid;
3474
3475 /*
3476 * Copy legacy XSAVE area, to avoid complications with CPUID
3477 * leaves 0 and 1 in the loop below.
3478 */
3479 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3480
3481 /* Set XSTATE_BV */
00c87e9a 3482 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3483 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3484
3485 /*
3486 * Copy each region from the possibly compacted offset to the
3487 * non-compacted offset.
3488 */
d91cab78 3489 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3490 while (valid) {
3491 u64 feature = valid & -valid;
3492 int index = fls64(feature) - 1;
3493 void *src = get_xsave_addr(xsave, feature);
3494
3495 if (src) {
3496 u32 size, offset, ecx, edx;
3497 cpuid_count(XSTATE_CPUID, index,
3498 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3499 if (feature == XFEATURE_MASK_PKRU)
3500 memcpy(dest + offset, &vcpu->arch.pkru,
3501 sizeof(vcpu->arch.pkru));
3502 else
3503 memcpy(dest + offset, src, size);
3504
df1daba7
PB		 3505 }
3506
3507 valid -= feature;
3508 }
3509}
3510
3511static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3512{
c47ada30 3513 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3514 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3515 u64 valid;
3516
3517 /*
3518 * Copy legacy XSAVE area, to avoid complications with CPUID
3519 * leaves 0 and 1 in the loop below.
3520 */
3521 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3522
3523 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3524 xsave->header.xfeatures = xstate_bv;
782511b0 3525 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3526 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3527
3528 /*
3529 * Copy each region from the non-compacted offset to the
3530 * possibly compacted offset.
3531 */
d91cab78 3532 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3533 while (valid) {
3534 u64 feature = valid & -valid;
3535 int index = fls64(feature) - 1;
3536 void *dest = get_xsave_addr(xsave, feature);
3537
3538 if (dest) {
3539 u32 size, offset, ecx, edx;
3540 cpuid_count(XSTATE_CPUID, index,
3541 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3542 if (feature == XFEATURE_MASK_PKRU)
3543 memcpy(&vcpu->arch.pkru, src + offset,
3544 sizeof(vcpu->arch.pkru));
3545 else
3546 memcpy(dest, src + offset, size);
ee4100da 3547 }
df1daba7
PB		 3548
3549 valid -= feature;
3550 }
3551}
3552
2d5b5a66
SY		 3553static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3554 struct kvm_xsave *guest_xsave)
3555{
d366bf7e 3556 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3557 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3558 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3559 } else {
2d5b5a66 3560 memcpy(guest_xsave->region,
7366ed77 3561 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3562 sizeof(struct fxregs_state));
2d5b5a66 3563 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3564 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3565 }
3566}
3567
a575813b
WL		 3568#define XSAVE_MXCSR_OFFSET 24
3569
2d5b5a66
SY		 3570static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3571 struct kvm_xsave *guest_xsave)
3572{
3573 u64 xstate_bv =
3574 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3575 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3576
d366bf7e 3577 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3578 /*
3579 * Here we allow setting states that are not present in
3580 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3581 * with old userspace.
3582 */
a575813b
WL		 3583 if (xstate_bv & ~kvm_supported_xcr0() ||
3584 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3585 return -EINVAL;
df1daba7 3586 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3587 } else {
a575813b
WL		 3588 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3589 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3590 return -EINVAL;
7366ed77 3591 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3592 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3593 }
3594 return 0;
3595}
3596
3597static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3598 struct kvm_xcrs *guest_xcrs)
3599{
d366bf7e 3600 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3601 guest_xcrs->nr_xcrs = 0;
3602 return;
3603 }
3604
3605 guest_xcrs->nr_xcrs = 1;
3606 guest_xcrs->flags = 0;
3607 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3608 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3609}
3610
3611static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3612 struct kvm_xcrs *guest_xcrs)
3613{
3614 int i, r = 0;
3615
d366bf7e 3616 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3617 return -EINVAL;
3618
3619 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3620 return -EINVAL;
3621
3622 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3623 /* Only support XCR0 currently */
c67a04cb 3624 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3625 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3626 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3627 break;
3628 }
3629 if (r)
3630 r = -EINVAL;
3631 return r;
3632}
3633
1c0b28c2
EM		 3634/*
3635 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3636 * stopped by the hypervisor. This function will be called from the host only.
3637 * EINVAL is returned when the host attempts to set the flag for a guest that
3638 * does not support pv clocks.
3639 */
3640static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3641{
0b79459b 3642 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3643 return -EINVAL;
51d59c6b 3644 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3645 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3646 return 0;
3647}
3648
5c919412
AS		 3649static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3650 struct kvm_enable_cap *cap)
3651{
3652 if (cap->flags)
3653 return -EINVAL;
3654
3655 switch (cap->cap) {
efc479e6
RK		 3656 case KVM_CAP_HYPERV_SYNIC2:
3657 if (cap->args[0])
3658 return -EINVAL;
5c919412 3659 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3660 if (!irqchip_in_kernel(vcpu->kvm))
3661 return -EINVAL;
efc479e6
RK		 3662 return kvm_hv_activate_synic(vcpu, cap->cap ==
3663 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3664 default:
3665 return -EINVAL;
3666 }
3667}
3668
313a3dc7
CO		 3669long kvm_arch_vcpu_ioctl(struct file *filp,
3670 unsigned int ioctl, unsigned long arg)
3671{
3672 struct kvm_vcpu *vcpu = filp->private_data;
3673 void __user *argp = (void __user *)arg;
3674 int r;
d1ac91d8
AK		 3675 union {
3676 struct kvm_lapic_state *lapic;
3677 struct kvm_xsave *xsave;
3678 struct kvm_xcrs *xcrs;
3679 void *buffer;
3680 } u;
3681
9b062471
CD		 3682 vcpu_load(vcpu);
3683
d1ac91d8 3684 u.buffer = NULL;
313a3dc7
CO		 3685 switch (ioctl) {
3686 case KVM_GET_LAPIC: {
2204ae3c 3687 r = -EINVAL;
bce87cce 3688 if (!lapic_in_kernel(vcpu))
2204ae3c 3689 goto out;
d1ac91d8 3690 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3691
b772ff36 3692 r = -ENOMEM;
d1ac91d8 3693 if (!u.lapic)
b772ff36 3694 goto out;
d1ac91d8 3695 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3696 if (r)
3697 goto out;
3698 r = -EFAULT;
d1ac91d8 3699 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3700 goto out;
3701 r = 0;
3702 break;
3703 }
3704 case KVM_SET_LAPIC: {
2204ae3c 3705 r = -EINVAL;
bce87cce 3706 if (!lapic_in_kernel(vcpu))
2204ae3c 3707 goto out;
ff5c2c03 3708 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3709 if (IS_ERR(u.lapic)) {
3710 r = PTR_ERR(u.lapic);
3711 goto out_nofree;
3712 }
ff5c2c03 3713
d1ac91d8 3714 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3715 break;
3716 }
f77bc6a4
ZX		 3717 case KVM_INTERRUPT: {
3718 struct kvm_interrupt irq;
3719
3720 r = -EFAULT;
3721 if (copy_from_user(&irq, argp, sizeof irq))
3722 goto out;
3723 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3724 break;
3725 }
c4abb7c9
JK		 3726 case KVM_NMI: {
3727 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3728 break;
3729 }
f077825a
PB		 3730 case KVM_SMI: {
3731 r = kvm_vcpu_ioctl_smi(vcpu);
3732 break;
3733 }
313a3dc7
CO		 3734 case KVM_SET_CPUID: {
3735 struct kvm_cpuid __user *cpuid_arg = argp;
3736 struct kvm_cpuid cpuid;
3737
3738 r = -EFAULT;
3739 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3740 goto out;
3741 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3742 break;
3743 }
07716717
DK		 3744 case KVM_SET_CPUID2: {
3745 struct kvm_cpuid2 __user *cpuid_arg = argp;
3746 struct kvm_cpuid2 cpuid;
3747
3748 r = -EFAULT;
3749 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3750 goto out;
3751 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3752 cpuid_arg->entries);
07716717
DK		 3753 break;
3754 }
3755 case KVM_GET_CPUID2: {
3756 struct kvm_cpuid2 __user *cpuid_arg = argp;
3757 struct kvm_cpuid2 cpuid;
3758
3759 r = -EFAULT;
3760 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3761 goto out;
3762 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3763 cpuid_arg->entries);
07716717
DK		 3764 if (r)
3765 goto out;
3766 r = -EFAULT;
3767 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3768 goto out;
3769 r = 0;
3770 break;
3771 }
801e459a
TL		 3772 case KVM_GET_MSRS: {
3773 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3774 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3775 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3776 break;
801e459a
TL		 3777 }
3778 case KVM_SET_MSRS: {
3779 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3780 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3781 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3782 break;
801e459a 3783 }
b209749f
AK		 3784 case KVM_TPR_ACCESS_REPORTING: {
3785 struct kvm_tpr_access_ctl tac;
3786
3787 r = -EFAULT;
3788 if (copy_from_user(&tac, argp, sizeof tac))
3789 goto out;
3790 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3791 if (r)
3792 goto out;
3793 r = -EFAULT;
3794 if (copy_to_user(argp, &tac, sizeof tac))
3795 goto out;
3796 r = 0;
3797 break;
3798 };
b93463aa
AK		 3799 case KVM_SET_VAPIC_ADDR: {
3800 struct kvm_vapic_addr va;
7301d6ab 3801 int idx;
b93463aa
AK		 3802
3803 r = -EINVAL;
35754c98 3804 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3805 goto out;
3806 r = -EFAULT;
3807 if (copy_from_user(&va, argp, sizeof va))
3808 goto out;
7301d6ab 3809 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3810 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3811 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3812 break;
3813 }
890ca9ae
HY		 3814 case KVM_X86_SETUP_MCE: {
3815 u64 mcg_cap;
3816
3817 r = -EFAULT;
3818 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3819 goto out;
3820 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3821 break;
3822 }
3823 case KVM_X86_SET_MCE: {
3824 struct kvm_x86_mce mce;
3825
3826 r = -EFAULT;
3827 if (copy_from_user(&mce, argp, sizeof mce))
3828 goto out;
3829 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3830 break;
3831 }
3cfc3092
JK		 3832 case KVM_GET_VCPU_EVENTS: {
3833 struct kvm_vcpu_events events;
3834
3835 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3836
3837 r = -EFAULT;
3838 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3839 break;
3840 r = 0;
3841 break;
3842 }
3843 case KVM_SET_VCPU_EVENTS: {
3844 struct kvm_vcpu_events events;
3845
3846 r = -EFAULT;
3847 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3848 break;
3849
3850 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3851 break;
3852 }
a1efbe77
JK		 3853 case KVM_GET_DEBUGREGS: {
3854 struct kvm_debugregs dbgregs;
3855
3856 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3857
3858 r = -EFAULT;
3859 if (copy_to_user(argp, &dbgregs,
3860 sizeof(struct kvm_debugregs)))
3861 break;
3862 r = 0;
3863 break;
3864 }
3865 case KVM_SET_DEBUGREGS: {
3866 struct kvm_debugregs dbgregs;
3867
3868 r = -EFAULT;
3869 if (copy_from_user(&dbgregs, argp,
3870 sizeof(struct kvm_debugregs)))
3871 break;
3872
3873 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3874 break;
3875 }
2d5b5a66 3876 case KVM_GET_XSAVE: {
d1ac91d8 3877 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3878 r = -ENOMEM;
d1ac91d8 3879 if (!u.xsave)
2d5b5a66
SY		 3880 break;
3881
d1ac91d8 3882 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3883
3884 r = -EFAULT;
d1ac91d8 3885 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3886 break;
3887 r = 0;
3888 break;
3889 }
3890 case KVM_SET_XSAVE: {
ff5c2c03 3891 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3892 if (IS_ERR(u.xsave)) {
3893 r = PTR_ERR(u.xsave);
3894 goto out_nofree;
3895 }
2d5b5a66 3896
d1ac91d8 3897 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3898 break;
3899 }
3900 case KVM_GET_XCRS: {
d1ac91d8 3901 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3902 r = -ENOMEM;
d1ac91d8 3903 if (!u.xcrs)
2d5b5a66
SY		 3904 break;
3905
d1ac91d8 3906 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3907
3908 r = -EFAULT;
d1ac91d8 3909 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3910 sizeof(struct kvm_xcrs)))
3911 break;
3912 r = 0;
3913 break;
3914 }
3915 case KVM_SET_XCRS: {
ff5c2c03 3916 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3917 if (IS_ERR(u.xcrs)) {
3918 r = PTR_ERR(u.xcrs);
3919 goto out_nofree;
3920 }
2d5b5a66 3921
d1ac91d8 3922 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3923 break;
3924 }
92a1f12d
JR		 3925 case KVM_SET_TSC_KHZ: {
3926 u32 user_tsc_khz;
3927
3928 r = -EINVAL;
92a1f12d
JR		 3929 user_tsc_khz = (u32)arg;
3930
3931 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3932 goto out;
3933
cc578287
ZA		 3934 if (user_tsc_khz == 0)
3935 user_tsc_khz = tsc_khz;
3936
381d585c
HZ		 3937 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3938 r = 0;
92a1f12d 3939
92a1f12d
JR		 3940 goto out;
3941 }
3942 case KVM_GET_TSC_KHZ: {
cc578287 3943 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3944 goto out;
3945 }
1c0b28c2
EM		 3946 case KVM_KVMCLOCK_CTRL: {
3947 r = kvm_set_guest_paused(vcpu);
3948 goto out;
3949 }
5c919412
AS		 3950 case KVM_ENABLE_CAP: {
3951 struct kvm_enable_cap cap;
3952
3953 r = -EFAULT;
3954 if (copy_from_user(&cap, argp, sizeof(cap)))
3955 goto out;
3956 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3957 break;
3958 }
313a3dc7
CO		 3959 default:
3960 r = -EINVAL;
3961 }
3962out:
d1ac91d8 3963 kfree(u.buffer);
9b062471
CD		 3964out_nofree:
3965 vcpu_put(vcpu);
313a3dc7
CO		 3966 return r;
3967}
3968
5b1c1493
CO		 3969int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3970{
3971 return VM_FAULT_SIGBUS;
3972}
3973
1fe779f8
CO		 3974static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3975{
3976 int ret;
3977
3978 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3979 return -EINVAL;
1fe779f8
CO		 3980 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3981 return ret;
3982}
3983
b927a3ce
SY		 3984static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3985 u64 ident_addr)
3986{
2ac52ab8 3987 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3988}
3989
1fe779f8
CO		 3990static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3991 u32 kvm_nr_mmu_pages)
3992{
3993 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3994 return -EINVAL;
3995
79fac95e 3996 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3997
3998 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3999 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4000
79fac95e 4001 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4002 return 0;
4003}
4004
4005static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4006{
39de71ec 4007 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4008}
4009
1fe779f8
CO		 4010static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4011{
90bca052 4012 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4013 int r;
4014
4015 r = 0;
4016 switch (chip->chip_id) {
4017 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4018 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4019 sizeof(struct kvm_pic_state));
4020 break;
4021 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4022 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4023 sizeof(struct kvm_pic_state));
4024 break;
4025 case KVM_IRQCHIP_IOAPIC:
33392b49 4026 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4027 break;
4028 default:
4029 r = -EINVAL;
4030 break;
4031 }
4032 return r;
4033}
4034
4035static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4036{
90bca052 4037 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4038 int r;
4039
4040 r = 0;
4041 switch (chip->chip_id) {
4042 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4043 spin_lock(&pic->lock);
4044 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4045 sizeof(struct kvm_pic_state));
90bca052 4046 spin_unlock(&pic->lock);
1fe779f8
CO		 4047 break;
4048 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4049 spin_lock(&pic->lock);
4050 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4051 sizeof(struct kvm_pic_state));
90bca052 4052 spin_unlock(&pic->lock);
1fe779f8
CO		 4053 break;
4054 case KVM_IRQCHIP_IOAPIC:
33392b49 4055 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4056 break;
4057 default:
4058 r = -EINVAL;
4059 break;
4060 }
90bca052 4061 kvm_pic_update_irq(pic);
1fe779f8
CO		 4062 return r;
4063}
4064
e0f63cb9
SY		 4065static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4066{
34f3941c
RK		 4067 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4068
4069 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4070
4071 mutex_lock(&kps->lock);
4072 memcpy(ps, &kps->channels, sizeof(*ps));
4073 mutex_unlock(&kps->lock);
2da29bcc 4074 return 0;
e0f63cb9
SY		 4075}
4076
4077static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4078{
0185604c 4079 int i;
09edea72
RK		 4080 struct kvm_pit *pit = kvm->arch.vpit;
4081
4082 mutex_lock(&pit->pit_state.lock);
34f3941c 4083 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4084 for (i = 0; i < 3; i++)
09edea72
RK		 4085 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4086 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4087 return 0;
e9f42757
BK		 4088}
4089
4090static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4091{
e9f42757
BK		 4092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4093 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4094 sizeof(ps->channels));
4095 ps->flags = kvm->arch.vpit->pit_state.flags;
4096 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4097 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4098 return 0;
e9f42757
BK		 4099}
4100
4101static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4102{
2da29bcc 4103 int start = 0;
0185604c 4104 int i;
e9f42757 4105 u32 prev_legacy, cur_legacy;
09edea72
RK		 4106 struct kvm_pit *pit = kvm->arch.vpit;
4107
4108 mutex_lock(&pit->pit_state.lock);
4109 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4110 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4111 if (!prev_legacy && cur_legacy)
4112 start = 1;
09edea72
RK		 4113 memcpy(&pit->pit_state.channels, &ps->channels,
4114 sizeof(pit->pit_state.channels));
4115 pit->pit_state.flags = ps->flags;
0185604c 4116 for (i = 0; i < 3; i++)
09edea72 4117 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4118 start && i == 0);
09edea72 4119 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4120 return 0;
e0f63cb9
SY		 4121}
4122
52d939a0
MT		 4123static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4124 struct kvm_reinject_control *control)
4125{
71474e2f
RK		 4126 struct kvm_pit *pit = kvm->arch.vpit;
4127
4128 if (!pit)
52d939a0 4129 return -ENXIO;
b39c90b6 4130
71474e2f
RK		 4131 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4132 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4133 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4134 */
4135 mutex_lock(&pit->pit_state.lock);
4136 kvm_pit_set_reinject(pit, control->pit_reinject);
4137 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4138
52d939a0
MT		 4139 return 0;
4140}
4141
95d4c16c 4142/**
60c34612
TY		 4143 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4144 * @kvm: kvm instance
4145 * @log: slot id and address to which we copy the log
95d4c16c 4146 *
e108ff2f
PB		 4147 * Steps 1-4 below provide general overview of dirty page logging. See
4148 * kvm_get_dirty_log_protect() function description for additional details.
4149 *
4150 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4151 * always flush the TLB (step 4) even if previous step failed and the dirty
4152 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4153 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4154 * writes will be marked dirty for next log read.
95d4c16c 4155 *
60c34612
TY		 4156 * 1. Take a snapshot of the bit and clear it if needed.
4157 * 2. Write protect the corresponding page.
e108ff2f
PB		 4158 * 3. Copy the snapshot to the userspace.
4159 * 4. Flush TLB's if needed.
5bb064dc 4160 */
60c34612 4161int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4162{
60c34612 4163 bool is_dirty = false;
e108ff2f 4164 int r;
5bb064dc 4165
79fac95e 4166 mutex_lock(&kvm->slots_lock);
5bb064dc 4167
88178fd4
KH		 4168 /*
4169 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4170 */
4171 if (kvm_x86_ops->flush_log_dirty)
4172 kvm_x86_ops->flush_log_dirty(kvm);
4173
e108ff2f 4174 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4175
4176 /*
4177 * All the TLBs can be flushed out of mmu lock, see the comments in
4178 * kvm_mmu_slot_remove_write_access().
4179 */
e108ff2f 4180 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4181 if (is_dirty)
4182 kvm_flush_remote_tlbs(kvm);
4183
79fac95e 4184 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4185 return r;
4186}
4187
aa2fbe6d
YZ		 4188int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4189 bool line_status)
23d43cf9
CD		 4190{
4191 if (!irqchip_in_kernel(kvm))
4192 return -ENXIO;
4193
4194 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4195 irq_event->irq, irq_event->level,
4196 line_status);
23d43cf9
CD		 4197 return 0;
4198}
4199
90de4a18
NA		 4200static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4201 struct kvm_enable_cap *cap)
4202{
4203 int r;
4204
4205 if (cap->flags)
4206 return -EINVAL;
4207
4208 switch (cap->cap) {
4209 case KVM_CAP_DISABLE_QUIRKS:
4210 kvm->arch.disabled_quirks = cap->args[0];
4211 r = 0;
4212 break;
49df6397
SR		 4213 case KVM_CAP_SPLIT_IRQCHIP: {
4214 mutex_lock(&kvm->lock);
b053b2ae
SR		 4215 r = -EINVAL;
4216 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4217 goto split_irqchip_unlock;
49df6397
SR		 4218 r = -EEXIST;
4219 if (irqchip_in_kernel(kvm))
4220 goto split_irqchip_unlock;
557abc40 4221 if (kvm->created_vcpus)
49df6397
SR		 4222 goto split_irqchip_unlock;
4223 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4224 if (r)
49df6397
SR		 4225 goto split_irqchip_unlock;
4226 /* Pairs with irqchip_in_kernel. */
4227 smp_wmb();
49776faf 4228 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4229 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4230 r = 0;
4231split_irqchip_unlock:
4232 mutex_unlock(&kvm->lock);
4233 break;
4234 }
37131313
RK		 4235 case KVM_CAP_X2APIC_API:
4236 r = -EINVAL;
4237 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4238 break;
4239
4240 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4241 kvm->arch.x2apic_format = true;
c519265f
RK		 4242 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4243 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4244
4245 r = 0;
4246 break;
4d5422ce
WL		 4247 case KVM_CAP_X86_DISABLE_EXITS:
4248 r = -EINVAL;
4249 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4250 break;
4251
4252 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4253 kvm_can_mwait_in_guest())
4254 kvm->arch.mwait_in_guest = true;
caa057a2
WL		 4255 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL)
4256 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4257 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4258 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4259 r = 0;
4260 break;
90de4a18
NA		 4261 default:
4262 r = -EINVAL;
4263 break;
4264 }
4265 return r;
4266}
4267
1fe779f8
CO		 4268long kvm_arch_vm_ioctl(struct file *filp,
4269 unsigned int ioctl, unsigned long arg)
4270{
4271 struct kvm *kvm = filp->private_data;
4272 void __user *argp = (void __user *)arg;
367e1319 4273 int r = -ENOTTY;
f0d66275
DH		 4274 /*
4275 * This union makes it completely explicit to gcc-3.x
4276 * that these two variables' stack usage should be
4277 * combined, not added together.
4278 */
4279 union {
4280 struct kvm_pit_state ps;
e9f42757 4281 struct kvm_pit_state2 ps2;
c5ff41ce 4282 struct kvm_pit_config pit_config;
f0d66275 4283 } u;
1fe779f8
CO		 4284
4285 switch (ioctl) {
4286 case KVM_SET_TSS_ADDR:
4287 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4288 break;
b927a3ce
SY		 4289 case KVM_SET_IDENTITY_MAP_ADDR: {
4290 u64 ident_addr;
4291
1af1ac91
DH		 4292 mutex_lock(&kvm->lock);
4293 r = -EINVAL;
4294 if (kvm->created_vcpus)
4295 goto set_identity_unlock;
b927a3ce
SY		 4296 r = -EFAULT;
4297 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4298 goto set_identity_unlock;
b927a3ce 4299 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4300set_identity_unlock:
4301 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4302 break;
4303 }
1fe779f8
CO		 4304 case KVM_SET_NR_MMU_PAGES:
4305 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4306 break;
4307 case KVM_GET_NR_MMU_PAGES:
4308 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4309 break;
3ddea128 4310 case KVM_CREATE_IRQCHIP: {
3ddea128 4311 mutex_lock(&kvm->lock);
09941366 4312
3ddea128 4313 r = -EEXIST;
35e6eaa3 4314 if (irqchip_in_kernel(kvm))
3ddea128 4315 goto create_irqchip_unlock;
09941366 4316
3e515705 4317 r = -EINVAL;
557abc40 4318 if (kvm->created_vcpus)
3e515705 4319 goto create_irqchip_unlock;
09941366
RK		 4320
4321 r = kvm_pic_init(kvm);
4322 if (r)
3ddea128 4323 goto create_irqchip_unlock;
09941366
RK		 4324
4325 r = kvm_ioapic_init(kvm);
4326 if (r) {
09941366 4327 kvm_pic_destroy(kvm);
3ddea128 4328 goto create_irqchip_unlock;
09941366
RK		 4329 }
4330
399ec807
AK		 4331 r = kvm_setup_default_irq_routing(kvm);
4332 if (r) {
72bb2fcd 4333 kvm_ioapic_destroy(kvm);
09941366 4334 kvm_pic_destroy(kvm);
71ba994c 4335 goto create_irqchip_unlock;
399ec807 4336 }
49776faf 4337 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4338 smp_wmb();
49776faf 4339 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4340 create_irqchip_unlock:
4341 mutex_unlock(&kvm->lock);
1fe779f8 4342 break;
3ddea128 4343 }
7837699f 4344 case KVM_CREATE_PIT:
c5ff41ce
JK		 4345 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4346 goto create_pit;
4347 case KVM_CREATE_PIT2:
4348 r = -EFAULT;
4349 if (copy_from_user(&u.pit_config, argp,
4350 sizeof(struct kvm_pit_config)))
4351 goto out;
4352 create_pit:
250715a6 4353 mutex_lock(&kvm->lock);
269e05e4
AK		 4354 r = -EEXIST;
4355 if (kvm->arch.vpit)
4356 goto create_pit_unlock;
7837699f 4357 r = -ENOMEM;
c5ff41ce 4358 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4359 if (kvm->arch.vpit)
4360 r = 0;
269e05e4 4361 create_pit_unlock:
250715a6 4362 mutex_unlock(&kvm->lock);
7837699f 4363 break;
1fe779f8
CO		 4364 case KVM_GET_IRQCHIP: {
4365 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4366 struct kvm_irqchip *chip;
1fe779f8 4367
ff5c2c03
SL		 4368 chip = memdup_user(argp, sizeof(*chip));
4369 if (IS_ERR(chip)) {
4370 r = PTR_ERR(chip);
1fe779f8 4371 goto out;
ff5c2c03
SL		 4372 }
4373
1fe779f8 4374 r = -ENXIO;
826da321 4375 if (!irqchip_kernel(kvm))
f0d66275
DH		 4376 goto get_irqchip_out;
4377 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4378 if (r)
f0d66275 4379 goto get_irqchip_out;
1fe779f8 4380 r = -EFAULT;
f0d66275
DH		 4381 if (copy_to_user(argp, chip, sizeof *chip))
4382 goto get_irqchip_out;
1fe779f8 4383 r = 0;
f0d66275
DH		 4384 get_irqchip_out:
4385 kfree(chip);
1fe779f8
CO		 4386 break;
4387 }
4388 case KVM_SET_IRQCHIP: {
4389 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4390 struct kvm_irqchip *chip;
1fe779f8 4391
ff5c2c03
SL		 4392 chip = memdup_user(argp, sizeof(*chip));
4393 if (IS_ERR(chip)) {
4394 r = PTR_ERR(chip);
1fe779f8 4395 goto out;
ff5c2c03
SL		 4396 }
4397
1fe779f8 4398 r = -ENXIO;
826da321 4399 if (!irqchip_kernel(kvm))
f0d66275
DH		 4400 goto set_irqchip_out;
4401 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4402 if (r)
f0d66275 4403 goto set_irqchip_out;
1fe779f8 4404 r = 0;
f0d66275
DH		 4405 set_irqchip_out:
4406 kfree(chip);
1fe779f8
CO		 4407 break;
4408 }
e0f63cb9 4409 case KVM_GET_PIT: {
e0f63cb9 4410 r = -EFAULT;
f0d66275 4411 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4412 goto out;
4413 r = -ENXIO;
4414 if (!kvm->arch.vpit)
4415 goto out;
f0d66275 4416 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4417 if (r)
4418 goto out;
4419 r = -EFAULT;
f0d66275 4420 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4421 goto out;
4422 r = 0;
4423 break;
4424 }
4425 case KVM_SET_PIT: {
e0f63cb9 4426 r = -EFAULT;
f0d66275 4427 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4428 goto out;
4429 r = -ENXIO;
4430 if (!kvm->arch.vpit)
4431 goto out;
f0d66275 4432 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4433 break;
4434 }
e9f42757
BK		 4435 case KVM_GET_PIT2: {
4436 r = -ENXIO;
4437 if (!kvm->arch.vpit)
4438 goto out;
4439 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4440 if (r)
4441 goto out;
4442 r = -EFAULT;
4443 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4444 goto out;
4445 r = 0;
4446 break;
4447 }
4448 case KVM_SET_PIT2: {
4449 r = -EFAULT;
4450 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4451 goto out;
4452 r = -ENXIO;
4453 if (!kvm->arch.vpit)
4454 goto out;
4455 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4456 break;
4457 }
52d939a0
MT		 4458 case KVM_REINJECT_CONTROL: {
4459 struct kvm_reinject_control control;
4460 r = -EFAULT;
4461 if (copy_from_user(&control, argp, sizeof(control)))
4462 goto out;
4463 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4464 break;
4465 }
d71ba788
PB		 4466 case KVM_SET_BOOT_CPU_ID:
4467 r = 0;
4468 mutex_lock(&kvm->lock);
557abc40 4469 if (kvm->created_vcpus)
d71ba788
PB		 4470 r = -EBUSY;
4471 else
4472 kvm->arch.bsp_vcpu_id = arg;
4473 mutex_unlock(&kvm->lock);
4474 break;
ffde22ac 4475 case KVM_XEN_HVM_CONFIG: {
51776043 4476 struct kvm_xen_hvm_config xhc;
ffde22ac 4477 r = -EFAULT;
51776043 4478 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4479 goto out;
4480 r = -EINVAL;
51776043 4481 if (xhc.flags)
ffde22ac 4482 goto out;
51776043 4483 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4484 r = 0;
4485 break;
4486 }
afbcf7ab 4487 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4488 struct kvm_clock_data user_ns;
4489 u64 now_ns;
afbcf7ab
GC		 4490
4491 r = -EFAULT;
4492 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4493 goto out;
4494
4495 r = -EINVAL;
4496 if (user_ns.flags)
4497 goto out;
4498
4499 r = 0;
0bc48bea
RK		 4500 /*
4501 * TODO: userspace has to take care of races with VCPU_RUN, so
4502 * kvm_gen_update_masterclock() can be cut down to locked
4503 * pvclock_update_vm_gtod_copy().
4504 */
4505 kvm_gen_update_masterclock(kvm);
e891a32e 4506 now_ns = get_kvmclock_ns(kvm);
108b249c 4507 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4508 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4509 break;
4510 }
4511 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4512 struct kvm_clock_data user_ns;
4513 u64 now_ns;
4514
e891a32e 4515 now_ns = get_kvmclock_ns(kvm);
108b249c 4516 user_ns.clock = now_ns;
e3fd9a93 4517 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4518 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4519
4520 r = -EFAULT;
4521 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4522 goto out;
4523 r = 0;
4524 break;
4525 }
90de4a18
NA		 4526 case KVM_ENABLE_CAP: {
4527 struct kvm_enable_cap cap;
afbcf7ab 4528
90de4a18
NA		 4529 r = -EFAULT;
4530 if (copy_from_user(&cap, argp, sizeof(cap)))
4531 goto out;
4532 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4533 break;
4534 }
5acc5c06
BS		 4535 case KVM_MEMORY_ENCRYPT_OP: {
4536 r = -ENOTTY;
4537 if (kvm_x86_ops->mem_enc_op)
4538 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4539 break;
4540 }
69eaedee
BS		 4541 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4542 struct kvm_enc_region region;
4543
4544 r = -EFAULT;
4545 if (copy_from_user(&region, argp, sizeof(region)))
4546 goto out;
4547
4548 r = -ENOTTY;
4549 if (kvm_x86_ops->mem_enc_reg_region)
4550 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4551 break;
4552 }
4553 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4554 struct kvm_enc_region region;
4555
4556 r = -EFAULT;
4557 if (copy_from_user(&region, argp, sizeof(region)))
4558 goto out;
4559
4560 r = -ENOTTY;
4561 if (kvm_x86_ops->mem_enc_unreg_region)
4562 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4563 break;
4564 }
faeb7833
RK		 4565 case KVM_HYPERV_EVENTFD: {
4566 struct kvm_hyperv_eventfd hvevfd;
4567
4568 r = -EFAULT;
4569 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4570 goto out;
4571 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4572 break;
4573 }
1fe779f8 4574 default:
ad6260da 4575 r = -ENOTTY;
1fe779f8
CO		 4576 }
4577out:
4578 return r;
4579}
4580
a16b043c 4581static void kvm_init_msr_list(void)
043405e1
CO		 4582{
4583 u32 dummy[2];
4584 unsigned i, j;
4585
62ef68bb 4586 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4587 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4588 continue;
93c4adc7
PB		 4589
4590 /*
4591 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4592 * to the guests in some cases.
93c4adc7
PB		 4593 */
4594 switch (msrs_to_save[i]) {
4595 case MSR_IA32_BNDCFGS:
4596 if (!kvm_x86_ops->mpx_supported())
4597 continue;
4598 break;
9dbe6cf9
PB		 4599 case MSR_TSC_AUX:
4600 if (!kvm_x86_ops->rdtscp_supported())
4601 continue;
4602 break;
93c4adc7
PB		 4603 default:
4604 break;
4605 }
4606
043405e1
CO		 4607 if (j < i)
4608 msrs_to_save[j] = msrs_to_save[i];
4609 j++;
4610 }
4611 num_msrs_to_save = j;
62ef68bb
PB		 4612
4613 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4614 switch (emulated_msrs[i]) {
6d396b55
PB		 4615 case MSR_IA32_SMBASE:
4616 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4617 continue;
4618 break;
62ef68bb
PB		 4619 default:
4620 break;
4621 }
4622
4623 if (j < i)
4624 emulated_msrs[j] = emulated_msrs[i];
4625 j++;
4626 }
4627 num_emulated_msrs = j;
801e459a
TL		 4628
4629 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4630 struct kvm_msr_entry msr;
4631
4632 msr.index = msr_based_features[i];
66421c1e 4633 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4634 continue;
4635
4636 if (j < i)
4637 msr_based_features[j] = msr_based_features[i];
4638 j++;
4639 }
4640 num_msr_based_features = j;
043405e1
CO		 4641}
4642
bda9020e
MT		 4643static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4644 const void *v)
bbd9b64e 4645{
70252a10
AK		 4646 int handled = 0;
4647 int n;
4648
4649 do {
4650 n = min(len, 8);
bce87cce 4651 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4652 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4653 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4654 break;
4655 handled += n;
4656 addr += n;
4657 len -= n;
4658 v += n;
4659 } while (len);
bbd9b64e 4660
70252a10 4661 return handled;
bbd9b64e
CO		 4662}
4663
bda9020e 4664static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4665{
70252a10
AK		 4666 int handled = 0;
4667 int n;
4668
4669 do {
4670 n = min(len, 8);
bce87cce 4671 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4672 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4673 addr, n, v))
4674 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4675 break;
e39d200f 4676 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4677 handled += n;
4678 addr += n;
4679 len -= n;
4680 v += n;
4681 } while (len);
bbd9b64e 4682
70252a10 4683 return handled;
bbd9b64e
CO		 4684}
4685
2dafc6c2
GN		 4686static void kvm_set_segment(struct kvm_vcpu *vcpu,
4687 struct kvm_segment *var, int seg)
4688{
4689 kvm_x86_ops->set_segment(vcpu, var, seg);
4690}
4691
4692void kvm_get_segment(struct kvm_vcpu *vcpu,
4693 struct kvm_segment *var, int seg)
4694{
4695 kvm_x86_ops->get_segment(vcpu, var, seg);
4696}
4697
54987b7a
PB		 4698gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4699 struct x86_exception *exception)
02f59dc9
JR		 4700{
4701 gpa_t t_gpa;
02f59dc9
JR		 4702
4703 BUG_ON(!mmu_is_nested(vcpu));
4704
4705 /* NPT walks are always user-walks */
4706 access |= PFERR_USER_MASK;
54987b7a 4707 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4708
4709 return t_gpa;
4710}
4711
ab9ae313
AK		 4712gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4713 struct x86_exception *exception)
1871c602
GN		 4714{
4715 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4716 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4717}
4718
ab9ae313
AK		 4719 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4720 struct x86_exception *exception)
1871c602
GN		 4721{
4722 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4723 access |= PFERR_FETCH_MASK;
ab9ae313 4724 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4725}
4726
ab9ae313
AK		 4727gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4728 struct x86_exception *exception)
1871c602
GN		 4729{
4730 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4731 access |= PFERR_WRITE_MASK;
ab9ae313 4732 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4733}
4734
4735/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4736gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4737 struct x86_exception *exception)
1871c602 4738{
ab9ae313 4739 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4740}
4741
4742static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4743 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4744 struct x86_exception *exception)
bbd9b64e
CO		 4745{
4746 void *data = val;
10589a46 4747 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4748
4749 while (bytes) {
14dfe855 4750 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4751 exception);
bbd9b64e 4752 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4753 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4754 int ret;
4755
bcc55cba 4756 if (gpa == UNMAPPED_GVA)
ab9ae313 4757 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4758 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4759 offset, toread);
10589a46 4760 if (ret < 0) {
c3cd7ffa 4761 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4762 goto out;
4763 }
bbd9b64e 4764
77c2002e
IE		 4765 bytes -= toread;
4766 data += toread;
4767 addr += toread;
bbd9b64e 4768 }
10589a46 4769out:
10589a46 4770 return r;
bbd9b64e 4771}
77c2002e 4772
1871c602 4773/* used for instruction fetching */
0f65dd70
AK		 4774static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4775 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4776 struct x86_exception *exception)
1871c602 4777{
0f65dd70 4778 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4779 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4780 unsigned offset;
4781 int ret;
0f65dd70 4782
44583cba
PB		 4783 /* Inline kvm_read_guest_virt_helper for speed. */
4784 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4785 exception);
4786 if (unlikely(gpa == UNMAPPED_GVA))
4787 return X86EMUL_PROPAGATE_FAULT;
4788
4789 offset = addr & (PAGE_SIZE-1);
4790 if (WARN_ON(offset + bytes > PAGE_SIZE))
4791 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4792 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4793 offset, bytes);
44583cba
PB		 4794 if (unlikely(ret < 0))
4795 return X86EMUL_IO_NEEDED;
4796
4797 return X86EMUL_CONTINUE;
1871c602
GN		 4798}
4799
064aea77 4800int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4801 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4802 struct x86_exception *exception)
1871c602 4803{
0f65dd70 4804 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4805 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4806
1871c602 4807 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4808 exception);
1871c602 4809}
064aea77 4810EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4811
0f65dd70
AK		 4812static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4813 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4814 struct x86_exception *exception)
1871c602 4815{
0f65dd70 4816 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4817 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4818}
4819
7a036a6f
RK		 4820static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4821 unsigned long addr, void *val, unsigned int bytes)
4822{
4823 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4824 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4825
4826 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4827}
4828
6a4d7550 4829int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4830 gva_t addr, void *val,
2dafc6c2 4831 unsigned int bytes,
bcc55cba 4832 struct x86_exception *exception)
77c2002e 4833{
0f65dd70 4834 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4835 void *data = val;
4836 int r = X86EMUL_CONTINUE;
4837
4838 while (bytes) {
14dfe855
JR		 4839 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4840 PFERR_WRITE_MASK,
ab9ae313 4841 exception);
77c2002e
IE		 4842 unsigned offset = addr & (PAGE_SIZE-1);
4843 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4844 int ret;
4845
bcc55cba 4846 if (gpa == UNMAPPED_GVA)
ab9ae313 4847 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4848 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4849 if (ret < 0) {
c3cd7ffa 4850 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4851 goto out;
4852 }
4853
4854 bytes -= towrite;
4855 data += towrite;
4856 addr += towrite;
4857 }
4858out:
4859 return r;
4860}
6a4d7550 4861EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4862
082d06ed
WL		 4863int handle_ud(struct kvm_vcpu *vcpu)
4864{
6c86eedc 4865 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4866 enum emulation_result er;
6c86eedc
WL		 4867 char sig[5]; /* ud2; .ascii "kvm" */
4868 struct x86_exception e;
4869
4870 if (force_emulation_prefix &&
4871 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt,
4872 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 &&
4873 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4874 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4875 emul_type = 0;
4876 }
082d06ed 4877
6c86eedc 4878 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4879 if (er == EMULATE_USER_EXIT)
4880 return 0;
4881 if (er != EMULATE_DONE)
4882 kvm_queue_exception(vcpu, UD_VECTOR);
4883 return 1;
4884}
4885EXPORT_SYMBOL_GPL(handle_ud);
4886
0f89b207
TL		 4887static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4888 gpa_t gpa, bool write)
4889{
4890 /* For APIC access vmexit */
4891 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4892 return 1;
4893
4894 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4895 trace_vcpu_match_mmio(gva, gpa, write, true);
4896 return 1;
4897 }
4898
4899 return 0;
4900}
4901
af7cc7d1
XG		 4902static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4903 gpa_t *gpa, struct x86_exception *exception,
4904 bool write)
4905{
97d64b78
AK		 4906 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4907 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4908
be94f6b7
HH		 4909 /*
4910 * currently PKRU is only applied to ept enabled guest so
4911 * there is no pkey in EPT page table for L1 guest or EPT
4912 * shadow page table for L2 guest.
4913 */
97d64b78 4914 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4915 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4916 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4917 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4918 (gva & (PAGE_SIZE - 1));
4f022648 4919 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4920 return 1;
4921 }
4922
af7cc7d1
XG		 4923 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4924
4925 if (*gpa == UNMAPPED_GVA)
4926 return -1;
4927
0f89b207 4928 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4929}
4930
3200f405 4931int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4932 const void *val, int bytes)
bbd9b64e
CO		 4933{
4934 int ret;
4935
54bf36aa 4936 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4937 if (ret < 0)
bbd9b64e 4938 return 0;
0eb05bf2 4939 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4940 return 1;
4941}
4942
77d197b2
XG		 4943struct read_write_emulator_ops {
4944 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4945 int bytes);
4946 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4947 void *val, int bytes);
4948 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4949 int bytes, void *val);
4950 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4951 void *val, int bytes);
4952 bool write;
4953};
4954
4955static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4956{
4957 if (vcpu->mmio_read_completed) {
77d197b2 4958 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4959 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4960 vcpu->mmio_read_completed = 0;
4961 return 1;
4962 }
4963
4964 return 0;
4965}
4966
4967static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4968 void *val, int bytes)
4969{
54bf36aa 4970 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4971}
4972
4973static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4974 void *val, int bytes)
4975{
4976 return emulator_write_phys(vcpu, gpa, val, bytes);
4977}
4978
4979static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4980{
e39d200f 4981 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4982 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4983}
4984
4985static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4986 void *val, int bytes)
4987{
e39d200f 4988 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4989 return X86EMUL_IO_NEEDED;
4990}
4991
4992static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4993 void *val, int bytes)
4994{
f78146b0
AK		 4995 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4996
87da7e66 4997 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4998 return X86EMUL_CONTINUE;
4999}
5000
0fbe9b0b 5001static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5002 .read_write_prepare = read_prepare,
5003 .read_write_emulate = read_emulate,
5004 .read_write_mmio = vcpu_mmio_read,
5005 .read_write_exit_mmio = read_exit_mmio,
5006};
5007
0fbe9b0b 5008static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5009 .read_write_emulate = write_emulate,
5010 .read_write_mmio = write_mmio,
5011 .read_write_exit_mmio = write_exit_mmio,
5012 .write = true,
5013};
5014
22388a3c
XG		 5015static int emulator_read_write_onepage(unsigned long addr, void *val,
5016 unsigned int bytes,
5017 struct x86_exception *exception,
5018 struct kvm_vcpu *vcpu,
0fbe9b0b 5019 const struct read_write_emulator_ops *ops)
bbd9b64e 5020{
af7cc7d1
XG		 5021 gpa_t gpa;
5022 int handled, ret;
22388a3c 5023 bool write = ops->write;
f78146b0 5024 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5025 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5026
5027 /*
5028 * If the exit was due to a NPF we may already have a GPA.
5029 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5030 * Note, this cannot be used on string operations since string
5031 * operation using rep will only have the initial GPA from the NPF
5032 * occurred.
5033 */
5034 if (vcpu->arch.gpa_available &&
5035 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5036 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5037 gpa = vcpu->arch.gpa_val;
5038 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5039 } else {
5040 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5041 if (ret < 0)
5042 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5043 }
10589a46 5044
618232e2 5045 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5046 return X86EMUL_CONTINUE;
5047
bbd9b64e
CO		 5048 /*
5049 * Is this MMIO handled locally?
5050 */
22388a3c 5051 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5052 if (handled == bytes)
bbd9b64e 5053 return X86EMUL_CONTINUE;
bbd9b64e 5054
70252a10
AK		 5055 gpa += handled;
5056 bytes -= handled;
5057 val += handled;
5058
87da7e66
XG		 5059 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5060 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5061 frag->gpa = gpa;
5062 frag->data = val;
5063 frag->len = bytes;
f78146b0 5064 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5065}
5066
52eb5a6d
XL		 5067static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5068 unsigned long addr,
22388a3c
XG		 5069 void *val, unsigned int bytes,
5070 struct x86_exception *exception,
0fbe9b0b 5071 const struct read_write_emulator_ops *ops)
bbd9b64e 5072{
0f65dd70 5073 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5074 gpa_t gpa;
5075 int rc;
5076
5077 if (ops->read_write_prepare &&
5078 ops->read_write_prepare(vcpu, val, bytes))
5079 return X86EMUL_CONTINUE;
5080
5081 vcpu->mmio_nr_fragments = 0;
0f65dd70 5082
bbd9b64e
CO		 5083 /* Crossing a page boundary? */
5084 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5085 int now;
bbd9b64e
CO		 5086
5087 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5088 rc = emulator_read_write_onepage(addr, val, now, exception,
5089 vcpu, ops);
5090
bbd9b64e
CO		 5091 if (rc != X86EMUL_CONTINUE)
5092 return rc;
5093 addr += now;
bac15531
NA		 5094 if (ctxt->mode != X86EMUL_MODE_PROT64)
5095 addr = (u32)addr;
bbd9b64e
CO		 5096 val += now;
5097 bytes -= now;
5098 }
22388a3c 5099
f78146b0
AK		 5100 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5101 vcpu, ops);
5102 if (rc != X86EMUL_CONTINUE)
5103 return rc;
5104
5105 if (!vcpu->mmio_nr_fragments)
5106 return rc;
5107
5108 gpa = vcpu->mmio_fragments[0].gpa;
5109
5110 vcpu->mmio_needed = 1;
5111 vcpu->mmio_cur_fragment = 0;
5112
87da7e66 5113 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5114 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5115 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5116 vcpu->run->mmio.phys_addr = gpa;
5117
5118 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5119}
5120
5121static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5122 unsigned long addr,
5123 void *val,
5124 unsigned int bytes,
5125 struct x86_exception *exception)
5126{
5127 return emulator_read_write(ctxt, addr, val, bytes,
5128 exception, &read_emultor);
5129}
5130
52eb5a6d 5131static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5132 unsigned long addr,
5133 const void *val,
5134 unsigned int bytes,
5135 struct x86_exception *exception)
5136{
5137 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5138 exception, &write_emultor);
bbd9b64e 5139}
bbd9b64e 5140
daea3e73
AK		 5141#define CMPXCHG_TYPE(t, ptr, old, new) \
5142 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5143
5144#ifdef CONFIG_X86_64
5145# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5146#else
5147# define CMPXCHG64(ptr, old, new) \
9749a6c0 5148 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5149#endif
5150
0f65dd70
AK		 5151static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5152 unsigned long addr,
bbd9b64e
CO		 5153 const void *old,
5154 const void *new,
5155 unsigned int bytes,
0f65dd70 5156 struct x86_exception *exception)
bbd9b64e 5157{
0f65dd70 5158 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5159 gpa_t gpa;
5160 struct page *page;
5161 char *kaddr;
5162 bool exchanged;
2bacc55c 5163
daea3e73
AK		 5164 /* guests cmpxchg8b have to be emulated atomically */
5165 if (bytes > 8 || (bytes & (bytes - 1)))
5166 goto emul_write;
10589a46 5167
daea3e73 5168 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5169
daea3e73
AK		 5170 if (gpa == UNMAPPED_GVA ||
5171 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5172 goto emul_write;
2bacc55c 5173
daea3e73
AK		 5174 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5175 goto emul_write;
72dc67a6 5176
54bf36aa 5177 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5178 if (is_error_page(page))
c19b8bd6 5179 goto emul_write;
72dc67a6 5180
8fd75e12 5181 kaddr = kmap_atomic(page);
daea3e73
AK		 5182 kaddr += offset_in_page(gpa);
5183 switch (bytes) {
5184 case 1:
5185 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5186 break;
5187 case 2:
5188 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5189 break;
5190 case 4:
5191 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5192 break;
5193 case 8:
5194 exchanged = CMPXCHG64(kaddr, old, new);
5195 break;
5196 default:
5197 BUG();
2bacc55c 5198 }
8fd75e12 5199 kunmap_atomic(kaddr);
daea3e73
AK		 5200 kvm_release_page_dirty(page);
5201
5202 if (!exchanged)
5203 return X86EMUL_CMPXCHG_FAILED;
5204
54bf36aa 5205 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5206 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5207
5208 return X86EMUL_CONTINUE;
4a5f48f6 5209
3200f405 5210emul_write:
daea3e73 5211 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5212
0f65dd70 5213 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5214}
5215
cf8f70bf
GN		 5216static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5217{
cbfc6c91 5218 int r = 0, i;
cf8f70bf 5219
cbfc6c91
WL		 5220 for (i = 0; i < vcpu->arch.pio.count; i++) {
5221 if (vcpu->arch.pio.in)
5222 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5223 vcpu->arch.pio.size, pd);
5224 else
5225 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5226 vcpu->arch.pio.port, vcpu->arch.pio.size,
5227 pd);
5228 if (r)
5229 break;
5230 pd += vcpu->arch.pio.size;
5231 }
cf8f70bf
GN		 5232 return r;
5233}
5234
6f6fbe98
XG		 5235static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5236 unsigned short port, void *val,
5237 unsigned int count, bool in)
cf8f70bf 5238{
cf8f70bf 5239 vcpu->arch.pio.port = port;
6f6fbe98 5240 vcpu->arch.pio.in = in;
7972995b 5241 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5242 vcpu->arch.pio.size = size;
5243
5244 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5245 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5246 return 1;
5247 }
5248
5249 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5250 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5251 vcpu->run->io.size = size;
5252 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5253 vcpu->run->io.count = count;
5254 vcpu->run->io.port = port;
5255
5256 return 0;
5257}
5258
6f6fbe98
XG		 5259static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5260 int size, unsigned short port, void *val,
5261 unsigned int count)
cf8f70bf 5262{
ca1d4a9e 5263 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5264 int ret;
ca1d4a9e 5265
6f6fbe98
XG		 5266 if (vcpu->arch.pio.count)
5267 goto data_avail;
cf8f70bf 5268
cbfc6c91
WL		 5269 memset(vcpu->arch.pio_data, 0, size * count);
5270
6f6fbe98
XG		 5271 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5272 if (ret) {
5273data_avail:
5274 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5275 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5276 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5277 return 1;
5278 }
5279
cf8f70bf
GN		 5280 return 0;
5281}
5282
6f6fbe98
XG		 5283static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5284 int size, unsigned short port,
5285 const void *val, unsigned int count)
5286{
5287 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5288
5289 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5290 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5291 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5292}
5293
bbd9b64e
CO		 5294static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5295{
5296 return kvm_x86_ops->get_segment_base(vcpu, seg);
5297}
5298
3cb16fe7 5299static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5300{
3cb16fe7 5301 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5302}
5303
ae6a2375 5304static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5305{
5306 if (!need_emulate_wbinvd(vcpu))
5307 return X86EMUL_CONTINUE;
5308
5309 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5310 int cpu = get_cpu();
5311
5312 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5313 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5314 wbinvd_ipi, NULL, 1);
2eec7343 5315 put_cpu();
f5f48ee1 5316 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5317 } else
5318 wbinvd();
f5f48ee1
SY		 5319 return X86EMUL_CONTINUE;
5320}
5cb56059
JS		 5321
5322int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5323{
6affcbed
KH		 5324 kvm_emulate_wbinvd_noskip(vcpu);
5325 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5326}
f5f48ee1
SY		 5327EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5328
5cb56059
JS		 5329
5330
bcaf5cc5
AK		 5331static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5332{
5cb56059 5333 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5334}
5335
52eb5a6d
XL		 5336static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5337 unsigned long *dest)
bbd9b64e 5338{
16f8a6f9 5339 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5340}
5341
52eb5a6d
XL		 5342static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5343 unsigned long value)
bbd9b64e 5344{
338dbc97 5345
717746e3 5346 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5347}
5348
52a46617 5349static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5350{
52a46617 5351 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5352}
5353
717746e3 5354static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5355{
717746e3 5356 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5357 unsigned long value;
5358
5359 switch (cr) {
5360 case 0:
5361 value = kvm_read_cr0(vcpu);
5362 break;
5363 case 2:
5364 value = vcpu->arch.cr2;
5365 break;
5366 case 3:
9f8fe504 5367 value = kvm_read_cr3(vcpu);
52a46617
GN		 5368 break;
5369 case 4:
5370 value = kvm_read_cr4(vcpu);
5371 break;
5372 case 8:
5373 value = kvm_get_cr8(vcpu);
5374 break;
5375 default:
a737f256 5376 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5377 return 0;
5378 }
5379
5380 return value;
5381}
5382
717746e3 5383static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5384{
717746e3 5385 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5386 int res = 0;
5387
52a46617
GN		 5388 switch (cr) {
5389 case 0:
49a9b07e 5390 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5391 break;
5392 case 2:
5393 vcpu->arch.cr2 = val;
5394 break;
5395 case 3:
2390218b 5396 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5397 break;
5398 case 4:
a83b29c6 5399 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5400 break;
5401 case 8:
eea1cff9 5402 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5403 break;
5404 default:
a737f256 5405 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5406 res = -1;
52a46617 5407 }
0f12244f
GN		 5408
5409 return res;
52a46617
GN		 5410}
5411
717746e3 5412static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5413{
717746e3 5414 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5415}
5416
4bff1e86 5417static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5418{
4bff1e86 5419 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5420}
5421
4bff1e86 5422static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5423{
4bff1e86 5424 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5425}
5426
1ac9d0cf
AK		 5427static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5428{
5429 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5430}
5431
5432static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5433{
5434 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5435}
5436
4bff1e86
AK		 5437static unsigned long emulator_get_cached_segment_base(
5438 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5439{
4bff1e86 5440 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5441}
5442
1aa36616
AK		 5443static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5444 struct desc_struct *desc, u32 *base3,
5445 int seg)
2dafc6c2
GN		 5446{
5447 struct kvm_segment var;
5448
4bff1e86 5449 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5450 *selector = var.selector;
2dafc6c2 5451
378a8b09
GN		 5452 if (var.unusable) {
5453 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5454 if (base3)
5455 *base3 = 0;
2dafc6c2 5456 return false;
378a8b09 5457 }
2dafc6c2
GN		 5458
5459 if (var.g)
5460 var.limit >>= 12;
5461 set_desc_limit(desc, var.limit);
5462 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5463#ifdef CONFIG_X86_64
5464 if (base3)
5465 *base3 = var.base >> 32;
5466#endif
2dafc6c2
GN		 5467 desc->type = var.type;
5468 desc->s = var.s;
5469 desc->dpl = var.dpl;
5470 desc->p = var.present;
5471 desc->avl = var.avl;
5472 desc->l = var.l;
5473 desc->d = var.db;
5474 desc->g = var.g;
5475
5476 return true;
5477}
5478
1aa36616
AK		 5479static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5480 struct desc_struct *desc, u32 base3,
5481 int seg)
2dafc6c2 5482{
4bff1e86 5483 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5484 struct kvm_segment var;
5485
1aa36616 5486 var.selector = selector;
2dafc6c2 5487 var.base = get_desc_base(desc);
5601d05b
GN		 5488#ifdef CONFIG_X86_64
5489 var.base |= ((u64)base3) << 32;
5490#endif
2dafc6c2
GN		 5491 var.limit = get_desc_limit(desc);
5492 if (desc->g)
5493 var.limit = (var.limit << 12) | 0xfff;
5494 var.type = desc->type;
2dafc6c2
GN		 5495 var.dpl = desc->dpl;
5496 var.db = desc->d;
5497 var.s = desc->s;
5498 var.l = desc->l;
5499 var.g = desc->g;
5500 var.avl = desc->avl;
5501 var.present = desc->p;
5502 var.unusable = !var.present;
5503 var.padding = 0;
5504
5505 kvm_set_segment(vcpu, &var, seg);
5506 return;
5507}
5508
717746e3
AK		 5509static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5510 u32 msr_index, u64 *pdata)
5511{
609e36d3
PB		 5512 struct msr_data msr;
5513 int r;
5514
5515 msr.index = msr_index;
5516 msr.host_initiated = false;
5517 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5518 if (r)
5519 return r;
5520
5521 *pdata = msr.data;
5522 return 0;
717746e3
AK		 5523}
5524
5525static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5526 u32 msr_index, u64 data)
5527{
8fe8ab46
WA		 5528 struct msr_data msr;
5529
5530 msr.data = data;
5531 msr.index = msr_index;
5532 msr.host_initiated = false;
5533 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5534}
5535
64d60670
PB		 5536static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5537{
5538 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5539
5540 return vcpu->arch.smbase;
5541}
5542
5543static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5544{
5545 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5546
5547 vcpu->arch.smbase = smbase;
5548}
5549
67f4d428
NA		 5550static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5551 u32 pmc)
5552{
c6702c9d 5553 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5554}
5555
222d21aa
AK		 5556static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5557 u32 pmc, u64 *pdata)
5558{
c6702c9d 5559 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5560}
5561
6c3287f7
AK		 5562static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5563{
5564 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5565}
5566
2953538e 5567static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5568 struct x86_instruction_info *info,
c4f035c6
AK		 5569 enum x86_intercept_stage stage)
5570{
2953538e 5571 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5572}
5573
e911eb3b
YZ		 5574static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5575 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5576{
e911eb3b 5577 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5578}
5579
dd856efa
AK		 5580static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5581{
5582 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5583}
5584
5585static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5586{
5587 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5588}
5589
801806d9
NA		 5590static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5591{
5592 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5593}
5594
6ed071f0
LP		 5595static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5596{
5597 return emul_to_vcpu(ctxt)->arch.hflags;
5598}
5599
5600static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5601{
5602 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5603}
5604
0234bf88
LP		 5605static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5606{
5607 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5608}
5609
0225fb50 5610static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5611 .read_gpr = emulator_read_gpr,
5612 .write_gpr = emulator_write_gpr,
1871c602 5613 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5614 .write_std = kvm_write_guest_virt_system,
7a036a6f 5615 .read_phys = kvm_read_guest_phys_system,
1871c602 5616 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5617 .read_emulated = emulator_read_emulated,
5618 .write_emulated = emulator_write_emulated,
5619 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5620 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5621 .pio_in_emulated = emulator_pio_in_emulated,
5622 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5623 .get_segment = emulator_get_segment,
5624 .set_segment = emulator_set_segment,
5951c442 5625 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5626 .get_gdt = emulator_get_gdt,
160ce1f1 5627 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5628 .set_gdt = emulator_set_gdt,
5629 .set_idt = emulator_set_idt,
52a46617
GN		 5630 .get_cr = emulator_get_cr,
5631 .set_cr = emulator_set_cr,
9c537244 5632 .cpl = emulator_get_cpl,
35aa5375
GN		 5633 .get_dr = emulator_get_dr,
5634 .set_dr = emulator_set_dr,
64d60670
PB		 5635 .get_smbase = emulator_get_smbase,
5636 .set_smbase = emulator_set_smbase,
717746e3
AK		 5637 .set_msr = emulator_set_msr,
5638 .get_msr = emulator_get_msr,
67f4d428 5639 .check_pmc = emulator_check_pmc,
222d21aa 5640 .read_pmc = emulator_read_pmc,
6c3287f7 5641 .halt = emulator_halt,
bcaf5cc5 5642 .wbinvd = emulator_wbinvd,
d6aa1000 5643 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5644 .intercept = emulator_intercept,
bdb42f5a 5645 .get_cpuid = emulator_get_cpuid,
801806d9 5646 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5647 .get_hflags = emulator_get_hflags,
5648 .set_hflags = emulator_set_hflags,
0234bf88 5649 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5650};
5651
95cb2295
GN		 5652static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5653{
37ccdcbe 5654 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5655 /*
5656 * an sti; sti; sequence only disable interrupts for the first
5657 * instruction. So, if the last instruction, be it emulated or
5658 * not, left the system with the INT_STI flag enabled, it
5659 * means that the last instruction is an sti. We should not
5660 * leave the flag on in this case. The same goes for mov ss
5661 */
37ccdcbe
PB		 5662 if (int_shadow & mask)
5663 mask = 0;
6addfc42 5664 if (unlikely(int_shadow || mask)) {
95cb2295 5665 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5666 if (!mask)
5667 kvm_make_request(KVM_REQ_EVENT, vcpu);
5668 }
95cb2295
GN		 5669}
5670
ef54bcfe 5671static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5672{
5673 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5674 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5675 return kvm_propagate_fault(vcpu, &ctxt->exception);
5676
5677 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5678 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5679 ctxt->exception.error_code);
54b8486f 5680 else
da9cb575 5681 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5682 return false;
54b8486f
GN		 5683}
5684
8ec4722d
MG		 5685static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5686{
adf52235 5687 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5688 int cs_db, cs_l;
5689
8ec4722d
MG		 5690 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5691
adf52235 5692 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5693 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5694
adf52235
TY		 5695 ctxt->eip = kvm_rip_read(vcpu);
5696 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5697 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5698 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5699 cs_db ? X86EMUL_MODE_PROT32 :
5700 X86EMUL_MODE_PROT16;
a584539b 5701 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5702 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5703 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5704
dd856efa 5705 init_decode_cache(ctxt);
7ae441ea 5706 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5707}
5708
71f9833b 5709int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5710{
9d74191a 5711 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5712 int ret;
5713
5714 init_emulate_ctxt(vcpu);
5715
9dac77fa
AK		 5716 ctxt->op_bytes = 2;
5717 ctxt->ad_bytes = 2;
5718 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5719 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5720
5721 if (ret != X86EMUL_CONTINUE)
5722 return EMULATE_FAIL;
5723
9dac77fa 5724 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5725 kvm_rip_write(vcpu, ctxt->eip);
5726 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5727
63995653
MG		 5728 return EMULATE_DONE;
5729}
5730EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5731
e2366171 5732static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5733{
fc3a9157
JR		 5734 int r = EMULATE_DONE;
5735
6d77dbfc
GN		 5736 ++vcpu->stat.insn_emulation_fail;
5737 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5738
5739 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5740 return EMULATE_FAIL;
5741
a2b9e6c1 5742 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5743 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5744 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5745 vcpu->run->internal.ndata = 0;
1f4dcb3b 5746 r = EMULATE_USER_EXIT;
fc3a9157 5747 }
e2366171 5748
6d77dbfc 5749 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5750
5751 return r;
6d77dbfc
GN		 5752}
5753
93c05d3e 5754static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5755 bool write_fault_to_shadow_pgtable,
5756 int emulation_type)
a6f177ef 5757{
95b3cf69 5758 gpa_t gpa = cr2;
ba049e93 5759 kvm_pfn_t pfn;
a6f177ef 5760
991eebf9
GN		 5761 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5762 return false;
5763
95b3cf69
XG		 5764 if (!vcpu->arch.mmu.direct_map) {
5765 /*
5766 * Write permission should be allowed since only
5767 * write access need to be emulated.
5768 */
5769 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5770
95b3cf69
XG		 5771 /*
5772 * If the mapping is invalid in guest, let cpu retry
5773 * it to generate fault.
5774 */
5775 if (gpa == UNMAPPED_GVA)
5776 return true;
5777 }
a6f177ef 5778
8e3d9d06
XG		 5779 /*
5780 * Do not retry the unhandleable instruction if it faults on the
5781 * readonly host memory, otherwise it will goto a infinite loop:
5782 * retry instruction -> write #PF -> emulation fail -> retry
5783 * instruction -> ...
5784 */
5785 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5786
5787 /*
5788 * If the instruction failed on the error pfn, it can not be fixed,
5789 * report the error to userspace.
5790 */
5791 if (is_error_noslot_pfn(pfn))
5792 return false;
5793
5794 kvm_release_pfn_clean(pfn);
5795
5796 /* The instructions are well-emulated on direct mmu. */
5797 if (vcpu->arch.mmu.direct_map) {
5798 unsigned int indirect_shadow_pages;
5799
5800 spin_lock(&vcpu->kvm->mmu_lock);
5801 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5802 spin_unlock(&vcpu->kvm->mmu_lock);
5803
5804 if (indirect_shadow_pages)
5805 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5806
a6f177ef 5807 return true;
8e3d9d06 5808 }
a6f177ef 5809
95b3cf69
XG		 5810 /*
5811 * if emulation was due to access to shadowed page table
5812 * and it failed try to unshadow page and re-enter the
5813 * guest to let CPU execute the instruction.
5814 */
5815 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5816
5817 /*
5818 * If the access faults on its page table, it can not
5819 * be fixed by unprotecting shadow page and it should
5820 * be reported to userspace.
5821 */
5822 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5823}
5824
1cb3f3ae
XG		 5825static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5826 unsigned long cr2, int emulation_type)
5827{
5828 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5829 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5830
5831 last_retry_eip = vcpu->arch.last_retry_eip;
5832 last_retry_addr = vcpu->arch.last_retry_addr;
5833
5834 /*
5835 * If the emulation is caused by #PF and it is non-page_table
5836 * writing instruction, it means the VM-EXIT is caused by shadow
5837 * page protected, we can zap the shadow page and retry this
5838 * instruction directly.
5839 *
5840 * Note: if the guest uses a non-page-table modifying instruction
5841 * on the PDE that points to the instruction, then we will unmap
5842 * the instruction and go to an infinite loop. So, we cache the
5843 * last retried eip and the last fault address, if we meet the eip
5844 * and the address again, we can break out of the potential infinite
5845 * loop.
5846 */
5847 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5848
5849 if (!(emulation_type & EMULTYPE_RETRY))
5850 return false;
5851
5852 if (x86_page_table_writing_insn(ctxt))
5853 return false;
5854
5855 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5856 return false;
5857
5858 vcpu->arch.last_retry_eip = ctxt->eip;
5859 vcpu->arch.last_retry_addr = cr2;
5860
5861 if (!vcpu->arch.mmu.direct_map)
5862 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5863
22368028 5864 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5865
5866 return true;
5867}
5868
716d51ab
GN		 5869static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5870static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5871
64d60670 5872static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5873{
64d60670 5874 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5875 /* This is a good place to trace that we are exiting SMM. */
5876 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5877
c43203ca
PB		 5878 /* Process a latched INIT or SMI, if any. */
5879 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5880 }
699023e2
PB		 5881
5882 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5883}
5884
5885static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5886{
5887 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5888
a584539b 5889 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5890
5891 if (changed & HF_SMM_MASK)
5892 kvm_smm_changed(vcpu);
a584539b
PB		 5893}
5894
4a1e10d5
PB		 5895static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5896 unsigned long *db)
5897{
5898 u32 dr6 = 0;
5899 int i;
5900 u32 enable, rwlen;
5901
5902 enable = dr7;
5903 rwlen = dr7 >> 16;
5904 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5905 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5906 dr6 |= (1 << i);
5907 return dr6;
5908}
5909
c8401dda 5910static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5911{
5912 struct kvm_run *kvm_run = vcpu->run;
5913
c8401dda
PB		 5914 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5915 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5916 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5917 kvm_run->debug.arch.exception = DB_VECTOR;
5918 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5919 *r = EMULATE_USER_EXIT;
5920 } else {
5921 /*
5922 * "Certain debug exceptions may clear bit 0-3. The
5923 * remaining contents of the DR6 register are never
5924 * cleared by the processor".
5925 */
5926 vcpu->arch.dr6 &= ~15;
5927 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5928 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5929 }
5930}
5931
6affcbed
KH		 5932int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5933{
5934 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5935 int r = EMULATE_DONE;
5936
5937 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5938
5939 /*
5940 * rflags is the old, "raw" value of the flags. The new value has
5941 * not been saved yet.
5942 *
5943 * This is correct even for TF set by the guest, because "the
5944 * processor will not generate this exception after the instruction
5945 * that sets the TF flag".
5946 */
5947 if (unlikely(rflags & X86_EFLAGS_TF))
5948 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5949 return r == EMULATE_DONE;
5950}
5951EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5952
4a1e10d5
PB		 5953static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5954{
4a1e10d5
PB		 5955 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5956 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5957 struct kvm_run *kvm_run = vcpu->run;
5958 unsigned long eip = kvm_get_linear_rip(vcpu);
5959 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5960 vcpu->arch.guest_debug_dr7,
5961 vcpu->arch.eff_db);
5962
5963 if (dr6 != 0) {
6f43ed01 5964 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5965 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5966 kvm_run->debug.arch.exception = DB_VECTOR;
5967 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5968 *r = EMULATE_USER_EXIT;
5969 return true;
5970 }
5971 }
5972
4161a569
NA		 5973 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5974 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5975 unsigned long eip = kvm_get_linear_rip(vcpu);
5976 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5977 vcpu->arch.dr7,
5978 vcpu->arch.db);
5979
5980 if (dr6 != 0) {
5981 vcpu->arch.dr6 &= ~15;
6f43ed01 5982 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5983 kvm_queue_exception(vcpu, DB_VECTOR);
5984 *r = EMULATE_DONE;
5985 return true;
5986 }
5987 }
5988
5989 return false;
5990}
5991
04789b66
LA		 5992static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
5993{
2d7921c4
AM		 5994 switch (ctxt->opcode_len) {
5995 case 1:
5996 switch (ctxt->b) {
5997 case 0xe4: /* IN */
5998 case 0xe5:
5999 case 0xec:
6000 case 0xed:
6001 case 0xe6: /* OUT */
6002 case 0xe7:
6003 case 0xee:
6004 case 0xef:
6005 case 0x6c: /* INS */
6006 case 0x6d:
6007 case 0x6e: /* OUTS */
6008 case 0x6f:
6009 return true;
6010 }
6011 break;
6012 case 2:
6013 switch (ctxt->b) {
6014 case 0x33: /* RDPMC */
6015 return true;
6016 }
6017 break;
04789b66
LA		 6018 }
6019
6020 return false;
6021}
6022
51d8b661
AP		 6023int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6024 unsigned long cr2,
dc25e89e
AP		 6025 int emulation_type,
6026 void *insn,
6027 int insn_len)
bbd9b64e 6028{
95cb2295 6029 int r;
9d74191a 6030 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6031 bool writeback = true;
93c05d3e 6032 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6033
93c05d3e
XG		 6034 /*
6035 * Clear write_fault_to_shadow_pgtable here to ensure it is
6036 * never reused.
6037 */
6038 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6039 kvm_clear_exception_queue(vcpu);
8d7d8102 6040
571008da 6041 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6042 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6043
6044 /*
6045 * We will reenter on the same instruction since
6046 * we do not set complete_userspace_io. This does not
6047 * handle watchpoints yet, those would be handled in
6048 * the emulate_ops.
6049 */
d391f120
VK		 6050 if (!(emulation_type & EMULTYPE_SKIP) &&
6051 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6052 return r;
6053
9d74191a
TY		 6054 ctxt->interruptibility = 0;
6055 ctxt->have_exception = false;
e0ad0b47 6056 ctxt->exception.vector = -1;
9d74191a 6057 ctxt->perm_ok = false;
bbd9b64e 6058
b51e974f 6059 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6060
9d74191a 6061 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6062
e46479f8 6063 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6064 ++vcpu->stat.insn_emulation;
1d2887e2 6065 if (r != EMULATION_OK) {
4005996e
AK		 6066 if (emulation_type & EMULTYPE_TRAP_UD)
6067 return EMULATE_FAIL;
991eebf9
GN		 6068 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6069 emulation_type))
bbd9b64e 6070 return EMULATE_DONE;
6ea6e843
PB		 6071 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6072 return EMULATE_DONE;
6d77dbfc
GN		 6073 if (emulation_type & EMULTYPE_SKIP)
6074 return EMULATE_FAIL;
e2366171 6075 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6076 }
6077 }
6078
04789b66
LA		 6079 if ((emulation_type & EMULTYPE_VMWARE) &&
6080 !is_vmware_backdoor_opcode(ctxt))
6081 return EMULATE_FAIL;
6082
ba8afb6b 6083 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6084 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6085 if (ctxt->eflags & X86_EFLAGS_RF)
6086 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6087 return EMULATE_DONE;
6088 }
6089
1cb3f3ae
XG		 6090 if (retry_instruction(ctxt, cr2, emulation_type))
6091 return EMULATE_DONE;
6092
7ae441ea 6093 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6094 changes registers values during IO operation */
7ae441ea
GN		 6095 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6096 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6097 emulator_invalidate_register_cache(ctxt);
7ae441ea 6098 }
4d2179e1 6099
5cd21917 6100restart:
0f89b207
TL		 6101 /* Save the faulting GPA (cr2) in the address field */
6102 ctxt->exception.address = cr2;
6103
9d74191a 6104 r = x86_emulate_insn(ctxt);
bbd9b64e 6105
775fde86
JR		 6106 if (r == EMULATION_INTERCEPTED)
6107 return EMULATE_DONE;
6108
d2ddd1c4 6109 if (r == EMULATION_FAILED) {
991eebf9
GN		 6110 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6111 emulation_type))
c3cd7ffa
GN		 6112 return EMULATE_DONE;
6113
e2366171 6114 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6115 }
6116
9d74191a 6117 if (ctxt->have_exception) {
d2ddd1c4 6118 r = EMULATE_DONE;
ef54bcfe
PB		 6119 if (inject_emulated_exception(vcpu))
6120 return r;
d2ddd1c4 6121 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6122 if (!vcpu->arch.pio.in) {
6123 /* FIXME: return into emulator if single-stepping. */
3457e419 6124 vcpu->arch.pio.count = 0;
0912c977 6125 } else {
7ae441ea 6126 writeback = false;
716d51ab
GN		 6127 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6128 }
ac0a48c3 6129 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6130 } else if (vcpu->mmio_needed) {
6131 if (!vcpu->mmio_is_write)
6132 writeback = false;
ac0a48c3 6133 r = EMULATE_USER_EXIT;
716d51ab 6134 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6135 } else if (r == EMULATION_RESTART)
5cd21917 6136 goto restart;
d2ddd1c4
GN		 6137 else
6138 r = EMULATE_DONE;
f850e2e6 6139
7ae441ea 6140 if (writeback) {
6addfc42 6141 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6142 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6143 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6144 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6145 if (r == EMULATE_DONE &&
6146 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6147 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6148 if (!ctxt->have_exception ||
6149 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6150 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6151
6152 /*
6153 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6154 * do nothing, and it will be requested again as soon as
6155 * the shadow expires. But we still need to check here,
6156 * because POPF has no interrupt shadow.
6157 */
6158 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6159 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6160 } else
6161 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6162
6163 return r;
de7d789a 6164}
51d8b661 6165EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6166
dca7f128
SC		 6167static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6168 unsigned short port)
de7d789a 6169{
cf8f70bf 6170 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6171 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6172 size, port, &val, 1);
cf8f70bf 6173 /* do not return to emulator after return from userspace */
7972995b 6174 vcpu->arch.pio.count = 0;
de7d789a
CO		 6175 return ret;
6176}
de7d789a 6177
8370c3d0
TL		 6178static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6179{
6180 unsigned long val;
6181
6182 /* We should only ever be called with arch.pio.count equal to 1 */
6183 BUG_ON(vcpu->arch.pio.count != 1);
6184
6185 /* For size less than 4 we merge, else we zero extend */
6186 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6187 : 0;
6188
6189 /*
6190 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6191 * the copy and tracing
6192 */
6193 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6194 vcpu->arch.pio.port, &val, 1);
6195 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6196
6197 return 1;
6198}
6199
dca7f128
SC		 6200static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6201 unsigned short port)
8370c3d0
TL		 6202{
6203 unsigned long val;
6204 int ret;
6205
6206 /* For size less than 4 we merge, else we zero extend */
6207 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6208
6209 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6210 &val, 1);
6211 if (ret) {
6212 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6213 return ret;
6214 }
6215
6216 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6217
6218 return 0;
6219}
dca7f128
SC		 6220
6221int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6222{
6223 int ret = kvm_skip_emulated_instruction(vcpu);
6224
6225 /*
6226 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6227 * KVM_EXIT_DEBUG here.
6228 */
6229 if (in)
6230 return kvm_fast_pio_in(vcpu, size, port) && ret;
6231 else
6232 return kvm_fast_pio_out(vcpu, size, port) && ret;
6233}
6234EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6235
251a5fd6 6236static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6237{
0a3aee0d 6238 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6239 return 0;
8cfdc000
ZA		 6240}
6241
6242static void tsc_khz_changed(void *data)
c8076604 6243{
8cfdc000
ZA		 6244 struct cpufreq_freqs *freq = data;
6245 unsigned long khz = 0;
6246
6247 if (data)
6248 khz = freq->new;
6249 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6250 khz = cpufreq_quick_get(raw_smp_processor_id());
6251 if (!khz)
6252 khz = tsc_khz;
0a3aee0d 6253 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6254}
6255
5fa4ec9c 6256#ifdef CONFIG_X86_64
0092e434
VK		 6257static void kvm_hyperv_tsc_notifier(void)
6258{
0092e434
VK		 6259 struct kvm *kvm;
6260 struct kvm_vcpu *vcpu;
6261 int cpu;
6262
6263 spin_lock(&kvm_lock);
6264 list_for_each_entry(kvm, &vm_list, vm_list)
6265 kvm_make_mclock_inprogress_request(kvm);
6266
6267 hyperv_stop_tsc_emulation();
6268
6269 /* TSC frequency always matches when on Hyper-V */
6270 for_each_present_cpu(cpu)
6271 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6272 kvm_max_guest_tsc_khz = tsc_khz;
6273
6274 list_for_each_entry(kvm, &vm_list, vm_list) {
6275 struct kvm_arch *ka = &kvm->arch;
6276
6277 spin_lock(&ka->pvclock_gtod_sync_lock);
6278
6279 pvclock_update_vm_gtod_copy(kvm);
6280
6281 kvm_for_each_vcpu(cpu, vcpu, kvm)
6282 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6283
6284 kvm_for_each_vcpu(cpu, vcpu, kvm)
6285 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6286
6287 spin_unlock(&ka->pvclock_gtod_sync_lock);
6288 }
6289 spin_unlock(&kvm_lock);
0092e434 6290}
5fa4ec9c 6291#endif
0092e434 6292
c8076604
GH		 6293static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6294 void *data)
6295{
6296 struct cpufreq_freqs *freq = data;
6297 struct kvm *kvm;
6298 struct kvm_vcpu *vcpu;
6299 int i, send_ipi = 0;
6300
8cfdc000
ZA		 6301 /*
6302 * We allow guests to temporarily run on slowing clocks,
6303 * provided we notify them after, or to run on accelerating
6304 * clocks, provided we notify them before. Thus time never
6305 * goes backwards.
6306 *
6307 * However, we have a problem. We can't atomically update
6308 * the frequency of a given CPU from this function; it is
6309 * merely a notifier, which can be called from any CPU.
6310 * Changing the TSC frequency at arbitrary points in time
6311 * requires a recomputation of local variables related to
6312 * the TSC for each VCPU. We must flag these local variables
6313 * to be updated and be sure the update takes place with the
6314 * new frequency before any guests proceed.
6315 *
6316 * Unfortunately, the combination of hotplug CPU and frequency
6317 * change creates an intractable locking scenario; the order
6318 * of when these callouts happen is undefined with respect to
6319 * CPU hotplug, and they can race with each other. As such,
6320 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6321 * undefined; you can actually have a CPU frequency change take
6322 * place in between the computation of X and the setting of the
6323 * variable. To protect against this problem, all updates of
6324 * the per_cpu tsc_khz variable are done in an interrupt
6325 * protected IPI, and all callers wishing to update the value
6326 * must wait for a synchronous IPI to complete (which is trivial
6327 * if the caller is on the CPU already). This establishes the
6328 * necessary total order on variable updates.
6329 *
6330 * Note that because a guest time update may take place
6331 * anytime after the setting of the VCPU's request bit, the
6332 * correct TSC value must be set before the request. However,
6333 * to ensure the update actually makes it to any guest which
6334 * starts running in hardware virtualization between the set
6335 * and the acquisition of the spinlock, we must also ping the
6336 * CPU after setting the request bit.
6337 *
6338 */
6339
c8076604
GH		 6340 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6341 return 0;
6342 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6343 return 0;
8cfdc000
ZA		 6344
6345 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6346
2f303b74 6347 spin_lock(&kvm_lock);
c8076604 6348 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6349 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6350 if (vcpu->cpu != freq->cpu)
6351 continue;
c285545f 6352 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6353 if (vcpu->cpu != smp_processor_id())
8cfdc000 6354 send_ipi = 1;
c8076604
GH		 6355 }
6356 }
2f303b74 6357 spin_unlock(&kvm_lock);
c8076604
GH		 6358
6359 if (freq->old < freq->new && send_ipi) {
6360 /*
6361 * We upscale the frequency. Must make the guest
6362 * doesn't see old kvmclock values while running with
6363 * the new frequency, otherwise we risk the guest sees
6364 * time go backwards.
6365 *
6366 * In case we update the frequency for another cpu
6367 * (which might be in guest context) send an interrupt
6368 * to kick the cpu out of guest context. Next time
6369 * guest context is entered kvmclock will be updated,
6370 * so the guest will not see stale values.
6371 */
8cfdc000 6372 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6373 }
6374 return 0;
6375}
6376
6377static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6378 .notifier_call = kvmclock_cpufreq_notifier
6379};
6380
251a5fd6 6381static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6382{
251a5fd6
SAS		 6383 tsc_khz_changed(NULL);
6384 return 0;
8cfdc000
ZA		 6385}
6386
b820cc0c
ZA		 6387static void kvm_timer_init(void)
6388{
c285545f 6389 max_tsc_khz = tsc_khz;
460dd42e 6390
b820cc0c 6391 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6392#ifdef CONFIG_CPU_FREQ
6393 struct cpufreq_policy policy;
758f588d
BP		 6394 int cpu;
6395
c285545f 6396 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6397 cpu = get_cpu();
6398 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6399 if (policy.cpuinfo.max_freq)
6400 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6401 put_cpu();
c285545f 6402#endif
b820cc0c
ZA		 6403 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6404 CPUFREQ_TRANSITION_NOTIFIER);
6405 }
c285545f 6406 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6407
73c1b41e 6408 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6409 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6410}
6411
dd60d217
AK		 6412DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6413EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6414
f5132b01 6415int kvm_is_in_guest(void)
ff9d07a0 6416{
086c9855 6417 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6418}
6419
6420static int kvm_is_user_mode(void)
6421{
6422 int user_mode = 3;
dcf46b94 6423
086c9855
AS		 6424 if (__this_cpu_read(current_vcpu))
6425 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6426
ff9d07a0
ZY		 6427 return user_mode != 0;
6428}
6429
6430static unsigned long kvm_get_guest_ip(void)
6431{
6432 unsigned long ip = 0;
dcf46b94 6433
086c9855
AS		 6434 if (__this_cpu_read(current_vcpu))
6435 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6436
ff9d07a0
ZY		 6437 return ip;
6438}
6439
6440static struct perf_guest_info_callbacks kvm_guest_cbs = {
6441 .is_in_guest = kvm_is_in_guest,
6442 .is_user_mode = kvm_is_user_mode,
6443 .get_guest_ip = kvm_get_guest_ip,
6444};
6445
ce88decf
XG		 6446static void kvm_set_mmio_spte_mask(void)
6447{
6448 u64 mask;
6449 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6450
6451 /*
6452 * Set the reserved bits and the present bit of an paging-structure
6453 * entry to generate page fault with PFER.RSV = 1.
6454 */
885032b9 6455 /* Mask the reserved physical address bits. */
d1431483 6456 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6457
885032b9 6458 /* Set the present bit. */
ce88decf
XG		 6459 mask |= 1ull;
6460
6461#ifdef CONFIG_X86_64
6462 /*
6463 * If reserved bit is not supported, clear the present bit to disable
6464 * mmio page fault.
6465 */
6466 if (maxphyaddr == 52)
6467 mask &= ~1ull;
6468#endif
6469
dcdca5fe 6470 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6471}
6472
16e8d74d
MT		 6473#ifdef CONFIG_X86_64
6474static void pvclock_gtod_update_fn(struct work_struct *work)
6475{
d828199e
MT		 6476 struct kvm *kvm;
6477
6478 struct kvm_vcpu *vcpu;
6479 int i;
6480
2f303b74 6481 spin_lock(&kvm_lock);
d828199e
MT		 6482 list_for_each_entry(kvm, &vm_list, vm_list)
6483 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6484 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6485 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6486 spin_unlock(&kvm_lock);
16e8d74d
MT		 6487}
6488
6489static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6490
6491/*
6492 * Notification about pvclock gtod data update.
6493 */
6494static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6495 void *priv)
6496{
6497 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6498 struct timekeeper *tk = priv;
6499
6500 update_pvclock_gtod(tk);
6501
6502 /* disable master clock if host does not trust, or does not
b0c39dc6 6503 * use, TSC based clocksource.
16e8d74d 6504 */
b0c39dc6 6505 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6506 atomic_read(&kvm_guest_has_master_clock) != 0)
6507 queue_work(system_long_wq, &pvclock_gtod_work);
6508
6509 return 0;
6510}
6511
6512static struct notifier_block pvclock_gtod_notifier = {
6513 .notifier_call = pvclock_gtod_notify,
6514};
6515#endif
6516
f8c16bba 6517int kvm_arch_init(void *opaque)
043405e1 6518{
b820cc0c 6519 int r;
6b61edf7 6520 struct kvm_x86_ops *ops = opaque;
f8c16bba 6521
f8c16bba
ZX		 6522 if (kvm_x86_ops) {
6523 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6524 r = -EEXIST;
6525 goto out;
f8c16bba
ZX		 6526 }
6527
6528 if (!ops->cpu_has_kvm_support()) {
6529 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6530 r = -EOPNOTSUPP;
6531 goto out;
f8c16bba
ZX		 6532 }
6533 if (ops->disabled_by_bios()) {
6534 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6535 r = -EOPNOTSUPP;
6536 goto out;
f8c16bba
ZX		 6537 }
6538
013f6a5d
MT		 6539 r = -ENOMEM;
6540 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6541 if (!shared_msrs) {
6542 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6543 goto out;
6544 }
6545
97db56ce
AK		 6546 r = kvm_mmu_module_init();
6547 if (r)
013f6a5d 6548 goto out_free_percpu;
97db56ce 6549
ce88decf 6550 kvm_set_mmio_spte_mask();
97db56ce 6551
f8c16bba 6552 kvm_x86_ops = ops;
920c8377 6553
7b52345e 6554 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6555 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6556 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6557 kvm_timer_init();
c8076604 6558
ff9d07a0
ZY		 6559 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6560
d366bf7e 6561 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6562 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6563
c5cc421b 6564 kvm_lapic_init();
16e8d74d
MT		 6565#ifdef CONFIG_X86_64
6566 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6567
5fa4ec9c 6568 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6569 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6570#endif
6571
f8c16bba 6572 return 0;
56c6d28a 6573
013f6a5d
MT		 6574out_free_percpu:
6575 free_percpu(shared_msrs);
56c6d28a 6576out:
56c6d28a 6577 return r;
043405e1 6578}
8776e519 6579
f8c16bba
ZX		 6580void kvm_arch_exit(void)
6581{
0092e434 6582#ifdef CONFIG_X86_64
5fa4ec9c 6583 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6584 clear_hv_tscchange_cb();
6585#endif
cef84c30 6586 kvm_lapic_exit();
ff9d07a0
ZY		 6587 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6588
888d256e
JK		 6589 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6590 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6591 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6592 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6593#ifdef CONFIG_X86_64
6594 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6595#endif
f8c16bba 6596 kvm_x86_ops = NULL;
56c6d28a 6597 kvm_mmu_module_exit();
013f6a5d 6598 free_percpu(shared_msrs);
56c6d28a 6599}
f8c16bba 6600
5cb56059 6601int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6602{
6603 ++vcpu->stat.halt_exits;
35754c98 6604 if (lapic_in_kernel(vcpu)) {
a4535290 6605 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6606 return 1;
6607 } else {
6608 vcpu->run->exit_reason = KVM_EXIT_HLT;
6609 return 0;
6610 }
6611}
5cb56059
JS		 6612EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6613
6614int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6615{
6affcbed
KH		 6616 int ret = kvm_skip_emulated_instruction(vcpu);
6617 /*
6618 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6619 * KVM_EXIT_DEBUG here.
6620 */
6621 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6622}
8776e519
HB		 6623EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6624
8ef81a9a 6625#ifdef CONFIG_X86_64
55dd00a7
MT		 6626static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6627 unsigned long clock_type)
6628{
6629 struct kvm_clock_pairing clock_pairing;
899a31f5 6630 struct timespec64 ts;
80fbd89c 6631 u64 cycle;
55dd00a7
MT		 6632 int ret;
6633
6634 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6635 return -KVM_EOPNOTSUPP;
6636
6637 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6638 return -KVM_EOPNOTSUPP;
6639
6640 clock_pairing.sec = ts.tv_sec;
6641 clock_pairing.nsec = ts.tv_nsec;
6642 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6643 clock_pairing.flags = 0;
6644
6645 ret = 0;
6646 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6647 sizeof(struct kvm_clock_pairing)))
6648 ret = -KVM_EFAULT;
6649
6650 return ret;
6651}
8ef81a9a 6652#endif
55dd00a7 6653
6aef266c
SV		 6654/*
6655 * kvm_pv_kick_cpu_op: Kick a vcpu.
6656 *
6657 * @apicid - apicid of vcpu to be kicked.
6658 */
6659static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6660{
24d2166b 6661 struct kvm_lapic_irq lapic_irq;
6aef266c 6662
24d2166b
R		 6663 lapic_irq.shorthand = 0;
6664 lapic_irq.dest_mode = 0;
ebd28fcb 6665 lapic_irq.level = 0;
24d2166b 6666 lapic_irq.dest_id = apicid;
93bbf0b8 6667 lapic_irq.msi_redir_hint = false;
6aef266c 6668
24d2166b 6669 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6670 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6671}
6672
d62caabb
AS		 6673void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6674{
6675 vcpu->arch.apicv_active = false;
6676 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6677}
6678
8776e519
HB		 6679int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6680{
6681 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6682 int op_64_bit;
8776e519 6683
6356ee0c
MR		 6684 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6685 if (!kvm_hv_hypercall(vcpu))
6686 return 0;
6687 goto out;
6688 }
55cd8e5a 6689
5fdbf976
MT		 6690 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6691 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6692 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6693 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6694 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6695
229456fc 6696 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6697
a449c7aa
NA		 6698 op_64_bit = is_64_bit_mode(vcpu);
6699 if (!op_64_bit) {
8776e519
HB		 6700 nr &= 0xFFFFFFFF;
6701 a0 &= 0xFFFFFFFF;
6702 a1 &= 0xFFFFFFFF;
6703 a2 &= 0xFFFFFFFF;
6704 a3 &= 0xFFFFFFFF;
6705 }
6706
07708c4a
JK		 6707 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6708 ret = -KVM_EPERM;
6356ee0c 6709 goto out_error;
07708c4a
JK		 6710 }
6711
8776e519 6712 switch (nr) {
b93463aa
AK		 6713 case KVM_HC_VAPIC_POLL_IRQ:
6714 ret = 0;
6715 break;
6aef266c
SV		 6716 case KVM_HC_KICK_CPU:
6717 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6718 ret = 0;
6719 break;
8ef81a9a 6720#ifdef CONFIG_X86_64
55dd00a7
MT		 6721 case KVM_HC_CLOCK_PAIRING:
6722 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6723 break;
8ef81a9a 6724#endif
8776e519
HB		 6725 default:
6726 ret = -KVM_ENOSYS;
6727 break;
6728 }
6356ee0c 6729out_error:
a449c7aa
NA		 6730 if (!op_64_bit)
6731 ret = (u32)ret;
5fdbf976 6732 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c
MR		 6733
6734out:
f11c3a8d 6735 ++vcpu->stat.hypercalls;
6356ee0c 6736 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6737}
6738EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6739
b6785def 6740static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6741{
d6aa1000 6742 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6743 char instruction[3];
5fdbf976 6744 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6745
8776e519 6746 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6747
ce2e852e
DV		 6748 return emulator_write_emulated(ctxt, rip, instruction, 3,
6749 &ctxt->exception);
8776e519
HB		 6750}
6751
851ba692 6752static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6753{
782d422b
MG		 6754 return vcpu->run->request_interrupt_window &&
6755 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6756}
6757
851ba692 6758static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6759{
851ba692
AK		 6760 struct kvm_run *kvm_run = vcpu->run;
6761
91586a3b 6762 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6763 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6764 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6765 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6766 kvm_run->ready_for_interrupt_injection =
6767 pic_in_kernel(vcpu->kvm) ||
782d422b 6768 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6769}
6770
95ba8273
GN		 6771static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6772{
6773 int max_irr, tpr;
6774
6775 if (!kvm_x86_ops->update_cr8_intercept)
6776 return;
6777
bce87cce 6778 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6779 return;
6780
d62caabb
AS		 6781 if (vcpu->arch.apicv_active)
6782 return;
6783
8db3baa2
GN		 6784 if (!vcpu->arch.apic->vapic_addr)
6785 max_irr = kvm_lapic_find_highest_irr(vcpu);
6786 else
6787 max_irr = -1;
95ba8273
GN		 6788
6789 if (max_irr != -1)
6790 max_irr >>= 4;
6791
6792 tpr = kvm_lapic_get_cr8(vcpu);
6793
6794 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6795}
6796
b6b8a145 6797static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6798{
b6b8a145
JK		 6799 int r;
6800
95ba8273 6801 /* try to reinject previous events if any */
664f8e26 6802
1a680e35
LA		 6803 if (vcpu->arch.exception.injected)
6804 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6805 /*
a042c26f
LA		 6806 * Do not inject an NMI or interrupt if there is a pending
6807 * exception. Exceptions and interrupts are recognized at
6808 * instruction boundaries, i.e. the start of an instruction.
6809 * Trap-like exceptions, e.g. #DB, have higher priority than
6810 * NMIs and interrupts, i.e. traps are recognized before an
6811 * NMI/interrupt that's pending on the same instruction.
6812 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6813 * priority, but are only generated (pended) during instruction
6814 * execution, i.e. a pending fault-like exception means the
6815 * fault occurred on the *previous* instruction and must be
6816 * serviced prior to recognizing any new events in order to
6817 * fully complete the previous instruction.
664f8e26 6818 */
1a680e35
LA		 6819 else if (!vcpu->arch.exception.pending) {
6820 if (vcpu->arch.nmi_injected)
664f8e26 6821 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6822 else if (vcpu->arch.interrupt.injected)
664f8e26 6823 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6824 }
6825
1a680e35
LA		 6826 /*
6827 * Call check_nested_events() even if we reinjected a previous event
6828 * in order for caller to determine if it should require immediate-exit
6829 * from L2 to L1 due to pending L1 events which require exit
6830 * from L2 to L1.
6831 */
664f8e26
WL		 6832 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6833 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6834 if (r != 0)
6835 return r;
6836 }
6837
6838 /* try to inject new event if pending */
b59bb7bd 6839 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6840 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6841 vcpu->arch.exception.has_error_code,
6842 vcpu->arch.exception.error_code);
d6e8c854 6843
1a680e35 6844 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6845 vcpu->arch.exception.pending = false;
6846 vcpu->arch.exception.injected = true;
6847
d6e8c854
NA		 6848 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6849 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6850 X86_EFLAGS_RF);
6851
6bdf0662
NA		 6852 if (vcpu->arch.exception.nr == DB_VECTOR &&
6853 (vcpu->arch.dr7 & DR7_GD)) {
6854 vcpu->arch.dr7 &= ~DR7_GD;
6855 kvm_update_dr7(vcpu);
6856 }
6857
cfcd20e5 6858 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6859 }
6860
6861 /* Don't consider new event if we re-injected an event */
6862 if (kvm_event_needs_reinjection(vcpu))
6863 return 0;
6864
6865 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6866 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6867 vcpu->arch.smi_pending = false;
52797bf9 6868 ++vcpu->arch.smi_count;
ee2cd4b7 6869 enter_smm(vcpu);
c43203ca 6870 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6871 --vcpu->arch.nmi_pending;
6872 vcpu->arch.nmi_injected = true;
6873 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6874 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6875 /*
6876 * Because interrupts can be injected asynchronously, we are
6877 * calling check_nested_events again here to avoid a race condition.
6878 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6879 * proposal and current concerns. Perhaps we should be setting
6880 * KVM_REQ_EVENT only on certain events and not unconditionally?
6881 */
6882 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6883 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6884 if (r != 0)
6885 return r;
6886 }
95ba8273 6887 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6888 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6889 false);
6890 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6891 }
6892 }
ee2cd4b7 6893
b6b8a145 6894 return 0;
95ba8273
GN		 6895}
6896
7460fb4a
AK		 6897static void process_nmi(struct kvm_vcpu *vcpu)
6898{
6899 unsigned limit = 2;
6900
6901 /*
6902 * x86 is limited to one NMI running, and one NMI pending after it.
6903 * If an NMI is already in progress, limit further NMIs to just one.
6904 * Otherwise, allow two (and we'll inject the first one immediately).
6905 */
6906 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6907 limit = 1;
6908
6909 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6910 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6911 kvm_make_request(KVM_REQ_EVENT, vcpu);
6912}
6913
ee2cd4b7 6914static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6915{
6916 u32 flags = 0;
6917 flags |= seg->g << 23;
6918 flags |= seg->db << 22;
6919 flags |= seg->l << 21;
6920 flags |= seg->avl << 20;
6921 flags |= seg->present << 15;
6922 flags |= seg->dpl << 13;
6923 flags |= seg->s << 12;
6924 flags |= seg->type << 8;
6925 return flags;
6926}
6927
ee2cd4b7 6928static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6929{
6930 struct kvm_segment seg;
6931 int offset;
6932
6933 kvm_get_segment(vcpu, &seg, n);
6934 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6935
6936 if (n < 3)
6937 offset = 0x7f84 + n * 12;
6938 else
6939 offset = 0x7f2c + (n - 3) * 12;
6940
6941 put_smstate(u32, buf, offset + 8, seg.base);
6942 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6943 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6944}
6945
efbb288a 6946#ifdef CONFIG_X86_64
ee2cd4b7 6947static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6948{
6949 struct kvm_segment seg;
6950 int offset;
6951 u16 flags;
6952
6953 kvm_get_segment(vcpu, &seg, n);
6954 offset = 0x7e00 + n * 16;
6955
ee2cd4b7 6956 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6957 put_smstate(u16, buf, offset, seg.selector);
6958 put_smstate(u16, buf, offset + 2, flags);
6959 put_smstate(u32, buf, offset + 4, seg.limit);
6960 put_smstate(u64, buf, offset + 8, seg.base);
6961}
efbb288a 6962#endif
660a5d51 6963
ee2cd4b7 6964static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6965{
6966 struct desc_ptr dt;
6967 struct kvm_segment seg;
6968 unsigned long val;
6969 int i;
6970
6971 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6972 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6973 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6974 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6975
6976 for (i = 0; i < 8; i++)
6977 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6978
6979 kvm_get_dr(vcpu, 6, &val);
6980 put_smstate(u32, buf, 0x7fcc, (u32)val);
6981 kvm_get_dr(vcpu, 7, &val);
6982 put_smstate(u32, buf, 0x7fc8, (u32)val);
6983
6984 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6985 put_smstate(u32, buf, 0x7fc4, seg.selector);
6986 put_smstate(u32, buf, 0x7f64, seg.base);
6987 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6988 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6989
6990 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6991 put_smstate(u32, buf, 0x7fc0, seg.selector);
6992 put_smstate(u32, buf, 0x7f80, seg.base);
6993 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6994 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6995
6996 kvm_x86_ops->get_gdt(vcpu, &dt);
6997 put_smstate(u32, buf, 0x7f74, dt.address);
6998 put_smstate(u32, buf, 0x7f70, dt.size);
6999
7000 kvm_x86_ops->get_idt(vcpu, &dt);
7001 put_smstate(u32, buf, 0x7f58, dt.address);
7002 put_smstate(u32, buf, 0x7f54, dt.size);
7003
7004 for (i = 0; i < 6; i++)
ee2cd4b7 7005 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7006
7007 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7008
7009 /* revision id */
7010 put_smstate(u32, buf, 0x7efc, 0x00020000);
7011 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7012}
7013
ee2cd4b7 7014static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7015{
7016#ifdef CONFIG_X86_64
7017 struct desc_ptr dt;
7018 struct kvm_segment seg;
7019 unsigned long val;
7020 int i;
7021
7022 for (i = 0; i < 16; i++)
7023 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7024
7025 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7026 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7027
7028 kvm_get_dr(vcpu, 6, &val);
7029 put_smstate(u64, buf, 0x7f68, val);
7030 kvm_get_dr(vcpu, 7, &val);
7031 put_smstate(u64, buf, 0x7f60, val);
7032
7033 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7034 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7035 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7036
7037 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7038
7039 /* revision id */
7040 put_smstate(u32, buf, 0x7efc, 0x00020064);
7041
7042 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7043
7044 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7045 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7046 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7047 put_smstate(u32, buf, 0x7e94, seg.limit);
7048 put_smstate(u64, buf, 0x7e98, seg.base);
7049
7050 kvm_x86_ops->get_idt(vcpu, &dt);
7051 put_smstate(u32, buf, 0x7e84, dt.size);
7052 put_smstate(u64, buf, 0x7e88, dt.address);
7053
7054 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7055 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7056 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7057 put_smstate(u32, buf, 0x7e74, seg.limit);
7058 put_smstate(u64, buf, 0x7e78, seg.base);
7059
7060 kvm_x86_ops->get_gdt(vcpu, &dt);
7061 put_smstate(u32, buf, 0x7e64, dt.size);
7062 put_smstate(u64, buf, 0x7e68, dt.address);
7063
7064 for (i = 0; i < 6; i++)
ee2cd4b7 7065 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7066#else
7067 WARN_ON_ONCE(1);
7068#endif
7069}
7070
ee2cd4b7 7071static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7072{
660a5d51 7073 struct kvm_segment cs, ds;
18c3626e 7074 struct desc_ptr dt;
660a5d51
PB		 7075 char buf[512];
7076 u32 cr0;
7077
660a5d51 7078 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7079 memset(buf, 0, 512);
d6321d49 7080 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7081 enter_smm_save_state_64(vcpu, buf);
660a5d51 7082 else
ee2cd4b7 7083 enter_smm_save_state_32(vcpu, buf);
660a5d51 7084
0234bf88
LP		 7085 /*
7086 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7087 * vCPU state (e.g. leave guest mode) after we've saved the state into
7088 * the SMM state-save area.
7089 */
7090 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7091
7092 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7093 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7094
7095 if (kvm_x86_ops->get_nmi_mask(vcpu))
7096 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7097 else
7098 kvm_x86_ops->set_nmi_mask(vcpu, true);
7099
7100 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7101 kvm_rip_write(vcpu, 0x8000);
7102
7103 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7104 kvm_x86_ops->set_cr0(vcpu, cr0);
7105 vcpu->arch.cr0 = cr0;
7106
7107 kvm_x86_ops->set_cr4(vcpu, 0);
7108
18c3626e
PB		 7109 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7110 dt.address = dt.size = 0;
7111 kvm_x86_ops->set_idt(vcpu, &dt);
7112
660a5d51
PB		 7113 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7114
7115 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7116 cs.base = vcpu->arch.smbase;
7117
7118 ds.selector = 0;
7119 ds.base = 0;
7120
7121 cs.limit = ds.limit = 0xffffffff;
7122 cs.type = ds.type = 0x3;
7123 cs.dpl = ds.dpl = 0;
7124 cs.db = ds.db = 0;
7125 cs.s = ds.s = 1;
7126 cs.l = ds.l = 0;
7127 cs.g = ds.g = 1;
7128 cs.avl = ds.avl = 0;
7129 cs.present = ds.present = 1;
7130 cs.unusable = ds.unusable = 0;
7131 cs.padding = ds.padding = 0;
7132
7133 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7134 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7135 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7136 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7137 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7138 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7139
d6321d49 7140 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7141 kvm_x86_ops->set_efer(vcpu, 0);
7142
7143 kvm_update_cpuid(vcpu);
7144 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7145}
7146
ee2cd4b7 7147static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7148{
7149 vcpu->arch.smi_pending = true;
7150 kvm_make_request(KVM_REQ_EVENT, vcpu);
7151}
7152
2860c4b1
PB		 7153void kvm_make_scan_ioapic_request(struct kvm *kvm)
7154{
7155 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7156}
7157
3d81bc7e 7158static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7159{
3d81bc7e
YZ		 7160 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7161 return;
c7c9c56c 7162
6308630b 7163 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7164
b053b2ae 7165 if (irqchip_split(vcpu->kvm))
6308630b 7166 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7167 else {
fa59cc00 7168 if (vcpu->arch.apicv_active)
d62caabb 7169 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7170 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7171 }
e40ff1d6
LA		 7172
7173 if (is_guest_mode(vcpu))
7174 vcpu->arch.load_eoi_exitmap_pending = true;
7175 else
7176 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7177}
7178
7179static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7180{
7181 u64 eoi_exit_bitmap[4];
7182
7183 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7184 return;
7185
5c919412
AS		 7186 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7187 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7188 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7189}
7190
b1394e74
RK		 7191void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7192 unsigned long start, unsigned long end)
7193{
7194 unsigned long apic_address;
7195
7196 /*
7197 * The physical address of apic access page is stored in the VMCS.
7198 * Update it when it becomes invalid.
7199 */
7200 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7201 if (start <= apic_address && apic_address < end)
7202 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7203}
7204
4256f43f
TC		 7205void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7206{
c24ae0dc
TC		 7207 struct page *page = NULL;
7208
35754c98 7209 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7210 return;
7211
4256f43f
TC		 7212 if (!kvm_x86_ops->set_apic_access_page_addr)
7213 return;
7214
c24ae0dc 7215 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7216 if (is_error_page(page))
7217 return;
c24ae0dc
TC		 7218 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7219
7220 /*
7221 * Do not pin apic access page in memory, the MMU notifier
7222 * will call us again if it is migrated or swapped out.
7223 */
7224 put_page(page);
4256f43f
TC		 7225}
7226EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7227
9357d939 7228/*
362c698f 7229 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7230 * exiting to the userspace. Otherwise, the value will be returned to the
7231 * userspace.
7232 */
851ba692 7233static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7234{
7235 int r;
62a193ed
MG		 7236 bool req_int_win =
7237 dm_request_for_irq_injection(vcpu) &&
7238 kvm_cpu_accept_dm_intr(vcpu);
7239
730dca42 7240 bool req_immediate_exit = false;
b6c7a5dc 7241
2fa6e1e1 7242 if (kvm_request_pending(vcpu)) {
a8eeb04a 7243 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7244 kvm_mmu_unload(vcpu);
a8eeb04a 7245 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7246 __kvm_migrate_timers(vcpu);
d828199e
MT		 7247 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7248 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7249 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7250 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7251 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7252 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7253 if (unlikely(r))
7254 goto out;
7255 }
a8eeb04a 7256 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7257 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7258 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7259 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7260 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7261 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7262 r = 0;
7263 goto out;
7264 }
a8eeb04a 7265 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7266 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7267 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7268 r = 0;
7269 goto out;
7270 }
af585b92
GN		 7271 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7272 /* Page is swapped out. Do synthetic halt */
7273 vcpu->arch.apf.halted = true;
7274 r = 1;
7275 goto out;
7276 }
c9aaa895
GC		 7277 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7278 record_steal_time(vcpu);
64d60670
PB		 7279 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7280 process_smi(vcpu);
7460fb4a
AK		 7281 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7282 process_nmi(vcpu);
f5132b01 7283 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7284 kvm_pmu_handle_event(vcpu);
f5132b01 7285 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7286 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7287 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7288 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7289 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7290 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7291 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7292 vcpu->run->eoi.vector =
7293 vcpu->arch.pending_ioapic_eoi;
7294 r = 0;
7295 goto out;
7296 }
7297 }
3d81bc7e
YZ		 7298 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7299 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7300 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7301 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7302 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7303 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7304 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7305 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7306 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7307 r = 0;
7308 goto out;
7309 }
e516cebb
AS		 7310 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7311 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7312 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7313 r = 0;
7314 goto out;
7315 }
db397571
AS		 7316 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7317 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7318 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7319 r = 0;
7320 goto out;
7321 }
f3b138c5
AS		 7322
7323 /*
7324 * KVM_REQ_HV_STIMER has to be processed after
7325 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7326 * depend on the guest clock being up-to-date
7327 */
1f4b34f8
AS		 7328 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7329 kvm_hv_process_stimers(vcpu);
2f52d58c 7330 }
b93463aa 7331
b463a6f7 7332 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7333 ++vcpu->stat.req_event;
66450a21
JK		 7334 kvm_apic_accept_events(vcpu);
7335 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7336 r = 1;
7337 goto out;
7338 }
7339
b6b8a145
JK		 7340 if (inject_pending_event(vcpu, req_int_win) != 0)
7341 req_immediate_exit = true;
321c5658 7342 else {
cc3d967f 7343 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7344 *
cc3d967f
LP		 7345 * SMIs have three cases:
7346 * 1) They can be nested, and then there is nothing to
7347 * do here because RSM will cause a vmexit anyway.
7348 * 2) There is an ISA-specific reason why SMI cannot be
7349 * injected, and the moment when this changes can be
7350 * intercepted.
7351 * 3) Or the SMI can be pending because
7352 * inject_pending_event has completed the injection
7353 * of an IRQ or NMI from the previous vmexit, and
7354 * then we request an immediate exit to inject the
7355 * SMI.
c43203ca
PB		 7356 */
7357 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7358 if (!kvm_x86_ops->enable_smi_window(vcpu))
7359 req_immediate_exit = true;
321c5658
YS		 7360 if (vcpu->arch.nmi_pending)
7361 kvm_x86_ops->enable_nmi_window(vcpu);
7362 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7363 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7364 WARN_ON(vcpu->arch.exception.pending);
321c5658 7365 }
b463a6f7
AK		 7366
7367 if (kvm_lapic_enabled(vcpu)) {
7368 update_cr8_intercept(vcpu);
7369 kvm_lapic_sync_to_vapic(vcpu);
7370 }
7371 }
7372
d8368af8
AK		 7373 r = kvm_mmu_reload(vcpu);
7374 if (unlikely(r)) {
d905c069 7375 goto cancel_injection;
d8368af8
AK		 7376 }
7377
b6c7a5dc
HB		 7378 preempt_disable();
7379
7380 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7381
7382 /*
7383 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7384 * IPI are then delayed after guest entry, which ensures that they
7385 * result in virtual interrupt delivery.
7386 */
7387 local_irq_disable();
6b7e2d09
XG		 7388 vcpu->mode = IN_GUEST_MODE;
7389
01b71917
MT		 7390 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7391
0f127d12 7392 /*
b95234c8 7393 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7394 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7395 *
7396 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7397 * pairs with the memory barrier implicit in pi_test_and_set_on
7398 * (see vmx_deliver_posted_interrupt).
7399 *
7400 * 3) This also orders the write to mode from any reads to the page
7401 * tables done while the VCPU is running. Please see the comment
7402 * in kvm_flush_remote_tlbs.
6b7e2d09 7403 */
01b71917 7404 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7405
b95234c8
PB		 7406 /*
7407 * This handles the case where a posted interrupt was
7408 * notified with kvm_vcpu_kick.
7409 */
fa59cc00
LA		 7410 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7411 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7412
2fa6e1e1 7413 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7414 || need_resched() || signal_pending(current)) {
6b7e2d09 7415 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7416 smp_wmb();
6c142801
AK		 7417 local_irq_enable();
7418 preempt_enable();
01b71917 7419 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7420 r = 1;
d905c069 7421 goto cancel_injection;
6c142801
AK		 7422 }
7423
fc5b7f3b
DM		 7424 kvm_load_guest_xcr0(vcpu);
7425
c43203ca
PB		 7426 if (req_immediate_exit) {
7427 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7428 smp_send_reschedule(vcpu->cpu);
c43203ca 7429 }
d6185f20 7430
8b89fe1f 7431 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7432 if (lapic_timer_advance_ns)
7433 wait_lapic_expire(vcpu);
6edaa530 7434 guest_enter_irqoff();
b6c7a5dc 7435
42dbaa5a 7436 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7437 set_debugreg(0, 7);
7438 set_debugreg(vcpu->arch.eff_db[0], 0);
7439 set_debugreg(vcpu->arch.eff_db[1], 1);
7440 set_debugreg(vcpu->arch.eff_db[2], 2);
7441 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7442 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7443 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7444 }
b6c7a5dc 7445
851ba692 7446 kvm_x86_ops->run(vcpu);
b6c7a5dc 7447
c77fb5fe
PB		 7448 /*
7449 * Do this here before restoring debug registers on the host. And
7450 * since we do this before handling the vmexit, a DR access vmexit
7451 * can (a) read the correct value of the debug registers, (b) set
7452 * KVM_DEBUGREG_WONT_EXIT again.
7453 */
7454 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7455 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7456 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7457 kvm_update_dr0123(vcpu);
7458 kvm_update_dr6(vcpu);
7459 kvm_update_dr7(vcpu);
7460 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7461 }
7462
24f1e32c
FW		 7463 /*
7464 * If the guest has used debug registers, at least dr7
7465 * will be disabled while returning to the host.
7466 * If we don't have active breakpoints in the host, we don't
7467 * care about the messed up debug address registers. But if
7468 * we have some of them active, restore the old state.
7469 */
59d8eb53 7470 if (hw_breakpoint_active())
24f1e32c 7471 hw_breakpoint_restore();
42dbaa5a 7472
4ba76538 7473 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7474
6b7e2d09 7475 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7476 smp_wmb();
a547c6db 7477
fc5b7f3b
DM		 7478 kvm_put_guest_xcr0(vcpu);
7479
dd60d217 7480 kvm_before_interrupt(vcpu);
a547c6db 7481 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7482 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7483
7484 ++vcpu->stat.exits;
7485
f2485b3e 7486 guest_exit_irqoff();
b6c7a5dc 7487
f2485b3e 7488 local_irq_enable();
b6c7a5dc
HB		 7489 preempt_enable();
7490
f656ce01 7491 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7492
b6c7a5dc
HB		 7493 /*
7494 * Profile KVM exit RIPs:
7495 */
7496 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7497 unsigned long rip = kvm_rip_read(vcpu);
7498 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7499 }
7500
cc578287
ZA		 7501 if (unlikely(vcpu->arch.tsc_always_catchup))
7502 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7503
5cfb1d5a
MT		 7504 if (vcpu->arch.apic_attention)
7505 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7506
618232e2 7507 vcpu->arch.gpa_available = false;
851ba692 7508 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7509 return r;
7510
7511cancel_injection:
7512 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7513 if (unlikely(vcpu->arch.apic_attention))
7514 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7515out:
7516 return r;
7517}
b6c7a5dc 7518
362c698f
PB		 7519static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7520{
bf9f6ac8
FW		 7521 if (!kvm_arch_vcpu_runnable(vcpu) &&
7522 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7523 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7524 kvm_vcpu_block(vcpu);
7525 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7526
7527 if (kvm_x86_ops->post_block)
7528 kvm_x86_ops->post_block(vcpu);
7529
9c8fd1ba
PB		 7530 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7531 return 1;
7532 }
362c698f
PB		 7533
7534 kvm_apic_accept_events(vcpu);
7535 switch(vcpu->arch.mp_state) {
7536 case KVM_MP_STATE_HALTED:
7537 vcpu->arch.pv.pv_unhalted = false;
7538 vcpu->arch.mp_state =
7539 KVM_MP_STATE_RUNNABLE;
7540 case KVM_MP_STATE_RUNNABLE:
7541 vcpu->arch.apf.halted = false;
7542 break;
7543 case KVM_MP_STATE_INIT_RECEIVED:
7544 break;
7545 default:
7546 return -EINTR;
7547 break;
7548 }
7549 return 1;
7550}
09cec754 7551
5d9bc648
PB		 7552static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7553{
0ad3bed6
PB		 7554 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7555 kvm_x86_ops->check_nested_events(vcpu, false);
7556
5d9bc648
PB		 7557 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7558 !vcpu->arch.apf.halted);
7559}
7560
362c698f 7561static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7562{
7563 int r;
f656ce01 7564 struct kvm *kvm = vcpu->kvm;
d7690175 7565
f656ce01 7566 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7567
362c698f 7568 for (;;) {
58f800d5 7569 if (kvm_vcpu_running(vcpu)) {
851ba692 7570 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7571 } else {
362c698f 7572 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7573 }
7574
09cec754
GN		 7575 if (r <= 0)
7576 break;
7577
72875d8a 7578 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7579 if (kvm_cpu_has_pending_timer(vcpu))
7580 kvm_inject_pending_timer_irqs(vcpu);
7581
782d422b
MG		 7582 if (dm_request_for_irq_injection(vcpu) &&
7583 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7584 r = 0;
7585 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7586 ++vcpu->stat.request_irq_exits;
362c698f 7587 break;
09cec754 7588 }
af585b92
GN		 7589
7590 kvm_check_async_pf_completion(vcpu);
7591
09cec754
GN		 7592 if (signal_pending(current)) {
7593 r = -EINTR;
851ba692 7594 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7595 ++vcpu->stat.signal_exits;
362c698f 7596 break;
09cec754
GN		 7597 }
7598 if (need_resched()) {
f656ce01 7599 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7600 cond_resched();
f656ce01 7601 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7602 }
b6c7a5dc
HB		 7603 }
7604
f656ce01 7605 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7606
7607 return r;
7608}
7609
716d51ab
GN		 7610static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7611{
7612 int r;
7613 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7614 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7615 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7616 if (r != EMULATE_DONE)
7617 return 0;
7618 return 1;
7619}
7620
7621static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7622{
7623 BUG_ON(!vcpu->arch.pio.count);
7624
7625 return complete_emulated_io(vcpu);
7626}
7627
f78146b0
AK		 7628/*
7629 * Implements the following, as a state machine:
7630 *
7631 * read:
7632 * for each fragment
87da7e66
XG		 7633 * for each mmio piece in the fragment
7634 * write gpa, len
7635 * exit
7636 * copy data
f78146b0
AK		 7637 * execute insn
7638 *
7639 * write:
7640 * for each fragment
87da7e66
XG		 7641 * for each mmio piece in the fragment
7642 * write gpa, len
7643 * copy data
7644 * exit
f78146b0 7645 */
716d51ab 7646static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7647{
7648 struct kvm_run *run = vcpu->run;
f78146b0 7649 struct kvm_mmio_fragment *frag;
87da7e66 7650 unsigned len;
5287f194 7651
716d51ab 7652 BUG_ON(!vcpu->mmio_needed);
5287f194 7653
716d51ab 7654 /* Complete previous fragment */
87da7e66
XG		 7655 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7656 len = min(8u, frag->len);
716d51ab 7657 if (!vcpu->mmio_is_write)
87da7e66
XG		 7658 memcpy(frag->data, run->mmio.data, len);
7659
7660 if (frag->len <= 8) {
7661 /* Switch to the next fragment. */
7662 frag++;
7663 vcpu->mmio_cur_fragment++;
7664 } else {
7665 /* Go forward to the next mmio piece. */
7666 frag->data += len;
7667 frag->gpa += len;
7668 frag->len -= len;
7669 }
7670
a08d3b3b 7671 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7672 vcpu->mmio_needed = 0;
0912c977
PB		 7673
7674 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7675 if (vcpu->mmio_is_write)
716d51ab
GN		 7676 return 1;
7677 vcpu->mmio_read_completed = 1;
7678 return complete_emulated_io(vcpu);
7679 }
87da7e66 7680
716d51ab
GN		 7681 run->exit_reason = KVM_EXIT_MMIO;
7682 run->mmio.phys_addr = frag->gpa;
7683 if (vcpu->mmio_is_write)
87da7e66
XG		 7684 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7685 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7686 run->mmio.is_write = vcpu->mmio_is_write;
7687 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7688 return 0;
5287f194
AK		 7689}
7690
b6c7a5dc
HB		 7691int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7692{
7693 int r;
b6c7a5dc 7694
accb757d 7695 vcpu_load(vcpu);
20b7035c 7696 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7697 kvm_load_guest_fpu(vcpu);
7698
a4535290 7699 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7700 if (kvm_run->immediate_exit) {
7701 r = -EINTR;
7702 goto out;
7703 }
b6c7a5dc 7704 kvm_vcpu_block(vcpu);
66450a21 7705 kvm_apic_accept_events(vcpu);
72875d8a 7706 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7707 r = -EAGAIN;
a0595000
JS		 7708 if (signal_pending(current)) {
7709 r = -EINTR;
7710 vcpu->run->exit_reason = KVM_EXIT_INTR;
7711 ++vcpu->stat.signal_exits;
7712 }
ac9f6dc0 7713 goto out;
b6c7a5dc
HB		 7714 }
7715
01643c51
KH		 7716 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7717 r = -EINVAL;
7718 goto out;
7719 }
7720
7721 if (vcpu->run->kvm_dirty_regs) {
7722 r = sync_regs(vcpu);
7723 if (r != 0)
7724 goto out;
7725 }
7726
b6c7a5dc 7727 /* re-sync apic's tpr */
35754c98 7728 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7729 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7730 r = -EINVAL;
7731 goto out;
7732 }
7733 }
b6c7a5dc 7734
716d51ab
GN		 7735 if (unlikely(vcpu->arch.complete_userspace_io)) {
7736 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7737 vcpu->arch.complete_userspace_io = NULL;
7738 r = cui(vcpu);
7739 if (r <= 0)
5663d8f9 7740 goto out;
716d51ab
GN		 7741 } else
7742 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7743
460df4c1
PB		 7744 if (kvm_run->immediate_exit)
7745 r = -EINTR;
7746 else
7747 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7748
7749out:
5663d8f9 7750 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7751 if (vcpu->run->kvm_valid_regs)
7752 store_regs(vcpu);
f1d86e46 7753 post_kvm_run_save(vcpu);
20b7035c 7754 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7755
accb757d 7756 vcpu_put(vcpu);
b6c7a5dc
HB		 7757 return r;
7758}
7759
01643c51 7760static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7761{
7ae441ea
GN		 7762 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7763 /*
7764 * We are here if userspace calls get_regs() in the middle of
7765 * instruction emulation. Registers state needs to be copied
4a969980 7766 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7767 * that usually, but some bad designed PV devices (vmware
7768 * backdoor interface) need this to work
7769 */
dd856efa 7770 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7771 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7772 }
5fdbf976
MT		 7773 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7774 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7775 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7776 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7777 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7778 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7779 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7780 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7781#ifdef CONFIG_X86_64
5fdbf976
MT		 7782 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7783 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7784 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7785 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7786 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7787 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7788 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7789 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7790#endif
7791
5fdbf976 7792 regs->rip = kvm_rip_read(vcpu);
91586a3b 7793 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7794}
b6c7a5dc 7795
01643c51
KH		 7796int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7797{
7798 vcpu_load(vcpu);
7799 __get_regs(vcpu, regs);
1fc9b76b 7800 vcpu_put(vcpu);
b6c7a5dc
HB		 7801 return 0;
7802}
7803
01643c51 7804static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7805{
7ae441ea
GN		 7806 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7807 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7808
5fdbf976
MT		 7809 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7810 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7811 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7812 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7813 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7814 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7815 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7816 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7817#ifdef CONFIG_X86_64
5fdbf976
MT		 7818 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7819 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7820 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7821 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7822 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7823 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7824 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7825 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7826#endif
7827
5fdbf976 7828 kvm_rip_write(vcpu, regs->rip);
d73235d1 7829 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7830
b4f14abd
JK		 7831 vcpu->arch.exception.pending = false;
7832
3842d135 7833 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7834}
3842d135 7835
01643c51
KH		 7836int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7837{
7838 vcpu_load(vcpu);
7839 __set_regs(vcpu, regs);
875656fe 7840 vcpu_put(vcpu);
b6c7a5dc
HB		 7841 return 0;
7842}
7843
b6c7a5dc
HB		 7844void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7845{
7846 struct kvm_segment cs;
7847
3e6e0aab 7848 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7849 *db = cs.db;
7850 *l = cs.l;
7851}
7852EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7853
01643c51 7854static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7855{
89a27f4d 7856 struct desc_ptr dt;
b6c7a5dc 7857
3e6e0aab
GT		 7858 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7859 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7860 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7861 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7862 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7863 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7864
3e6e0aab
GT		 7865 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7866 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7867
7868 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7869 sregs->idt.limit = dt.size;
7870 sregs->idt.base = dt.address;
b6c7a5dc 7871 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7872 sregs->gdt.limit = dt.size;
7873 sregs->gdt.base = dt.address;
b6c7a5dc 7874
4d4ec087 7875 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7876 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7877 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7878 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7879 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7880 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7881 sregs->apic_base = kvm_get_apic_base(vcpu);
7882
923c61bb 7883 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7884
04140b41 7885 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7886 set_bit(vcpu->arch.interrupt.nr,
7887 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7888}
16d7a191 7889
01643c51
KH		 7890int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7891 struct kvm_sregs *sregs)
7892{
7893 vcpu_load(vcpu);
7894 __get_sregs(vcpu, sregs);
bcdec41c 7895 vcpu_put(vcpu);
b6c7a5dc
HB		 7896 return 0;
7897}
7898
62d9f0db
MT		 7899int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7900 struct kvm_mp_state *mp_state)
7901{
fd232561
CD		 7902 vcpu_load(vcpu);
7903
66450a21 7904 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7905 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7906 vcpu->arch.pv.pv_unhalted)
7907 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7908 else
7909 mp_state->mp_state = vcpu->arch.mp_state;
7910
fd232561 7911 vcpu_put(vcpu);
62d9f0db
MT		 7912 return 0;
7913}
7914
7915int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7916 struct kvm_mp_state *mp_state)
7917{
e83dff5e
CD		 7918 int ret = -EINVAL;
7919
7920 vcpu_load(vcpu);
7921
bce87cce 7922 if (!lapic_in_kernel(vcpu) &&
66450a21 7923 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7924 goto out;
66450a21 7925
28bf2888
DH		 7926 /* INITs are latched while in SMM */
7927 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7928 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7929 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7930 goto out;
28bf2888 7931
66450a21
JK		 7932 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7933 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7934 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7935 } else
7936 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7937 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7938
7939 ret = 0;
7940out:
7941 vcpu_put(vcpu);
7942 return ret;
62d9f0db
MT		 7943}
7944
7f3d35fd
KW		 7945int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7946 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7947{
9d74191a 7948 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7949 int ret;
e01c2426 7950
8ec4722d 7951 init_emulate_ctxt(vcpu);
c697518a 7952
7f3d35fd 7953 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7954 has_error_code, error_code);
c697518a 7955
c697518a 7956 if (ret)
19d04437 7957 return EMULATE_FAIL;
37817f29 7958
9d74191a
TY		 7959 kvm_rip_write(vcpu, ctxt->eip);
7960 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7961 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7962 return EMULATE_DONE;
37817f29
IE		 7963}
7964EXPORT_SYMBOL_GPL(kvm_task_switch);
7965
3140c156 7966static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 7967{
37b95951 7968 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7969 /*
7970 * When EFER.LME and CR0.PG are set, the processor is in
7971 * 64-bit mode (though maybe in a 32-bit code segment).
7972 * CR4.PAE and EFER.LMA must be set.
7973 */
37b95951 7974 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7975 || !(sregs->efer & EFER_LMA))
7976 return -EINVAL;
7977 } else {
7978 /*
7979 * Not in 64-bit mode: EFER.LMA is clear and the code
7980 * segment cannot be 64-bit.
7981 */
7982 if (sregs->efer & EFER_LMA || sregs->cs.l)
7983 return -EINVAL;
7984 }
7985
7986 return 0;
7987}
7988
01643c51 7989static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7990{
58cb628d 7991 struct msr_data apic_base_msr;
b6c7a5dc 7992 int mmu_reset_needed = 0;
63f42e02 7993 int pending_vec, max_bits, idx;
89a27f4d 7994 struct desc_ptr dt;
b4ef9d4e
CD		 7995 int ret = -EINVAL;
7996
d6321d49
RK		 7997 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7998 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7999 goto out;
6d1068b3 8000
f2981033 8001 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8002 goto out;
f2981033 8003
d3802286
JM		 8004 apic_base_msr.data = sregs->apic_base;
8005 apic_base_msr.host_initiated = true;
8006 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8007 goto out;
6d1068b3 8008
89a27f4d
GN		 8009 dt.size = sregs->idt.limit;
8010 dt.address = sregs->idt.base;
b6c7a5dc 8011 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8012 dt.size = sregs->gdt.limit;
8013 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8014 kvm_x86_ops->set_gdt(vcpu, &dt);
8015
ad312c7c 8016 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8017 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8018 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8019 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8020
2d3ad1f4 8021 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8022
f6801dff 8023 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8024 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8025
4d4ec087 8026 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8027 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8028 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8029
fc78f519 8030 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 8031 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 8032 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 8033 kvm_update_cpuid(vcpu);
63f42e02
XG		 8034
8035 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8036 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8037 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8038 mmu_reset_needed = 1;
8039 }
63f42e02 8040 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8041
8042 if (mmu_reset_needed)
8043 kvm_mmu_reset_context(vcpu);
8044
a50abc3b 8045 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8046 pending_vec = find_first_bit(
8047 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8048 if (pending_vec < max_bits) {
66fd3f7f 8049 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8050 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8051 }
8052
3e6e0aab
GT		 8053 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8054 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8055 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8056 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8057 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8058 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8059
3e6e0aab
GT		 8060 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8061 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8062
5f0269f5
ME		 8063 update_cr8_intercept(vcpu);
8064
9c3e4aab 8065 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8066 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8067 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8068 !is_protmode(vcpu))
9c3e4aab
MT		 8069 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8070
3842d135
AK		 8071 kvm_make_request(KVM_REQ_EVENT, vcpu);
8072
b4ef9d4e
CD		 8073 ret = 0;
8074out:
01643c51
KH		 8075 return ret;
8076}
8077
8078int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8079 struct kvm_sregs *sregs)
8080{
8081 int ret;
8082
8083 vcpu_load(vcpu);
8084 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8085 vcpu_put(vcpu);
8086 return ret;
b6c7a5dc
HB		 8087}
8088
d0bfb940
JK		 8089int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8090 struct kvm_guest_debug *dbg)
b6c7a5dc 8091{
355be0b9 8092 unsigned long rflags;
ae675ef0 8093 int i, r;
b6c7a5dc 8094
66b56562
CD		 8095 vcpu_load(vcpu);
8096
4f926bf2
JK		 8097 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8098 r = -EBUSY;
8099 if (vcpu->arch.exception.pending)
2122ff5e 8100 goto out;
4f926bf2
JK		 8101 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8102 kvm_queue_exception(vcpu, DB_VECTOR);
8103 else
8104 kvm_queue_exception(vcpu, BP_VECTOR);
8105 }
8106
91586a3b
JK		 8107 /*
8108 * Read rflags as long as potentially injected trace flags are still
8109 * filtered out.
8110 */
8111 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8112
8113 vcpu->guest_debug = dbg->control;
8114 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8115 vcpu->guest_debug = 0;
8116
8117 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8118 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8119 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8120 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8121 } else {
8122 for (i = 0; i < KVM_NR_DB_REGS; i++)
8123 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8124 }
c8639010 8125 kvm_update_dr7(vcpu);
ae675ef0 8126
f92653ee
JK		 8127 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8128 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8129 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8130
91586a3b
JK		 8131 /*
8132 * Trigger an rflags update that will inject or remove the trace
8133 * flags.
8134 */
8135 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8136
a96036b8 8137 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8138
4f926bf2 8139 r = 0;
d0bfb940 8140
2122ff5e 8141out:
66b56562 8142 vcpu_put(vcpu);
b6c7a5dc
HB		 8143 return r;
8144}
8145
8b006791
ZX		 8146/*
8147 * Translate a guest virtual address to a guest physical address.
8148 */
8149int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8150 struct kvm_translation *tr)
8151{
8152 unsigned long vaddr = tr->linear_address;
8153 gpa_t gpa;
f656ce01 8154 int idx;
8b006791 8155
1da5b61d
CD		 8156 vcpu_load(vcpu);
8157
f656ce01 8158 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8159 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8160 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8161 tr->physical_address = gpa;
8162 tr->valid = gpa != UNMAPPED_GVA;
8163 tr->writeable = 1;
8164 tr->usermode = 0;
8b006791 8165
1da5b61d 8166 vcpu_put(vcpu);
8b006791
ZX		 8167 return 0;
8168}
8169
d0752060
HB		 8170int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8171{
1393123e 8172 struct fxregs_state *fxsave;
d0752060 8173
1393123e 8174 vcpu_load(vcpu);
d0752060 8175
1393123e 8176 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8177 memcpy(fpu->fpr, fxsave->st_space, 128);
8178 fpu->fcw = fxsave->cwd;
8179 fpu->fsw = fxsave->swd;
8180 fpu->ftwx = fxsave->twd;
8181 fpu->last_opcode = fxsave->fop;
8182 fpu->last_ip = fxsave->rip;
8183 fpu->last_dp = fxsave->rdp;
8184 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8185
1393123e 8186 vcpu_put(vcpu);
d0752060
HB		 8187 return 0;
8188}
8189
8190int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8191{
6a96bc7f
CD		 8192 struct fxregs_state *fxsave;
8193
8194 vcpu_load(vcpu);
8195
8196 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8197
d0752060
HB		 8198 memcpy(fxsave->st_space, fpu->fpr, 128);
8199 fxsave->cwd = fpu->fcw;
8200 fxsave->swd = fpu->fsw;
8201 fxsave->twd = fpu->ftwx;
8202 fxsave->fop = fpu->last_opcode;
8203 fxsave->rip = fpu->last_ip;
8204 fxsave->rdp = fpu->last_dp;
8205 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8206
6a96bc7f 8207 vcpu_put(vcpu);
d0752060
HB		 8208 return 0;
8209}
8210
01643c51
KH		 8211static void store_regs(struct kvm_vcpu *vcpu)
8212{
8213 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8214
8215 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8216 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8217
8218 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8219 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8220
8221 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8222 kvm_vcpu_ioctl_x86_get_vcpu_events(
8223 vcpu, &vcpu->run->s.regs.events);
8224}
8225
8226static int sync_regs(struct kvm_vcpu *vcpu)
8227{
8228 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8229 return -EINVAL;
8230
8231 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8232 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8233 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8234 }
8235 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8236 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8237 return -EINVAL;
8238 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8239 }
8240 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8241 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8242 vcpu, &vcpu->run->s.regs.events))
8243 return -EINVAL;
8244 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8245 }
8246
8247 return 0;
8248}
8249
0ee6a517 8250static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8251{
bf935b0b 8252 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8253 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8254 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8255 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8256
2acf923e
DC		 8257 /*
8258 * Ensure guest xcr0 is valid for loading
8259 */
d91cab78 8260 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8261
ad312c7c 8262 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8263}
d0752060 8264
f775b13e 8265/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8266void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8267{
f775b13e
RR		 8268 preempt_disable();
8269 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8270 /* PKRU is separately restored in kvm_x86_ops->run. */
8271 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8272 ~XFEATURE_MASK_PKRU);
f775b13e 8273 preempt_enable();
0c04851c 8274 trace_kvm_fpu(1);
d0752060 8275}
d0752060 8276
f775b13e 8277/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8278void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8279{
f775b13e 8280 preempt_disable();
4f836347 8281 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8282 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8283 preempt_enable();
f096ed85 8284 ++vcpu->stat.fpu_reload;
0c04851c 8285 trace_kvm_fpu(0);
d0752060 8286}
e9b11c17
ZX		 8287
8288void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8289{
bd768e14
IY		 8290 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8291
12f9a48f 8292 kvmclock_reset(vcpu);
7f1ea208 8293
e9b11c17 8294 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8295 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8296}
8297
8298struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8299 unsigned int id)
8300{
c447e76b
LL		 8301 struct kvm_vcpu *vcpu;
8302
b0c39dc6 8303 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8304 printk_once(KERN_WARNING
8305 "kvm: SMP vm created on host with unstable TSC; "
8306 "guest TSC will not be reliable\n");
c447e76b
LL		 8307
8308 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8309
c447e76b 8310 return vcpu;
26e5215f 8311}
e9b11c17 8312
26e5215f
AK		 8313int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8314{
19efffa2 8315 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8316 vcpu_load(vcpu);
d28bc9dd 8317 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8318 kvm_mmu_setup(vcpu);
e9b11c17 8319 vcpu_put(vcpu);
ec7660cc 8320 return 0;
e9b11c17
ZX		 8321}
8322
31928aa5 8323void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8324{
8fe8ab46 8325 struct msr_data msr;
332967a3 8326 struct kvm *kvm = vcpu->kvm;
42897d86 8327
d3457c87
RK		 8328 kvm_hv_vcpu_postcreate(vcpu);
8329
ec7660cc 8330 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8331 return;
ec7660cc 8332 vcpu_load(vcpu);
8fe8ab46
WA		 8333 msr.data = 0x0;
8334 msr.index = MSR_IA32_TSC;
8335 msr.host_initiated = true;
8336 kvm_write_tsc(vcpu, &msr);
42897d86 8337 vcpu_put(vcpu);
ec7660cc 8338 mutex_unlock(&vcpu->mutex);
42897d86 8339
630994b3
MT		 8340 if (!kvmclock_periodic_sync)
8341 return;
8342
332967a3
AJ		 8343 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8344 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8345}
8346
d40ccc62 8347void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8348{
344d9588
GN		 8349 vcpu->arch.apf.msr_val = 0;
8350
ec7660cc 8351 vcpu_load(vcpu);
e9b11c17
ZX		 8352 kvm_mmu_unload(vcpu);
8353 vcpu_put(vcpu);
8354
8355 kvm_x86_ops->vcpu_free(vcpu);
8356}
8357
d28bc9dd 8358void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8359{
b7e31be3
RK		 8360 kvm_lapic_reset(vcpu, init_event);
8361
e69fab5d
PB		 8362 vcpu->arch.hflags = 0;
8363
c43203ca 8364 vcpu->arch.smi_pending = 0;
52797bf9 8365 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8366 atomic_set(&vcpu->arch.nmi_queued, 0);
8367 vcpu->arch.nmi_pending = 0;
448fa4a9 8368 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8369 kvm_clear_interrupt_queue(vcpu);
8370 kvm_clear_exception_queue(vcpu);
664f8e26 8371 vcpu->arch.exception.pending = false;
448fa4a9 8372
42dbaa5a 8373 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8374 kvm_update_dr0123(vcpu);
6f43ed01 8375 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8376 kvm_update_dr6(vcpu);
42dbaa5a 8377 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8378 kvm_update_dr7(vcpu);
42dbaa5a 8379
1119022c
NA		 8380 vcpu->arch.cr2 = 0;
8381
3842d135 8382 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8383 vcpu->arch.apf.msr_val = 0;
c9aaa895 8384 vcpu->arch.st.msr_val = 0;
3842d135 8385
12f9a48f
GC		 8386 kvmclock_reset(vcpu);
8387
af585b92
GN		 8388 kvm_clear_async_pf_completion_queue(vcpu);
8389 kvm_async_pf_hash_reset(vcpu);
8390 vcpu->arch.apf.halted = false;
3842d135 8391
a554d207
WL		 8392 if (kvm_mpx_supported()) {
8393 void *mpx_state_buffer;
8394
8395 /*
8396 * To avoid have the INIT path from kvm_apic_has_events() that be
8397 * called with loaded FPU and does not let userspace fix the state.
8398 */
f775b13e
RR		 8399 if (init_event)
8400 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8401 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8402 XFEATURE_MASK_BNDREGS);
8403 if (mpx_state_buffer)
8404 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8405 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8406 XFEATURE_MASK_BNDCSR);
8407 if (mpx_state_buffer)
8408 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8409 if (init_event)
8410 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8411 }
8412
64d60670 8413 if (!init_event) {
d28bc9dd 8414 kvm_pmu_reset(vcpu);
64d60670 8415 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8416
8417 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8418 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8419
8420 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8421 }
f5132b01 8422
66f7b72e
JS		 8423 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8424 vcpu->arch.regs_avail = ~0;
8425 vcpu->arch.regs_dirty = ~0;
8426
a554d207
WL		 8427 vcpu->arch.ia32_xss = 0;
8428
d28bc9dd 8429 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8430}
8431
2b4a273b 8432void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8433{
8434 struct kvm_segment cs;
8435
8436 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8437 cs.selector = vector << 8;
8438 cs.base = vector << 12;
8439 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8440 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8441}
8442
13a34e06 8443int kvm_arch_hardware_enable(void)
e9b11c17 8444{
ca84d1a2
ZA		 8445 struct kvm *kvm;
8446 struct kvm_vcpu *vcpu;
8447 int i;
0dd6a6ed
ZA		 8448 int ret;
8449 u64 local_tsc;
8450 u64 max_tsc = 0;
8451 bool stable, backwards_tsc = false;
18863bdd
AK		 8452
8453 kvm_shared_msr_cpu_online();
13a34e06 8454 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8455 if (ret != 0)
8456 return ret;
8457
4ea1636b 8458 local_tsc = rdtsc();
b0c39dc6 8459 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8460 list_for_each_entry(kvm, &vm_list, vm_list) {
8461 kvm_for_each_vcpu(i, vcpu, kvm) {
8462 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8463 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8464 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8465 backwards_tsc = true;
8466 if (vcpu->arch.last_host_tsc > max_tsc)
8467 max_tsc = vcpu->arch.last_host_tsc;
8468 }
8469 }
8470 }
8471
8472 /*
8473 * Sometimes, even reliable TSCs go backwards. This happens on
8474 * platforms that reset TSC during suspend or hibernate actions, but
8475 * maintain synchronization. We must compensate. Fortunately, we can
8476 * detect that condition here, which happens early in CPU bringup,
8477 * before any KVM threads can be running. Unfortunately, we can't
8478 * bring the TSCs fully up to date with real time, as we aren't yet far
8479 * enough into CPU bringup that we know how much real time has actually
108b249c 8480 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8481 * variables that haven't been updated yet.
8482 *
8483 * So we simply find the maximum observed TSC above, then record the
8484 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8485 * the adjustment will be applied. Note that we accumulate
8486 * adjustments, in case multiple suspend cycles happen before some VCPU
8487 * gets a chance to run again. In the event that no KVM threads get a
8488 * chance to run, we will miss the entire elapsed period, as we'll have
8489 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8490 * loose cycle time. This isn't too big a deal, since the loss will be
8491 * uniform across all VCPUs (not to mention the scenario is extremely
8492 * unlikely). It is possible that a second hibernate recovery happens
8493 * much faster than a first, causing the observed TSC here to be
8494 * smaller; this would require additional padding adjustment, which is
8495 * why we set last_host_tsc to the local tsc observed here.
8496 *
8497 * N.B. - this code below runs only on platforms with reliable TSC,
8498 * as that is the only way backwards_tsc is set above. Also note
8499 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8500 * have the same delta_cyc adjustment applied if backwards_tsc
8501 * is detected. Note further, this adjustment is only done once,
8502 * as we reset last_host_tsc on all VCPUs to stop this from being
8503 * called multiple times (one for each physical CPU bringup).
8504 *
4a969980 8505 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8506 * will be compensated by the logic in vcpu_load, which sets the TSC to
8507 * catchup mode. This will catchup all VCPUs to real time, but cannot
8508 * guarantee that they stay in perfect synchronization.
8509 */
8510 if (backwards_tsc) {
8511 u64 delta_cyc = max_tsc - local_tsc;
8512 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8513 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8514 kvm_for_each_vcpu(i, vcpu, kvm) {
8515 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8516 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8517 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8518 }
8519
8520 /*
8521 * We have to disable TSC offset matching.. if you were
8522 * booting a VM while issuing an S4 host suspend....
8523 * you may have some problem. Solving this issue is
8524 * left as an exercise to the reader.
8525 */
8526 kvm->arch.last_tsc_nsec = 0;
8527 kvm->arch.last_tsc_write = 0;
8528 }
8529
8530 }
8531 return 0;
e9b11c17
ZX		 8532}
8533
13a34e06 8534void kvm_arch_hardware_disable(void)
e9b11c17 8535{
13a34e06
RK		 8536 kvm_x86_ops->hardware_disable();
8537 drop_user_return_notifiers();
e9b11c17
ZX		 8538}
8539
8540int kvm_arch_hardware_setup(void)
8541{
9e9c3fe4
NA		 8542 int r;
8543
8544 r = kvm_x86_ops->hardware_setup();
8545 if (r != 0)
8546 return r;
8547
35181e86
HZ		 8548 if (kvm_has_tsc_control) {
8549 /*
8550 * Make sure the user can only configure tsc_khz values that
8551 * fit into a signed integer.
8552 * A min value is not calculated needed because it will always
8553 * be 1 on all machines.
8554 */
8555 u64 max = min(0x7fffffffULL,
8556 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8557 kvm_max_guest_tsc_khz = max;
8558
ad721883 8559 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8560 }
ad721883 8561
9e9c3fe4
NA		 8562 kvm_init_msr_list();
8563 return 0;
e9b11c17
ZX		 8564}
8565
8566void kvm_arch_hardware_unsetup(void)
8567{
8568 kvm_x86_ops->hardware_unsetup();
8569}
8570
8571void kvm_arch_check_processor_compat(void *rtn)
8572{
8573 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8574}
8575
8576bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8577{
8578 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8579}
8580EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8581
8582bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8583{
8584 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8585}
8586
54e9818f 8587struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8588EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8589
e9b11c17
ZX		 8590int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8591{
8592 struct page *page;
e9b11c17
ZX		 8593 int r;
8594
b2a05fef 8595 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8596 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8597 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8598 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8599 else
a4535290 8600 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8601
8602 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8603 if (!page) {
8604 r = -ENOMEM;
8605 goto fail;
8606 }
ad312c7c 8607 vcpu->arch.pio_data = page_address(page);
e9b11c17 8608
cc578287 8609 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8610
e9b11c17
ZX		 8611 r = kvm_mmu_create(vcpu);
8612 if (r < 0)
8613 goto fail_free_pio_data;
8614
26de7988 8615 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8616 r = kvm_create_lapic(vcpu);
8617 if (r < 0)
8618 goto fail_mmu_destroy;
54e9818f
GN		 8619 } else
8620 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8621
890ca9ae
HY		 8622 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8623 GFP_KERNEL);
8624 if (!vcpu->arch.mce_banks) {
8625 r = -ENOMEM;
443c39bc 8626 goto fail_free_lapic;
890ca9ae
HY		 8627 }
8628 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8629
f1797359
WY		 8630 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8631 r = -ENOMEM;
f5f48ee1 8632 goto fail_free_mce_banks;
f1797359 8633 }
f5f48ee1 8634
0ee6a517 8635 fx_init(vcpu);
66f7b72e 8636
4344ee98 8637 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8638
5a4f55cd
EK		 8639 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8640
74545705
RK		 8641 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8642
af585b92 8643 kvm_async_pf_hash_reset(vcpu);
f5132b01 8644 kvm_pmu_init(vcpu);
af585b92 8645
1c1a9ce9 8646 vcpu->arch.pending_external_vector = -1;
de63ad4c 8647 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8648
5c919412
AS		 8649 kvm_hv_vcpu_init(vcpu);
8650
e9b11c17 8651 return 0;
0ee6a517 8652
f5f48ee1
SY		 8653fail_free_mce_banks:
8654 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8655fail_free_lapic:
8656 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8657fail_mmu_destroy:
8658 kvm_mmu_destroy(vcpu);
8659fail_free_pio_data:
ad312c7c 8660 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8661fail:
8662 return r;
8663}
8664
8665void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8666{
f656ce01
MT		 8667 int idx;
8668
1f4b34f8 8669 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8670 kvm_pmu_destroy(vcpu);
36cb93fd 8671 kfree(vcpu->arch.mce_banks);
e9b11c17 8672 kvm_free_lapic(vcpu);
f656ce01 8673 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8674 kvm_mmu_destroy(vcpu);
f656ce01 8675 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8676 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8677 if (!lapic_in_kernel(vcpu))
54e9818f 8678 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8679}
d19a9cd2 8680
e790d9ef
RK		 8681void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8682{
ae97a3b8 8683 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8684}
8685
e08b9637 8686int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8687{
e08b9637
CO		 8688 if (type)
8689 return -EINVAL;
8690
6ef768fa 8691 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8692 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8693 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8694 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8695 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8696
5550af4d
SY		 8697 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8698 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8699 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8700 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8701 &kvm->arch.irq_sources_bitmap);
5550af4d 8702
038f8c11 8703 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8704 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8705 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8706
108b249c 8707 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8708 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8709
7e44e449 8710 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8711 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8712
cbc0236a 8713 kvm_hv_init_vm(kvm);
0eb05bf2 8714 kvm_page_track_init(kvm);
13d268ca 8715 kvm_mmu_init_vm(kvm);
0eb05bf2 8716
03543133
SS		 8717 if (kvm_x86_ops->vm_init)
8718 return kvm_x86_ops->vm_init(kvm);
8719
d89f5eff 8720 return 0;
d19a9cd2
ZX		 8721}
8722
8723static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8724{
ec7660cc 8725 vcpu_load(vcpu);
d19a9cd2
ZX		 8726 kvm_mmu_unload(vcpu);
8727 vcpu_put(vcpu);
8728}
8729
8730static void kvm_free_vcpus(struct kvm *kvm)
8731{
8732 unsigned int i;
988a2cae 8733 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8734
8735 /*
8736 * Unpin any mmu pages first.
8737 */
af585b92
GN		 8738 kvm_for_each_vcpu(i, vcpu, kvm) {
8739 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8740 kvm_unload_vcpu_mmu(vcpu);
af585b92 8741 }
988a2cae
GN		 8742 kvm_for_each_vcpu(i, vcpu, kvm)
8743 kvm_arch_vcpu_free(vcpu);
8744
8745 mutex_lock(&kvm->lock);
8746 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8747 kvm->vcpus[i] = NULL;
d19a9cd2 8748
988a2cae
GN		 8749 atomic_set(&kvm->online_vcpus, 0);
8750 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8751}
8752
ad8ba2cd
SY		 8753void kvm_arch_sync_events(struct kvm *kvm)
8754{
332967a3 8755 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8756 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8757 kvm_free_pit(kvm);
ad8ba2cd
SY		 8758}
8759
1d8007bd 8760int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8761{
8762 int i, r;
25188b99 8763 unsigned long hva;
f0d648bd
PB		 8764 struct kvm_memslots *slots = kvm_memslots(kvm);
8765 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8766
8767 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8768 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8769 return -EINVAL;
9da0e4d5 8770
f0d648bd
PB		 8771 slot = id_to_memslot(slots, id);
8772 if (size) {
b21629da 8773 if (slot->npages)
f0d648bd
PB		 8774 return -EEXIST;
8775
8776 /*
8777 * MAP_SHARED to prevent internal slot pages from being moved
8778 * by fork()/COW.
8779 */
8780 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8781 MAP_SHARED | MAP_ANONYMOUS, 0);
8782 if (IS_ERR((void *)hva))
8783 return PTR_ERR((void *)hva);
8784 } else {
8785 if (!slot->npages)
8786 return 0;
8787
8788 hva = 0;
8789 }
8790
8791 old = *slot;
9da0e4d5 8792 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8793 struct kvm_userspace_memory_region m;
9da0e4d5 8794
1d8007bd
PB		 8795 m.slot = id | (i << 16);
8796 m.flags = 0;
8797 m.guest_phys_addr = gpa;
f0d648bd 8798 m.userspace_addr = hva;
1d8007bd 8799 m.memory_size = size;
9da0e4d5
PB		 8800 r = __kvm_set_memory_region(kvm, &m);
8801 if (r < 0)
8802 return r;
8803 }
8804
103c763c
EB		 8805 if (!size)
8806 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8807
9da0e4d5
PB		 8808 return 0;
8809}
8810EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8811
1d8007bd 8812int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8813{
8814 int r;
8815
8816 mutex_lock(&kvm->slots_lock);
1d8007bd 8817 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8818 mutex_unlock(&kvm->slots_lock);
8819
8820 return r;
8821}
8822EXPORT_SYMBOL_GPL(x86_set_memory_region);
8823
d19a9cd2
ZX		 8824void kvm_arch_destroy_vm(struct kvm *kvm)
8825{
27469d29
AH		 8826 if (current->mm == kvm->mm) {
8827 /*
8828 * Free memory regions allocated on behalf of userspace,
8829 * unless the the memory map has changed due to process exit
8830 * or fd copying.
8831 */
1d8007bd
PB		 8832 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8833 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8834 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8835 }
03543133
SS		 8836 if (kvm_x86_ops->vm_destroy)
8837 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8838 kvm_pic_destroy(kvm);
8839 kvm_ioapic_destroy(kvm);
d19a9cd2 8840 kvm_free_vcpus(kvm);
af1bae54 8841 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8842 kvm_mmu_uninit_vm(kvm);
2beb6dad 8843 kvm_page_track_cleanup(kvm);
cbc0236a 8844 kvm_hv_destroy_vm(kvm);
d19a9cd2 8845}
0de10343 8846
5587027c 8847void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8848 struct kvm_memory_slot *dont)
8849{
8850 int i;
8851
d89cc617
TY		 8852 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8853 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8854 kvfree(free->arch.rmap[i]);
d89cc617 8855 free->arch.rmap[i] = NULL;
77d11309 8856 }
d89cc617
TY		 8857 if (i == 0)
8858 continue;
8859
8860 if (!dont || free->arch.lpage_info[i - 1] !=
8861 dont->arch.lpage_info[i - 1]) {
548ef284 8862 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8863 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8864 }
8865 }
21ebbeda
XG		 8866
8867 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8868}
8869
5587027c
AK		 8870int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8871 unsigned long npages)
db3fe4eb
TY		 8872{
8873 int i;
8874
d89cc617 8875 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8876 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8877 unsigned long ugfn;
8878 int lpages;
d89cc617 8879 int level = i + 1;
db3fe4eb
TY		 8880
8881 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8882 slot->base_gfn, level) + 1;
8883
d89cc617 8884 slot->arch.rmap[i] =
a7c3e901 8885 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8886 if (!slot->arch.rmap[i])
77d11309 8887 goto out_free;
d89cc617
TY		 8888 if (i == 0)
8889 continue;
77d11309 8890
a7c3e901 8891 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8892 if (!linfo)
db3fe4eb
TY		 8893 goto out_free;
8894
92f94f1e
XG		 8895 slot->arch.lpage_info[i - 1] = linfo;
8896
db3fe4eb 8897 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8898 linfo[0].disallow_lpage = 1;
db3fe4eb 8899 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8900 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8901 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8902 /*
8903 * If the gfn and userspace address are not aligned wrt each
8904 * other, or if explicitly asked to, disable large page
8905 * support for this slot
8906 */
8907 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8908 !kvm_largepages_enabled()) {
8909 unsigned long j;
8910
8911 for (j = 0; j < lpages; ++j)
92f94f1e 8912 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8913 }
8914 }
8915
21ebbeda
XG		 8916 if (kvm_page_track_create_memslot(slot, npages))
8917 goto out_free;
8918
db3fe4eb
TY		 8919 return 0;
8920
8921out_free:
d89cc617 8922 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8923 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8924 slot->arch.rmap[i] = NULL;
8925 if (i == 0)
8926 continue;
8927
548ef284 8928 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8929 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8930 }
8931 return -ENOMEM;
8932}
8933
15f46015 8934void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8935{
e6dff7d1
TY		 8936 /*
8937 * memslots->generation has been incremented.
8938 * mmio generation may have reached its maximum value.
8939 */
54bf36aa 8940 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8941}
8942
f7784b8e
MT		 8943int kvm_arch_prepare_memory_region(struct kvm *kvm,
8944 struct kvm_memory_slot *memslot,
09170a49 8945 const struct kvm_userspace_memory_region *mem,
7b6195a9 8946 enum kvm_mr_change change)
0de10343 8947{
f7784b8e
MT		 8948 return 0;
8949}
8950
88178fd4
KH		 8951static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8952 struct kvm_memory_slot *new)
8953{
8954 /* Still write protect RO slot */
8955 if (new->flags & KVM_MEM_READONLY) {
8956 kvm_mmu_slot_remove_write_access(kvm, new);
8957 return;
8958 }
8959
8960 /*
8961 * Call kvm_x86_ops dirty logging hooks when they are valid.
8962 *
8963 * kvm_x86_ops->slot_disable_log_dirty is called when:
8964 *
8965 * - KVM_MR_CREATE with dirty logging is disabled
8966 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8967 *
8968 * The reason is, in case of PML, we need to set D-bit for any slots
8969 * with dirty logging disabled in order to eliminate unnecessary GPA
8970 * logging in PML buffer (and potential PML buffer full VMEXT). This
8971 * guarantees leaving PML enabled during guest's lifetime won't have
8972 * any additonal overhead from PML when guest is running with dirty
8973 * logging disabled for memory slots.
8974 *
8975 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8976 * to dirty logging mode.
8977 *
8978 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8979 *
8980 * In case of write protect:
8981 *
8982 * Write protect all pages for dirty logging.
8983 *
8984 * All the sptes including the large sptes which point to this
8985 * slot are set to readonly. We can not create any new large
8986 * spte on this slot until the end of the logging.
8987 *
8988 * See the comments in fast_page_fault().
8989 */
8990 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8991 if (kvm_x86_ops->slot_enable_log_dirty)
8992 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8993 else
8994 kvm_mmu_slot_remove_write_access(kvm, new);
8995 } else {
8996 if (kvm_x86_ops->slot_disable_log_dirty)
8997 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8998 }
8999}
9000
f7784b8e 9001void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9002 const struct kvm_userspace_memory_region *mem,
8482644a 9003 const struct kvm_memory_slot *old,
f36f3f28 9004 const struct kvm_memory_slot *new,
8482644a 9005 enum kvm_mr_change change)
f7784b8e 9006{
8482644a 9007 int nr_mmu_pages = 0;
f7784b8e 9008
48c0e4e9
XG		 9009 if (!kvm->arch.n_requested_mmu_pages)
9010 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9011
48c0e4e9 9012 if (nr_mmu_pages)
0de10343 9013 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9014
3ea3b7fa
WL		 9015 /*
9016 * Dirty logging tracks sptes in 4k granularity, meaning that large
9017 * sptes have to be split. If live migration is successful, the guest
9018 * in the source machine will be destroyed and large sptes will be
9019 * created in the destination. However, if the guest continues to run
9020 * in the source machine (for example if live migration fails), small
9021 * sptes will remain around and cause bad performance.
9022 *
9023 * Scan sptes if dirty logging has been stopped, dropping those
9024 * which can be collapsed into a single large-page spte. Later
9025 * page faults will create the large-page sptes.
9026 */
9027 if ((change != KVM_MR_DELETE) &&
9028 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9029 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9030 kvm_mmu_zap_collapsible_sptes(kvm, new);
9031
c972f3b1 9032 /*
88178fd4 9033 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9034 *
88178fd4
KH		 9035 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9036 * been zapped so no dirty logging staff is needed for old slot. For
9037 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9038 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9039 *
9040 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9041 */
88178fd4 9042 if (change != KVM_MR_DELETE)
f36f3f28 9043 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9044}
1d737c8a 9045
2df72e9b 9046void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9047{
6ca18b69 9048 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9049}
9050
2df72e9b
MT		 9051void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9052 struct kvm_memory_slot *slot)
9053{
ae7cd873 9054 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9055}
9056
5d9bc648
PB		 9057static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9058{
9059 if (!list_empty_careful(&vcpu->async_pf.done))
9060 return true;
9061
9062 if (kvm_apic_has_events(vcpu))
9063 return true;
9064
9065 if (vcpu->arch.pv.pv_unhalted)
9066 return true;
9067
a5f01f8e
WL		 9068 if (vcpu->arch.exception.pending)
9069 return true;
9070
47a66eed
Z		 9071 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9072 (vcpu->arch.nmi_pending &&
9073 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9074 return true;
9075
47a66eed
Z		 9076 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9077 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9078 return true;
9079
5d9bc648
PB		 9080 if (kvm_arch_interrupt_allowed(vcpu) &&
9081 kvm_cpu_has_interrupt(vcpu))
9082 return true;
9083
1f4b34f8
AS		 9084 if (kvm_hv_has_stimer_pending(vcpu))
9085 return true;
9086
5d9bc648
PB		 9087 return false;
9088}
9089
1d737c8a
ZX		 9090int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9091{
5d9bc648 9092 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9093}
5736199a 9094
199b5763
LM		 9095bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9096{
de63ad4c 9097 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9098}
9099
b6d33834 9100int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9101{
b6d33834 9102 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9103}
78646121
GN		 9104
9105int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9106{
9107 return kvm_x86_ops->interrupt_allowed(vcpu);
9108}
229456fc 9109
82b32774 9110unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9111{
82b32774
NA		 9112 if (is_64_bit_mode(vcpu))
9113 return kvm_rip_read(vcpu);
9114 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9115 kvm_rip_read(vcpu));
9116}
9117EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9118
82b32774
NA		 9119bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9120{
9121 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9122}
9123EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9124
94fe45da
JK		 9125unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9126{
9127 unsigned long rflags;
9128
9129 rflags = kvm_x86_ops->get_rflags(vcpu);
9130 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9131 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9132 return rflags;
9133}
9134EXPORT_SYMBOL_GPL(kvm_get_rflags);
9135
6addfc42 9136static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9137{
9138 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9139 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9140 rflags |= X86_EFLAGS_TF;
94fe45da 9141 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9142}
9143
9144void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9145{
9146 __kvm_set_rflags(vcpu, rflags);
3842d135 9147 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9148}
9149EXPORT_SYMBOL_GPL(kvm_set_rflags);
9150
56028d08
GN		 9151void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9152{
9153 int r;
9154
fb67e14f 9155 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9156 work->wakeup_all)
56028d08
GN		 9157 return;
9158
9159 r = kvm_mmu_reload(vcpu);
9160 if (unlikely(r))
9161 return;
9162
fb67e14f
XG		 9163 if (!vcpu->arch.mmu.direct_map &&
9164 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9165 return;
9166
56028d08
GN		 9167 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9168}
9169
af585b92
GN		 9170static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9171{
9172 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9173}
9174
9175static inline u32 kvm_async_pf_next_probe(u32 key)
9176{
9177 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9178}
9179
9180static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9181{
9182 u32 key = kvm_async_pf_hash_fn(gfn);
9183
9184 while (vcpu->arch.apf.gfns[key] != ~0)
9185 key = kvm_async_pf_next_probe(key);
9186
9187 vcpu->arch.apf.gfns[key] = gfn;
9188}
9189
9190static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9191{
9192 int i;
9193 u32 key = kvm_async_pf_hash_fn(gfn);
9194
9195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9196 (vcpu->arch.apf.gfns[key] != gfn &&
9197 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9198 key = kvm_async_pf_next_probe(key);
9199
9200 return key;
9201}
9202
9203bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9204{
9205 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9206}
9207
9208static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9209{
9210 u32 i, j, k;
9211
9212 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9213 while (true) {
9214 vcpu->arch.apf.gfns[i] = ~0;
9215 do {
9216 j = kvm_async_pf_next_probe(j);
9217 if (vcpu->arch.apf.gfns[j] == ~0)
9218 return;
9219 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9220 /*
9221 * k lies cyclically in ]i,j]
9222 * | i.k.j |
9223 * |....j i.k.| or |.k..j i...|
9224 */
9225 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9226 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9227 i = j;
9228 }
9229}
9230
7c90705b
GN		 9231static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9232{
4e335d9e
PB		 9233
9234 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9235 sizeof(val));
7c90705b
GN		 9236}
9237
9a6e7c39
WL		 9238static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9239{
9240
9241 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9242 sizeof(u32));
9243}
9244
af585b92
GN		 9245void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9246 struct kvm_async_pf *work)
9247{
6389ee94
AK		 9248 struct x86_exception fault;
9249
7c90705b 9250 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9251 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9252
9253 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9254 (vcpu->arch.apf.send_user_only &&
9255 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9256 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9257 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9258 fault.vector = PF_VECTOR;
9259 fault.error_code_valid = true;
9260 fault.error_code = 0;
9261 fault.nested_page_fault = false;
9262 fault.address = work->arch.token;
adfe20fb 9263 fault.async_page_fault = true;
6389ee94 9264 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9265 }
af585b92
GN		 9266}
9267
9268void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9269 struct kvm_async_pf *work)
9270{
6389ee94 9271 struct x86_exception fault;
9a6e7c39 9272 u32 val;
6389ee94 9273
f2e10669 9274 if (work->wakeup_all)
7c90705b
GN		 9275 work->arch.token = ~0; /* broadcast wakeup */
9276 else
9277 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9278 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9279
9a6e7c39
WL		 9280 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9281 !apf_get_user(vcpu, &val)) {
9282 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9283 vcpu->arch.exception.pending &&
9284 vcpu->arch.exception.nr == PF_VECTOR &&
9285 !apf_put_user(vcpu, 0)) {
9286 vcpu->arch.exception.injected = false;
9287 vcpu->arch.exception.pending = false;
9288 vcpu->arch.exception.nr = 0;
9289 vcpu->arch.exception.has_error_code = false;
9290 vcpu->arch.exception.error_code = 0;
9291 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9292 fault.vector = PF_VECTOR;
9293 fault.error_code_valid = true;
9294 fault.error_code = 0;
9295 fault.nested_page_fault = false;
9296 fault.address = work->arch.token;
9297 fault.async_page_fault = true;
9298 kvm_inject_page_fault(vcpu, &fault);
9299 }
7c90705b 9300 }
e6d53e3b 9301 vcpu->arch.apf.halted = false;
a4fa1635 9302 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9303}
9304
9305bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9306{
9307 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9308 return true;
9309 else
9bc1f09f 9310 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9311}
9312
5544eb9b
PB		 9313void kvm_arch_start_assignment(struct kvm *kvm)
9314{
9315 atomic_inc(&kvm->arch.assigned_device_count);
9316}
9317EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9318
9319void kvm_arch_end_assignment(struct kvm *kvm)
9320{
9321 atomic_dec(&kvm->arch.assigned_device_count);
9322}
9323EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9324
9325bool kvm_arch_has_assigned_device(struct kvm *kvm)
9326{
9327 return atomic_read(&kvm->arch.assigned_device_count);
9328}
9329EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9330
e0f0bbc5
AW		 9331void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9332{
9333 atomic_inc(&kvm->arch.noncoherent_dma_count);
9334}
9335EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9336
9337void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9338{
9339 atomic_dec(&kvm->arch.noncoherent_dma_count);
9340}
9341EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9342
9343bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9344{
9345 return atomic_read(&kvm->arch.noncoherent_dma_count);
9346}
9347EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9348
14717e20
AW		 9349bool kvm_arch_has_irq_bypass(void)
9350{
9351 return kvm_x86_ops->update_pi_irte != NULL;
9352}
9353
87276880
FW		 9354int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9355 struct irq_bypass_producer *prod)
9356{
9357 struct kvm_kernel_irqfd *irqfd =
9358 container_of(cons, struct kvm_kernel_irqfd, consumer);
9359
14717e20 9360 irqfd->producer = prod;
87276880 9361
14717e20
AW		 9362 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9363 prod->irq, irqfd->gsi, 1);
87276880
FW		 9364}
9365
9366void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9367 struct irq_bypass_producer *prod)
9368{
9369 int ret;
9370 struct kvm_kernel_irqfd *irqfd =
9371 container_of(cons, struct kvm_kernel_irqfd, consumer);
9372
87276880
FW		 9373 WARN_ON(irqfd->producer != prod);
9374 irqfd->producer = NULL;
9375
9376 /*
9377 * When producer of consumer is unregistered, we change back to
9378 * remapped mode, so we can re-use the current implementation
bb3541f1 9379 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9380 * int this case doesn't want to receive the interrupts.
9381 */
9382 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9383 if (ret)
9384 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9385 " fails: %d\n", irqfd->consumer.token, ret);
9386}
9387
9388int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9389 uint32_t guest_irq, bool set)
9390{
9391 if (!kvm_x86_ops->update_pi_irte)
9392 return -EINVAL;
9393
9394 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9395}
9396
52004014
FW		 9397bool kvm_vector_hashing_enabled(void)
9398{
9399 return vector_hashing;
9400}
9401EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9402
229456fc 9403EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9404EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9405EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9406EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9407EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9408EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9409EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9410EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9411EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9412EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9413EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9414EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9415EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9416EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)