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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 105
893590c7 106struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 107EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 108
893590c7 109static bool __read_mostly ignore_msrs = 0;
476bc001 110module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 111
fab0aa3b
EM		 112static bool __read_mostly report_ignored_msrs = true;
113module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
114
9ed96e87
MT		 115unsigned int min_timer_period_us = 500;
116module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
117
630994b3
MT		 118static bool __read_mostly kvmclock_periodic_sync = true;
119module_param(kvmclock_periodic_sync, bool, S_IRUGO);
120
893590c7 121bool __read_mostly kvm_has_tsc_control;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 123u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 125u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
126EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
127u64 __read_mostly kvm_max_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 129u64 __read_mostly kvm_default_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 131
cc578287 132/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 133static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 134module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
135
d0659d94 136/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 137unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 138module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
139
52004014
FW		 140static bool __read_mostly vector_hashing = true;
141module_param(vector_hashing, bool, S_IRUGO);
142
18863bdd
AK		 143#define KVM_NR_SHARED_MSRS 16
144
145struct kvm_shared_msrs_global {
146 int nr;
2bf78fa7 147 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 148};
149
150struct kvm_shared_msrs {
151 struct user_return_notifier urn;
152 bool registered;
2bf78fa7
SY		 153 struct kvm_shared_msr_values {
154 u64 host;
155 u64 curr;
156 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 157};
158
159static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 160static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 161
417bc304 162struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 163 { "pf_fixed", VCPU_STAT(pf_fixed) },
164 { "pf_guest", VCPU_STAT(pf_guest) },
165 { "tlb_flush", VCPU_STAT(tlb_flush) },
166 { "invlpg", VCPU_STAT(invlpg) },
167 { "exits", VCPU_STAT(exits) },
168 { "io_exits", VCPU_STAT(io_exits) },
169 { "mmio_exits", VCPU_STAT(mmio_exits) },
170 { "signal_exits", VCPU_STAT(signal_exits) },
171 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 172 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 173 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 174 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 175 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 176 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 177 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 178 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 179 { "request_irq", VCPU_STAT(request_irq_exits) },
180 { "irq_exits", VCPU_STAT(irq_exits) },
181 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 182 { "fpu_reload", VCPU_STAT(fpu_reload) },
183 { "insn_emulation", VCPU_STAT(insn_emulation) },
184 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 185 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 186 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 187 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 195 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 197 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 200 { NULL }
201};
202
2acf923e
DC		 203u64 __read_mostly host_xcr0;
204
b6785def 205static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 206
af585b92
GN		 207static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208{
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212}
213
18863bdd
AK		 214static void kvm_on_user_return(struct user_return_notifier *urn)
215{
216 unsigned slot;
18863bdd
AK		 217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 219 struct kvm_shared_msr_values *values;
1650b4eb
IA		 220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
18863bdd 232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
18863bdd
AK		 237 }
238 }
18863bdd
AK		 239}
240
2bf78fa7 241static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 242{
18863bdd 243 u64 value;
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 246
2bf78fa7
SY		 247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256}
257
258void kvm_define_shared_msr(unsigned slot, u32 msr)
259{
0123be42 260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 261 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 264}
265EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267static void kvm_shared_msr_cpu_online(void)
268{
269 unsigned i;
18863bdd
AK		 270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 272 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 273}
274
8b3c3104 275int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 276{
013f6a5d
MT		 277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 279 int err;
18863bdd 280
2bf78fa7 281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 282 return 0;
2bf78fa7 283 smsr->values[slot].curr = value;
8b3c3104
AH		 284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
18863bdd
AK		 288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
8b3c3104 293 return 0;
18863bdd
AK		 294}
295EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
13a34e06 297static void drop_user_return_notifiers(void)
3548bab5 298{
013f6a5d
MT		 299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304}
305
6866b83e
CO		 306u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307{
8a5a87d9 308 return vcpu->arch.apic_base;
6866b83e
CO		 309}
310EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
58cb628d
JK		 312int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313{
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 320
d3802286
JM		 321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
58cb628d 323 if (!msr_info->host_initiated &&
d3802286 324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
6866b83e
CO		 332}
333EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
2605fc21 335asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 336{
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339}
340EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
3fd28fce
ED		 342#define EXCPT_BENIGN 0
343#define EXCPT_CONTRIBUTORY 1
344#define EXCPT_PF 2
345
346static int exception_class(int vector)
347{
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361}
362
d6e8c854
NA		 363#define EXCPT_FAULT 0
364#define EXCPT_TRAP 1
365#define EXCPT_ABORT 2
366#define EXCPT_INTERRUPT 3
367
368static int exception_type(int vector)
369{
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386}
387
3fd28fce 388static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
3fd28fce
ED		 391{
392 u32 prev_nr;
393 int class1, class2;
394
3842d135
AK		 395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
664f8e26 397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 398 queue:
3ffb2468
NA		 399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
664f8e26
WL		 401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
3fd28fce
ED		 416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
a8eeb04a 426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
3fd28fce 438 vcpu->arch.exception.pending = true;
664f8e26 439 vcpu->arch.exception.injected = false;
3fd28fce
ED		 440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448}
449
298101da
AK		 450void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451{
ce7ddec4 452 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 453}
454EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
ce7ddec4
JR		 456void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457{
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459}
460EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
6affcbed 462int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 463{
db8fcefa
AP		 464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
6affcbed
KH		 467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
db8fcefa
AP		 470}
471EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 472
6389ee94 473void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 474{
475 ++vcpu->stat.pf_guest;
adfe20fb
WL		 476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
6389ee94 482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 483}
27d6c865 484EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 485
ef54bcfe 486static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 487{
6389ee94
AK		 488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 490 else
6389ee94 491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 492
493 return fault->nested_page_fault;
d4f8cf66
JR		 494}
495
3419ffc8
SY		 496void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497{
7460fb4a
AK		 498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 500}
501EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
298101da
AK		 503void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504{
ce7ddec4 505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 506}
507EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
ce7ddec4
JR		 509void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510{
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512}
513EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
0a79b009
AK		 515/*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 520{
0a79b009
AK		 521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
298101da 525}
0a79b009 526EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 527
16f8a6f9
NA		 528bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529{
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535}
536EXPORT_SYMBOL_GPL(kvm_require_dr);
537
ec92fe44
JR		 538/*
539 * This function will be used to read from the physical memory of the currently
54bf36aa 540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 541 * can read from guest physical or from the guest's guest physical memory.
542 */
543int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546{
54987b7a 547 struct x86_exception exception;
ec92fe44
JR		 548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
54987b7a 552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
54bf36aa 558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 559}
560EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
69b0049a 562static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 563 void *data, int offset, int len, u32 access)
564{
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567}
568
a03490ed
CO		 569/*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
ff03a073 572int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 573{
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
ff03a073 578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 579
ff03a073
JR		 580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 588 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
ff03a073 597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 602out:
a03490ed
CO		 603
604 return ret;
605}
cc4b6871 606EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 607
9ed38ffa 608bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 609{
ff03a073 610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 611 bool changed = true;
3d06b8bf
JR		 612 int offset;
613 gfn_t gfn;
d835dfec
AK		 614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
6de4f3ad
AK		 619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
a512177e
PB		 623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 627 if (r < 0)
628 goto out;
ff03a073 629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 630out:
d835dfec
AK		 631
632 return changed;
633}
9ed38ffa 634EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 635
49a9b07e 636int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 637{
aad82703 638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 640
f9a48e6a
AK		 641 cr0 |= X86_CR0_ET;
642
ab344828 643#ifdef CONFIG_X86_64
0f12244f
GN		 644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
ab344828
GN		 646#endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 649
0f12244f
GN		 650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
a03490ed 652
0f12244f
GN		 653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
a03490ed
CO		 655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657#ifdef CONFIG_X86_64
f6801dff 658 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 659 int cs_db, cs_l;
660
0f12244f
GN		 661 if (!is_pae(vcpu))
662 return 1;
a03490ed 663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 664 if (cs_l)
665 return 1;
a03490ed
CO		 666 } else
667#endif
ff03a073 668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 669 kvm_read_cr3(vcpu)))
0f12244f 670 return 1;
a03490ed
CO		 671 }
672
ad756a16
MJ		 673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
a03490ed 676 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 677
d170c419 678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 679 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 680 kvm_async_pf_hash_reset(vcpu);
681 }
e5f3f027 682
aad82703
SY		 683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
b18d5431 685
879ae188
LE		 686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
0f12244f
GN		 691 return 0;
692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 694
2d3ad1f4 695void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 696{
49a9b07e 697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 700
42bdf991
MT		 701static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702{
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 706 if (vcpu->arch.xcr0 != host_xcr0)
707 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 708 vcpu->guest_xcr0_loaded = 1;
709 }
710}
711
712static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
713{
714 if (vcpu->guest_xcr0_loaded) {
715 if (vcpu->arch.xcr0 != host_xcr0)
716 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
717 vcpu->guest_xcr0_loaded = 0;
718 }
719}
720
69b0049a 721static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 722{
56c103ec
LJ		 723 u64 xcr0 = xcr;
724 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 725 u64 valid_bits;
2acf923e
DC		 726
727 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
728 if (index != XCR_XFEATURE_ENABLED_MASK)
729 return 1;
d91cab78 730 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 731 return 1;
d91cab78 732 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 733 return 1;
46c34cb0
PB		 734
735 /*
736 * Do not allow the guest to set bits that we do not support
737 * saving. However, xcr0 bit 0 is always set, even if the
738 * emulated CPU does not support XSAVE (see fx_init).
739 */
d91cab78 740 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 741 if (xcr0 & ~valid_bits)
2acf923e 742 return 1;
46c34cb0 743
d91cab78
DH		 744 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
745 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 746 return 1;
747
d91cab78
DH		 748 if (xcr0 & XFEATURE_MASK_AVX512) {
749 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 750 return 1;
d91cab78 751 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 752 return 1;
753 }
2acf923e 754 vcpu->arch.xcr0 = xcr0;
56c103ec 755
d91cab78 756 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 757 kvm_update_cpuid(vcpu);
2acf923e
DC		 758 return 0;
759}
760
761int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
762{
764bcbc5
Z		 763 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
764 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 765 kvm_inject_gp(vcpu, 0);
766 return 1;
767 }
768 return 0;
769}
770EXPORT_SYMBOL_GPL(kvm_set_xcr);
771
a83b29c6 772int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 773{
fc78f519 774 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 775 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 776 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 777
0f12244f
GN		 778 if (cr4 & CR4_RESERVED_BITS)
779 return 1;
a03490ed 780
d6321d49 781 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 782 return 1;
783
d6321d49 784 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 785 return 1;
786
d6321d49 787 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 788 return 1;
789
d6321d49 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 791 return 1;
792
d6321d49 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 794 return 1;
795
fd8cb433 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 797 return 1;
798
ae3e61e1
PB		 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
800 return 1;
801
a03490ed 802 if (is_long_mode(vcpu)) {
0f12244f
GN		 803 if (!(cr4 & X86_CR4_PAE))
804 return 1;
a2edf57f
AK		 805 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
806 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 807 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
808 kvm_read_cr3(vcpu)))
0f12244f
GN		 809 return 1;
810
ad756a16 811 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 812 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 813 return 1;
814
815 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
816 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
817 return 1;
818 }
819
5e1746d6 820 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 821 return 1;
a03490ed 822
ad756a16
MJ		 823 if (((cr4 ^ old_cr4) & pdptr_bits) ||
824 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 825 kvm_mmu_reset_context(vcpu);
0f12244f 826
b9baba86 827 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 828 kvm_update_cpuid(vcpu);
2acf923e 829
0f12244f
GN		 830 return 0;
831}
2d3ad1f4 832EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 833
2390218b 834int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 835{
ac146235 836#ifdef CONFIG_X86_64
9d88fca7 837 cr3 &= ~CR3_PCID_INVD;
ac146235 838#endif
9d88fca7 839
9f8fe504 840 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 841 kvm_mmu_sync_roots(vcpu);
77c3913b 842 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 843 return 0;
d835dfec
AK		 844 }
845
d1cd3ce9
YZ		 846 if (is_long_mode(vcpu) &&
847 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
848 return 1;
849 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 850 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 851 return 1;
a03490ed 852
0f12244f 853 vcpu->arch.cr3 = cr3;
aff48baa 854 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 855 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 856 return 0;
857}
2d3ad1f4 858EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 859
eea1cff9 860int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 861{
0f12244f
GN		 862 if (cr8 & CR8_RESERVED_BITS)
863 return 1;
35754c98 864 if (lapic_in_kernel(vcpu))
a03490ed
CO		 865 kvm_lapic_set_tpr(vcpu, cr8);
866 else
ad312c7c 867 vcpu->arch.cr8 = cr8;
0f12244f
GN		 868 return 0;
869}
2d3ad1f4 870EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 871
2d3ad1f4 872unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 873{
35754c98 874 if (lapic_in_kernel(vcpu))
a03490ed
CO		 875 return kvm_lapic_get_cr8(vcpu);
876 else
ad312c7c 877 return vcpu->arch.cr8;
a03490ed 878}
2d3ad1f4 879EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 880
ae561ede
NA		 881static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
882{
883 int i;
884
885 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
886 for (i = 0; i < KVM_NR_DB_REGS; i++)
887 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
888 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
889 }
890}
891
73aaf249
JK		 892static void kvm_update_dr6(struct kvm_vcpu *vcpu)
893{
894 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
895 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
896}
897
c8639010
JK		 898static void kvm_update_dr7(struct kvm_vcpu *vcpu)
899{
900 unsigned long dr7;
901
902 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
903 dr7 = vcpu->arch.guest_debug_dr7;
904 else
905 dr7 = vcpu->arch.dr7;
906 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 907 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
908 if (dr7 & DR7_BP_EN_MASK)
909 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 910}
911
6f43ed01
NA		 912static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
913{
914 u64 fixed = DR6_FIXED_1;
915
d6321d49 916 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 917 fixed |= DR6_RTM;
918 return fixed;
919}
920
338dbc97 921static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 922{
923 switch (dr) {
924 case 0 ... 3:
925 vcpu->arch.db[dr] = val;
926 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
927 vcpu->arch.eff_db[dr] = val;
928 break;
929 case 4:
020df079
GN		 930 /* fall through */
931 case 6:
338dbc97
GN		 932 if (val & 0xffffffff00000000ULL)
933 return -1; /* #GP */
6f43ed01 934 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 935 kvm_update_dr6(vcpu);
020df079
GN		 936 break;
937 case 5:
020df079
GN		 938 /* fall through */
939 default: /* 7 */
338dbc97
GN		 940 if (val & 0xffffffff00000000ULL)
941 return -1; /* #GP */
020df079 942 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 943 kvm_update_dr7(vcpu);
020df079
GN		 944 break;
945 }
946
947 return 0;
948}
338dbc97
GN		 949
950int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
951{
16f8a6f9 952 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 953 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 954 return 1;
955 }
956 return 0;
338dbc97 957}
020df079
GN		 958EXPORT_SYMBOL_GPL(kvm_set_dr);
959
16f8a6f9 960int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 961{
962 switch (dr) {
963 case 0 ... 3:
964 *val = vcpu->arch.db[dr];
965 break;
966 case 4:
020df079
GN		 967 /* fall through */
968 case 6:
73aaf249
JK		 969 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
970 *val = vcpu->arch.dr6;
971 else
972 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 973 break;
974 case 5:
020df079
GN		 975 /* fall through */
976 default: /* 7 */
977 *val = vcpu->arch.dr7;
978 break;
979 }
338dbc97
GN		 980 return 0;
981}
020df079
GN		 982EXPORT_SYMBOL_GPL(kvm_get_dr);
983
022cd0e8
AK		 984bool kvm_rdpmc(struct kvm_vcpu *vcpu)
985{
986 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
987 u64 data;
988 int err;
989
c6702c9d 990 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 991 if (err)
992 return err;
993 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
994 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
995 return err;
996}
997EXPORT_SYMBOL_GPL(kvm_rdpmc);
998
043405e1
CO		 999/*
1000 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1001 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1002 *
1003 * This list is modified at module load time to reflect the
e3267cbb 1004 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1005 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1006 * may depend on host virtualization features rather than host cpu features.
043405e1 1007 */
e3267cbb 1008
043405e1
CO		 1009static u32 msrs_to_save[] = {
1010 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1011 MSR_STAR,
043405e1
CO		 1012#ifdef CONFIG_X86_64
1013 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1014#endif
b3897a49 1015 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1016 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1017 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1018};
1019
1020static unsigned num_msrs_to_save;
1021
62ef68bb
PB		 1022static u32 emulated_msrs[] = {
1023 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1024 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1025 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1026 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1027 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1028 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1029 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1030 HV_X64_MSR_RESET,
11c4b1ca 1031 HV_X64_MSR_VP_INDEX,
9eec50b8 1032 HV_X64_MSR_VP_RUNTIME,
5c919412 1033 HV_X64_MSR_SCONTROL,
1f4b34f8 1034 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1035 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1036 MSR_KVM_PV_EOI_EN,
1037
ba904635 1038 MSR_IA32_TSC_ADJUST,
a3e06bbe 1039 MSR_IA32_TSCDEADLINE,
043405e1 1040 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1041 MSR_IA32_MCG_STATUS,
1042 MSR_IA32_MCG_CTL,
c45dcc71 1043 MSR_IA32_MCG_EXT_CTL,
64d60670 1044 MSR_IA32_SMBASE,
52797bf9 1045 MSR_SMI_COUNT,
db2336a8
KH		 1046 MSR_PLATFORM_INFO,
1047 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1048};
1049
62ef68bb
PB		 1050static unsigned num_emulated_msrs;
1051
384bb783 1052bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1053{
b69e8cae 1054 if (efer & efer_reserved_bits)
384bb783 1055 return false;
15c4a640 1056
1b4d56b8 1057 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1058 return false;
1b2fd70c 1059
1b4d56b8 1060 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1061 return false;
d8017474 1062
384bb783
JK		 1063 return true;
1064}
1065EXPORT_SYMBOL_GPL(kvm_valid_efer);
1066
1067static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1068{
1069 u64 old_efer = vcpu->arch.efer;
1070
1071 if (!kvm_valid_efer(vcpu, efer))
1072 return 1;
1073
1074 if (is_paging(vcpu)
1075 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1076 return 1;
1077
15c4a640 1078 efer &= ~EFER_LMA;
f6801dff 1079 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1080
a3d204e2
SY		 1081 kvm_x86_ops->set_efer(vcpu, efer);
1082
aad82703
SY		 1083 /* Update reserved bits */
1084 if ((efer ^ old_efer) & EFER_NX)
1085 kvm_mmu_reset_context(vcpu);
1086
b69e8cae 1087 return 0;
15c4a640
CO		 1088}
1089
f2b4b7dd
JR		 1090void kvm_enable_efer_bits(u64 mask)
1091{
1092 efer_reserved_bits &= ~mask;
1093}
1094EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1095
15c4a640
CO		 1096/*
1097 * Writes msr value into into the appropriate "register".
1098 * Returns 0 on success, non-0 otherwise.
1099 * Assumes vcpu_load() was already called.
1100 */
8fe8ab46 1101int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1102{
854e8bb1
NA		 1103 switch (msr->index) {
1104 case MSR_FS_BASE:
1105 case MSR_GS_BASE:
1106 case MSR_KERNEL_GS_BASE:
1107 case MSR_CSTAR:
1108 case MSR_LSTAR:
fd8cb433 1109 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1110 return 1;
1111 break;
1112 case MSR_IA32_SYSENTER_EIP:
1113 case MSR_IA32_SYSENTER_ESP:
1114 /*
1115 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1116 * non-canonical address is written on Intel but not on
1117 * AMD (which ignores the top 32-bits, because it does
1118 * not implement 64-bit SYSENTER).
1119 *
1120 * 64-bit code should hence be able to write a non-canonical
1121 * value on AMD. Making the address canonical ensures that
1122 * vmentry does not fail on Intel after writing a non-canonical
1123 * value, and that something deterministic happens if the guest
1124 * invokes 64-bit SYSENTER.
1125 */
fd8cb433 1126 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1127 }
8fe8ab46 1128 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1129}
854e8bb1 1130EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1131
313a3dc7
CO		 1132/*
1133 * Adapt set_msr() to msr_io()'s calling convention
1134 */
609e36d3
PB		 1135static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1136{
1137 struct msr_data msr;
1138 int r;
1139
1140 msr.index = index;
1141 msr.host_initiated = true;
1142 r = kvm_get_msr(vcpu, &msr);
1143 if (r)
1144 return r;
1145
1146 *data = msr.data;
1147 return 0;
1148}
1149
313a3dc7
CO		 1150static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1151{
8fe8ab46
WA		 1152 struct msr_data msr;
1153
1154 msr.data = *data;
1155 msr.index = index;
1156 msr.host_initiated = true;
1157 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1158}
1159
16e8d74d
MT		 1160#ifdef CONFIG_X86_64
1161struct pvclock_gtod_data {
1162 seqcount_t seq;
1163
1164 struct { /* extract of a clocksource struct */
1165 int vclock_mode;
a5a1d1c2
TG		 1166 u64 cycle_last;
1167 u64 mask;
16e8d74d
MT		 1168 u32 mult;
1169 u32 shift;
1170 } clock;
1171
cbcf2dd3
TG		 1172 u64 boot_ns;
1173 u64 nsec_base;
55dd00a7 1174 u64 wall_time_sec;
16e8d74d
MT		 1175};
1176
1177static struct pvclock_gtod_data pvclock_gtod_data;
1178
1179static void update_pvclock_gtod(struct timekeeper *tk)
1180{
1181 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1182 u64 boot_ns;
1183
876e7881 1184 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1185
1186 write_seqcount_begin(&vdata->seq);
1187
1188 /* copy pvclock gtod data */
876e7881
PZ		 1189 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1190 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1191 vdata->clock.mask = tk->tkr_mono.mask;
1192 vdata->clock.mult = tk->tkr_mono.mult;
1193 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1194
cbcf2dd3 1195 vdata->boot_ns = boot_ns;
876e7881 1196 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1197
55dd00a7
MT		 1198 vdata->wall_time_sec = tk->xtime_sec;
1199
16e8d74d
MT		 1200 write_seqcount_end(&vdata->seq);
1201}
1202#endif
1203
bab5bb39
NK		 1204void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1205{
1206 /*
1207 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1208 * vcpu_enter_guest. This function is only called from
1209 * the physical CPU that is running vcpu.
1210 */
1211 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1212}
16e8d74d 1213
18068523
GOC		 1214static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1215{
9ed3c444
AK		 1216 int version;
1217 int r;
50d0a0f9 1218 struct pvclock_wall_clock wc;
87aeb54f 1219 struct timespec64 boot;
18068523
GOC		 1220
1221 if (!wall_clock)
1222 return;
1223
9ed3c444
AK		 1224 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1225 if (r)
1226 return;
1227
1228 if (version & 1)
1229 ++version; /* first time write, random junk */
1230
1231 ++version;
18068523 1232
1dab1345
NK		 1233 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1234 return;
18068523 1235
50d0a0f9
GH		 1236 /*
1237 * The guest calculates current wall clock time by adding
34c238a1 1238 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1239 * wall clock specified here. guest system time equals host
1240 * system time for us, thus we must fill in host boot time here.
1241 */
87aeb54f 1242 getboottime64(&boot);
50d0a0f9 1243
4b648665 1244 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1245 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1246 boot = timespec64_sub(boot, ts);
4b648665 1247 }
87aeb54f 1248 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1249 wc.nsec = boot.tv_nsec;
1250 wc.version = version;
18068523
GOC		 1251
1252 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1253
1254 version++;
1255 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1256}
1257
50d0a0f9
GH		 1258static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1259{
b51012de
PB		 1260 do_shl32_div32(dividend, divisor);
1261 return dividend;
50d0a0f9
GH		 1262}
1263
3ae13faa 1264static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1265 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1266{
5f4e3f88 1267 uint64_t scaled64;
50d0a0f9
GH		 1268 int32_t shift = 0;
1269 uint64_t tps64;
1270 uint32_t tps32;
1271
3ae13faa
PB		 1272 tps64 = base_hz;
1273 scaled64 = scaled_hz;
50933623 1274 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1275 tps64 >>= 1;
1276 shift--;
1277 }
1278
1279 tps32 = (uint32_t)tps64;
50933623
JK		 1280 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1281 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1282 scaled64 >>= 1;
1283 else
1284 tps32 <<= 1;
50d0a0f9
GH		 1285 shift++;
1286 }
1287
5f4e3f88
ZA		 1288 *pshift = shift;
1289 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1290
3ae13faa
PB		 1291 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1292 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1293}
1294
d828199e 1295#ifdef CONFIG_X86_64
16e8d74d 1296static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1297#endif
16e8d74d 1298
c8076604 1299static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1300static unsigned long max_tsc_khz;
c8076604 1301
cc578287 1302static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1303{
cc578287
ZA		 1304 u64 v = (u64)khz * (1000000 + ppm);
1305 do_div(v, 1000000);
1306 return v;
1e993611
JR		 1307}
1308
381d585c
HZ		 1309static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1310{
1311 u64 ratio;
1312
1313 /* Guest TSC same frequency as host TSC? */
1314 if (!scale) {
1315 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1316 return 0;
1317 }
1318
1319 /* TSC scaling supported? */
1320 if (!kvm_has_tsc_control) {
1321 if (user_tsc_khz > tsc_khz) {
1322 vcpu->arch.tsc_catchup = 1;
1323 vcpu->arch.tsc_always_catchup = 1;
1324 return 0;
1325 } else {
1326 WARN(1, "user requested TSC rate below hardware speed\n");
1327 return -1;
1328 }
1329 }
1330
1331 /* TSC scaling required - calculate ratio */
1332 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1333 user_tsc_khz, tsc_khz);
1334
1335 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1336 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1337 user_tsc_khz);
1338 return -1;
1339 }
1340
1341 vcpu->arch.tsc_scaling_ratio = ratio;
1342 return 0;
1343}
1344
4941b8cb 1345static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1346{
cc578287
ZA		 1347 u32 thresh_lo, thresh_hi;
1348 int use_scaling = 0;
217fc9cf 1349
03ba32ca 1350 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1351 if (user_tsc_khz == 0) {
ad721883
HZ		 1352 /* set tsc_scaling_ratio to a safe value */
1353 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1354 return -1;
ad721883 1355 }
03ba32ca 1356
c285545f 1357 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1358 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1359 &vcpu->arch.virtual_tsc_shift,
1360 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1361 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1362
1363 /*
1364 * Compute the variation in TSC rate which is acceptable
1365 * within the range of tolerance and decide if the
1366 * rate being applied is within that bounds of the hardware
1367 * rate. If so, no scaling or compensation need be done.
1368 */
1369 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1370 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1371 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1372 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1373 use_scaling = 1;
1374 }
4941b8cb 1375 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1376}
1377
1378static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1379{
e26101b1 1380 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1381 vcpu->arch.virtual_tsc_mult,
1382 vcpu->arch.virtual_tsc_shift);
e26101b1 1383 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1384 return tsc;
1385}
1386
b0c39dc6
VK		 1387static inline int gtod_is_based_on_tsc(int mode)
1388{
1389 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1390}
1391
69b0049a 1392static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1393{
1394#ifdef CONFIG_X86_64
1395 bool vcpus_matched;
b48aa97e
MT		 1396 struct kvm_arch *ka = &vcpu->kvm->arch;
1397 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1398
1399 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1400 atomic_read(&vcpu->kvm->online_vcpus));
1401
7f187922
MT		 1402 /*
1403 * Once the masterclock is enabled, always perform request in
1404 * order to update it.
1405 *
1406 * In order to enable masterclock, the host clocksource must be TSC
1407 * and the vcpus need to have matched TSCs. When that happens,
1408 * perform request to enable masterclock.
1409 */
1410 if (ka->use_master_clock ||
b0c39dc6 1411 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1412 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1413
1414 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1415 atomic_read(&vcpu->kvm->online_vcpus),
1416 ka->use_master_clock, gtod->clock.vclock_mode);
1417#endif
1418}
1419
ba904635
WA		 1420static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1421{
3e3f5026 1422 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1423 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1424}
1425
35181e86
HZ		 1426/*
1427 * Multiply tsc by a fixed point number represented by ratio.
1428 *
1429 * The most significant 64-N bits (mult) of ratio represent the
1430 * integral part of the fixed point number; the remaining N bits
1431 * (frac) represent the fractional part, ie. ratio represents a fixed
1432 * point number (mult + frac * 2^(-N)).
1433 *
1434 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1435 */
1436static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1437{
1438 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1439}
1440
1441u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1442{
1443 u64 _tsc = tsc;
1444 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1445
1446 if (ratio != kvm_default_tsc_scaling_ratio)
1447 _tsc = __scale_tsc(ratio, tsc);
1448
1449 return _tsc;
1450}
1451EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1452
07c1419a
HZ		 1453static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1454{
1455 u64 tsc;
1456
1457 tsc = kvm_scale_tsc(vcpu, rdtsc());
1458
1459 return target_tsc - tsc;
1460}
1461
4ba76538
HZ		 1462u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1463{
ea26e4ec 1464 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1465}
1466EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1467
a545ab6a
LC		 1468static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1469{
1470 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1471 vcpu->arch.tsc_offset = offset;
1472}
1473
b0c39dc6
VK		 1474static inline bool kvm_check_tsc_unstable(void)
1475{
1476#ifdef CONFIG_X86_64
1477 /*
1478 * TSC is marked unstable when we're running on Hyper-V,
1479 * 'TSC page' clocksource is good.
1480 */
1481 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1482 return false;
1483#endif
1484 return check_tsc_unstable();
1485}
1486
8fe8ab46 1487void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1488{
1489 struct kvm *kvm = vcpu->kvm;
f38e098f 1490 u64 offset, ns, elapsed;
99e3e30a 1491 unsigned long flags;
b48aa97e 1492 bool matched;
0d3da0d2 1493 bool already_matched;
8fe8ab46 1494 u64 data = msr->data;
c5e8ec8e 1495 bool synchronizing = false;
99e3e30a 1496
038f8c11 1497 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1498 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1499 ns = ktime_get_boot_ns();
f38e098f 1500 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1501
03ba32ca 1502 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1503 if (data == 0 && msr->host_initiated) {
1504 /*
1505 * detection of vcpu initialization -- need to sync
1506 * with other vCPUs. This particularly helps to keep
1507 * kvm_clock stable after CPU hotplug
1508 */
1509 synchronizing = true;
1510 } else {
1511 u64 tsc_exp = kvm->arch.last_tsc_write +
1512 nsec_to_cycles(vcpu, elapsed);
1513 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1514 /*
1515 * Special case: TSC write with a small delta (1 second)
1516 * of virtual cycle time against real time is
1517 * interpreted as an attempt to synchronize the CPU.
1518 */
1519 synchronizing = data < tsc_exp + tsc_hz &&
1520 data + tsc_hz > tsc_exp;
1521 }
c5e8ec8e 1522 }
f38e098f
ZA		 1523
1524 /*
5d3cb0f6
ZA		 1525 * For a reliable TSC, we can match TSC offsets, and for an unstable
1526 * TSC, we add elapsed time in this computation. We could let the
1527 * compensation code attempt to catch up if we fall behind, but
1528 * it's better to try to match offsets from the beginning.
1529 */
c5e8ec8e 1530 if (synchronizing &&
5d3cb0f6 1531 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1532 if (!kvm_check_tsc_unstable()) {
e26101b1 1533 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1534 pr_debug("kvm: matched tsc offset for %llu\n", data);
1535 } else {
857e4099 1536 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1537 data += delta;
07c1419a 1538 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1539 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1540 }
b48aa97e 1541 matched = true;
0d3da0d2 1542 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1543 } else {
1544 /*
1545 * We split periods of matched TSC writes into generations.
1546 * For each generation, we track the original measured
1547 * nanosecond time, offset, and write, so if TSCs are in
1548 * sync, we can match exact offset, and if not, we can match
4a969980 1549 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1550 *
1551 * These values are tracked in kvm->arch.cur_xxx variables.
1552 */
1553 kvm->arch.cur_tsc_generation++;
1554 kvm->arch.cur_tsc_nsec = ns;
1555 kvm->arch.cur_tsc_write = data;
1556 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1557 matched = false;
0d3da0d2 1558 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1559 kvm->arch.cur_tsc_generation, data);
f38e098f 1560 }
e26101b1
ZA		 1561
1562 /*
1563 * We also track th most recent recorded KHZ, write and time to
1564 * allow the matching interval to be extended at each write.
1565 */
f38e098f
ZA		 1566 kvm->arch.last_tsc_nsec = ns;
1567 kvm->arch.last_tsc_write = data;
5d3cb0f6 1568 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1569
b183aa58 1570 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1571
1572 /* Keep track of which generation this VCPU has synchronized to */
1573 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1574 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1575 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1576
d6321d49 1577 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1578 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1579
a545ab6a 1580 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1581 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1582
1583 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1584 if (!matched) {
b48aa97e 1585 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1586 } else if (!already_matched) {
1587 kvm->arch.nr_vcpus_matched_tsc++;
1588 }
b48aa97e
MT		 1589
1590 kvm_track_tsc_matching(vcpu);
1591 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1592}
e26101b1 1593
99e3e30a
ZA		 1594EXPORT_SYMBOL_GPL(kvm_write_tsc);
1595
58ea6767
HZ		 1596static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1597 s64 adjustment)
1598{
ea26e4ec 1599 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1600}
1601
1602static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1603{
1604 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1605 WARN_ON(adjustment < 0);
1606 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1607 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1608}
1609
d828199e
MT		 1610#ifdef CONFIG_X86_64
1611
a5a1d1c2 1612static u64 read_tsc(void)
d828199e 1613{
a5a1d1c2 1614 u64 ret = (u64)rdtsc_ordered();
03b9730b 1615 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1616
1617 if (likely(ret >= last))
1618 return ret;
1619
1620 /*
1621 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1622 * predictable (it's just a function of time and the likely is
d828199e
MT		 1623 * very likely) and there's a data dependence, so force GCC
1624 * to generate a branch instead. I don't barrier() because
1625 * we don't actually need a barrier, and if this function
1626 * ever gets inlined it will generate worse code.
1627 */
1628 asm volatile ("");
1629 return last;
1630}
1631
b0c39dc6 1632static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1633{
1634 long v;
1635 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1636 u64 tsc_pg_val;
1637
1638 switch (gtod->clock.vclock_mode) {
1639 case VCLOCK_HVCLOCK:
1640 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1641 tsc_timestamp);
1642 if (tsc_pg_val != U64_MAX) {
1643 /* TSC page valid */
1644 *mode = VCLOCK_HVCLOCK;
1645 v = (tsc_pg_val - gtod->clock.cycle_last) &
1646 gtod->clock.mask;
1647 } else {
1648 /* TSC page invalid */
1649 *mode = VCLOCK_NONE;
1650 }
1651 break;
1652 case VCLOCK_TSC:
1653 *mode = VCLOCK_TSC;
1654 *tsc_timestamp = read_tsc();
1655 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1656 gtod->clock.mask;
1657 break;
1658 default:
1659 *mode = VCLOCK_NONE;
1660 }
d828199e 1661
b0c39dc6
VK		 1662 if (*mode == VCLOCK_NONE)
1663 *tsc_timestamp = v = 0;
d828199e 1664
d828199e
MT		 1665 return v * gtod->clock.mult;
1666}
1667
b0c39dc6 1668static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1669{
cbcf2dd3 1670 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1671 unsigned long seq;
d828199e 1672 int mode;
cbcf2dd3 1673 u64 ns;
d828199e 1674
d828199e
MT		 1675 do {
1676 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1677 ns = gtod->nsec_base;
b0c39dc6 1678 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1679 ns >>= gtod->clock.shift;
cbcf2dd3 1680 ns += gtod->boot_ns;
d828199e 1681 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1682 *t = ns;
d828199e
MT		 1683
1684 return mode;
1685}
1686
b0c39dc6 1687static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1688{
1689 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1690 unsigned long seq;
1691 int mode;
1692 u64 ns;
1693
1694 do {
1695 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1696 ts->tv_sec = gtod->wall_time_sec;
1697 ns = gtod->nsec_base;
b0c39dc6 1698 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1699 ns >>= gtod->clock.shift;
1700 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1701
1702 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1703 ts->tv_nsec = ns;
1704
1705 return mode;
1706}
1707
b0c39dc6
VK		 1708/* returns true if host is using TSC based clocksource */
1709static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1710{
d828199e 1711 /* checked again under seqlock below */
b0c39dc6 1712 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1713 return false;
1714
b0c39dc6
VK		 1715 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1716 tsc_timestamp));
d828199e 1717}
55dd00a7 1718
b0c39dc6 1719/* returns true if host is using TSC based clocksource */
55dd00a7 1720static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1721 u64 *tsc_timestamp)
55dd00a7
MT		 1722{
1723 /* checked again under seqlock below */
b0c39dc6 1724 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1725 return false;
1726
b0c39dc6 1727 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1728}
d828199e
MT		 1729#endif
1730
1731/*
1732 *
b48aa97e
MT		 1733 * Assuming a stable TSC across physical CPUS, and a stable TSC
1734 * across virtual CPUs, the following condition is possible.
1735 * Each numbered line represents an event visible to both
d828199e
MT		 1736 * CPUs at the next numbered event.
1737 *
1738 * "timespecX" represents host monotonic time. "tscX" represents
1739 * RDTSC value.
1740 *
1741 * VCPU0 on CPU0 | VCPU1 on CPU1
1742 *
1743 * 1. read timespec0,tsc0
1744 * 2. | timespec1 = timespec0 + N
1745 * | tsc1 = tsc0 + M
1746 * 3. transition to guest | transition to guest
1747 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1748 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1749 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1750 *
1751 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1752 *
1753 * - ret0 < ret1
1754 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1755 * ...
1756 * - 0 < N - M => M < N
1757 *
1758 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1759 * always the case (the difference between two distinct xtime instances
1760 * might be smaller then the difference between corresponding TSC reads,
1761 * when updating guest vcpus pvclock areas).
1762 *
1763 * To avoid that problem, do not allow visibility of distinct
1764 * system_timestamp/tsc_timestamp values simultaneously: use a master
1765 * copy of host monotonic time values. Update that master copy
1766 * in lockstep.
1767 *
b48aa97e 1768 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1769 *
1770 */
1771
1772static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1773{
1774#ifdef CONFIG_X86_64
1775 struct kvm_arch *ka = &kvm->arch;
1776 int vclock_mode;
b48aa97e
MT		 1777 bool host_tsc_clocksource, vcpus_matched;
1778
1779 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1780 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1781
1782 /*
1783 * If the host uses TSC clock, then passthrough TSC as stable
1784 * to the guest.
1785 */
b48aa97e 1786 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1787 &ka->master_kernel_ns,
1788 &ka->master_cycle_now);
1789
16a96021 1790 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1791 && !ka->backwards_tsc_observed
54750f2c 1792 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1793
d828199e
MT		 1794 if (ka->use_master_clock)
1795 atomic_set(&kvm_guest_has_master_clock, 1);
1796
1797 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1798 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1799 vcpus_matched);
d828199e
MT		 1800#endif
1801}
1802
2860c4b1
PB		 1803void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1804{
1805 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1806}
1807
2e762ff7
MT		 1808static void kvm_gen_update_masterclock(struct kvm *kvm)
1809{
1810#ifdef CONFIG_X86_64
1811 int i;
1812 struct kvm_vcpu *vcpu;
1813 struct kvm_arch *ka = &kvm->arch;
1814
1815 spin_lock(&ka->pvclock_gtod_sync_lock);
1816 kvm_make_mclock_inprogress_request(kvm);
1817 /* no guest entries from this point */
1818 pvclock_update_vm_gtod_copy(kvm);
1819
1820 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1821 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1822
1823 /* guest entries allowed */
1824 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1825 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1826
1827 spin_unlock(&ka->pvclock_gtod_sync_lock);
1828#endif
1829}
1830
e891a32e 1831u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1832{
108b249c 1833 struct kvm_arch *ka = &kvm->arch;
8b953440 1834 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1835 u64 ret;
108b249c 1836
8b953440
PB		 1837 spin_lock(&ka->pvclock_gtod_sync_lock);
1838 if (!ka->use_master_clock) {
1839 spin_unlock(&ka->pvclock_gtod_sync_lock);
1840 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1841 }
1842
8b953440
PB		 1843 hv_clock.tsc_timestamp = ka->master_cycle_now;
1844 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1845 spin_unlock(&ka->pvclock_gtod_sync_lock);
1846
e2c2206a
WL		 1847 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1848 get_cpu();
1849
e70b57a6
WL		 1850 if (__this_cpu_read(cpu_tsc_khz)) {
1851 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1852 &hv_clock.tsc_shift,
1853 &hv_clock.tsc_to_system_mul);
1854 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1855 } else
1856 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1857
1858 put_cpu();
1859
1860 return ret;
108b249c
PB		 1861}
1862
0d6dd2ff
PB		 1863static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1864{
1865 struct kvm_vcpu_arch *vcpu = &v->arch;
1866 struct pvclock_vcpu_time_info guest_hv_clock;
1867
4e335d9e 1868 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1869 &guest_hv_clock, sizeof(guest_hv_clock))))
1870 return;
1871
1872 /* This VCPU is paused, but it's legal for a guest to read another
1873 * VCPU's kvmclock, so we really have to follow the specification where
1874 * it says that version is odd if data is being modified, and even after
1875 * it is consistent.
1876 *
1877 * Version field updates must be kept separate. This is because
1878 * kvm_write_guest_cached might use a "rep movs" instruction, and
1879 * writes within a string instruction are weakly ordered. So there
1880 * are three writes overall.
1881 *
1882 * As a small optimization, only write the version field in the first
1883 * and third write. The vcpu->pv_time cache is still valid, because the
1884 * version field is the first in the struct.
1885 */
1886 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1887
51c4b8bb
LA		 1888 if (guest_hv_clock.version & 1)
1889 ++guest_hv_clock.version; /* first time write, random junk */
1890
0d6dd2ff 1891 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1892 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1893 &vcpu->hv_clock,
1894 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1895
1896 smp_wmb();
1897
1898 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1899 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1900
1901 if (vcpu->pvclock_set_guest_stopped_request) {
1902 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1903 vcpu->pvclock_set_guest_stopped_request = false;
1904 }
1905
1906 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1907
4e335d9e
PB		 1908 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1909 &vcpu->hv_clock,
1910 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1911
1912 smp_wmb();
1913
1914 vcpu->hv_clock.version++;
4e335d9e
PB		 1915 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1916 &vcpu->hv_clock,
1917 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1918}
1919
34c238a1 1920static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1921{
78db6a50 1922 unsigned long flags, tgt_tsc_khz;
18068523 1923 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1924 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1925 s64 kernel_ns;
d828199e 1926 u64 tsc_timestamp, host_tsc;
51d59c6b 1927 u8 pvclock_flags;
d828199e
MT		 1928 bool use_master_clock;
1929
1930 kernel_ns = 0;
1931 host_tsc = 0;
18068523 1932
d828199e
MT		 1933 /*
1934 * If the host uses TSC clock, then passthrough TSC as stable
1935 * to the guest.
1936 */
1937 spin_lock(&ka->pvclock_gtod_sync_lock);
1938 use_master_clock = ka->use_master_clock;
1939 if (use_master_clock) {
1940 host_tsc = ka->master_cycle_now;
1941 kernel_ns = ka->master_kernel_ns;
1942 }
1943 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1944
1945 /* Keep irq disabled to prevent changes to the clock */
1946 local_irq_save(flags);
78db6a50
PB		 1947 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1948 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1949 local_irq_restore(flags);
1950 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1951 return 1;
1952 }
d828199e 1953 if (!use_master_clock) {
4ea1636b 1954 host_tsc = rdtsc();
108b249c 1955 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1956 }
1957
4ba76538 1958 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1959
c285545f
ZA		 1960 /*
1961 * We may have to catch up the TSC to match elapsed wall clock
1962 * time for two reasons, even if kvmclock is used.
1963 * 1) CPU could have been running below the maximum TSC rate
1964 * 2) Broken TSC compensation resets the base at each VCPU
1965 * entry to avoid unknown leaps of TSC even when running
1966 * again on the same CPU. This may cause apparent elapsed
1967 * time to disappear, and the guest to stand still or run
1968 * very slowly.
1969 */
1970 if (vcpu->tsc_catchup) {
1971 u64 tsc = compute_guest_tsc(v, kernel_ns);
1972 if (tsc > tsc_timestamp) {
f1e2b260 1973 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1974 tsc_timestamp = tsc;
1975 }
50d0a0f9
GH		 1976 }
1977
18068523
GOC		 1978 local_irq_restore(flags);
1979
0d6dd2ff 1980 /* With all the info we got, fill in the values */
18068523 1981
78db6a50
PB		 1982 if (kvm_has_tsc_control)
1983 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1984
1985 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1986 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1987 &vcpu->hv_clock.tsc_shift,
1988 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1989 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1990 }
1991
1d5f066e 1992 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1993 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1994 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1995
d828199e 1996 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1997 pvclock_flags = 0;
d828199e
MT		 1998 if (use_master_clock)
1999 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2000
78c0337a
MT		 2001 vcpu->hv_clock.flags = pvclock_flags;
2002
095cf55d
PB		 2003 if (vcpu->pv_time_enabled)
2004 kvm_setup_pvclock_page(v);
2005 if (v == kvm_get_vcpu(v->kvm, 0))
2006 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2007 return 0;
c8076604
GH		 2008}
2009
0061d53d
MT		 2010/*
2011 * kvmclock updates which are isolated to a given vcpu, such as
2012 * vcpu->cpu migration, should not allow system_timestamp from
2013 * the rest of the vcpus to remain static. Otherwise ntp frequency
2014 * correction applies to one vcpu's system_timestamp but not
2015 * the others.
2016 *
2017 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2018 * We need to rate-limit these requests though, as they can
2019 * considerably slow guests that have a large number of vcpus.
2020 * The time for a remote vcpu to update its kvmclock is bound
2021 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2022 */
2023
7e44e449
AJ		 2024#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2025
2026static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2027{
2028 int i;
7e44e449
AJ		 2029 struct delayed_work *dwork = to_delayed_work(work);
2030 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2031 kvmclock_update_work);
2032 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2033 struct kvm_vcpu *vcpu;
2034
2035 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2036 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2037 kvm_vcpu_kick(vcpu);
2038 }
2039}
2040
7e44e449
AJ		 2041static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2042{
2043 struct kvm *kvm = v->kvm;
2044
105b21bb 2045 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2046 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2047 KVMCLOCK_UPDATE_DELAY);
2048}
2049
332967a3
AJ		 2050#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2051
2052static void kvmclock_sync_fn(struct work_struct *work)
2053{
2054 struct delayed_work *dwork = to_delayed_work(work);
2055 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2056 kvmclock_sync_work);
2057 struct kvm *kvm = container_of(ka, struct kvm, arch);
2058
630994b3
MT		 2059 if (!kvmclock_periodic_sync)
2060 return;
2061
332967a3
AJ		 2062 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2063 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2064 KVMCLOCK_SYNC_PERIOD);
2065}
2066
9ffd986c 2067static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2068{
890ca9ae
HY		 2069 u64 mcg_cap = vcpu->arch.mcg_cap;
2070 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2071 u32 msr = msr_info->index;
2072 u64 data = msr_info->data;
890ca9ae 2073
15c4a640 2074 switch (msr) {
15c4a640 2075 case MSR_IA32_MCG_STATUS:
890ca9ae 2076 vcpu->arch.mcg_status = data;
15c4a640 2077 break;
c7ac679c 2078 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2079 if (!(mcg_cap & MCG_CTL_P))
2080 return 1;
2081 if (data != 0 && data != ~(u64)0)
2082 return -1;
2083 vcpu->arch.mcg_ctl = data;
2084 break;
2085 default:
2086 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2087 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2088 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2089 /* only 0 or all 1s can be written to IA32_MCi_CTL
2090 * some Linux kernels though clear bit 10 in bank 4 to
2091 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2092 * this to avoid an uncatched #GP in the guest
2093 */
890ca9ae 2094 if ((offset & 0x3) == 0 &&
114be429 2095 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2096 return -1;
9ffd986c
WL		 2097 if (!msr_info->host_initiated &&
2098 (offset & 0x3) == 1 && data != 0)
2099 return -1;
890ca9ae
HY		 2100 vcpu->arch.mce_banks[offset] = data;
2101 break;
2102 }
2103 return 1;
2104 }
2105 return 0;
2106}
2107
ffde22ac
ES		 2108static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2109{
2110 struct kvm *kvm = vcpu->kvm;
2111 int lm = is_long_mode(vcpu);
2112 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2113 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2114 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2115 : kvm->arch.xen_hvm_config.blob_size_32;
2116 u32 page_num = data & ~PAGE_MASK;
2117 u64 page_addr = data & PAGE_MASK;
2118 u8 *page;
2119 int r;
2120
2121 r = -E2BIG;
2122 if (page_num >= blob_size)
2123 goto out;
2124 r = -ENOMEM;
ff5c2c03
SL		 2125 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2126 if (IS_ERR(page)) {
2127 r = PTR_ERR(page);
ffde22ac 2128 goto out;
ff5c2c03 2129 }
54bf36aa 2130 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2131 goto out_free;
2132 r = 0;
2133out_free:
2134 kfree(page);
2135out:
2136 return r;
2137}
2138
344d9588
GN		 2139static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2140{
2141 gpa_t gpa = data & ~0x3f;
2142
52a5c155
WL		 2143 /* Bits 3:5 are reserved, Should be zero */
2144 if (data & 0x38)
344d9588
GN		 2145 return 1;
2146
2147 vcpu->arch.apf.msr_val = data;
2148
2149 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2150 kvm_clear_async_pf_completion_queue(vcpu);
2151 kvm_async_pf_hash_reset(vcpu);
2152 return 0;
2153 }
2154
4e335d9e 2155 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2156 sizeof(u32)))
344d9588
GN		 2157 return 1;
2158
6adba527 2159 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2160 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2161 kvm_async_pf_wakeup_all(vcpu);
2162 return 0;
2163}
2164
12f9a48f
GC		 2165static void kvmclock_reset(struct kvm_vcpu *vcpu)
2166{
0b79459b 2167 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2168}
2169
f38a7b75
WL		 2170static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2171{
2172 ++vcpu->stat.tlb_flush;
2173 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2174}
2175
c9aaa895
GC		 2176static void record_steal_time(struct kvm_vcpu *vcpu)
2177{
2178 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2179 return;
2180
4e335d9e 2181 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2182 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2183 return;
2184
f38a7b75
WL		 2185 /*
2186 * Doing a TLB flush here, on the guest's behalf, can avoid
2187 * expensive IPIs.
2188 */
2189 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2190 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2191
35f3fae1
WL		 2192 if (vcpu->arch.st.steal.version & 1)
2193 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2194
2195 vcpu->arch.st.steal.version += 1;
2196
4e335d9e 2197 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2198 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2199
2200 smp_wmb();
2201
c54cdf14
LC		 2202 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2203 vcpu->arch.st.last_steal;
2204 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2205
4e335d9e 2206 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2207 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2208
2209 smp_wmb();
2210
2211 vcpu->arch.st.steal.version += 1;
c9aaa895 2212
4e335d9e 2213 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2214 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2215}
2216
8fe8ab46 2217int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2218{
5753785f 2219 bool pr = false;
8fe8ab46
WA		 2220 u32 msr = msr_info->index;
2221 u64 data = msr_info->data;
5753785f 2222
15c4a640 2223 switch (msr) {
2e32b719
BP		 2224 case MSR_AMD64_NB_CFG:
2225 case MSR_IA32_UCODE_REV:
2226 case MSR_IA32_UCODE_WRITE:
2227 case MSR_VM_HSAVE_PA:
2228 case MSR_AMD64_PATCH_LOADER:
2229 case MSR_AMD64_BU_CFG2:
405a353a 2230 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2231 break;
2232
15c4a640 2233 case MSR_EFER:
b69e8cae 2234 return set_efer(vcpu, data);
8f1589d9
AP		 2235 case MSR_K7_HWCR:
2236 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2237 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2238 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2239 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2240 if (data != 0) {
a737f256
CD		 2241 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2242 data);
8f1589d9
AP		 2243 return 1;
2244 }
15c4a640 2245 break;
f7c6d140
AP		 2246 case MSR_FAM10H_MMIO_CONF_BASE:
2247 if (data != 0) {
a737f256
CD		 2248 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2249 "0x%llx\n", data);
f7c6d140
AP		 2250 return 1;
2251 }
15c4a640 2252 break;
b5e2fec0
AG		 2253 case MSR_IA32_DEBUGCTLMSR:
2254 if (!data) {
2255 /* We support the non-activated case already */
2256 break;
2257 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2258 /* Values other than LBR and BTF are vendor-specific,
2259 thus reserved and should throw a #GP */
2260 return 1;
2261 }
a737f256
CD		 2262 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2263 __func__, data);
b5e2fec0 2264 break;
9ba075a6 2265 case 0x200 ... 0x2ff:
ff53604b 2266 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2267 case MSR_IA32_APICBASE:
58cb628d 2268 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2269 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2270 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2271 case MSR_IA32_TSCDEADLINE:
2272 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2273 break;
ba904635 2274 case MSR_IA32_TSC_ADJUST:
d6321d49 2275 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2276 if (!msr_info->host_initiated) {
d913b904 2277 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2278 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2279 }
2280 vcpu->arch.ia32_tsc_adjust_msr = data;
2281 }
2282 break;
15c4a640 2283 case MSR_IA32_MISC_ENABLE:
ad312c7c 2284 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2285 break;
64d60670
PB		 2286 case MSR_IA32_SMBASE:
2287 if (!msr_info->host_initiated)
2288 return 1;
2289 vcpu->arch.smbase = data;
2290 break;
52797bf9
LA		 2291 case MSR_SMI_COUNT:
2292 if (!msr_info->host_initiated)
2293 return 1;
2294 vcpu->arch.smi_count = data;
2295 break;
11c6bffa 2296 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2297 case MSR_KVM_WALL_CLOCK:
2298 vcpu->kvm->arch.wall_clock = data;
2299 kvm_write_wall_clock(vcpu->kvm, data);
2300 break;
11c6bffa 2301 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2302 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2303 struct kvm_arch *ka = &vcpu->kvm->arch;
2304
12f9a48f 2305 kvmclock_reset(vcpu);
18068523 2306
54750f2c
MT		 2307 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2308 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2309
2310 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2311 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2312
2313 ka->boot_vcpu_runs_old_kvmclock = tmp;
2314 }
2315
18068523 2316 vcpu->arch.time = data;
0061d53d 2317 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2318
2319 /* we verify if the enable bit is set... */
2320 if (!(data & 1))
2321 break;
2322
4e335d9e 2323 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2324 &vcpu->arch.pv_time, data & ~1ULL,
2325 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2326 vcpu->arch.pv_time_enabled = false;
2327 else
2328 vcpu->arch.pv_time_enabled = true;
32cad84f 2329
18068523
GOC		 2330 break;
2331 }
344d9588
GN		 2332 case MSR_KVM_ASYNC_PF_EN:
2333 if (kvm_pv_enable_async_pf(vcpu, data))
2334 return 1;
2335 break;
c9aaa895
GC		 2336 case MSR_KVM_STEAL_TIME:
2337
2338 if (unlikely(!sched_info_on()))
2339 return 1;
2340
2341 if (data & KVM_STEAL_RESERVED_MASK)
2342 return 1;
2343
4e335d9e 2344 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2345 data & KVM_STEAL_VALID_BITS,
2346 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2347 return 1;
2348
2349 vcpu->arch.st.msr_val = data;
2350
2351 if (!(data & KVM_MSR_ENABLED))
2352 break;
2353
c9aaa895
GC		 2354 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2355
2356 break;
ae7a2a3f
MT		 2357 case MSR_KVM_PV_EOI_EN:
2358 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2359 return 1;
2360 break;
c9aaa895 2361
890ca9ae
HY		 2362 case MSR_IA32_MCG_CTL:
2363 case MSR_IA32_MCG_STATUS:
81760dcc 2364 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2365 return set_msr_mce(vcpu, msr_info);
71db6023 2366
6912ac32
WH		 2367 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2368 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2369 pr = true; /* fall through */
2370 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2371 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2372 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2373 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2374
2375 if (pr || data != 0)
a737f256
CD		 2376 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2377 "0x%x data 0x%llx\n", msr, data);
5753785f 2378 break;
84e0cefa
JS		 2379 case MSR_K7_CLK_CTL:
2380 /*
2381 * Ignore all writes to this no longer documented MSR.
2382 * Writes are only relevant for old K7 processors,
2383 * all pre-dating SVM, but a recommended workaround from
4a969980 2384 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2385 * affected processor models on the command line, hence
2386 * the need to ignore the workaround.
2387 */
2388 break;
55cd8e5a 2389 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2390 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2391 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2392 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2393 return kvm_hv_set_msr_common(vcpu, msr, data,
2394 msr_info->host_initiated);
91c9c3ed 2395 case MSR_IA32_BBL_CR_CTL3:
2396 /* Drop writes to this legacy MSR -- see rdmsr
2397 * counterpart for further detail.
2398 */
fab0aa3b
EM		 2399 if (report_ignored_msrs)
2400 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2401 msr, data);
91c9c3ed 2402 break;
2b036c6b 2403 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2404 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2405 return 1;
2406 vcpu->arch.osvw.length = data;
2407 break;
2408 case MSR_AMD64_OSVW_STATUS:
d6321d49 2409 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2410 return 1;
2411 vcpu->arch.osvw.status = data;
2412 break;
db2336a8
KH		 2413 case MSR_PLATFORM_INFO:
2414 if (!msr_info->host_initiated ||
2415 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2416 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2417 cpuid_fault_enabled(vcpu)))
2418 return 1;
2419 vcpu->arch.msr_platform_info = data;
2420 break;
2421 case MSR_MISC_FEATURES_ENABLES:
2422 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2423 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2424 !supports_cpuid_fault(vcpu)))
2425 return 1;
2426 vcpu->arch.msr_misc_features_enables = data;
2427 break;
15c4a640 2428 default:
ffde22ac
ES		 2429 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2430 return xen_hvm_config(vcpu, data);
c6702c9d 2431 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2432 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2433 if (!ignore_msrs) {
ae0f5499 2434 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2435 msr, data);
ed85c068
AP		 2436 return 1;
2437 } else {
fab0aa3b
EM		 2438 if (report_ignored_msrs)
2439 vcpu_unimpl(vcpu,
2440 "ignored wrmsr: 0x%x data 0x%llx\n",
2441 msr, data);
ed85c068
AP		 2442 break;
2443 }
15c4a640
CO		 2444 }
2445 return 0;
2446}
2447EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2448
2449
2450/*
2451 * Reads an msr value (of 'msr_index') into 'pdata'.
2452 * Returns 0 on success, non-0 otherwise.
2453 * Assumes vcpu_load() was already called.
2454 */
609e36d3 2455int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2456{
609e36d3 2457 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2458}
ff651cb6 2459EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2460
890ca9ae 2461static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2462{
2463 u64 data;
890ca9ae
HY		 2464 u64 mcg_cap = vcpu->arch.mcg_cap;
2465 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2466
2467 switch (msr) {
15c4a640
CO		 2468 case MSR_IA32_P5_MC_ADDR:
2469 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2470 data = 0;
2471 break;
15c4a640 2472 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2473 data = vcpu->arch.mcg_cap;
2474 break;
c7ac679c 2475 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2476 if (!(mcg_cap & MCG_CTL_P))
2477 return 1;
2478 data = vcpu->arch.mcg_ctl;
2479 break;
2480 case MSR_IA32_MCG_STATUS:
2481 data = vcpu->arch.mcg_status;
2482 break;
2483 default:
2484 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2485 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2486 u32 offset = msr - MSR_IA32_MC0_CTL;
2487 data = vcpu->arch.mce_banks[offset];
2488 break;
2489 }
2490 return 1;
2491 }
2492 *pdata = data;
2493 return 0;
2494}
2495
609e36d3 2496int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2497{
609e36d3 2498 switch (msr_info->index) {
890ca9ae 2499 case MSR_IA32_PLATFORM_ID:
15c4a640 2500 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2501 case MSR_IA32_DEBUGCTLMSR:
2502 case MSR_IA32_LASTBRANCHFROMIP:
2503 case MSR_IA32_LASTBRANCHTOIP:
2504 case MSR_IA32_LASTINTFROMIP:
2505 case MSR_IA32_LASTINTTOIP:
60af2ecd 2506 case MSR_K8_SYSCFG:
3afb1121
PB		 2507 case MSR_K8_TSEG_ADDR:
2508 case MSR_K8_TSEG_MASK:
60af2ecd 2509 case MSR_K7_HWCR:
61a6bd67 2510 case MSR_VM_HSAVE_PA:
1fdbd48c 2511 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2512 case MSR_AMD64_NB_CFG:
f7c6d140 2513 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2514 case MSR_AMD64_BU_CFG2:
0c2df2a1 2515 case MSR_IA32_PERF_CTL:
405a353a 2516 case MSR_AMD64_DC_CFG:
609e36d3 2517 msr_info->data = 0;
15c4a640 2518 break;
6912ac32
WH		 2519 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2520 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2521 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2522 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2523 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2524 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2525 msr_info->data = 0;
5753785f 2526 break;
742bc670 2527 case MSR_IA32_UCODE_REV:
609e36d3 2528 msr_info->data = 0x100000000ULL;
742bc670 2529 break;
9ba075a6 2530 case MSR_MTRRcap:
9ba075a6 2531 case 0x200 ... 0x2ff:
ff53604b 2532 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2533 case 0xcd: /* fsb frequency */
609e36d3 2534 msr_info->data = 3;
15c4a640 2535 break;
7b914098
JS		 2536 /*
2537 * MSR_EBC_FREQUENCY_ID
2538 * Conservative value valid for even the basic CPU models.
2539 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2540 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2541 * and 266MHz for model 3, or 4. Set Core Clock
2542 * Frequency to System Bus Frequency Ratio to 1 (bits
2543 * 31:24) even though these are only valid for CPU
2544 * models > 2, however guests may end up dividing or
2545 * multiplying by zero otherwise.
2546 */
2547 case MSR_EBC_FREQUENCY_ID:
609e36d3 2548 msr_info->data = 1 << 24;
7b914098 2549 break;
15c4a640 2550 case MSR_IA32_APICBASE:
609e36d3 2551 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2552 break;
0105d1a5 2553 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2554 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2555 break;
a3e06bbe 2556 case MSR_IA32_TSCDEADLINE:
609e36d3 2557 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2558 break;
ba904635 2559 case MSR_IA32_TSC_ADJUST:
609e36d3 2560 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2561 break;
15c4a640 2562 case MSR_IA32_MISC_ENABLE:
609e36d3 2563 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2564 break;
64d60670
PB		 2565 case MSR_IA32_SMBASE:
2566 if (!msr_info->host_initiated)
2567 return 1;
2568 msr_info->data = vcpu->arch.smbase;
15c4a640 2569 break;
52797bf9
LA		 2570 case MSR_SMI_COUNT:
2571 msr_info->data = vcpu->arch.smi_count;
2572 break;
847f0ad8
AG		 2573 case MSR_IA32_PERF_STATUS:
2574 /* TSC increment by tick */
609e36d3 2575 msr_info->data = 1000ULL;
847f0ad8 2576 /* CPU multiplier */
b0996ae4 2577 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2578 break;
15c4a640 2579 case MSR_EFER:
609e36d3 2580 msr_info->data = vcpu->arch.efer;
15c4a640 2581 break;
18068523 2582 case MSR_KVM_WALL_CLOCK:
11c6bffa 2583 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2584 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2585 break;
2586 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2587 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2588 msr_info->data = vcpu->arch.time;
18068523 2589 break;
344d9588 2590 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2591 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2592 break;
c9aaa895 2593 case MSR_KVM_STEAL_TIME:
609e36d3 2594 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2595 break;
1d92128f 2596 case MSR_KVM_PV_EOI_EN:
609e36d3 2597 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2598 break;
890ca9ae
HY		 2599 case MSR_IA32_P5_MC_ADDR:
2600 case MSR_IA32_P5_MC_TYPE:
2601 case MSR_IA32_MCG_CAP:
2602 case MSR_IA32_MCG_CTL:
2603 case MSR_IA32_MCG_STATUS:
81760dcc 2604 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2605 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2606 case MSR_K7_CLK_CTL:
2607 /*
2608 * Provide expected ramp-up count for K7. All other
2609 * are set to zero, indicating minimum divisors for
2610 * every field.
2611 *
2612 * This prevents guest kernels on AMD host with CPU
2613 * type 6, model 8 and higher from exploding due to
2614 * the rdmsr failing.
2615 */
609e36d3 2616 msr_info->data = 0x20000000;
84e0cefa 2617 break;
55cd8e5a 2618 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2619 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2620 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2621 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2622 return kvm_hv_get_msr_common(vcpu,
2623 msr_info->index, &msr_info->data);
55cd8e5a 2624 break;
91c9c3ed 2625 case MSR_IA32_BBL_CR_CTL3:
2626 /* This legacy MSR exists but isn't fully documented in current
2627 * silicon. It is however accessed by winxp in very narrow
2628 * scenarios where it sets bit #19, itself documented as
2629 * a "reserved" bit. Best effort attempt to source coherent
2630 * read data here should the balance of the register be
2631 * interpreted by the guest:
2632 *
2633 * L2 cache control register 3: 64GB range, 256KB size,
2634 * enabled, latency 0x1, configured
2635 */
609e36d3 2636 msr_info->data = 0xbe702111;
91c9c3ed 2637 break;
2b036c6b 2638 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2639 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2640 return 1;
609e36d3 2641 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2642 break;
2643 case MSR_AMD64_OSVW_STATUS:
d6321d49 2644 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2645 return 1;
609e36d3 2646 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2647 break;
db2336a8
KH		 2648 case MSR_PLATFORM_INFO:
2649 msr_info->data = vcpu->arch.msr_platform_info;
2650 break;
2651 case MSR_MISC_FEATURES_ENABLES:
2652 msr_info->data = vcpu->arch.msr_misc_features_enables;
2653 break;
15c4a640 2654 default:
c6702c9d 2655 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2656 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2657 if (!ignore_msrs) {
ae0f5499
BD		 2658 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2659 msr_info->index);
ed85c068
AP		 2660 return 1;
2661 } else {
fab0aa3b
EM		 2662 if (report_ignored_msrs)
2663 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2664 msr_info->index);
609e36d3 2665 msr_info->data = 0;
ed85c068
AP		 2666 }
2667 break;
15c4a640 2668 }
15c4a640
CO		 2669 return 0;
2670}
2671EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2672
313a3dc7
CO		 2673/*
2674 * Read or write a bunch of msrs. All parameters are kernel addresses.
2675 *
2676 * @return number of msrs set successfully.
2677 */
2678static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2679 struct kvm_msr_entry *entries,
2680 int (*do_msr)(struct kvm_vcpu *vcpu,
2681 unsigned index, u64 *data))
2682{
f656ce01 2683 int i, idx;
313a3dc7 2684
f656ce01 2685 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2686 for (i = 0; i < msrs->nmsrs; ++i)
2687 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2688 break;
f656ce01 2689 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2690
313a3dc7
CO		 2691 return i;
2692}
2693
2694/*
2695 * Read or write a bunch of msrs. Parameters are user addresses.
2696 *
2697 * @return number of msrs set successfully.
2698 */
2699static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2700 int (*do_msr)(struct kvm_vcpu *vcpu,
2701 unsigned index, u64 *data),
2702 int writeback)
2703{
2704 struct kvm_msrs msrs;
2705 struct kvm_msr_entry *entries;
2706 int r, n;
2707 unsigned size;
2708
2709 r = -EFAULT;
2710 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2711 goto out;
2712
2713 r = -E2BIG;
2714 if (msrs.nmsrs >= MAX_IO_MSRS)
2715 goto out;
2716
313a3dc7 2717 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2718 entries = memdup_user(user_msrs->entries, size);
2719 if (IS_ERR(entries)) {
2720 r = PTR_ERR(entries);
313a3dc7 2721 goto out;
ff5c2c03 2722 }
313a3dc7
CO		 2723
2724 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2725 if (r < 0)
2726 goto out_free;
2727
2728 r = -EFAULT;
2729 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2730 goto out_free;
2731
2732 r = n;
2733
2734out_free:
7a73c028 2735 kfree(entries);
313a3dc7
CO		 2736out:
2737 return r;
2738}
2739
784aa3d7 2740int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2741{
2742 int r;
2743
2744 switch (ext) {
2745 case KVM_CAP_IRQCHIP:
2746 case KVM_CAP_HLT:
2747 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2748 case KVM_CAP_SET_TSS_ADDR:
07716717 2749 case KVM_CAP_EXT_CPUID:
9c15bb1d 2750 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2751 case KVM_CAP_CLOCKSOURCE:
7837699f 2752 case KVM_CAP_PIT:
a28e4f5a 2753 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2754 case KVM_CAP_MP_STATE:
ed848624 2755 case KVM_CAP_SYNC_MMU:
a355c85c 2756 case KVM_CAP_USER_NMI:
52d939a0 2757 case KVM_CAP_REINJECT_CONTROL:
4925663a 2758 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2759 case KVM_CAP_IOEVENTFD:
f848a5a8 2760 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2761 case KVM_CAP_PIT2:
e9f42757 2762 case KVM_CAP_PIT_STATE2:
b927a3ce 2763 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2764 case KVM_CAP_XEN_HVM:
3cfc3092 2765 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2766 case KVM_CAP_HYPERV:
10388a07 2767 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2768 case KVM_CAP_HYPERV_SPIN:
5c919412 2769 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2770 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2771 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2772 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2773 case KVM_CAP_DEBUGREGS:
d2be1651 2774 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2775 case KVM_CAP_XSAVE:
344d9588 2776 case KVM_CAP_ASYNC_PF:
92a1f12d 2777 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2778 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2779 case KVM_CAP_READONLY_MEM:
5f66b620 2780 case KVM_CAP_HYPERV_TIME:
100943c5 2781 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2782 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2783 case KVM_CAP_ENABLE_CAP_VM:
2784 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2785 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2786 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2787 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2788 r = 1;
2789 break;
e3fd9a93
PB		 2790 case KVM_CAP_ADJUST_CLOCK:
2791 r = KVM_CLOCK_TSC_STABLE;
2792 break;
668fffa3
MT		 2793 case KVM_CAP_X86_GUEST_MWAIT:
2794 r = kvm_mwait_in_guest();
2795 break;
6d396b55
PB		 2796 case KVM_CAP_X86_SMM:
2797 /* SMBASE is usually relocated above 1M on modern chipsets,
2798 * and SMM handlers might indeed rely on 4G segment limits,
2799 * so do not report SMM to be available if real mode is
2800 * emulated via vm86 mode. Still, do not go to great lengths
2801 * to avoid userspace's usage of the feature, because it is a
2802 * fringe case that is not enabled except via specific settings
2803 * of the module parameters.
2804 */
2805 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2806 break;
774ead3a
AK		 2807 case KVM_CAP_VAPIC:
2808 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2809 break;
f725230a 2810 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2811 r = KVM_SOFT_MAX_VCPUS;
2812 break;
2813 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2814 r = KVM_MAX_VCPUS;
2815 break;
a988b910 2816 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2817 r = KVM_USER_MEM_SLOTS;
a988b910 2818 break;
a68a6a72
MT		 2819 case KVM_CAP_PV_MMU: /* obsolete */
2820 r = 0;
2f333bcb 2821 break;
890ca9ae
HY		 2822 case KVM_CAP_MCE:
2823 r = KVM_MAX_MCE_BANKS;
2824 break;
2d5b5a66 2825 case KVM_CAP_XCRS:
d366bf7e 2826 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2827 break;
92a1f12d
JR		 2828 case KVM_CAP_TSC_CONTROL:
2829 r = kvm_has_tsc_control;
2830 break;
37131313
RK		 2831 case KVM_CAP_X2APIC_API:
2832 r = KVM_X2APIC_API_VALID_FLAGS;
2833 break;
018d00d2
ZX		 2834 default:
2835 r = 0;
2836 break;
2837 }
2838 return r;
2839
2840}
2841
043405e1
CO		 2842long kvm_arch_dev_ioctl(struct file *filp,
2843 unsigned int ioctl, unsigned long arg)
2844{
2845 void __user *argp = (void __user *)arg;
2846 long r;
2847
2848 switch (ioctl) {
2849 case KVM_GET_MSR_INDEX_LIST: {
2850 struct kvm_msr_list __user *user_msr_list = argp;
2851 struct kvm_msr_list msr_list;
2852 unsigned n;
2853
2854 r = -EFAULT;
2855 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2856 goto out;
2857 n = msr_list.nmsrs;
62ef68bb 2858 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2859 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2860 goto out;
2861 r = -E2BIG;
e125e7b6 2862 if (n < msr_list.nmsrs)
043405e1
CO		 2863 goto out;
2864 r = -EFAULT;
2865 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2866 num_msrs_to_save * sizeof(u32)))
2867 goto out;
e125e7b6 2868 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2869 &emulated_msrs,
62ef68bb 2870 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2871 goto out;
2872 r = 0;
2873 break;
2874 }
9c15bb1d
BP		 2875 case KVM_GET_SUPPORTED_CPUID:
2876 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2877 struct kvm_cpuid2 __user *cpuid_arg = argp;
2878 struct kvm_cpuid2 cpuid;
2879
2880 r = -EFAULT;
2881 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2882 goto out;
9c15bb1d
BP		 2883
2884 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2885 ioctl);
674eea0f
AK		 2886 if (r)
2887 goto out;
2888
2889 r = -EFAULT;
2890 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2891 goto out;
2892 r = 0;
2893 break;
2894 }
890ca9ae 2895 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2896 r = -EFAULT;
c45dcc71
AR		 2897 if (copy_to_user(argp, &kvm_mce_cap_supported,
2898 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2899 goto out;
2900 r = 0;
2901 break;
2902 }
043405e1
CO		 2903 default:
2904 r = -EINVAL;
2905 }
2906out:
2907 return r;
2908}
2909
f5f48ee1
SY		 2910static void wbinvd_ipi(void *garbage)
2911{
2912 wbinvd();
2913}
2914
2915static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2916{
e0f0bbc5 2917 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2918}
2919
313a3dc7
CO		 2920void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2921{
f5f48ee1
SY		 2922 /* Address WBINVD may be executed by guest */
2923 if (need_emulate_wbinvd(vcpu)) {
2924 if (kvm_x86_ops->has_wbinvd_exit())
2925 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2926 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2927 smp_call_function_single(vcpu->cpu,
2928 wbinvd_ipi, NULL, 1);
2929 }
2930
313a3dc7 2931 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2932
0dd6a6ed
ZA		 2933 /* Apply any externally detected TSC adjustments (due to suspend) */
2934 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2935 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2936 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2937 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2938 }
8f6055cb 2939
b0c39dc6 2940 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 2941 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2942 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2943 if (tsc_delta < 0)
2944 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2945
b0c39dc6 2946 if (kvm_check_tsc_unstable()) {
07c1419a 2947 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2948 vcpu->arch.last_guest_tsc);
a545ab6a 2949 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2950 vcpu->arch.tsc_catchup = 1;
c285545f 2951 }
a749e247
PB		 2952
2953 if (kvm_lapic_hv_timer_in_use(vcpu))
2954 kvm_lapic_restart_hv_timer(vcpu);
2955
d98d07ca
MT		 2956 /*
2957 * On a host with synchronized TSC, there is no need to update
2958 * kvmclock on vcpu->cpu migration
2959 */
2960 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2961 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2962 if (vcpu->cpu != cpu)
1bd2009e 2963 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2964 vcpu->cpu = cpu;
6b7d7e76 2965 }
c9aaa895 2966
c9aaa895 2967 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2968}
2969
0b9f6c46
PX		 2970static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2971{
2972 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2973 return;
2974
fa55eedd 2975 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 2976
4e335d9e 2977 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2978 &vcpu->arch.st.steal.preempted,
2979 offsetof(struct kvm_steal_time, preempted),
2980 sizeof(vcpu->arch.st.steal.preempted));
2981}
2982
313a3dc7
CO		 2983void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2984{
cc0d907c 2985 int idx;
de63ad4c
LM		 2986
2987 if (vcpu->preempted)
2988 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2989
931f261b
AA		 2990 /*
2991 * Disable page faults because we're in atomic context here.
2992 * kvm_write_guest_offset_cached() would call might_fault()
2993 * that relies on pagefault_disable() to tell if there's a
2994 * bug. NOTE: the write to guest memory may not go through if
2995 * during postcopy live migration or if there's heavy guest
2996 * paging.
2997 */
2998 pagefault_disable();
cc0d907c
AA		 2999 /*
3000 * kvm_memslots() will be called by
3001 * kvm_write_guest_offset_cached() so take the srcu lock.
3002 */
3003 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3004 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3005 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3006 pagefault_enable();
02daab21 3007 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3008 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3009 /*
3010 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3011 * on every vmexit, but if not, we might have a stale dr6 from the
3012 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3013 */
3014 set_debugreg(0, 6);
313a3dc7
CO		 3015}
3016
313a3dc7
CO		 3017static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3018 struct kvm_lapic_state *s)
3019{
fa59cc00 3020 if (vcpu->arch.apicv_active)
d62caabb
AS		 3021 kvm_x86_ops->sync_pir_to_irr(vcpu);
3022
a92e2543 3023 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3024}
3025
3026static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3027 struct kvm_lapic_state *s)
3028{
a92e2543
RK		 3029 int r;
3030
3031 r = kvm_apic_set_state(vcpu, s);
3032 if (r)
3033 return r;
cb142eb7 3034 update_cr8_intercept(vcpu);
313a3dc7
CO		 3035
3036 return 0;
3037}
3038
127a457a
MG		 3039static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3040{
3041 return (!lapic_in_kernel(vcpu) ||
3042 kvm_apic_accept_pic_intr(vcpu));
3043}
3044
782d422b
MG		 3045/*
3046 * if userspace requested an interrupt window, check that the
3047 * interrupt window is open.
3048 *
3049 * No need to exit to userspace if we already have an interrupt queued.
3050 */
3051static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3052{
3053 return kvm_arch_interrupt_allowed(vcpu) &&
3054 !kvm_cpu_has_interrupt(vcpu) &&
3055 !kvm_event_needs_reinjection(vcpu) &&
3056 kvm_cpu_accept_dm_intr(vcpu);
3057}
3058
f77bc6a4
ZX		 3059static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3060 struct kvm_interrupt *irq)
3061{
02cdb50f 3062 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3063 return -EINVAL;
1c1a9ce9
SR		 3064
3065 if (!irqchip_in_kernel(vcpu->kvm)) {
3066 kvm_queue_interrupt(vcpu, irq->irq, false);
3067 kvm_make_request(KVM_REQ_EVENT, vcpu);
3068 return 0;
3069 }
3070
3071 /*
3072 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3073 * fail for in-kernel 8259.
3074 */
3075 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3076 return -ENXIO;
f77bc6a4 3077
1c1a9ce9
SR		 3078 if (vcpu->arch.pending_external_vector != -1)
3079 return -EEXIST;
f77bc6a4 3080
1c1a9ce9 3081 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3082 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3083 return 0;
3084}
3085
c4abb7c9
JK		 3086static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3087{
c4abb7c9 3088 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3089
3090 return 0;
3091}
3092
f077825a
PB		 3093static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3094{
64d60670
PB		 3095 kvm_make_request(KVM_REQ_SMI, vcpu);
3096
f077825a
PB		 3097 return 0;
3098}
3099
b209749f
AK		 3100static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3101 struct kvm_tpr_access_ctl *tac)
3102{
3103 if (tac->flags)
3104 return -EINVAL;
3105 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3106 return 0;
3107}
3108
890ca9ae
HY		 3109static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3110 u64 mcg_cap)
3111{
3112 int r;
3113 unsigned bank_num = mcg_cap & 0xff, bank;
3114
3115 r = -EINVAL;
a9e38c3e 3116 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3117 goto out;
c45dcc71 3118 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3119 goto out;
3120 r = 0;
3121 vcpu->arch.mcg_cap = mcg_cap;
3122 /* Init IA32_MCG_CTL to all 1s */
3123 if (mcg_cap & MCG_CTL_P)
3124 vcpu->arch.mcg_ctl = ~(u64)0;
3125 /* Init IA32_MCi_CTL to all 1s */
3126 for (bank = 0; bank < bank_num; bank++)
3127 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3128
3129 if (kvm_x86_ops->setup_mce)
3130 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3131out:
3132 return r;
3133}
3134
3135static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3136 struct kvm_x86_mce *mce)
3137{
3138 u64 mcg_cap = vcpu->arch.mcg_cap;
3139 unsigned bank_num = mcg_cap & 0xff;
3140 u64 *banks = vcpu->arch.mce_banks;
3141
3142 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3143 return -EINVAL;
3144 /*
3145 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3146 * reporting is disabled
3147 */
3148 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3149 vcpu->arch.mcg_ctl != ~(u64)0)
3150 return 0;
3151 banks += 4 * mce->bank;
3152 /*
3153 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3154 * reporting is disabled for the bank
3155 */
3156 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3157 return 0;
3158 if (mce->status & MCI_STATUS_UC) {
3159 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3160 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3161 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3162 return 0;
3163 }
3164 if (banks[1] & MCI_STATUS_VAL)
3165 mce->status |= MCI_STATUS_OVER;
3166 banks[2] = mce->addr;
3167 banks[3] = mce->misc;
3168 vcpu->arch.mcg_status = mce->mcg_status;
3169 banks[1] = mce->status;
3170 kvm_queue_exception(vcpu, MC_VECTOR);
3171 } else if (!(banks[1] & MCI_STATUS_VAL)
3172 || !(banks[1] & MCI_STATUS_UC)) {
3173 if (banks[1] & MCI_STATUS_VAL)
3174 mce->status |= MCI_STATUS_OVER;
3175 banks[2] = mce->addr;
3176 banks[3] = mce->misc;
3177 banks[1] = mce->status;
3178 } else
3179 banks[1] |= MCI_STATUS_OVER;
3180 return 0;
3181}
3182
3cfc3092
JK		 3183static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3184 struct kvm_vcpu_events *events)
3185{
7460fb4a 3186 process_nmi(vcpu);
664f8e26
WL		 3187 /*
3188 * FIXME: pass injected and pending separately. This is only
3189 * needed for nested virtualization, whose state cannot be
3190 * migrated yet. For now we can combine them.
3191 */
03b82a30 3192 events->exception.injected =
664f8e26
WL		 3193 (vcpu->arch.exception.pending ||
3194 vcpu->arch.exception.injected) &&
03b82a30 3195 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3196 events->exception.nr = vcpu->arch.exception.nr;
3197 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3198 events->exception.pad = 0;
3cfc3092
JK		 3199 events->exception.error_code = vcpu->arch.exception.error_code;
3200
03b82a30
JK		 3201 events->interrupt.injected =
3202 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3203 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3204 events->interrupt.soft = 0;
37ccdcbe 3205 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3206
3207 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3208 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3209 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3210 events->nmi.pad = 0;
3cfc3092 3211
66450a21 3212 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3213
f077825a
PB		 3214 events->smi.smm = is_smm(vcpu);
3215 events->smi.pending = vcpu->arch.smi_pending;
3216 events->smi.smm_inside_nmi =
3217 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3218 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3219
dab4b911 3220 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3221 | KVM_VCPUEVENT_VALID_SHADOW
3222 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3223 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3224}
3225
6ef4e07e
XG		 3226static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3227
3cfc3092
JK		 3228static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3229 struct kvm_vcpu_events *events)
3230{
dab4b911 3231 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3232 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3233 | KVM_VCPUEVENT_VALID_SHADOW
3234 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3235 return -EINVAL;
3236
78e546c8 3237 if (events->exception.injected &&
28d06353
JM		 3238 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3239 is_guest_mode(vcpu)))
78e546c8
PB		 3240 return -EINVAL;
3241
28bf2888
DH		 3242 /* INITs are latched while in SMM */
3243 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3244 (events->smi.smm || events->smi.pending) &&
3245 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3246 return -EINVAL;
3247
7460fb4a 3248 process_nmi(vcpu);
664f8e26 3249 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3250 vcpu->arch.exception.pending = events->exception.injected;
3251 vcpu->arch.exception.nr = events->exception.nr;
3252 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3253 vcpu->arch.exception.error_code = events->exception.error_code;
3254
3255 vcpu->arch.interrupt.pending = events->interrupt.injected;
3256 vcpu->arch.interrupt.nr = events->interrupt.nr;
3257 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3258 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3259 kvm_x86_ops->set_interrupt_shadow(vcpu,
3260 events->interrupt.shadow);
3cfc3092
JK		 3261
3262 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3263 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3264 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3265 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3266
66450a21 3267 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3268 lapic_in_kernel(vcpu))
66450a21 3269 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3270
f077825a 3271 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3272 u32 hflags = vcpu->arch.hflags;
f077825a 3273 if (events->smi.smm)
6ef4e07e 3274 hflags |= HF_SMM_MASK;
f077825a 3275 else
6ef4e07e
XG		 3276 hflags &= ~HF_SMM_MASK;
3277 kvm_set_hflags(vcpu, hflags);
3278
f077825a 3279 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3280
3281 if (events->smi.smm) {
3282 if (events->smi.smm_inside_nmi)
3283 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3284 else
f4ef1910
WL		 3285 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3286 if (lapic_in_kernel(vcpu)) {
3287 if (events->smi.latched_init)
3288 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3289 else
3290 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3291 }
f077825a
PB		 3292 }
3293 }
3294
3842d135
AK		 3295 kvm_make_request(KVM_REQ_EVENT, vcpu);
3296
3cfc3092
JK		 3297 return 0;
3298}
3299
a1efbe77
JK		 3300static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3301 struct kvm_debugregs *dbgregs)
3302{
73aaf249
JK		 3303 unsigned long val;
3304
a1efbe77 3305 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3306 kvm_get_dr(vcpu, 6, &val);
73aaf249 3307 dbgregs->dr6 = val;
a1efbe77
JK		 3308 dbgregs->dr7 = vcpu->arch.dr7;
3309 dbgregs->flags = 0;
97e69aa6 3310 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3311}
3312
3313static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3314 struct kvm_debugregs *dbgregs)
3315{
3316 if (dbgregs->flags)
3317 return -EINVAL;
3318
d14bdb55
PB		 3319 if (dbgregs->dr6 & ~0xffffffffull)
3320 return -EINVAL;
3321 if (dbgregs->dr7 & ~0xffffffffull)
3322 return -EINVAL;
3323
a1efbe77 3324 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3325 kvm_update_dr0123(vcpu);
a1efbe77 3326 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3327 kvm_update_dr6(vcpu);
a1efbe77 3328 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3329 kvm_update_dr7(vcpu);
a1efbe77 3330
a1efbe77
JK		 3331 return 0;
3332}
3333
df1daba7
PB		 3334#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3335
3336static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3337{
c47ada30 3338 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3339 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3340 u64 valid;
3341
3342 /*
3343 * Copy legacy XSAVE area, to avoid complications with CPUID
3344 * leaves 0 and 1 in the loop below.
3345 */
3346 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3347
3348 /* Set XSTATE_BV */
00c87e9a 3349 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3350 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3351
3352 /*
3353 * Copy each region from the possibly compacted offset to the
3354 * non-compacted offset.
3355 */
d91cab78 3356 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3357 while (valid) {
3358 u64 feature = valid & -valid;
3359 int index = fls64(feature) - 1;
3360 void *src = get_xsave_addr(xsave, feature);
3361
3362 if (src) {
3363 u32 size, offset, ecx, edx;
3364 cpuid_count(XSTATE_CPUID, index,
3365 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3366 if (feature == XFEATURE_MASK_PKRU)
3367 memcpy(dest + offset, &vcpu->arch.pkru,
3368 sizeof(vcpu->arch.pkru));
3369 else
3370 memcpy(dest + offset, src, size);
3371
df1daba7
PB		 3372 }
3373
3374 valid -= feature;
3375 }
3376}
3377
3378static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3379{
c47ada30 3380 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3381 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3382 u64 valid;
3383
3384 /*
3385 * Copy legacy XSAVE area, to avoid complications with CPUID
3386 * leaves 0 and 1 in the loop below.
3387 */
3388 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3389
3390 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3391 xsave->header.xfeatures = xstate_bv;
782511b0 3392 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3393 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3394
3395 /*
3396 * Copy each region from the non-compacted offset to the
3397 * possibly compacted offset.
3398 */
d91cab78 3399 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3400 while (valid) {
3401 u64 feature = valid & -valid;
3402 int index = fls64(feature) - 1;
3403 void *dest = get_xsave_addr(xsave, feature);
3404
3405 if (dest) {
3406 u32 size, offset, ecx, edx;
3407 cpuid_count(XSTATE_CPUID, index,
3408 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3409 if (feature == XFEATURE_MASK_PKRU)
3410 memcpy(&vcpu->arch.pkru, src + offset,
3411 sizeof(vcpu->arch.pkru));
3412 else
3413 memcpy(dest, src + offset, size);
ee4100da 3414 }
df1daba7
PB		 3415
3416 valid -= feature;
3417 }
3418}
3419
2d5b5a66
SY		 3420static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3421 struct kvm_xsave *guest_xsave)
3422{
d366bf7e 3423 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3424 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3425 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3426 } else {
2d5b5a66 3427 memcpy(guest_xsave->region,
7366ed77 3428 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3429 sizeof(struct fxregs_state));
2d5b5a66 3430 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3431 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3432 }
3433}
3434
a575813b
WL		 3435#define XSAVE_MXCSR_OFFSET 24
3436
2d5b5a66
SY		 3437static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3438 struct kvm_xsave *guest_xsave)
3439{
3440 u64 xstate_bv =
3441 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3442 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3443
d366bf7e 3444 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3445 /*
3446 * Here we allow setting states that are not present in
3447 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3448 * with old userspace.
3449 */
a575813b
WL		 3450 if (xstate_bv & ~kvm_supported_xcr0() ||
3451 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3452 return -EINVAL;
df1daba7 3453 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3454 } else {
a575813b
WL		 3455 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3456 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3457 return -EINVAL;
7366ed77 3458 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3459 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3460 }
3461 return 0;
3462}
3463
3464static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3465 struct kvm_xcrs *guest_xcrs)
3466{
d366bf7e 3467 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3468 guest_xcrs->nr_xcrs = 0;
3469 return;
3470 }
3471
3472 guest_xcrs->nr_xcrs = 1;
3473 guest_xcrs->flags = 0;
3474 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3475 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3476}
3477
3478static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3479 struct kvm_xcrs *guest_xcrs)
3480{
3481 int i, r = 0;
3482
d366bf7e 3483 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3484 return -EINVAL;
3485
3486 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3487 return -EINVAL;
3488
3489 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3490 /* Only support XCR0 currently */
c67a04cb 3491 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3492 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3493 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3494 break;
3495 }
3496 if (r)
3497 r = -EINVAL;
3498 return r;
3499}
3500
1c0b28c2
EM		 3501/*
3502 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3503 * stopped by the hypervisor. This function will be called from the host only.
3504 * EINVAL is returned when the host attempts to set the flag for a guest that
3505 * does not support pv clocks.
3506 */
3507static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3508{
0b79459b 3509 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3510 return -EINVAL;
51d59c6b 3511 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3512 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3513 return 0;
3514}
3515
5c919412
AS		 3516static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3517 struct kvm_enable_cap *cap)
3518{
3519 if (cap->flags)
3520 return -EINVAL;
3521
3522 switch (cap->cap) {
efc479e6
RK		 3523 case KVM_CAP_HYPERV_SYNIC2:
3524 if (cap->args[0])
3525 return -EINVAL;
5c919412 3526 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3527 if (!irqchip_in_kernel(vcpu->kvm))
3528 return -EINVAL;
efc479e6
RK		 3529 return kvm_hv_activate_synic(vcpu, cap->cap ==
3530 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3531 default:
3532 return -EINVAL;
3533 }
3534}
3535
313a3dc7
CO		 3536long kvm_arch_vcpu_ioctl(struct file *filp,
3537 unsigned int ioctl, unsigned long arg)
3538{
3539 struct kvm_vcpu *vcpu = filp->private_data;
3540 void __user *argp = (void __user *)arg;
3541 int r;
d1ac91d8
AK		 3542 union {
3543 struct kvm_lapic_state *lapic;
3544 struct kvm_xsave *xsave;
3545 struct kvm_xcrs *xcrs;
3546 void *buffer;
3547 } u;
3548
9b062471
CD		 3549 vcpu_load(vcpu);
3550
d1ac91d8 3551 u.buffer = NULL;
313a3dc7
CO		 3552 switch (ioctl) {
3553 case KVM_GET_LAPIC: {
2204ae3c 3554 r = -EINVAL;
bce87cce 3555 if (!lapic_in_kernel(vcpu))
2204ae3c 3556 goto out;
d1ac91d8 3557 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3558
b772ff36 3559 r = -ENOMEM;
d1ac91d8 3560 if (!u.lapic)
b772ff36 3561 goto out;
d1ac91d8 3562 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3563 if (r)
3564 goto out;
3565 r = -EFAULT;
d1ac91d8 3566 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3567 goto out;
3568 r = 0;
3569 break;
3570 }
3571 case KVM_SET_LAPIC: {
2204ae3c 3572 r = -EINVAL;
bce87cce 3573 if (!lapic_in_kernel(vcpu))
2204ae3c 3574 goto out;
ff5c2c03 3575 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3576 if (IS_ERR(u.lapic)) {
3577 r = PTR_ERR(u.lapic);
3578 goto out_nofree;
3579 }
ff5c2c03 3580
d1ac91d8 3581 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3582 break;
3583 }
f77bc6a4
ZX		 3584 case KVM_INTERRUPT: {
3585 struct kvm_interrupt irq;
3586
3587 r = -EFAULT;
3588 if (copy_from_user(&irq, argp, sizeof irq))
3589 goto out;
3590 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3591 break;
3592 }
c4abb7c9
JK		 3593 case KVM_NMI: {
3594 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3595 break;
3596 }
f077825a
PB		 3597 case KVM_SMI: {
3598 r = kvm_vcpu_ioctl_smi(vcpu);
3599 break;
3600 }
313a3dc7
CO		 3601 case KVM_SET_CPUID: {
3602 struct kvm_cpuid __user *cpuid_arg = argp;
3603 struct kvm_cpuid cpuid;
3604
3605 r = -EFAULT;
3606 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3607 goto out;
3608 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3609 break;
3610 }
07716717
DK		 3611 case KVM_SET_CPUID2: {
3612 struct kvm_cpuid2 __user *cpuid_arg = argp;
3613 struct kvm_cpuid2 cpuid;
3614
3615 r = -EFAULT;
3616 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3617 goto out;
3618 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3619 cpuid_arg->entries);
07716717
DK		 3620 break;
3621 }
3622 case KVM_GET_CPUID2: {
3623 struct kvm_cpuid2 __user *cpuid_arg = argp;
3624 struct kvm_cpuid2 cpuid;
3625
3626 r = -EFAULT;
3627 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3628 goto out;
3629 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3630 cpuid_arg->entries);
07716717
DK		 3631 if (r)
3632 goto out;
3633 r = -EFAULT;
3634 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3635 goto out;
3636 r = 0;
3637 break;
3638 }
313a3dc7 3639 case KVM_GET_MSRS:
609e36d3 3640 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3641 break;
3642 case KVM_SET_MSRS:
3643 r = msr_io(vcpu, argp, do_set_msr, 0);
3644 break;
b209749f
AK		 3645 case KVM_TPR_ACCESS_REPORTING: {
3646 struct kvm_tpr_access_ctl tac;
3647
3648 r = -EFAULT;
3649 if (copy_from_user(&tac, argp, sizeof tac))
3650 goto out;
3651 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3652 if (r)
3653 goto out;
3654 r = -EFAULT;
3655 if (copy_to_user(argp, &tac, sizeof tac))
3656 goto out;
3657 r = 0;
3658 break;
3659 };
b93463aa
AK		 3660 case KVM_SET_VAPIC_ADDR: {
3661 struct kvm_vapic_addr va;
7301d6ab 3662 int idx;
b93463aa
AK		 3663
3664 r = -EINVAL;
35754c98 3665 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3666 goto out;
3667 r = -EFAULT;
3668 if (copy_from_user(&va, argp, sizeof va))
3669 goto out;
7301d6ab 3670 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3671 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3672 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3673 break;
3674 }
890ca9ae
HY		 3675 case KVM_X86_SETUP_MCE: {
3676 u64 mcg_cap;
3677
3678 r = -EFAULT;
3679 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3680 goto out;
3681 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3682 break;
3683 }
3684 case KVM_X86_SET_MCE: {
3685 struct kvm_x86_mce mce;
3686
3687 r = -EFAULT;
3688 if (copy_from_user(&mce, argp, sizeof mce))
3689 goto out;
3690 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3691 break;
3692 }
3cfc3092
JK		 3693 case KVM_GET_VCPU_EVENTS: {
3694 struct kvm_vcpu_events events;
3695
3696 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3697
3698 r = -EFAULT;
3699 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3700 break;
3701 r = 0;
3702 break;
3703 }
3704 case KVM_SET_VCPU_EVENTS: {
3705 struct kvm_vcpu_events events;
3706
3707 r = -EFAULT;
3708 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3709 break;
3710
3711 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3712 break;
3713 }
a1efbe77
JK		 3714 case KVM_GET_DEBUGREGS: {
3715 struct kvm_debugregs dbgregs;
3716
3717 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3718
3719 r = -EFAULT;
3720 if (copy_to_user(argp, &dbgregs,
3721 sizeof(struct kvm_debugregs)))
3722 break;
3723 r = 0;
3724 break;
3725 }
3726 case KVM_SET_DEBUGREGS: {
3727 struct kvm_debugregs dbgregs;
3728
3729 r = -EFAULT;
3730 if (copy_from_user(&dbgregs, argp,
3731 sizeof(struct kvm_debugregs)))
3732 break;
3733
3734 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3735 break;
3736 }
2d5b5a66 3737 case KVM_GET_XSAVE: {
d1ac91d8 3738 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3739 r = -ENOMEM;
d1ac91d8 3740 if (!u.xsave)
2d5b5a66
SY		 3741 break;
3742
d1ac91d8 3743 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3744
3745 r = -EFAULT;
d1ac91d8 3746 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3747 break;
3748 r = 0;
3749 break;
3750 }
3751 case KVM_SET_XSAVE: {
ff5c2c03 3752 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3753 if (IS_ERR(u.xsave)) {
3754 r = PTR_ERR(u.xsave);
3755 goto out_nofree;
3756 }
2d5b5a66 3757
d1ac91d8 3758 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3759 break;
3760 }
3761 case KVM_GET_XCRS: {
d1ac91d8 3762 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3763 r = -ENOMEM;
d1ac91d8 3764 if (!u.xcrs)
2d5b5a66
SY		 3765 break;
3766
d1ac91d8 3767 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3768
3769 r = -EFAULT;
d1ac91d8 3770 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3771 sizeof(struct kvm_xcrs)))
3772 break;
3773 r = 0;
3774 break;
3775 }
3776 case KVM_SET_XCRS: {
ff5c2c03 3777 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3778 if (IS_ERR(u.xcrs)) {
3779 r = PTR_ERR(u.xcrs);
3780 goto out_nofree;
3781 }
2d5b5a66 3782
d1ac91d8 3783 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3784 break;
3785 }
92a1f12d
JR		 3786 case KVM_SET_TSC_KHZ: {
3787 u32 user_tsc_khz;
3788
3789 r = -EINVAL;
92a1f12d
JR		 3790 user_tsc_khz = (u32)arg;
3791
3792 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3793 goto out;
3794
cc578287
ZA		 3795 if (user_tsc_khz == 0)
3796 user_tsc_khz = tsc_khz;
3797
381d585c
HZ		 3798 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3799 r = 0;
92a1f12d 3800
92a1f12d
JR		 3801 goto out;
3802 }
3803 case KVM_GET_TSC_KHZ: {
cc578287 3804 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3805 goto out;
3806 }
1c0b28c2
EM		 3807 case KVM_KVMCLOCK_CTRL: {
3808 r = kvm_set_guest_paused(vcpu);
3809 goto out;
3810 }
5c919412
AS		 3811 case KVM_ENABLE_CAP: {
3812 struct kvm_enable_cap cap;
3813
3814 r = -EFAULT;
3815 if (copy_from_user(&cap, argp, sizeof(cap)))
3816 goto out;
3817 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3818 break;
3819 }
313a3dc7
CO		 3820 default:
3821 r = -EINVAL;
3822 }
3823out:
d1ac91d8 3824 kfree(u.buffer);
9b062471
CD		 3825out_nofree:
3826 vcpu_put(vcpu);
313a3dc7
CO		 3827 return r;
3828}
3829
5b1c1493
CO		 3830int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3831{
3832 return VM_FAULT_SIGBUS;
3833}
3834
1fe779f8
CO		 3835static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3836{
3837 int ret;
3838
3839 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3840 return -EINVAL;
1fe779f8
CO		 3841 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3842 return ret;
3843}
3844
b927a3ce
SY		 3845static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3846 u64 ident_addr)
3847{
3848 kvm->arch.ept_identity_map_addr = ident_addr;
3849 return 0;
3850}
3851
1fe779f8
CO		 3852static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3853 u32 kvm_nr_mmu_pages)
3854{
3855 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3856 return -EINVAL;
3857
79fac95e 3858 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3859
3860 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3861 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3862
79fac95e 3863 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3864 return 0;
3865}
3866
3867static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3868{
39de71ec 3869 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3870}
3871
1fe779f8
CO		 3872static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3873{
90bca052 3874 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3875 int r;
3876
3877 r = 0;
3878 switch (chip->chip_id) {
3879 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3880 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3881 sizeof(struct kvm_pic_state));
3882 break;
3883 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3884 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3885 sizeof(struct kvm_pic_state));
3886 break;
3887 case KVM_IRQCHIP_IOAPIC:
33392b49 3888 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3889 break;
3890 default:
3891 r = -EINVAL;
3892 break;
3893 }
3894 return r;
3895}
3896
3897static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3898{
90bca052 3899 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3900 int r;
3901
3902 r = 0;
3903 switch (chip->chip_id) {
3904 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3905 spin_lock(&pic->lock);
3906 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3907 sizeof(struct kvm_pic_state));
90bca052 3908 spin_unlock(&pic->lock);
1fe779f8
CO		 3909 break;
3910 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3911 spin_lock(&pic->lock);
3912 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3913 sizeof(struct kvm_pic_state));
90bca052 3914 spin_unlock(&pic->lock);
1fe779f8
CO		 3915 break;
3916 case KVM_IRQCHIP_IOAPIC:
33392b49 3917 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3918 break;
3919 default:
3920 r = -EINVAL;
3921 break;
3922 }
90bca052 3923 kvm_pic_update_irq(pic);
1fe779f8
CO		 3924 return r;
3925}
3926
e0f63cb9
SY		 3927static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3928{
34f3941c
RK		 3929 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3930
3931 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3932
3933 mutex_lock(&kps->lock);
3934 memcpy(ps, &kps->channels, sizeof(*ps));
3935 mutex_unlock(&kps->lock);
2da29bcc 3936 return 0;
e0f63cb9
SY		 3937}
3938
3939static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3940{
0185604c 3941 int i;
09edea72
RK		 3942 struct kvm_pit *pit = kvm->arch.vpit;
3943
3944 mutex_lock(&pit->pit_state.lock);
34f3941c 3945 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3946 for (i = 0; i < 3; i++)
09edea72
RK		 3947 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3948 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3949 return 0;
e9f42757
BK		 3950}
3951
3952static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3953{
e9f42757
BK		 3954 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3955 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3956 sizeof(ps->channels));
3957 ps->flags = kvm->arch.vpit->pit_state.flags;
3958 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3959 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3960 return 0;
e9f42757
BK		 3961}
3962
3963static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3964{
2da29bcc 3965 int start = 0;
0185604c 3966 int i;
e9f42757 3967 u32 prev_legacy, cur_legacy;
09edea72
RK		 3968 struct kvm_pit *pit = kvm->arch.vpit;
3969
3970 mutex_lock(&pit->pit_state.lock);
3971 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3972 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3973 if (!prev_legacy && cur_legacy)
3974 start = 1;
09edea72
RK		 3975 memcpy(&pit->pit_state.channels, &ps->channels,
3976 sizeof(pit->pit_state.channels));
3977 pit->pit_state.flags = ps->flags;
0185604c 3978 for (i = 0; i < 3; i++)
09edea72 3979 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3980 start && i == 0);
09edea72 3981 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3982 return 0;
e0f63cb9
SY		 3983}
3984
52d939a0
MT		 3985static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3986 struct kvm_reinject_control *control)
3987{
71474e2f
RK		 3988 struct kvm_pit *pit = kvm->arch.vpit;
3989
3990 if (!pit)
52d939a0 3991 return -ENXIO;
b39c90b6 3992
71474e2f
RK		 3993 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3994 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3995 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3996 */
3997 mutex_lock(&pit->pit_state.lock);
3998 kvm_pit_set_reinject(pit, control->pit_reinject);
3999 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4000
52d939a0
MT		 4001 return 0;
4002}
4003
95d4c16c 4004/**
60c34612
TY		 4005 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4006 * @kvm: kvm instance
4007 * @log: slot id and address to which we copy the log
95d4c16c 4008 *
e108ff2f
PB		 4009 * Steps 1-4 below provide general overview of dirty page logging. See
4010 * kvm_get_dirty_log_protect() function description for additional details.
4011 *
4012 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4013 * always flush the TLB (step 4) even if previous step failed and the dirty
4014 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4015 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4016 * writes will be marked dirty for next log read.
95d4c16c 4017 *
60c34612
TY		 4018 * 1. Take a snapshot of the bit and clear it if needed.
4019 * 2. Write protect the corresponding page.
e108ff2f
PB		 4020 * 3. Copy the snapshot to the userspace.
4021 * 4. Flush TLB's if needed.
5bb064dc 4022 */
60c34612 4023int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4024{
60c34612 4025 bool is_dirty = false;
e108ff2f 4026 int r;
5bb064dc 4027
79fac95e 4028 mutex_lock(&kvm->slots_lock);
5bb064dc 4029
88178fd4
KH		 4030 /*
4031 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4032 */
4033 if (kvm_x86_ops->flush_log_dirty)
4034 kvm_x86_ops->flush_log_dirty(kvm);
4035
e108ff2f 4036 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4037
4038 /*
4039 * All the TLBs can be flushed out of mmu lock, see the comments in
4040 * kvm_mmu_slot_remove_write_access().
4041 */
e108ff2f 4042 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4043 if (is_dirty)
4044 kvm_flush_remote_tlbs(kvm);
4045
79fac95e 4046 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4047 return r;
4048}
4049
aa2fbe6d
YZ		 4050int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4051 bool line_status)
23d43cf9
CD		 4052{
4053 if (!irqchip_in_kernel(kvm))
4054 return -ENXIO;
4055
4056 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4057 irq_event->irq, irq_event->level,
4058 line_status);
23d43cf9
CD		 4059 return 0;
4060}
4061
90de4a18
NA		 4062static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4063 struct kvm_enable_cap *cap)
4064{
4065 int r;
4066
4067 if (cap->flags)
4068 return -EINVAL;
4069
4070 switch (cap->cap) {
4071 case KVM_CAP_DISABLE_QUIRKS:
4072 kvm->arch.disabled_quirks = cap->args[0];
4073 r = 0;
4074 break;
49df6397
SR		 4075 case KVM_CAP_SPLIT_IRQCHIP: {
4076 mutex_lock(&kvm->lock);
b053b2ae
SR		 4077 r = -EINVAL;
4078 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4079 goto split_irqchip_unlock;
49df6397
SR		 4080 r = -EEXIST;
4081 if (irqchip_in_kernel(kvm))
4082 goto split_irqchip_unlock;
557abc40 4083 if (kvm->created_vcpus)
49df6397
SR		 4084 goto split_irqchip_unlock;
4085 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4086 if (r)
49df6397
SR		 4087 goto split_irqchip_unlock;
4088 /* Pairs with irqchip_in_kernel. */
4089 smp_wmb();
49776faf 4090 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4091 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4092 r = 0;
4093split_irqchip_unlock:
4094 mutex_unlock(&kvm->lock);
4095 break;
4096 }
37131313
RK		 4097 case KVM_CAP_X2APIC_API:
4098 r = -EINVAL;
4099 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4100 break;
4101
4102 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4103 kvm->arch.x2apic_format = true;
c519265f
RK		 4104 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4105 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4106
4107 r = 0;
4108 break;
90de4a18
NA		 4109 default:
4110 r = -EINVAL;
4111 break;
4112 }
4113 return r;
4114}
4115
1fe779f8
CO		 4116long kvm_arch_vm_ioctl(struct file *filp,
4117 unsigned int ioctl, unsigned long arg)
4118{
4119 struct kvm *kvm = filp->private_data;
4120 void __user *argp = (void __user *)arg;
367e1319 4121 int r = -ENOTTY;
f0d66275
DH		 4122 /*
4123 * This union makes it completely explicit to gcc-3.x
4124 * that these two variables' stack usage should be
4125 * combined, not added together.
4126 */
4127 union {
4128 struct kvm_pit_state ps;
e9f42757 4129 struct kvm_pit_state2 ps2;
c5ff41ce 4130 struct kvm_pit_config pit_config;
f0d66275 4131 } u;
1fe779f8
CO		 4132
4133 switch (ioctl) {
4134 case KVM_SET_TSS_ADDR:
4135 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4136 break;
b927a3ce
SY		 4137 case KVM_SET_IDENTITY_MAP_ADDR: {
4138 u64 ident_addr;
4139
1af1ac91
DH		 4140 mutex_lock(&kvm->lock);
4141 r = -EINVAL;
4142 if (kvm->created_vcpus)
4143 goto set_identity_unlock;
b927a3ce
SY		 4144 r = -EFAULT;
4145 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4146 goto set_identity_unlock;
b927a3ce 4147 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4148set_identity_unlock:
4149 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4150 break;
4151 }
1fe779f8
CO		 4152 case KVM_SET_NR_MMU_PAGES:
4153 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4154 break;
4155 case KVM_GET_NR_MMU_PAGES:
4156 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4157 break;
3ddea128 4158 case KVM_CREATE_IRQCHIP: {
3ddea128 4159 mutex_lock(&kvm->lock);
09941366 4160
3ddea128 4161 r = -EEXIST;
35e6eaa3 4162 if (irqchip_in_kernel(kvm))
3ddea128 4163 goto create_irqchip_unlock;
09941366 4164
3e515705 4165 r = -EINVAL;
557abc40 4166 if (kvm->created_vcpus)
3e515705 4167 goto create_irqchip_unlock;
09941366
RK		 4168
4169 r = kvm_pic_init(kvm);
4170 if (r)
3ddea128 4171 goto create_irqchip_unlock;
09941366
RK		 4172
4173 r = kvm_ioapic_init(kvm);
4174 if (r) {
09941366 4175 kvm_pic_destroy(kvm);
3ddea128 4176 goto create_irqchip_unlock;
09941366
RK		 4177 }
4178
399ec807
AK		 4179 r = kvm_setup_default_irq_routing(kvm);
4180 if (r) {
72bb2fcd 4181 kvm_ioapic_destroy(kvm);
09941366 4182 kvm_pic_destroy(kvm);
71ba994c 4183 goto create_irqchip_unlock;
399ec807 4184 }
49776faf 4185 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4186 smp_wmb();
49776faf 4187 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4188 create_irqchip_unlock:
4189 mutex_unlock(&kvm->lock);
1fe779f8 4190 break;
3ddea128 4191 }
7837699f 4192 case KVM_CREATE_PIT:
c5ff41ce
JK		 4193 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4194 goto create_pit;
4195 case KVM_CREATE_PIT2:
4196 r = -EFAULT;
4197 if (copy_from_user(&u.pit_config, argp,
4198 sizeof(struct kvm_pit_config)))
4199 goto out;
4200 create_pit:
250715a6 4201 mutex_lock(&kvm->lock);
269e05e4
AK		 4202 r = -EEXIST;
4203 if (kvm->arch.vpit)
4204 goto create_pit_unlock;
7837699f 4205 r = -ENOMEM;
c5ff41ce 4206 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4207 if (kvm->arch.vpit)
4208 r = 0;
269e05e4 4209 create_pit_unlock:
250715a6 4210 mutex_unlock(&kvm->lock);
7837699f 4211 break;
1fe779f8
CO		 4212 case KVM_GET_IRQCHIP: {
4213 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4214 struct kvm_irqchip *chip;
1fe779f8 4215
ff5c2c03
SL		 4216 chip = memdup_user(argp, sizeof(*chip));
4217 if (IS_ERR(chip)) {
4218 r = PTR_ERR(chip);
1fe779f8 4219 goto out;
ff5c2c03
SL		 4220 }
4221
1fe779f8 4222 r = -ENXIO;
826da321 4223 if (!irqchip_kernel(kvm))
f0d66275
DH		 4224 goto get_irqchip_out;
4225 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4226 if (r)
f0d66275 4227 goto get_irqchip_out;
1fe779f8 4228 r = -EFAULT;
f0d66275
DH		 4229 if (copy_to_user(argp, chip, sizeof *chip))
4230 goto get_irqchip_out;
1fe779f8 4231 r = 0;
f0d66275
DH		 4232 get_irqchip_out:
4233 kfree(chip);
1fe779f8
CO		 4234 break;
4235 }
4236 case KVM_SET_IRQCHIP: {
4237 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4238 struct kvm_irqchip *chip;
1fe779f8 4239
ff5c2c03
SL		 4240 chip = memdup_user(argp, sizeof(*chip));
4241 if (IS_ERR(chip)) {
4242 r = PTR_ERR(chip);
1fe779f8 4243 goto out;
ff5c2c03
SL		 4244 }
4245
1fe779f8 4246 r = -ENXIO;
826da321 4247 if (!irqchip_kernel(kvm))
f0d66275
DH		 4248 goto set_irqchip_out;
4249 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4250 if (r)
f0d66275 4251 goto set_irqchip_out;
1fe779f8 4252 r = 0;
f0d66275
DH		 4253 set_irqchip_out:
4254 kfree(chip);
1fe779f8
CO		 4255 break;
4256 }
e0f63cb9 4257 case KVM_GET_PIT: {
e0f63cb9 4258 r = -EFAULT;
f0d66275 4259 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4260 goto out;
4261 r = -ENXIO;
4262 if (!kvm->arch.vpit)
4263 goto out;
f0d66275 4264 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4265 if (r)
4266 goto out;
4267 r = -EFAULT;
f0d66275 4268 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4269 goto out;
4270 r = 0;
4271 break;
4272 }
4273 case KVM_SET_PIT: {
e0f63cb9 4274 r = -EFAULT;
f0d66275 4275 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4276 goto out;
4277 r = -ENXIO;
4278 if (!kvm->arch.vpit)
4279 goto out;
f0d66275 4280 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4281 break;
4282 }
e9f42757
BK		 4283 case KVM_GET_PIT2: {
4284 r = -ENXIO;
4285 if (!kvm->arch.vpit)
4286 goto out;
4287 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4288 if (r)
4289 goto out;
4290 r = -EFAULT;
4291 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4292 goto out;
4293 r = 0;
4294 break;
4295 }
4296 case KVM_SET_PIT2: {
4297 r = -EFAULT;
4298 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4299 goto out;
4300 r = -ENXIO;
4301 if (!kvm->arch.vpit)
4302 goto out;
4303 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4304 break;
4305 }
52d939a0
MT		 4306 case KVM_REINJECT_CONTROL: {
4307 struct kvm_reinject_control control;
4308 r = -EFAULT;
4309 if (copy_from_user(&control, argp, sizeof(control)))
4310 goto out;
4311 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4312 break;
4313 }
d71ba788
PB		 4314 case KVM_SET_BOOT_CPU_ID:
4315 r = 0;
4316 mutex_lock(&kvm->lock);
557abc40 4317 if (kvm->created_vcpus)
d71ba788
PB		 4318 r = -EBUSY;
4319 else
4320 kvm->arch.bsp_vcpu_id = arg;
4321 mutex_unlock(&kvm->lock);
4322 break;
ffde22ac 4323 case KVM_XEN_HVM_CONFIG: {
51776043 4324 struct kvm_xen_hvm_config xhc;
ffde22ac 4325 r = -EFAULT;
51776043 4326 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4327 goto out;
4328 r = -EINVAL;
51776043 4329 if (xhc.flags)
ffde22ac 4330 goto out;
51776043 4331 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4332 r = 0;
4333 break;
4334 }
afbcf7ab 4335 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4336 struct kvm_clock_data user_ns;
4337 u64 now_ns;
afbcf7ab
GC		 4338
4339 r = -EFAULT;
4340 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4341 goto out;
4342
4343 r = -EINVAL;
4344 if (user_ns.flags)
4345 goto out;
4346
4347 r = 0;
0bc48bea
RK		 4348 /*
4349 * TODO: userspace has to take care of races with VCPU_RUN, so
4350 * kvm_gen_update_masterclock() can be cut down to locked
4351 * pvclock_update_vm_gtod_copy().
4352 */
4353 kvm_gen_update_masterclock(kvm);
e891a32e 4354 now_ns = get_kvmclock_ns(kvm);
108b249c 4355 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4356 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4357 break;
4358 }
4359 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4360 struct kvm_clock_data user_ns;
4361 u64 now_ns;
4362
e891a32e 4363 now_ns = get_kvmclock_ns(kvm);
108b249c 4364 user_ns.clock = now_ns;
e3fd9a93 4365 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4366 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4367
4368 r = -EFAULT;
4369 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4370 goto out;
4371 r = 0;
4372 break;
4373 }
90de4a18
NA		 4374 case KVM_ENABLE_CAP: {
4375 struct kvm_enable_cap cap;
afbcf7ab 4376
90de4a18
NA		 4377 r = -EFAULT;
4378 if (copy_from_user(&cap, argp, sizeof(cap)))
4379 goto out;
4380 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4381 break;
4382 }
5acc5c06
BS		 4383 case KVM_MEMORY_ENCRYPT_OP: {
4384 r = -ENOTTY;
4385 if (kvm_x86_ops->mem_enc_op)
4386 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4387 break;
4388 }
69eaedee
BS		 4389 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4390 struct kvm_enc_region region;
4391
4392 r = -EFAULT;
4393 if (copy_from_user(&region, argp, sizeof(region)))
4394 goto out;
4395
4396 r = -ENOTTY;
4397 if (kvm_x86_ops->mem_enc_reg_region)
4398 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4399 break;
4400 }
4401 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4402 struct kvm_enc_region region;
4403
4404 r = -EFAULT;
4405 if (copy_from_user(&region, argp, sizeof(region)))
4406 goto out;
4407
4408 r = -ENOTTY;
4409 if (kvm_x86_ops->mem_enc_unreg_region)
4410 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4411 break;
4412 }
1fe779f8 4413 default:
ad6260da 4414 r = -ENOTTY;
1fe779f8
CO		 4415 }
4416out:
4417 return r;
4418}
4419
a16b043c 4420static void kvm_init_msr_list(void)
043405e1
CO		 4421{
4422 u32 dummy[2];
4423 unsigned i, j;
4424
62ef68bb 4425 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4426 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4427 continue;
93c4adc7
PB		 4428
4429 /*
4430 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4431 * to the guests in some cases.
93c4adc7
PB		 4432 */
4433 switch (msrs_to_save[i]) {
4434 case MSR_IA32_BNDCFGS:
4435 if (!kvm_x86_ops->mpx_supported())
4436 continue;
4437 break;
9dbe6cf9
PB		 4438 case MSR_TSC_AUX:
4439 if (!kvm_x86_ops->rdtscp_supported())
4440 continue;
4441 break;
93c4adc7
PB		 4442 default:
4443 break;
4444 }
4445
043405e1
CO		 4446 if (j < i)
4447 msrs_to_save[j] = msrs_to_save[i];
4448 j++;
4449 }
4450 num_msrs_to_save = j;
62ef68bb
PB		 4451
4452 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4453 switch (emulated_msrs[i]) {
6d396b55
PB		 4454 case MSR_IA32_SMBASE:
4455 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4456 continue;
4457 break;
62ef68bb
PB		 4458 default:
4459 break;
4460 }
4461
4462 if (j < i)
4463 emulated_msrs[j] = emulated_msrs[i];
4464 j++;
4465 }
4466 num_emulated_msrs = j;
043405e1
CO		 4467}
4468
bda9020e
MT		 4469static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4470 const void *v)
bbd9b64e 4471{
70252a10
AK		 4472 int handled = 0;
4473 int n;
4474
4475 do {
4476 n = min(len, 8);
bce87cce 4477 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4478 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4479 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4480 break;
4481 handled += n;
4482 addr += n;
4483 len -= n;
4484 v += n;
4485 } while (len);
bbd9b64e 4486
70252a10 4487 return handled;
bbd9b64e
CO		 4488}
4489
bda9020e 4490static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4491{
70252a10
AK		 4492 int handled = 0;
4493 int n;
4494
4495 do {
4496 n = min(len, 8);
bce87cce 4497 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4498 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4499 addr, n, v))
4500 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4501 break;
e39d200f 4502 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4503 handled += n;
4504 addr += n;
4505 len -= n;
4506 v += n;
4507 } while (len);
bbd9b64e 4508
70252a10 4509 return handled;
bbd9b64e
CO		 4510}
4511
2dafc6c2
GN		 4512static void kvm_set_segment(struct kvm_vcpu *vcpu,
4513 struct kvm_segment *var, int seg)
4514{
4515 kvm_x86_ops->set_segment(vcpu, var, seg);
4516}
4517
4518void kvm_get_segment(struct kvm_vcpu *vcpu,
4519 struct kvm_segment *var, int seg)
4520{
4521 kvm_x86_ops->get_segment(vcpu, var, seg);
4522}
4523
54987b7a
PB		 4524gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4525 struct x86_exception *exception)
02f59dc9
JR		 4526{
4527 gpa_t t_gpa;
02f59dc9
JR		 4528
4529 BUG_ON(!mmu_is_nested(vcpu));
4530
4531 /* NPT walks are always user-walks */
4532 access |= PFERR_USER_MASK;
54987b7a 4533 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4534
4535 return t_gpa;
4536}
4537
ab9ae313
AK		 4538gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4539 struct x86_exception *exception)
1871c602
GN		 4540{
4541 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4542 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4543}
4544
ab9ae313
AK		 4545 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4546 struct x86_exception *exception)
1871c602
GN		 4547{
4548 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4549 access |= PFERR_FETCH_MASK;
ab9ae313 4550 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4551}
4552
ab9ae313
AK		 4553gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4554 struct x86_exception *exception)
1871c602
GN		 4555{
4556 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4557 access |= PFERR_WRITE_MASK;
ab9ae313 4558 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4559}
4560
4561/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4562gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4563 struct x86_exception *exception)
1871c602 4564{
ab9ae313 4565 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4566}
4567
4568static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4569 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4570 struct x86_exception *exception)
bbd9b64e
CO		 4571{
4572 void *data = val;
10589a46 4573 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4574
4575 while (bytes) {
14dfe855 4576 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4577 exception);
bbd9b64e 4578 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4579 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4580 int ret;
4581
bcc55cba 4582 if (gpa == UNMAPPED_GVA)
ab9ae313 4583 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4584 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4585 offset, toread);
10589a46 4586 if (ret < 0) {
c3cd7ffa 4587 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4588 goto out;
4589 }
bbd9b64e 4590
77c2002e
IE		 4591 bytes -= toread;
4592 data += toread;
4593 addr += toread;
bbd9b64e 4594 }
10589a46 4595out:
10589a46 4596 return r;
bbd9b64e 4597}
77c2002e 4598
1871c602 4599/* used for instruction fetching */
0f65dd70
AK		 4600static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4601 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4602 struct x86_exception *exception)
1871c602 4603{
0f65dd70 4604 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4605 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4606 unsigned offset;
4607 int ret;
0f65dd70 4608
44583cba
PB		 4609 /* Inline kvm_read_guest_virt_helper for speed. */
4610 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4611 exception);
4612 if (unlikely(gpa == UNMAPPED_GVA))
4613 return X86EMUL_PROPAGATE_FAULT;
4614
4615 offset = addr & (PAGE_SIZE-1);
4616 if (WARN_ON(offset + bytes > PAGE_SIZE))
4617 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4618 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4619 offset, bytes);
44583cba
PB		 4620 if (unlikely(ret < 0))
4621 return X86EMUL_IO_NEEDED;
4622
4623 return X86EMUL_CONTINUE;
1871c602
GN		 4624}
4625
064aea77 4626int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4627 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4628 struct x86_exception *exception)
1871c602 4629{
0f65dd70 4630 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4631 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4632
1871c602 4633 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4634 exception);
1871c602 4635}
064aea77 4636EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4637
0f65dd70
AK		 4638static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4639 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4640 struct x86_exception *exception)
1871c602 4641{
0f65dd70 4642 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4643 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4644}
4645
7a036a6f
RK		 4646static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4647 unsigned long addr, void *val, unsigned int bytes)
4648{
4649 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4650 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4651
4652 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4653}
4654
6a4d7550 4655int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4656 gva_t addr, void *val,
2dafc6c2 4657 unsigned int bytes,
bcc55cba 4658 struct x86_exception *exception)
77c2002e 4659{
0f65dd70 4660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4661 void *data = val;
4662 int r = X86EMUL_CONTINUE;
4663
4664 while (bytes) {
14dfe855
JR		 4665 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4666 PFERR_WRITE_MASK,
ab9ae313 4667 exception);
77c2002e
IE		 4668 unsigned offset = addr & (PAGE_SIZE-1);
4669 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4670 int ret;
4671
bcc55cba 4672 if (gpa == UNMAPPED_GVA)
ab9ae313 4673 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4674 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4675 if (ret < 0) {
c3cd7ffa 4676 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4677 goto out;
4678 }
4679
4680 bytes -= towrite;
4681 data += towrite;
4682 addr += towrite;
4683 }
4684out:
4685 return r;
4686}
6a4d7550 4687EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4688
0f89b207
TL		 4689static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4690 gpa_t gpa, bool write)
4691{
4692 /* For APIC access vmexit */
4693 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4694 return 1;
4695
4696 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4697 trace_vcpu_match_mmio(gva, gpa, write, true);
4698 return 1;
4699 }
4700
4701 return 0;
4702}
4703
af7cc7d1
XG		 4704static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4705 gpa_t *gpa, struct x86_exception *exception,
4706 bool write)
4707{
97d64b78
AK		 4708 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4709 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4710
be94f6b7
HH		 4711 /*
4712 * currently PKRU is only applied to ept enabled guest so
4713 * there is no pkey in EPT page table for L1 guest or EPT
4714 * shadow page table for L2 guest.
4715 */
97d64b78 4716 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4717 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4718 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4719 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4720 (gva & (PAGE_SIZE - 1));
4f022648 4721 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4722 return 1;
4723 }
4724
af7cc7d1
XG		 4725 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4726
4727 if (*gpa == UNMAPPED_GVA)
4728 return -1;
4729
0f89b207 4730 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4731}
4732
3200f405 4733int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4734 const void *val, int bytes)
bbd9b64e
CO		 4735{
4736 int ret;
4737
54bf36aa 4738 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4739 if (ret < 0)
bbd9b64e 4740 return 0;
0eb05bf2 4741 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4742 return 1;
4743}
4744
77d197b2
XG		 4745struct read_write_emulator_ops {
4746 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4747 int bytes);
4748 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4749 void *val, int bytes);
4750 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4751 int bytes, void *val);
4752 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4753 void *val, int bytes);
4754 bool write;
4755};
4756
4757static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4758{
4759 if (vcpu->mmio_read_completed) {
77d197b2 4760 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4761 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4762 vcpu->mmio_read_completed = 0;
4763 return 1;
4764 }
4765
4766 return 0;
4767}
4768
4769static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4770 void *val, int bytes)
4771{
54bf36aa 4772 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4773}
4774
4775static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4776 void *val, int bytes)
4777{
4778 return emulator_write_phys(vcpu, gpa, val, bytes);
4779}
4780
4781static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4782{
e39d200f 4783 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4784 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4785}
4786
4787static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4788 void *val, int bytes)
4789{
e39d200f 4790 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4791 return X86EMUL_IO_NEEDED;
4792}
4793
4794static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4795 void *val, int bytes)
4796{
f78146b0
AK		 4797 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4798
87da7e66 4799 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4800 return X86EMUL_CONTINUE;
4801}
4802
0fbe9b0b 4803static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4804 .read_write_prepare = read_prepare,
4805 .read_write_emulate = read_emulate,
4806 .read_write_mmio = vcpu_mmio_read,
4807 .read_write_exit_mmio = read_exit_mmio,
4808};
4809
0fbe9b0b 4810static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4811 .read_write_emulate = write_emulate,
4812 .read_write_mmio = write_mmio,
4813 .read_write_exit_mmio = write_exit_mmio,
4814 .write = true,
4815};
4816
22388a3c
XG		 4817static int emulator_read_write_onepage(unsigned long addr, void *val,
4818 unsigned int bytes,
4819 struct x86_exception *exception,
4820 struct kvm_vcpu *vcpu,
0fbe9b0b 4821 const struct read_write_emulator_ops *ops)
bbd9b64e 4822{
af7cc7d1
XG		 4823 gpa_t gpa;
4824 int handled, ret;
22388a3c 4825 bool write = ops->write;
f78146b0 4826 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4827 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4828
4829 /*
4830 * If the exit was due to a NPF we may already have a GPA.
4831 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4832 * Note, this cannot be used on string operations since string
4833 * operation using rep will only have the initial GPA from the NPF
4834 * occurred.
4835 */
4836 if (vcpu->arch.gpa_available &&
4837 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4838 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4839 gpa = vcpu->arch.gpa_val;
4840 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4841 } else {
4842 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4843 if (ret < 0)
4844 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4845 }
10589a46 4846
618232e2 4847 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4848 return X86EMUL_CONTINUE;
4849
bbd9b64e
CO		 4850 /*
4851 * Is this MMIO handled locally?
4852 */
22388a3c 4853 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4854 if (handled == bytes)
bbd9b64e 4855 return X86EMUL_CONTINUE;
bbd9b64e 4856
70252a10
AK		 4857 gpa += handled;
4858 bytes -= handled;
4859 val += handled;
4860
87da7e66
XG		 4861 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4862 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4863 frag->gpa = gpa;
4864 frag->data = val;
4865 frag->len = bytes;
f78146b0 4866 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4867}
4868
52eb5a6d
XL		 4869static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4870 unsigned long addr,
22388a3c
XG		 4871 void *val, unsigned int bytes,
4872 struct x86_exception *exception,
0fbe9b0b 4873 const struct read_write_emulator_ops *ops)
bbd9b64e 4874{
0f65dd70 4875 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4876 gpa_t gpa;
4877 int rc;
4878
4879 if (ops->read_write_prepare &&
4880 ops->read_write_prepare(vcpu, val, bytes))
4881 return X86EMUL_CONTINUE;
4882
4883 vcpu->mmio_nr_fragments = 0;
0f65dd70 4884
bbd9b64e
CO		 4885 /* Crossing a page boundary? */
4886 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4887 int now;
bbd9b64e
CO		 4888
4889 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4890 rc = emulator_read_write_onepage(addr, val, now, exception,
4891 vcpu, ops);
4892
bbd9b64e
CO		 4893 if (rc != X86EMUL_CONTINUE)
4894 return rc;
4895 addr += now;
bac15531
NA		 4896 if (ctxt->mode != X86EMUL_MODE_PROT64)
4897 addr = (u32)addr;
bbd9b64e
CO		 4898 val += now;
4899 bytes -= now;
4900 }
22388a3c 4901
f78146b0
AK		 4902 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4903 vcpu, ops);
4904 if (rc != X86EMUL_CONTINUE)
4905 return rc;
4906
4907 if (!vcpu->mmio_nr_fragments)
4908 return rc;
4909
4910 gpa = vcpu->mmio_fragments[0].gpa;
4911
4912 vcpu->mmio_needed = 1;
4913 vcpu->mmio_cur_fragment = 0;
4914
87da7e66 4915 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4916 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4917 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4918 vcpu->run->mmio.phys_addr = gpa;
4919
4920 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4921}
4922
4923static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4924 unsigned long addr,
4925 void *val,
4926 unsigned int bytes,
4927 struct x86_exception *exception)
4928{
4929 return emulator_read_write(ctxt, addr, val, bytes,
4930 exception, &read_emultor);
4931}
4932
52eb5a6d 4933static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4934 unsigned long addr,
4935 const void *val,
4936 unsigned int bytes,
4937 struct x86_exception *exception)
4938{
4939 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4940 exception, &write_emultor);
bbd9b64e 4941}
bbd9b64e 4942
daea3e73
AK		 4943#define CMPXCHG_TYPE(t, ptr, old, new) \
4944 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4945
4946#ifdef CONFIG_X86_64
4947# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4948#else
4949# define CMPXCHG64(ptr, old, new) \
9749a6c0 4950 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4951#endif
4952
0f65dd70
AK		 4953static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4954 unsigned long addr,
bbd9b64e
CO		 4955 const void *old,
4956 const void *new,
4957 unsigned int bytes,
0f65dd70 4958 struct x86_exception *exception)
bbd9b64e 4959{
0f65dd70 4960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4961 gpa_t gpa;
4962 struct page *page;
4963 char *kaddr;
4964 bool exchanged;
2bacc55c 4965
daea3e73
AK		 4966 /* guests cmpxchg8b have to be emulated atomically */
4967 if (bytes > 8 || (bytes & (bytes - 1)))
4968 goto emul_write;
10589a46 4969
daea3e73 4970 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4971
daea3e73
AK		 4972 if (gpa == UNMAPPED_GVA ||
4973 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4974 goto emul_write;
2bacc55c 4975
daea3e73
AK		 4976 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4977 goto emul_write;
72dc67a6 4978
54bf36aa 4979 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4980 if (is_error_page(page))
c19b8bd6 4981 goto emul_write;
72dc67a6 4982
8fd75e12 4983 kaddr = kmap_atomic(page);
daea3e73
AK		 4984 kaddr += offset_in_page(gpa);
4985 switch (bytes) {
4986 case 1:
4987 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4988 break;
4989 case 2:
4990 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4991 break;
4992 case 4:
4993 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4994 break;
4995 case 8:
4996 exchanged = CMPXCHG64(kaddr, old, new);
4997 break;
4998 default:
4999 BUG();
2bacc55c 5000 }
8fd75e12 5001 kunmap_atomic(kaddr);
daea3e73
AK		 5002 kvm_release_page_dirty(page);
5003
5004 if (!exchanged)
5005 return X86EMUL_CMPXCHG_FAILED;
5006
54bf36aa 5007 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5008 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5009
5010 return X86EMUL_CONTINUE;
4a5f48f6 5011
3200f405 5012emul_write:
daea3e73 5013 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5014
0f65dd70 5015 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5016}
5017
cf8f70bf
GN		 5018static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5019{
cbfc6c91 5020 int r = 0, i;
cf8f70bf 5021
cbfc6c91
WL		 5022 for (i = 0; i < vcpu->arch.pio.count; i++) {
5023 if (vcpu->arch.pio.in)
5024 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5025 vcpu->arch.pio.size, pd);
5026 else
5027 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5028 vcpu->arch.pio.port, vcpu->arch.pio.size,
5029 pd);
5030 if (r)
5031 break;
5032 pd += vcpu->arch.pio.size;
5033 }
cf8f70bf
GN		 5034 return r;
5035}
5036
6f6fbe98
XG		 5037static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5038 unsigned short port, void *val,
5039 unsigned int count, bool in)
cf8f70bf 5040{
cf8f70bf 5041 vcpu->arch.pio.port = port;
6f6fbe98 5042 vcpu->arch.pio.in = in;
7972995b 5043 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5044 vcpu->arch.pio.size = size;
5045
5046 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5047 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5048 return 1;
5049 }
5050
5051 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5052 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5053 vcpu->run->io.size = size;
5054 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5055 vcpu->run->io.count = count;
5056 vcpu->run->io.port = port;
5057
5058 return 0;
5059}
5060
6f6fbe98
XG		 5061static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5062 int size, unsigned short port, void *val,
5063 unsigned int count)
cf8f70bf 5064{
ca1d4a9e 5065 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5066 int ret;
ca1d4a9e 5067
6f6fbe98
XG		 5068 if (vcpu->arch.pio.count)
5069 goto data_avail;
cf8f70bf 5070
cbfc6c91
WL		 5071 memset(vcpu->arch.pio_data, 0, size * count);
5072
6f6fbe98
XG		 5073 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5074 if (ret) {
5075data_avail:
5076 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5077 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5078 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5079 return 1;
5080 }
5081
cf8f70bf
GN		 5082 return 0;
5083}
5084
6f6fbe98
XG		 5085static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5086 int size, unsigned short port,
5087 const void *val, unsigned int count)
5088{
5089 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5090
5091 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5092 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5093 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5094}
5095
bbd9b64e
CO		 5096static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5097{
5098 return kvm_x86_ops->get_segment_base(vcpu, seg);
5099}
5100
3cb16fe7 5101static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5102{
3cb16fe7 5103 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5104}
5105
ae6a2375 5106static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5107{
5108 if (!need_emulate_wbinvd(vcpu))
5109 return X86EMUL_CONTINUE;
5110
5111 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5112 int cpu = get_cpu();
5113
5114 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5115 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5116 wbinvd_ipi, NULL, 1);
2eec7343 5117 put_cpu();
f5f48ee1 5118 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5119 } else
5120 wbinvd();
f5f48ee1
SY		 5121 return X86EMUL_CONTINUE;
5122}
5cb56059
JS		 5123
5124int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5125{
6affcbed
KH		 5126 kvm_emulate_wbinvd_noskip(vcpu);
5127 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5128}
f5f48ee1
SY		 5129EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5130
5cb56059
JS		 5131
5132
bcaf5cc5
AK		 5133static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5134{
5cb56059 5135 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5136}
5137
52eb5a6d
XL		 5138static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5139 unsigned long *dest)
bbd9b64e 5140{
16f8a6f9 5141 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5142}
5143
52eb5a6d
XL		 5144static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5145 unsigned long value)
bbd9b64e 5146{
338dbc97 5147
717746e3 5148 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5149}
5150
52a46617 5151static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5152{
52a46617 5153 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5154}
5155
717746e3 5156static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5157{
717746e3 5158 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5159 unsigned long value;
5160
5161 switch (cr) {
5162 case 0:
5163 value = kvm_read_cr0(vcpu);
5164 break;
5165 case 2:
5166 value = vcpu->arch.cr2;
5167 break;
5168 case 3:
9f8fe504 5169 value = kvm_read_cr3(vcpu);
52a46617
GN		 5170 break;
5171 case 4:
5172 value = kvm_read_cr4(vcpu);
5173 break;
5174 case 8:
5175 value = kvm_get_cr8(vcpu);
5176 break;
5177 default:
a737f256 5178 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5179 return 0;
5180 }
5181
5182 return value;
5183}
5184
717746e3 5185static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5186{
717746e3 5187 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5188 int res = 0;
5189
52a46617
GN		 5190 switch (cr) {
5191 case 0:
49a9b07e 5192 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5193 break;
5194 case 2:
5195 vcpu->arch.cr2 = val;
5196 break;
5197 case 3:
2390218b 5198 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5199 break;
5200 case 4:
a83b29c6 5201 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5202 break;
5203 case 8:
eea1cff9 5204 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5205 break;
5206 default:
a737f256 5207 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5208 res = -1;
52a46617 5209 }
0f12244f
GN		 5210
5211 return res;
52a46617
GN		 5212}
5213
717746e3 5214static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5215{
717746e3 5216 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5217}
5218
4bff1e86 5219static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5220{
4bff1e86 5221 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5222}
5223
4bff1e86 5224static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5225{
4bff1e86 5226 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5227}
5228
1ac9d0cf
AK		 5229static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5230{
5231 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5232}
5233
5234static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5235{
5236 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5237}
5238
4bff1e86
AK		 5239static unsigned long emulator_get_cached_segment_base(
5240 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5241{
4bff1e86 5242 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5243}
5244
1aa36616
AK		 5245static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5246 struct desc_struct *desc, u32 *base3,
5247 int seg)
2dafc6c2
GN		 5248{
5249 struct kvm_segment var;
5250
4bff1e86 5251 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5252 *selector = var.selector;
2dafc6c2 5253
378a8b09
GN		 5254 if (var.unusable) {
5255 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5256 if (base3)
5257 *base3 = 0;
2dafc6c2 5258 return false;
378a8b09 5259 }
2dafc6c2
GN		 5260
5261 if (var.g)
5262 var.limit >>= 12;
5263 set_desc_limit(desc, var.limit);
5264 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5265#ifdef CONFIG_X86_64
5266 if (base3)
5267 *base3 = var.base >> 32;
5268#endif
2dafc6c2
GN		 5269 desc->type = var.type;
5270 desc->s = var.s;
5271 desc->dpl = var.dpl;
5272 desc->p = var.present;
5273 desc->avl = var.avl;
5274 desc->l = var.l;
5275 desc->d = var.db;
5276 desc->g = var.g;
5277
5278 return true;
5279}
5280
1aa36616
AK		 5281static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5282 struct desc_struct *desc, u32 base3,
5283 int seg)
2dafc6c2 5284{
4bff1e86 5285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5286 struct kvm_segment var;
5287
1aa36616 5288 var.selector = selector;
2dafc6c2 5289 var.base = get_desc_base(desc);
5601d05b
GN		 5290#ifdef CONFIG_X86_64
5291 var.base |= ((u64)base3) << 32;
5292#endif
2dafc6c2
GN		 5293 var.limit = get_desc_limit(desc);
5294 if (desc->g)
5295 var.limit = (var.limit << 12) | 0xfff;
5296 var.type = desc->type;
2dafc6c2
GN		 5297 var.dpl = desc->dpl;
5298 var.db = desc->d;
5299 var.s = desc->s;
5300 var.l = desc->l;
5301 var.g = desc->g;
5302 var.avl = desc->avl;
5303 var.present = desc->p;
5304 var.unusable = !var.present;
5305 var.padding = 0;
5306
5307 kvm_set_segment(vcpu, &var, seg);
5308 return;
5309}
5310
717746e3
AK		 5311static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5312 u32 msr_index, u64 *pdata)
5313{
609e36d3
PB		 5314 struct msr_data msr;
5315 int r;
5316
5317 msr.index = msr_index;
5318 msr.host_initiated = false;
5319 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5320 if (r)
5321 return r;
5322
5323 *pdata = msr.data;
5324 return 0;
717746e3
AK		 5325}
5326
5327static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5328 u32 msr_index, u64 data)
5329{
8fe8ab46
WA		 5330 struct msr_data msr;
5331
5332 msr.data = data;
5333 msr.index = msr_index;
5334 msr.host_initiated = false;
5335 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5336}
5337
64d60670
PB		 5338static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5339{
5340 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5341
5342 return vcpu->arch.smbase;
5343}
5344
5345static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5346{
5347 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5348
5349 vcpu->arch.smbase = smbase;
5350}
5351
67f4d428
NA		 5352static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5353 u32 pmc)
5354{
c6702c9d 5355 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5356}
5357
222d21aa
AK		 5358static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5359 u32 pmc, u64 *pdata)
5360{
c6702c9d 5361 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5362}
5363
6c3287f7
AK		 5364static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5365{
5366 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5367}
5368
2953538e 5369static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5370 struct x86_instruction_info *info,
c4f035c6
AK		 5371 enum x86_intercept_stage stage)
5372{
2953538e 5373 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5374}
5375
e911eb3b
YZ		 5376static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5377 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5378{
e911eb3b 5379 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5380}
5381
dd856efa
AK		 5382static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5383{
5384 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5385}
5386
5387static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5388{
5389 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5390}
5391
801806d9
NA		 5392static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5393{
5394 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5395}
5396
6ed071f0
LP		 5397static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5398{
5399 return emul_to_vcpu(ctxt)->arch.hflags;
5400}
5401
5402static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5403{
5404 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5405}
5406
0234bf88
LP		 5407static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5408{
5409 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5410}
5411
0225fb50 5412static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5413 .read_gpr = emulator_read_gpr,
5414 .write_gpr = emulator_write_gpr,
1871c602 5415 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5416 .write_std = kvm_write_guest_virt_system,
7a036a6f 5417 .read_phys = kvm_read_guest_phys_system,
1871c602 5418 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5419 .read_emulated = emulator_read_emulated,
5420 .write_emulated = emulator_write_emulated,
5421 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5422 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5423 .pio_in_emulated = emulator_pio_in_emulated,
5424 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5425 .get_segment = emulator_get_segment,
5426 .set_segment = emulator_set_segment,
5951c442 5427 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5428 .get_gdt = emulator_get_gdt,
160ce1f1 5429 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5430 .set_gdt = emulator_set_gdt,
5431 .set_idt = emulator_set_idt,
52a46617
GN		 5432 .get_cr = emulator_get_cr,
5433 .set_cr = emulator_set_cr,
9c537244 5434 .cpl = emulator_get_cpl,
35aa5375
GN		 5435 .get_dr = emulator_get_dr,
5436 .set_dr = emulator_set_dr,
64d60670
PB		 5437 .get_smbase = emulator_get_smbase,
5438 .set_smbase = emulator_set_smbase,
717746e3
AK		 5439 .set_msr = emulator_set_msr,
5440 .get_msr = emulator_get_msr,
67f4d428 5441 .check_pmc = emulator_check_pmc,
222d21aa 5442 .read_pmc = emulator_read_pmc,
6c3287f7 5443 .halt = emulator_halt,
bcaf5cc5 5444 .wbinvd = emulator_wbinvd,
d6aa1000 5445 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5446 .intercept = emulator_intercept,
bdb42f5a 5447 .get_cpuid = emulator_get_cpuid,
801806d9 5448 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5449 .get_hflags = emulator_get_hflags,
5450 .set_hflags = emulator_set_hflags,
0234bf88 5451 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5452};
5453
95cb2295
GN		 5454static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5455{
37ccdcbe 5456 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5457 /*
5458 * an sti; sti; sequence only disable interrupts for the first
5459 * instruction. So, if the last instruction, be it emulated or
5460 * not, left the system with the INT_STI flag enabled, it
5461 * means that the last instruction is an sti. We should not
5462 * leave the flag on in this case. The same goes for mov ss
5463 */
37ccdcbe
PB		 5464 if (int_shadow & mask)
5465 mask = 0;
6addfc42 5466 if (unlikely(int_shadow || mask)) {
95cb2295 5467 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5468 if (!mask)
5469 kvm_make_request(KVM_REQ_EVENT, vcpu);
5470 }
95cb2295
GN		 5471}
5472
ef54bcfe 5473static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5474{
5475 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5476 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5477 return kvm_propagate_fault(vcpu, &ctxt->exception);
5478
5479 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5480 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5481 ctxt->exception.error_code);
54b8486f 5482 else
da9cb575 5483 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5484 return false;
54b8486f
GN		 5485}
5486
8ec4722d
MG		 5487static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5488{
adf52235 5489 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5490 int cs_db, cs_l;
5491
8ec4722d
MG		 5492 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5493
adf52235 5494 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5495 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5496
adf52235
TY		 5497 ctxt->eip = kvm_rip_read(vcpu);
5498 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5499 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5500 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5501 cs_db ? X86EMUL_MODE_PROT32 :
5502 X86EMUL_MODE_PROT16;
a584539b 5503 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5504 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5505 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5506
dd856efa 5507 init_decode_cache(ctxt);
7ae441ea 5508 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5509}
5510
71f9833b 5511int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5512{
9d74191a 5513 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5514 int ret;
5515
5516 init_emulate_ctxt(vcpu);
5517
9dac77fa
AK		 5518 ctxt->op_bytes = 2;
5519 ctxt->ad_bytes = 2;
5520 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5521 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5522
5523 if (ret != X86EMUL_CONTINUE)
5524 return EMULATE_FAIL;
5525
9dac77fa 5526 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5527 kvm_rip_write(vcpu, ctxt->eip);
5528 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5529
5530 if (irq == NMI_VECTOR)
7460fb4a 5531 vcpu->arch.nmi_pending = 0;
63995653
MG		 5532 else
5533 vcpu->arch.interrupt.pending = false;
5534
5535 return EMULATE_DONE;
5536}
5537EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5538
6d77dbfc
GN		 5539static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5540{
fc3a9157
JR		 5541 int r = EMULATE_DONE;
5542
6d77dbfc
GN		 5543 ++vcpu->stat.insn_emulation_fail;
5544 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5545 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5546 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5547 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5548 vcpu->run->internal.ndata = 0;
1f4dcb3b 5549 r = EMULATE_USER_EXIT;
fc3a9157 5550 }
6d77dbfc 5551 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5552
5553 return r;
6d77dbfc
GN		 5554}
5555
93c05d3e 5556static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5557 bool write_fault_to_shadow_pgtable,
5558 int emulation_type)
a6f177ef 5559{
95b3cf69 5560 gpa_t gpa = cr2;
ba049e93 5561 kvm_pfn_t pfn;
a6f177ef 5562
991eebf9
GN		 5563 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5564 return false;
5565
95b3cf69
XG		 5566 if (!vcpu->arch.mmu.direct_map) {
5567 /*
5568 * Write permission should be allowed since only
5569 * write access need to be emulated.
5570 */
5571 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5572
95b3cf69
XG		 5573 /*
5574 * If the mapping is invalid in guest, let cpu retry
5575 * it to generate fault.
5576 */
5577 if (gpa == UNMAPPED_GVA)
5578 return true;
5579 }
a6f177ef 5580
8e3d9d06
XG		 5581 /*
5582 * Do not retry the unhandleable instruction if it faults on the
5583 * readonly host memory, otherwise it will goto a infinite loop:
5584 * retry instruction -> write #PF -> emulation fail -> retry
5585 * instruction -> ...
5586 */
5587 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5588
5589 /*
5590 * If the instruction failed on the error pfn, it can not be fixed,
5591 * report the error to userspace.
5592 */
5593 if (is_error_noslot_pfn(pfn))
5594 return false;
5595
5596 kvm_release_pfn_clean(pfn);
5597
5598 /* The instructions are well-emulated on direct mmu. */
5599 if (vcpu->arch.mmu.direct_map) {
5600 unsigned int indirect_shadow_pages;
5601
5602 spin_lock(&vcpu->kvm->mmu_lock);
5603 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5604 spin_unlock(&vcpu->kvm->mmu_lock);
5605
5606 if (indirect_shadow_pages)
5607 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5608
a6f177ef 5609 return true;
8e3d9d06 5610 }
a6f177ef 5611
95b3cf69
XG		 5612 /*
5613 * if emulation was due to access to shadowed page table
5614 * and it failed try to unshadow page and re-enter the
5615 * guest to let CPU execute the instruction.
5616 */
5617 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5618
5619 /*
5620 * If the access faults on its page table, it can not
5621 * be fixed by unprotecting shadow page and it should
5622 * be reported to userspace.
5623 */
5624 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5625}
5626
1cb3f3ae
XG		 5627static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5628 unsigned long cr2, int emulation_type)
5629{
5630 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5631 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5632
5633 last_retry_eip = vcpu->arch.last_retry_eip;
5634 last_retry_addr = vcpu->arch.last_retry_addr;
5635
5636 /*
5637 * If the emulation is caused by #PF and it is non-page_table
5638 * writing instruction, it means the VM-EXIT is caused by shadow
5639 * page protected, we can zap the shadow page and retry this
5640 * instruction directly.
5641 *
5642 * Note: if the guest uses a non-page-table modifying instruction
5643 * on the PDE that points to the instruction, then we will unmap
5644 * the instruction and go to an infinite loop. So, we cache the
5645 * last retried eip and the last fault address, if we meet the eip
5646 * and the address again, we can break out of the potential infinite
5647 * loop.
5648 */
5649 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5650
5651 if (!(emulation_type & EMULTYPE_RETRY))
5652 return false;
5653
5654 if (x86_page_table_writing_insn(ctxt))
5655 return false;
5656
5657 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5658 return false;
5659
5660 vcpu->arch.last_retry_eip = ctxt->eip;
5661 vcpu->arch.last_retry_addr = cr2;
5662
5663 if (!vcpu->arch.mmu.direct_map)
5664 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5665
22368028 5666 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5667
5668 return true;
5669}
5670
716d51ab
GN		 5671static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5672static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5673
64d60670 5674static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5675{
64d60670 5676 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5677 /* This is a good place to trace that we are exiting SMM. */
5678 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5679
c43203ca
PB		 5680 /* Process a latched INIT or SMI, if any. */
5681 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5682 }
699023e2
PB		 5683
5684 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5685}
5686
5687static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5688{
5689 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5690
a584539b 5691 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5692
5693 if (changed & HF_SMM_MASK)
5694 kvm_smm_changed(vcpu);
a584539b
PB		 5695}
5696
4a1e10d5
PB		 5697static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5698 unsigned long *db)
5699{
5700 u32 dr6 = 0;
5701 int i;
5702 u32 enable, rwlen;
5703
5704 enable = dr7;
5705 rwlen = dr7 >> 16;
5706 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5707 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5708 dr6 |= (1 << i);
5709 return dr6;
5710}
5711
c8401dda 5712static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5713{
5714 struct kvm_run *kvm_run = vcpu->run;
5715
c8401dda
PB		 5716 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5717 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5718 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5719 kvm_run->debug.arch.exception = DB_VECTOR;
5720 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5721 *r = EMULATE_USER_EXIT;
5722 } else {
5723 /*
5724 * "Certain debug exceptions may clear bit 0-3. The
5725 * remaining contents of the DR6 register are never
5726 * cleared by the processor".
5727 */
5728 vcpu->arch.dr6 &= ~15;
5729 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5730 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5731 }
5732}
5733
6affcbed
KH		 5734int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5735{
5736 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5737 int r = EMULATE_DONE;
5738
5739 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5740
5741 /*
5742 * rflags is the old, "raw" value of the flags. The new value has
5743 * not been saved yet.
5744 *
5745 * This is correct even for TF set by the guest, because "the
5746 * processor will not generate this exception after the instruction
5747 * that sets the TF flag".
5748 */
5749 if (unlikely(rflags & X86_EFLAGS_TF))
5750 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5751 return r == EMULATE_DONE;
5752}
5753EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5754
4a1e10d5
PB		 5755static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5756{
4a1e10d5
PB		 5757 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5758 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5759 struct kvm_run *kvm_run = vcpu->run;
5760 unsigned long eip = kvm_get_linear_rip(vcpu);
5761 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5762 vcpu->arch.guest_debug_dr7,
5763 vcpu->arch.eff_db);
5764
5765 if (dr6 != 0) {
6f43ed01 5766 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5767 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5768 kvm_run->debug.arch.exception = DB_VECTOR;
5769 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5770 *r = EMULATE_USER_EXIT;
5771 return true;
5772 }
5773 }
5774
4161a569
NA		 5775 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5776 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5777 unsigned long eip = kvm_get_linear_rip(vcpu);
5778 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5779 vcpu->arch.dr7,
5780 vcpu->arch.db);
5781
5782 if (dr6 != 0) {
5783 vcpu->arch.dr6 &= ~15;
6f43ed01 5784 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5785 kvm_queue_exception(vcpu, DB_VECTOR);
5786 *r = EMULATE_DONE;
5787 return true;
5788 }
5789 }
5790
5791 return false;
5792}
5793
51d8b661
AP		 5794int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5795 unsigned long cr2,
dc25e89e
AP		 5796 int emulation_type,
5797 void *insn,
5798 int insn_len)
bbd9b64e 5799{
95cb2295 5800 int r;
9d74191a 5801 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5802 bool writeback = true;
93c05d3e 5803 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5804
93c05d3e
XG		 5805 /*
5806 * Clear write_fault_to_shadow_pgtable here to ensure it is
5807 * never reused.
5808 */
5809 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5810 kvm_clear_exception_queue(vcpu);
8d7d8102 5811
571008da 5812 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5813 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5814
5815 /*
5816 * We will reenter on the same instruction since
5817 * we do not set complete_userspace_io. This does not
5818 * handle watchpoints yet, those would be handled in
5819 * the emulate_ops.
5820 */
d391f120
VK		 5821 if (!(emulation_type & EMULTYPE_SKIP) &&
5822 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5823 return r;
5824
9d74191a
TY		 5825 ctxt->interruptibility = 0;
5826 ctxt->have_exception = false;
e0ad0b47 5827 ctxt->exception.vector = -1;
9d74191a 5828 ctxt->perm_ok = false;
bbd9b64e 5829
b51e974f 5830 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5831
9d74191a 5832 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5833
e46479f8 5834 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5835 ++vcpu->stat.insn_emulation;
1d2887e2 5836 if (r != EMULATION_OK) {
4005996e
AK		 5837 if (emulation_type & EMULTYPE_TRAP_UD)
5838 return EMULATE_FAIL;
991eebf9
GN		 5839 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5840 emulation_type))
bbd9b64e 5841 return EMULATE_DONE;
6ea6e843
PB		 5842 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5843 return EMULATE_DONE;
6d77dbfc
GN		 5844 if (emulation_type & EMULTYPE_SKIP)
5845 return EMULATE_FAIL;
5846 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5847 }
5848 }
5849
ba8afb6b 5850 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5851 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5852 if (ctxt->eflags & X86_EFLAGS_RF)
5853 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5854 return EMULATE_DONE;
5855 }
5856
1cb3f3ae
XG		 5857 if (retry_instruction(ctxt, cr2, emulation_type))
5858 return EMULATE_DONE;
5859
7ae441ea 5860 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5861 changes registers values during IO operation */
7ae441ea
GN		 5862 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5863 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5864 emulator_invalidate_register_cache(ctxt);
7ae441ea 5865 }
4d2179e1 5866
5cd21917 5867restart:
0f89b207
TL		 5868 /* Save the faulting GPA (cr2) in the address field */
5869 ctxt->exception.address = cr2;
5870
9d74191a 5871 r = x86_emulate_insn(ctxt);
bbd9b64e 5872
775fde86
JR		 5873 if (r == EMULATION_INTERCEPTED)
5874 return EMULATE_DONE;
5875
d2ddd1c4 5876 if (r == EMULATION_FAILED) {
991eebf9
GN		 5877 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5878 emulation_type))
c3cd7ffa
GN		 5879 return EMULATE_DONE;
5880
6d77dbfc 5881 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5882 }
5883
9d74191a 5884 if (ctxt->have_exception) {
d2ddd1c4 5885 r = EMULATE_DONE;
ef54bcfe
PB		 5886 if (inject_emulated_exception(vcpu))
5887 return r;
d2ddd1c4 5888 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5889 if (!vcpu->arch.pio.in) {
5890 /* FIXME: return into emulator if single-stepping. */
3457e419 5891 vcpu->arch.pio.count = 0;
0912c977 5892 } else {
7ae441ea 5893 writeback = false;
716d51ab
GN		 5894 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5895 }
ac0a48c3 5896 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5897 } else if (vcpu->mmio_needed) {
5898 if (!vcpu->mmio_is_write)
5899 writeback = false;
ac0a48c3 5900 r = EMULATE_USER_EXIT;
716d51ab 5901 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5902 } else if (r == EMULATION_RESTART)
5cd21917 5903 goto restart;
d2ddd1c4
GN		 5904 else
5905 r = EMULATE_DONE;
f850e2e6 5906
7ae441ea 5907 if (writeback) {
6addfc42 5908 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5909 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5910 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5911 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5912 if (r == EMULATE_DONE &&
5913 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5914 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5915 if (!ctxt->have_exception ||
5916 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5917 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5918
5919 /*
5920 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5921 * do nothing, and it will be requested again as soon as
5922 * the shadow expires. But we still need to check here,
5923 * because POPF has no interrupt shadow.
5924 */
5925 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5926 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5927 } else
5928 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5929
5930 return r;
de7d789a 5931}
51d8b661 5932EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5933
cf8f70bf 5934int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5935{
cf8f70bf 5936 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5937 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5938 size, port, &val, 1);
cf8f70bf 5939 /* do not return to emulator after return from userspace */
7972995b 5940 vcpu->arch.pio.count = 0;
de7d789a
CO		 5941 return ret;
5942}
cf8f70bf 5943EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5944
8370c3d0
TL		 5945static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5946{
5947 unsigned long val;
5948
5949 /* We should only ever be called with arch.pio.count equal to 1 */
5950 BUG_ON(vcpu->arch.pio.count != 1);
5951
5952 /* For size less than 4 we merge, else we zero extend */
5953 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5954 : 0;
5955
5956 /*
5957 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5958 * the copy and tracing
5959 */
5960 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5961 vcpu->arch.pio.port, &val, 1);
5962 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5963
5964 return 1;
5965}
5966
5967int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5968{
5969 unsigned long val;
5970 int ret;
5971
5972 /* For size less than 4 we merge, else we zero extend */
5973 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5974
5975 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5976 &val, 1);
5977 if (ret) {
5978 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5979 return ret;
5980 }
5981
5982 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5983
5984 return 0;
5985}
5986EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5987
251a5fd6 5988static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5989{
0a3aee0d 5990 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5991 return 0;
8cfdc000
ZA		 5992}
5993
5994static void tsc_khz_changed(void *data)
c8076604 5995{
8cfdc000
ZA		 5996 struct cpufreq_freqs *freq = data;
5997 unsigned long khz = 0;
5998
5999 if (data)
6000 khz = freq->new;
6001 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6002 khz = cpufreq_quick_get(raw_smp_processor_id());
6003 if (!khz)
6004 khz = tsc_khz;
0a3aee0d 6005 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6006}
6007
5fa4ec9c 6008#ifdef CONFIG_X86_64
0092e434
VK		 6009static void kvm_hyperv_tsc_notifier(void)
6010{
0092e434
VK		 6011 struct kvm *kvm;
6012 struct kvm_vcpu *vcpu;
6013 int cpu;
6014
6015 spin_lock(&kvm_lock);
6016 list_for_each_entry(kvm, &vm_list, vm_list)
6017 kvm_make_mclock_inprogress_request(kvm);
6018
6019 hyperv_stop_tsc_emulation();
6020
6021 /* TSC frequency always matches when on Hyper-V */
6022 for_each_present_cpu(cpu)
6023 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6024 kvm_max_guest_tsc_khz = tsc_khz;
6025
6026 list_for_each_entry(kvm, &vm_list, vm_list) {
6027 struct kvm_arch *ka = &kvm->arch;
6028
6029 spin_lock(&ka->pvclock_gtod_sync_lock);
6030
6031 pvclock_update_vm_gtod_copy(kvm);
6032
6033 kvm_for_each_vcpu(cpu, vcpu, kvm)
6034 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6035
6036 kvm_for_each_vcpu(cpu, vcpu, kvm)
6037 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6038
6039 spin_unlock(&ka->pvclock_gtod_sync_lock);
6040 }
6041 spin_unlock(&kvm_lock);
0092e434 6042}
5fa4ec9c 6043#endif
0092e434 6044
c8076604
GH		 6045static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6046 void *data)
6047{
6048 struct cpufreq_freqs *freq = data;
6049 struct kvm *kvm;
6050 struct kvm_vcpu *vcpu;
6051 int i, send_ipi = 0;
6052
8cfdc000
ZA		 6053 /*
6054 * We allow guests to temporarily run on slowing clocks,
6055 * provided we notify them after, or to run on accelerating
6056 * clocks, provided we notify them before. Thus time never
6057 * goes backwards.
6058 *
6059 * However, we have a problem. We can't atomically update
6060 * the frequency of a given CPU from this function; it is
6061 * merely a notifier, which can be called from any CPU.
6062 * Changing the TSC frequency at arbitrary points in time
6063 * requires a recomputation of local variables related to
6064 * the TSC for each VCPU. We must flag these local variables
6065 * to be updated and be sure the update takes place with the
6066 * new frequency before any guests proceed.
6067 *
6068 * Unfortunately, the combination of hotplug CPU and frequency
6069 * change creates an intractable locking scenario; the order
6070 * of when these callouts happen is undefined with respect to
6071 * CPU hotplug, and they can race with each other. As such,
6072 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6073 * undefined; you can actually have a CPU frequency change take
6074 * place in between the computation of X and the setting of the
6075 * variable. To protect against this problem, all updates of
6076 * the per_cpu tsc_khz variable are done in an interrupt
6077 * protected IPI, and all callers wishing to update the value
6078 * must wait for a synchronous IPI to complete (which is trivial
6079 * if the caller is on the CPU already). This establishes the
6080 * necessary total order on variable updates.
6081 *
6082 * Note that because a guest time update may take place
6083 * anytime after the setting of the VCPU's request bit, the
6084 * correct TSC value must be set before the request. However,
6085 * to ensure the update actually makes it to any guest which
6086 * starts running in hardware virtualization between the set
6087 * and the acquisition of the spinlock, we must also ping the
6088 * CPU after setting the request bit.
6089 *
6090 */
6091
c8076604
GH		 6092 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6093 return 0;
6094 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6095 return 0;
8cfdc000
ZA		 6096
6097 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6098
2f303b74 6099 spin_lock(&kvm_lock);
c8076604 6100 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6101 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6102 if (vcpu->cpu != freq->cpu)
6103 continue;
c285545f 6104 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6105 if (vcpu->cpu != smp_processor_id())
8cfdc000 6106 send_ipi = 1;
c8076604
GH		 6107 }
6108 }
2f303b74 6109 spin_unlock(&kvm_lock);
c8076604
GH		 6110
6111 if (freq->old < freq->new && send_ipi) {
6112 /*
6113 * We upscale the frequency. Must make the guest
6114 * doesn't see old kvmclock values while running with
6115 * the new frequency, otherwise we risk the guest sees
6116 * time go backwards.
6117 *
6118 * In case we update the frequency for another cpu
6119 * (which might be in guest context) send an interrupt
6120 * to kick the cpu out of guest context. Next time
6121 * guest context is entered kvmclock will be updated,
6122 * so the guest will not see stale values.
6123 */
8cfdc000 6124 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6125 }
6126 return 0;
6127}
6128
6129static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6130 .notifier_call = kvmclock_cpufreq_notifier
6131};
6132
251a5fd6 6133static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6134{
251a5fd6
SAS		 6135 tsc_khz_changed(NULL);
6136 return 0;
8cfdc000
ZA		 6137}
6138
b820cc0c
ZA		 6139static void kvm_timer_init(void)
6140{
c285545f 6141 max_tsc_khz = tsc_khz;
460dd42e 6142
b820cc0c 6143 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6144#ifdef CONFIG_CPU_FREQ
6145 struct cpufreq_policy policy;
758f588d
BP		 6146 int cpu;
6147
c285545f 6148 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6149 cpu = get_cpu();
6150 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6151 if (policy.cpuinfo.max_freq)
6152 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6153 put_cpu();
c285545f 6154#endif
b820cc0c
ZA		 6155 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6156 CPUFREQ_TRANSITION_NOTIFIER);
6157 }
c285545f 6158 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6159
73c1b41e 6160 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6161 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6162}
6163
ff9d07a0
ZY		 6164static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6165
f5132b01 6166int kvm_is_in_guest(void)
ff9d07a0 6167{
086c9855 6168 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6169}
6170
6171static int kvm_is_user_mode(void)
6172{
6173 int user_mode = 3;
dcf46b94 6174
086c9855
AS		 6175 if (__this_cpu_read(current_vcpu))
6176 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6177
ff9d07a0
ZY		 6178 return user_mode != 0;
6179}
6180
6181static unsigned long kvm_get_guest_ip(void)
6182{
6183 unsigned long ip = 0;
dcf46b94 6184
086c9855
AS		 6185 if (__this_cpu_read(current_vcpu))
6186 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6187
ff9d07a0
ZY		 6188 return ip;
6189}
6190
6191static struct perf_guest_info_callbacks kvm_guest_cbs = {
6192 .is_in_guest = kvm_is_in_guest,
6193 .is_user_mode = kvm_is_user_mode,
6194 .get_guest_ip = kvm_get_guest_ip,
6195};
6196
6197void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6198{
086c9855 6199 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6200}
6201EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6202
6203void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6204{
086c9855 6205 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6206}
6207EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6208
ce88decf
XG		 6209static void kvm_set_mmio_spte_mask(void)
6210{
6211 u64 mask;
6212 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6213
6214 /*
6215 * Set the reserved bits and the present bit of an paging-structure
6216 * entry to generate page fault with PFER.RSV = 1.
6217 */
885032b9 6218 /* Mask the reserved physical address bits. */
d1431483 6219 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6220
885032b9 6221 /* Set the present bit. */
ce88decf
XG		 6222 mask |= 1ull;
6223
6224#ifdef CONFIG_X86_64
6225 /*
6226 * If reserved bit is not supported, clear the present bit to disable
6227 * mmio page fault.
6228 */
6229 if (maxphyaddr == 52)
6230 mask &= ~1ull;
6231#endif
6232
dcdca5fe 6233 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6234}
6235
16e8d74d
MT		 6236#ifdef CONFIG_X86_64
6237static void pvclock_gtod_update_fn(struct work_struct *work)
6238{
d828199e
MT		 6239 struct kvm *kvm;
6240
6241 struct kvm_vcpu *vcpu;
6242 int i;
6243
2f303b74 6244 spin_lock(&kvm_lock);
d828199e
MT		 6245 list_for_each_entry(kvm, &vm_list, vm_list)
6246 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6247 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6248 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6249 spin_unlock(&kvm_lock);
16e8d74d
MT		 6250}
6251
6252static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6253
6254/*
6255 * Notification about pvclock gtod data update.
6256 */
6257static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6258 void *priv)
6259{
6260 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6261 struct timekeeper *tk = priv;
6262
6263 update_pvclock_gtod(tk);
6264
6265 /* disable master clock if host does not trust, or does not
b0c39dc6 6266 * use, TSC based clocksource.
16e8d74d 6267 */
b0c39dc6 6268 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6269 atomic_read(&kvm_guest_has_master_clock) != 0)
6270 queue_work(system_long_wq, &pvclock_gtod_work);
6271
6272 return 0;
6273}
6274
6275static struct notifier_block pvclock_gtod_notifier = {
6276 .notifier_call = pvclock_gtod_notify,
6277};
6278#endif
6279
f8c16bba 6280int kvm_arch_init(void *opaque)
043405e1 6281{
b820cc0c 6282 int r;
6b61edf7 6283 struct kvm_x86_ops *ops = opaque;
f8c16bba 6284
f8c16bba
ZX		 6285 if (kvm_x86_ops) {
6286 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6287 r = -EEXIST;
6288 goto out;
f8c16bba
ZX		 6289 }
6290
6291 if (!ops->cpu_has_kvm_support()) {
6292 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6293 r = -EOPNOTSUPP;
6294 goto out;
f8c16bba
ZX		 6295 }
6296 if (ops->disabled_by_bios()) {
6297 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6298 r = -EOPNOTSUPP;
6299 goto out;
f8c16bba
ZX		 6300 }
6301
013f6a5d
MT		 6302 r = -ENOMEM;
6303 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6304 if (!shared_msrs) {
6305 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6306 goto out;
6307 }
6308
97db56ce
AK		 6309 r = kvm_mmu_module_init();
6310 if (r)
013f6a5d 6311 goto out_free_percpu;
97db56ce 6312
ce88decf 6313 kvm_set_mmio_spte_mask();
97db56ce 6314
f8c16bba 6315 kvm_x86_ops = ops;
920c8377 6316
7b52345e 6317 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6318 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6319 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6320 kvm_timer_init();
c8076604 6321
ff9d07a0
ZY		 6322 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6323
d366bf7e 6324 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6325 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6326
c5cc421b 6327 kvm_lapic_init();
16e8d74d
MT		 6328#ifdef CONFIG_X86_64
6329 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6330
5fa4ec9c 6331 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6332 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6333#endif
6334
f8c16bba 6335 return 0;
56c6d28a 6336
013f6a5d
MT		 6337out_free_percpu:
6338 free_percpu(shared_msrs);
56c6d28a 6339out:
56c6d28a 6340 return r;
043405e1 6341}
8776e519 6342
f8c16bba
ZX		 6343void kvm_arch_exit(void)
6344{
0092e434 6345#ifdef CONFIG_X86_64
5fa4ec9c 6346 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6347 clear_hv_tscchange_cb();
6348#endif
cef84c30 6349 kvm_lapic_exit();
ff9d07a0
ZY		 6350 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6351
888d256e
JK		 6352 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6353 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6354 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6355 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6356#ifdef CONFIG_X86_64
6357 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6358#endif
f8c16bba 6359 kvm_x86_ops = NULL;
56c6d28a 6360 kvm_mmu_module_exit();
013f6a5d 6361 free_percpu(shared_msrs);
56c6d28a 6362}
f8c16bba 6363
5cb56059 6364int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6365{
6366 ++vcpu->stat.halt_exits;
35754c98 6367 if (lapic_in_kernel(vcpu)) {
a4535290 6368 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6369 return 1;
6370 } else {
6371 vcpu->run->exit_reason = KVM_EXIT_HLT;
6372 return 0;
6373 }
6374}
5cb56059
JS		 6375EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6376
6377int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6378{
6affcbed
KH		 6379 int ret = kvm_skip_emulated_instruction(vcpu);
6380 /*
6381 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6382 * KVM_EXIT_DEBUG here.
6383 */
6384 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6385}
8776e519
HB		 6386EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6387
8ef81a9a 6388#ifdef CONFIG_X86_64
55dd00a7
MT		 6389static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6390 unsigned long clock_type)
6391{
6392 struct kvm_clock_pairing clock_pairing;
6393 struct timespec ts;
80fbd89c 6394 u64 cycle;
55dd00a7
MT		 6395 int ret;
6396
6397 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6398 return -KVM_EOPNOTSUPP;
6399
6400 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6401 return -KVM_EOPNOTSUPP;
6402
6403 clock_pairing.sec = ts.tv_sec;
6404 clock_pairing.nsec = ts.tv_nsec;
6405 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6406 clock_pairing.flags = 0;
6407
6408 ret = 0;
6409 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6410 sizeof(struct kvm_clock_pairing)))
6411 ret = -KVM_EFAULT;
6412
6413 return ret;
6414}
8ef81a9a 6415#endif
55dd00a7 6416
6aef266c
SV		 6417/*
6418 * kvm_pv_kick_cpu_op: Kick a vcpu.
6419 *
6420 * @apicid - apicid of vcpu to be kicked.
6421 */
6422static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6423{
24d2166b 6424 struct kvm_lapic_irq lapic_irq;
6aef266c 6425
24d2166b
R		 6426 lapic_irq.shorthand = 0;
6427 lapic_irq.dest_mode = 0;
ebd28fcb 6428 lapic_irq.level = 0;
24d2166b 6429 lapic_irq.dest_id = apicid;
93bbf0b8 6430 lapic_irq.msi_redir_hint = false;
6aef266c 6431
24d2166b 6432 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6433 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6434}
6435
d62caabb
AS		 6436void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6437{
6438 vcpu->arch.apicv_active = false;
6439 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6440}
6441
8776e519
HB		 6442int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6443{
6444 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6445 int op_64_bit, r;
8776e519 6446
6affcbed 6447 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6448
55cd8e5a
GN		 6449 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6450 return kvm_hv_hypercall(vcpu);
6451
5fdbf976
MT		 6452 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6453 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6454 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6455 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6456 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6457
229456fc 6458 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6459
a449c7aa
NA		 6460 op_64_bit = is_64_bit_mode(vcpu);
6461 if (!op_64_bit) {
8776e519
HB		 6462 nr &= 0xFFFFFFFF;
6463 a0 &= 0xFFFFFFFF;
6464 a1 &= 0xFFFFFFFF;
6465 a2 &= 0xFFFFFFFF;
6466 a3 &= 0xFFFFFFFF;
6467 }
6468
07708c4a
JK		 6469 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6470 ret = -KVM_EPERM;
6471 goto out;
6472 }
6473
8776e519 6474 switch (nr) {
b93463aa
AK		 6475 case KVM_HC_VAPIC_POLL_IRQ:
6476 ret = 0;
6477 break;
6aef266c
SV		 6478 case KVM_HC_KICK_CPU:
6479 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6480 ret = 0;
6481 break;
8ef81a9a 6482#ifdef CONFIG_X86_64
55dd00a7
MT		 6483 case KVM_HC_CLOCK_PAIRING:
6484 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6485 break;
8ef81a9a 6486#endif
8776e519
HB		 6487 default:
6488 ret = -KVM_ENOSYS;
6489 break;
6490 }
07708c4a 6491out:
a449c7aa
NA		 6492 if (!op_64_bit)
6493 ret = (u32)ret;
5fdbf976 6494 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6495 ++vcpu->stat.hypercalls;
2f333bcb 6496 return r;
8776e519
HB		 6497}
6498EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6499
b6785def 6500static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6501{
d6aa1000 6502 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6503 char instruction[3];
5fdbf976 6504 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6505
8776e519 6506 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6507
ce2e852e
DV		 6508 return emulator_write_emulated(ctxt, rip, instruction, 3,
6509 &ctxt->exception);
8776e519
HB		 6510}
6511
851ba692 6512static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6513{
782d422b
MG		 6514 return vcpu->run->request_interrupt_window &&
6515 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6516}
6517
851ba692 6518static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6519{
851ba692
AK		 6520 struct kvm_run *kvm_run = vcpu->run;
6521
91586a3b 6522 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6523 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6524 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6525 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6526 kvm_run->ready_for_interrupt_injection =
6527 pic_in_kernel(vcpu->kvm) ||
782d422b 6528 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6529}
6530
95ba8273
GN		 6531static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6532{
6533 int max_irr, tpr;
6534
6535 if (!kvm_x86_ops->update_cr8_intercept)
6536 return;
6537
bce87cce 6538 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6539 return;
6540
d62caabb
AS		 6541 if (vcpu->arch.apicv_active)
6542 return;
6543
8db3baa2
GN		 6544 if (!vcpu->arch.apic->vapic_addr)
6545 max_irr = kvm_lapic_find_highest_irr(vcpu);
6546 else
6547 max_irr = -1;
95ba8273
GN		 6548
6549 if (max_irr != -1)
6550 max_irr >>= 4;
6551
6552 tpr = kvm_lapic_get_cr8(vcpu);
6553
6554 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6555}
6556
b6b8a145 6557static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6558{
b6b8a145
JK		 6559 int r;
6560
95ba8273 6561 /* try to reinject previous events if any */
664f8e26
WL		 6562 if (vcpu->arch.exception.injected) {
6563 kvm_x86_ops->queue_exception(vcpu);
6564 return 0;
6565 }
6566
6567 /*
6568 * Exceptions must be injected immediately, or the exception
6569 * frame will have the address of the NMI or interrupt handler.
6570 */
6571 if (!vcpu->arch.exception.pending) {
6572 if (vcpu->arch.nmi_injected) {
6573 kvm_x86_ops->set_nmi(vcpu);
6574 return 0;
6575 }
6576
6577 if (vcpu->arch.interrupt.pending) {
6578 kvm_x86_ops->set_irq(vcpu);
6579 return 0;
6580 }
6581 }
6582
6583 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6584 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6585 if (r != 0)
6586 return r;
6587 }
6588
6589 /* try to inject new event if pending */
b59bb7bd 6590 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6591 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6592 vcpu->arch.exception.has_error_code,
6593 vcpu->arch.exception.error_code);
d6e8c854 6594
664f8e26
WL		 6595 vcpu->arch.exception.pending = false;
6596 vcpu->arch.exception.injected = true;
6597
d6e8c854
NA		 6598 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6599 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6600 X86_EFLAGS_RF);
6601
6bdf0662
NA		 6602 if (vcpu->arch.exception.nr == DB_VECTOR &&
6603 (vcpu->arch.dr7 & DR7_GD)) {
6604 vcpu->arch.dr7 &= ~DR7_GD;
6605 kvm_update_dr7(vcpu);
6606 }
6607
cfcd20e5 6608 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6609 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6610 vcpu->arch.smi_pending = false;
52797bf9 6611 ++vcpu->arch.smi_count;
ee2cd4b7 6612 enter_smm(vcpu);
c43203ca 6613 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6614 --vcpu->arch.nmi_pending;
6615 vcpu->arch.nmi_injected = true;
6616 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6617 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6618 /*
6619 * Because interrupts can be injected asynchronously, we are
6620 * calling check_nested_events again here to avoid a race condition.
6621 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6622 * proposal and current concerns. Perhaps we should be setting
6623 * KVM_REQ_EVENT only on certain events and not unconditionally?
6624 */
6625 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6626 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6627 if (r != 0)
6628 return r;
6629 }
95ba8273 6630 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6631 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6632 false);
6633 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6634 }
6635 }
ee2cd4b7 6636
b6b8a145 6637 return 0;
95ba8273
GN		 6638}
6639
7460fb4a
AK		 6640static void process_nmi(struct kvm_vcpu *vcpu)
6641{
6642 unsigned limit = 2;
6643
6644 /*
6645 * x86 is limited to one NMI running, and one NMI pending after it.
6646 * If an NMI is already in progress, limit further NMIs to just one.
6647 * Otherwise, allow two (and we'll inject the first one immediately).
6648 */
6649 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6650 limit = 1;
6651
6652 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6653 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6654 kvm_make_request(KVM_REQ_EVENT, vcpu);
6655}
6656
ee2cd4b7 6657static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6658{
6659 u32 flags = 0;
6660 flags |= seg->g << 23;
6661 flags |= seg->db << 22;
6662 flags |= seg->l << 21;
6663 flags |= seg->avl << 20;
6664 flags |= seg->present << 15;
6665 flags |= seg->dpl << 13;
6666 flags |= seg->s << 12;
6667 flags |= seg->type << 8;
6668 return flags;
6669}
6670
ee2cd4b7 6671static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6672{
6673 struct kvm_segment seg;
6674 int offset;
6675
6676 kvm_get_segment(vcpu, &seg, n);
6677 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6678
6679 if (n < 3)
6680 offset = 0x7f84 + n * 12;
6681 else
6682 offset = 0x7f2c + (n - 3) * 12;
6683
6684 put_smstate(u32, buf, offset + 8, seg.base);
6685 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6686 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6687}
6688
efbb288a 6689#ifdef CONFIG_X86_64
ee2cd4b7 6690static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6691{
6692 struct kvm_segment seg;
6693 int offset;
6694 u16 flags;
6695
6696 kvm_get_segment(vcpu, &seg, n);
6697 offset = 0x7e00 + n * 16;
6698
ee2cd4b7 6699 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6700 put_smstate(u16, buf, offset, seg.selector);
6701 put_smstate(u16, buf, offset + 2, flags);
6702 put_smstate(u32, buf, offset + 4, seg.limit);
6703 put_smstate(u64, buf, offset + 8, seg.base);
6704}
efbb288a 6705#endif
660a5d51 6706
ee2cd4b7 6707static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6708{
6709 struct desc_ptr dt;
6710 struct kvm_segment seg;
6711 unsigned long val;
6712 int i;
6713
6714 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6715 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6716 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6717 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6718
6719 for (i = 0; i < 8; i++)
6720 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6721
6722 kvm_get_dr(vcpu, 6, &val);
6723 put_smstate(u32, buf, 0x7fcc, (u32)val);
6724 kvm_get_dr(vcpu, 7, &val);
6725 put_smstate(u32, buf, 0x7fc8, (u32)val);
6726
6727 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6728 put_smstate(u32, buf, 0x7fc4, seg.selector);
6729 put_smstate(u32, buf, 0x7f64, seg.base);
6730 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6731 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6732
6733 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6734 put_smstate(u32, buf, 0x7fc0, seg.selector);
6735 put_smstate(u32, buf, 0x7f80, seg.base);
6736 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6737 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6738
6739 kvm_x86_ops->get_gdt(vcpu, &dt);
6740 put_smstate(u32, buf, 0x7f74, dt.address);
6741 put_smstate(u32, buf, 0x7f70, dt.size);
6742
6743 kvm_x86_ops->get_idt(vcpu, &dt);
6744 put_smstate(u32, buf, 0x7f58, dt.address);
6745 put_smstate(u32, buf, 0x7f54, dt.size);
6746
6747 for (i = 0; i < 6; i++)
ee2cd4b7 6748 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6749
6750 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6751
6752 /* revision id */
6753 put_smstate(u32, buf, 0x7efc, 0x00020000);
6754 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6755}
6756
ee2cd4b7 6757static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6758{
6759#ifdef CONFIG_X86_64
6760 struct desc_ptr dt;
6761 struct kvm_segment seg;
6762 unsigned long val;
6763 int i;
6764
6765 for (i = 0; i < 16; i++)
6766 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6767
6768 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6769 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6770
6771 kvm_get_dr(vcpu, 6, &val);
6772 put_smstate(u64, buf, 0x7f68, val);
6773 kvm_get_dr(vcpu, 7, &val);
6774 put_smstate(u64, buf, 0x7f60, val);
6775
6776 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6777 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6778 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6779
6780 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6781
6782 /* revision id */
6783 put_smstate(u32, buf, 0x7efc, 0x00020064);
6784
6785 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6786
6787 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6788 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6789 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6790 put_smstate(u32, buf, 0x7e94, seg.limit);
6791 put_smstate(u64, buf, 0x7e98, seg.base);
6792
6793 kvm_x86_ops->get_idt(vcpu, &dt);
6794 put_smstate(u32, buf, 0x7e84, dt.size);
6795 put_smstate(u64, buf, 0x7e88, dt.address);
6796
6797 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6798 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6799 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6800 put_smstate(u32, buf, 0x7e74, seg.limit);
6801 put_smstate(u64, buf, 0x7e78, seg.base);
6802
6803 kvm_x86_ops->get_gdt(vcpu, &dt);
6804 put_smstate(u32, buf, 0x7e64, dt.size);
6805 put_smstate(u64, buf, 0x7e68, dt.address);
6806
6807 for (i = 0; i < 6; i++)
ee2cd4b7 6808 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6809#else
6810 WARN_ON_ONCE(1);
6811#endif
6812}
6813
ee2cd4b7 6814static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6815{
660a5d51 6816 struct kvm_segment cs, ds;
18c3626e 6817 struct desc_ptr dt;
660a5d51
PB		 6818 char buf[512];
6819 u32 cr0;
6820
660a5d51 6821 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6822 memset(buf, 0, 512);
d6321d49 6823 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6824 enter_smm_save_state_64(vcpu, buf);
660a5d51 6825 else
ee2cd4b7 6826 enter_smm_save_state_32(vcpu, buf);
660a5d51 6827
0234bf88
LP		 6828 /*
6829 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6830 * vCPU state (e.g. leave guest mode) after we've saved the state into
6831 * the SMM state-save area.
6832 */
6833 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6834
6835 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6836 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6837
6838 if (kvm_x86_ops->get_nmi_mask(vcpu))
6839 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6840 else
6841 kvm_x86_ops->set_nmi_mask(vcpu, true);
6842
6843 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6844 kvm_rip_write(vcpu, 0x8000);
6845
6846 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6847 kvm_x86_ops->set_cr0(vcpu, cr0);
6848 vcpu->arch.cr0 = cr0;
6849
6850 kvm_x86_ops->set_cr4(vcpu, 0);
6851
18c3626e
PB		 6852 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6853 dt.address = dt.size = 0;
6854 kvm_x86_ops->set_idt(vcpu, &dt);
6855
660a5d51
PB		 6856 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6857
6858 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6859 cs.base = vcpu->arch.smbase;
6860
6861 ds.selector = 0;
6862 ds.base = 0;
6863
6864 cs.limit = ds.limit = 0xffffffff;
6865 cs.type = ds.type = 0x3;
6866 cs.dpl = ds.dpl = 0;
6867 cs.db = ds.db = 0;
6868 cs.s = ds.s = 1;
6869 cs.l = ds.l = 0;
6870 cs.g = ds.g = 1;
6871 cs.avl = ds.avl = 0;
6872 cs.present = ds.present = 1;
6873 cs.unusable = ds.unusable = 0;
6874 cs.padding = ds.padding = 0;
6875
6876 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6877 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6878 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6879 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6880 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6881 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6882
d6321d49 6883 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6884 kvm_x86_ops->set_efer(vcpu, 0);
6885
6886 kvm_update_cpuid(vcpu);
6887 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6888}
6889
ee2cd4b7 6890static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6891{
6892 vcpu->arch.smi_pending = true;
6893 kvm_make_request(KVM_REQ_EVENT, vcpu);
6894}
6895
2860c4b1
PB		 6896void kvm_make_scan_ioapic_request(struct kvm *kvm)
6897{
6898 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6899}
6900
3d81bc7e 6901static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6902{
5c919412
AS		 6903 u64 eoi_exit_bitmap[4];
6904
3d81bc7e
YZ		 6905 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6906 return;
c7c9c56c 6907
6308630b 6908 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6909
b053b2ae 6910 if (irqchip_split(vcpu->kvm))
6308630b 6911 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6912 else {
fa59cc00 6913 if (vcpu->arch.apicv_active)
d62caabb 6914 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6915 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6916 }
5c919412
AS		 6917 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6918 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6919 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6920}
6921
b1394e74
RK		 6922void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6923 unsigned long start, unsigned long end)
6924{
6925 unsigned long apic_address;
6926
6927 /*
6928 * The physical address of apic access page is stored in the VMCS.
6929 * Update it when it becomes invalid.
6930 */
6931 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6932 if (start <= apic_address && apic_address < end)
6933 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6934}
6935
4256f43f
TC		 6936void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6937{
c24ae0dc
TC		 6938 struct page *page = NULL;
6939
35754c98 6940 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6941 return;
6942
4256f43f
TC		 6943 if (!kvm_x86_ops->set_apic_access_page_addr)
6944 return;
6945
c24ae0dc 6946 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6947 if (is_error_page(page))
6948 return;
c24ae0dc
TC		 6949 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6950
6951 /*
6952 * Do not pin apic access page in memory, the MMU notifier
6953 * will call us again if it is migrated or swapped out.
6954 */
6955 put_page(page);
4256f43f
TC		 6956}
6957EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6958
9357d939 6959/*
362c698f 6960 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6961 * exiting to the userspace. Otherwise, the value will be returned to the
6962 * userspace.
6963 */
851ba692 6964static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6965{
6966 int r;
62a193ed
MG		 6967 bool req_int_win =
6968 dm_request_for_irq_injection(vcpu) &&
6969 kvm_cpu_accept_dm_intr(vcpu);
6970
730dca42 6971 bool req_immediate_exit = false;
b6c7a5dc 6972
2fa6e1e1 6973 if (kvm_request_pending(vcpu)) {
a8eeb04a 6974 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6975 kvm_mmu_unload(vcpu);
a8eeb04a 6976 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6977 __kvm_migrate_timers(vcpu);
d828199e
MT		 6978 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6979 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6980 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6981 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6982 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6983 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6984 if (unlikely(r))
6985 goto out;
6986 }
a8eeb04a 6987 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6988 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6989 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 6990 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 6991 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6992 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6993 r = 0;
6994 goto out;
6995 }
a8eeb04a 6996 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6997 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6998 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6999 r = 0;
7000 goto out;
7001 }
af585b92
GN		 7002 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7003 /* Page is swapped out. Do synthetic halt */
7004 vcpu->arch.apf.halted = true;
7005 r = 1;
7006 goto out;
7007 }
c9aaa895
GC		 7008 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7009 record_steal_time(vcpu);
64d60670
PB		 7010 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7011 process_smi(vcpu);
7460fb4a
AK		 7012 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7013 process_nmi(vcpu);
f5132b01 7014 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7015 kvm_pmu_handle_event(vcpu);
f5132b01 7016 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7017 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7018 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7019 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7020 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7021 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7022 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7023 vcpu->run->eoi.vector =
7024 vcpu->arch.pending_ioapic_eoi;
7025 r = 0;
7026 goto out;
7027 }
7028 }
3d81bc7e
YZ		 7029 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7030 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 7031 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7032 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7033 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7034 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7035 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7036 r = 0;
7037 goto out;
7038 }
e516cebb
AS		 7039 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7040 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7041 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7042 r = 0;
7043 goto out;
7044 }
db397571
AS		 7045 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7046 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7047 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7048 r = 0;
7049 goto out;
7050 }
f3b138c5
AS		 7051
7052 /*
7053 * KVM_REQ_HV_STIMER has to be processed after
7054 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7055 * depend on the guest clock being up-to-date
7056 */
1f4b34f8
AS		 7057 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7058 kvm_hv_process_stimers(vcpu);
2f52d58c 7059 }
b93463aa 7060
b463a6f7 7061 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7062 ++vcpu->stat.req_event;
66450a21
JK		 7063 kvm_apic_accept_events(vcpu);
7064 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7065 r = 1;
7066 goto out;
7067 }
7068
b6b8a145
JK		 7069 if (inject_pending_event(vcpu, req_int_win) != 0)
7070 req_immediate_exit = true;
321c5658 7071 else {
cc3d967f 7072 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7073 *
cc3d967f
LP		 7074 * SMIs have three cases:
7075 * 1) They can be nested, and then there is nothing to
7076 * do here because RSM will cause a vmexit anyway.
7077 * 2) There is an ISA-specific reason why SMI cannot be
7078 * injected, and the moment when this changes can be
7079 * intercepted.
7080 * 3) Or the SMI can be pending because
7081 * inject_pending_event has completed the injection
7082 * of an IRQ or NMI from the previous vmexit, and
7083 * then we request an immediate exit to inject the
7084 * SMI.
c43203ca
PB		 7085 */
7086 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7087 if (!kvm_x86_ops->enable_smi_window(vcpu))
7088 req_immediate_exit = true;
321c5658
YS		 7089 if (vcpu->arch.nmi_pending)
7090 kvm_x86_ops->enable_nmi_window(vcpu);
7091 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7092 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7093 WARN_ON(vcpu->arch.exception.pending);
321c5658 7094 }
b463a6f7
AK		 7095
7096 if (kvm_lapic_enabled(vcpu)) {
7097 update_cr8_intercept(vcpu);
7098 kvm_lapic_sync_to_vapic(vcpu);
7099 }
7100 }
7101
d8368af8
AK		 7102 r = kvm_mmu_reload(vcpu);
7103 if (unlikely(r)) {
d905c069 7104 goto cancel_injection;
d8368af8
AK		 7105 }
7106
b6c7a5dc
HB		 7107 preempt_disable();
7108
7109 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7110
7111 /*
7112 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7113 * IPI are then delayed after guest entry, which ensures that they
7114 * result in virtual interrupt delivery.
7115 */
7116 local_irq_disable();
6b7e2d09
XG		 7117 vcpu->mode = IN_GUEST_MODE;
7118
01b71917
MT		 7119 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7120
0f127d12 7121 /*
b95234c8 7122 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7123 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7124 *
7125 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7126 * pairs with the memory barrier implicit in pi_test_and_set_on
7127 * (see vmx_deliver_posted_interrupt).
7128 *
7129 * 3) This also orders the write to mode from any reads to the page
7130 * tables done while the VCPU is running. Please see the comment
7131 * in kvm_flush_remote_tlbs.
6b7e2d09 7132 */
01b71917 7133 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7134
b95234c8
PB		 7135 /*
7136 * This handles the case where a posted interrupt was
7137 * notified with kvm_vcpu_kick.
7138 */
fa59cc00
LA		 7139 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7140 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7141
2fa6e1e1 7142 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7143 || need_resched() || signal_pending(current)) {
6b7e2d09 7144 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7145 smp_wmb();
6c142801
AK		 7146 local_irq_enable();
7147 preempt_enable();
01b71917 7148 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7149 r = 1;
d905c069 7150 goto cancel_injection;
6c142801
AK		 7151 }
7152
fc5b7f3b
DM		 7153 kvm_load_guest_xcr0(vcpu);
7154
c43203ca
PB		 7155 if (req_immediate_exit) {
7156 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7157 smp_send_reschedule(vcpu->cpu);
c43203ca 7158 }
d6185f20 7159
8b89fe1f 7160 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7161 if (lapic_timer_advance_ns)
7162 wait_lapic_expire(vcpu);
6edaa530 7163 guest_enter_irqoff();
b6c7a5dc 7164
42dbaa5a 7165 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7166 set_debugreg(0, 7);
7167 set_debugreg(vcpu->arch.eff_db[0], 0);
7168 set_debugreg(vcpu->arch.eff_db[1], 1);
7169 set_debugreg(vcpu->arch.eff_db[2], 2);
7170 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7171 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7172 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7173 }
b6c7a5dc 7174
851ba692 7175 kvm_x86_ops->run(vcpu);
b6c7a5dc 7176
c77fb5fe
PB		 7177 /*
7178 * Do this here before restoring debug registers on the host. And
7179 * since we do this before handling the vmexit, a DR access vmexit
7180 * can (a) read the correct value of the debug registers, (b) set
7181 * KVM_DEBUGREG_WONT_EXIT again.
7182 */
7183 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7184 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7185 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7186 kvm_update_dr0123(vcpu);
7187 kvm_update_dr6(vcpu);
7188 kvm_update_dr7(vcpu);
7189 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7190 }
7191
24f1e32c
FW		 7192 /*
7193 * If the guest has used debug registers, at least dr7
7194 * will be disabled while returning to the host.
7195 * If we don't have active breakpoints in the host, we don't
7196 * care about the messed up debug address registers. But if
7197 * we have some of them active, restore the old state.
7198 */
59d8eb53 7199 if (hw_breakpoint_active())
24f1e32c 7200 hw_breakpoint_restore();
42dbaa5a 7201
4ba76538 7202 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7203
6b7e2d09 7204 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7205 smp_wmb();
a547c6db 7206
fc5b7f3b
DM		 7207 kvm_put_guest_xcr0(vcpu);
7208
a547c6db 7209 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7210
7211 ++vcpu->stat.exits;
7212
f2485b3e 7213 guest_exit_irqoff();
b6c7a5dc 7214
f2485b3e 7215 local_irq_enable();
b6c7a5dc
HB		 7216 preempt_enable();
7217
f656ce01 7218 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7219
b6c7a5dc
HB		 7220 /*
7221 * Profile KVM exit RIPs:
7222 */
7223 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7224 unsigned long rip = kvm_rip_read(vcpu);
7225 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7226 }
7227
cc578287
ZA		 7228 if (unlikely(vcpu->arch.tsc_always_catchup))
7229 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7230
5cfb1d5a
MT		 7231 if (vcpu->arch.apic_attention)
7232 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7233
618232e2 7234 vcpu->arch.gpa_available = false;
851ba692 7235 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7236 return r;
7237
7238cancel_injection:
7239 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7240 if (unlikely(vcpu->arch.apic_attention))
7241 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7242out:
7243 return r;
7244}
b6c7a5dc 7245
362c698f
PB		 7246static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7247{
bf9f6ac8
FW		 7248 if (!kvm_arch_vcpu_runnable(vcpu) &&
7249 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7250 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7251 kvm_vcpu_block(vcpu);
7252 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7253
7254 if (kvm_x86_ops->post_block)
7255 kvm_x86_ops->post_block(vcpu);
7256
9c8fd1ba
PB		 7257 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7258 return 1;
7259 }
362c698f
PB		 7260
7261 kvm_apic_accept_events(vcpu);
7262 switch(vcpu->arch.mp_state) {
7263 case KVM_MP_STATE_HALTED:
7264 vcpu->arch.pv.pv_unhalted = false;
7265 vcpu->arch.mp_state =
7266 KVM_MP_STATE_RUNNABLE;
7267 case KVM_MP_STATE_RUNNABLE:
7268 vcpu->arch.apf.halted = false;
7269 break;
7270 case KVM_MP_STATE_INIT_RECEIVED:
7271 break;
7272 default:
7273 return -EINTR;
7274 break;
7275 }
7276 return 1;
7277}
09cec754 7278
5d9bc648
PB		 7279static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7280{
0ad3bed6
PB		 7281 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7282 kvm_x86_ops->check_nested_events(vcpu, false);
7283
5d9bc648
PB		 7284 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7285 !vcpu->arch.apf.halted);
7286}
7287
362c698f 7288static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7289{
7290 int r;
f656ce01 7291 struct kvm *kvm = vcpu->kvm;
d7690175 7292
f656ce01 7293 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7294
362c698f 7295 for (;;) {
58f800d5 7296 if (kvm_vcpu_running(vcpu)) {
851ba692 7297 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7298 } else {
362c698f 7299 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7300 }
7301
09cec754
GN		 7302 if (r <= 0)
7303 break;
7304
72875d8a 7305 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7306 if (kvm_cpu_has_pending_timer(vcpu))
7307 kvm_inject_pending_timer_irqs(vcpu);
7308
782d422b
MG		 7309 if (dm_request_for_irq_injection(vcpu) &&
7310 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7311 r = 0;
7312 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7313 ++vcpu->stat.request_irq_exits;
362c698f 7314 break;
09cec754 7315 }
af585b92
GN		 7316
7317 kvm_check_async_pf_completion(vcpu);
7318
09cec754
GN		 7319 if (signal_pending(current)) {
7320 r = -EINTR;
851ba692 7321 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7322 ++vcpu->stat.signal_exits;
362c698f 7323 break;
09cec754
GN		 7324 }
7325 if (need_resched()) {
f656ce01 7326 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7327 cond_resched();
f656ce01 7328 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7329 }
b6c7a5dc
HB		 7330 }
7331
f656ce01 7332 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7333
7334 return r;
7335}
7336
716d51ab
GN		 7337static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7338{
7339 int r;
7340 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7341 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7342 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7343 if (r != EMULATE_DONE)
7344 return 0;
7345 return 1;
7346}
7347
7348static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7349{
7350 BUG_ON(!vcpu->arch.pio.count);
7351
7352 return complete_emulated_io(vcpu);
7353}
7354
f78146b0
AK		 7355/*
7356 * Implements the following, as a state machine:
7357 *
7358 * read:
7359 * for each fragment
87da7e66
XG		 7360 * for each mmio piece in the fragment
7361 * write gpa, len
7362 * exit
7363 * copy data
f78146b0
AK		 7364 * execute insn
7365 *
7366 * write:
7367 * for each fragment
87da7e66
XG		 7368 * for each mmio piece in the fragment
7369 * write gpa, len
7370 * copy data
7371 * exit
f78146b0 7372 */
716d51ab 7373static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7374{
7375 struct kvm_run *run = vcpu->run;
f78146b0 7376 struct kvm_mmio_fragment *frag;
87da7e66 7377 unsigned len;
5287f194 7378
716d51ab 7379 BUG_ON(!vcpu->mmio_needed);
5287f194 7380
716d51ab 7381 /* Complete previous fragment */
87da7e66
XG		 7382 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7383 len = min(8u, frag->len);
716d51ab 7384 if (!vcpu->mmio_is_write)
87da7e66
XG		 7385 memcpy(frag->data, run->mmio.data, len);
7386
7387 if (frag->len <= 8) {
7388 /* Switch to the next fragment. */
7389 frag++;
7390 vcpu->mmio_cur_fragment++;
7391 } else {
7392 /* Go forward to the next mmio piece. */
7393 frag->data += len;
7394 frag->gpa += len;
7395 frag->len -= len;
7396 }
7397
a08d3b3b 7398 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7399 vcpu->mmio_needed = 0;
0912c977
PB		 7400
7401 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7402 if (vcpu->mmio_is_write)
716d51ab
GN		 7403 return 1;
7404 vcpu->mmio_read_completed = 1;
7405 return complete_emulated_io(vcpu);
7406 }
87da7e66 7407
716d51ab
GN		 7408 run->exit_reason = KVM_EXIT_MMIO;
7409 run->mmio.phys_addr = frag->gpa;
7410 if (vcpu->mmio_is_write)
87da7e66
XG		 7411 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7412 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7413 run->mmio.is_write = vcpu->mmio_is_write;
7414 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7415 return 0;
5287f194
AK		 7416}
7417
716d51ab 7418
b6c7a5dc
HB		 7419int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7420{
7421 int r;
b6c7a5dc 7422
accb757d 7423 vcpu_load(vcpu);
20b7035c 7424 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7425 kvm_load_guest_fpu(vcpu);
7426
a4535290 7427 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7428 if (kvm_run->immediate_exit) {
7429 r = -EINTR;
7430 goto out;
7431 }
b6c7a5dc 7432 kvm_vcpu_block(vcpu);
66450a21 7433 kvm_apic_accept_events(vcpu);
72875d8a 7434 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7435 r = -EAGAIN;
a0595000
JS		 7436 if (signal_pending(current)) {
7437 r = -EINTR;
7438 vcpu->run->exit_reason = KVM_EXIT_INTR;
7439 ++vcpu->stat.signal_exits;
7440 }
ac9f6dc0 7441 goto out;
b6c7a5dc
HB		 7442 }
7443
b6c7a5dc 7444 /* re-sync apic's tpr */
35754c98 7445 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7446 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7447 r = -EINVAL;
7448 goto out;
7449 }
7450 }
b6c7a5dc 7451
716d51ab
GN		 7452 if (unlikely(vcpu->arch.complete_userspace_io)) {
7453 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7454 vcpu->arch.complete_userspace_io = NULL;
7455 r = cui(vcpu);
7456 if (r <= 0)
5663d8f9 7457 goto out;
716d51ab
GN		 7458 } else
7459 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7460
460df4c1
PB		 7461 if (kvm_run->immediate_exit)
7462 r = -EINTR;
7463 else
7464 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7465
7466out:
5663d8f9 7467 kvm_put_guest_fpu(vcpu);
f1d86e46 7468 post_kvm_run_save(vcpu);
20b7035c 7469 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7470
accb757d 7471 vcpu_put(vcpu);
b6c7a5dc
HB		 7472 return r;
7473}
7474
7475int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7476{
1fc9b76b
CD		 7477 vcpu_load(vcpu);
7478
7ae441ea
GN		 7479 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7480 /*
7481 * We are here if userspace calls get_regs() in the middle of
7482 * instruction emulation. Registers state needs to be copied
4a969980 7483 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7484 * that usually, but some bad designed PV devices (vmware
7485 * backdoor interface) need this to work
7486 */
dd856efa 7487 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7488 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7489 }
5fdbf976
MT		 7490 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7491 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7492 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7493 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7494 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7495 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7496 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7497 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7498#ifdef CONFIG_X86_64
5fdbf976
MT		 7499 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7500 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7501 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7502 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7503 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7504 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7505 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7506 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7507#endif
7508
5fdbf976 7509 regs->rip = kvm_rip_read(vcpu);
91586a3b 7510 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7511
1fc9b76b 7512 vcpu_put(vcpu);
b6c7a5dc
HB		 7513 return 0;
7514}
7515
7516int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7517{
875656fe
CD		 7518 vcpu_load(vcpu);
7519
7ae441ea
GN		 7520 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7521 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7522
5fdbf976
MT		 7523 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7524 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7525 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7526 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7527 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7528 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7529 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7530 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7531#ifdef CONFIG_X86_64
5fdbf976
MT		 7532 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7533 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7534 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7535 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7536 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7537 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7538 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7539 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7540#endif
7541
5fdbf976 7542 kvm_rip_write(vcpu, regs->rip);
d73235d1 7543 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7544
b4f14abd
JK		 7545 vcpu->arch.exception.pending = false;
7546
3842d135
AK		 7547 kvm_make_request(KVM_REQ_EVENT, vcpu);
7548
875656fe 7549 vcpu_put(vcpu);
b6c7a5dc
HB		 7550 return 0;
7551}
7552
b6c7a5dc
HB		 7553void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7554{
7555 struct kvm_segment cs;
7556
3e6e0aab 7557 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7558 *db = cs.db;
7559 *l = cs.l;
7560}
7561EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7562
7563int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7564 struct kvm_sregs *sregs)
7565{
89a27f4d 7566 struct desc_ptr dt;
b6c7a5dc 7567
bcdec41c
CD		 7568 vcpu_load(vcpu);
7569
3e6e0aab
GT		 7570 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7571 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7572 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7573 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7574 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7575 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7576
3e6e0aab
GT		 7577 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7578 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7579
7580 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7581 sregs->idt.limit = dt.size;
7582 sregs->idt.base = dt.address;
b6c7a5dc 7583 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7584 sregs->gdt.limit = dt.size;
7585 sregs->gdt.base = dt.address;
b6c7a5dc 7586
4d4ec087 7587 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7588 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7589 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7590 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7591 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7592 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7593 sregs->apic_base = kvm_get_apic_base(vcpu);
7594
923c61bb 7595 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7596
36752c9b 7597 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7598 set_bit(vcpu->arch.interrupt.nr,
7599 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7600
bcdec41c 7601 vcpu_put(vcpu);
b6c7a5dc
HB		 7602 return 0;
7603}
7604
62d9f0db
MT		 7605int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7606 struct kvm_mp_state *mp_state)
7607{
fd232561
CD		 7608 vcpu_load(vcpu);
7609
66450a21 7610 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7611 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7612 vcpu->arch.pv.pv_unhalted)
7613 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7614 else
7615 mp_state->mp_state = vcpu->arch.mp_state;
7616
fd232561 7617 vcpu_put(vcpu);
62d9f0db
MT		 7618 return 0;
7619}
7620
7621int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7622 struct kvm_mp_state *mp_state)
7623{
e83dff5e
CD		 7624 int ret = -EINVAL;
7625
7626 vcpu_load(vcpu);
7627
bce87cce 7628 if (!lapic_in_kernel(vcpu) &&
66450a21 7629 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7630 goto out;
66450a21 7631
28bf2888
DH		 7632 /* INITs are latched while in SMM */
7633 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7634 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7635 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7636 goto out;
28bf2888 7637
66450a21
JK		 7638 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7639 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7640 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7641 } else
7642 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7643 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7644
7645 ret = 0;
7646out:
7647 vcpu_put(vcpu);
7648 return ret;
62d9f0db
MT		 7649}
7650
7f3d35fd
KW		 7651int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7652 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7653{
9d74191a 7654 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7655 int ret;
e01c2426 7656
8ec4722d 7657 init_emulate_ctxt(vcpu);
c697518a 7658
7f3d35fd 7659 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7660 has_error_code, error_code);
c697518a 7661
c697518a 7662 if (ret)
19d04437 7663 return EMULATE_FAIL;
37817f29 7664
9d74191a
TY		 7665 kvm_rip_write(vcpu, ctxt->eip);
7666 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7667 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7668 return EMULATE_DONE;
37817f29
IE		 7669}
7670EXPORT_SYMBOL_GPL(kvm_task_switch);
7671
f2981033
LT		 7672int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7673{
37b95951 7674 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7675 /*
7676 * When EFER.LME and CR0.PG are set, the processor is in
7677 * 64-bit mode (though maybe in a 32-bit code segment).
7678 * CR4.PAE and EFER.LMA must be set.
7679 */
37b95951 7680 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7681 || !(sregs->efer & EFER_LMA))
7682 return -EINVAL;
7683 } else {
7684 /*
7685 * Not in 64-bit mode: EFER.LMA is clear and the code
7686 * segment cannot be 64-bit.
7687 */
7688 if (sregs->efer & EFER_LMA || sregs->cs.l)
7689 return -EINVAL;
7690 }
7691
7692 return 0;
7693}
7694
b6c7a5dc
HB		 7695int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7696 struct kvm_sregs *sregs)
7697{
58cb628d 7698 struct msr_data apic_base_msr;
b6c7a5dc 7699 int mmu_reset_needed = 0;
63f42e02 7700 int pending_vec, max_bits, idx;
89a27f4d 7701 struct desc_ptr dt;
b4ef9d4e
CD		 7702 int ret = -EINVAL;
7703
7704 vcpu_load(vcpu);
b6c7a5dc 7705
d6321d49
RK		 7706 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7707 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7708 goto out;
6d1068b3 7709
f2981033 7710 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7711 goto out;
f2981033 7712
d3802286
JM		 7713 apic_base_msr.data = sregs->apic_base;
7714 apic_base_msr.host_initiated = true;
7715 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7716 goto out;
6d1068b3 7717
89a27f4d
GN		 7718 dt.size = sregs->idt.limit;
7719 dt.address = sregs->idt.base;
b6c7a5dc 7720 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7721 dt.size = sregs->gdt.limit;
7722 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7723 kvm_x86_ops->set_gdt(vcpu, &dt);
7724
ad312c7c 7725 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7726 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7727 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7728 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7729
2d3ad1f4 7730 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7731
f6801dff 7732 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7733 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7734
4d4ec087 7735 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7736 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7737 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7738
fc78f519 7739 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7740 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7741 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7742 kvm_update_cpuid(vcpu);
63f42e02
XG		 7743
7744 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7745 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7746 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7747 mmu_reset_needed = 1;
7748 }
63f42e02 7749 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7750
7751 if (mmu_reset_needed)
7752 kvm_mmu_reset_context(vcpu);
7753
a50abc3b 7754 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7755 pending_vec = find_first_bit(
7756 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7757 if (pending_vec < max_bits) {
66fd3f7f 7758 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7759 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7760 }
7761
3e6e0aab
GT		 7762 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7763 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7764 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7765 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7766 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7767 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7768
3e6e0aab
GT		 7769 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7770 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7771
5f0269f5
ME		 7772 update_cr8_intercept(vcpu);
7773
9c3e4aab 7774 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7775 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7776 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7777 !is_protmode(vcpu))
9c3e4aab
MT		 7778 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7779
3842d135
AK		 7780 kvm_make_request(KVM_REQ_EVENT, vcpu);
7781
b4ef9d4e
CD		 7782 ret = 0;
7783out:
7784 vcpu_put(vcpu);
7785 return ret;
b6c7a5dc
HB		 7786}
7787
d0bfb940
JK		 7788int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7789 struct kvm_guest_debug *dbg)
b6c7a5dc 7790{
355be0b9 7791 unsigned long rflags;
ae675ef0 7792 int i, r;
b6c7a5dc 7793
66b56562
CD		 7794 vcpu_load(vcpu);
7795
4f926bf2
JK		 7796 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7797 r = -EBUSY;
7798 if (vcpu->arch.exception.pending)
2122ff5e 7799 goto out;
4f926bf2
JK		 7800 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7801 kvm_queue_exception(vcpu, DB_VECTOR);
7802 else
7803 kvm_queue_exception(vcpu, BP_VECTOR);
7804 }
7805
91586a3b
JK		 7806 /*
7807 * Read rflags as long as potentially injected trace flags are still
7808 * filtered out.
7809 */
7810 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7811
7812 vcpu->guest_debug = dbg->control;
7813 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7814 vcpu->guest_debug = 0;
7815
7816 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7817 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7818 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7819 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7820 } else {
7821 for (i = 0; i < KVM_NR_DB_REGS; i++)
7822 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7823 }
c8639010 7824 kvm_update_dr7(vcpu);
ae675ef0 7825
f92653ee
JK		 7826 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7827 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7828 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7829
91586a3b
JK		 7830 /*
7831 * Trigger an rflags update that will inject or remove the trace
7832 * flags.
7833 */
7834 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7835
a96036b8 7836 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7837
4f926bf2 7838 r = 0;
d0bfb940 7839
2122ff5e 7840out:
66b56562 7841 vcpu_put(vcpu);
b6c7a5dc
HB		 7842 return r;
7843}
7844
8b006791
ZX		 7845/*
7846 * Translate a guest virtual address to a guest physical address.
7847 */
7848int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7849 struct kvm_translation *tr)
7850{
7851 unsigned long vaddr = tr->linear_address;
7852 gpa_t gpa;
f656ce01 7853 int idx;
8b006791 7854
1da5b61d
CD		 7855 vcpu_load(vcpu);
7856
f656ce01 7857 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7858 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7859 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7860 tr->physical_address = gpa;
7861 tr->valid = gpa != UNMAPPED_GVA;
7862 tr->writeable = 1;
7863 tr->usermode = 0;
8b006791 7864
1da5b61d 7865 vcpu_put(vcpu);
8b006791
ZX		 7866 return 0;
7867}
7868
d0752060
HB		 7869int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7870{
1393123e 7871 struct fxregs_state *fxsave;
d0752060 7872
1393123e 7873 vcpu_load(vcpu);
d0752060 7874
1393123e 7875 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 7876 memcpy(fpu->fpr, fxsave->st_space, 128);
7877 fpu->fcw = fxsave->cwd;
7878 fpu->fsw = fxsave->swd;
7879 fpu->ftwx = fxsave->twd;
7880 fpu->last_opcode = fxsave->fop;
7881 fpu->last_ip = fxsave->rip;
7882 fpu->last_dp = fxsave->rdp;
7883 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7884
1393123e 7885 vcpu_put(vcpu);
d0752060
HB		 7886 return 0;
7887}
7888
7889int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7890{
6a96bc7f
CD		 7891 struct fxregs_state *fxsave;
7892
7893 vcpu_load(vcpu);
7894
7895 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7896
d0752060
HB		 7897 memcpy(fxsave->st_space, fpu->fpr, 128);
7898 fxsave->cwd = fpu->fcw;
7899 fxsave->swd = fpu->fsw;
7900 fxsave->twd = fpu->ftwx;
7901 fxsave->fop = fpu->last_opcode;
7902 fxsave->rip = fpu->last_ip;
7903 fxsave->rdp = fpu->last_dp;
7904 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7905
6a96bc7f 7906 vcpu_put(vcpu);
d0752060
HB		 7907 return 0;
7908}
7909
0ee6a517 7910static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7911{
bf935b0b 7912 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7913 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7914 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7915 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7916
2acf923e
DC		 7917 /*
7918 * Ensure guest xcr0 is valid for loading
7919 */
d91cab78 7920 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7921
ad312c7c 7922 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7923}
d0752060 7924
f775b13e 7925/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7926void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7927{
f775b13e
RR		 7928 preempt_disable();
7929 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7930 /* PKRU is separately restored in kvm_x86_ops->run. */
7931 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7932 ~XFEATURE_MASK_PKRU);
f775b13e 7933 preempt_enable();
0c04851c 7934 trace_kvm_fpu(1);
d0752060 7935}
d0752060 7936
f775b13e 7937/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 7938void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7939{
f775b13e 7940 preempt_disable();
4f836347 7941 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 7942 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7943 preempt_enable();
f096ed85 7944 ++vcpu->stat.fpu_reload;
0c04851c 7945 trace_kvm_fpu(0);
d0752060 7946}
e9b11c17
ZX		 7947
7948void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7949{
bd768e14
IY		 7950 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7951
12f9a48f 7952 kvmclock_reset(vcpu);
7f1ea208 7953
e9b11c17 7954 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7955 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7956}
7957
7958struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7959 unsigned int id)
7960{
c447e76b
LL		 7961 struct kvm_vcpu *vcpu;
7962
b0c39dc6 7963 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 7964 printk_once(KERN_WARNING
7965 "kvm: SMP vm created on host with unstable TSC; "
7966 "guest TSC will not be reliable\n");
c447e76b
LL		 7967
7968 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7969
c447e76b 7970 return vcpu;
26e5215f 7971}
e9b11c17 7972
26e5215f
AK		 7973int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7974{
19efffa2 7975 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 7976 vcpu_load(vcpu);
d28bc9dd 7977 kvm_vcpu_reset(vcpu, false);
0b2e9904 7978 kvm_lapic_reset(vcpu, false);
8a3c1a33 7979 kvm_mmu_setup(vcpu);
e9b11c17 7980 vcpu_put(vcpu);
ec7660cc 7981 return 0;
e9b11c17
ZX		 7982}
7983
31928aa5 7984void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7985{
8fe8ab46 7986 struct msr_data msr;
332967a3 7987 struct kvm *kvm = vcpu->kvm;
42897d86 7988
d3457c87
RK		 7989 kvm_hv_vcpu_postcreate(vcpu);
7990
ec7660cc 7991 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 7992 return;
ec7660cc 7993 vcpu_load(vcpu);
8fe8ab46
WA		 7994 msr.data = 0x0;
7995 msr.index = MSR_IA32_TSC;
7996 msr.host_initiated = true;
7997 kvm_write_tsc(vcpu, &msr);
42897d86 7998 vcpu_put(vcpu);
ec7660cc 7999 mutex_unlock(&vcpu->mutex);
42897d86 8000
630994b3
MT		 8001 if (!kvmclock_periodic_sync)
8002 return;
8003
332967a3
AJ		 8004 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8005 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8006}
8007
d40ccc62 8008void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8009{
344d9588
GN		 8010 vcpu->arch.apf.msr_val = 0;
8011
ec7660cc 8012 vcpu_load(vcpu);
e9b11c17
ZX		 8013 kvm_mmu_unload(vcpu);
8014 vcpu_put(vcpu);
8015
8016 kvm_x86_ops->vcpu_free(vcpu);
8017}
8018
d28bc9dd 8019void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8020{
e69fab5d
PB		 8021 vcpu->arch.hflags = 0;
8022
c43203ca 8023 vcpu->arch.smi_pending = 0;
52797bf9 8024 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8025 atomic_set(&vcpu->arch.nmi_queued, 0);
8026 vcpu->arch.nmi_pending = 0;
448fa4a9 8027 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8028 kvm_clear_interrupt_queue(vcpu);
8029 kvm_clear_exception_queue(vcpu);
664f8e26 8030 vcpu->arch.exception.pending = false;
448fa4a9 8031
42dbaa5a 8032 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8033 kvm_update_dr0123(vcpu);
6f43ed01 8034 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8035 kvm_update_dr6(vcpu);
42dbaa5a 8036 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8037 kvm_update_dr7(vcpu);
42dbaa5a 8038
1119022c
NA		 8039 vcpu->arch.cr2 = 0;
8040
3842d135 8041 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8042 vcpu->arch.apf.msr_val = 0;
c9aaa895 8043 vcpu->arch.st.msr_val = 0;
3842d135 8044
12f9a48f
GC		 8045 kvmclock_reset(vcpu);
8046
af585b92
GN		 8047 kvm_clear_async_pf_completion_queue(vcpu);
8048 kvm_async_pf_hash_reset(vcpu);
8049 vcpu->arch.apf.halted = false;
3842d135 8050
a554d207
WL		 8051 if (kvm_mpx_supported()) {
8052 void *mpx_state_buffer;
8053
8054 /*
8055 * To avoid have the INIT path from kvm_apic_has_events() that be
8056 * called with loaded FPU and does not let userspace fix the state.
8057 */
f775b13e
RR		 8058 if (init_event)
8059 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8060 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8061 XFEATURE_MASK_BNDREGS);
8062 if (mpx_state_buffer)
8063 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8064 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8065 XFEATURE_MASK_BNDCSR);
8066 if (mpx_state_buffer)
8067 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8068 if (init_event)
8069 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8070 }
8071
64d60670 8072 if (!init_event) {
d28bc9dd 8073 kvm_pmu_reset(vcpu);
64d60670 8074 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8075
8076 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8077 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8078
8079 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8080 }
f5132b01 8081
66f7b72e
JS		 8082 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8083 vcpu->arch.regs_avail = ~0;
8084 vcpu->arch.regs_dirty = ~0;
8085
a554d207
WL		 8086 vcpu->arch.ia32_xss = 0;
8087
d28bc9dd 8088 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8089}
8090
2b4a273b 8091void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8092{
8093 struct kvm_segment cs;
8094
8095 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8096 cs.selector = vector << 8;
8097 cs.base = vector << 12;
8098 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8099 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8100}
8101
13a34e06 8102int kvm_arch_hardware_enable(void)
e9b11c17 8103{
ca84d1a2
ZA		 8104 struct kvm *kvm;
8105 struct kvm_vcpu *vcpu;
8106 int i;
0dd6a6ed
ZA		 8107 int ret;
8108 u64 local_tsc;
8109 u64 max_tsc = 0;
8110 bool stable, backwards_tsc = false;
18863bdd
AK		 8111
8112 kvm_shared_msr_cpu_online();
13a34e06 8113 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8114 if (ret != 0)
8115 return ret;
8116
4ea1636b 8117 local_tsc = rdtsc();
b0c39dc6 8118 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8119 list_for_each_entry(kvm, &vm_list, vm_list) {
8120 kvm_for_each_vcpu(i, vcpu, kvm) {
8121 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8122 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8123 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8124 backwards_tsc = true;
8125 if (vcpu->arch.last_host_tsc > max_tsc)
8126 max_tsc = vcpu->arch.last_host_tsc;
8127 }
8128 }
8129 }
8130
8131 /*
8132 * Sometimes, even reliable TSCs go backwards. This happens on
8133 * platforms that reset TSC during suspend or hibernate actions, but
8134 * maintain synchronization. We must compensate. Fortunately, we can
8135 * detect that condition here, which happens early in CPU bringup,
8136 * before any KVM threads can be running. Unfortunately, we can't
8137 * bring the TSCs fully up to date with real time, as we aren't yet far
8138 * enough into CPU bringup that we know how much real time has actually
108b249c 8139 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8140 * variables that haven't been updated yet.
8141 *
8142 * So we simply find the maximum observed TSC above, then record the
8143 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8144 * the adjustment will be applied. Note that we accumulate
8145 * adjustments, in case multiple suspend cycles happen before some VCPU
8146 * gets a chance to run again. In the event that no KVM threads get a
8147 * chance to run, we will miss the entire elapsed period, as we'll have
8148 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8149 * loose cycle time. This isn't too big a deal, since the loss will be
8150 * uniform across all VCPUs (not to mention the scenario is extremely
8151 * unlikely). It is possible that a second hibernate recovery happens
8152 * much faster than a first, causing the observed TSC here to be
8153 * smaller; this would require additional padding adjustment, which is
8154 * why we set last_host_tsc to the local tsc observed here.
8155 *
8156 * N.B. - this code below runs only on platforms with reliable TSC,
8157 * as that is the only way backwards_tsc is set above. Also note
8158 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8159 * have the same delta_cyc adjustment applied if backwards_tsc
8160 * is detected. Note further, this adjustment is only done once,
8161 * as we reset last_host_tsc on all VCPUs to stop this from being
8162 * called multiple times (one for each physical CPU bringup).
8163 *
4a969980 8164 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8165 * will be compensated by the logic in vcpu_load, which sets the TSC to
8166 * catchup mode. This will catchup all VCPUs to real time, but cannot
8167 * guarantee that they stay in perfect synchronization.
8168 */
8169 if (backwards_tsc) {
8170 u64 delta_cyc = max_tsc - local_tsc;
8171 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8172 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8173 kvm_for_each_vcpu(i, vcpu, kvm) {
8174 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8175 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8176 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8177 }
8178
8179 /*
8180 * We have to disable TSC offset matching.. if you were
8181 * booting a VM while issuing an S4 host suspend....
8182 * you may have some problem. Solving this issue is
8183 * left as an exercise to the reader.
8184 */
8185 kvm->arch.last_tsc_nsec = 0;
8186 kvm->arch.last_tsc_write = 0;
8187 }
8188
8189 }
8190 return 0;
e9b11c17
ZX		 8191}
8192
13a34e06 8193void kvm_arch_hardware_disable(void)
e9b11c17 8194{
13a34e06
RK		 8195 kvm_x86_ops->hardware_disable();
8196 drop_user_return_notifiers();
e9b11c17
ZX		 8197}
8198
8199int kvm_arch_hardware_setup(void)
8200{
9e9c3fe4
NA		 8201 int r;
8202
8203 r = kvm_x86_ops->hardware_setup();
8204 if (r != 0)
8205 return r;
8206
35181e86
HZ		 8207 if (kvm_has_tsc_control) {
8208 /*
8209 * Make sure the user can only configure tsc_khz values that
8210 * fit into a signed integer.
8211 * A min value is not calculated needed because it will always
8212 * be 1 on all machines.
8213 */
8214 u64 max = min(0x7fffffffULL,
8215 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8216 kvm_max_guest_tsc_khz = max;
8217
ad721883 8218 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8219 }
ad721883 8220
9e9c3fe4
NA		 8221 kvm_init_msr_list();
8222 return 0;
e9b11c17
ZX		 8223}
8224
8225void kvm_arch_hardware_unsetup(void)
8226{
8227 kvm_x86_ops->hardware_unsetup();
8228}
8229
8230void kvm_arch_check_processor_compat(void *rtn)
8231{
8232 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8233}
8234
8235bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8236{
8237 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8238}
8239EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8240
8241bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8242{
8243 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8244}
8245
54e9818f 8246struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8247EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8248
e9b11c17
ZX		 8249int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8250{
8251 struct page *page;
e9b11c17
ZX		 8252 int r;
8253
b2a05fef 8254 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8255 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8256 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8257 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8258 else
a4535290 8259 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8260
8261 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8262 if (!page) {
8263 r = -ENOMEM;
8264 goto fail;
8265 }
ad312c7c 8266 vcpu->arch.pio_data = page_address(page);
e9b11c17 8267
cc578287 8268 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8269
e9b11c17
ZX		 8270 r = kvm_mmu_create(vcpu);
8271 if (r < 0)
8272 goto fail_free_pio_data;
8273
26de7988 8274 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8275 r = kvm_create_lapic(vcpu);
8276 if (r < 0)
8277 goto fail_mmu_destroy;
54e9818f
GN		 8278 } else
8279 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8280
890ca9ae
HY		 8281 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8282 GFP_KERNEL);
8283 if (!vcpu->arch.mce_banks) {
8284 r = -ENOMEM;
443c39bc 8285 goto fail_free_lapic;
890ca9ae
HY		 8286 }
8287 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8288
f1797359
WY		 8289 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8290 r = -ENOMEM;
f5f48ee1 8291 goto fail_free_mce_banks;
f1797359 8292 }
f5f48ee1 8293
0ee6a517 8294 fx_init(vcpu);
66f7b72e 8295
4344ee98 8296 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8297
5a4f55cd
EK		 8298 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8299
74545705
RK		 8300 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8301
af585b92 8302 kvm_async_pf_hash_reset(vcpu);
f5132b01 8303 kvm_pmu_init(vcpu);
af585b92 8304
1c1a9ce9 8305 vcpu->arch.pending_external_vector = -1;
de63ad4c 8306 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8307
5c919412
AS		 8308 kvm_hv_vcpu_init(vcpu);
8309
e9b11c17 8310 return 0;
0ee6a517 8311
f5f48ee1
SY		 8312fail_free_mce_banks:
8313 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8314fail_free_lapic:
8315 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8316fail_mmu_destroy:
8317 kvm_mmu_destroy(vcpu);
8318fail_free_pio_data:
ad312c7c 8319 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8320fail:
8321 return r;
8322}
8323
8324void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8325{
f656ce01
MT		 8326 int idx;
8327
1f4b34f8 8328 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8329 kvm_pmu_destroy(vcpu);
36cb93fd 8330 kfree(vcpu->arch.mce_banks);
e9b11c17 8331 kvm_free_lapic(vcpu);
f656ce01 8332 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8333 kvm_mmu_destroy(vcpu);
f656ce01 8334 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8335 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8336 if (!lapic_in_kernel(vcpu))
54e9818f 8337 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8338}
d19a9cd2 8339
e790d9ef
RK		 8340void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8341{
ae97a3b8 8342 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8343}
8344
e08b9637 8345int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8346{
e08b9637
CO		 8347 if (type)
8348 return -EINVAL;
8349
6ef768fa 8350 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8351 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8352 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8353 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8354 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8355
5550af4d
SY		 8356 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8357 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8358 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8359 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8360 &kvm->arch.irq_sources_bitmap);
5550af4d 8361
038f8c11 8362 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8363 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8364 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8365 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8366
108b249c 8367 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8368 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8369
7e44e449 8370 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8371 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8372
0eb05bf2 8373 kvm_page_track_init(kvm);
13d268ca 8374 kvm_mmu_init_vm(kvm);
0eb05bf2 8375
03543133
SS		 8376 if (kvm_x86_ops->vm_init)
8377 return kvm_x86_ops->vm_init(kvm);
8378
d89f5eff 8379 return 0;
d19a9cd2
ZX		 8380}
8381
8382static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8383{
ec7660cc 8384 vcpu_load(vcpu);
d19a9cd2
ZX		 8385 kvm_mmu_unload(vcpu);
8386 vcpu_put(vcpu);
8387}
8388
8389static void kvm_free_vcpus(struct kvm *kvm)
8390{
8391 unsigned int i;
988a2cae 8392 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8393
8394 /*
8395 * Unpin any mmu pages first.
8396 */
af585b92
GN		 8397 kvm_for_each_vcpu(i, vcpu, kvm) {
8398 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8399 kvm_unload_vcpu_mmu(vcpu);
af585b92 8400 }
988a2cae
GN		 8401 kvm_for_each_vcpu(i, vcpu, kvm)
8402 kvm_arch_vcpu_free(vcpu);
8403
8404 mutex_lock(&kvm->lock);
8405 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8406 kvm->vcpus[i] = NULL;
d19a9cd2 8407
988a2cae
GN		 8408 atomic_set(&kvm->online_vcpus, 0);
8409 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8410}
8411
ad8ba2cd
SY		 8412void kvm_arch_sync_events(struct kvm *kvm)
8413{
332967a3 8414 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8415 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8416 kvm_free_pit(kvm);
ad8ba2cd
SY		 8417}
8418
1d8007bd 8419int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8420{
8421 int i, r;
25188b99 8422 unsigned long hva;
f0d648bd
PB		 8423 struct kvm_memslots *slots = kvm_memslots(kvm);
8424 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8425
8426 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8427 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8428 return -EINVAL;
9da0e4d5 8429
f0d648bd
PB		 8430 slot = id_to_memslot(slots, id);
8431 if (size) {
b21629da 8432 if (slot->npages)
f0d648bd
PB		 8433 return -EEXIST;
8434
8435 /*
8436 * MAP_SHARED to prevent internal slot pages from being moved
8437 * by fork()/COW.
8438 */
8439 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8440 MAP_SHARED | MAP_ANONYMOUS, 0);
8441 if (IS_ERR((void *)hva))
8442 return PTR_ERR((void *)hva);
8443 } else {
8444 if (!slot->npages)
8445 return 0;
8446
8447 hva = 0;
8448 }
8449
8450 old = *slot;
9da0e4d5 8451 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8452 struct kvm_userspace_memory_region m;
9da0e4d5 8453
1d8007bd
PB		 8454 m.slot = id | (i << 16);
8455 m.flags = 0;
8456 m.guest_phys_addr = gpa;
f0d648bd 8457 m.userspace_addr = hva;
1d8007bd 8458 m.memory_size = size;
9da0e4d5
PB		 8459 r = __kvm_set_memory_region(kvm, &m);
8460 if (r < 0)
8461 return r;
8462 }
8463
103c763c
EB		 8464 if (!size)
8465 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8466
9da0e4d5
PB		 8467 return 0;
8468}
8469EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8470
1d8007bd 8471int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8472{
8473 int r;
8474
8475 mutex_lock(&kvm->slots_lock);
1d8007bd 8476 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8477 mutex_unlock(&kvm->slots_lock);
8478
8479 return r;
8480}
8481EXPORT_SYMBOL_GPL(x86_set_memory_region);
8482
d19a9cd2
ZX		 8483void kvm_arch_destroy_vm(struct kvm *kvm)
8484{
27469d29
AH		 8485 if (current->mm == kvm->mm) {
8486 /*
8487 * Free memory regions allocated on behalf of userspace,
8488 * unless the the memory map has changed due to process exit
8489 * or fd copying.
8490 */
1d8007bd
PB		 8491 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8492 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8493 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8494 }
03543133
SS		 8495 if (kvm_x86_ops->vm_destroy)
8496 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8497 kvm_pic_destroy(kvm);
8498 kvm_ioapic_destroy(kvm);
d19a9cd2 8499 kvm_free_vcpus(kvm);
af1bae54 8500 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8501 kvm_mmu_uninit_vm(kvm);
2beb6dad 8502 kvm_page_track_cleanup(kvm);
d19a9cd2 8503}
0de10343 8504
5587027c 8505void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8506 struct kvm_memory_slot *dont)
8507{
8508 int i;
8509
d89cc617
TY		 8510 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8511 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8512 kvfree(free->arch.rmap[i]);
d89cc617 8513 free->arch.rmap[i] = NULL;
77d11309 8514 }
d89cc617
TY		 8515 if (i == 0)
8516 continue;
8517
8518 if (!dont || free->arch.lpage_info[i - 1] !=
8519 dont->arch.lpage_info[i - 1]) {
548ef284 8520 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8521 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8522 }
8523 }
21ebbeda
XG		 8524
8525 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8526}
8527
5587027c
AK		 8528int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8529 unsigned long npages)
db3fe4eb
TY		 8530{
8531 int i;
8532
d89cc617 8533 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8534 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8535 unsigned long ugfn;
8536 int lpages;
d89cc617 8537 int level = i + 1;
db3fe4eb
TY		 8538
8539 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8540 slot->base_gfn, level) + 1;
8541
d89cc617 8542 slot->arch.rmap[i] =
a7c3e901 8543 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8544 if (!slot->arch.rmap[i])
77d11309 8545 goto out_free;
d89cc617
TY		 8546 if (i == 0)
8547 continue;
77d11309 8548
a7c3e901 8549 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8550 if (!linfo)
db3fe4eb
TY		 8551 goto out_free;
8552
92f94f1e
XG		 8553 slot->arch.lpage_info[i - 1] = linfo;
8554
db3fe4eb 8555 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8556 linfo[0].disallow_lpage = 1;
db3fe4eb 8557 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8558 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8559 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8560 /*
8561 * If the gfn and userspace address are not aligned wrt each
8562 * other, or if explicitly asked to, disable large page
8563 * support for this slot
8564 */
8565 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8566 !kvm_largepages_enabled()) {
8567 unsigned long j;
8568
8569 for (j = 0; j < lpages; ++j)
92f94f1e 8570 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8571 }
8572 }
8573
21ebbeda
XG		 8574 if (kvm_page_track_create_memslot(slot, npages))
8575 goto out_free;
8576
db3fe4eb
TY		 8577 return 0;
8578
8579out_free:
d89cc617 8580 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8581 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8582 slot->arch.rmap[i] = NULL;
8583 if (i == 0)
8584 continue;
8585
548ef284 8586 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8587 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8588 }
8589 return -ENOMEM;
8590}
8591
15f46015 8592void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8593{
e6dff7d1
TY		 8594 /*
8595 * memslots->generation has been incremented.
8596 * mmio generation may have reached its maximum value.
8597 */
54bf36aa 8598 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8599}
8600
f7784b8e
MT		 8601int kvm_arch_prepare_memory_region(struct kvm *kvm,
8602 struct kvm_memory_slot *memslot,
09170a49 8603 const struct kvm_userspace_memory_region *mem,
7b6195a9 8604 enum kvm_mr_change change)
0de10343 8605{
f7784b8e
MT		 8606 return 0;
8607}
8608
88178fd4
KH		 8609static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8610 struct kvm_memory_slot *new)
8611{
8612 /* Still write protect RO slot */
8613 if (new->flags & KVM_MEM_READONLY) {
8614 kvm_mmu_slot_remove_write_access(kvm, new);
8615 return;
8616 }
8617
8618 /*
8619 * Call kvm_x86_ops dirty logging hooks when they are valid.
8620 *
8621 * kvm_x86_ops->slot_disable_log_dirty is called when:
8622 *
8623 * - KVM_MR_CREATE with dirty logging is disabled
8624 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8625 *
8626 * The reason is, in case of PML, we need to set D-bit for any slots
8627 * with dirty logging disabled in order to eliminate unnecessary GPA
8628 * logging in PML buffer (and potential PML buffer full VMEXT). This
8629 * guarantees leaving PML enabled during guest's lifetime won't have
8630 * any additonal overhead from PML when guest is running with dirty
8631 * logging disabled for memory slots.
8632 *
8633 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8634 * to dirty logging mode.
8635 *
8636 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8637 *
8638 * In case of write protect:
8639 *
8640 * Write protect all pages for dirty logging.
8641 *
8642 * All the sptes including the large sptes which point to this
8643 * slot are set to readonly. We can not create any new large
8644 * spte on this slot until the end of the logging.
8645 *
8646 * See the comments in fast_page_fault().
8647 */
8648 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8649 if (kvm_x86_ops->slot_enable_log_dirty)
8650 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8651 else
8652 kvm_mmu_slot_remove_write_access(kvm, new);
8653 } else {
8654 if (kvm_x86_ops->slot_disable_log_dirty)
8655 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8656 }
8657}
8658
f7784b8e 8659void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8660 const struct kvm_userspace_memory_region *mem,
8482644a 8661 const struct kvm_memory_slot *old,
f36f3f28 8662 const struct kvm_memory_slot *new,
8482644a 8663 enum kvm_mr_change change)
f7784b8e 8664{
8482644a 8665 int nr_mmu_pages = 0;
f7784b8e 8666
48c0e4e9
XG		 8667 if (!kvm->arch.n_requested_mmu_pages)
8668 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8669
48c0e4e9 8670 if (nr_mmu_pages)
0de10343 8671 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8672
3ea3b7fa
WL		 8673 /*
8674 * Dirty logging tracks sptes in 4k granularity, meaning that large
8675 * sptes have to be split. If live migration is successful, the guest
8676 * in the source machine will be destroyed and large sptes will be
8677 * created in the destination. However, if the guest continues to run
8678 * in the source machine (for example if live migration fails), small
8679 * sptes will remain around and cause bad performance.
8680 *
8681 * Scan sptes if dirty logging has been stopped, dropping those
8682 * which can be collapsed into a single large-page spte. Later
8683 * page faults will create the large-page sptes.
8684 */
8685 if ((change != KVM_MR_DELETE) &&
8686 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8687 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8688 kvm_mmu_zap_collapsible_sptes(kvm, new);
8689
c972f3b1 8690 /*
88178fd4 8691 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8692 *
88178fd4
KH		 8693 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8694 * been zapped so no dirty logging staff is needed for old slot. For
8695 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8696 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8697 *
8698 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8699 */
88178fd4 8700 if (change != KVM_MR_DELETE)
f36f3f28 8701 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8702}
1d737c8a 8703
2df72e9b 8704void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8705{
6ca18b69 8706 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8707}
8708
2df72e9b
MT		 8709void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8710 struct kvm_memory_slot *slot)
8711{
ae7cd873 8712 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8713}
8714
5d9bc648
PB		 8715static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8716{
8717 if (!list_empty_careful(&vcpu->async_pf.done))
8718 return true;
8719
8720 if (kvm_apic_has_events(vcpu))
8721 return true;
8722
8723 if (vcpu->arch.pv.pv_unhalted)
8724 return true;
8725
a5f01f8e
WL		 8726 if (vcpu->arch.exception.pending)
8727 return true;
8728
47a66eed
Z		 8729 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8730 (vcpu->arch.nmi_pending &&
8731 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8732 return true;
8733
47a66eed
Z		 8734 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8735 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8736 return true;
8737
5d9bc648
PB		 8738 if (kvm_arch_interrupt_allowed(vcpu) &&
8739 kvm_cpu_has_interrupt(vcpu))
8740 return true;
8741
1f4b34f8
AS		 8742 if (kvm_hv_has_stimer_pending(vcpu))
8743 return true;
8744
5d9bc648
PB		 8745 return false;
8746}
8747
1d737c8a
ZX		 8748int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8749{
5d9bc648 8750 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8751}
5736199a 8752
199b5763
LM		 8753bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8754{
de63ad4c 8755 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8756}
8757
b6d33834 8758int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8759{
b6d33834 8760 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8761}
78646121
GN		 8762
8763int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8764{
8765 return kvm_x86_ops->interrupt_allowed(vcpu);
8766}
229456fc 8767
82b32774 8768unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8769{
82b32774
NA		 8770 if (is_64_bit_mode(vcpu))
8771 return kvm_rip_read(vcpu);
8772 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8773 kvm_rip_read(vcpu));
8774}
8775EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8776
82b32774
NA		 8777bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8778{
8779 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8780}
8781EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8782
94fe45da
JK		 8783unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8784{
8785 unsigned long rflags;
8786
8787 rflags = kvm_x86_ops->get_rflags(vcpu);
8788 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8789 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8790 return rflags;
8791}
8792EXPORT_SYMBOL_GPL(kvm_get_rflags);
8793
6addfc42 8794static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8795{
8796 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8797 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8798 rflags |= X86_EFLAGS_TF;
94fe45da 8799 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8800}
8801
8802void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8803{
8804 __kvm_set_rflags(vcpu, rflags);
3842d135 8805 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8806}
8807EXPORT_SYMBOL_GPL(kvm_set_rflags);
8808
56028d08
GN		 8809void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8810{
8811 int r;
8812
fb67e14f 8813 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8814 work->wakeup_all)
56028d08
GN		 8815 return;
8816
8817 r = kvm_mmu_reload(vcpu);
8818 if (unlikely(r))
8819 return;
8820
fb67e14f
XG		 8821 if (!vcpu->arch.mmu.direct_map &&
8822 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8823 return;
8824
56028d08
GN		 8825 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8826}
8827
af585b92
GN		 8828static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8829{
8830 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8831}
8832
8833static inline u32 kvm_async_pf_next_probe(u32 key)
8834{
8835 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8836}
8837
8838static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8839{
8840 u32 key = kvm_async_pf_hash_fn(gfn);
8841
8842 while (vcpu->arch.apf.gfns[key] != ~0)
8843 key = kvm_async_pf_next_probe(key);
8844
8845 vcpu->arch.apf.gfns[key] = gfn;
8846}
8847
8848static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8849{
8850 int i;
8851 u32 key = kvm_async_pf_hash_fn(gfn);
8852
8853 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8854 (vcpu->arch.apf.gfns[key] != gfn &&
8855 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8856 key = kvm_async_pf_next_probe(key);
8857
8858 return key;
8859}
8860
8861bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8862{
8863 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8864}
8865
8866static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8867{
8868 u32 i, j, k;
8869
8870 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8871 while (true) {
8872 vcpu->arch.apf.gfns[i] = ~0;
8873 do {
8874 j = kvm_async_pf_next_probe(j);
8875 if (vcpu->arch.apf.gfns[j] == ~0)
8876 return;
8877 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8878 /*
8879 * k lies cyclically in ]i,j]
8880 * | i.k.j |
8881 * |....j i.k.| or |.k..j i...|
8882 */
8883 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8884 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8885 i = j;
8886 }
8887}
8888
7c90705b
GN		 8889static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8890{
4e335d9e
PB		 8891
8892 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8893 sizeof(val));
7c90705b
GN		 8894}
8895
9a6e7c39
WL		 8896static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8897{
8898
8899 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8900 sizeof(u32));
8901}
8902
af585b92
GN		 8903void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8904 struct kvm_async_pf *work)
8905{
6389ee94
AK		 8906 struct x86_exception fault;
8907
7c90705b 8908 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8909 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8910
8911 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8912 (vcpu->arch.apf.send_user_only &&
8913 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8914 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8915 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8916 fault.vector = PF_VECTOR;
8917 fault.error_code_valid = true;
8918 fault.error_code = 0;
8919 fault.nested_page_fault = false;
8920 fault.address = work->arch.token;
adfe20fb 8921 fault.async_page_fault = true;
6389ee94 8922 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8923 }
af585b92
GN		 8924}
8925
8926void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8927 struct kvm_async_pf *work)
8928{
6389ee94 8929 struct x86_exception fault;
9a6e7c39 8930 u32 val;
6389ee94 8931
f2e10669 8932 if (work->wakeup_all)
7c90705b
GN		 8933 work->arch.token = ~0; /* broadcast wakeup */
8934 else
8935 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8936 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8937
9a6e7c39
WL		 8938 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8939 !apf_get_user(vcpu, &val)) {
8940 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8941 vcpu->arch.exception.pending &&
8942 vcpu->arch.exception.nr == PF_VECTOR &&
8943 !apf_put_user(vcpu, 0)) {
8944 vcpu->arch.exception.injected = false;
8945 vcpu->arch.exception.pending = false;
8946 vcpu->arch.exception.nr = 0;
8947 vcpu->arch.exception.has_error_code = false;
8948 vcpu->arch.exception.error_code = 0;
8949 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8950 fault.vector = PF_VECTOR;
8951 fault.error_code_valid = true;
8952 fault.error_code = 0;
8953 fault.nested_page_fault = false;
8954 fault.address = work->arch.token;
8955 fault.async_page_fault = true;
8956 kvm_inject_page_fault(vcpu, &fault);
8957 }
7c90705b 8958 }
e6d53e3b 8959 vcpu->arch.apf.halted = false;
a4fa1635 8960 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8961}
8962
8963bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8964{
8965 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8966 return true;
8967 else
9bc1f09f 8968 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8969}
8970
5544eb9b
PB		 8971void kvm_arch_start_assignment(struct kvm *kvm)
8972{
8973 atomic_inc(&kvm->arch.assigned_device_count);
8974}
8975EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8976
8977void kvm_arch_end_assignment(struct kvm *kvm)
8978{
8979 atomic_dec(&kvm->arch.assigned_device_count);
8980}
8981EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8982
8983bool kvm_arch_has_assigned_device(struct kvm *kvm)
8984{
8985 return atomic_read(&kvm->arch.assigned_device_count);
8986}
8987EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8988
e0f0bbc5
AW		 8989void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8990{
8991 atomic_inc(&kvm->arch.noncoherent_dma_count);
8992}
8993EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8994
8995void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8996{
8997 atomic_dec(&kvm->arch.noncoherent_dma_count);
8998}
8999EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9000
9001bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9002{
9003 return atomic_read(&kvm->arch.noncoherent_dma_count);
9004}
9005EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9006
14717e20
AW		 9007bool kvm_arch_has_irq_bypass(void)
9008{
9009 return kvm_x86_ops->update_pi_irte != NULL;
9010}
9011
87276880
FW		 9012int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9013 struct irq_bypass_producer *prod)
9014{
9015 struct kvm_kernel_irqfd *irqfd =
9016 container_of(cons, struct kvm_kernel_irqfd, consumer);
9017
14717e20 9018 irqfd->producer = prod;
87276880 9019
14717e20
AW		 9020 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9021 prod->irq, irqfd->gsi, 1);
87276880
FW		 9022}
9023
9024void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9025 struct irq_bypass_producer *prod)
9026{
9027 int ret;
9028 struct kvm_kernel_irqfd *irqfd =
9029 container_of(cons, struct kvm_kernel_irqfd, consumer);
9030
87276880
FW		 9031 WARN_ON(irqfd->producer != prod);
9032 irqfd->producer = NULL;
9033
9034 /*
9035 * When producer of consumer is unregistered, we change back to
9036 * remapped mode, so we can re-use the current implementation
bb3541f1 9037 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9038 * int this case doesn't want to receive the interrupts.
9039 */
9040 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9041 if (ret)
9042 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9043 " fails: %d\n", irqfd->consumer.token, ret);
9044}
9045
9046int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9047 uint32_t guest_irq, bool set)
9048{
9049 if (!kvm_x86_ops->update_pi_irte)
9050 return -EINVAL;
9051
9052 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9053}
9054
52004014
FW		 9055bool kvm_vector_hashing_enabled(void)
9056{
9057 return vector_hashing;
9058}
9059EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9060
229456fc 9061EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9062EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9063EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9064EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9065EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9066EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9067EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9068EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9069EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9070EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9071EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9072EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9073EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9074EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9075EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9076EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9077EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9078EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9079EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)