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Merge tag 'kvm-s390-next-4.12-3' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
893590c7 137static bool __read_mostly backwards_tsc_observed = false;
16a96021 138
18863bdd
AK		 139#define KVM_NR_SHARED_MSRS 16
140
141struct kvm_shared_msrs_global {
142 int nr;
2bf78fa7 143 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 144};
145
146struct kvm_shared_msrs {
147 struct user_return_notifier urn;
148 bool registered;
2bf78fa7
SY		 149 struct kvm_shared_msr_values {
150 u64 host;
151 u64 curr;
152 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 153};
154
155static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 156static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 157
417bc304 158struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 159 { "pf_fixed", VCPU_STAT(pf_fixed) },
160 { "pf_guest", VCPU_STAT(pf_guest) },
161 { "tlb_flush", VCPU_STAT(tlb_flush) },
162 { "invlpg", VCPU_STAT(invlpg) },
163 { "exits", VCPU_STAT(exits) },
164 { "io_exits", VCPU_STAT(io_exits) },
165 { "mmio_exits", VCPU_STAT(mmio_exits) },
166 { "signal_exits", VCPU_STAT(signal_exits) },
167 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 168 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 169 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 170 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 171 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 172 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 173 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 174 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 175 { "request_irq", VCPU_STAT(request_irq_exits) },
176 { "irq_exits", VCPU_STAT(irq_exits) },
177 { "host_state_reload", VCPU_STAT(host_state_reload) },
178 { "efer_reload", VCPU_STAT(efer_reload) },
179 { "fpu_reload", VCPU_STAT(fpu_reload) },
180 { "insn_emulation", VCPU_STAT(insn_emulation) },
181 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 182 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 183 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 184 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 185 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
186 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
187 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
188 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
189 { "mmu_flooded", VM_STAT(mmu_flooded) },
190 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 191 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 192 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 193 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 194 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 195 { "max_mmu_page_hash_collisions",
196 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 197 { NULL }
198};
199
2acf923e
DC		 200u64 __read_mostly host_xcr0;
201
b6785def 202static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 203
af585b92
GN		 204static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
205{
206 int i;
207 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
208 vcpu->arch.apf.gfns[i] = ~0;
209}
210
18863bdd
AK		 211static void kvm_on_user_return(struct user_return_notifier *urn)
212{
213 unsigned slot;
18863bdd
AK		 214 struct kvm_shared_msrs *locals
215 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 216 struct kvm_shared_msr_values *values;
1650b4eb
IA		 217 unsigned long flags;
218
219 /*
220 * Disabling irqs at this point since the following code could be
221 * interrupted and executed through kvm_arch_hardware_disable()
222 */
223 local_irq_save(flags);
224 if (locals->registered) {
225 locals->registered = false;
226 user_return_notifier_unregister(urn);
227 }
228 local_irq_restore(flags);
18863bdd 229 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 230 values = &locals->values[slot];
231 if (values->host != values->curr) {
232 wrmsrl(shared_msrs_global.msrs[slot], values->host);
233 values->curr = values->host;
18863bdd
AK		 234 }
235 }
18863bdd
AK		 236}
237
2bf78fa7 238static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 239{
18863bdd 240 u64 value;
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 243
2bf78fa7
SY		 244 /* only read, and nobody should modify it at this time,
245 * so don't need lock */
246 if (slot >= shared_msrs_global.nr) {
247 printk(KERN_ERR "kvm: invalid MSR slot!");
248 return;
249 }
250 rdmsrl_safe(msr, &value);
251 smsr->values[slot].host = value;
252 smsr->values[slot].curr = value;
253}
254
255void kvm_define_shared_msr(unsigned slot, u32 msr)
256{
0123be42 257 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 258 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 259 if (slot >= shared_msrs_global.nr)
260 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 261}
262EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
263
264static void kvm_shared_msr_cpu_online(void)
265{
266 unsigned i;
18863bdd
AK		 267
268 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 269 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 270}
271
8b3c3104 272int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 273{
013f6a5d
MT		 274 unsigned int cpu = smp_processor_id();
275 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 276 int err;
18863bdd 277
2bf78fa7 278 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 279 return 0;
2bf78fa7 280 smsr->values[slot].curr = value;
8b3c3104
AH		 281 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
282 if (err)
283 return 1;
284
18863bdd
AK		 285 if (!smsr->registered) {
286 smsr->urn.on_user_return = kvm_on_user_return;
287 user_return_notifier_register(&smsr->urn);
288 smsr->registered = true;
289 }
8b3c3104 290 return 0;
18863bdd
AK		 291}
292EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
293
13a34e06 294static void drop_user_return_notifiers(void)
3548bab5 295{
013f6a5d
MT		 296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 298
299 if (smsr->registered)
300 kvm_on_user_return(&smsr->urn);
301}
302
6866b83e
CO		 303u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
304{
8a5a87d9 305 return vcpu->arch.apic_base;
6866b83e
CO		 306}
307EXPORT_SYMBOL_GPL(kvm_get_apic_base);
308
58cb628d
JK		 309int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
310{
311 u64 old_state = vcpu->arch.apic_base &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 new_state = msr_info->data &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
316 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
317
318 if (!msr_info->host_initiated &&
319 ((msr_info->data & reserved_bits) != 0 ||
320 new_state == X2APIC_ENABLE ||
321 (new_state == MSR_IA32_APICBASE_ENABLE &&
322 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
323 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
324 old_state == 0)))
325 return 1;
326
327 kvm_lapic_set_base(vcpu, msr_info->data);
328 return 0;
6866b83e
CO		 329}
330EXPORT_SYMBOL_GPL(kvm_set_apic_base);
331
2605fc21 332asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 333{
334 /* Fault while not rebooting. We want the trace. */
335 BUG();
336}
337EXPORT_SYMBOL_GPL(kvm_spurious_fault);
338
3fd28fce
ED		 339#define EXCPT_BENIGN 0
340#define EXCPT_CONTRIBUTORY 1
341#define EXCPT_PF 2
342
343static int exception_class(int vector)
344{
345 switch (vector) {
346 case PF_VECTOR:
347 return EXCPT_PF;
348 case DE_VECTOR:
349 case TS_VECTOR:
350 case NP_VECTOR:
351 case SS_VECTOR:
352 case GP_VECTOR:
353 return EXCPT_CONTRIBUTORY;
354 default:
355 break;
356 }
357 return EXCPT_BENIGN;
358}
359
d6e8c854
NA		 360#define EXCPT_FAULT 0
361#define EXCPT_TRAP 1
362#define EXCPT_ABORT 2
363#define EXCPT_INTERRUPT 3
364
365static int exception_type(int vector)
366{
367 unsigned int mask;
368
369 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
370 return EXCPT_INTERRUPT;
371
372 mask = 1 << vector;
373
374 /* #DB is trap, as instruction watchpoints are handled elsewhere */
375 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
376 return EXCPT_TRAP;
377
378 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
379 return EXCPT_ABORT;
380
381 /* Reserved exceptions will result in fault */
382 return EXCPT_FAULT;
383}
384
3fd28fce 385static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 386 unsigned nr, bool has_error, u32 error_code,
387 bool reinject)
3fd28fce
ED		 388{
389 u32 prev_nr;
390 int class1, class2;
391
3842d135
AK		 392 kvm_make_request(KVM_REQ_EVENT, vcpu);
393
3fd28fce
ED		 394 if (!vcpu->arch.exception.pending) {
395 queue:
3ffb2468
NA		 396 if (has_error && !is_protmode(vcpu))
397 has_error = false;
3fd28fce
ED		 398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = has_error;
400 vcpu->arch.exception.nr = nr;
401 vcpu->arch.exception.error_code = error_code;
3f0fd292 402 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 403 return;
404 }
405
406 /* to check exception */
407 prev_nr = vcpu->arch.exception.nr;
408 if (prev_nr == DF_VECTOR) {
409 /* triple fault -> shutdown */
a8eeb04a 410 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 411 return;
412 }
413 class1 = exception_class(prev_nr);
414 class2 = exception_class(nr);
415 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
416 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
417 /* generate double fault per SDM Table 5-5 */
418 vcpu->arch.exception.pending = true;
419 vcpu->arch.exception.has_error_code = true;
420 vcpu->arch.exception.nr = DF_VECTOR;
421 vcpu->arch.exception.error_code = 0;
422 } else
423 /* replace previous exception with a new one in a hope
424 that instruction re-execution will regenerate lost
425 exception */
426 goto queue;
427}
428
298101da
AK		 429void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
430{
ce7ddec4 431 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 432}
433EXPORT_SYMBOL_GPL(kvm_queue_exception);
434
ce7ddec4
JR		 435void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
436{
437 kvm_multiple_exception(vcpu, nr, false, 0, true);
438}
439EXPORT_SYMBOL_GPL(kvm_requeue_exception);
440
6affcbed 441int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 442{
db8fcefa
AP		 443 if (err)
444 kvm_inject_gp(vcpu, 0);
445 else
6affcbed
KH		 446 return kvm_skip_emulated_instruction(vcpu);
447
448 return 1;
db8fcefa
AP		 449}
450EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 451
6389ee94 452void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 453{
454 ++vcpu->stat.pf_guest;
6389ee94
AK		 455 vcpu->arch.cr2 = fault->address;
456 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 457}
27d6c865 458EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 459
ef54bcfe 460static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 461{
6389ee94
AK		 462 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
463 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 464 else
6389ee94 465 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 466
467 return fault->nested_page_fault;
d4f8cf66
JR		 468}
469
3419ffc8
SY		 470void kvm_inject_nmi(struct kvm_vcpu *vcpu)
471{
7460fb4a
AK		 472 atomic_inc(&vcpu->arch.nmi_queued);
473 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 474}
475EXPORT_SYMBOL_GPL(kvm_inject_nmi);
476
298101da
AK		 477void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
478{
ce7ddec4 479 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 480}
481EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
482
ce7ddec4
JR		 483void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
484{
485 kvm_multiple_exception(vcpu, nr, true, error_code, true);
486}
487EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
488
0a79b009
AK		 489/*
490 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
491 * a #GP and return false.
492 */
493bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 494{
0a79b009
AK		 495 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
496 return true;
497 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
498 return false;
298101da 499}
0a79b009 500EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 501
16f8a6f9
NA		 502bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
503{
504 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
505 return true;
506
507 kvm_queue_exception(vcpu, UD_VECTOR);
508 return false;
509}
510EXPORT_SYMBOL_GPL(kvm_require_dr);
511
ec92fe44
JR		 512/*
513 * This function will be used to read from the physical memory of the currently
54bf36aa 514 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 515 * can read from guest physical or from the guest's guest physical memory.
516 */
517int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
518 gfn_t ngfn, void *data, int offset, int len,
519 u32 access)
520{
54987b7a 521 struct x86_exception exception;
ec92fe44
JR		 522 gfn_t real_gfn;
523 gpa_t ngpa;
524
525 ngpa = gfn_to_gpa(ngfn);
54987b7a 526 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 527 if (real_gfn == UNMAPPED_GVA)
528 return -EFAULT;
529
530 real_gfn = gpa_to_gfn(real_gfn);
531
54bf36aa 532 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 533}
534EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
535
69b0049a 536static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 537 void *data, int offset, int len, u32 access)
538{
539 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
540 data, offset, len, access);
541}
542
a03490ed
CO		 543/*
544 * Load the pae pdptrs. Return true is they are all valid.
545 */
ff03a073 546int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 547{
548 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
549 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
550 int i;
551 int ret;
ff03a073 552 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 553
ff03a073
JR		 554 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
555 offset * sizeof(u64), sizeof(pdpte),
556 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 557 if (ret < 0) {
558 ret = 0;
559 goto out;
560 }
561 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 562 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 563 (pdpte[i] &
564 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 565 ret = 0;
566 goto out;
567 }
568 }
569 ret = 1;
570
ff03a073 571 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail);
574 __set_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 576out:
a03490ed
CO		 577
578 return ret;
579}
cc4b6871 580EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 581
9ed38ffa 582bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 583{
ff03a073 584 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 585 bool changed = true;
3d06b8bf
JR		 586 int offset;
587 gfn_t gfn;
d835dfec
AK		 588 int r;
589
590 if (is_long_mode(vcpu) || !is_pae(vcpu))
591 return false;
592
6de4f3ad
AK		 593 if (!test_bit(VCPU_EXREG_PDPTR,
594 (unsigned long *)&vcpu->arch.regs_avail))
595 return true;
596
9f8fe504
AK		 597 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
598 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 599 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
600 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 601 if (r < 0)
602 goto out;
ff03a073 603 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 604out:
d835dfec
AK		 605
606 return changed;
607}
9ed38ffa 608EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 609
49a9b07e 610int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 611{
aad82703 612 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 613 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 614
f9a48e6a
AK		 615 cr0 |= X86_CR0_ET;
616
ab344828 617#ifdef CONFIG_X86_64
0f12244f
GN		 618 if (cr0 & 0xffffffff00000000UL)
619 return 1;
ab344828
GN		 620#endif
621
622 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 623
0f12244f
GN		 624 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
625 return 1;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
628 return 1;
a03490ed
CO		 629
630 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
631#ifdef CONFIG_X86_64
f6801dff 632 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 633 int cs_db, cs_l;
634
0f12244f
GN		 635 if (!is_pae(vcpu))
636 return 1;
a03490ed 637 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 638 if (cs_l)
639 return 1;
a03490ed
CO		 640 } else
641#endif
ff03a073 642 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 643 kvm_read_cr3(vcpu)))
0f12244f 644 return 1;
a03490ed
CO		 645 }
646
ad756a16
MJ		 647 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
648 return 1;
649
a03490ed 650 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 651
d170c419 652 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 653 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 654 kvm_async_pf_hash_reset(vcpu);
655 }
e5f3f027 656
aad82703
SY		 657 if ((cr0 ^ old_cr0) & update_bits)
658 kvm_mmu_reset_context(vcpu);
b18d5431 659
879ae188
LE		 660 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
661 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
662 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 663 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
664
0f12244f
GN		 665 return 0;
666}
2d3ad1f4 667EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 668
2d3ad1f4 669void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 670{
49a9b07e 671 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 674
42bdf991
MT		 675static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
676{
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
678 !vcpu->guest_xcr0_loaded) {
679 /* kvm_set_xcr() also depends on this */
680 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
681 vcpu->guest_xcr0_loaded = 1;
682 }
683}
684
685static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
686{
687 if (vcpu->guest_xcr0_loaded) {
688 if (vcpu->arch.xcr0 != host_xcr0)
689 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
690 vcpu->guest_xcr0_loaded = 0;
691 }
692}
693
69b0049a 694static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 695{
56c103ec
LJ		 696 u64 xcr0 = xcr;
697 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 698 u64 valid_bits;
2acf923e
DC		 699
700 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
701 if (index != XCR_XFEATURE_ENABLED_MASK)
702 return 1;
d91cab78 703 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 704 return 1;
d91cab78 705 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 706 return 1;
46c34cb0
PB		 707
708 /*
709 * Do not allow the guest to set bits that we do not support
710 * saving. However, xcr0 bit 0 is always set, even if the
711 * emulated CPU does not support XSAVE (see fx_init).
712 */
d91cab78 713 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 714 if (xcr0 & ~valid_bits)
2acf923e 715 return 1;
46c34cb0 716
d91cab78
DH		 717 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
718 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 719 return 1;
720
d91cab78
DH		 721 if (xcr0 & XFEATURE_MASK_AVX512) {
722 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 723 return 1;
d91cab78 724 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 725 return 1;
726 }
2acf923e 727 vcpu->arch.xcr0 = xcr0;
56c103ec 728
d91cab78 729 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 730 kvm_update_cpuid(vcpu);
2acf923e
DC		 731 return 0;
732}
733
734int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
735{
764bcbc5
Z		 736 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
737 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 738 kvm_inject_gp(vcpu, 0);
739 return 1;
740 }
741 return 0;
742}
743EXPORT_SYMBOL_GPL(kvm_set_xcr);
744
a83b29c6 745int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 746{
fc78f519 747 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 748 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 749 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 750
0f12244f
GN		 751 if (cr4 & CR4_RESERVED_BITS)
752 return 1;
a03490ed 753
2acf923e
DC		 754 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
755 return 1;
756
c68b734f
YW		 757 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
758 return 1;
759
97ec8c06
FW		 760 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
761 return 1;
762
afcbf13f 763 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 764 return 1;
765
b9baba86
HH		 766 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
767 return 1;
768
a03490ed 769 if (is_long_mode(vcpu)) {
0f12244f
GN		 770 if (!(cr4 & X86_CR4_PAE))
771 return 1;
a2edf57f
AK		 772 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
773 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 774 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 kvm_read_cr3(vcpu)))
0f12244f
GN		 776 return 1;
777
ad756a16
MJ		 778 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
779 if (!guest_cpuid_has_pcid(vcpu))
780 return 1;
781
782 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
783 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
784 return 1;
785 }
786
5e1746d6 787 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 788 return 1;
a03490ed 789
ad756a16
MJ		 790 if (((cr4 ^ old_cr4) & pdptr_bits) ||
791 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 792 kvm_mmu_reset_context(vcpu);
0f12244f 793
b9baba86 794 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 795 kvm_update_cpuid(vcpu);
2acf923e 796
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 800
2390218b 801int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 802{
ac146235 803#ifdef CONFIG_X86_64
9d88fca7 804 cr3 &= ~CR3_PCID_INVD;
ac146235 805#endif
9d88fca7 806
9f8fe504 807 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 808 kvm_mmu_sync_roots(vcpu);
77c3913b 809 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 810 return 0;
d835dfec
AK		 811 }
812
a03490ed 813 if (is_long_mode(vcpu)) {
d9f89b88
JK		 814 if (cr3 & CR3_L_MODE_RESERVED_BITS)
815 return 1;
816 } else if (is_pae(vcpu) && is_paging(vcpu) &&
817 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 818 return 1;
a03490ed 819
0f12244f 820 vcpu->arch.cr3 = cr3;
aff48baa 821 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 822 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 823 return 0;
824}
2d3ad1f4 825EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 826
eea1cff9 827int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 828{
0f12244f
GN		 829 if (cr8 & CR8_RESERVED_BITS)
830 return 1;
35754c98 831 if (lapic_in_kernel(vcpu))
a03490ed
CO		 832 kvm_lapic_set_tpr(vcpu, cr8);
833 else
ad312c7c 834 vcpu->arch.cr8 = cr8;
0f12244f
GN		 835 return 0;
836}
2d3ad1f4 837EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 838
2d3ad1f4 839unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 840{
35754c98 841 if (lapic_in_kernel(vcpu))
a03490ed
CO		 842 return kvm_lapic_get_cr8(vcpu);
843 else
ad312c7c 844 return vcpu->arch.cr8;
a03490ed 845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 847
ae561ede
NA		 848static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
849{
850 int i;
851
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
853 for (i = 0; i < KVM_NR_DB_REGS; i++)
854 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
855 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
856 }
857}
858
73aaf249
JK		 859static void kvm_update_dr6(struct kvm_vcpu *vcpu)
860{
861 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
862 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
863}
864
c8639010
JK		 865static void kvm_update_dr7(struct kvm_vcpu *vcpu)
866{
867 unsigned long dr7;
868
869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
870 dr7 = vcpu->arch.guest_debug_dr7;
871 else
872 dr7 = vcpu->arch.dr7;
873 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 874 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
875 if (dr7 & DR7_BP_EN_MASK)
876 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 877}
878
6f43ed01
NA		 879static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
880{
881 u64 fixed = DR6_FIXED_1;
882
883 if (!guest_cpuid_has_rtm(vcpu))
884 fixed |= DR6_RTM;
885 return fixed;
886}
887
338dbc97 888static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 889{
890 switch (dr) {
891 case 0 ... 3:
892 vcpu->arch.db[dr] = val;
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 vcpu->arch.eff_db[dr] = val;
895 break;
896 case 4:
020df079
GN		 897 /* fall through */
898 case 6:
338dbc97
GN		 899 if (val & 0xffffffff00000000ULL)
900 return -1; /* #GP */
6f43ed01 901 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 902 kvm_update_dr6(vcpu);
020df079
GN		 903 break;
904 case 5:
020df079
GN		 905 /* fall through */
906 default: /* 7 */
338dbc97
GN		 907 if (val & 0xffffffff00000000ULL)
908 return -1; /* #GP */
020df079 909 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 910 kvm_update_dr7(vcpu);
020df079
GN		 911 break;
912 }
913
914 return 0;
915}
338dbc97
GN		 916
917int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
918{
16f8a6f9 919 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 920 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 921 return 1;
922 }
923 return 0;
338dbc97 924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_set_dr);
926
16f8a6f9 927int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 928{
929 switch (dr) {
930 case 0 ... 3:
931 *val = vcpu->arch.db[dr];
932 break;
933 case 4:
020df079
GN		 934 /* fall through */
935 case 6:
73aaf249
JK		 936 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
937 *val = vcpu->arch.dr6;
938 else
939 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 940 break;
941 case 5:
020df079
GN		 942 /* fall through */
943 default: /* 7 */
944 *val = vcpu->arch.dr7;
945 break;
946 }
338dbc97
GN		 947 return 0;
948}
020df079
GN		 949EXPORT_SYMBOL_GPL(kvm_get_dr);
950
022cd0e8
AK		 951bool kvm_rdpmc(struct kvm_vcpu *vcpu)
952{
953 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
954 u64 data;
955 int err;
956
c6702c9d 957 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 958 if (err)
959 return err;
960 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
961 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
962 return err;
963}
964EXPORT_SYMBOL_GPL(kvm_rdpmc);
965
043405e1
CO		 966/*
967 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
968 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
969 *
970 * This list is modified at module load time to reflect the
e3267cbb 971 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 972 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
973 * may depend on host virtualization features rather than host cpu features.
043405e1 974 */
e3267cbb 975
043405e1
CO		 976static u32 msrs_to_save[] = {
977 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 978 MSR_STAR,
043405e1
CO		 979#ifdef CONFIG_X86_64
980 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
981#endif
b3897a49 982 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 983 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 984};
985
986static unsigned num_msrs_to_save;
987
62ef68bb
PB		 988static u32 emulated_msrs[] = {
989 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
990 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
991 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
992 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 993 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
994 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 995 HV_X64_MSR_RESET,
11c4b1ca 996 HV_X64_MSR_VP_INDEX,
9eec50b8 997 HV_X64_MSR_VP_RUNTIME,
5c919412 998 HV_X64_MSR_SCONTROL,
1f4b34f8 999 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1000 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1001 MSR_KVM_PV_EOI_EN,
1002
ba904635 1003 MSR_IA32_TSC_ADJUST,
a3e06bbe 1004 MSR_IA32_TSCDEADLINE,
043405e1 1005 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1006 MSR_IA32_MCG_STATUS,
1007 MSR_IA32_MCG_CTL,
c45dcc71 1008 MSR_IA32_MCG_EXT_CTL,
64d60670 1009 MSR_IA32_SMBASE,
db2336a8
KH		 1010 MSR_PLATFORM_INFO,
1011 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1012};
1013
62ef68bb
PB		 1014static unsigned num_emulated_msrs;
1015
384bb783 1016bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1017{
b69e8cae 1018 if (efer & efer_reserved_bits)
384bb783 1019 return false;
15c4a640 1020
1b2fd70c
AG		 1021 if (efer & EFER_FFXSR) {
1022 struct kvm_cpuid_entry2 *feat;
1023
1024 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1025 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1026 return false;
1b2fd70c
AG		 1027 }
1028
d8017474
AG		 1029 if (efer & EFER_SVME) {
1030 struct kvm_cpuid_entry2 *feat;
1031
1032 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1033 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1034 return false;
d8017474
AG		 1035 }
1036
384bb783
JK		 1037 return true;
1038}
1039EXPORT_SYMBOL_GPL(kvm_valid_efer);
1040
1041static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1042{
1043 u64 old_efer = vcpu->arch.efer;
1044
1045 if (!kvm_valid_efer(vcpu, efer))
1046 return 1;
1047
1048 if (is_paging(vcpu)
1049 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1050 return 1;
1051
15c4a640 1052 efer &= ~EFER_LMA;
f6801dff 1053 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1054
a3d204e2
SY		 1055 kvm_x86_ops->set_efer(vcpu, efer);
1056
aad82703
SY		 1057 /* Update reserved bits */
1058 if ((efer ^ old_efer) & EFER_NX)
1059 kvm_mmu_reset_context(vcpu);
1060
b69e8cae 1061 return 0;
15c4a640
CO		 1062}
1063
f2b4b7dd
JR		 1064void kvm_enable_efer_bits(u64 mask)
1065{
1066 efer_reserved_bits &= ~mask;
1067}
1068EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1069
15c4a640
CO		 1070/*
1071 * Writes msr value into into the appropriate "register".
1072 * Returns 0 on success, non-0 otherwise.
1073 * Assumes vcpu_load() was already called.
1074 */
8fe8ab46 1075int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1076{
854e8bb1
NA		 1077 switch (msr->index) {
1078 case MSR_FS_BASE:
1079 case MSR_GS_BASE:
1080 case MSR_KERNEL_GS_BASE:
1081 case MSR_CSTAR:
1082 case MSR_LSTAR:
1083 if (is_noncanonical_address(msr->data))
1084 return 1;
1085 break;
1086 case MSR_IA32_SYSENTER_EIP:
1087 case MSR_IA32_SYSENTER_ESP:
1088 /*
1089 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1090 * non-canonical address is written on Intel but not on
1091 * AMD (which ignores the top 32-bits, because it does
1092 * not implement 64-bit SYSENTER).
1093 *
1094 * 64-bit code should hence be able to write a non-canonical
1095 * value on AMD. Making the address canonical ensures that
1096 * vmentry does not fail on Intel after writing a non-canonical
1097 * value, and that something deterministic happens if the guest
1098 * invokes 64-bit SYSENTER.
1099 */
1100 msr->data = get_canonical(msr->data);
1101 }
8fe8ab46 1102 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1103}
854e8bb1 1104EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1105
313a3dc7
CO		 1106/*
1107 * Adapt set_msr() to msr_io()'s calling convention
1108 */
609e36d3
PB		 1109static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1110{
1111 struct msr_data msr;
1112 int r;
1113
1114 msr.index = index;
1115 msr.host_initiated = true;
1116 r = kvm_get_msr(vcpu, &msr);
1117 if (r)
1118 return r;
1119
1120 *data = msr.data;
1121 return 0;
1122}
1123
313a3dc7
CO		 1124static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1125{
8fe8ab46
WA		 1126 struct msr_data msr;
1127
1128 msr.data = *data;
1129 msr.index = index;
1130 msr.host_initiated = true;
1131 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1132}
1133
16e8d74d
MT		 1134#ifdef CONFIG_X86_64
1135struct pvclock_gtod_data {
1136 seqcount_t seq;
1137
1138 struct { /* extract of a clocksource struct */
1139 int vclock_mode;
a5a1d1c2
TG		 1140 u64 cycle_last;
1141 u64 mask;
16e8d74d
MT		 1142 u32 mult;
1143 u32 shift;
1144 } clock;
1145
cbcf2dd3
TG		 1146 u64 boot_ns;
1147 u64 nsec_base;
55dd00a7 1148 u64 wall_time_sec;
16e8d74d
MT		 1149};
1150
1151static struct pvclock_gtod_data pvclock_gtod_data;
1152
1153static void update_pvclock_gtod(struct timekeeper *tk)
1154{
1155 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1156 u64 boot_ns;
1157
876e7881 1158 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1159
1160 write_seqcount_begin(&vdata->seq);
1161
1162 /* copy pvclock gtod data */
876e7881
PZ		 1163 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1164 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1165 vdata->clock.mask = tk->tkr_mono.mask;
1166 vdata->clock.mult = tk->tkr_mono.mult;
1167 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1168
cbcf2dd3 1169 vdata->boot_ns = boot_ns;
876e7881 1170 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1171
55dd00a7
MT		 1172 vdata->wall_time_sec = tk->xtime_sec;
1173
16e8d74d
MT		 1174 write_seqcount_end(&vdata->seq);
1175}
1176#endif
1177
bab5bb39
NK		 1178void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1179{
1180 /*
1181 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1182 * vcpu_enter_guest. This function is only called from
1183 * the physical CPU that is running vcpu.
1184 */
1185 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1186}
16e8d74d 1187
18068523
GOC		 1188static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1189{
9ed3c444
AK		 1190 int version;
1191 int r;
50d0a0f9 1192 struct pvclock_wall_clock wc;
87aeb54f 1193 struct timespec64 boot;
18068523
GOC		 1194
1195 if (!wall_clock)
1196 return;
1197
9ed3c444
AK		 1198 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1199 if (r)
1200 return;
1201
1202 if (version & 1)
1203 ++version; /* first time write, random junk */
1204
1205 ++version;
18068523 1206
1dab1345
NK		 1207 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1208 return;
18068523 1209
50d0a0f9
GH		 1210 /*
1211 * The guest calculates current wall clock time by adding
34c238a1 1212 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1213 * wall clock specified here. guest system time equals host
1214 * system time for us, thus we must fill in host boot time here.
1215 */
87aeb54f 1216 getboottime64(&boot);
50d0a0f9 1217
4b648665 1218 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1219 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1220 boot = timespec64_sub(boot, ts);
4b648665 1221 }
87aeb54f 1222 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1223 wc.nsec = boot.tv_nsec;
1224 wc.version = version;
18068523
GOC		 1225
1226 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1227
1228 version++;
1229 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1230}
1231
50d0a0f9
GH		 1232static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1233{
b51012de
PB		 1234 do_shl32_div32(dividend, divisor);
1235 return dividend;
50d0a0f9
GH		 1236}
1237
3ae13faa 1238static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1239 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1240{
5f4e3f88 1241 uint64_t scaled64;
50d0a0f9
GH		 1242 int32_t shift = 0;
1243 uint64_t tps64;
1244 uint32_t tps32;
1245
3ae13faa
PB		 1246 tps64 = base_hz;
1247 scaled64 = scaled_hz;
50933623 1248 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1249 tps64 >>= 1;
1250 shift--;
1251 }
1252
1253 tps32 = (uint32_t)tps64;
50933623
JK		 1254 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1255 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1256 scaled64 >>= 1;
1257 else
1258 tps32 <<= 1;
50d0a0f9
GH		 1259 shift++;
1260 }
1261
5f4e3f88
ZA		 1262 *pshift = shift;
1263 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1264
3ae13faa
PB		 1265 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1266 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1267}
1268
d828199e 1269#ifdef CONFIG_X86_64
16e8d74d 1270static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1271#endif
16e8d74d 1272
c8076604 1273static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1274static unsigned long max_tsc_khz;
c8076604 1275
cc578287 1276static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1277{
cc578287
ZA		 1278 u64 v = (u64)khz * (1000000 + ppm);
1279 do_div(v, 1000000);
1280 return v;
1e993611
JR		 1281}
1282
381d585c
HZ		 1283static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1284{
1285 u64 ratio;
1286
1287 /* Guest TSC same frequency as host TSC? */
1288 if (!scale) {
1289 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1290 return 0;
1291 }
1292
1293 /* TSC scaling supported? */
1294 if (!kvm_has_tsc_control) {
1295 if (user_tsc_khz > tsc_khz) {
1296 vcpu->arch.tsc_catchup = 1;
1297 vcpu->arch.tsc_always_catchup = 1;
1298 return 0;
1299 } else {
1300 WARN(1, "user requested TSC rate below hardware speed\n");
1301 return -1;
1302 }
1303 }
1304
1305 /* TSC scaling required - calculate ratio */
1306 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1307 user_tsc_khz, tsc_khz);
1308
1309 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1310 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1311 user_tsc_khz);
1312 return -1;
1313 }
1314
1315 vcpu->arch.tsc_scaling_ratio = ratio;
1316 return 0;
1317}
1318
4941b8cb 1319static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1320{
cc578287
ZA		 1321 u32 thresh_lo, thresh_hi;
1322 int use_scaling = 0;
217fc9cf 1323
03ba32ca 1324 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1325 if (user_tsc_khz == 0) {
ad721883
HZ		 1326 /* set tsc_scaling_ratio to a safe value */
1327 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1328 return -1;
ad721883 1329 }
03ba32ca 1330
c285545f 1331 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1332 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1333 &vcpu->arch.virtual_tsc_shift,
1334 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1335 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1336
1337 /*
1338 * Compute the variation in TSC rate which is acceptable
1339 * within the range of tolerance and decide if the
1340 * rate being applied is within that bounds of the hardware
1341 * rate. If so, no scaling or compensation need be done.
1342 */
1343 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1344 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1345 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1346 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1347 use_scaling = 1;
1348 }
4941b8cb 1349 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1350}
1351
1352static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1353{
e26101b1 1354 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1355 vcpu->arch.virtual_tsc_mult,
1356 vcpu->arch.virtual_tsc_shift);
e26101b1 1357 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1358 return tsc;
1359}
1360
69b0049a 1361static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1362{
1363#ifdef CONFIG_X86_64
1364 bool vcpus_matched;
b48aa97e
MT		 1365 struct kvm_arch *ka = &vcpu->kvm->arch;
1366 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1367
1368 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1369 atomic_read(&vcpu->kvm->online_vcpus));
1370
7f187922
MT		 1371 /*
1372 * Once the masterclock is enabled, always perform request in
1373 * order to update it.
1374 *
1375 * In order to enable masterclock, the host clocksource must be TSC
1376 * and the vcpus need to have matched TSCs. When that happens,
1377 * perform request to enable masterclock.
1378 */
1379 if (ka->use_master_clock ||
1380 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1381 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1382
1383 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1384 atomic_read(&vcpu->kvm->online_vcpus),
1385 ka->use_master_clock, gtod->clock.vclock_mode);
1386#endif
1387}
1388
ba904635
WA		 1389static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1390{
3e3f5026 1391 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1392 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1393}
1394
35181e86
HZ		 1395/*
1396 * Multiply tsc by a fixed point number represented by ratio.
1397 *
1398 * The most significant 64-N bits (mult) of ratio represent the
1399 * integral part of the fixed point number; the remaining N bits
1400 * (frac) represent the fractional part, ie. ratio represents a fixed
1401 * point number (mult + frac * 2^(-N)).
1402 *
1403 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1404 */
1405static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1406{
1407 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1408}
1409
1410u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1411{
1412 u64 _tsc = tsc;
1413 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1414
1415 if (ratio != kvm_default_tsc_scaling_ratio)
1416 _tsc = __scale_tsc(ratio, tsc);
1417
1418 return _tsc;
1419}
1420EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1421
07c1419a
HZ		 1422static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1423{
1424 u64 tsc;
1425
1426 tsc = kvm_scale_tsc(vcpu, rdtsc());
1427
1428 return target_tsc - tsc;
1429}
1430
4ba76538
HZ		 1431u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1432{
ea26e4ec 1433 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1434}
1435EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1436
a545ab6a
LC		 1437static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1438{
1439 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1440 vcpu->arch.tsc_offset = offset;
1441}
1442
8fe8ab46 1443void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1444{
1445 struct kvm *kvm = vcpu->kvm;
f38e098f 1446 u64 offset, ns, elapsed;
99e3e30a 1447 unsigned long flags;
b48aa97e 1448 bool matched;
0d3da0d2 1449 bool already_matched;
8fe8ab46 1450 u64 data = msr->data;
c5e8ec8e 1451 bool synchronizing = false;
99e3e30a 1452
038f8c11 1453 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1454 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1455 ns = ktime_get_boot_ns();
f38e098f 1456 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1457
03ba32ca 1458 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1459 if (data == 0 && msr->host_initiated) {
1460 /*
1461 * detection of vcpu initialization -- need to sync
1462 * with other vCPUs. This particularly helps to keep
1463 * kvm_clock stable after CPU hotplug
1464 */
1465 synchronizing = true;
1466 } else {
1467 u64 tsc_exp = kvm->arch.last_tsc_write +
1468 nsec_to_cycles(vcpu, elapsed);
1469 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1470 /*
1471 * Special case: TSC write with a small delta (1 second)
1472 * of virtual cycle time against real time is
1473 * interpreted as an attempt to synchronize the CPU.
1474 */
1475 synchronizing = data < tsc_exp + tsc_hz &&
1476 data + tsc_hz > tsc_exp;
1477 }
c5e8ec8e 1478 }
f38e098f
ZA		 1479
1480 /*
5d3cb0f6
ZA		 1481 * For a reliable TSC, we can match TSC offsets, and for an unstable
1482 * TSC, we add elapsed time in this computation. We could let the
1483 * compensation code attempt to catch up if we fall behind, but
1484 * it's better to try to match offsets from the beginning.
1485 */
c5e8ec8e 1486 if (synchronizing &&
5d3cb0f6 1487 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1488 if (!check_tsc_unstable()) {
e26101b1 1489 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1490 pr_debug("kvm: matched tsc offset for %llu\n", data);
1491 } else {
857e4099 1492 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1493 data += delta;
07c1419a 1494 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1495 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1496 }
b48aa97e 1497 matched = true;
0d3da0d2 1498 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1499 } else {
1500 /*
1501 * We split periods of matched TSC writes into generations.
1502 * For each generation, we track the original measured
1503 * nanosecond time, offset, and write, so if TSCs are in
1504 * sync, we can match exact offset, and if not, we can match
4a969980 1505 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1506 *
1507 * These values are tracked in kvm->arch.cur_xxx variables.
1508 */
1509 kvm->arch.cur_tsc_generation++;
1510 kvm->arch.cur_tsc_nsec = ns;
1511 kvm->arch.cur_tsc_write = data;
1512 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1513 matched = false;
0d3da0d2 1514 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1515 kvm->arch.cur_tsc_generation, data);
f38e098f 1516 }
e26101b1
ZA		 1517
1518 /*
1519 * We also track th most recent recorded KHZ, write and time to
1520 * allow the matching interval to be extended at each write.
1521 */
f38e098f
ZA		 1522 kvm->arch.last_tsc_nsec = ns;
1523 kvm->arch.last_tsc_write = data;
5d3cb0f6 1524 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1525
b183aa58 1526 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1527
1528 /* Keep track of which generation this VCPU has synchronized to */
1529 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1530 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1531 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1532
ba904635
WA		 1533 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1534 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1535 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1536 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1537
1538 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1539 if (!matched) {
b48aa97e 1540 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1541 } else if (!already_matched) {
1542 kvm->arch.nr_vcpus_matched_tsc++;
1543 }
b48aa97e
MT		 1544
1545 kvm_track_tsc_matching(vcpu);
1546 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1547}
e26101b1 1548
99e3e30a
ZA		 1549EXPORT_SYMBOL_GPL(kvm_write_tsc);
1550
58ea6767
HZ		 1551static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1552 s64 adjustment)
1553{
ea26e4ec 1554 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1555}
1556
1557static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1558{
1559 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1560 WARN_ON(adjustment < 0);
1561 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1562 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1563}
1564
d828199e
MT		 1565#ifdef CONFIG_X86_64
1566
a5a1d1c2 1567static u64 read_tsc(void)
d828199e 1568{
a5a1d1c2 1569 u64 ret = (u64)rdtsc_ordered();
03b9730b 1570 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1571
1572 if (likely(ret >= last))
1573 return ret;
1574
1575 /*
1576 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1577 * predictable (it's just a function of time and the likely is
d828199e
MT		 1578 * very likely) and there's a data dependence, so force GCC
1579 * to generate a branch instead. I don't barrier() because
1580 * we don't actually need a barrier, and if this function
1581 * ever gets inlined it will generate worse code.
1582 */
1583 asm volatile ("");
1584 return last;
1585}
1586
a5a1d1c2 1587static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1588{
1589 long v;
1590 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1591
1592 *cycle_now = read_tsc();
1593
1594 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1595 return v * gtod->clock.mult;
1596}
1597
a5a1d1c2 1598static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1599{
cbcf2dd3 1600 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1601 unsigned long seq;
d828199e 1602 int mode;
cbcf2dd3 1603 u64 ns;
d828199e 1604
d828199e
MT		 1605 do {
1606 seq = read_seqcount_begin(&gtod->seq);
1607 mode = gtod->clock.vclock_mode;
cbcf2dd3 1608 ns = gtod->nsec_base;
d828199e
MT		 1609 ns += vgettsc(cycle_now);
1610 ns >>= gtod->clock.shift;
cbcf2dd3 1611 ns += gtod->boot_ns;
d828199e 1612 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1613 *t = ns;
d828199e
MT		 1614
1615 return mode;
1616}
1617
55dd00a7
MT		 1618static int do_realtime(struct timespec *ts, u64 *cycle_now)
1619{
1620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1621 unsigned long seq;
1622 int mode;
1623 u64 ns;
1624
1625 do {
1626 seq = read_seqcount_begin(&gtod->seq);
1627 mode = gtod->clock.vclock_mode;
1628 ts->tv_sec = gtod->wall_time_sec;
1629 ns = gtod->nsec_base;
1630 ns += vgettsc(cycle_now);
1631 ns >>= gtod->clock.shift;
1632 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1633
1634 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1635 ts->tv_nsec = ns;
1636
1637 return mode;
1638}
1639
d828199e 1640/* returns true if host is using tsc clocksource */
a5a1d1c2 1641static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1642{
d828199e
MT		 1643 /* checked again under seqlock below */
1644 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1645 return false;
1646
cbcf2dd3 1647 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1648}
55dd00a7
MT		 1649
1650/* returns true if host is using tsc clocksource */
1651static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1652 u64 *cycle_now)
1653{
1654 /* checked again under seqlock below */
1655 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1656 return false;
1657
1658 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1659}
d828199e
MT		 1660#endif
1661
1662/*
1663 *
b48aa97e
MT		 1664 * Assuming a stable TSC across physical CPUS, and a stable TSC
1665 * across virtual CPUs, the following condition is possible.
1666 * Each numbered line represents an event visible to both
d828199e
MT		 1667 * CPUs at the next numbered event.
1668 *
1669 * "timespecX" represents host monotonic time. "tscX" represents
1670 * RDTSC value.
1671 *
1672 * VCPU0 on CPU0 | VCPU1 on CPU1
1673 *
1674 * 1. read timespec0,tsc0
1675 * 2. | timespec1 = timespec0 + N
1676 * | tsc1 = tsc0 + M
1677 * 3. transition to guest | transition to guest
1678 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1679 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1680 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1681 *
1682 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1683 *
1684 * - ret0 < ret1
1685 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1686 * ...
1687 * - 0 < N - M => M < N
1688 *
1689 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1690 * always the case (the difference between two distinct xtime instances
1691 * might be smaller then the difference between corresponding TSC reads,
1692 * when updating guest vcpus pvclock areas).
1693 *
1694 * To avoid that problem, do not allow visibility of distinct
1695 * system_timestamp/tsc_timestamp values simultaneously: use a master
1696 * copy of host monotonic time values. Update that master copy
1697 * in lockstep.
1698 *
b48aa97e 1699 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1700 *
1701 */
1702
1703static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1704{
1705#ifdef CONFIG_X86_64
1706 struct kvm_arch *ka = &kvm->arch;
1707 int vclock_mode;
b48aa97e
MT		 1708 bool host_tsc_clocksource, vcpus_matched;
1709
1710 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1711 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1712
1713 /*
1714 * If the host uses TSC clock, then passthrough TSC as stable
1715 * to the guest.
1716 */
b48aa97e 1717 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1718 &ka->master_kernel_ns,
1719 &ka->master_cycle_now);
1720
16a96021 1721 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1722 && !backwards_tsc_observed
1723 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1724
d828199e
MT		 1725 if (ka->use_master_clock)
1726 atomic_set(&kvm_guest_has_master_clock, 1);
1727
1728 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1729 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1730 vcpus_matched);
d828199e
MT		 1731#endif
1732}
1733
2860c4b1
PB		 1734void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1735{
1736 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1737}
1738
2e762ff7
MT		 1739static void kvm_gen_update_masterclock(struct kvm *kvm)
1740{
1741#ifdef CONFIG_X86_64
1742 int i;
1743 struct kvm_vcpu *vcpu;
1744 struct kvm_arch *ka = &kvm->arch;
1745
1746 spin_lock(&ka->pvclock_gtod_sync_lock);
1747 kvm_make_mclock_inprogress_request(kvm);
1748 /* no guest entries from this point */
1749 pvclock_update_vm_gtod_copy(kvm);
1750
1751 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1752 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1753
1754 /* guest entries allowed */
1755 kvm_for_each_vcpu(i, vcpu, kvm)
1756 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1757
1758 spin_unlock(&ka->pvclock_gtod_sync_lock);
1759#endif
1760}
1761
e891a32e 1762u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1763{
108b249c 1764 struct kvm_arch *ka = &kvm->arch;
8b953440 1765 struct pvclock_vcpu_time_info hv_clock;
108b249c 1766
8b953440
PB		 1767 spin_lock(&ka->pvclock_gtod_sync_lock);
1768 if (!ka->use_master_clock) {
1769 spin_unlock(&ka->pvclock_gtod_sync_lock);
1770 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1771 }
1772
8b953440
PB		 1773 hv_clock.tsc_timestamp = ka->master_cycle_now;
1774 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1775 spin_unlock(&ka->pvclock_gtod_sync_lock);
1776
1777 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1778 &hv_clock.tsc_shift,
1779 &hv_clock.tsc_to_system_mul);
1780 return __pvclock_read_cycles(&hv_clock, rdtsc());
108b249c
PB		 1781}
1782
0d6dd2ff
PB		 1783static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1784{
1785 struct kvm_vcpu_arch *vcpu = &v->arch;
1786 struct pvclock_vcpu_time_info guest_hv_clock;
1787
bbd64115 1788 if (unlikely(kvm_vcpu_read_guest_cached(v, &vcpu->pv_time,
0d6dd2ff
PB		 1789 &guest_hv_clock, sizeof(guest_hv_clock))))
1790 return;
1791
1792 /* This VCPU is paused, but it's legal for a guest to read another
1793 * VCPU's kvmclock, so we really have to follow the specification where
1794 * it says that version is odd if data is being modified, and even after
1795 * it is consistent.
1796 *
1797 * Version field updates must be kept separate. This is because
1798 * kvm_write_guest_cached might use a "rep movs" instruction, and
1799 * writes within a string instruction are weakly ordered. So there
1800 * are three writes overall.
1801 *
1802 * As a small optimization, only write the version field in the first
1803 * and third write. The vcpu->pv_time cache is still valid, because the
1804 * version field is the first in the struct.
1805 */
1806 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1807
1808 vcpu->hv_clock.version = guest_hv_clock.version + 1;
bbd64115
CL		 1809 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1810 &vcpu->hv_clock,
1811 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1812
1813 smp_wmb();
1814
1815 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1816 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1817
1818 if (vcpu->pvclock_set_guest_stopped_request) {
1819 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1820 vcpu->pvclock_set_guest_stopped_request = false;
1821 }
1822
1823 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1824
bbd64115
CL		 1825 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1826 &vcpu->hv_clock,
1827 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1828
1829 smp_wmb();
1830
1831 vcpu->hv_clock.version++;
bbd64115
CL		 1832 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1833 &vcpu->hv_clock,
1834 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1835}
1836
34c238a1 1837static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1838{
78db6a50 1839 unsigned long flags, tgt_tsc_khz;
18068523 1840 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1841 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1842 s64 kernel_ns;
d828199e 1843 u64 tsc_timestamp, host_tsc;
51d59c6b 1844 u8 pvclock_flags;
d828199e
MT		 1845 bool use_master_clock;
1846
1847 kernel_ns = 0;
1848 host_tsc = 0;
18068523 1849
d828199e
MT		 1850 /*
1851 * If the host uses TSC clock, then passthrough TSC as stable
1852 * to the guest.
1853 */
1854 spin_lock(&ka->pvclock_gtod_sync_lock);
1855 use_master_clock = ka->use_master_clock;
1856 if (use_master_clock) {
1857 host_tsc = ka->master_cycle_now;
1858 kernel_ns = ka->master_kernel_ns;
1859 }
1860 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1861
1862 /* Keep irq disabled to prevent changes to the clock */
1863 local_irq_save(flags);
78db6a50
PB		 1864 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1865 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1866 local_irq_restore(flags);
1867 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1868 return 1;
1869 }
d828199e 1870 if (!use_master_clock) {
4ea1636b 1871 host_tsc = rdtsc();
108b249c 1872 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1873 }
1874
4ba76538 1875 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1876
c285545f
ZA		 1877 /*
1878 * We may have to catch up the TSC to match elapsed wall clock
1879 * time for two reasons, even if kvmclock is used.
1880 * 1) CPU could have been running below the maximum TSC rate
1881 * 2) Broken TSC compensation resets the base at each VCPU
1882 * entry to avoid unknown leaps of TSC even when running
1883 * again on the same CPU. This may cause apparent elapsed
1884 * time to disappear, and the guest to stand still or run
1885 * very slowly.
1886 */
1887 if (vcpu->tsc_catchup) {
1888 u64 tsc = compute_guest_tsc(v, kernel_ns);
1889 if (tsc > tsc_timestamp) {
f1e2b260 1890 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1891 tsc_timestamp = tsc;
1892 }
50d0a0f9
GH		 1893 }
1894
18068523
GOC		 1895 local_irq_restore(flags);
1896
0d6dd2ff 1897 /* With all the info we got, fill in the values */
18068523 1898
78db6a50
PB		 1899 if (kvm_has_tsc_control)
1900 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1901
1902 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1903 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1904 &vcpu->hv_clock.tsc_shift,
1905 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1906 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1907 }
1908
1d5f066e 1909 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1910 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1911 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1912
d828199e 1913 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1914 pvclock_flags = 0;
d828199e
MT		 1915 if (use_master_clock)
1916 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1917
78c0337a
MT		 1918 vcpu->hv_clock.flags = pvclock_flags;
1919
095cf55d
PB		 1920 if (vcpu->pv_time_enabled)
1921 kvm_setup_pvclock_page(v);
1922 if (v == kvm_get_vcpu(v->kvm, 0))
1923 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1924 return 0;
c8076604
GH		 1925}
1926
0061d53d
MT		 1927/*
1928 * kvmclock updates which are isolated to a given vcpu, such as
1929 * vcpu->cpu migration, should not allow system_timestamp from
1930 * the rest of the vcpus to remain static. Otherwise ntp frequency
1931 * correction applies to one vcpu's system_timestamp but not
1932 * the others.
1933 *
1934 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1935 * We need to rate-limit these requests though, as they can
1936 * considerably slow guests that have a large number of vcpus.
1937 * The time for a remote vcpu to update its kvmclock is bound
1938 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1939 */
1940
7e44e449
AJ		 1941#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1942
1943static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1944{
1945 int i;
7e44e449
AJ		 1946 struct delayed_work *dwork = to_delayed_work(work);
1947 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1948 kvmclock_update_work);
1949 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1950 struct kvm_vcpu *vcpu;
1951
1952 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1953 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1954 kvm_vcpu_kick(vcpu);
1955 }
1956}
1957
7e44e449
AJ		 1958static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1959{
1960 struct kvm *kvm = v->kvm;
1961
105b21bb 1962 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1963 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1964 KVMCLOCK_UPDATE_DELAY);
1965}
1966
332967a3
AJ		 1967#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1968
1969static void kvmclock_sync_fn(struct work_struct *work)
1970{
1971 struct delayed_work *dwork = to_delayed_work(work);
1972 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1973 kvmclock_sync_work);
1974 struct kvm *kvm = container_of(ka, struct kvm, arch);
1975
630994b3
MT		 1976 if (!kvmclock_periodic_sync)
1977 return;
1978
332967a3
AJ		 1979 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1980 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1981 KVMCLOCK_SYNC_PERIOD);
1982}
1983
890ca9ae 1984static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1985{
890ca9ae
HY		 1986 u64 mcg_cap = vcpu->arch.mcg_cap;
1987 unsigned bank_num = mcg_cap & 0xff;
1988
15c4a640 1989 switch (msr) {
15c4a640 1990 case MSR_IA32_MCG_STATUS:
890ca9ae 1991 vcpu->arch.mcg_status = data;
15c4a640 1992 break;
c7ac679c 1993 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1994 if (!(mcg_cap & MCG_CTL_P))
1995 return 1;
1996 if (data != 0 && data != ~(u64)0)
1997 return -1;
1998 vcpu->arch.mcg_ctl = data;
1999 break;
2000 default:
2001 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2002 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2003 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2004 /* only 0 or all 1s can be written to IA32_MCi_CTL
2005 * some Linux kernels though clear bit 10 in bank 4 to
2006 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2007 * this to avoid an uncatched #GP in the guest
2008 */
890ca9ae 2009 if ((offset & 0x3) == 0 &&
114be429 2010 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2011 return -1;
2012 vcpu->arch.mce_banks[offset] = data;
2013 break;
2014 }
2015 return 1;
2016 }
2017 return 0;
2018}
2019
ffde22ac
ES		 2020static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2021{
2022 struct kvm *kvm = vcpu->kvm;
2023 int lm = is_long_mode(vcpu);
2024 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2025 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2026 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2027 : kvm->arch.xen_hvm_config.blob_size_32;
2028 u32 page_num = data & ~PAGE_MASK;
2029 u64 page_addr = data & PAGE_MASK;
2030 u8 *page;
2031 int r;
2032
2033 r = -E2BIG;
2034 if (page_num >= blob_size)
2035 goto out;
2036 r = -ENOMEM;
ff5c2c03
SL		 2037 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2038 if (IS_ERR(page)) {
2039 r = PTR_ERR(page);
ffde22ac 2040 goto out;
ff5c2c03 2041 }
54bf36aa 2042 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2043 goto out_free;
2044 r = 0;
2045out_free:
2046 kfree(page);
2047out:
2048 return r;
2049}
2050
344d9588
GN		 2051static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2052{
2053 gpa_t gpa = data & ~0x3f;
2054
4a969980 2055 /* Bits 2:5 are reserved, Should be zero */
6adba527 2056 if (data & 0x3c)
344d9588
GN		 2057 return 1;
2058
2059 vcpu->arch.apf.msr_val = data;
2060
2061 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2062 kvm_clear_async_pf_completion_queue(vcpu);
2063 kvm_async_pf_hash_reset(vcpu);
2064 return 0;
2065 }
2066
bbd64115 2067 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.apf.data, gpa,
8f964525 2068 sizeof(u32)))
344d9588
GN		 2069 return 1;
2070
6adba527 2071 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2072 kvm_async_pf_wakeup_all(vcpu);
2073 return 0;
2074}
2075
12f9a48f
GC		 2076static void kvmclock_reset(struct kvm_vcpu *vcpu)
2077{
0b79459b 2078 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2079}
2080
c9aaa895
GC		 2081static void record_steal_time(struct kvm_vcpu *vcpu)
2082{
2083 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2084 return;
2085
bbd64115 2086 if (unlikely(kvm_vcpu_read_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2087 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2088 return;
2089
0b9f6c46
PX		 2090 vcpu->arch.st.steal.preempted = 0;
2091
35f3fae1
WL		 2092 if (vcpu->arch.st.steal.version & 1)
2093 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2094
2095 vcpu->arch.st.steal.version += 1;
2096
bbd64115 2097 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2098 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2099
2100 smp_wmb();
2101
c54cdf14
LC		 2102 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2103 vcpu->arch.st.last_steal;
2104 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2105
bbd64115 2106 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2107 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2108
2109 smp_wmb();
2110
2111 vcpu->arch.st.steal.version += 1;
c9aaa895 2112
bbd64115 2113 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2114 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2115}
2116
8fe8ab46 2117int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2118{
5753785f 2119 bool pr = false;
8fe8ab46
WA		 2120 u32 msr = msr_info->index;
2121 u64 data = msr_info->data;
5753785f 2122
15c4a640 2123 switch (msr) {
2e32b719
BP		 2124 case MSR_AMD64_NB_CFG:
2125 case MSR_IA32_UCODE_REV:
2126 case MSR_IA32_UCODE_WRITE:
2127 case MSR_VM_HSAVE_PA:
2128 case MSR_AMD64_PATCH_LOADER:
2129 case MSR_AMD64_BU_CFG2:
405a353a 2130 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2131 break;
2132
15c4a640 2133 case MSR_EFER:
b69e8cae 2134 return set_efer(vcpu, data);
8f1589d9
AP		 2135 case MSR_K7_HWCR:
2136 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2137 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2138 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2139 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2140 if (data != 0) {
a737f256
CD		 2141 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2142 data);
8f1589d9
AP		 2143 return 1;
2144 }
15c4a640 2145 break;
f7c6d140
AP		 2146 case MSR_FAM10H_MMIO_CONF_BASE:
2147 if (data != 0) {
a737f256
CD		 2148 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2149 "0x%llx\n", data);
f7c6d140
AP		 2150 return 1;
2151 }
15c4a640 2152 break;
b5e2fec0
AG		 2153 case MSR_IA32_DEBUGCTLMSR:
2154 if (!data) {
2155 /* We support the non-activated case already */
2156 break;
2157 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2158 /* Values other than LBR and BTF are vendor-specific,
2159 thus reserved and should throw a #GP */
2160 return 1;
2161 }
a737f256
CD		 2162 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2163 __func__, data);
b5e2fec0 2164 break;
9ba075a6 2165 case 0x200 ... 0x2ff:
ff53604b 2166 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2167 case MSR_IA32_APICBASE:
58cb628d 2168 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2169 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2170 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2171 case MSR_IA32_TSCDEADLINE:
2172 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2173 break;
ba904635
WA		 2174 case MSR_IA32_TSC_ADJUST:
2175 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2176 if (!msr_info->host_initiated) {
d913b904 2177 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2178 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2179 }
2180 vcpu->arch.ia32_tsc_adjust_msr = data;
2181 }
2182 break;
15c4a640 2183 case MSR_IA32_MISC_ENABLE:
ad312c7c 2184 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2185 break;
64d60670
PB		 2186 case MSR_IA32_SMBASE:
2187 if (!msr_info->host_initiated)
2188 return 1;
2189 vcpu->arch.smbase = data;
2190 break;
11c6bffa 2191 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2192 case MSR_KVM_WALL_CLOCK:
2193 vcpu->kvm->arch.wall_clock = data;
2194 kvm_write_wall_clock(vcpu->kvm, data);
2195 break;
11c6bffa 2196 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2197 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2198 struct kvm_arch *ka = &vcpu->kvm->arch;
2199
12f9a48f 2200 kvmclock_reset(vcpu);
18068523 2201
54750f2c
MT		 2202 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2203 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2204
2205 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2206 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2207 &vcpu->requests);
2208
2209 ka->boot_vcpu_runs_old_kvmclock = tmp;
2210 }
2211
18068523 2212 vcpu->arch.time = data;
0061d53d 2213 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2214
2215 /* we verify if the enable bit is set... */
2216 if (!(data & 1))
2217 break;
2218
bbd64115 2219 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu,
8f964525
AH		 2220 &vcpu->arch.pv_time, data & ~1ULL,
2221 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2222 vcpu->arch.pv_time_enabled = false;
2223 else
2224 vcpu->arch.pv_time_enabled = true;
32cad84f 2225
18068523
GOC		 2226 break;
2227 }
344d9588
GN		 2228 case MSR_KVM_ASYNC_PF_EN:
2229 if (kvm_pv_enable_async_pf(vcpu, data))
2230 return 1;
2231 break;
c9aaa895
GC		 2232 case MSR_KVM_STEAL_TIME:
2233
2234 if (unlikely(!sched_info_on()))
2235 return 1;
2236
2237 if (data & KVM_STEAL_RESERVED_MASK)
2238 return 1;
2239
bbd64115 2240 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.st.stime,
8f964525
AH		 2241 data & KVM_STEAL_VALID_BITS,
2242 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2243 return 1;
2244
2245 vcpu->arch.st.msr_val = data;
2246
2247 if (!(data & KVM_MSR_ENABLED))
2248 break;
2249
c9aaa895
GC		 2250 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2251
2252 break;
ae7a2a3f
MT		 2253 case MSR_KVM_PV_EOI_EN:
2254 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2255 return 1;
2256 break;
c9aaa895 2257
890ca9ae
HY		 2258 case MSR_IA32_MCG_CTL:
2259 case MSR_IA32_MCG_STATUS:
81760dcc 2260 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2261 return set_msr_mce(vcpu, msr, data);
71db6023 2262
6912ac32
WH		 2263 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2264 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2265 pr = true; /* fall through */
2266 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2267 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2268 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2269 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2270
2271 if (pr || data != 0)
a737f256
CD		 2272 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2273 "0x%x data 0x%llx\n", msr, data);
5753785f 2274 break;
84e0cefa
JS		 2275 case MSR_K7_CLK_CTL:
2276 /*
2277 * Ignore all writes to this no longer documented MSR.
2278 * Writes are only relevant for old K7 processors,
2279 * all pre-dating SVM, but a recommended workaround from
4a969980 2280 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2281 * affected processor models on the command line, hence
2282 * the need to ignore the workaround.
2283 */
2284 break;
55cd8e5a 2285 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2286 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2287 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2288 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2289 return kvm_hv_set_msr_common(vcpu, msr, data,
2290 msr_info->host_initiated);
91c9c3ed 2291 case MSR_IA32_BBL_CR_CTL3:
2292 /* Drop writes to this legacy MSR -- see rdmsr
2293 * counterpart for further detail.
2294 */
796f4687 2295 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2296 break;
2b036c6b
BO		 2297 case MSR_AMD64_OSVW_ID_LENGTH:
2298 if (!guest_cpuid_has_osvw(vcpu))
2299 return 1;
2300 vcpu->arch.osvw.length = data;
2301 break;
2302 case MSR_AMD64_OSVW_STATUS:
2303 if (!guest_cpuid_has_osvw(vcpu))
2304 return 1;
2305 vcpu->arch.osvw.status = data;
2306 break;
db2336a8
KH		 2307 case MSR_PLATFORM_INFO:
2308 if (!msr_info->host_initiated ||
2309 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2310 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2311 cpuid_fault_enabled(vcpu)))
2312 return 1;
2313 vcpu->arch.msr_platform_info = data;
2314 break;
2315 case MSR_MISC_FEATURES_ENABLES:
2316 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2317 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2318 !supports_cpuid_fault(vcpu)))
2319 return 1;
2320 vcpu->arch.msr_misc_features_enables = data;
2321 break;
15c4a640 2322 default:
ffde22ac
ES		 2323 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2324 return xen_hvm_config(vcpu, data);
c6702c9d 2325 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2326 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2327 if (!ignore_msrs) {
ae0f5499 2328 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2329 msr, data);
ed85c068
AP		 2330 return 1;
2331 } else {
796f4687 2332 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2333 msr, data);
ed85c068
AP		 2334 break;
2335 }
15c4a640
CO		 2336 }
2337 return 0;
2338}
2339EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2340
2341
2342/*
2343 * Reads an msr value (of 'msr_index') into 'pdata'.
2344 * Returns 0 on success, non-0 otherwise.
2345 * Assumes vcpu_load() was already called.
2346 */
609e36d3 2347int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2348{
609e36d3 2349 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2350}
ff651cb6 2351EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2352
890ca9ae 2353static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2354{
2355 u64 data;
890ca9ae
HY		 2356 u64 mcg_cap = vcpu->arch.mcg_cap;
2357 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2358
2359 switch (msr) {
15c4a640
CO		 2360 case MSR_IA32_P5_MC_ADDR:
2361 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2362 data = 0;
2363 break;
15c4a640 2364 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2365 data = vcpu->arch.mcg_cap;
2366 break;
c7ac679c 2367 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2368 if (!(mcg_cap & MCG_CTL_P))
2369 return 1;
2370 data = vcpu->arch.mcg_ctl;
2371 break;
2372 case MSR_IA32_MCG_STATUS:
2373 data = vcpu->arch.mcg_status;
2374 break;
2375 default:
2376 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2377 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2378 u32 offset = msr - MSR_IA32_MC0_CTL;
2379 data = vcpu->arch.mce_banks[offset];
2380 break;
2381 }
2382 return 1;
2383 }
2384 *pdata = data;
2385 return 0;
2386}
2387
609e36d3 2388int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2389{
609e36d3 2390 switch (msr_info->index) {
890ca9ae 2391 case MSR_IA32_PLATFORM_ID:
15c4a640 2392 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2393 case MSR_IA32_DEBUGCTLMSR:
2394 case MSR_IA32_LASTBRANCHFROMIP:
2395 case MSR_IA32_LASTBRANCHTOIP:
2396 case MSR_IA32_LASTINTFROMIP:
2397 case MSR_IA32_LASTINTTOIP:
60af2ecd 2398 case MSR_K8_SYSCFG:
3afb1121
PB		 2399 case MSR_K8_TSEG_ADDR:
2400 case MSR_K8_TSEG_MASK:
60af2ecd 2401 case MSR_K7_HWCR:
61a6bd67 2402 case MSR_VM_HSAVE_PA:
1fdbd48c 2403 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2404 case MSR_AMD64_NB_CFG:
f7c6d140 2405 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2406 case MSR_AMD64_BU_CFG2:
0c2df2a1 2407 case MSR_IA32_PERF_CTL:
405a353a 2408 case MSR_AMD64_DC_CFG:
609e36d3 2409 msr_info->data = 0;
15c4a640 2410 break;
6912ac32
WH		 2411 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2412 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2413 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2414 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2415 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2416 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2417 msr_info->data = 0;
5753785f 2418 break;
742bc670 2419 case MSR_IA32_UCODE_REV:
609e36d3 2420 msr_info->data = 0x100000000ULL;
742bc670 2421 break;
9ba075a6 2422 case MSR_MTRRcap:
9ba075a6 2423 case 0x200 ... 0x2ff:
ff53604b 2424 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2425 case 0xcd: /* fsb frequency */
609e36d3 2426 msr_info->data = 3;
15c4a640 2427 break;
7b914098
JS		 2428 /*
2429 * MSR_EBC_FREQUENCY_ID
2430 * Conservative value valid for even the basic CPU models.
2431 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2432 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2433 * and 266MHz for model 3, or 4. Set Core Clock
2434 * Frequency to System Bus Frequency Ratio to 1 (bits
2435 * 31:24) even though these are only valid for CPU
2436 * models > 2, however guests may end up dividing or
2437 * multiplying by zero otherwise.
2438 */
2439 case MSR_EBC_FREQUENCY_ID:
609e36d3 2440 msr_info->data = 1 << 24;
7b914098 2441 break;
15c4a640 2442 case MSR_IA32_APICBASE:
609e36d3 2443 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2444 break;
0105d1a5 2445 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2446 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2447 break;
a3e06bbe 2448 case MSR_IA32_TSCDEADLINE:
609e36d3 2449 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2450 break;
ba904635 2451 case MSR_IA32_TSC_ADJUST:
609e36d3 2452 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2453 break;
15c4a640 2454 case MSR_IA32_MISC_ENABLE:
609e36d3 2455 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2456 break;
64d60670
PB		 2457 case MSR_IA32_SMBASE:
2458 if (!msr_info->host_initiated)
2459 return 1;
2460 msr_info->data = vcpu->arch.smbase;
15c4a640 2461 break;
847f0ad8
AG		 2462 case MSR_IA32_PERF_STATUS:
2463 /* TSC increment by tick */
609e36d3 2464 msr_info->data = 1000ULL;
847f0ad8 2465 /* CPU multiplier */
b0996ae4 2466 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2467 break;
15c4a640 2468 case MSR_EFER:
609e36d3 2469 msr_info->data = vcpu->arch.efer;
15c4a640 2470 break;
18068523 2471 case MSR_KVM_WALL_CLOCK:
11c6bffa 2472 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2473 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2474 break;
2475 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2476 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2477 msr_info->data = vcpu->arch.time;
18068523 2478 break;
344d9588 2479 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2480 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2481 break;
c9aaa895 2482 case MSR_KVM_STEAL_TIME:
609e36d3 2483 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2484 break;
1d92128f 2485 case MSR_KVM_PV_EOI_EN:
609e36d3 2486 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2487 break;
890ca9ae
HY		 2488 case MSR_IA32_P5_MC_ADDR:
2489 case MSR_IA32_P5_MC_TYPE:
2490 case MSR_IA32_MCG_CAP:
2491 case MSR_IA32_MCG_CTL:
2492 case MSR_IA32_MCG_STATUS:
81760dcc 2493 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2494 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2495 case MSR_K7_CLK_CTL:
2496 /*
2497 * Provide expected ramp-up count for K7. All other
2498 * are set to zero, indicating minimum divisors for
2499 * every field.
2500 *
2501 * This prevents guest kernels on AMD host with CPU
2502 * type 6, model 8 and higher from exploding due to
2503 * the rdmsr failing.
2504 */
609e36d3 2505 msr_info->data = 0x20000000;
84e0cefa 2506 break;
55cd8e5a 2507 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2508 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2509 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2510 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2511 return kvm_hv_get_msr_common(vcpu,
2512 msr_info->index, &msr_info->data);
55cd8e5a 2513 break;
91c9c3ed 2514 case MSR_IA32_BBL_CR_CTL3:
2515 /* This legacy MSR exists but isn't fully documented in current
2516 * silicon. It is however accessed by winxp in very narrow
2517 * scenarios where it sets bit #19, itself documented as
2518 * a "reserved" bit. Best effort attempt to source coherent
2519 * read data here should the balance of the register be
2520 * interpreted by the guest:
2521 *
2522 * L2 cache control register 3: 64GB range, 256KB size,
2523 * enabled, latency 0x1, configured
2524 */
609e36d3 2525 msr_info->data = 0xbe702111;
91c9c3ed 2526 break;
2b036c6b
BO		 2527 case MSR_AMD64_OSVW_ID_LENGTH:
2528 if (!guest_cpuid_has_osvw(vcpu))
2529 return 1;
609e36d3 2530 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2531 break;
2532 case MSR_AMD64_OSVW_STATUS:
2533 if (!guest_cpuid_has_osvw(vcpu))
2534 return 1;
609e36d3 2535 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2536 break;
db2336a8
KH		 2537 case MSR_PLATFORM_INFO:
2538 msr_info->data = vcpu->arch.msr_platform_info;
2539 break;
2540 case MSR_MISC_FEATURES_ENABLES:
2541 msr_info->data = vcpu->arch.msr_misc_features_enables;
2542 break;
15c4a640 2543 default:
c6702c9d 2544 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2545 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2546 if (!ignore_msrs) {
ae0f5499
BD		 2547 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2548 msr_info->index);
ed85c068
AP		 2549 return 1;
2550 } else {
609e36d3
PB		 2551 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2552 msr_info->data = 0;
ed85c068
AP		 2553 }
2554 break;
15c4a640 2555 }
15c4a640
CO		 2556 return 0;
2557}
2558EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2559
313a3dc7
CO		 2560/*
2561 * Read or write a bunch of msrs. All parameters are kernel addresses.
2562 *
2563 * @return number of msrs set successfully.
2564 */
2565static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2566 struct kvm_msr_entry *entries,
2567 int (*do_msr)(struct kvm_vcpu *vcpu,
2568 unsigned index, u64 *data))
2569{
f656ce01 2570 int i, idx;
313a3dc7 2571
f656ce01 2572 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2573 for (i = 0; i < msrs->nmsrs; ++i)
2574 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2575 break;
f656ce01 2576 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2577
313a3dc7
CO		 2578 return i;
2579}
2580
2581/*
2582 * Read or write a bunch of msrs. Parameters are user addresses.
2583 *
2584 * @return number of msrs set successfully.
2585 */
2586static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2587 int (*do_msr)(struct kvm_vcpu *vcpu,
2588 unsigned index, u64 *data),
2589 int writeback)
2590{
2591 struct kvm_msrs msrs;
2592 struct kvm_msr_entry *entries;
2593 int r, n;
2594 unsigned size;
2595
2596 r = -EFAULT;
2597 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2598 goto out;
2599
2600 r = -E2BIG;
2601 if (msrs.nmsrs >= MAX_IO_MSRS)
2602 goto out;
2603
313a3dc7 2604 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2605 entries = memdup_user(user_msrs->entries, size);
2606 if (IS_ERR(entries)) {
2607 r = PTR_ERR(entries);
313a3dc7 2608 goto out;
ff5c2c03 2609 }
313a3dc7
CO		 2610
2611 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2612 if (r < 0)
2613 goto out_free;
2614
2615 r = -EFAULT;
2616 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2617 goto out_free;
2618
2619 r = n;
2620
2621out_free:
7a73c028 2622 kfree(entries);
313a3dc7
CO		 2623out:
2624 return r;
2625}
2626
784aa3d7 2627int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2628{
2629 int r;
2630
2631 switch (ext) {
2632 case KVM_CAP_IRQCHIP:
2633 case KVM_CAP_HLT:
2634 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2635 case KVM_CAP_SET_TSS_ADDR:
07716717 2636 case KVM_CAP_EXT_CPUID:
9c15bb1d 2637 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2638 case KVM_CAP_CLOCKSOURCE:
7837699f 2639 case KVM_CAP_PIT:
a28e4f5a 2640 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2641 case KVM_CAP_MP_STATE:
ed848624 2642 case KVM_CAP_SYNC_MMU:
a355c85c 2643 case KVM_CAP_USER_NMI:
52d939a0 2644 case KVM_CAP_REINJECT_CONTROL:
4925663a 2645 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2646 case KVM_CAP_IOEVENTFD:
f848a5a8 2647 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2648 case KVM_CAP_PIT2:
e9f42757 2649 case KVM_CAP_PIT_STATE2:
b927a3ce 2650 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2651 case KVM_CAP_XEN_HVM:
3cfc3092 2652 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2653 case KVM_CAP_HYPERV:
10388a07 2654 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2655 case KVM_CAP_HYPERV_SPIN:
5c919412 2656 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2657 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2658 case KVM_CAP_DEBUGREGS:
d2be1651 2659 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2660 case KVM_CAP_XSAVE:
344d9588 2661 case KVM_CAP_ASYNC_PF:
92a1f12d 2662 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2663 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2664 case KVM_CAP_READONLY_MEM:
5f66b620 2665 case KVM_CAP_HYPERV_TIME:
100943c5 2666 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2667 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2668 case KVM_CAP_ENABLE_CAP_VM:
2669 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2670 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2671 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2672 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2673 r = 1;
2674 break;
e3fd9a93
PB		 2675 case KVM_CAP_ADJUST_CLOCK:
2676 r = KVM_CLOCK_TSC_STABLE;
2677 break;
668fffa3
MT		 2678 case KVM_CAP_X86_GUEST_MWAIT:
2679 r = kvm_mwait_in_guest();
2680 break;
6d396b55
PB		 2681 case KVM_CAP_X86_SMM:
2682 /* SMBASE is usually relocated above 1M on modern chipsets,
2683 * and SMM handlers might indeed rely on 4G segment limits,
2684 * so do not report SMM to be available if real mode is
2685 * emulated via vm86 mode. Still, do not go to great lengths
2686 * to avoid userspace's usage of the feature, because it is a
2687 * fringe case that is not enabled except via specific settings
2688 * of the module parameters.
2689 */
2690 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2691 break;
774ead3a
AK		 2692 case KVM_CAP_VAPIC:
2693 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2694 break;
f725230a 2695 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2696 r = KVM_SOFT_MAX_VCPUS;
2697 break;
2698 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2699 r = KVM_MAX_VCPUS;
2700 break;
a988b910 2701 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2702 r = KVM_USER_MEM_SLOTS;
a988b910 2703 break;
a68a6a72
MT		 2704 case KVM_CAP_PV_MMU: /* obsolete */
2705 r = 0;
2f333bcb 2706 break;
890ca9ae
HY		 2707 case KVM_CAP_MCE:
2708 r = KVM_MAX_MCE_BANKS;
2709 break;
2d5b5a66 2710 case KVM_CAP_XCRS:
d366bf7e 2711 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2712 break;
92a1f12d
JR		 2713 case KVM_CAP_TSC_CONTROL:
2714 r = kvm_has_tsc_control;
2715 break;
37131313
RK		 2716 case KVM_CAP_X2APIC_API:
2717 r = KVM_X2APIC_API_VALID_FLAGS;
2718 break;
018d00d2
ZX		 2719 default:
2720 r = 0;
2721 break;
2722 }
2723 return r;
2724
2725}
2726
043405e1
CO		 2727long kvm_arch_dev_ioctl(struct file *filp,
2728 unsigned int ioctl, unsigned long arg)
2729{
2730 void __user *argp = (void __user *)arg;
2731 long r;
2732
2733 switch (ioctl) {
2734 case KVM_GET_MSR_INDEX_LIST: {
2735 struct kvm_msr_list __user *user_msr_list = argp;
2736 struct kvm_msr_list msr_list;
2737 unsigned n;
2738
2739 r = -EFAULT;
2740 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2741 goto out;
2742 n = msr_list.nmsrs;
62ef68bb 2743 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2744 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2745 goto out;
2746 r = -E2BIG;
e125e7b6 2747 if (n < msr_list.nmsrs)
043405e1
CO		 2748 goto out;
2749 r = -EFAULT;
2750 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2751 num_msrs_to_save * sizeof(u32)))
2752 goto out;
e125e7b6 2753 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2754 &emulated_msrs,
62ef68bb 2755 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2756 goto out;
2757 r = 0;
2758 break;
2759 }
9c15bb1d
BP		 2760 case KVM_GET_SUPPORTED_CPUID:
2761 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2762 struct kvm_cpuid2 __user *cpuid_arg = argp;
2763 struct kvm_cpuid2 cpuid;
2764
2765 r = -EFAULT;
2766 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2767 goto out;
9c15bb1d
BP		 2768
2769 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2770 ioctl);
674eea0f
AK		 2771 if (r)
2772 goto out;
2773
2774 r = -EFAULT;
2775 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2776 goto out;
2777 r = 0;
2778 break;
2779 }
890ca9ae 2780 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2781 r = -EFAULT;
c45dcc71
AR		 2782 if (copy_to_user(argp, &kvm_mce_cap_supported,
2783 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2784 goto out;
2785 r = 0;
2786 break;
2787 }
043405e1
CO		 2788 default:
2789 r = -EINVAL;
2790 }
2791out:
2792 return r;
2793}
2794
f5f48ee1
SY		 2795static void wbinvd_ipi(void *garbage)
2796{
2797 wbinvd();
2798}
2799
2800static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2801{
e0f0bbc5 2802 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2803}
2804
2860c4b1
PB		 2805static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2806{
2807 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2808}
2809
313a3dc7
CO		 2810void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2811{
f5f48ee1
SY		 2812 /* Address WBINVD may be executed by guest */
2813 if (need_emulate_wbinvd(vcpu)) {
2814 if (kvm_x86_ops->has_wbinvd_exit())
2815 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2816 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2817 smp_call_function_single(vcpu->cpu,
2818 wbinvd_ipi, NULL, 1);
2819 }
2820
313a3dc7 2821 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2822
0dd6a6ed
ZA		 2823 /* Apply any externally detected TSC adjustments (due to suspend) */
2824 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2825 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2826 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2827 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2828 }
8f6055cb 2829
48434c20 2830 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2831 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2832 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2833 if (tsc_delta < 0)
2834 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2835
c285545f 2836 if (check_tsc_unstable()) {
07c1419a 2837 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2838 vcpu->arch.last_guest_tsc);
a545ab6a 2839 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2840 vcpu->arch.tsc_catchup = 1;
c285545f 2841 }
e12c8f36
WL		 2842 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2843 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2844 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2845 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2846 /*
2847 * On a host with synchronized TSC, there is no need to update
2848 * kvmclock on vcpu->cpu migration
2849 */
2850 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2851 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2852 if (vcpu->cpu != cpu)
2853 kvm_migrate_timers(vcpu);
e48672fa 2854 vcpu->cpu = cpu;
6b7d7e76 2855 }
c9aaa895 2856
c9aaa895 2857 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2858}
2859
0b9f6c46
PX		 2860static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2861{
2862 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2863 return;
2864
2865 vcpu->arch.st.steal.preempted = 1;
2866
bbd64115 2867 kvm_vcpu_write_guest_offset_cached(vcpu, &vcpu->arch.st.stime,
0b9f6c46
PX		 2868 &vcpu->arch.st.steal.preempted,
2869 offsetof(struct kvm_steal_time, preempted),
2870 sizeof(vcpu->arch.st.steal.preempted));
2871}
2872
313a3dc7
CO		 2873void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2874{
cc0d907c 2875 int idx;
931f261b
AA		 2876 /*
2877 * Disable page faults because we're in atomic context here.
2878 * kvm_write_guest_offset_cached() would call might_fault()
2879 * that relies on pagefault_disable() to tell if there's a
2880 * bug. NOTE: the write to guest memory may not go through if
2881 * during postcopy live migration or if there's heavy guest
2882 * paging.
2883 */
2884 pagefault_disable();
cc0d907c
AA		 2885 /*
2886 * kvm_memslots() will be called by
2887 * kvm_write_guest_offset_cached() so take the srcu lock.
2888 */
2889 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2890 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2891 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2892 pagefault_enable();
02daab21 2893 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2894 kvm_put_guest_fpu(vcpu);
4ea1636b 2895 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2896}
2897
313a3dc7
CO		 2898static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2899 struct kvm_lapic_state *s)
2900{
76dfafd5 2901 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2902 kvm_x86_ops->sync_pir_to_irr(vcpu);
2903
a92e2543 2904 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2905}
2906
2907static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2908 struct kvm_lapic_state *s)
2909{
a92e2543
RK		 2910 int r;
2911
2912 r = kvm_apic_set_state(vcpu, s);
2913 if (r)
2914 return r;
cb142eb7 2915 update_cr8_intercept(vcpu);
313a3dc7
CO		 2916
2917 return 0;
2918}
2919
127a457a
MG		 2920static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2921{
2922 return (!lapic_in_kernel(vcpu) ||
2923 kvm_apic_accept_pic_intr(vcpu));
2924}
2925
782d422b
MG		 2926/*
2927 * if userspace requested an interrupt window, check that the
2928 * interrupt window is open.
2929 *
2930 * No need to exit to userspace if we already have an interrupt queued.
2931 */
2932static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2933{
2934 return kvm_arch_interrupt_allowed(vcpu) &&
2935 !kvm_cpu_has_interrupt(vcpu) &&
2936 !kvm_event_needs_reinjection(vcpu) &&
2937 kvm_cpu_accept_dm_intr(vcpu);
2938}
2939
f77bc6a4
ZX		 2940static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2941 struct kvm_interrupt *irq)
2942{
02cdb50f 2943 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2944 return -EINVAL;
1c1a9ce9
SR		 2945
2946 if (!irqchip_in_kernel(vcpu->kvm)) {
2947 kvm_queue_interrupt(vcpu, irq->irq, false);
2948 kvm_make_request(KVM_REQ_EVENT, vcpu);
2949 return 0;
2950 }
2951
2952 /*
2953 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2954 * fail for in-kernel 8259.
2955 */
2956 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2957 return -ENXIO;
f77bc6a4 2958
1c1a9ce9
SR		 2959 if (vcpu->arch.pending_external_vector != -1)
2960 return -EEXIST;
f77bc6a4 2961
1c1a9ce9 2962 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2963 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2964 return 0;
2965}
2966
c4abb7c9
JK		 2967static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2968{
c4abb7c9 2969 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2970
2971 return 0;
2972}
2973
f077825a
PB		 2974static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2975{
64d60670
PB		 2976 kvm_make_request(KVM_REQ_SMI, vcpu);
2977
f077825a
PB		 2978 return 0;
2979}
2980
b209749f
AK		 2981static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2982 struct kvm_tpr_access_ctl *tac)
2983{
2984 if (tac->flags)
2985 return -EINVAL;
2986 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2987 return 0;
2988}
2989
890ca9ae
HY		 2990static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2991 u64 mcg_cap)
2992{
2993 int r;
2994 unsigned bank_num = mcg_cap & 0xff, bank;
2995
2996 r = -EINVAL;
a9e38c3e 2997 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2998 goto out;
c45dcc71 2999 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3000 goto out;
3001 r = 0;
3002 vcpu->arch.mcg_cap = mcg_cap;
3003 /* Init IA32_MCG_CTL to all 1s */
3004 if (mcg_cap & MCG_CTL_P)
3005 vcpu->arch.mcg_ctl = ~(u64)0;
3006 /* Init IA32_MCi_CTL to all 1s */
3007 for (bank = 0; bank < bank_num; bank++)
3008 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3009
3010 if (kvm_x86_ops->setup_mce)
3011 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3012out:
3013 return r;
3014}
3015
3016static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3017 struct kvm_x86_mce *mce)
3018{
3019 u64 mcg_cap = vcpu->arch.mcg_cap;
3020 unsigned bank_num = mcg_cap & 0xff;
3021 u64 *banks = vcpu->arch.mce_banks;
3022
3023 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3024 return -EINVAL;
3025 /*
3026 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3027 * reporting is disabled
3028 */
3029 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3030 vcpu->arch.mcg_ctl != ~(u64)0)
3031 return 0;
3032 banks += 4 * mce->bank;
3033 /*
3034 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3035 * reporting is disabled for the bank
3036 */
3037 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3038 return 0;
3039 if (mce->status & MCI_STATUS_UC) {
3040 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3041 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3042 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3043 return 0;
3044 }
3045 if (banks[1] & MCI_STATUS_VAL)
3046 mce->status |= MCI_STATUS_OVER;
3047 banks[2] = mce->addr;
3048 banks[3] = mce->misc;
3049 vcpu->arch.mcg_status = mce->mcg_status;
3050 banks[1] = mce->status;
3051 kvm_queue_exception(vcpu, MC_VECTOR);
3052 } else if (!(banks[1] & MCI_STATUS_VAL)
3053 || !(banks[1] & MCI_STATUS_UC)) {
3054 if (banks[1] & MCI_STATUS_VAL)
3055 mce->status |= MCI_STATUS_OVER;
3056 banks[2] = mce->addr;
3057 banks[3] = mce->misc;
3058 banks[1] = mce->status;
3059 } else
3060 banks[1] |= MCI_STATUS_OVER;
3061 return 0;
3062}
3063
3cfc3092
JK		 3064static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3065 struct kvm_vcpu_events *events)
3066{
7460fb4a 3067 process_nmi(vcpu);
03b82a30
JK		 3068 events->exception.injected =
3069 vcpu->arch.exception.pending &&
3070 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3071 events->exception.nr = vcpu->arch.exception.nr;
3072 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3073 events->exception.pad = 0;
3cfc3092
JK		 3074 events->exception.error_code = vcpu->arch.exception.error_code;
3075
03b82a30
JK		 3076 events->interrupt.injected =
3077 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3078 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3079 events->interrupt.soft = 0;
37ccdcbe 3080 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3081
3082 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3083 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3084 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3085 events->nmi.pad = 0;
3cfc3092 3086
66450a21 3087 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3088
f077825a
PB		 3089 events->smi.smm = is_smm(vcpu);
3090 events->smi.pending = vcpu->arch.smi_pending;
3091 events->smi.smm_inside_nmi =
3092 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3093 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3094
dab4b911 3095 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3096 | KVM_VCPUEVENT_VALID_SHADOW
3097 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3098 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3099}
3100
6ef4e07e
XG		 3101static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3102
3cfc3092
JK		 3103static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3104 struct kvm_vcpu_events *events)
3105{
dab4b911 3106 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3107 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3108 | KVM_VCPUEVENT_VALID_SHADOW
3109 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3110 return -EINVAL;
3111
78e546c8 3112 if (events->exception.injected &&
28d06353
JM		 3113 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3114 is_guest_mode(vcpu)))
78e546c8
PB		 3115 return -EINVAL;
3116
28bf2888
DH		 3117 /* INITs are latched while in SMM */
3118 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3119 (events->smi.smm || events->smi.pending) &&
3120 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3121 return -EINVAL;
3122
7460fb4a 3123 process_nmi(vcpu);
3cfc3092
JK		 3124 vcpu->arch.exception.pending = events->exception.injected;
3125 vcpu->arch.exception.nr = events->exception.nr;
3126 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3127 vcpu->arch.exception.error_code = events->exception.error_code;
3128
3129 vcpu->arch.interrupt.pending = events->interrupt.injected;
3130 vcpu->arch.interrupt.nr = events->interrupt.nr;
3131 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3132 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3133 kvm_x86_ops->set_interrupt_shadow(vcpu,
3134 events->interrupt.shadow);
3cfc3092
JK		 3135
3136 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3137 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3138 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3139 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3140
66450a21 3141 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3142 lapic_in_kernel(vcpu))
66450a21 3143 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3144
f077825a 3145 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3146 u32 hflags = vcpu->arch.hflags;
f077825a 3147 if (events->smi.smm)
6ef4e07e 3148 hflags |= HF_SMM_MASK;
f077825a 3149 else
6ef4e07e
XG		 3150 hflags &= ~HF_SMM_MASK;
3151 kvm_set_hflags(vcpu, hflags);
3152
f077825a
PB		 3153 vcpu->arch.smi_pending = events->smi.pending;
3154 if (events->smi.smm_inside_nmi)
3155 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3156 else
3157 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3158 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3159 if (events->smi.latched_init)
3160 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3161 else
3162 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3163 }
3164 }
3165
3842d135
AK		 3166 kvm_make_request(KVM_REQ_EVENT, vcpu);
3167
3cfc3092
JK		 3168 return 0;
3169}
3170
a1efbe77
JK		 3171static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3172 struct kvm_debugregs *dbgregs)
3173{
73aaf249
JK		 3174 unsigned long val;
3175
a1efbe77 3176 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3177 kvm_get_dr(vcpu, 6, &val);
73aaf249 3178 dbgregs->dr6 = val;
a1efbe77
JK		 3179 dbgregs->dr7 = vcpu->arch.dr7;
3180 dbgregs->flags = 0;
97e69aa6 3181 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3182}
3183
3184static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3185 struct kvm_debugregs *dbgregs)
3186{
3187 if (dbgregs->flags)
3188 return -EINVAL;
3189
d14bdb55
PB		 3190 if (dbgregs->dr6 & ~0xffffffffull)
3191 return -EINVAL;
3192 if (dbgregs->dr7 & ~0xffffffffull)
3193 return -EINVAL;
3194
a1efbe77 3195 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3196 kvm_update_dr0123(vcpu);
a1efbe77 3197 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3198 kvm_update_dr6(vcpu);
a1efbe77 3199 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3200 kvm_update_dr7(vcpu);
a1efbe77 3201
a1efbe77
JK		 3202 return 0;
3203}
3204
df1daba7
PB		 3205#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3206
3207static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3208{
c47ada30 3209 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3210 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3211 u64 valid;
3212
3213 /*
3214 * Copy legacy XSAVE area, to avoid complications with CPUID
3215 * leaves 0 and 1 in the loop below.
3216 */
3217 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3218
3219 /* Set XSTATE_BV */
00c87e9a 3220 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3221 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3222
3223 /*
3224 * Copy each region from the possibly compacted offset to the
3225 * non-compacted offset.
3226 */
d91cab78 3227 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3228 while (valid) {
3229 u64 feature = valid & -valid;
3230 int index = fls64(feature) - 1;
3231 void *src = get_xsave_addr(xsave, feature);
3232
3233 if (src) {
3234 u32 size, offset, ecx, edx;
3235 cpuid_count(XSTATE_CPUID, index,
3236 &size, &offset, &ecx, &edx);
3237 memcpy(dest + offset, src, size);
3238 }
3239
3240 valid -= feature;
3241 }
3242}
3243
3244static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3245{
c47ada30 3246 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3247 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3248 u64 valid;
3249
3250 /*
3251 * Copy legacy XSAVE area, to avoid complications with CPUID
3252 * leaves 0 and 1 in the loop below.
3253 */
3254 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3255
3256 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3257 xsave->header.xfeatures = xstate_bv;
782511b0 3258 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3259 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3260
3261 /*
3262 * Copy each region from the non-compacted offset to the
3263 * possibly compacted offset.
3264 */
d91cab78 3265 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3266 while (valid) {
3267 u64 feature = valid & -valid;
3268 int index = fls64(feature) - 1;
3269 void *dest = get_xsave_addr(xsave, feature);
3270
3271 if (dest) {
3272 u32 size, offset, ecx, edx;
3273 cpuid_count(XSTATE_CPUID, index,
3274 &size, &offset, &ecx, &edx);
3275 memcpy(dest, src + offset, size);
ee4100da 3276 }
df1daba7
PB		 3277
3278 valid -= feature;
3279 }
3280}
3281
2d5b5a66
SY		 3282static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3283 struct kvm_xsave *guest_xsave)
3284{
d366bf7e 3285 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3286 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3287 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3288 } else {
2d5b5a66 3289 memcpy(guest_xsave->region,
7366ed77 3290 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3291 sizeof(struct fxregs_state));
2d5b5a66 3292 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3293 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3294 }
3295}
3296
3297static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3298 struct kvm_xsave *guest_xsave)
3299{
3300 u64 xstate_bv =
3301 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3302
d366bf7e 3303 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3304 /*
3305 * Here we allow setting states that are not present in
3306 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3307 * with old userspace.
3308 */
4ff41732 3309 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3310 return -EINVAL;
df1daba7 3311 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3312 } else {
d91cab78 3313 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3314 return -EINVAL;
7366ed77 3315 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3316 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3317 }
3318 return 0;
3319}
3320
3321static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3322 struct kvm_xcrs *guest_xcrs)
3323{
d366bf7e 3324 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3325 guest_xcrs->nr_xcrs = 0;
3326 return;
3327 }
3328
3329 guest_xcrs->nr_xcrs = 1;
3330 guest_xcrs->flags = 0;
3331 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3332 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3333}
3334
3335static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3336 struct kvm_xcrs *guest_xcrs)
3337{
3338 int i, r = 0;
3339
d366bf7e 3340 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3341 return -EINVAL;
3342
3343 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3344 return -EINVAL;
3345
3346 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3347 /* Only support XCR0 currently */
c67a04cb 3348 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3349 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3350 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3351 break;
3352 }
3353 if (r)
3354 r = -EINVAL;
3355 return r;
3356}
3357
1c0b28c2
EM		 3358/*
3359 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3360 * stopped by the hypervisor. This function will be called from the host only.
3361 * EINVAL is returned when the host attempts to set the flag for a guest that
3362 * does not support pv clocks.
3363 */
3364static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3365{
0b79459b 3366 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3367 return -EINVAL;
51d59c6b 3368 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3369 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3370 return 0;
3371}
3372
5c919412
AS		 3373static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3374 struct kvm_enable_cap *cap)
3375{
3376 if (cap->flags)
3377 return -EINVAL;
3378
3379 switch (cap->cap) {
3380 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3381 if (!irqchip_in_kernel(vcpu->kvm))
3382 return -EINVAL;
5c919412
AS		 3383 return kvm_hv_activate_synic(vcpu);
3384 default:
3385 return -EINVAL;
3386 }
3387}
3388
313a3dc7
CO		 3389long kvm_arch_vcpu_ioctl(struct file *filp,
3390 unsigned int ioctl, unsigned long arg)
3391{
3392 struct kvm_vcpu *vcpu = filp->private_data;
3393 void __user *argp = (void __user *)arg;
3394 int r;
d1ac91d8
AK		 3395 union {
3396 struct kvm_lapic_state *lapic;
3397 struct kvm_xsave *xsave;
3398 struct kvm_xcrs *xcrs;
3399 void *buffer;
3400 } u;
3401
3402 u.buffer = NULL;
313a3dc7
CO		 3403 switch (ioctl) {
3404 case KVM_GET_LAPIC: {
2204ae3c 3405 r = -EINVAL;
bce87cce 3406 if (!lapic_in_kernel(vcpu))
2204ae3c 3407 goto out;
d1ac91d8 3408 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3409
b772ff36 3410 r = -ENOMEM;
d1ac91d8 3411 if (!u.lapic)
b772ff36 3412 goto out;
d1ac91d8 3413 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3414 if (r)
3415 goto out;
3416 r = -EFAULT;
d1ac91d8 3417 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3418 goto out;
3419 r = 0;
3420 break;
3421 }
3422 case KVM_SET_LAPIC: {
2204ae3c 3423 r = -EINVAL;
bce87cce 3424 if (!lapic_in_kernel(vcpu))
2204ae3c 3425 goto out;
ff5c2c03 3426 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3427 if (IS_ERR(u.lapic))
3428 return PTR_ERR(u.lapic);
ff5c2c03 3429
d1ac91d8 3430 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3431 break;
3432 }
f77bc6a4
ZX		 3433 case KVM_INTERRUPT: {
3434 struct kvm_interrupt irq;
3435
3436 r = -EFAULT;
3437 if (copy_from_user(&irq, argp, sizeof irq))
3438 goto out;
3439 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3440 break;
3441 }
c4abb7c9
JK		 3442 case KVM_NMI: {
3443 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3444 break;
3445 }
f077825a
PB		 3446 case KVM_SMI: {
3447 r = kvm_vcpu_ioctl_smi(vcpu);
3448 break;
3449 }
313a3dc7
CO		 3450 case KVM_SET_CPUID: {
3451 struct kvm_cpuid __user *cpuid_arg = argp;
3452 struct kvm_cpuid cpuid;
3453
3454 r = -EFAULT;
3455 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3456 goto out;
3457 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3458 break;
3459 }
07716717
DK		 3460 case KVM_SET_CPUID2: {
3461 struct kvm_cpuid2 __user *cpuid_arg = argp;
3462 struct kvm_cpuid2 cpuid;
3463
3464 r = -EFAULT;
3465 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3466 goto out;
3467 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3468 cpuid_arg->entries);
07716717
DK		 3469 break;
3470 }
3471 case KVM_GET_CPUID2: {
3472 struct kvm_cpuid2 __user *cpuid_arg = argp;
3473 struct kvm_cpuid2 cpuid;
3474
3475 r = -EFAULT;
3476 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3477 goto out;
3478 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3479 cpuid_arg->entries);
07716717
DK		 3480 if (r)
3481 goto out;
3482 r = -EFAULT;
3483 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3484 goto out;
3485 r = 0;
3486 break;
3487 }
313a3dc7 3488 case KVM_GET_MSRS:
609e36d3 3489 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3490 break;
3491 case KVM_SET_MSRS:
3492 r = msr_io(vcpu, argp, do_set_msr, 0);
3493 break;
b209749f
AK		 3494 case KVM_TPR_ACCESS_REPORTING: {
3495 struct kvm_tpr_access_ctl tac;
3496
3497 r = -EFAULT;
3498 if (copy_from_user(&tac, argp, sizeof tac))
3499 goto out;
3500 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3501 if (r)
3502 goto out;
3503 r = -EFAULT;
3504 if (copy_to_user(argp, &tac, sizeof tac))
3505 goto out;
3506 r = 0;
3507 break;
3508 };
b93463aa
AK		 3509 case KVM_SET_VAPIC_ADDR: {
3510 struct kvm_vapic_addr va;
7301d6ab 3511 int idx;
b93463aa
AK		 3512
3513 r = -EINVAL;
35754c98 3514 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3515 goto out;
3516 r = -EFAULT;
3517 if (copy_from_user(&va, argp, sizeof va))
3518 goto out;
7301d6ab 3519 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3520 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3521 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3522 break;
3523 }
890ca9ae
HY		 3524 case KVM_X86_SETUP_MCE: {
3525 u64 mcg_cap;
3526
3527 r = -EFAULT;
3528 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3529 goto out;
3530 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3531 break;
3532 }
3533 case KVM_X86_SET_MCE: {
3534 struct kvm_x86_mce mce;
3535
3536 r = -EFAULT;
3537 if (copy_from_user(&mce, argp, sizeof mce))
3538 goto out;
3539 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3540 break;
3541 }
3cfc3092
JK		 3542 case KVM_GET_VCPU_EVENTS: {
3543 struct kvm_vcpu_events events;
3544
3545 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3546
3547 r = -EFAULT;
3548 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3549 break;
3550 r = 0;
3551 break;
3552 }
3553 case KVM_SET_VCPU_EVENTS: {
3554 struct kvm_vcpu_events events;
3555
3556 r = -EFAULT;
3557 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3558 break;
3559
3560 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3561 break;
3562 }
a1efbe77
JK		 3563 case KVM_GET_DEBUGREGS: {
3564 struct kvm_debugregs dbgregs;
3565
3566 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3567
3568 r = -EFAULT;
3569 if (copy_to_user(argp, &dbgregs,
3570 sizeof(struct kvm_debugregs)))
3571 break;
3572 r = 0;
3573 break;
3574 }
3575 case KVM_SET_DEBUGREGS: {
3576 struct kvm_debugregs dbgregs;
3577
3578 r = -EFAULT;
3579 if (copy_from_user(&dbgregs, argp,
3580 sizeof(struct kvm_debugregs)))
3581 break;
3582
3583 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3584 break;
3585 }
2d5b5a66 3586 case KVM_GET_XSAVE: {
d1ac91d8 3587 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3588 r = -ENOMEM;
d1ac91d8 3589 if (!u.xsave)
2d5b5a66
SY		 3590 break;
3591
d1ac91d8 3592 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3593
3594 r = -EFAULT;
d1ac91d8 3595 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3596 break;
3597 r = 0;
3598 break;
3599 }
3600 case KVM_SET_XSAVE: {
ff5c2c03 3601 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3602 if (IS_ERR(u.xsave))
3603 return PTR_ERR(u.xsave);
2d5b5a66 3604
d1ac91d8 3605 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3606 break;
3607 }
3608 case KVM_GET_XCRS: {
d1ac91d8 3609 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3610 r = -ENOMEM;
d1ac91d8 3611 if (!u.xcrs)
2d5b5a66
SY		 3612 break;
3613
d1ac91d8 3614 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3615
3616 r = -EFAULT;
d1ac91d8 3617 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3618 sizeof(struct kvm_xcrs)))
3619 break;
3620 r = 0;
3621 break;
3622 }
3623 case KVM_SET_XCRS: {
ff5c2c03 3624 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3625 if (IS_ERR(u.xcrs))
3626 return PTR_ERR(u.xcrs);
2d5b5a66 3627
d1ac91d8 3628 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3629 break;
3630 }
92a1f12d
JR		 3631 case KVM_SET_TSC_KHZ: {
3632 u32 user_tsc_khz;
3633
3634 r = -EINVAL;
92a1f12d
JR		 3635 user_tsc_khz = (u32)arg;
3636
3637 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3638 goto out;
3639
cc578287
ZA		 3640 if (user_tsc_khz == 0)
3641 user_tsc_khz = tsc_khz;
3642
381d585c
HZ		 3643 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3644 r = 0;
92a1f12d 3645
92a1f12d
JR		 3646 goto out;
3647 }
3648 case KVM_GET_TSC_KHZ: {
cc578287 3649 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3650 goto out;
3651 }
1c0b28c2
EM		 3652 case KVM_KVMCLOCK_CTRL: {
3653 r = kvm_set_guest_paused(vcpu);
3654 goto out;
3655 }
5c919412
AS		 3656 case KVM_ENABLE_CAP: {
3657 struct kvm_enable_cap cap;
3658
3659 r = -EFAULT;
3660 if (copy_from_user(&cap, argp, sizeof(cap)))
3661 goto out;
3662 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3663 break;
3664 }
313a3dc7
CO		 3665 default:
3666 r = -EINVAL;
3667 }
3668out:
d1ac91d8 3669 kfree(u.buffer);
313a3dc7
CO		 3670 return r;
3671}
3672
5b1c1493
CO		 3673int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3674{
3675 return VM_FAULT_SIGBUS;
3676}
3677
1fe779f8
CO		 3678static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3679{
3680 int ret;
3681
3682 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3683 return -EINVAL;
1fe779f8
CO		 3684 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3685 return ret;
3686}
3687
b927a3ce
SY		 3688static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3689 u64 ident_addr)
3690{
3691 kvm->arch.ept_identity_map_addr = ident_addr;
3692 return 0;
3693}
3694
1fe779f8
CO		 3695static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3696 u32 kvm_nr_mmu_pages)
3697{
3698 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3699 return -EINVAL;
3700
79fac95e 3701 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3702
3703 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3704 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3705
79fac95e 3706 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3707 return 0;
3708}
3709
3710static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3711{
39de71ec 3712 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3713}
3714
1fe779f8
CO		 3715static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3716{
90bca052 3717 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3718 int r;
3719
3720 r = 0;
3721 switch (chip->chip_id) {
3722 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3723 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3724 sizeof(struct kvm_pic_state));
3725 break;
3726 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3727 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3728 sizeof(struct kvm_pic_state));
3729 break;
3730 case KVM_IRQCHIP_IOAPIC:
33392b49 3731 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3732 break;
3733 default:
3734 r = -EINVAL;
3735 break;
3736 }
3737 return r;
3738}
3739
3740static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3741{
90bca052 3742 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3743 int r;
3744
3745 r = 0;
3746 switch (chip->chip_id) {
3747 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3748 spin_lock(&pic->lock);
3749 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3750 sizeof(struct kvm_pic_state));
90bca052 3751 spin_unlock(&pic->lock);
1fe779f8
CO		 3752 break;
3753 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3754 spin_lock(&pic->lock);
3755 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3756 sizeof(struct kvm_pic_state));
90bca052 3757 spin_unlock(&pic->lock);
1fe779f8
CO		 3758 break;
3759 case KVM_IRQCHIP_IOAPIC:
33392b49 3760 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3761 break;
3762 default:
3763 r = -EINVAL;
3764 break;
3765 }
90bca052 3766 kvm_pic_update_irq(pic);
1fe779f8
CO		 3767 return r;
3768}
3769
e0f63cb9
SY		 3770static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3771{
34f3941c
RK		 3772 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3773
3774 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3775
3776 mutex_lock(&kps->lock);
3777 memcpy(ps, &kps->channels, sizeof(*ps));
3778 mutex_unlock(&kps->lock);
2da29bcc 3779 return 0;
e0f63cb9
SY		 3780}
3781
3782static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3783{
0185604c 3784 int i;
09edea72
RK		 3785 struct kvm_pit *pit = kvm->arch.vpit;
3786
3787 mutex_lock(&pit->pit_state.lock);
34f3941c 3788 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3789 for (i = 0; i < 3; i++)
09edea72
RK		 3790 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3791 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3792 return 0;
e9f42757
BK		 3793}
3794
3795static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3796{
e9f42757
BK		 3797 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3798 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3799 sizeof(ps->channels));
3800 ps->flags = kvm->arch.vpit->pit_state.flags;
3801 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3802 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3803 return 0;
e9f42757
BK		 3804}
3805
3806static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3807{
2da29bcc 3808 int start = 0;
0185604c 3809 int i;
e9f42757 3810 u32 prev_legacy, cur_legacy;
09edea72
RK		 3811 struct kvm_pit *pit = kvm->arch.vpit;
3812
3813 mutex_lock(&pit->pit_state.lock);
3814 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3815 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3816 if (!prev_legacy && cur_legacy)
3817 start = 1;
09edea72
RK		 3818 memcpy(&pit->pit_state.channels, &ps->channels,
3819 sizeof(pit->pit_state.channels));
3820 pit->pit_state.flags = ps->flags;
0185604c 3821 for (i = 0; i < 3; i++)
09edea72 3822 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3823 start && i == 0);
09edea72 3824 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3825 return 0;
e0f63cb9
SY		 3826}
3827
52d939a0
MT		 3828static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3829 struct kvm_reinject_control *control)
3830{
71474e2f
RK		 3831 struct kvm_pit *pit = kvm->arch.vpit;
3832
3833 if (!pit)
52d939a0 3834 return -ENXIO;
b39c90b6 3835
71474e2f
RK		 3836 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3837 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3838 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3839 */
3840 mutex_lock(&pit->pit_state.lock);
3841 kvm_pit_set_reinject(pit, control->pit_reinject);
3842 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3843
52d939a0
MT		 3844 return 0;
3845}
3846
95d4c16c 3847/**
60c34612
TY		 3848 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3849 * @kvm: kvm instance
3850 * @log: slot id and address to which we copy the log
95d4c16c 3851 *
e108ff2f
PB		 3852 * Steps 1-4 below provide general overview of dirty page logging. See
3853 * kvm_get_dirty_log_protect() function description for additional details.
3854 *
3855 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3856 * always flush the TLB (step 4) even if previous step failed and the dirty
3857 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3858 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3859 * writes will be marked dirty for next log read.
95d4c16c 3860 *
60c34612
TY		 3861 * 1. Take a snapshot of the bit and clear it if needed.
3862 * 2. Write protect the corresponding page.
e108ff2f
PB		 3863 * 3. Copy the snapshot to the userspace.
3864 * 4. Flush TLB's if needed.
5bb064dc 3865 */
60c34612 3866int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3867{
60c34612 3868 bool is_dirty = false;
e108ff2f 3869 int r;
5bb064dc 3870
79fac95e 3871 mutex_lock(&kvm->slots_lock);
5bb064dc 3872
88178fd4
KH		 3873 /*
3874 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3875 */
3876 if (kvm_x86_ops->flush_log_dirty)
3877 kvm_x86_ops->flush_log_dirty(kvm);
3878
e108ff2f 3879 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3880
3881 /*
3882 * All the TLBs can be flushed out of mmu lock, see the comments in
3883 * kvm_mmu_slot_remove_write_access().
3884 */
e108ff2f 3885 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3886 if (is_dirty)
3887 kvm_flush_remote_tlbs(kvm);
3888
79fac95e 3889 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3890 return r;
3891}
3892
aa2fbe6d
YZ		 3893int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3894 bool line_status)
23d43cf9
CD		 3895{
3896 if (!irqchip_in_kernel(kvm))
3897 return -ENXIO;
3898
3899 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3900 irq_event->irq, irq_event->level,
3901 line_status);
23d43cf9
CD		 3902 return 0;
3903}
3904
90de4a18
NA		 3905static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3906 struct kvm_enable_cap *cap)
3907{
3908 int r;
3909
3910 if (cap->flags)
3911 return -EINVAL;
3912
3913 switch (cap->cap) {
3914 case KVM_CAP_DISABLE_QUIRKS:
3915 kvm->arch.disabled_quirks = cap->args[0];
3916 r = 0;
3917 break;
49df6397
SR		 3918 case KVM_CAP_SPLIT_IRQCHIP: {
3919 mutex_lock(&kvm->lock);
b053b2ae
SR		 3920 r = -EINVAL;
3921 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3922 goto split_irqchip_unlock;
49df6397
SR		 3923 r = -EEXIST;
3924 if (irqchip_in_kernel(kvm))
3925 goto split_irqchip_unlock;
557abc40 3926 if (kvm->created_vcpus)
49df6397 3927 goto split_irqchip_unlock;
637e3f86 3928 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
49df6397 3929 r = kvm_setup_empty_irq_routing(kvm);
637e3f86
DH		 3930 if (r) {
3931 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
3932 /* Pairs with smp_rmb() when reading irqchip_mode */
3933 smp_wmb();
49df6397 3934 goto split_irqchip_unlock;
637e3f86 3935 }
49df6397
SR		 3936 /* Pairs with irqchip_in_kernel. */
3937 smp_wmb();
49776faf 3938 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3939 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3940 r = 0;
3941split_irqchip_unlock:
3942 mutex_unlock(&kvm->lock);
3943 break;
3944 }
37131313
RK		 3945 case KVM_CAP_X2APIC_API:
3946 r = -EINVAL;
3947 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3948 break;
3949
3950 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3951 kvm->arch.x2apic_format = true;
c519265f
RK		 3952 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3953 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3954
3955 r = 0;
3956 break;
90de4a18
NA		 3957 default:
3958 r = -EINVAL;
3959 break;
3960 }
3961 return r;
3962}
3963
1fe779f8
CO		 3964long kvm_arch_vm_ioctl(struct file *filp,
3965 unsigned int ioctl, unsigned long arg)
3966{
3967 struct kvm *kvm = filp->private_data;
3968 void __user *argp = (void __user *)arg;
367e1319 3969 int r = -ENOTTY;
f0d66275
DH		 3970 /*
3971 * This union makes it completely explicit to gcc-3.x
3972 * that these two variables' stack usage should be
3973 * combined, not added together.
3974 */
3975 union {
3976 struct kvm_pit_state ps;
e9f42757 3977 struct kvm_pit_state2 ps2;
c5ff41ce 3978 struct kvm_pit_config pit_config;
f0d66275 3979 } u;
1fe779f8
CO		 3980
3981 switch (ioctl) {
3982 case KVM_SET_TSS_ADDR:
3983 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3984 break;
b927a3ce
SY		 3985 case KVM_SET_IDENTITY_MAP_ADDR: {
3986 u64 ident_addr;
3987
3988 r = -EFAULT;
3989 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3990 goto out;
3991 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3992 break;
3993 }
1fe779f8
CO		 3994 case KVM_SET_NR_MMU_PAGES:
3995 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3996 break;
3997 case KVM_GET_NR_MMU_PAGES:
3998 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3999 break;
3ddea128 4000 case KVM_CREATE_IRQCHIP: {
3ddea128 4001 mutex_lock(&kvm->lock);
09941366 4002
3ddea128 4003 r = -EEXIST;
35e6eaa3 4004 if (irqchip_in_kernel(kvm))
3ddea128 4005 goto create_irqchip_unlock;
09941366 4006
3e515705 4007 r = -EINVAL;
557abc40 4008 if (kvm->created_vcpus)
3e515705 4009 goto create_irqchip_unlock;
09941366
RK		 4010
4011 r = kvm_pic_init(kvm);
4012 if (r)
3ddea128 4013 goto create_irqchip_unlock;
09941366
RK		 4014
4015 r = kvm_ioapic_init(kvm);
4016 if (r) {
09941366 4017 kvm_pic_destroy(kvm);
3ddea128 4018 goto create_irqchip_unlock;
09941366
RK		 4019 }
4020
637e3f86 4021 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
399ec807
AK		 4022 r = kvm_setup_default_irq_routing(kvm);
4023 if (r) {
637e3f86
DH		 4024 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
4025 /* Pairs with smp_rmb() when reading irqchip_mode */
4026 smp_wmb();
72bb2fcd 4027 kvm_ioapic_destroy(kvm);
09941366 4028 kvm_pic_destroy(kvm);
71ba994c 4029 goto create_irqchip_unlock;
399ec807 4030 }
49776faf 4031 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4032 smp_wmb();
49776faf 4033 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4034 create_irqchip_unlock:
4035 mutex_unlock(&kvm->lock);
1fe779f8 4036 break;
3ddea128 4037 }
7837699f 4038 case KVM_CREATE_PIT:
c5ff41ce
JK		 4039 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4040 goto create_pit;
4041 case KVM_CREATE_PIT2:
4042 r = -EFAULT;
4043 if (copy_from_user(&u.pit_config, argp,
4044 sizeof(struct kvm_pit_config)))
4045 goto out;
4046 create_pit:
250715a6 4047 mutex_lock(&kvm->lock);
269e05e4
AK		 4048 r = -EEXIST;
4049 if (kvm->arch.vpit)
4050 goto create_pit_unlock;
7837699f 4051 r = -ENOMEM;
c5ff41ce 4052 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4053 if (kvm->arch.vpit)
4054 r = 0;
269e05e4 4055 create_pit_unlock:
250715a6 4056 mutex_unlock(&kvm->lock);
7837699f 4057 break;
1fe779f8
CO		 4058 case KVM_GET_IRQCHIP: {
4059 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4060 struct kvm_irqchip *chip;
1fe779f8 4061
ff5c2c03
SL		 4062 chip = memdup_user(argp, sizeof(*chip));
4063 if (IS_ERR(chip)) {
4064 r = PTR_ERR(chip);
1fe779f8 4065 goto out;
ff5c2c03
SL		 4066 }
4067
1fe779f8 4068 r = -ENXIO;
826da321 4069 if (!irqchip_kernel(kvm))
f0d66275
DH		 4070 goto get_irqchip_out;
4071 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4072 if (r)
f0d66275 4073 goto get_irqchip_out;
1fe779f8 4074 r = -EFAULT;
f0d66275
DH		 4075 if (copy_to_user(argp, chip, sizeof *chip))
4076 goto get_irqchip_out;
1fe779f8 4077 r = 0;
f0d66275
DH		 4078 get_irqchip_out:
4079 kfree(chip);
1fe779f8
CO		 4080 break;
4081 }
4082 case KVM_SET_IRQCHIP: {
4083 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4084 struct kvm_irqchip *chip;
1fe779f8 4085
ff5c2c03
SL		 4086 chip = memdup_user(argp, sizeof(*chip));
4087 if (IS_ERR(chip)) {
4088 r = PTR_ERR(chip);
1fe779f8 4089 goto out;
ff5c2c03
SL		 4090 }
4091
1fe779f8 4092 r = -ENXIO;
826da321 4093 if (!irqchip_kernel(kvm))
f0d66275
DH		 4094 goto set_irqchip_out;
4095 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4096 if (r)
f0d66275 4097 goto set_irqchip_out;
1fe779f8 4098 r = 0;
f0d66275
DH		 4099 set_irqchip_out:
4100 kfree(chip);
1fe779f8
CO		 4101 break;
4102 }
e0f63cb9 4103 case KVM_GET_PIT: {
e0f63cb9 4104 r = -EFAULT;
f0d66275 4105 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4106 goto out;
4107 r = -ENXIO;
4108 if (!kvm->arch.vpit)
4109 goto out;
f0d66275 4110 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4111 if (r)
4112 goto out;
4113 r = -EFAULT;
f0d66275 4114 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4115 goto out;
4116 r = 0;
4117 break;
4118 }
4119 case KVM_SET_PIT: {
e0f63cb9 4120 r = -EFAULT;
f0d66275 4121 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4122 goto out;
4123 r = -ENXIO;
4124 if (!kvm->arch.vpit)
4125 goto out;
f0d66275 4126 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4127 break;
4128 }
e9f42757
BK		 4129 case KVM_GET_PIT2: {
4130 r = -ENXIO;
4131 if (!kvm->arch.vpit)
4132 goto out;
4133 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4134 if (r)
4135 goto out;
4136 r = -EFAULT;
4137 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4138 goto out;
4139 r = 0;
4140 break;
4141 }
4142 case KVM_SET_PIT2: {
4143 r = -EFAULT;
4144 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4145 goto out;
4146 r = -ENXIO;
4147 if (!kvm->arch.vpit)
4148 goto out;
4149 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4150 break;
4151 }
52d939a0
MT		 4152 case KVM_REINJECT_CONTROL: {
4153 struct kvm_reinject_control control;
4154 r = -EFAULT;
4155 if (copy_from_user(&control, argp, sizeof(control)))
4156 goto out;
4157 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4158 break;
4159 }
d71ba788
PB		 4160 case KVM_SET_BOOT_CPU_ID:
4161 r = 0;
4162 mutex_lock(&kvm->lock);
557abc40 4163 if (kvm->created_vcpus)
d71ba788
PB		 4164 r = -EBUSY;
4165 else
4166 kvm->arch.bsp_vcpu_id = arg;
4167 mutex_unlock(&kvm->lock);
4168 break;
ffde22ac
ES		 4169 case KVM_XEN_HVM_CONFIG: {
4170 r = -EFAULT;
4171 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4172 sizeof(struct kvm_xen_hvm_config)))
4173 goto out;
4174 r = -EINVAL;
4175 if (kvm->arch.xen_hvm_config.flags)
4176 goto out;
4177 r = 0;
4178 break;
4179 }
afbcf7ab 4180 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4181 struct kvm_clock_data user_ns;
4182 u64 now_ns;
afbcf7ab
GC		 4183
4184 r = -EFAULT;
4185 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4186 goto out;
4187
4188 r = -EINVAL;
4189 if (user_ns.flags)
4190 goto out;
4191
4192 r = 0;
e891a32e 4193 now_ns = get_kvmclock_ns(kvm);
108b249c 4194 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
2e762ff7 4195 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4196 break;
4197 }
4198 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4199 struct kvm_clock_data user_ns;
4200 u64 now_ns;
4201
e891a32e 4202 now_ns = get_kvmclock_ns(kvm);
108b249c 4203 user_ns.clock = now_ns;
e3fd9a93 4204 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4205 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4206
4207 r = -EFAULT;
4208 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4209 goto out;
4210 r = 0;
4211 break;
4212 }
90de4a18
NA		 4213 case KVM_ENABLE_CAP: {
4214 struct kvm_enable_cap cap;
afbcf7ab 4215
90de4a18
NA		 4216 r = -EFAULT;
4217 if (copy_from_user(&cap, argp, sizeof(cap)))
4218 goto out;
4219 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4220 break;
4221 }
1fe779f8 4222 default:
ad6260da 4223 r = -ENOTTY;
1fe779f8
CO		 4224 }
4225out:
4226 return r;
4227}
4228
a16b043c 4229static void kvm_init_msr_list(void)
043405e1
CO		 4230{
4231 u32 dummy[2];
4232 unsigned i, j;
4233
62ef68bb 4234 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4235 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4236 continue;
93c4adc7
PB		 4237
4238 /*
4239 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4240 * to the guests in some cases.
93c4adc7
PB		 4241 */
4242 switch (msrs_to_save[i]) {
4243 case MSR_IA32_BNDCFGS:
4244 if (!kvm_x86_ops->mpx_supported())
4245 continue;
4246 break;
9dbe6cf9
PB		 4247 case MSR_TSC_AUX:
4248 if (!kvm_x86_ops->rdtscp_supported())
4249 continue;
4250 break;
93c4adc7
PB		 4251 default:
4252 break;
4253 }
4254
043405e1
CO		 4255 if (j < i)
4256 msrs_to_save[j] = msrs_to_save[i];
4257 j++;
4258 }
4259 num_msrs_to_save = j;
62ef68bb
PB		 4260
4261 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4262 switch (emulated_msrs[i]) {
6d396b55
PB		 4263 case MSR_IA32_SMBASE:
4264 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4265 continue;
4266 break;
62ef68bb
PB		 4267 default:
4268 break;
4269 }
4270
4271 if (j < i)
4272 emulated_msrs[j] = emulated_msrs[i];
4273 j++;
4274 }
4275 num_emulated_msrs = j;
043405e1
CO		 4276}
4277
bda9020e
MT		 4278static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4279 const void *v)
bbd9b64e 4280{
70252a10
AK		 4281 int handled = 0;
4282 int n;
4283
4284 do {
4285 n = min(len, 8);
bce87cce 4286 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4287 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4288 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4289 break;
4290 handled += n;
4291 addr += n;
4292 len -= n;
4293 v += n;
4294 } while (len);
bbd9b64e 4295
70252a10 4296 return handled;
bbd9b64e
CO		 4297}
4298
bda9020e 4299static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4300{
70252a10
AK		 4301 int handled = 0;
4302 int n;
4303
4304 do {
4305 n = min(len, 8);
bce87cce 4306 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4307 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4308 addr, n, v))
4309 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4310 break;
4311 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4312 handled += n;
4313 addr += n;
4314 len -= n;
4315 v += n;
4316 } while (len);
bbd9b64e 4317
70252a10 4318 return handled;
bbd9b64e
CO		 4319}
4320
2dafc6c2
GN		 4321static void kvm_set_segment(struct kvm_vcpu *vcpu,
4322 struct kvm_segment *var, int seg)
4323{
4324 kvm_x86_ops->set_segment(vcpu, var, seg);
4325}
4326
4327void kvm_get_segment(struct kvm_vcpu *vcpu,
4328 struct kvm_segment *var, int seg)
4329{
4330 kvm_x86_ops->get_segment(vcpu, var, seg);
4331}
4332
54987b7a
PB		 4333gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4334 struct x86_exception *exception)
02f59dc9
JR		 4335{
4336 gpa_t t_gpa;
02f59dc9
JR		 4337
4338 BUG_ON(!mmu_is_nested(vcpu));
4339
4340 /* NPT walks are always user-walks */
4341 access |= PFERR_USER_MASK;
54987b7a 4342 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4343
4344 return t_gpa;
4345}
4346
ab9ae313
AK		 4347gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4348 struct x86_exception *exception)
1871c602
GN		 4349{
4350 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4351 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4352}
4353
ab9ae313
AK		 4354 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4355 struct x86_exception *exception)
1871c602
GN		 4356{
4357 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4358 access |= PFERR_FETCH_MASK;
ab9ae313 4359 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4360}
4361
ab9ae313
AK		 4362gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4363 struct x86_exception *exception)
1871c602
GN		 4364{
4365 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4366 access |= PFERR_WRITE_MASK;
ab9ae313 4367 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4368}
4369
4370/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4371gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4372 struct x86_exception *exception)
1871c602 4373{
ab9ae313 4374 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4375}
4376
4377static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4378 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4379 struct x86_exception *exception)
bbd9b64e
CO		 4380{
4381 void *data = val;
10589a46 4382 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4383
4384 while (bytes) {
14dfe855 4385 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4386 exception);
bbd9b64e 4387 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4388 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4389 int ret;
4390
bcc55cba 4391 if (gpa == UNMAPPED_GVA)
ab9ae313 4392 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4393 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4394 offset, toread);
10589a46 4395 if (ret < 0) {
c3cd7ffa 4396 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4397 goto out;
4398 }
bbd9b64e 4399
77c2002e
IE		 4400 bytes -= toread;
4401 data += toread;
4402 addr += toread;
bbd9b64e 4403 }
10589a46 4404out:
10589a46 4405 return r;
bbd9b64e 4406}
77c2002e 4407
1871c602 4408/* used for instruction fetching */
0f65dd70
AK		 4409static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4410 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4411 struct x86_exception *exception)
1871c602 4412{
0f65dd70 4413 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4414 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4415 unsigned offset;
4416 int ret;
0f65dd70 4417
44583cba
PB		 4418 /* Inline kvm_read_guest_virt_helper for speed. */
4419 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4420 exception);
4421 if (unlikely(gpa == UNMAPPED_GVA))
4422 return X86EMUL_PROPAGATE_FAULT;
4423
4424 offset = addr & (PAGE_SIZE-1);
4425 if (WARN_ON(offset + bytes > PAGE_SIZE))
4426 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4427 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4428 offset, bytes);
44583cba
PB		 4429 if (unlikely(ret < 0))
4430 return X86EMUL_IO_NEEDED;
4431
4432 return X86EMUL_CONTINUE;
1871c602
GN		 4433}
4434
064aea77 4435int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4436 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4437 struct x86_exception *exception)
1871c602 4438{
0f65dd70 4439 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4440 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4441
1871c602 4442 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4443 exception);
1871c602 4444}
064aea77 4445EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4446
0f65dd70
AK		 4447static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4448 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4449 struct x86_exception *exception)
1871c602 4450{
0f65dd70 4451 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4452 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4453}
4454
7a036a6f
RK		 4455static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4456 unsigned long addr, void *val, unsigned int bytes)
4457{
4458 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4459 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4460
4461 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4462}
4463
6a4d7550 4464int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4465 gva_t addr, void *val,
2dafc6c2 4466 unsigned int bytes,
bcc55cba 4467 struct x86_exception *exception)
77c2002e 4468{
0f65dd70 4469 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4470 void *data = val;
4471 int r = X86EMUL_CONTINUE;
4472
4473 while (bytes) {
14dfe855
JR		 4474 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4475 PFERR_WRITE_MASK,
ab9ae313 4476 exception);
77c2002e
IE		 4477 unsigned offset = addr & (PAGE_SIZE-1);
4478 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4479 int ret;
4480
bcc55cba 4481 if (gpa == UNMAPPED_GVA)
ab9ae313 4482 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4483 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4484 if (ret < 0) {
c3cd7ffa 4485 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4486 goto out;
4487 }
4488
4489 bytes -= towrite;
4490 data += towrite;
4491 addr += towrite;
4492 }
4493out:
4494 return r;
4495}
6a4d7550 4496EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4497
0f89b207
TL		 4498static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4499 gpa_t gpa, bool write)
4500{
4501 /* For APIC access vmexit */
4502 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4503 return 1;
4504
4505 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4506 trace_vcpu_match_mmio(gva, gpa, write, true);
4507 return 1;
4508 }
4509
4510 return 0;
4511}
4512
af7cc7d1
XG		 4513static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4514 gpa_t *gpa, struct x86_exception *exception,
4515 bool write)
4516{
97d64b78
AK		 4517 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4518 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4519
be94f6b7
HH		 4520 /*
4521 * currently PKRU is only applied to ept enabled guest so
4522 * there is no pkey in EPT page table for L1 guest or EPT
4523 * shadow page table for L2 guest.
4524 */
97d64b78 4525 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4526 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4527 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4528 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4529 (gva & (PAGE_SIZE - 1));
4f022648 4530 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4531 return 1;
4532 }
4533
af7cc7d1
XG		 4534 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4535
4536 if (*gpa == UNMAPPED_GVA)
4537 return -1;
4538
0f89b207 4539 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4540}
4541
3200f405 4542int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4543 const void *val, int bytes)
bbd9b64e
CO		 4544{
4545 int ret;
4546
54bf36aa 4547 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4548 if (ret < 0)
bbd9b64e 4549 return 0;
0eb05bf2 4550 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4551 return 1;
4552}
4553
77d197b2
XG		 4554struct read_write_emulator_ops {
4555 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4556 int bytes);
4557 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4558 void *val, int bytes);
4559 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4560 int bytes, void *val);
4561 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4562 void *val, int bytes);
4563 bool write;
4564};
4565
4566static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4567{
4568 if (vcpu->mmio_read_completed) {
77d197b2 4569 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4570 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4571 vcpu->mmio_read_completed = 0;
4572 return 1;
4573 }
4574
4575 return 0;
4576}
4577
4578static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4579 void *val, int bytes)
4580{
54bf36aa 4581 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4582}
4583
4584static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4585 void *val, int bytes)
4586{
4587 return emulator_write_phys(vcpu, gpa, val, bytes);
4588}
4589
4590static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4591{
4592 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4593 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4594}
4595
4596static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4597 void *val, int bytes)
4598{
4599 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4600 return X86EMUL_IO_NEEDED;
4601}
4602
4603static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4604 void *val, int bytes)
4605{
f78146b0
AK		 4606 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4607
87da7e66 4608 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4609 return X86EMUL_CONTINUE;
4610}
4611
0fbe9b0b 4612static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4613 .read_write_prepare = read_prepare,
4614 .read_write_emulate = read_emulate,
4615 .read_write_mmio = vcpu_mmio_read,
4616 .read_write_exit_mmio = read_exit_mmio,
4617};
4618
0fbe9b0b 4619static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4620 .read_write_emulate = write_emulate,
4621 .read_write_mmio = write_mmio,
4622 .read_write_exit_mmio = write_exit_mmio,
4623 .write = true,
4624};
4625
22388a3c
XG		 4626static int emulator_read_write_onepage(unsigned long addr, void *val,
4627 unsigned int bytes,
4628 struct x86_exception *exception,
4629 struct kvm_vcpu *vcpu,
0fbe9b0b 4630 const struct read_write_emulator_ops *ops)
bbd9b64e 4631{
af7cc7d1
XG		 4632 gpa_t gpa;
4633 int handled, ret;
22388a3c 4634 bool write = ops->write;
f78146b0 4635 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4636 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4637
4638 /*
4639 * If the exit was due to a NPF we may already have a GPA.
4640 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4641 * Note, this cannot be used on string operations since string
4642 * operation using rep will only have the initial GPA from the NPF
4643 * occurred.
4644 */
4645 if (vcpu->arch.gpa_available &&
4646 emulator_can_use_gpa(ctxt) &&
4647 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4648 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4649 gpa = exception->address;
4650 goto mmio;
4651 }
10589a46 4652
22388a3c 4653 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4654
af7cc7d1 4655 if (ret < 0)
bbd9b64e 4656 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4657
4658 /* For APIC access vmexit */
af7cc7d1 4659 if (ret)
bbd9b64e
CO		 4660 goto mmio;
4661
22388a3c 4662 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4663 return X86EMUL_CONTINUE;
4664
4665mmio:
4666 /*
4667 * Is this MMIO handled locally?
4668 */
22388a3c 4669 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4670 if (handled == bytes)
bbd9b64e 4671 return X86EMUL_CONTINUE;
bbd9b64e 4672
70252a10
AK		 4673 gpa += handled;
4674 bytes -= handled;
4675 val += handled;
4676
87da7e66
XG		 4677 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4678 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4679 frag->gpa = gpa;
4680 frag->data = val;
4681 frag->len = bytes;
f78146b0 4682 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4683}
4684
52eb5a6d
XL		 4685static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4686 unsigned long addr,
22388a3c
XG		 4687 void *val, unsigned int bytes,
4688 struct x86_exception *exception,
0fbe9b0b 4689 const struct read_write_emulator_ops *ops)
bbd9b64e 4690{
0f65dd70 4691 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4692 gpa_t gpa;
4693 int rc;
4694
4695 if (ops->read_write_prepare &&
4696 ops->read_write_prepare(vcpu, val, bytes))
4697 return X86EMUL_CONTINUE;
4698
4699 vcpu->mmio_nr_fragments = 0;
0f65dd70 4700
bbd9b64e
CO		 4701 /* Crossing a page boundary? */
4702 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4703 int now;
bbd9b64e
CO		 4704
4705 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4706 rc = emulator_read_write_onepage(addr, val, now, exception,
4707 vcpu, ops);
4708
bbd9b64e
CO		 4709 if (rc != X86EMUL_CONTINUE)
4710 return rc;
4711 addr += now;
bac15531
NA		 4712 if (ctxt->mode != X86EMUL_MODE_PROT64)
4713 addr = (u32)addr;
bbd9b64e
CO		 4714 val += now;
4715 bytes -= now;
4716 }
22388a3c 4717
f78146b0
AK		 4718 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4719 vcpu, ops);
4720 if (rc != X86EMUL_CONTINUE)
4721 return rc;
4722
4723 if (!vcpu->mmio_nr_fragments)
4724 return rc;
4725
4726 gpa = vcpu->mmio_fragments[0].gpa;
4727
4728 vcpu->mmio_needed = 1;
4729 vcpu->mmio_cur_fragment = 0;
4730
87da7e66 4731 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4732 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4733 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4734 vcpu->run->mmio.phys_addr = gpa;
4735
4736 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4737}
4738
4739static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4740 unsigned long addr,
4741 void *val,
4742 unsigned int bytes,
4743 struct x86_exception *exception)
4744{
4745 return emulator_read_write(ctxt, addr, val, bytes,
4746 exception, &read_emultor);
4747}
4748
52eb5a6d 4749static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4750 unsigned long addr,
4751 const void *val,
4752 unsigned int bytes,
4753 struct x86_exception *exception)
4754{
4755 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4756 exception, &write_emultor);
bbd9b64e 4757}
bbd9b64e 4758
daea3e73
AK		 4759#define CMPXCHG_TYPE(t, ptr, old, new) \
4760 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4761
4762#ifdef CONFIG_X86_64
4763# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4764#else
4765# define CMPXCHG64(ptr, old, new) \
9749a6c0 4766 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4767#endif
4768
0f65dd70
AK		 4769static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4770 unsigned long addr,
bbd9b64e
CO		 4771 const void *old,
4772 const void *new,
4773 unsigned int bytes,
0f65dd70 4774 struct x86_exception *exception)
bbd9b64e 4775{
0f65dd70 4776 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4777 gpa_t gpa;
4778 struct page *page;
4779 char *kaddr;
4780 bool exchanged;
2bacc55c 4781
daea3e73
AK		 4782 /* guests cmpxchg8b have to be emulated atomically */
4783 if (bytes > 8 || (bytes & (bytes - 1)))
4784 goto emul_write;
10589a46 4785
daea3e73 4786 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4787
daea3e73
AK		 4788 if (gpa == UNMAPPED_GVA ||
4789 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4790 goto emul_write;
2bacc55c 4791
daea3e73
AK		 4792 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4793 goto emul_write;
72dc67a6 4794
54bf36aa 4795 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4796 if (is_error_page(page))
c19b8bd6 4797 goto emul_write;
72dc67a6 4798
8fd75e12 4799 kaddr = kmap_atomic(page);
daea3e73
AK		 4800 kaddr += offset_in_page(gpa);
4801 switch (bytes) {
4802 case 1:
4803 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4804 break;
4805 case 2:
4806 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4807 break;
4808 case 4:
4809 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4810 break;
4811 case 8:
4812 exchanged = CMPXCHG64(kaddr, old, new);
4813 break;
4814 default:
4815 BUG();
2bacc55c 4816 }
8fd75e12 4817 kunmap_atomic(kaddr);
daea3e73
AK		 4818 kvm_release_page_dirty(page);
4819
4820 if (!exchanged)
4821 return X86EMUL_CMPXCHG_FAILED;
4822
54bf36aa 4823 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4824 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4825
4826 return X86EMUL_CONTINUE;
4a5f48f6 4827
3200f405 4828emul_write:
daea3e73 4829 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4830
0f65dd70 4831 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4832}
4833
cf8f70bf
GN		 4834static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4835{
4836 /* TODO: String I/O for in kernel device */
4837 int r;
4838
4839 if (vcpu->arch.pio.in)
e32edf4f 4840 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4841 vcpu->arch.pio.size, pd);
4842 else
e32edf4f 4843 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4844 vcpu->arch.pio.port, vcpu->arch.pio.size,
4845 pd);
4846 return r;
4847}
4848
6f6fbe98
XG		 4849static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4850 unsigned short port, void *val,
4851 unsigned int count, bool in)
cf8f70bf 4852{
cf8f70bf 4853 vcpu->arch.pio.port = port;
6f6fbe98 4854 vcpu->arch.pio.in = in;
7972995b 4855 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4856 vcpu->arch.pio.size = size;
4857
4858 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4859 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4860 return 1;
4861 }
4862
4863 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4864 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4865 vcpu->run->io.size = size;
4866 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4867 vcpu->run->io.count = count;
4868 vcpu->run->io.port = port;
4869
4870 return 0;
4871}
4872
6f6fbe98
XG		 4873static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4874 int size, unsigned short port, void *val,
4875 unsigned int count)
cf8f70bf 4876{
ca1d4a9e 4877 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4878 int ret;
ca1d4a9e 4879
6f6fbe98
XG		 4880 if (vcpu->arch.pio.count)
4881 goto data_avail;
cf8f70bf 4882
6f6fbe98
XG		 4883 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4884 if (ret) {
4885data_avail:
4886 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4887 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4888 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4889 return 1;
4890 }
4891
cf8f70bf
GN		 4892 return 0;
4893}
4894
6f6fbe98
XG		 4895static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4896 int size, unsigned short port,
4897 const void *val, unsigned int count)
4898{
4899 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4900
4901 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4902 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4903 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4904}
4905
bbd9b64e
CO		 4906static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4907{
4908 return kvm_x86_ops->get_segment_base(vcpu, seg);
4909}
4910
3cb16fe7 4911static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4912{
3cb16fe7 4913 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4914}
4915
ae6a2375 4916static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4917{
4918 if (!need_emulate_wbinvd(vcpu))
4919 return X86EMUL_CONTINUE;
4920
4921 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4922 int cpu = get_cpu();
4923
4924 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4925 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4926 wbinvd_ipi, NULL, 1);
2eec7343 4927 put_cpu();
f5f48ee1 4928 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4929 } else
4930 wbinvd();
f5f48ee1
SY		 4931 return X86EMUL_CONTINUE;
4932}
5cb56059
JS		 4933
4934int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4935{
6affcbed
KH		 4936 kvm_emulate_wbinvd_noskip(vcpu);
4937 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4938}
f5f48ee1
SY		 4939EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4940
5cb56059
JS		 4941
4942
bcaf5cc5
AK		 4943static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4944{
5cb56059 4945 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4946}
4947
52eb5a6d
XL		 4948static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4949 unsigned long *dest)
bbd9b64e 4950{
16f8a6f9 4951 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4952}
4953
52eb5a6d
XL		 4954static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4955 unsigned long value)
bbd9b64e 4956{
338dbc97 4957
717746e3 4958 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4959}
4960
52a46617 4961static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4962{
52a46617 4963 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4964}
4965
717746e3 4966static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4967{
717746e3 4968 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4969 unsigned long value;
4970
4971 switch (cr) {
4972 case 0:
4973 value = kvm_read_cr0(vcpu);
4974 break;
4975 case 2:
4976 value = vcpu->arch.cr2;
4977 break;
4978 case 3:
9f8fe504 4979 value = kvm_read_cr3(vcpu);
52a46617
GN		 4980 break;
4981 case 4:
4982 value = kvm_read_cr4(vcpu);
4983 break;
4984 case 8:
4985 value = kvm_get_cr8(vcpu);
4986 break;
4987 default:
a737f256 4988 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4989 return 0;
4990 }
4991
4992 return value;
4993}
4994
717746e3 4995static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4996{
717746e3 4997 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4998 int res = 0;
4999
52a46617
GN		 5000 switch (cr) {
5001 case 0:
49a9b07e 5002 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5003 break;
5004 case 2:
5005 vcpu->arch.cr2 = val;
5006 break;
5007 case 3:
2390218b 5008 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5009 break;
5010 case 4:
a83b29c6 5011 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5012 break;
5013 case 8:
eea1cff9 5014 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5015 break;
5016 default:
a737f256 5017 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5018 res = -1;
52a46617 5019 }
0f12244f
GN		 5020
5021 return res;
52a46617
GN		 5022}
5023
717746e3 5024static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5025{
717746e3 5026 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5027}
5028
4bff1e86 5029static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5030{
4bff1e86 5031 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5032}
5033
4bff1e86 5034static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5035{
4bff1e86 5036 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5037}
5038
1ac9d0cf
AK		 5039static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5040{
5041 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5042}
5043
5044static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5045{
5046 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5047}
5048
4bff1e86
AK		 5049static unsigned long emulator_get_cached_segment_base(
5050 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5051{
4bff1e86 5052 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5053}
5054
1aa36616
AK		 5055static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5056 struct desc_struct *desc, u32 *base3,
5057 int seg)
2dafc6c2
GN		 5058{
5059 struct kvm_segment var;
5060
4bff1e86 5061 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5062 *selector = var.selector;
2dafc6c2 5063
378a8b09
GN		 5064 if (var.unusable) {
5065 memset(desc, 0, sizeof(*desc));
2dafc6c2 5066 return false;
378a8b09 5067 }
2dafc6c2
GN		 5068
5069 if (var.g)
5070 var.limit >>= 12;
5071 set_desc_limit(desc, var.limit);
5072 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5073#ifdef CONFIG_X86_64
5074 if (base3)
5075 *base3 = var.base >> 32;
5076#endif
2dafc6c2
GN		 5077 desc->type = var.type;
5078 desc->s = var.s;
5079 desc->dpl = var.dpl;
5080 desc->p = var.present;
5081 desc->avl = var.avl;
5082 desc->l = var.l;
5083 desc->d = var.db;
5084 desc->g = var.g;
5085
5086 return true;
5087}
5088
1aa36616
AK		 5089static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5090 struct desc_struct *desc, u32 base3,
5091 int seg)
2dafc6c2 5092{
4bff1e86 5093 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5094 struct kvm_segment var;
5095
1aa36616 5096 var.selector = selector;
2dafc6c2 5097 var.base = get_desc_base(desc);
5601d05b
GN		 5098#ifdef CONFIG_X86_64
5099 var.base |= ((u64)base3) << 32;
5100#endif
2dafc6c2
GN		 5101 var.limit = get_desc_limit(desc);
5102 if (desc->g)
5103 var.limit = (var.limit << 12) | 0xfff;
5104 var.type = desc->type;
2dafc6c2
GN		 5105 var.dpl = desc->dpl;
5106 var.db = desc->d;
5107 var.s = desc->s;
5108 var.l = desc->l;
5109 var.g = desc->g;
5110 var.avl = desc->avl;
5111 var.present = desc->p;
5112 var.unusable = !var.present;
5113 var.padding = 0;
5114
5115 kvm_set_segment(vcpu, &var, seg);
5116 return;
5117}
5118
717746e3
AK		 5119static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5120 u32 msr_index, u64 *pdata)
5121{
609e36d3
PB		 5122 struct msr_data msr;
5123 int r;
5124
5125 msr.index = msr_index;
5126 msr.host_initiated = false;
5127 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5128 if (r)
5129 return r;
5130
5131 *pdata = msr.data;
5132 return 0;
717746e3
AK		 5133}
5134
5135static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5136 u32 msr_index, u64 data)
5137{
8fe8ab46
WA		 5138 struct msr_data msr;
5139
5140 msr.data = data;
5141 msr.index = msr_index;
5142 msr.host_initiated = false;
5143 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5144}
5145
64d60670
PB		 5146static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5147{
5148 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5149
5150 return vcpu->arch.smbase;
5151}
5152
5153static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5154{
5155 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5156
5157 vcpu->arch.smbase = smbase;
5158}
5159
67f4d428
NA		 5160static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5161 u32 pmc)
5162{
c6702c9d 5163 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5164}
5165
222d21aa
AK		 5166static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5167 u32 pmc, u64 *pdata)
5168{
c6702c9d 5169 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5170}
5171
6c3287f7
AK		 5172static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5173{
5174 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5175}
5176
5037f6f3
AK		 5177static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5178{
5179 preempt_disable();
5197b808 5180 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5181}
5182
5183static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5184{
5185 preempt_enable();
5186}
5187
2953538e 5188static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5189 struct x86_instruction_info *info,
c4f035c6
AK		 5190 enum x86_intercept_stage stage)
5191{
2953538e 5192 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5193}
5194
0017f93a 5195static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5196 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5197{
0017f93a 5198 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5199}
5200
dd856efa
AK		 5201static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5202{
5203 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5204}
5205
5206static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5207{
5208 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5209}
5210
801806d9
NA		 5211static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5212{
5213 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5214}
5215
0225fb50 5216static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5217 .read_gpr = emulator_read_gpr,
5218 .write_gpr = emulator_write_gpr,
1871c602 5219 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5220 .write_std = kvm_write_guest_virt_system,
7a036a6f 5221 .read_phys = kvm_read_guest_phys_system,
1871c602 5222 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5223 .read_emulated = emulator_read_emulated,
5224 .write_emulated = emulator_write_emulated,
5225 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5226 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5227 .pio_in_emulated = emulator_pio_in_emulated,
5228 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5229 .get_segment = emulator_get_segment,
5230 .set_segment = emulator_set_segment,
5951c442 5231 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5232 .get_gdt = emulator_get_gdt,
160ce1f1 5233 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5234 .set_gdt = emulator_set_gdt,
5235 .set_idt = emulator_set_idt,
52a46617
GN		 5236 .get_cr = emulator_get_cr,
5237 .set_cr = emulator_set_cr,
9c537244 5238 .cpl = emulator_get_cpl,
35aa5375
GN		 5239 .get_dr = emulator_get_dr,
5240 .set_dr = emulator_set_dr,
64d60670
PB		 5241 .get_smbase = emulator_get_smbase,
5242 .set_smbase = emulator_set_smbase,
717746e3
AK		 5243 .set_msr = emulator_set_msr,
5244 .get_msr = emulator_get_msr,
67f4d428 5245 .check_pmc = emulator_check_pmc,
222d21aa 5246 .read_pmc = emulator_read_pmc,
6c3287f7 5247 .halt = emulator_halt,
bcaf5cc5 5248 .wbinvd = emulator_wbinvd,
d6aa1000 5249 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5250 .get_fpu = emulator_get_fpu,
5251 .put_fpu = emulator_put_fpu,
c4f035c6 5252 .intercept = emulator_intercept,
bdb42f5a 5253 .get_cpuid = emulator_get_cpuid,
801806d9 5254 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5255};
5256
95cb2295
GN		 5257static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5258{
37ccdcbe 5259 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5260 /*
5261 * an sti; sti; sequence only disable interrupts for the first
5262 * instruction. So, if the last instruction, be it emulated or
5263 * not, left the system with the INT_STI flag enabled, it
5264 * means that the last instruction is an sti. We should not
5265 * leave the flag on in this case. The same goes for mov ss
5266 */
37ccdcbe
PB		 5267 if (int_shadow & mask)
5268 mask = 0;
6addfc42 5269 if (unlikely(int_shadow || mask)) {
95cb2295 5270 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5271 if (!mask)
5272 kvm_make_request(KVM_REQ_EVENT, vcpu);
5273 }
95cb2295
GN		 5274}
5275
ef54bcfe 5276static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5277{
5278 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5279 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5280 return kvm_propagate_fault(vcpu, &ctxt->exception);
5281
5282 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5283 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5284 ctxt->exception.error_code);
54b8486f 5285 else
da9cb575 5286 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5287 return false;
54b8486f
GN		 5288}
5289
8ec4722d
MG		 5290static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5291{
adf52235 5292 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5293 int cs_db, cs_l;
5294
8ec4722d
MG		 5295 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5296
adf52235
TY		 5297 ctxt->eflags = kvm_get_rflags(vcpu);
5298 ctxt->eip = kvm_rip_read(vcpu);
5299 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5300 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5301 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5302 cs_db ? X86EMUL_MODE_PROT32 :
5303 X86EMUL_MODE_PROT16;
a584539b 5304 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5305 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5306 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5307 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5308
dd856efa 5309 init_decode_cache(ctxt);
7ae441ea 5310 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5311}
5312
71f9833b 5313int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5314{
9d74191a 5315 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5316 int ret;
5317
5318 init_emulate_ctxt(vcpu);
5319
9dac77fa
AK		 5320 ctxt->op_bytes = 2;
5321 ctxt->ad_bytes = 2;
5322 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5323 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5324
5325 if (ret != X86EMUL_CONTINUE)
5326 return EMULATE_FAIL;
5327
9dac77fa 5328 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5329 kvm_rip_write(vcpu, ctxt->eip);
5330 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5331
5332 if (irq == NMI_VECTOR)
7460fb4a 5333 vcpu->arch.nmi_pending = 0;
63995653
MG		 5334 else
5335 vcpu->arch.interrupt.pending = false;
5336
5337 return EMULATE_DONE;
5338}
5339EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5340
6d77dbfc
GN		 5341static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5342{
fc3a9157
JR		 5343 int r = EMULATE_DONE;
5344
6d77dbfc
GN		 5345 ++vcpu->stat.insn_emulation_fail;
5346 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5347 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5348 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5349 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5350 vcpu->run->internal.ndata = 0;
5351 r = EMULATE_FAIL;
5352 }
6d77dbfc 5353 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5354
5355 return r;
6d77dbfc
GN		 5356}
5357
93c05d3e 5358static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5359 bool write_fault_to_shadow_pgtable,
5360 int emulation_type)
a6f177ef 5361{
95b3cf69 5362 gpa_t gpa = cr2;
ba049e93 5363 kvm_pfn_t pfn;
a6f177ef 5364
991eebf9
GN		 5365 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5366 return false;
5367
95b3cf69
XG		 5368 if (!vcpu->arch.mmu.direct_map) {
5369 /*
5370 * Write permission should be allowed since only
5371 * write access need to be emulated.
5372 */
5373 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5374
95b3cf69
XG		 5375 /*
5376 * If the mapping is invalid in guest, let cpu retry
5377 * it to generate fault.
5378 */
5379 if (gpa == UNMAPPED_GVA)
5380 return true;
5381 }
a6f177ef 5382
8e3d9d06
XG		 5383 /*
5384 * Do not retry the unhandleable instruction if it faults on the
5385 * readonly host memory, otherwise it will goto a infinite loop:
5386 * retry instruction -> write #PF -> emulation fail -> retry
5387 * instruction -> ...
5388 */
5389 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5390
5391 /*
5392 * If the instruction failed on the error pfn, it can not be fixed,
5393 * report the error to userspace.
5394 */
5395 if (is_error_noslot_pfn(pfn))
5396 return false;
5397
5398 kvm_release_pfn_clean(pfn);
5399
5400 /* The instructions are well-emulated on direct mmu. */
5401 if (vcpu->arch.mmu.direct_map) {
5402 unsigned int indirect_shadow_pages;
5403
5404 spin_lock(&vcpu->kvm->mmu_lock);
5405 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5406 spin_unlock(&vcpu->kvm->mmu_lock);
5407
5408 if (indirect_shadow_pages)
5409 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5410
a6f177ef 5411 return true;
8e3d9d06 5412 }
a6f177ef 5413
95b3cf69
XG		 5414 /*
5415 * if emulation was due to access to shadowed page table
5416 * and it failed try to unshadow page and re-enter the
5417 * guest to let CPU execute the instruction.
5418 */
5419 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5420
5421 /*
5422 * If the access faults on its page table, it can not
5423 * be fixed by unprotecting shadow page and it should
5424 * be reported to userspace.
5425 */
5426 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5427}
5428
1cb3f3ae
XG		 5429static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5430 unsigned long cr2, int emulation_type)
5431{
5432 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5433 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5434
5435 last_retry_eip = vcpu->arch.last_retry_eip;
5436 last_retry_addr = vcpu->arch.last_retry_addr;
5437
5438 /*
5439 * If the emulation is caused by #PF and it is non-page_table
5440 * writing instruction, it means the VM-EXIT is caused by shadow
5441 * page protected, we can zap the shadow page and retry this
5442 * instruction directly.
5443 *
5444 * Note: if the guest uses a non-page-table modifying instruction
5445 * on the PDE that points to the instruction, then we will unmap
5446 * the instruction and go to an infinite loop. So, we cache the
5447 * last retried eip and the last fault address, if we meet the eip
5448 * and the address again, we can break out of the potential infinite
5449 * loop.
5450 */
5451 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5452
5453 if (!(emulation_type & EMULTYPE_RETRY))
5454 return false;
5455
5456 if (x86_page_table_writing_insn(ctxt))
5457 return false;
5458
5459 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5460 return false;
5461
5462 vcpu->arch.last_retry_eip = ctxt->eip;
5463 vcpu->arch.last_retry_addr = cr2;
5464
5465 if (!vcpu->arch.mmu.direct_map)
5466 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5467
22368028 5468 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5469
5470 return true;
5471}
5472
716d51ab
GN		 5473static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5474static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5475
64d60670 5476static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5477{
64d60670 5478 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5479 /* This is a good place to trace that we are exiting SMM. */
5480 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5481
c43203ca
PB		 5482 /* Process a latched INIT or SMI, if any. */
5483 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5484 }
699023e2
PB		 5485
5486 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5487}
5488
5489static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5490{
5491 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5492
a584539b 5493 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5494
5495 if (changed & HF_SMM_MASK)
5496 kvm_smm_changed(vcpu);
a584539b
PB		 5497}
5498
4a1e10d5
PB		 5499static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5500 unsigned long *db)
5501{
5502 u32 dr6 = 0;
5503 int i;
5504 u32 enable, rwlen;
5505
5506 enable = dr7;
5507 rwlen = dr7 >> 16;
5508 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5509 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5510 dr6 |= (1 << i);
5511 return dr6;
5512}
5513
6addfc42 5514static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5515{
5516 struct kvm_run *kvm_run = vcpu->run;
5517
5518 /*
6addfc42
PB		 5519 * rflags is the old, "raw" value of the flags. The new value has
5520 * not been saved yet.
663f4c61
PB		 5521 *
5522 * This is correct even for TF set by the guest, because "the
5523 * processor will not generate this exception after the instruction
5524 * that sets the TF flag".
5525 */
663f4c61
PB		 5526 if (unlikely(rflags & X86_EFLAGS_TF)) {
5527 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5528 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5529 DR6_RTM;
663f4c61
PB		 5530 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5531 kvm_run->debug.arch.exception = DB_VECTOR;
5532 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5533 *r = EMULATE_USER_EXIT;
5534 } else {
663f4c61
PB		 5535 /*
5536 * "Certain debug exceptions may clear bit 0-3. The
5537 * remaining contents of the DR6 register are never
5538 * cleared by the processor".
5539 */
5540 vcpu->arch.dr6 &= ~15;
6f43ed01 5541 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5542 kvm_queue_exception(vcpu, DB_VECTOR);
5543 }
5544 }
5545}
5546
6affcbed
KH		 5547int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5548{
5549 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5550 int r = EMULATE_DONE;
5551
5552 kvm_x86_ops->skip_emulated_instruction(vcpu);
5553 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5554 return r == EMULATE_DONE;
5555}
5556EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5557
4a1e10d5
PB		 5558static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5559{
4a1e10d5
PB		 5560 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5561 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5562 struct kvm_run *kvm_run = vcpu->run;
5563 unsigned long eip = kvm_get_linear_rip(vcpu);
5564 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5565 vcpu->arch.guest_debug_dr7,
5566 vcpu->arch.eff_db);
5567
5568 if (dr6 != 0) {
6f43ed01 5569 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5570 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5571 kvm_run->debug.arch.exception = DB_VECTOR;
5572 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5573 *r = EMULATE_USER_EXIT;
5574 return true;
5575 }
5576 }
5577
4161a569
NA		 5578 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5579 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5580 unsigned long eip = kvm_get_linear_rip(vcpu);
5581 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5582 vcpu->arch.dr7,
5583 vcpu->arch.db);
5584
5585 if (dr6 != 0) {
5586 vcpu->arch.dr6 &= ~15;
6f43ed01 5587 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5588 kvm_queue_exception(vcpu, DB_VECTOR);
5589 *r = EMULATE_DONE;
5590 return true;
5591 }
5592 }
5593
5594 return false;
5595}
5596
51d8b661
AP		 5597int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5598 unsigned long cr2,
dc25e89e
AP		 5599 int emulation_type,
5600 void *insn,
5601 int insn_len)
bbd9b64e 5602{
95cb2295 5603 int r;
9d74191a 5604 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5605 bool writeback = true;
93c05d3e 5606 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5607
93c05d3e
XG		 5608 /*
5609 * Clear write_fault_to_shadow_pgtable here to ensure it is
5610 * never reused.
5611 */
5612 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5613 kvm_clear_exception_queue(vcpu);
8d7d8102 5614
571008da 5615 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5616 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5617
5618 /*
5619 * We will reenter on the same instruction since
5620 * we do not set complete_userspace_io. This does not
5621 * handle watchpoints yet, those would be handled in
5622 * the emulate_ops.
5623 */
5624 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5625 return r;
5626
9d74191a
TY		 5627 ctxt->interruptibility = 0;
5628 ctxt->have_exception = false;
e0ad0b47 5629 ctxt->exception.vector = -1;
9d74191a 5630 ctxt->perm_ok = false;
bbd9b64e 5631
b51e974f 5632 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5633
9d74191a 5634 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5635
e46479f8 5636 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5637 ++vcpu->stat.insn_emulation;
1d2887e2 5638 if (r != EMULATION_OK) {
4005996e
AK		 5639 if (emulation_type & EMULTYPE_TRAP_UD)
5640 return EMULATE_FAIL;
991eebf9
GN		 5641 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5642 emulation_type))
bbd9b64e 5643 return EMULATE_DONE;
6d77dbfc
GN		 5644 if (emulation_type & EMULTYPE_SKIP)
5645 return EMULATE_FAIL;
5646 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5647 }
5648 }
5649
ba8afb6b 5650 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5651 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5652 if (ctxt->eflags & X86_EFLAGS_RF)
5653 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5654 return EMULATE_DONE;
5655 }
5656
1cb3f3ae
XG		 5657 if (retry_instruction(ctxt, cr2, emulation_type))
5658 return EMULATE_DONE;
5659
7ae441ea 5660 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5661 changes registers values during IO operation */
7ae441ea
GN		 5662 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5663 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5664 emulator_invalidate_register_cache(ctxt);
7ae441ea 5665 }
4d2179e1 5666
5cd21917 5667restart:
0f89b207
TL		 5668 /* Save the faulting GPA (cr2) in the address field */
5669 ctxt->exception.address = cr2;
5670
9d74191a 5671 r = x86_emulate_insn(ctxt);
bbd9b64e 5672
775fde86
JR		 5673 if (r == EMULATION_INTERCEPTED)
5674 return EMULATE_DONE;
5675
d2ddd1c4 5676 if (r == EMULATION_FAILED) {
991eebf9
GN		 5677 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5678 emulation_type))
c3cd7ffa
GN		 5679 return EMULATE_DONE;
5680
6d77dbfc 5681 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5682 }
5683
9d74191a 5684 if (ctxt->have_exception) {
d2ddd1c4 5685 r = EMULATE_DONE;
ef54bcfe
PB		 5686 if (inject_emulated_exception(vcpu))
5687 return r;
d2ddd1c4 5688 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5689 if (!vcpu->arch.pio.in) {
5690 /* FIXME: return into emulator if single-stepping. */
3457e419 5691 vcpu->arch.pio.count = 0;
0912c977 5692 } else {
7ae441ea 5693 writeback = false;
716d51ab
GN		 5694 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5695 }
ac0a48c3 5696 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5697 } else if (vcpu->mmio_needed) {
5698 if (!vcpu->mmio_is_write)
5699 writeback = false;
ac0a48c3 5700 r = EMULATE_USER_EXIT;
716d51ab 5701 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5702 } else if (r == EMULATION_RESTART)
5cd21917 5703 goto restart;
d2ddd1c4
GN		 5704 else
5705 r = EMULATE_DONE;
f850e2e6 5706
7ae441ea 5707 if (writeback) {
6addfc42 5708 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5709 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5710 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5711 if (vcpu->arch.hflags != ctxt->emul_flags)
5712 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5713 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5714 if (r == EMULATE_DONE)
6addfc42 5715 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5716 if (!ctxt->have_exception ||
5717 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5718 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5719
5720 /*
5721 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5722 * do nothing, and it will be requested again as soon as
5723 * the shadow expires. But we still need to check here,
5724 * because POPF has no interrupt shadow.
5725 */
5726 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5727 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5728 } else
5729 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5730
5731 return r;
de7d789a 5732}
51d8b661 5733EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5734
cf8f70bf 5735int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5736{
cf8f70bf 5737 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5738 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5739 size, port, &val, 1);
cf8f70bf 5740 /* do not return to emulator after return from userspace */
7972995b 5741 vcpu->arch.pio.count = 0;
de7d789a
CO		 5742 return ret;
5743}
cf8f70bf 5744EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5745
8370c3d0
TL		 5746static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5747{
5748 unsigned long val;
5749
5750 /* We should only ever be called with arch.pio.count equal to 1 */
5751 BUG_ON(vcpu->arch.pio.count != 1);
5752
5753 /* For size less than 4 we merge, else we zero extend */
5754 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5755 : 0;
5756
5757 /*
5758 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5759 * the copy and tracing
5760 */
5761 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5762 vcpu->arch.pio.port, &val, 1);
5763 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5764
5765 return 1;
5766}
5767
5768int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5769{
5770 unsigned long val;
5771 int ret;
5772
5773 /* For size less than 4 we merge, else we zero extend */
5774 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5775
5776 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5777 &val, 1);
5778 if (ret) {
5779 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5780 return ret;
5781 }
5782
5783 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5784
5785 return 0;
5786}
5787EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5788
251a5fd6 5789static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5790{
0a3aee0d 5791 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5792 return 0;
8cfdc000
ZA		 5793}
5794
5795static void tsc_khz_changed(void *data)
c8076604 5796{
8cfdc000
ZA		 5797 struct cpufreq_freqs *freq = data;
5798 unsigned long khz = 0;
5799
5800 if (data)
5801 khz = freq->new;
5802 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5803 khz = cpufreq_quick_get(raw_smp_processor_id());
5804 if (!khz)
5805 khz = tsc_khz;
0a3aee0d 5806 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5807}
5808
c8076604
GH		 5809static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5810 void *data)
5811{
5812 struct cpufreq_freqs *freq = data;
5813 struct kvm *kvm;
5814 struct kvm_vcpu *vcpu;
5815 int i, send_ipi = 0;
5816
8cfdc000
ZA		 5817 /*
5818 * We allow guests to temporarily run on slowing clocks,
5819 * provided we notify them after, or to run on accelerating
5820 * clocks, provided we notify them before. Thus time never
5821 * goes backwards.
5822 *
5823 * However, we have a problem. We can't atomically update
5824 * the frequency of a given CPU from this function; it is
5825 * merely a notifier, which can be called from any CPU.
5826 * Changing the TSC frequency at arbitrary points in time
5827 * requires a recomputation of local variables related to
5828 * the TSC for each VCPU. We must flag these local variables
5829 * to be updated and be sure the update takes place with the
5830 * new frequency before any guests proceed.
5831 *
5832 * Unfortunately, the combination of hotplug CPU and frequency
5833 * change creates an intractable locking scenario; the order
5834 * of when these callouts happen is undefined with respect to
5835 * CPU hotplug, and they can race with each other. As such,
5836 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5837 * undefined; you can actually have a CPU frequency change take
5838 * place in between the computation of X and the setting of the
5839 * variable. To protect against this problem, all updates of
5840 * the per_cpu tsc_khz variable are done in an interrupt
5841 * protected IPI, and all callers wishing to update the value
5842 * must wait for a synchronous IPI to complete (which is trivial
5843 * if the caller is on the CPU already). This establishes the
5844 * necessary total order on variable updates.
5845 *
5846 * Note that because a guest time update may take place
5847 * anytime after the setting of the VCPU's request bit, the
5848 * correct TSC value must be set before the request. However,
5849 * to ensure the update actually makes it to any guest which
5850 * starts running in hardware virtualization between the set
5851 * and the acquisition of the spinlock, we must also ping the
5852 * CPU after setting the request bit.
5853 *
5854 */
5855
c8076604
GH		 5856 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5857 return 0;
5858 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5859 return 0;
8cfdc000
ZA		 5860
5861 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5862
2f303b74 5863 spin_lock(&kvm_lock);
c8076604 5864 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5865 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5866 if (vcpu->cpu != freq->cpu)
5867 continue;
c285545f 5868 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5869 if (vcpu->cpu != smp_processor_id())
8cfdc000 5870 send_ipi = 1;
c8076604
GH		 5871 }
5872 }
2f303b74 5873 spin_unlock(&kvm_lock);
c8076604
GH		 5874
5875 if (freq->old < freq->new && send_ipi) {
5876 /*
5877 * We upscale the frequency. Must make the guest
5878 * doesn't see old kvmclock values while running with
5879 * the new frequency, otherwise we risk the guest sees
5880 * time go backwards.
5881 *
5882 * In case we update the frequency for another cpu
5883 * (which might be in guest context) send an interrupt
5884 * to kick the cpu out of guest context. Next time
5885 * guest context is entered kvmclock will be updated,
5886 * so the guest will not see stale values.
5887 */
8cfdc000 5888 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5889 }
5890 return 0;
5891}
5892
5893static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5894 .notifier_call = kvmclock_cpufreq_notifier
5895};
5896
251a5fd6 5897static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5898{
251a5fd6
SAS		 5899 tsc_khz_changed(NULL);
5900 return 0;
8cfdc000
ZA		 5901}
5902
b820cc0c
ZA		 5903static void kvm_timer_init(void)
5904{
c285545f 5905 max_tsc_khz = tsc_khz;
460dd42e 5906
b820cc0c 5907 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5908#ifdef CONFIG_CPU_FREQ
5909 struct cpufreq_policy policy;
758f588d
BP		 5910 int cpu;
5911
c285545f 5912 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5913 cpu = get_cpu();
5914 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5915 if (policy.cpuinfo.max_freq)
5916 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5917 put_cpu();
c285545f 5918#endif
b820cc0c
ZA		 5919 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5920 CPUFREQ_TRANSITION_NOTIFIER);
5921 }
c285545f 5922 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5923
73c1b41e 5924 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5925 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5926}
5927
ff9d07a0
ZY		 5928static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5929
f5132b01 5930int kvm_is_in_guest(void)
ff9d07a0 5931{
086c9855 5932 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5933}
5934
5935static int kvm_is_user_mode(void)
5936{
5937 int user_mode = 3;
dcf46b94 5938
086c9855
AS		 5939 if (__this_cpu_read(current_vcpu))
5940 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5941
ff9d07a0
ZY		 5942 return user_mode != 0;
5943}
5944
5945static unsigned long kvm_get_guest_ip(void)
5946{
5947 unsigned long ip = 0;
dcf46b94 5948
086c9855
AS		 5949 if (__this_cpu_read(current_vcpu))
5950 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5951
ff9d07a0
ZY		 5952 return ip;
5953}
5954
5955static struct perf_guest_info_callbacks kvm_guest_cbs = {
5956 .is_in_guest = kvm_is_in_guest,
5957 .is_user_mode = kvm_is_user_mode,
5958 .get_guest_ip = kvm_get_guest_ip,
5959};
5960
5961void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5962{
086c9855 5963 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5964}
5965EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5966
5967void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5968{
086c9855 5969 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5970}
5971EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5972
ce88decf
XG		 5973static void kvm_set_mmio_spte_mask(void)
5974{
5975 u64 mask;
5976 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5977
5978 /*
5979 * Set the reserved bits and the present bit of an paging-structure
5980 * entry to generate page fault with PFER.RSV = 1.
5981 */
885032b9 5982 /* Mask the reserved physical address bits. */
d1431483 5983 mask = rsvd_bits(maxphyaddr, 51);
885032b9 5984
885032b9 5985 /* Set the present bit. */
ce88decf
XG		 5986 mask |= 1ull;
5987
5988#ifdef CONFIG_X86_64
5989 /*
5990 * If reserved bit is not supported, clear the present bit to disable
5991 * mmio page fault.
5992 */
5993 if (maxphyaddr == 52)
5994 mask &= ~1ull;
5995#endif
5996
5997 kvm_mmu_set_mmio_spte_mask(mask);
5998}
5999
16e8d74d
MT		 6000#ifdef CONFIG_X86_64
6001static void pvclock_gtod_update_fn(struct work_struct *work)
6002{
d828199e
MT		 6003 struct kvm *kvm;
6004
6005 struct kvm_vcpu *vcpu;
6006 int i;
6007
2f303b74 6008 spin_lock(&kvm_lock);
d828199e
MT		 6009 list_for_each_entry(kvm, &vm_list, vm_list)
6010 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6011 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6012 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6013 spin_unlock(&kvm_lock);
16e8d74d
MT		 6014}
6015
6016static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6017
6018/*
6019 * Notification about pvclock gtod data update.
6020 */
6021static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6022 void *priv)
6023{
6024 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6025 struct timekeeper *tk = priv;
6026
6027 update_pvclock_gtod(tk);
6028
6029 /* disable master clock if host does not trust, or does not
6030 * use, TSC clocksource
6031 */
6032 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6033 atomic_read(&kvm_guest_has_master_clock) != 0)
6034 queue_work(system_long_wq, &pvclock_gtod_work);
6035
6036 return 0;
6037}
6038
6039static struct notifier_block pvclock_gtod_notifier = {
6040 .notifier_call = pvclock_gtod_notify,
6041};
6042#endif
6043
f8c16bba 6044int kvm_arch_init(void *opaque)
043405e1 6045{
b820cc0c 6046 int r;
6b61edf7 6047 struct kvm_x86_ops *ops = opaque;
f8c16bba 6048
f8c16bba
ZX		 6049 if (kvm_x86_ops) {
6050 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6051 r = -EEXIST;
6052 goto out;
f8c16bba
ZX		 6053 }
6054
6055 if (!ops->cpu_has_kvm_support()) {
6056 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6057 r = -EOPNOTSUPP;
6058 goto out;
f8c16bba
ZX		 6059 }
6060 if (ops->disabled_by_bios()) {
6061 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6062 r = -EOPNOTSUPP;
6063 goto out;
f8c16bba
ZX		 6064 }
6065
013f6a5d
MT		 6066 r = -ENOMEM;
6067 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6068 if (!shared_msrs) {
6069 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6070 goto out;
6071 }
6072
97db56ce
AK		 6073 r = kvm_mmu_module_init();
6074 if (r)
013f6a5d 6075 goto out_free_percpu;
97db56ce 6076
ce88decf 6077 kvm_set_mmio_spte_mask();
97db56ce 6078
f8c16bba 6079 kvm_x86_ops = ops;
920c8377 6080
7b52345e 6081 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6082 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6083 PT_PRESENT_MASK, 0);
b820cc0c 6084 kvm_timer_init();
c8076604 6085
ff9d07a0
ZY		 6086 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6087
d366bf7e 6088 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6089 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6090
c5cc421b 6091 kvm_lapic_init();
16e8d74d
MT		 6092#ifdef CONFIG_X86_64
6093 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6094#endif
6095
f8c16bba 6096 return 0;
56c6d28a 6097
013f6a5d
MT		 6098out_free_percpu:
6099 free_percpu(shared_msrs);
56c6d28a 6100out:
56c6d28a 6101 return r;
043405e1 6102}
8776e519 6103
f8c16bba
ZX		 6104void kvm_arch_exit(void)
6105{
cef84c30 6106 kvm_lapic_exit();
ff9d07a0
ZY		 6107 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6108
888d256e
JK		 6109 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6110 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6111 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6112 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6113#ifdef CONFIG_X86_64
6114 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6115#endif
f8c16bba 6116 kvm_x86_ops = NULL;
56c6d28a 6117 kvm_mmu_module_exit();
013f6a5d 6118 free_percpu(shared_msrs);
56c6d28a 6119}
f8c16bba 6120
5cb56059 6121int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6122{
6123 ++vcpu->stat.halt_exits;
35754c98 6124 if (lapic_in_kernel(vcpu)) {
a4535290 6125 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6126 return 1;
6127 } else {
6128 vcpu->run->exit_reason = KVM_EXIT_HLT;
6129 return 0;
6130 }
6131}
5cb56059
JS		 6132EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6133
6134int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6135{
6affcbed
KH		 6136 int ret = kvm_skip_emulated_instruction(vcpu);
6137 /*
6138 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6139 * KVM_EXIT_DEBUG here.
6140 */
6141 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6142}
8776e519
HB		 6143EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6144
8ef81a9a 6145#ifdef CONFIG_X86_64
55dd00a7
MT		 6146static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6147 unsigned long clock_type)
6148{
6149 struct kvm_clock_pairing clock_pairing;
6150 struct timespec ts;
80fbd89c 6151 u64 cycle;
55dd00a7
MT		 6152 int ret;
6153
6154 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6155 return -KVM_EOPNOTSUPP;
6156
6157 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6158 return -KVM_EOPNOTSUPP;
6159
6160 clock_pairing.sec = ts.tv_sec;
6161 clock_pairing.nsec = ts.tv_nsec;
6162 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6163 clock_pairing.flags = 0;
6164
6165 ret = 0;
6166 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6167 sizeof(struct kvm_clock_pairing)))
6168 ret = -KVM_EFAULT;
6169
6170 return ret;
6171}
8ef81a9a 6172#endif
55dd00a7 6173
6aef266c
SV		 6174/*
6175 * kvm_pv_kick_cpu_op: Kick a vcpu.
6176 *
6177 * @apicid - apicid of vcpu to be kicked.
6178 */
6179static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6180{
24d2166b 6181 struct kvm_lapic_irq lapic_irq;
6aef266c 6182
24d2166b
R		 6183 lapic_irq.shorthand = 0;
6184 lapic_irq.dest_mode = 0;
6185 lapic_irq.dest_id = apicid;
93bbf0b8 6186 lapic_irq.msi_redir_hint = false;
6aef266c 6187
24d2166b 6188 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6189 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6190}
6191
d62caabb
AS		 6192void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6193{
6194 vcpu->arch.apicv_active = false;
6195 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6196}
6197
8776e519
HB		 6198int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6199{
6200 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6201 int op_64_bit, r;
8776e519 6202
6affcbed 6203 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6204
55cd8e5a
GN		 6205 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6206 return kvm_hv_hypercall(vcpu);
6207
5fdbf976
MT		 6208 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6209 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6210 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6211 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6212 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6213
229456fc 6214 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6215
a449c7aa
NA		 6216 op_64_bit = is_64_bit_mode(vcpu);
6217 if (!op_64_bit) {
8776e519
HB		 6218 nr &= 0xFFFFFFFF;
6219 a0 &= 0xFFFFFFFF;
6220 a1 &= 0xFFFFFFFF;
6221 a2 &= 0xFFFFFFFF;
6222 a3 &= 0xFFFFFFFF;
6223 }
6224
07708c4a
JK		 6225 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6226 ret = -KVM_EPERM;
6227 goto out;
6228 }
6229
8776e519 6230 switch (nr) {
b93463aa
AK		 6231 case KVM_HC_VAPIC_POLL_IRQ:
6232 ret = 0;
6233 break;
6aef266c
SV		 6234 case KVM_HC_KICK_CPU:
6235 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6236 ret = 0;
6237 break;
8ef81a9a 6238#ifdef CONFIG_X86_64
55dd00a7
MT		 6239 case KVM_HC_CLOCK_PAIRING:
6240 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6241 break;
8ef81a9a 6242#endif
8776e519
HB		 6243 default:
6244 ret = -KVM_ENOSYS;
6245 break;
6246 }
07708c4a 6247out:
a449c7aa
NA		 6248 if (!op_64_bit)
6249 ret = (u32)ret;
5fdbf976 6250 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6251 ++vcpu->stat.hypercalls;
2f333bcb 6252 return r;
8776e519
HB		 6253}
6254EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6255
b6785def 6256static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6257{
d6aa1000 6258 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6259 char instruction[3];
5fdbf976 6260 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6261
8776e519 6262 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6263
ce2e852e
DV		 6264 return emulator_write_emulated(ctxt, rip, instruction, 3,
6265 &ctxt->exception);
8776e519
HB		 6266}
6267
851ba692 6268static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6269{
782d422b
MG		 6270 return vcpu->run->request_interrupt_window &&
6271 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6272}
6273
851ba692 6274static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6275{
851ba692
AK		 6276 struct kvm_run *kvm_run = vcpu->run;
6277
91586a3b 6278 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6279 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6280 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6281 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6282 kvm_run->ready_for_interrupt_injection =
6283 pic_in_kernel(vcpu->kvm) ||
782d422b 6284 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6285}
6286
95ba8273
GN		 6287static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6288{
6289 int max_irr, tpr;
6290
6291 if (!kvm_x86_ops->update_cr8_intercept)
6292 return;
6293
bce87cce 6294 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6295 return;
6296
d62caabb
AS		 6297 if (vcpu->arch.apicv_active)
6298 return;
6299
8db3baa2
GN		 6300 if (!vcpu->arch.apic->vapic_addr)
6301 max_irr = kvm_lapic_find_highest_irr(vcpu);
6302 else
6303 max_irr = -1;
95ba8273
GN		 6304
6305 if (max_irr != -1)
6306 max_irr >>= 4;
6307
6308 tpr = kvm_lapic_get_cr8(vcpu);
6309
6310 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6311}
6312
b6b8a145 6313static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6314{
b6b8a145
JK		 6315 int r;
6316
95ba8273 6317 /* try to reinject previous events if any */
b59bb7bd 6318 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6319 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6320 vcpu->arch.exception.has_error_code,
6321 vcpu->arch.exception.error_code);
d6e8c854
NA		 6322
6323 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6324 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6325 X86_EFLAGS_RF);
6326
6bdf0662
NA		 6327 if (vcpu->arch.exception.nr == DB_VECTOR &&
6328 (vcpu->arch.dr7 & DR7_GD)) {
6329 vcpu->arch.dr7 &= ~DR7_GD;
6330 kvm_update_dr7(vcpu);
6331 }
6332
b59bb7bd
GN		 6333 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6334 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6335 vcpu->arch.exception.error_code,
6336 vcpu->arch.exception.reinject);
b6b8a145 6337 return 0;
b59bb7bd
GN		 6338 }
6339
95ba8273
GN		 6340 if (vcpu->arch.nmi_injected) {
6341 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6342 return 0;
95ba8273
GN		 6343 }
6344
6345 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6346 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6347 return 0;
6348 }
6349
6350 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6351 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6352 if (r != 0)
6353 return r;
95ba8273
GN		 6354 }
6355
6356 /* try to inject new event if pending */
c43203ca
PB		 6357 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6358 vcpu->arch.smi_pending = false;
ee2cd4b7 6359 enter_smm(vcpu);
c43203ca 6360 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6361 --vcpu->arch.nmi_pending;
6362 vcpu->arch.nmi_injected = true;
6363 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6364 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6365 /*
6366 * Because interrupts can be injected asynchronously, we are
6367 * calling check_nested_events again here to avoid a race condition.
6368 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6369 * proposal and current concerns. Perhaps we should be setting
6370 * KVM_REQ_EVENT only on certain events and not unconditionally?
6371 */
6372 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6373 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6374 if (r != 0)
6375 return r;
6376 }
95ba8273 6377 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6378 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6379 false);
6380 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6381 }
6382 }
ee2cd4b7 6383
b6b8a145 6384 return 0;
95ba8273
GN		 6385}
6386
7460fb4a
AK		 6387static void process_nmi(struct kvm_vcpu *vcpu)
6388{
6389 unsigned limit = 2;
6390
6391 /*
6392 * x86 is limited to one NMI running, and one NMI pending after it.
6393 * If an NMI is already in progress, limit further NMIs to just one.
6394 * Otherwise, allow two (and we'll inject the first one immediately).
6395 */
6396 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6397 limit = 1;
6398
6399 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6400 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6401 kvm_make_request(KVM_REQ_EVENT, vcpu);
6402}
6403
660a5d51
PB		 6404#define put_smstate(type, buf, offset, val) \
6405 *(type *)((buf) + (offset) - 0x7e00) = val
6406
ee2cd4b7 6407static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6408{
6409 u32 flags = 0;
6410 flags |= seg->g << 23;
6411 flags |= seg->db << 22;
6412 flags |= seg->l << 21;
6413 flags |= seg->avl << 20;
6414 flags |= seg->present << 15;
6415 flags |= seg->dpl << 13;
6416 flags |= seg->s << 12;
6417 flags |= seg->type << 8;
6418 return flags;
6419}
6420
ee2cd4b7 6421static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6422{
6423 struct kvm_segment seg;
6424 int offset;
6425
6426 kvm_get_segment(vcpu, &seg, n);
6427 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6428
6429 if (n < 3)
6430 offset = 0x7f84 + n * 12;
6431 else
6432 offset = 0x7f2c + (n - 3) * 12;
6433
6434 put_smstate(u32, buf, offset + 8, seg.base);
6435 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6436 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6437}
6438
efbb288a 6439#ifdef CONFIG_X86_64
ee2cd4b7 6440static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6441{
6442 struct kvm_segment seg;
6443 int offset;
6444 u16 flags;
6445
6446 kvm_get_segment(vcpu, &seg, n);
6447 offset = 0x7e00 + n * 16;
6448
ee2cd4b7 6449 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6450 put_smstate(u16, buf, offset, seg.selector);
6451 put_smstate(u16, buf, offset + 2, flags);
6452 put_smstate(u32, buf, offset + 4, seg.limit);
6453 put_smstate(u64, buf, offset + 8, seg.base);
6454}
efbb288a 6455#endif
660a5d51 6456
ee2cd4b7 6457static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6458{
6459 struct desc_ptr dt;
6460 struct kvm_segment seg;
6461 unsigned long val;
6462 int i;
6463
6464 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6465 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6466 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6467 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6468
6469 for (i = 0; i < 8; i++)
6470 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6471
6472 kvm_get_dr(vcpu, 6, &val);
6473 put_smstate(u32, buf, 0x7fcc, (u32)val);
6474 kvm_get_dr(vcpu, 7, &val);
6475 put_smstate(u32, buf, 0x7fc8, (u32)val);
6476
6477 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6478 put_smstate(u32, buf, 0x7fc4, seg.selector);
6479 put_smstate(u32, buf, 0x7f64, seg.base);
6480 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6481 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6482
6483 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6484 put_smstate(u32, buf, 0x7fc0, seg.selector);
6485 put_smstate(u32, buf, 0x7f80, seg.base);
6486 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6487 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6488
6489 kvm_x86_ops->get_gdt(vcpu, &dt);
6490 put_smstate(u32, buf, 0x7f74, dt.address);
6491 put_smstate(u32, buf, 0x7f70, dt.size);
6492
6493 kvm_x86_ops->get_idt(vcpu, &dt);
6494 put_smstate(u32, buf, 0x7f58, dt.address);
6495 put_smstate(u32, buf, 0x7f54, dt.size);
6496
6497 for (i = 0; i < 6; i++)
ee2cd4b7 6498 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6499
6500 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6501
6502 /* revision id */
6503 put_smstate(u32, buf, 0x7efc, 0x00020000);
6504 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6505}
6506
ee2cd4b7 6507static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6508{
6509#ifdef CONFIG_X86_64
6510 struct desc_ptr dt;
6511 struct kvm_segment seg;
6512 unsigned long val;
6513 int i;
6514
6515 for (i = 0; i < 16; i++)
6516 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6517
6518 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6519 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6520
6521 kvm_get_dr(vcpu, 6, &val);
6522 put_smstate(u64, buf, 0x7f68, val);
6523 kvm_get_dr(vcpu, 7, &val);
6524 put_smstate(u64, buf, 0x7f60, val);
6525
6526 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6527 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6528 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6529
6530 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6531
6532 /* revision id */
6533 put_smstate(u32, buf, 0x7efc, 0x00020064);
6534
6535 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6536
6537 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6538 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6539 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6540 put_smstate(u32, buf, 0x7e94, seg.limit);
6541 put_smstate(u64, buf, 0x7e98, seg.base);
6542
6543 kvm_x86_ops->get_idt(vcpu, &dt);
6544 put_smstate(u32, buf, 0x7e84, dt.size);
6545 put_smstate(u64, buf, 0x7e88, dt.address);
6546
6547 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6548 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6549 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6550 put_smstate(u32, buf, 0x7e74, seg.limit);
6551 put_smstate(u64, buf, 0x7e78, seg.base);
6552
6553 kvm_x86_ops->get_gdt(vcpu, &dt);
6554 put_smstate(u32, buf, 0x7e64, dt.size);
6555 put_smstate(u64, buf, 0x7e68, dt.address);
6556
6557 for (i = 0; i < 6; i++)
ee2cd4b7 6558 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6559#else
6560 WARN_ON_ONCE(1);
6561#endif
6562}
6563
ee2cd4b7 6564static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6565{
660a5d51 6566 struct kvm_segment cs, ds;
18c3626e 6567 struct desc_ptr dt;
660a5d51
PB		 6568 char buf[512];
6569 u32 cr0;
6570
660a5d51
PB		 6571 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6572 vcpu->arch.hflags |= HF_SMM_MASK;
6573 memset(buf, 0, 512);
6574 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6575 enter_smm_save_state_64(vcpu, buf);
660a5d51 6576 else
ee2cd4b7 6577 enter_smm_save_state_32(vcpu, buf);
660a5d51 6578
54bf36aa 6579 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6580
6581 if (kvm_x86_ops->get_nmi_mask(vcpu))
6582 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6583 else
6584 kvm_x86_ops->set_nmi_mask(vcpu, true);
6585
6586 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6587 kvm_rip_write(vcpu, 0x8000);
6588
6589 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6590 kvm_x86_ops->set_cr0(vcpu, cr0);
6591 vcpu->arch.cr0 = cr0;
6592
6593 kvm_x86_ops->set_cr4(vcpu, 0);
6594
18c3626e
PB		 6595 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6596 dt.address = dt.size = 0;
6597 kvm_x86_ops->set_idt(vcpu, &dt);
6598
660a5d51
PB		 6599 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6600
6601 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6602 cs.base = vcpu->arch.smbase;
6603
6604 ds.selector = 0;
6605 ds.base = 0;
6606
6607 cs.limit = ds.limit = 0xffffffff;
6608 cs.type = ds.type = 0x3;
6609 cs.dpl = ds.dpl = 0;
6610 cs.db = ds.db = 0;
6611 cs.s = ds.s = 1;
6612 cs.l = ds.l = 0;
6613 cs.g = ds.g = 1;
6614 cs.avl = ds.avl = 0;
6615 cs.present = ds.present = 1;
6616 cs.unusable = ds.unusable = 0;
6617 cs.padding = ds.padding = 0;
6618
6619 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6620 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6621 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6622 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6623 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6624 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6625
6626 if (guest_cpuid_has_longmode(vcpu))
6627 kvm_x86_ops->set_efer(vcpu, 0);
6628
6629 kvm_update_cpuid(vcpu);
6630 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6631}
6632
ee2cd4b7 6633static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6634{
6635 vcpu->arch.smi_pending = true;
6636 kvm_make_request(KVM_REQ_EVENT, vcpu);
6637}
6638
2860c4b1
PB		 6639void kvm_make_scan_ioapic_request(struct kvm *kvm)
6640{
6641 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6642}
6643
3d81bc7e 6644static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6645{
5c919412
AS		 6646 u64 eoi_exit_bitmap[4];
6647
3d81bc7e
YZ		 6648 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6649 return;
c7c9c56c 6650
6308630b 6651 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6652
b053b2ae 6653 if (irqchip_split(vcpu->kvm))
6308630b 6654 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6655 else {
76dfafd5 6656 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6657 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6658 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6659 }
5c919412
AS		 6660 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6661 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6662 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6663}
6664
a70656b6
RK		 6665static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6666{
6667 ++vcpu->stat.tlb_flush;
6668 kvm_x86_ops->tlb_flush(vcpu);
6669}
6670
4256f43f
TC		 6671void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6672{
c24ae0dc
TC		 6673 struct page *page = NULL;
6674
35754c98 6675 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6676 return;
6677
4256f43f
TC		 6678 if (!kvm_x86_ops->set_apic_access_page_addr)
6679 return;
6680
c24ae0dc 6681 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6682 if (is_error_page(page))
6683 return;
c24ae0dc
TC		 6684 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6685
6686 /*
6687 * Do not pin apic access page in memory, the MMU notifier
6688 * will call us again if it is migrated or swapped out.
6689 */
6690 put_page(page);
4256f43f
TC		 6691}
6692EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6693
fe71557a
TC		 6694void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6695 unsigned long address)
6696{
c24ae0dc
TC		 6697 /*
6698 * The physical address of apic access page is stored in the VMCS.
6699 * Update it when it becomes invalid.
6700 */
6701 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6702 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6703}
6704
9357d939 6705/*
362c698f 6706 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6707 * exiting to the userspace. Otherwise, the value will be returned to the
6708 * userspace.
6709 */
851ba692 6710static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6711{
6712 int r;
62a193ed
MG		 6713 bool req_int_win =
6714 dm_request_for_irq_injection(vcpu) &&
6715 kvm_cpu_accept_dm_intr(vcpu);
6716
730dca42 6717 bool req_immediate_exit = false;
b6c7a5dc 6718
3e007509 6719 if (vcpu->requests) {
a8eeb04a 6720 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6721 kvm_mmu_unload(vcpu);
a8eeb04a 6722 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6723 __kvm_migrate_timers(vcpu);
d828199e
MT		 6724 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6725 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6726 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6727 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6728 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6729 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6730 if (unlikely(r))
6731 goto out;
6732 }
a8eeb04a 6733 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6734 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6735 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6736 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6737 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6738 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6739 r = 0;
6740 goto out;
6741 }
a8eeb04a 6742 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6743 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6744 r = 0;
6745 goto out;
6746 }
af585b92
GN		 6747 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6748 /* Page is swapped out. Do synthetic halt */
6749 vcpu->arch.apf.halted = true;
6750 r = 1;
6751 goto out;
6752 }
c9aaa895
GC		 6753 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6754 record_steal_time(vcpu);
64d60670
PB		 6755 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6756 process_smi(vcpu);
7460fb4a
AK		 6757 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6758 process_nmi(vcpu);
f5132b01 6759 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6760 kvm_pmu_handle_event(vcpu);
f5132b01 6761 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6762 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6763 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6764 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6765 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6766 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6767 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6768 vcpu->run->eoi.vector =
6769 vcpu->arch.pending_ioapic_eoi;
6770 r = 0;
6771 goto out;
6772 }
6773 }
3d81bc7e
YZ		 6774 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6775 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6776 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6777 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6778 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6779 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6780 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6781 r = 0;
6782 goto out;
6783 }
e516cebb
AS		 6784 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6785 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6786 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6787 r = 0;
6788 goto out;
6789 }
db397571
AS		 6790 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6791 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6792 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6793 r = 0;
6794 goto out;
6795 }
f3b138c5
AS		 6796
6797 /*
6798 * KVM_REQ_HV_STIMER has to be processed after
6799 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6800 * depend on the guest clock being up-to-date
6801 */
1f4b34f8
AS		 6802 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6803 kvm_hv_process_stimers(vcpu);
2f52d58c 6804 }
b93463aa 6805
b463a6f7 6806 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6807 ++vcpu->stat.req_event;
66450a21
JK		 6808 kvm_apic_accept_events(vcpu);
6809 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6810 r = 1;
6811 goto out;
6812 }
6813
b6b8a145
JK		 6814 if (inject_pending_event(vcpu, req_int_win) != 0)
6815 req_immediate_exit = true;
321c5658 6816 else {
c43203ca
PB		 6817 /* Enable NMI/IRQ window open exits if needed.
6818 *
6819 * SMIs have two cases: 1) they can be nested, and
6820 * then there is nothing to do here because RSM will
6821 * cause a vmexit anyway; 2) or the SMI can be pending
6822 * because inject_pending_event has completed the
6823 * injection of an IRQ or NMI from the previous vmexit,
6824 * and then we request an immediate exit to inject the SMI.
6825 */
6826 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6827 req_immediate_exit = true;
321c5658
YS		 6828 if (vcpu->arch.nmi_pending)
6829 kvm_x86_ops->enable_nmi_window(vcpu);
6830 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6831 kvm_x86_ops->enable_irq_window(vcpu);
6832 }
b463a6f7
AK		 6833
6834 if (kvm_lapic_enabled(vcpu)) {
6835 update_cr8_intercept(vcpu);
6836 kvm_lapic_sync_to_vapic(vcpu);
6837 }
6838 }
6839
d8368af8
AK		 6840 r = kvm_mmu_reload(vcpu);
6841 if (unlikely(r)) {
d905c069 6842 goto cancel_injection;
d8368af8
AK		 6843 }
6844
b6c7a5dc
HB		 6845 preempt_disable();
6846
6847 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6848 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6849
6850 /*
6851 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6852 * IPI are then delayed after guest entry, which ensures that they
6853 * result in virtual interrupt delivery.
6854 */
6855 local_irq_disable();
6b7e2d09
XG		 6856 vcpu->mode = IN_GUEST_MODE;
6857
01b71917
MT		 6858 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6859
0f127d12 6860 /*
b95234c8
PB		 6861 * 1) We should set ->mode before checking ->requests. Please see
6862 * the comment in kvm_make_all_cpus_request.
6863 *
6864 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6865 * pairs with the memory barrier implicit in pi_test_and_set_on
6866 * (see vmx_deliver_posted_interrupt).
6867 *
6868 * 3) This also orders the write to mode from any reads to the page
6869 * tables done while the VCPU is running. Please see the comment
6870 * in kvm_flush_remote_tlbs.
6b7e2d09 6871 */
01b71917 6872 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6873
b95234c8
PB		 6874 /*
6875 * This handles the case where a posted interrupt was
6876 * notified with kvm_vcpu_kick.
6877 */
6878 if (kvm_lapic_enabled(vcpu)) {
6879 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6880 kvm_x86_ops->sync_pir_to_irr(vcpu);
6881 }
32f88400 6882
6b7e2d09 6883 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6884 || need_resched() || signal_pending(current)) {
6b7e2d09 6885 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6886 smp_wmb();
6c142801
AK		 6887 local_irq_enable();
6888 preempt_enable();
01b71917 6889 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6890 r = 1;
d905c069 6891 goto cancel_injection;
6c142801
AK		 6892 }
6893
fc5b7f3b
DM		 6894 kvm_load_guest_xcr0(vcpu);
6895
c43203ca
PB		 6896 if (req_immediate_exit) {
6897 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6898 smp_send_reschedule(vcpu->cpu);
c43203ca 6899 }
d6185f20 6900
8b89fe1f
PB		 6901 trace_kvm_entry(vcpu->vcpu_id);
6902 wait_lapic_expire(vcpu);
6edaa530 6903 guest_enter_irqoff();
b6c7a5dc 6904
42dbaa5a 6905 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6906 set_debugreg(0, 7);
6907 set_debugreg(vcpu->arch.eff_db[0], 0);
6908 set_debugreg(vcpu->arch.eff_db[1], 1);
6909 set_debugreg(vcpu->arch.eff_db[2], 2);
6910 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6911 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6912 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6913 }
b6c7a5dc 6914
851ba692 6915 kvm_x86_ops->run(vcpu);
b6c7a5dc 6916
c77fb5fe
PB		 6917 /*
6918 * Do this here before restoring debug registers on the host. And
6919 * since we do this before handling the vmexit, a DR access vmexit
6920 * can (a) read the correct value of the debug registers, (b) set
6921 * KVM_DEBUGREG_WONT_EXIT again.
6922 */
6923 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6924 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6925 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6926 kvm_update_dr0123(vcpu);
6927 kvm_update_dr6(vcpu);
6928 kvm_update_dr7(vcpu);
6929 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6930 }
6931
24f1e32c
FW		 6932 /*
6933 * If the guest has used debug registers, at least dr7
6934 * will be disabled while returning to the host.
6935 * If we don't have active breakpoints in the host, we don't
6936 * care about the messed up debug address registers. But if
6937 * we have some of them active, restore the old state.
6938 */
59d8eb53 6939 if (hw_breakpoint_active())
24f1e32c 6940 hw_breakpoint_restore();
42dbaa5a 6941
4ba76538 6942 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6943
6b7e2d09 6944 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6945 smp_wmb();
a547c6db 6946
fc5b7f3b
DM		 6947 kvm_put_guest_xcr0(vcpu);
6948
a547c6db 6949 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6950
6951 ++vcpu->stat.exits;
6952
f2485b3e 6953 guest_exit_irqoff();
b6c7a5dc 6954
f2485b3e 6955 local_irq_enable();
b6c7a5dc
HB		 6956 preempt_enable();
6957
f656ce01 6958 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6959
b6c7a5dc
HB		 6960 /*
6961 * Profile KVM exit RIPs:
6962 */
6963 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6964 unsigned long rip = kvm_rip_read(vcpu);
6965 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6966 }
6967
cc578287
ZA		 6968 if (unlikely(vcpu->arch.tsc_always_catchup))
6969 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6970
5cfb1d5a
MT		 6971 if (vcpu->arch.apic_attention)
6972 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6973
851ba692 6974 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6975 return r;
6976
6977cancel_injection:
6978 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6979 if (unlikely(vcpu->arch.apic_attention))
6980 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6981out:
6982 return r;
6983}
b6c7a5dc 6984
362c698f
PB		 6985static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6986{
bf9f6ac8
FW		 6987 if (!kvm_arch_vcpu_runnable(vcpu) &&
6988 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6989 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6990 kvm_vcpu_block(vcpu);
6991 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6992
6993 if (kvm_x86_ops->post_block)
6994 kvm_x86_ops->post_block(vcpu);
6995
9c8fd1ba
PB		 6996 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6997 return 1;
6998 }
362c698f
PB		 6999
7000 kvm_apic_accept_events(vcpu);
7001 switch(vcpu->arch.mp_state) {
7002 case KVM_MP_STATE_HALTED:
7003 vcpu->arch.pv.pv_unhalted = false;
7004 vcpu->arch.mp_state =
7005 KVM_MP_STATE_RUNNABLE;
7006 case KVM_MP_STATE_RUNNABLE:
7007 vcpu->arch.apf.halted = false;
7008 break;
7009 case KVM_MP_STATE_INIT_RECEIVED:
7010 break;
7011 default:
7012 return -EINTR;
7013 break;
7014 }
7015 return 1;
7016}
09cec754 7017
5d9bc648
PB		 7018static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7019{
0ad3bed6
PB		 7020 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7021 kvm_x86_ops->check_nested_events(vcpu, false);
7022
5d9bc648
PB		 7023 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7024 !vcpu->arch.apf.halted);
7025}
7026
362c698f 7027static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7028{
7029 int r;
f656ce01 7030 struct kvm *kvm = vcpu->kvm;
d7690175 7031
f656ce01 7032 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7033
362c698f 7034 for (;;) {
58f800d5 7035 if (kvm_vcpu_running(vcpu)) {
851ba692 7036 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7037 } else {
362c698f 7038 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7039 }
7040
09cec754
GN		 7041 if (r <= 0)
7042 break;
7043
7044 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
7045 if (kvm_cpu_has_pending_timer(vcpu))
7046 kvm_inject_pending_timer_irqs(vcpu);
7047
782d422b
MG		 7048 if (dm_request_for_irq_injection(vcpu) &&
7049 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7050 r = 0;
7051 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7052 ++vcpu->stat.request_irq_exits;
362c698f 7053 break;
09cec754 7054 }
af585b92
GN		 7055
7056 kvm_check_async_pf_completion(vcpu);
7057
09cec754
GN		 7058 if (signal_pending(current)) {
7059 r = -EINTR;
851ba692 7060 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7061 ++vcpu->stat.signal_exits;
362c698f 7062 break;
09cec754
GN		 7063 }
7064 if (need_resched()) {
f656ce01 7065 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7066 cond_resched();
f656ce01 7067 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7068 }
b6c7a5dc
HB		 7069 }
7070
f656ce01 7071 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7072
7073 return r;
7074}
7075
716d51ab
GN		 7076static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7077{
7078 int r;
7079 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7080 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7081 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7082 if (r != EMULATE_DONE)
7083 return 0;
7084 return 1;
7085}
7086
7087static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7088{
7089 BUG_ON(!vcpu->arch.pio.count);
7090
7091 return complete_emulated_io(vcpu);
7092}
7093
f78146b0
AK		 7094/*
7095 * Implements the following, as a state machine:
7096 *
7097 * read:
7098 * for each fragment
87da7e66
XG		 7099 * for each mmio piece in the fragment
7100 * write gpa, len
7101 * exit
7102 * copy data
f78146b0
AK		 7103 * execute insn
7104 *
7105 * write:
7106 * for each fragment
87da7e66
XG		 7107 * for each mmio piece in the fragment
7108 * write gpa, len
7109 * copy data
7110 * exit
f78146b0 7111 */
716d51ab 7112static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7113{
7114 struct kvm_run *run = vcpu->run;
f78146b0 7115 struct kvm_mmio_fragment *frag;
87da7e66 7116 unsigned len;
5287f194 7117
716d51ab 7118 BUG_ON(!vcpu->mmio_needed);
5287f194 7119
716d51ab 7120 /* Complete previous fragment */
87da7e66
XG		 7121 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7122 len = min(8u, frag->len);
716d51ab 7123 if (!vcpu->mmio_is_write)
87da7e66
XG		 7124 memcpy(frag->data, run->mmio.data, len);
7125
7126 if (frag->len <= 8) {
7127 /* Switch to the next fragment. */
7128 frag++;
7129 vcpu->mmio_cur_fragment++;
7130 } else {
7131 /* Go forward to the next mmio piece. */
7132 frag->data += len;
7133 frag->gpa += len;
7134 frag->len -= len;
7135 }
7136
a08d3b3b 7137 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7138 vcpu->mmio_needed = 0;
0912c977
PB		 7139
7140 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7141 if (vcpu->mmio_is_write)
716d51ab
GN		 7142 return 1;
7143 vcpu->mmio_read_completed = 1;
7144 return complete_emulated_io(vcpu);
7145 }
87da7e66 7146
716d51ab
GN		 7147 run->exit_reason = KVM_EXIT_MMIO;
7148 run->mmio.phys_addr = frag->gpa;
7149 if (vcpu->mmio_is_write)
87da7e66
XG		 7150 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7151 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7152 run->mmio.is_write = vcpu->mmio_is_write;
7153 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7154 return 0;
5287f194
AK		 7155}
7156
716d51ab 7157
b6c7a5dc
HB		 7158int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7159{
c5bedc68 7160 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7161 int r;
7162 sigset_t sigsaved;
7163
c4d72e2d 7164 fpu__activate_curr(fpu);
e5c30142 7165
ac9f6dc0
AK		 7166 if (vcpu->sigset_active)
7167 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7168
a4535290 7169 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7170 kvm_vcpu_block(vcpu);
66450a21 7171 kvm_apic_accept_events(vcpu);
d7690175 7172 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 7173 r = -EAGAIN;
7174 goto out;
b6c7a5dc
HB		 7175 }
7176
b6c7a5dc 7177 /* re-sync apic's tpr */
35754c98 7178 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7179 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7180 r = -EINVAL;
7181 goto out;
7182 }
7183 }
b6c7a5dc 7184
716d51ab
GN		 7185 if (unlikely(vcpu->arch.complete_userspace_io)) {
7186 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7187 vcpu->arch.complete_userspace_io = NULL;
7188 r = cui(vcpu);
7189 if (r <= 0)
7190 goto out;
7191 } else
7192 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7193
460df4c1
PB		 7194 if (kvm_run->immediate_exit)
7195 r = -EINTR;
7196 else
7197 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7198
7199out:
f1d86e46 7200 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7201 if (vcpu->sigset_active)
7202 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7203
b6c7a5dc
HB		 7204 return r;
7205}
7206
7207int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7208{
7ae441ea
GN		 7209 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7210 /*
7211 * We are here if userspace calls get_regs() in the middle of
7212 * instruction emulation. Registers state needs to be copied
4a969980 7213 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7214 * that usually, but some bad designed PV devices (vmware
7215 * backdoor interface) need this to work
7216 */
dd856efa 7217 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7218 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7219 }
5fdbf976
MT		 7220 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7221 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7222 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7223 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7224 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7225 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7226 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7227 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7228#ifdef CONFIG_X86_64
5fdbf976
MT		 7229 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7230 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7231 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7232 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7233 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7234 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7235 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7236 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7237#endif
7238
5fdbf976 7239 regs->rip = kvm_rip_read(vcpu);
91586a3b 7240 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7241
b6c7a5dc
HB		 7242 return 0;
7243}
7244
7245int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7246{
7ae441ea
GN		 7247 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7248 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7249
5fdbf976
MT		 7250 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7251 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7252 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7253 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7254 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7255 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7256 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7257 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7258#ifdef CONFIG_X86_64
5fdbf976
MT		 7259 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7260 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7261 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7262 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7263 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7264 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7265 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7266 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7267#endif
7268
5fdbf976 7269 kvm_rip_write(vcpu, regs->rip);
91586a3b 7270 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7271
b4f14abd
JK		 7272 vcpu->arch.exception.pending = false;
7273
3842d135
AK		 7274 kvm_make_request(KVM_REQ_EVENT, vcpu);
7275
b6c7a5dc
HB		 7276 return 0;
7277}
7278
b6c7a5dc
HB		 7279void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7280{
7281 struct kvm_segment cs;
7282
3e6e0aab 7283 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7284 *db = cs.db;
7285 *l = cs.l;
7286}
7287EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7288
7289int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7290 struct kvm_sregs *sregs)
7291{
89a27f4d 7292 struct desc_ptr dt;
b6c7a5dc 7293
3e6e0aab
GT		 7294 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7295 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7296 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7297 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7298 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7299 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7300
3e6e0aab
GT		 7301 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7302 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7303
7304 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7305 sregs->idt.limit = dt.size;
7306 sregs->idt.base = dt.address;
b6c7a5dc 7307 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7308 sregs->gdt.limit = dt.size;
7309 sregs->gdt.base = dt.address;
b6c7a5dc 7310
4d4ec087 7311 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7312 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7313 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7314 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7315 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7316 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7317 sregs->apic_base = kvm_get_apic_base(vcpu);
7318
923c61bb 7319 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7320
36752c9b 7321 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7322 set_bit(vcpu->arch.interrupt.nr,
7323 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7324
b6c7a5dc
HB		 7325 return 0;
7326}
7327
62d9f0db
MT		 7328int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7329 struct kvm_mp_state *mp_state)
7330{
66450a21 7331 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7332 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7333 vcpu->arch.pv.pv_unhalted)
7334 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7335 else
7336 mp_state->mp_state = vcpu->arch.mp_state;
7337
62d9f0db
MT		 7338 return 0;
7339}
7340
7341int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7342 struct kvm_mp_state *mp_state)
7343{
bce87cce 7344 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7345 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7346 return -EINVAL;
7347
28bf2888
DH		 7348 /* INITs are latched while in SMM */
7349 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7350 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7351 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7352 return -EINVAL;
7353
66450a21
JK		 7354 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7355 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7356 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7357 } else
7358 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7359 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7360 return 0;
7361}
7362
7f3d35fd
KW		 7363int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7364 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7365{
9d74191a 7366 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7367 int ret;
e01c2426 7368
8ec4722d 7369 init_emulate_ctxt(vcpu);
c697518a 7370
7f3d35fd 7371 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7372 has_error_code, error_code);
c697518a 7373
c697518a 7374 if (ret)
19d04437 7375 return EMULATE_FAIL;
37817f29 7376
9d74191a
TY		 7377 kvm_rip_write(vcpu, ctxt->eip);
7378 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7379 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7380 return EMULATE_DONE;
37817f29
IE		 7381}
7382EXPORT_SYMBOL_GPL(kvm_task_switch);
7383
b6c7a5dc
HB		 7384int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7385 struct kvm_sregs *sregs)
7386{
58cb628d 7387 struct msr_data apic_base_msr;
b6c7a5dc 7388 int mmu_reset_needed = 0;
63f42e02 7389 int pending_vec, max_bits, idx;
89a27f4d 7390 struct desc_ptr dt;
b6c7a5dc 7391
6d1068b3
PM		 7392 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7393 return -EINVAL;
7394
89a27f4d
GN		 7395 dt.size = sregs->idt.limit;
7396 dt.address = sregs->idt.base;
b6c7a5dc 7397 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7398 dt.size = sregs->gdt.limit;
7399 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7400 kvm_x86_ops->set_gdt(vcpu, &dt);
7401
ad312c7c 7402 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7403 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7404 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7405 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7406
2d3ad1f4 7407 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7408
f6801dff 7409 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7410 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7411 apic_base_msr.data = sregs->apic_base;
7412 apic_base_msr.host_initiated = true;
7413 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7414
4d4ec087 7415 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7416 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7417 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7418
fc78f519 7419 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7420 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7421 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7422 kvm_update_cpuid(vcpu);
63f42e02
XG		 7423
7424 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7425 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7426 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7427 mmu_reset_needed = 1;
7428 }
63f42e02 7429 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7430
7431 if (mmu_reset_needed)
7432 kvm_mmu_reset_context(vcpu);
7433
a50abc3b 7434 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7435 pending_vec = find_first_bit(
7436 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7437 if (pending_vec < max_bits) {
66fd3f7f 7438 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7439 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7440 }
7441
3e6e0aab
GT		 7442 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7443 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7444 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7445 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7446 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7447 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7448
3e6e0aab
GT		 7449 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7450 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7451
5f0269f5
ME		 7452 update_cr8_intercept(vcpu);
7453
9c3e4aab 7454 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7455 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7456 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7457 !is_protmode(vcpu))
9c3e4aab
MT		 7458 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7459
3842d135
AK		 7460 kvm_make_request(KVM_REQ_EVENT, vcpu);
7461
b6c7a5dc
HB		 7462 return 0;
7463}
7464
d0bfb940
JK		 7465int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7466 struct kvm_guest_debug *dbg)
b6c7a5dc 7467{
355be0b9 7468 unsigned long rflags;
ae675ef0 7469 int i, r;
b6c7a5dc 7470
4f926bf2
JK		 7471 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7472 r = -EBUSY;
7473 if (vcpu->arch.exception.pending)
2122ff5e 7474 goto out;
4f926bf2
JK		 7475 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7476 kvm_queue_exception(vcpu, DB_VECTOR);
7477 else
7478 kvm_queue_exception(vcpu, BP_VECTOR);
7479 }
7480
91586a3b
JK		 7481 /*
7482 * Read rflags as long as potentially injected trace flags are still
7483 * filtered out.
7484 */
7485 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7486
7487 vcpu->guest_debug = dbg->control;
7488 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7489 vcpu->guest_debug = 0;
7490
7491 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7492 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7493 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7494 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7495 } else {
7496 for (i = 0; i < KVM_NR_DB_REGS; i++)
7497 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7498 }
c8639010 7499 kvm_update_dr7(vcpu);
ae675ef0 7500
f92653ee
JK		 7501 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7502 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7503 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7504
91586a3b
JK		 7505 /*
7506 * Trigger an rflags update that will inject or remove the trace
7507 * flags.
7508 */
7509 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7510
a96036b8 7511 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7512
4f926bf2 7513 r = 0;
d0bfb940 7514
2122ff5e 7515out:
b6c7a5dc
HB		 7516
7517 return r;
7518}
7519
8b006791
ZX		 7520/*
7521 * Translate a guest virtual address to a guest physical address.
7522 */
7523int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7524 struct kvm_translation *tr)
7525{
7526 unsigned long vaddr = tr->linear_address;
7527 gpa_t gpa;
f656ce01 7528 int idx;
8b006791 7529
f656ce01 7530 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7531 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7532 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7533 tr->physical_address = gpa;
7534 tr->valid = gpa != UNMAPPED_GVA;
7535 tr->writeable = 1;
7536 tr->usermode = 0;
8b006791
ZX		 7537
7538 return 0;
7539}
7540
d0752060
HB		 7541int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7542{
c47ada30 7543 struct fxregs_state *fxsave =
7366ed77 7544 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7545
d0752060
HB		 7546 memcpy(fpu->fpr, fxsave->st_space, 128);
7547 fpu->fcw = fxsave->cwd;
7548 fpu->fsw = fxsave->swd;
7549 fpu->ftwx = fxsave->twd;
7550 fpu->last_opcode = fxsave->fop;
7551 fpu->last_ip = fxsave->rip;
7552 fpu->last_dp = fxsave->rdp;
7553 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7554
d0752060
HB		 7555 return 0;
7556}
7557
7558int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7559{
c47ada30 7560 struct fxregs_state *fxsave =
7366ed77 7561 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7562
d0752060
HB		 7563 memcpy(fxsave->st_space, fpu->fpr, 128);
7564 fxsave->cwd = fpu->fcw;
7565 fxsave->swd = fpu->fsw;
7566 fxsave->twd = fpu->ftwx;
7567 fxsave->fop = fpu->last_opcode;
7568 fxsave->rip = fpu->last_ip;
7569 fxsave->rdp = fpu->last_dp;
7570 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7571
d0752060
HB		 7572 return 0;
7573}
7574
0ee6a517 7575static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7576{
bf935b0b 7577 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7578 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7579 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7580 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7581
2acf923e
DC		 7582 /*
7583 * Ensure guest xcr0 is valid for loading
7584 */
d91cab78 7585 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7586
ad312c7c 7587 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7588}
d0752060
HB		 7589
7590void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7591{
2608d7a1 7592 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7593 return;
7594
2acf923e
DC		 7595 /*
7596 * Restore all possible states in the guest,
7597 * and assume host would use all available bits.
7598 * Guest xcr0 would be loaded later.
7599 */
d0752060 7600 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7601 __kernel_fpu_begin();
003e2e8b 7602 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7603 trace_kvm_fpu(1);
d0752060 7604}
d0752060
HB		 7605
7606void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7607{
3d42de25 7608 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7609 return;
7610
7611 vcpu->guest_fpu_loaded = 0;
4f836347 7612 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7613 __kernel_fpu_end();
f096ed85 7614 ++vcpu->stat.fpu_reload;
0c04851c 7615 trace_kvm_fpu(0);
d0752060 7616}
e9b11c17
ZX		 7617
7618void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7619{
bd768e14
IY		 7620 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7621
12f9a48f 7622 kvmclock_reset(vcpu);
7f1ea208 7623
e9b11c17 7624 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7625 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7626}
7627
7628struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7629 unsigned int id)
7630{
c447e76b
LL		 7631 struct kvm_vcpu *vcpu;
7632
6755bae8
ZA		 7633 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7634 printk_once(KERN_WARNING
7635 "kvm: SMP vm created on host with unstable TSC; "
7636 "guest TSC will not be reliable\n");
c447e76b
LL		 7637
7638 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7639
c447e76b 7640 return vcpu;
26e5215f 7641}
e9b11c17 7642
26e5215f
AK		 7643int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7644{
7645 int r;
e9b11c17 7646
19efffa2 7647 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7648 r = vcpu_load(vcpu);
7649 if (r)
7650 return r;
d28bc9dd 7651 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7652 kvm_mmu_setup(vcpu);
e9b11c17 7653 vcpu_put(vcpu);
26e5215f 7654 return r;
e9b11c17
ZX		 7655}
7656
31928aa5 7657void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7658{
8fe8ab46 7659 struct msr_data msr;
332967a3 7660 struct kvm *kvm = vcpu->kvm;
42897d86 7661
31928aa5
DD		 7662 if (vcpu_load(vcpu))
7663 return;
8fe8ab46
WA		 7664 msr.data = 0x0;
7665 msr.index = MSR_IA32_TSC;
7666 msr.host_initiated = true;
7667 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7668 vcpu_put(vcpu);
7669
630994b3
MT		 7670 if (!kvmclock_periodic_sync)
7671 return;
7672
332967a3
AJ		 7673 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7674 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7675}
7676
d40ccc62 7677void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7678{
9fc77441 7679 int r;
344d9588
GN		 7680 vcpu->arch.apf.msr_val = 0;
7681
9fc77441
MT		 7682 r = vcpu_load(vcpu);
7683 BUG_ON(r);
e9b11c17
ZX		 7684 kvm_mmu_unload(vcpu);
7685 vcpu_put(vcpu);
7686
7687 kvm_x86_ops->vcpu_free(vcpu);
7688}
7689
d28bc9dd 7690void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7691{
e69fab5d
PB		 7692 vcpu->arch.hflags = 0;
7693
c43203ca 7694 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7695 atomic_set(&vcpu->arch.nmi_queued, 0);
7696 vcpu->arch.nmi_pending = 0;
448fa4a9 7697 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7698 kvm_clear_interrupt_queue(vcpu);
7699 kvm_clear_exception_queue(vcpu);
448fa4a9 7700
42dbaa5a 7701 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7702 kvm_update_dr0123(vcpu);
6f43ed01 7703 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7704 kvm_update_dr6(vcpu);
42dbaa5a 7705 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7706 kvm_update_dr7(vcpu);
42dbaa5a 7707
1119022c
NA		 7708 vcpu->arch.cr2 = 0;
7709
3842d135 7710 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7711 vcpu->arch.apf.msr_val = 0;
c9aaa895 7712 vcpu->arch.st.msr_val = 0;
3842d135 7713
12f9a48f
GC		 7714 kvmclock_reset(vcpu);
7715
af585b92
GN		 7716 kvm_clear_async_pf_completion_queue(vcpu);
7717 kvm_async_pf_hash_reset(vcpu);
7718 vcpu->arch.apf.halted = false;
3842d135 7719
64d60670 7720 if (!init_event) {
d28bc9dd 7721 kvm_pmu_reset(vcpu);
64d60670 7722 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7723
7724 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7725 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7726 }
f5132b01 7727
66f7b72e
JS		 7728 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7729 vcpu->arch.regs_avail = ~0;
7730 vcpu->arch.regs_dirty = ~0;
7731
d28bc9dd 7732 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7733}
7734
2b4a273b 7735void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7736{
7737 struct kvm_segment cs;
7738
7739 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7740 cs.selector = vector << 8;
7741 cs.base = vector << 12;
7742 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7743 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7744}
7745
13a34e06 7746int kvm_arch_hardware_enable(void)
e9b11c17 7747{
ca84d1a2
ZA		 7748 struct kvm *kvm;
7749 struct kvm_vcpu *vcpu;
7750 int i;
0dd6a6ed
ZA		 7751 int ret;
7752 u64 local_tsc;
7753 u64 max_tsc = 0;
7754 bool stable, backwards_tsc = false;
18863bdd
AK		 7755
7756 kvm_shared_msr_cpu_online();
13a34e06 7757 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7758 if (ret != 0)
7759 return ret;
7760
4ea1636b 7761 local_tsc = rdtsc();
0dd6a6ed
ZA		 7762 stable = !check_tsc_unstable();
7763 list_for_each_entry(kvm, &vm_list, vm_list) {
7764 kvm_for_each_vcpu(i, vcpu, kvm) {
7765 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7766 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7767 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7768 backwards_tsc = true;
7769 if (vcpu->arch.last_host_tsc > max_tsc)
7770 max_tsc = vcpu->arch.last_host_tsc;
7771 }
7772 }
7773 }
7774
7775 /*
7776 * Sometimes, even reliable TSCs go backwards. This happens on
7777 * platforms that reset TSC during suspend or hibernate actions, but
7778 * maintain synchronization. We must compensate. Fortunately, we can
7779 * detect that condition here, which happens early in CPU bringup,
7780 * before any KVM threads can be running. Unfortunately, we can't
7781 * bring the TSCs fully up to date with real time, as we aren't yet far
7782 * enough into CPU bringup that we know how much real time has actually
108b249c 7783 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7784 * variables that haven't been updated yet.
7785 *
7786 * So we simply find the maximum observed TSC above, then record the
7787 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7788 * the adjustment will be applied. Note that we accumulate
7789 * adjustments, in case multiple suspend cycles happen before some VCPU
7790 * gets a chance to run again. In the event that no KVM threads get a
7791 * chance to run, we will miss the entire elapsed period, as we'll have
7792 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7793 * loose cycle time. This isn't too big a deal, since the loss will be
7794 * uniform across all VCPUs (not to mention the scenario is extremely
7795 * unlikely). It is possible that a second hibernate recovery happens
7796 * much faster than a first, causing the observed TSC here to be
7797 * smaller; this would require additional padding adjustment, which is
7798 * why we set last_host_tsc to the local tsc observed here.
7799 *
7800 * N.B. - this code below runs only on platforms with reliable TSC,
7801 * as that is the only way backwards_tsc is set above. Also note
7802 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7803 * have the same delta_cyc adjustment applied if backwards_tsc
7804 * is detected. Note further, this adjustment is only done once,
7805 * as we reset last_host_tsc on all VCPUs to stop this from being
7806 * called multiple times (one for each physical CPU bringup).
7807 *
4a969980 7808 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7809 * will be compensated by the logic in vcpu_load, which sets the TSC to
7810 * catchup mode. This will catchup all VCPUs to real time, but cannot
7811 * guarantee that they stay in perfect synchronization.
7812 */
7813 if (backwards_tsc) {
7814 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7815 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7816 list_for_each_entry(kvm, &vm_list, vm_list) {
7817 kvm_for_each_vcpu(i, vcpu, kvm) {
7818 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7819 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7820 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7821 }
7822
7823 /*
7824 * We have to disable TSC offset matching.. if you were
7825 * booting a VM while issuing an S4 host suspend....
7826 * you may have some problem. Solving this issue is
7827 * left as an exercise to the reader.
7828 */
7829 kvm->arch.last_tsc_nsec = 0;
7830 kvm->arch.last_tsc_write = 0;
7831 }
7832
7833 }
7834 return 0;
e9b11c17
ZX		 7835}
7836
13a34e06 7837void kvm_arch_hardware_disable(void)
e9b11c17 7838{
13a34e06
RK		 7839 kvm_x86_ops->hardware_disable();
7840 drop_user_return_notifiers();
e9b11c17
ZX		 7841}
7842
7843int kvm_arch_hardware_setup(void)
7844{
9e9c3fe4
NA		 7845 int r;
7846
7847 r = kvm_x86_ops->hardware_setup();
7848 if (r != 0)
7849 return r;
7850
35181e86
HZ		 7851 if (kvm_has_tsc_control) {
7852 /*
7853 * Make sure the user can only configure tsc_khz values that
7854 * fit into a signed integer.
7855 * A min value is not calculated needed because it will always
7856 * be 1 on all machines.
7857 */
7858 u64 max = min(0x7fffffffULL,
7859 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7860 kvm_max_guest_tsc_khz = max;
7861
ad721883 7862 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7863 }
ad721883 7864
9e9c3fe4
NA		 7865 kvm_init_msr_list();
7866 return 0;
e9b11c17
ZX		 7867}
7868
7869void kvm_arch_hardware_unsetup(void)
7870{
7871 kvm_x86_ops->hardware_unsetup();
7872}
7873
7874void kvm_arch_check_processor_compat(void *rtn)
7875{
7876 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7877}
7878
7879bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7880{
7881 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7882}
7883EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7884
7885bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7886{
7887 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7888}
7889
54e9818f 7890struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7891EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7892
e9b11c17
ZX		 7893int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7894{
7895 struct page *page;
7896 struct kvm *kvm;
7897 int r;
7898
7899 BUG_ON(vcpu->kvm == NULL);
7900 kvm = vcpu->kvm;
7901
d62caabb 7902 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7903 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7904 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7905 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7906 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7907 else
a4535290 7908 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7909
7910 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7911 if (!page) {
7912 r = -ENOMEM;
7913 goto fail;
7914 }
ad312c7c 7915 vcpu->arch.pio_data = page_address(page);
e9b11c17 7916
cc578287 7917 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7918
e9b11c17
ZX		 7919 r = kvm_mmu_create(vcpu);
7920 if (r < 0)
7921 goto fail_free_pio_data;
7922
7923 if (irqchip_in_kernel(kvm)) {
7924 r = kvm_create_lapic(vcpu);
7925 if (r < 0)
7926 goto fail_mmu_destroy;
54e9818f
GN		 7927 } else
7928 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7929
890ca9ae
HY		 7930 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7931 GFP_KERNEL);
7932 if (!vcpu->arch.mce_banks) {
7933 r = -ENOMEM;
443c39bc 7934 goto fail_free_lapic;
890ca9ae
HY		 7935 }
7936 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7937
f1797359
WY		 7938 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7939 r = -ENOMEM;
f5f48ee1 7940 goto fail_free_mce_banks;
f1797359 7941 }
f5f48ee1 7942
0ee6a517 7943 fx_init(vcpu);
66f7b72e 7944
ba904635 7945 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7946 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7947
7948 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7949 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7950
5a4f55cd
EK		 7951 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7952
74545705
RK		 7953 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7954
af585b92 7955 kvm_async_pf_hash_reset(vcpu);
f5132b01 7956 kvm_pmu_init(vcpu);
af585b92 7957
1c1a9ce9
SR		 7958 vcpu->arch.pending_external_vector = -1;
7959
5c919412
AS		 7960 kvm_hv_vcpu_init(vcpu);
7961
e9b11c17 7962 return 0;
0ee6a517 7963
f5f48ee1
SY		 7964fail_free_mce_banks:
7965 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7966fail_free_lapic:
7967 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7968fail_mmu_destroy:
7969 kvm_mmu_destroy(vcpu);
7970fail_free_pio_data:
ad312c7c 7971 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7972fail:
7973 return r;
7974}
7975
7976void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7977{
f656ce01
MT		 7978 int idx;
7979
1f4b34f8 7980 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7981 kvm_pmu_destroy(vcpu);
36cb93fd 7982 kfree(vcpu->arch.mce_banks);
e9b11c17 7983 kvm_free_lapic(vcpu);
f656ce01 7984 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7985 kvm_mmu_destroy(vcpu);
f656ce01 7986 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7987 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7988 if (!lapic_in_kernel(vcpu))
54e9818f 7989 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7990}
d19a9cd2 7991
e790d9ef
RK		 7992void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7993{
ae97a3b8 7994 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7995}
7996
e08b9637 7997int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7998{
e08b9637
CO		 7999 if (type)
8000 return -EINVAL;
8001
6ef768fa 8002 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8003 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8004 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8005 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8006 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8007
5550af4d
SY		 8008 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8009 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8010 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8011 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8012 &kvm->arch.irq_sources_bitmap);
5550af4d 8013
038f8c11 8014 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8015 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8016 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8017 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8018
108b249c 8019 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8020 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8021
7e44e449 8022 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8023 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8024
0eb05bf2 8025 kvm_page_track_init(kvm);
13d268ca 8026 kvm_mmu_init_vm(kvm);
0eb05bf2 8027
03543133
SS		 8028 if (kvm_x86_ops->vm_init)
8029 return kvm_x86_ops->vm_init(kvm);
8030
d89f5eff 8031 return 0;
d19a9cd2
ZX		 8032}
8033
8034static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8035{
9fc77441
MT		 8036 int r;
8037 r = vcpu_load(vcpu);
8038 BUG_ON(r);
d19a9cd2
ZX		 8039 kvm_mmu_unload(vcpu);
8040 vcpu_put(vcpu);
8041}
8042
8043static void kvm_free_vcpus(struct kvm *kvm)
8044{
8045 unsigned int i;
988a2cae 8046 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8047
8048 /*
8049 * Unpin any mmu pages first.
8050 */
af585b92
GN		 8051 kvm_for_each_vcpu(i, vcpu, kvm) {
8052 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8053 kvm_unload_vcpu_mmu(vcpu);
af585b92 8054 }
988a2cae
GN		 8055 kvm_for_each_vcpu(i, vcpu, kvm)
8056 kvm_arch_vcpu_free(vcpu);
8057
8058 mutex_lock(&kvm->lock);
8059 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8060 kvm->vcpus[i] = NULL;
d19a9cd2 8061
988a2cae
GN		 8062 atomic_set(&kvm->online_vcpus, 0);
8063 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8064}
8065
ad8ba2cd
SY		 8066void kvm_arch_sync_events(struct kvm *kvm)
8067{
332967a3 8068 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8069 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8070 kvm_free_pit(kvm);
ad8ba2cd
SY		 8071}
8072
1d8007bd 8073int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8074{
8075 int i, r;
25188b99 8076 unsigned long hva;
f0d648bd
PB		 8077 struct kvm_memslots *slots = kvm_memslots(kvm);
8078 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8079
8080 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8081 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8082 return -EINVAL;
9da0e4d5 8083
f0d648bd
PB		 8084 slot = id_to_memslot(slots, id);
8085 if (size) {
b21629da 8086 if (slot->npages)
f0d648bd
PB		 8087 return -EEXIST;
8088
8089 /*
8090 * MAP_SHARED to prevent internal slot pages from being moved
8091 * by fork()/COW.
8092 */
8093 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8094 MAP_SHARED | MAP_ANONYMOUS, 0);
8095 if (IS_ERR((void *)hva))
8096 return PTR_ERR((void *)hva);
8097 } else {
8098 if (!slot->npages)
8099 return 0;
8100
8101 hva = 0;
8102 }
8103
8104 old = *slot;
9da0e4d5 8105 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8106 struct kvm_userspace_memory_region m;
9da0e4d5 8107
1d8007bd
PB		 8108 m.slot = id | (i << 16);
8109 m.flags = 0;
8110 m.guest_phys_addr = gpa;
f0d648bd 8111 m.userspace_addr = hva;
1d8007bd 8112 m.memory_size = size;
9da0e4d5
PB		 8113 r = __kvm_set_memory_region(kvm, &m);
8114 if (r < 0)
8115 return r;
8116 }
8117
f0d648bd
PB		 8118 if (!size) {
8119 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8120 WARN_ON(r < 0);
8121 }
8122
9da0e4d5
PB		 8123 return 0;
8124}
8125EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8126
1d8007bd 8127int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8128{
8129 int r;
8130
8131 mutex_lock(&kvm->slots_lock);
1d8007bd 8132 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8133 mutex_unlock(&kvm->slots_lock);
8134
8135 return r;
8136}
8137EXPORT_SYMBOL_GPL(x86_set_memory_region);
8138
d19a9cd2
ZX		 8139void kvm_arch_destroy_vm(struct kvm *kvm)
8140{
27469d29
AH		 8141 if (current->mm == kvm->mm) {
8142 /*
8143 * Free memory regions allocated on behalf of userspace,
8144 * unless the the memory map has changed due to process exit
8145 * or fd copying.
8146 */
1d8007bd
PB		 8147 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8148 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8149 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8150 }
03543133
SS		 8151 if (kvm_x86_ops->vm_destroy)
8152 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8153 kvm_pic_destroy(kvm);
8154 kvm_ioapic_destroy(kvm);
d19a9cd2 8155 kvm_free_vcpus(kvm);
af1bae54 8156 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8157 kvm_mmu_uninit_vm(kvm);
2beb6dad 8158 kvm_page_track_cleanup(kvm);
d19a9cd2 8159}
0de10343 8160
5587027c 8161void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8162 struct kvm_memory_slot *dont)
8163{
8164 int i;
8165
d89cc617
TY		 8166 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8167 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8168 kvfree(free->arch.rmap[i]);
d89cc617 8169 free->arch.rmap[i] = NULL;
77d11309 8170 }
d89cc617
TY		 8171 if (i == 0)
8172 continue;
8173
8174 if (!dont || free->arch.lpage_info[i - 1] !=
8175 dont->arch.lpage_info[i - 1]) {
548ef284 8176 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8177 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8178 }
8179 }
21ebbeda
XG		 8180
8181 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8182}
8183
5587027c
AK		 8184int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8185 unsigned long npages)
db3fe4eb
TY		 8186{
8187 int i;
8188
d89cc617 8189 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8190 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8191 unsigned long ugfn;
8192 int lpages;
d89cc617 8193 int level = i + 1;
db3fe4eb
TY		 8194
8195 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8196 slot->base_gfn, level) + 1;
8197
d89cc617
TY		 8198 slot->arch.rmap[i] =
8199 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8200 if (!slot->arch.rmap[i])
77d11309 8201 goto out_free;
d89cc617
TY		 8202 if (i == 0)
8203 continue;
77d11309 8204
92f94f1e
XG		 8205 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8206 if (!linfo)
db3fe4eb
TY		 8207 goto out_free;
8208
92f94f1e
XG		 8209 slot->arch.lpage_info[i - 1] = linfo;
8210
db3fe4eb 8211 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8212 linfo[0].disallow_lpage = 1;
db3fe4eb 8213 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8214 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8215 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8216 /*
8217 * If the gfn and userspace address are not aligned wrt each
8218 * other, or if explicitly asked to, disable large page
8219 * support for this slot
8220 */
8221 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8222 !kvm_largepages_enabled()) {
8223 unsigned long j;
8224
8225 for (j = 0; j < lpages; ++j)
92f94f1e 8226 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8227 }
8228 }
8229
21ebbeda
XG		 8230 if (kvm_page_track_create_memslot(slot, npages))
8231 goto out_free;
8232
db3fe4eb
TY		 8233 return 0;
8234
8235out_free:
d89cc617 8236 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8237 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8238 slot->arch.rmap[i] = NULL;
8239 if (i == 0)
8240 continue;
8241
548ef284 8242 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8243 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8244 }
8245 return -ENOMEM;
8246}
8247
15f46015 8248void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8249{
e6dff7d1
TY		 8250 /*
8251 * memslots->generation has been incremented.
8252 * mmio generation may have reached its maximum value.
8253 */
54bf36aa 8254 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8255}
8256
f7784b8e
MT		 8257int kvm_arch_prepare_memory_region(struct kvm *kvm,
8258 struct kvm_memory_slot *memslot,
09170a49 8259 const struct kvm_userspace_memory_region *mem,
7b6195a9 8260 enum kvm_mr_change change)
0de10343 8261{
f7784b8e
MT		 8262 return 0;
8263}
8264
88178fd4
KH		 8265static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8266 struct kvm_memory_slot *new)
8267{
8268 /* Still write protect RO slot */
8269 if (new->flags & KVM_MEM_READONLY) {
8270 kvm_mmu_slot_remove_write_access(kvm, new);
8271 return;
8272 }
8273
8274 /*
8275 * Call kvm_x86_ops dirty logging hooks when they are valid.
8276 *
8277 * kvm_x86_ops->slot_disable_log_dirty is called when:
8278 *
8279 * - KVM_MR_CREATE with dirty logging is disabled
8280 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8281 *
8282 * The reason is, in case of PML, we need to set D-bit for any slots
8283 * with dirty logging disabled in order to eliminate unnecessary GPA
8284 * logging in PML buffer (and potential PML buffer full VMEXT). This
8285 * guarantees leaving PML enabled during guest's lifetime won't have
8286 * any additonal overhead from PML when guest is running with dirty
8287 * logging disabled for memory slots.
8288 *
8289 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8290 * to dirty logging mode.
8291 *
8292 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8293 *
8294 * In case of write protect:
8295 *
8296 * Write protect all pages for dirty logging.
8297 *
8298 * All the sptes including the large sptes which point to this
8299 * slot are set to readonly. We can not create any new large
8300 * spte on this slot until the end of the logging.
8301 *
8302 * See the comments in fast_page_fault().
8303 */
8304 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8305 if (kvm_x86_ops->slot_enable_log_dirty)
8306 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8307 else
8308 kvm_mmu_slot_remove_write_access(kvm, new);
8309 } else {
8310 if (kvm_x86_ops->slot_disable_log_dirty)
8311 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8312 }
8313}
8314
f7784b8e 8315void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8316 const struct kvm_userspace_memory_region *mem,
8482644a 8317 const struct kvm_memory_slot *old,
f36f3f28 8318 const struct kvm_memory_slot *new,
8482644a 8319 enum kvm_mr_change change)
f7784b8e 8320{
8482644a 8321 int nr_mmu_pages = 0;
f7784b8e 8322
48c0e4e9
XG		 8323 if (!kvm->arch.n_requested_mmu_pages)
8324 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8325
48c0e4e9 8326 if (nr_mmu_pages)
0de10343 8327 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8328
3ea3b7fa
WL		 8329 /*
8330 * Dirty logging tracks sptes in 4k granularity, meaning that large
8331 * sptes have to be split. If live migration is successful, the guest
8332 * in the source machine will be destroyed and large sptes will be
8333 * created in the destination. However, if the guest continues to run
8334 * in the source machine (for example if live migration fails), small
8335 * sptes will remain around and cause bad performance.
8336 *
8337 * Scan sptes if dirty logging has been stopped, dropping those
8338 * which can be collapsed into a single large-page spte. Later
8339 * page faults will create the large-page sptes.
8340 */
8341 if ((change != KVM_MR_DELETE) &&
8342 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8343 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8344 kvm_mmu_zap_collapsible_sptes(kvm, new);
8345
c972f3b1 8346 /*
88178fd4 8347 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8348 *
88178fd4
KH		 8349 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8350 * been zapped so no dirty logging staff is needed for old slot. For
8351 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8352 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8353 *
8354 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8355 */
88178fd4 8356 if (change != KVM_MR_DELETE)
f36f3f28 8357 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8358}
1d737c8a 8359
2df72e9b 8360void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8361{
6ca18b69 8362 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8363}
8364
2df72e9b
MT		 8365void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8366 struct kvm_memory_slot *slot)
8367{
ae7cd873 8368 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8369}
8370
5d9bc648
PB		 8371static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8372{
8373 if (!list_empty_careful(&vcpu->async_pf.done))
8374 return true;
8375
8376 if (kvm_apic_has_events(vcpu))
8377 return true;
8378
8379 if (vcpu->arch.pv.pv_unhalted)
8380 return true;
8381
8382 if (atomic_read(&vcpu->arch.nmi_queued))
8383 return true;
8384
73917739
PB		 8385 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8386 return true;
8387
5d9bc648
PB		 8388 if (kvm_arch_interrupt_allowed(vcpu) &&
8389 kvm_cpu_has_interrupt(vcpu))
8390 return true;
8391
1f4b34f8
AS		 8392 if (kvm_hv_has_stimer_pending(vcpu))
8393 return true;
8394
5d9bc648
PB		 8395 return false;
8396}
8397
1d737c8a
ZX		 8398int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8399{
5d9bc648 8400 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8401}
5736199a 8402
b6d33834 8403int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8404{
b6d33834 8405 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8406}
78646121
GN		 8407
8408int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8409{
8410 return kvm_x86_ops->interrupt_allowed(vcpu);
8411}
229456fc 8412
82b32774 8413unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8414{
82b32774
NA		 8415 if (is_64_bit_mode(vcpu))
8416 return kvm_rip_read(vcpu);
8417 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8418 kvm_rip_read(vcpu));
8419}
8420EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8421
82b32774
NA		 8422bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8423{
8424 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8425}
8426EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8427
94fe45da
JK		 8428unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8429{
8430 unsigned long rflags;
8431
8432 rflags = kvm_x86_ops->get_rflags(vcpu);
8433 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8434 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8435 return rflags;
8436}
8437EXPORT_SYMBOL_GPL(kvm_get_rflags);
8438
6addfc42 8439static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8440{
8441 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8442 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8443 rflags |= X86_EFLAGS_TF;
94fe45da 8444 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8445}
8446
8447void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8448{
8449 __kvm_set_rflags(vcpu, rflags);
3842d135 8450 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8451}
8452EXPORT_SYMBOL_GPL(kvm_set_rflags);
8453
56028d08
GN		 8454void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8455{
8456 int r;
8457
fb67e14f 8458 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8459 work->wakeup_all)
56028d08
GN		 8460 return;
8461
8462 r = kvm_mmu_reload(vcpu);
8463 if (unlikely(r))
8464 return;
8465
fb67e14f
XG		 8466 if (!vcpu->arch.mmu.direct_map &&
8467 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8468 return;
8469
56028d08
GN		 8470 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8471}
8472
af585b92
GN		 8473static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8474{
8475 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8476}
8477
8478static inline u32 kvm_async_pf_next_probe(u32 key)
8479{
8480 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8481}
8482
8483static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8484{
8485 u32 key = kvm_async_pf_hash_fn(gfn);
8486
8487 while (vcpu->arch.apf.gfns[key] != ~0)
8488 key = kvm_async_pf_next_probe(key);
8489
8490 vcpu->arch.apf.gfns[key] = gfn;
8491}
8492
8493static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8494{
8495 int i;
8496 u32 key = kvm_async_pf_hash_fn(gfn);
8497
8498 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8499 (vcpu->arch.apf.gfns[key] != gfn &&
8500 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8501 key = kvm_async_pf_next_probe(key);
8502
8503 return key;
8504}
8505
8506bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8507{
8508 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8509}
8510
8511static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8512{
8513 u32 i, j, k;
8514
8515 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8516 while (true) {
8517 vcpu->arch.apf.gfns[i] = ~0;
8518 do {
8519 j = kvm_async_pf_next_probe(j);
8520 if (vcpu->arch.apf.gfns[j] == ~0)
8521 return;
8522 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8523 /*
8524 * k lies cyclically in ]i,j]
8525 * | i.k.j |
8526 * |....j i.k.| or |.k..j i...|
8527 */
8528 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8529 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8530 i = j;
8531 }
8532}
8533
7c90705b
GN		 8534static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8535{
bbd64115
CL		 8536 return kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.apf.data, &val,
8537 sizeof(val));
7c90705b
GN		 8538}
8539
af585b92
GN		 8540void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8541 struct kvm_async_pf *work)
8542{
6389ee94
AK		 8543 struct x86_exception fault;
8544
7c90705b 8545 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8546 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8547
8548 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8549 (vcpu->arch.apf.send_user_only &&
8550 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8551 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8552 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8553 fault.vector = PF_VECTOR;
8554 fault.error_code_valid = true;
8555 fault.error_code = 0;
8556 fault.nested_page_fault = false;
8557 fault.address = work->arch.token;
8558 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8559 }
af585b92
GN		 8560}
8561
8562void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8563 struct kvm_async_pf *work)
8564{
6389ee94
AK		 8565 struct x86_exception fault;
8566
f2e10669 8567 if (work->wakeup_all)
7c90705b
GN		 8568 work->arch.token = ~0; /* broadcast wakeup */
8569 else
8570 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8571 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8572
8573 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8574 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8575 fault.vector = PF_VECTOR;
8576 fault.error_code_valid = true;
8577 fault.error_code = 0;
8578 fault.nested_page_fault = false;
8579 fault.address = work->arch.token;
8580 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8581 }
e6d53e3b 8582 vcpu->arch.apf.halted = false;
a4fa1635 8583 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8584}
8585
8586bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8587{
8588 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8589 return true;
8590 else
8591 return !kvm_event_needs_reinjection(vcpu) &&
8592 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8593}
8594
5544eb9b
PB		 8595void kvm_arch_start_assignment(struct kvm *kvm)
8596{
8597 atomic_inc(&kvm->arch.assigned_device_count);
8598}
8599EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8600
8601void kvm_arch_end_assignment(struct kvm *kvm)
8602{
8603 atomic_dec(&kvm->arch.assigned_device_count);
8604}
8605EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8606
8607bool kvm_arch_has_assigned_device(struct kvm *kvm)
8608{
8609 return atomic_read(&kvm->arch.assigned_device_count);
8610}
8611EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8612
e0f0bbc5
AW		 8613void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8614{
8615 atomic_inc(&kvm->arch.noncoherent_dma_count);
8616}
8617EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8618
8619void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8620{
8621 atomic_dec(&kvm->arch.noncoherent_dma_count);
8622}
8623EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8624
8625bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8626{
8627 return atomic_read(&kvm->arch.noncoherent_dma_count);
8628}
8629EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8630
14717e20
AW		 8631bool kvm_arch_has_irq_bypass(void)
8632{
8633 return kvm_x86_ops->update_pi_irte != NULL;
8634}
8635
87276880
FW		 8636int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8637 struct irq_bypass_producer *prod)
8638{
8639 struct kvm_kernel_irqfd *irqfd =
8640 container_of(cons, struct kvm_kernel_irqfd, consumer);
8641
14717e20 8642 irqfd->producer = prod;
87276880 8643
14717e20
AW		 8644 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8645 prod->irq, irqfd->gsi, 1);
87276880
FW		 8646}
8647
8648void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8649 struct irq_bypass_producer *prod)
8650{
8651 int ret;
8652 struct kvm_kernel_irqfd *irqfd =
8653 container_of(cons, struct kvm_kernel_irqfd, consumer);
8654
87276880
FW		 8655 WARN_ON(irqfd->producer != prod);
8656 irqfd->producer = NULL;
8657
8658 /*
8659 * When producer of consumer is unregistered, we change back to
8660 * remapped mode, so we can re-use the current implementation
bb3541f1 8661 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8662 * int this case doesn't want to receive the interrupts.
8663 */
8664 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8665 if (ret)
8666 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8667 " fails: %d\n", irqfd->consumer.token, ret);
8668}
8669
8670int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8671 uint32_t guest_irq, bool set)
8672{
8673 if (!kvm_x86_ops->update_pi_irte)
8674 return -EINVAL;
8675
8676 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8677}
8678
52004014
FW		 8679bool kvm_vector_hashing_enabled(void)
8680{
8681 return vector_hashing;
8682}
8683EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8684
229456fc 8685EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8686EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8687EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8689EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8691EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8692EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8693EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8694EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8695EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8696EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8697EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8698EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8699EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8700EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8701EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8702EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8703EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)