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KVM: x86: pass kvm_vcpu to kvm_read_guest_virt and kvm_write_guest_virt_system
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 198 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
199 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
200 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
201 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
202 { "mmu_flooded", VM_STAT(mmu_flooded) },
203 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 204 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 205 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 206 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 207 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 208 { "max_mmu_page_hash_collisions",
209 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 210 { NULL }
211};
212
2acf923e
DC		 213u64 __read_mostly host_xcr0;
214
b6785def 215static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 216
af585b92
GN		 217static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
218{
219 int i;
220 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
221 vcpu->arch.apf.gfns[i] = ~0;
222}
223
18863bdd
AK		 224static void kvm_on_user_return(struct user_return_notifier *urn)
225{
226 unsigned slot;
18863bdd
AK		 227 struct kvm_shared_msrs *locals
228 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 229 struct kvm_shared_msr_values *values;
1650b4eb
IA		 230 unsigned long flags;
231
232 /*
233 * Disabling irqs at this point since the following code could be
234 * interrupted and executed through kvm_arch_hardware_disable()
235 */
236 local_irq_save(flags);
237 if (locals->registered) {
238 locals->registered = false;
239 user_return_notifier_unregister(urn);
240 }
241 local_irq_restore(flags);
18863bdd 242 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 243 values = &locals->values[slot];
244 if (values->host != values->curr) {
245 wrmsrl(shared_msrs_global.msrs[slot], values->host);
246 values->curr = values->host;
18863bdd
AK		 247 }
248 }
18863bdd
AK		 249}
250
2bf78fa7 251static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 252{
18863bdd 253 u64 value;
013f6a5d
MT		 254 unsigned int cpu = smp_processor_id();
255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 256
2bf78fa7
SY		 257 /* only read, and nobody should modify it at this time,
258 * so don't need lock */
259 if (slot >= shared_msrs_global.nr) {
260 printk(KERN_ERR "kvm: invalid MSR slot!");
261 return;
262 }
263 rdmsrl_safe(msr, &value);
264 smsr->values[slot].host = value;
265 smsr->values[slot].curr = value;
266}
267
268void kvm_define_shared_msr(unsigned slot, u32 msr)
269{
0123be42 270 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 271 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 272 if (slot >= shared_msrs_global.nr)
273 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 274}
275EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
276
277static void kvm_shared_msr_cpu_online(void)
278{
279 unsigned i;
18863bdd
AK		 280
281 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 282 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 283}
284
8b3c3104 285int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 286{
013f6a5d
MT		 287 unsigned int cpu = smp_processor_id();
288 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 289 int err;
18863bdd 290
2bf78fa7 291 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 292 return 0;
2bf78fa7 293 smsr->values[slot].curr = value;
8b3c3104
AH		 294 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
295 if (err)
296 return 1;
297
18863bdd
AK		 298 if (!smsr->registered) {
299 smsr->urn.on_user_return = kvm_on_user_return;
300 user_return_notifier_register(&smsr->urn);
301 smsr->registered = true;
302 }
8b3c3104 303 return 0;
18863bdd
AK		 304}
305EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
306
13a34e06 307static void drop_user_return_notifiers(void)
3548bab5 308{
013f6a5d
MT		 309 unsigned int cpu = smp_processor_id();
310 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 311
312 if (smsr->registered)
313 kvm_on_user_return(&smsr->urn);
314}
315
6866b83e
CO		 316u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
317{
8a5a87d9 318 return vcpu->arch.apic_base;
6866b83e
CO		 319}
320EXPORT_SYMBOL_GPL(kvm_get_apic_base);
321
58871649
JM		 322enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
323{
324 return kvm_apic_mode(kvm_get_apic_base(vcpu));
325}
326EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
327
58cb628d
JK		 328int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
329{
58871649
JM		 330 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
331 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 332 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
333 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 334
58871649 335 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 336 return 1;
58871649
JM		 337 if (!msr_info->host_initiated) {
338 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
339 return 1;
340 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
341 return 1;
342 }
58cb628d
JK		 343
344 kvm_lapic_set_base(vcpu, msr_info->data);
345 return 0;
6866b83e
CO		 346}
347EXPORT_SYMBOL_GPL(kvm_set_apic_base);
348
2605fc21 349asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 350{
351 /* Fault while not rebooting. We want the trace. */
352 BUG();
353}
354EXPORT_SYMBOL_GPL(kvm_spurious_fault);
355
3fd28fce
ED		 356#define EXCPT_BENIGN 0
357#define EXCPT_CONTRIBUTORY 1
358#define EXCPT_PF 2
359
360static int exception_class(int vector)
361{
362 switch (vector) {
363 case PF_VECTOR:
364 return EXCPT_PF;
365 case DE_VECTOR:
366 case TS_VECTOR:
367 case NP_VECTOR:
368 case SS_VECTOR:
369 case GP_VECTOR:
370 return EXCPT_CONTRIBUTORY;
371 default:
372 break;
373 }
374 return EXCPT_BENIGN;
375}
376
d6e8c854
NA		 377#define EXCPT_FAULT 0
378#define EXCPT_TRAP 1
379#define EXCPT_ABORT 2
380#define EXCPT_INTERRUPT 3
381
382static int exception_type(int vector)
383{
384 unsigned int mask;
385
386 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
387 return EXCPT_INTERRUPT;
388
389 mask = 1 << vector;
390
391 /* #DB is trap, as instruction watchpoints are handled elsewhere */
392 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
393 return EXCPT_TRAP;
394
395 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
396 return EXCPT_ABORT;
397
398 /* Reserved exceptions will result in fault */
399 return EXCPT_FAULT;
400}
401
3fd28fce 402static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 403 unsigned nr, bool has_error, u32 error_code,
404 bool reinject)
3fd28fce
ED		 405{
406 u32 prev_nr;
407 int class1, class2;
408
3842d135
AK		 409 kvm_make_request(KVM_REQ_EVENT, vcpu);
410
664f8e26 411 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 412 queue:
3ffb2468
NA		 413 if (has_error && !is_protmode(vcpu))
414 has_error = false;
664f8e26
WL		 415 if (reinject) {
416 /*
417 * On vmentry, vcpu->arch.exception.pending is only
418 * true if an event injection was blocked by
419 * nested_run_pending. In that case, however,
420 * vcpu_enter_guest requests an immediate exit,
421 * and the guest shouldn't proceed far enough to
422 * need reinjection.
423 */
424 WARN_ON_ONCE(vcpu->arch.exception.pending);
425 vcpu->arch.exception.injected = true;
426 } else {
427 vcpu->arch.exception.pending = true;
428 vcpu->arch.exception.injected = false;
429 }
3fd28fce
ED		 430 vcpu->arch.exception.has_error_code = has_error;
431 vcpu->arch.exception.nr = nr;
432 vcpu->arch.exception.error_code = error_code;
433 return;
434 }
435
436 /* to check exception */
437 prev_nr = vcpu->arch.exception.nr;
438 if (prev_nr == DF_VECTOR) {
439 /* triple fault -> shutdown */
a8eeb04a 440 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 441 return;
442 }
443 class1 = exception_class(prev_nr);
444 class2 = exception_class(nr);
445 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
446 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 447 /*
448 * Generate double fault per SDM Table 5-5. Set
449 * exception.pending = true so that the double fault
450 * can trigger a nested vmexit.
451 */
3fd28fce 452 vcpu->arch.exception.pending = true;
664f8e26 453 vcpu->arch.exception.injected = false;
3fd28fce
ED		 454 vcpu->arch.exception.has_error_code = true;
455 vcpu->arch.exception.nr = DF_VECTOR;
456 vcpu->arch.exception.error_code = 0;
457 } else
458 /* replace previous exception with a new one in a hope
459 that instruction re-execution will regenerate lost
460 exception */
461 goto queue;
462}
463
298101da
AK		 464void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
465{
ce7ddec4 466 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 467}
468EXPORT_SYMBOL_GPL(kvm_queue_exception);
469
ce7ddec4
JR		 470void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
471{
472 kvm_multiple_exception(vcpu, nr, false, 0, true);
473}
474EXPORT_SYMBOL_GPL(kvm_requeue_exception);
475
6affcbed 476int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 477{
db8fcefa
AP		 478 if (err)
479 kvm_inject_gp(vcpu, 0);
480 else
6affcbed
KH		 481 return kvm_skip_emulated_instruction(vcpu);
482
483 return 1;
db8fcefa
AP		 484}
485EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 486
6389ee94 487void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 488{
489 ++vcpu->stat.pf_guest;
adfe20fb
WL		 490 vcpu->arch.exception.nested_apf =
491 is_guest_mode(vcpu) && fault->async_page_fault;
492 if (vcpu->arch.exception.nested_apf)
493 vcpu->arch.apf.nested_apf_token = fault->address;
494 else
495 vcpu->arch.cr2 = fault->address;
6389ee94 496 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 497}
27d6c865 498EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 499
ef54bcfe 500static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 501{
6389ee94
AK		 502 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
503 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 504 else
6389ee94 505 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 506
507 return fault->nested_page_fault;
d4f8cf66
JR		 508}
509
3419ffc8
SY		 510void kvm_inject_nmi(struct kvm_vcpu *vcpu)
511{
7460fb4a
AK		 512 atomic_inc(&vcpu->arch.nmi_queued);
513 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 514}
515EXPORT_SYMBOL_GPL(kvm_inject_nmi);
516
298101da
AK		 517void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
518{
ce7ddec4 519 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 520}
521EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
522
ce7ddec4
JR		 523void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
524{
525 kvm_multiple_exception(vcpu, nr, true, error_code, true);
526}
527EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
528
0a79b009
AK		 529/*
530 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
531 * a #GP and return false.
532 */
533bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 534{
0a79b009
AK		 535 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
536 return true;
537 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
538 return false;
298101da 539}
0a79b009 540EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 541
16f8a6f9
NA		 542bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
543{
544 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
545 return true;
546
547 kvm_queue_exception(vcpu, UD_VECTOR);
548 return false;
549}
550EXPORT_SYMBOL_GPL(kvm_require_dr);
551
ec92fe44
JR		 552/*
553 * This function will be used to read from the physical memory of the currently
54bf36aa 554 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 555 * can read from guest physical or from the guest's guest physical memory.
556 */
557int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
558 gfn_t ngfn, void *data, int offset, int len,
559 u32 access)
560{
54987b7a 561 struct x86_exception exception;
ec92fe44
JR		 562 gfn_t real_gfn;
563 gpa_t ngpa;
564
565 ngpa = gfn_to_gpa(ngfn);
54987b7a 566 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 567 if (real_gfn == UNMAPPED_GVA)
568 return -EFAULT;
569
570 real_gfn = gpa_to_gfn(real_gfn);
571
54bf36aa 572 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 573}
574EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
575
69b0049a 576static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 577 void *data, int offset, int len, u32 access)
578{
579 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
580 data, offset, len, access);
581}
582
a03490ed
CO		 583/*
584 * Load the pae pdptrs. Return true is they are all valid.
585 */
ff03a073 586int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 587{
588 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
589 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
590 int i;
591 int ret;
ff03a073 592 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 593
ff03a073
JR		 594 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
595 offset * sizeof(u64), sizeof(pdpte),
596 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 597 if (ret < 0) {
598 ret = 0;
599 goto out;
600 }
601 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 602 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 603 (pdpte[i] &
604 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 605 ret = 0;
606 goto out;
607 }
608 }
609 ret = 1;
610
ff03a073 611 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 612 __set_bit(VCPU_EXREG_PDPTR,
613 (unsigned long *)&vcpu->arch.regs_avail);
614 __set_bit(VCPU_EXREG_PDPTR,
615 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 616out:
a03490ed
CO		 617
618 return ret;
619}
cc4b6871 620EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 621
9ed38ffa 622bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 623{
ff03a073 624 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 625 bool changed = true;
3d06b8bf
JR		 626 int offset;
627 gfn_t gfn;
d835dfec
AK		 628 int r;
629
630 if (is_long_mode(vcpu) || !is_pae(vcpu))
631 return false;
632
6de4f3ad
AK		 633 if (!test_bit(VCPU_EXREG_PDPTR,
634 (unsigned long *)&vcpu->arch.regs_avail))
635 return true;
636
a512177e
PB		 637 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
638 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 639 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
640 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 641 if (r < 0)
642 goto out;
ff03a073 643 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 644out:
d835dfec
AK		 645
646 return changed;
647}
9ed38ffa 648EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 649
49a9b07e 650int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 651{
aad82703 652 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 653 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 654
f9a48e6a
AK		 655 cr0 |= X86_CR0_ET;
656
ab344828 657#ifdef CONFIG_X86_64
0f12244f
GN		 658 if (cr0 & 0xffffffff00000000UL)
659 return 1;
ab344828
GN		 660#endif
661
662 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 663
0f12244f
GN		 664 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
665 return 1;
a03490ed 666
0f12244f
GN		 667 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
668 return 1;
a03490ed
CO		 669
670 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
671#ifdef CONFIG_X86_64
f6801dff 672 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 673 int cs_db, cs_l;
674
0f12244f
GN		 675 if (!is_pae(vcpu))
676 return 1;
a03490ed 677 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 678 if (cs_l)
679 return 1;
a03490ed
CO		 680 } else
681#endif
ff03a073 682 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 683 kvm_read_cr3(vcpu)))
0f12244f 684 return 1;
a03490ed
CO		 685 }
686
ad756a16
MJ		 687 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
688 return 1;
689
a03490ed 690 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 691
d170c419 692 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 693 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 694 kvm_async_pf_hash_reset(vcpu);
695 }
e5f3f027 696
aad82703
SY		 697 if ((cr0 ^ old_cr0) & update_bits)
698 kvm_mmu_reset_context(vcpu);
b18d5431 699
879ae188
LE		 700 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
701 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
702 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 703 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
704
0f12244f
GN		 705 return 0;
706}
2d3ad1f4 707EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 708
2d3ad1f4 709void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 710{
49a9b07e 711 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 712}
2d3ad1f4 713EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 714
42bdf991
MT		 715static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
716{
717 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
718 !vcpu->guest_xcr0_loaded) {
719 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 720 if (vcpu->arch.xcr0 != host_xcr0)
721 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 722 vcpu->guest_xcr0_loaded = 1;
723 }
724}
725
726static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
727{
728 if (vcpu->guest_xcr0_loaded) {
729 if (vcpu->arch.xcr0 != host_xcr0)
730 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
731 vcpu->guest_xcr0_loaded = 0;
732 }
733}
734
69b0049a 735static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 736{
56c103ec
LJ		 737 u64 xcr0 = xcr;
738 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 739 u64 valid_bits;
2acf923e
DC		 740
741 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
742 if (index != XCR_XFEATURE_ENABLED_MASK)
743 return 1;
d91cab78 744 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 745 return 1;
d91cab78 746 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 747 return 1;
46c34cb0
PB		 748
749 /*
750 * Do not allow the guest to set bits that we do not support
751 * saving. However, xcr0 bit 0 is always set, even if the
752 * emulated CPU does not support XSAVE (see fx_init).
753 */
d91cab78 754 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 755 if (xcr0 & ~valid_bits)
2acf923e 756 return 1;
46c34cb0 757
d91cab78
DH		 758 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
759 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 760 return 1;
761
d91cab78
DH		 762 if (xcr0 & XFEATURE_MASK_AVX512) {
763 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 764 return 1;
d91cab78 765 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 766 return 1;
767 }
2acf923e 768 vcpu->arch.xcr0 = xcr0;
56c103ec 769
d91cab78 770 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 771 kvm_update_cpuid(vcpu);
2acf923e
DC		 772 return 0;
773}
774
775int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
776{
764bcbc5
Z		 777 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
778 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 779 kvm_inject_gp(vcpu, 0);
780 return 1;
781 }
782 return 0;
783}
784EXPORT_SYMBOL_GPL(kvm_set_xcr);
785
a83b29c6 786int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 787{
fc78f519 788 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 789 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 790 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 791
0f12244f
GN		 792 if (cr4 & CR4_RESERVED_BITS)
793 return 1;
a03490ed 794
d6321d49 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 796 return 1;
797
d6321d49 798 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 799 return 1;
800
d6321d49 801 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 802 return 1;
803
d6321d49 804 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 805 return 1;
806
d6321d49 807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 808 return 1;
809
fd8cb433 810 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 811 return 1;
812
ae3e61e1
PB		 813 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
814 return 1;
815
a03490ed 816 if (is_long_mode(vcpu)) {
0f12244f
GN		 817 if (!(cr4 & X86_CR4_PAE))
818 return 1;
a2edf57f
AK		 819 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
820 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 821 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
822 kvm_read_cr3(vcpu)))
0f12244f
GN		 823 return 1;
824
ad756a16 825 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 826 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 827 return 1;
828
829 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
830 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
831 return 1;
832 }
833
5e1746d6 834 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 835 return 1;
a03490ed 836
ad756a16
MJ		 837 if (((cr4 ^ old_cr4) & pdptr_bits) ||
838 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 839 kvm_mmu_reset_context(vcpu);
0f12244f 840
b9baba86 841 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 842 kvm_update_cpuid(vcpu);
2acf923e 843
0f12244f
GN		 844 return 0;
845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 847
2390218b 848int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 849{
ac146235 850#ifdef CONFIG_X86_64
c19986fe
JS		 851 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
852
853 if (pcid_enabled)
854 cr3 &= ~CR3_PCID_INVD;
ac146235 855#endif
9d88fca7 856
9f8fe504 857 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 858 kvm_mmu_sync_roots(vcpu);
77c3913b 859 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 860 return 0;
d835dfec
AK		 861 }
862
d1cd3ce9 863 if (is_long_mode(vcpu) &&
a780a3ea 864 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 865 return 1;
866 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 867 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 868 return 1;
a03490ed 869
0f12244f 870 vcpu->arch.cr3 = cr3;
aff48baa 871 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 872 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 873 return 0;
874}
2d3ad1f4 875EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 876
eea1cff9 877int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 878{
0f12244f
GN		 879 if (cr8 & CR8_RESERVED_BITS)
880 return 1;
35754c98 881 if (lapic_in_kernel(vcpu))
a03490ed
CO		 882 kvm_lapic_set_tpr(vcpu, cr8);
883 else
ad312c7c 884 vcpu->arch.cr8 = cr8;
0f12244f
GN		 885 return 0;
886}
2d3ad1f4 887EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 888
2d3ad1f4 889unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 890{
35754c98 891 if (lapic_in_kernel(vcpu))
a03490ed
CO		 892 return kvm_lapic_get_cr8(vcpu);
893 else
ad312c7c 894 return vcpu->arch.cr8;
a03490ed 895}
2d3ad1f4 896EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 897
ae561ede
NA		 898static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
899{
900 int i;
901
902 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
903 for (i = 0; i < KVM_NR_DB_REGS; i++)
904 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
905 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
906 }
907}
908
73aaf249
JK		 909static void kvm_update_dr6(struct kvm_vcpu *vcpu)
910{
911 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
912 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
913}
914
c8639010
JK		 915static void kvm_update_dr7(struct kvm_vcpu *vcpu)
916{
917 unsigned long dr7;
918
919 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
920 dr7 = vcpu->arch.guest_debug_dr7;
921 else
922 dr7 = vcpu->arch.dr7;
923 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 924 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
925 if (dr7 & DR7_BP_EN_MASK)
926 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 927}
928
6f43ed01
NA		 929static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
930{
931 u64 fixed = DR6_FIXED_1;
932
d6321d49 933 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 934 fixed |= DR6_RTM;
935 return fixed;
936}
937
338dbc97 938static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 939{
940 switch (dr) {
941 case 0 ... 3:
942 vcpu->arch.db[dr] = val;
943 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
944 vcpu->arch.eff_db[dr] = val;
945 break;
946 case 4:
020df079
GN		 947 /* fall through */
948 case 6:
338dbc97
GN		 949 if (val & 0xffffffff00000000ULL)
950 return -1; /* #GP */
6f43ed01 951 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 952 kvm_update_dr6(vcpu);
020df079
GN		 953 break;
954 case 5:
020df079
GN		 955 /* fall through */
956 default: /* 7 */
338dbc97
GN		 957 if (val & 0xffffffff00000000ULL)
958 return -1; /* #GP */
020df079 959 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 960 kvm_update_dr7(vcpu);
020df079
GN		 961 break;
962 }
963
964 return 0;
965}
338dbc97
GN		 966
967int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
968{
16f8a6f9 969 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 970 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 971 return 1;
972 }
973 return 0;
338dbc97 974}
020df079
GN		 975EXPORT_SYMBOL_GPL(kvm_set_dr);
976
16f8a6f9 977int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 978{
979 switch (dr) {
980 case 0 ... 3:
981 *val = vcpu->arch.db[dr];
982 break;
983 case 4:
020df079
GN		 984 /* fall through */
985 case 6:
73aaf249
JK		 986 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
987 *val = vcpu->arch.dr6;
988 else
989 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 990 break;
991 case 5:
020df079
GN		 992 /* fall through */
993 default: /* 7 */
994 *val = vcpu->arch.dr7;
995 break;
996 }
338dbc97
GN		 997 return 0;
998}
020df079
GN		 999EXPORT_SYMBOL_GPL(kvm_get_dr);
1000
022cd0e8
AK		 1001bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1002{
1003 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1004 u64 data;
1005 int err;
1006
c6702c9d 1007 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1008 if (err)
1009 return err;
1010 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1011 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1012 return err;
1013}
1014EXPORT_SYMBOL_GPL(kvm_rdpmc);
1015
043405e1
CO		 1016/*
1017 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1018 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1019 *
1020 * This list is modified at module load time to reflect the
e3267cbb 1021 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1022 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1023 * may depend on host virtualization features rather than host cpu features.
043405e1 1024 */
e3267cbb 1025
043405e1
CO		 1026static u32 msrs_to_save[] = {
1027 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1028 MSR_STAR,
043405e1
CO		 1029#ifdef CONFIG_X86_64
1030 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1031#endif
b3897a49 1032 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1033 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1034 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1035};
1036
1037static unsigned num_msrs_to_save;
1038
62ef68bb
PB		 1039static u32 emulated_msrs[] = {
1040 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1041 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1042 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1043 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1044 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1045 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1046 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1047 HV_X64_MSR_RESET,
11c4b1ca 1048 HV_X64_MSR_VP_INDEX,
9eec50b8 1049 HV_X64_MSR_VP_RUNTIME,
5c919412 1050 HV_X64_MSR_SCONTROL,
1f4b34f8 1051 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1052 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1053 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1054 HV_X64_MSR_TSC_EMULATION_STATUS,
1055
1056 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1057 MSR_KVM_PV_EOI_EN,
1058
ba904635 1059 MSR_IA32_TSC_ADJUST,
a3e06bbe 1060 MSR_IA32_TSCDEADLINE,
043405e1 1061 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1062 MSR_IA32_MCG_STATUS,
1063 MSR_IA32_MCG_CTL,
c45dcc71 1064 MSR_IA32_MCG_EXT_CTL,
64d60670 1065 MSR_IA32_SMBASE,
52797bf9 1066 MSR_SMI_COUNT,
db2336a8
KH		 1067 MSR_PLATFORM_INFO,
1068 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1069};
1070
62ef68bb
PB		 1071static unsigned num_emulated_msrs;
1072
801e459a
TL		 1073/*
1074 * List of msr numbers which are used to expose MSR-based features that
1075 * can be used by a hypervisor to validate requested CPU features.
1076 */
1077static u32 msr_based_features[] = {
1389309c
PB		 1078 MSR_IA32_VMX_BASIC,
1079 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1080 MSR_IA32_VMX_PINBASED_CTLS,
1081 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1082 MSR_IA32_VMX_PROCBASED_CTLS,
1083 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1084 MSR_IA32_VMX_EXIT_CTLS,
1085 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1086 MSR_IA32_VMX_ENTRY_CTLS,
1087 MSR_IA32_VMX_MISC,
1088 MSR_IA32_VMX_CR0_FIXED0,
1089 MSR_IA32_VMX_CR0_FIXED1,
1090 MSR_IA32_VMX_CR4_FIXED0,
1091 MSR_IA32_VMX_CR4_FIXED1,
1092 MSR_IA32_VMX_VMCS_ENUM,
1093 MSR_IA32_VMX_PROCBASED_CTLS2,
1094 MSR_IA32_VMX_EPT_VPID_CAP,
1095 MSR_IA32_VMX_VMFUNC,
1096
d1d93fa9 1097 MSR_F10H_DECFG,
518e7b94 1098 MSR_IA32_UCODE_REV,
801e459a
TL		 1099};
1100
1101static unsigned int num_msr_based_features;
1102
66421c1e
WL		 1103static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1104{
1105 switch (msr->index) {
518e7b94
WL		 1106 case MSR_IA32_UCODE_REV:
1107 rdmsrl(msr->index, msr->data);
1108 break;
66421c1e
WL		 1109 default:
1110 if (kvm_x86_ops->get_msr_feature(msr))
1111 return 1;
1112 }
1113 return 0;
1114}
1115
801e459a
TL		 1116static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1117{
1118 struct kvm_msr_entry msr;
66421c1e 1119 int r;
801e459a
TL		 1120
1121 msr.index = index;
66421c1e
WL		 1122 r = kvm_get_msr_feature(&msr);
1123 if (r)
1124 return r;
801e459a
TL		 1125
1126 *data = msr.data;
1127
1128 return 0;
1129}
1130
384bb783 1131bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1132{
b69e8cae 1133 if (efer & efer_reserved_bits)
384bb783 1134 return false;
15c4a640 1135
1b4d56b8 1136 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1137 return false;
1b2fd70c 1138
1b4d56b8 1139 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1140 return false;
d8017474 1141
384bb783
JK		 1142 return true;
1143}
1144EXPORT_SYMBOL_GPL(kvm_valid_efer);
1145
1146static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1147{
1148 u64 old_efer = vcpu->arch.efer;
1149
1150 if (!kvm_valid_efer(vcpu, efer))
1151 return 1;
1152
1153 if (is_paging(vcpu)
1154 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1155 return 1;
1156
15c4a640 1157 efer &= ~EFER_LMA;
f6801dff 1158 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1159
a3d204e2
SY		 1160 kvm_x86_ops->set_efer(vcpu, efer);
1161
aad82703
SY		 1162 /* Update reserved bits */
1163 if ((efer ^ old_efer) & EFER_NX)
1164 kvm_mmu_reset_context(vcpu);
1165
b69e8cae 1166 return 0;
15c4a640
CO		 1167}
1168
f2b4b7dd
JR		 1169void kvm_enable_efer_bits(u64 mask)
1170{
1171 efer_reserved_bits &= ~mask;
1172}
1173EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1174
15c4a640
CO		 1175/*
1176 * Writes msr value into into the appropriate "register".
1177 * Returns 0 on success, non-0 otherwise.
1178 * Assumes vcpu_load() was already called.
1179 */
8fe8ab46 1180int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1181{
854e8bb1
NA		 1182 switch (msr->index) {
1183 case MSR_FS_BASE:
1184 case MSR_GS_BASE:
1185 case MSR_KERNEL_GS_BASE:
1186 case MSR_CSTAR:
1187 case MSR_LSTAR:
fd8cb433 1188 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1189 return 1;
1190 break;
1191 case MSR_IA32_SYSENTER_EIP:
1192 case MSR_IA32_SYSENTER_ESP:
1193 /*
1194 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1195 * non-canonical address is written on Intel but not on
1196 * AMD (which ignores the top 32-bits, because it does
1197 * not implement 64-bit SYSENTER).
1198 *
1199 * 64-bit code should hence be able to write a non-canonical
1200 * value on AMD. Making the address canonical ensures that
1201 * vmentry does not fail on Intel after writing a non-canonical
1202 * value, and that something deterministic happens if the guest
1203 * invokes 64-bit SYSENTER.
1204 */
fd8cb433 1205 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1206 }
8fe8ab46 1207 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1208}
854e8bb1 1209EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1210
313a3dc7
CO		 1211/*
1212 * Adapt set_msr() to msr_io()'s calling convention
1213 */
609e36d3
PB		 1214static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1215{
1216 struct msr_data msr;
1217 int r;
1218
1219 msr.index = index;
1220 msr.host_initiated = true;
1221 r = kvm_get_msr(vcpu, &msr);
1222 if (r)
1223 return r;
1224
1225 *data = msr.data;
1226 return 0;
1227}
1228
313a3dc7
CO		 1229static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1230{
8fe8ab46
WA		 1231 struct msr_data msr;
1232
1233 msr.data = *data;
1234 msr.index = index;
1235 msr.host_initiated = true;
1236 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1237}
1238
16e8d74d
MT		 1239#ifdef CONFIG_X86_64
1240struct pvclock_gtod_data {
1241 seqcount_t seq;
1242
1243 struct { /* extract of a clocksource struct */
1244 int vclock_mode;
a5a1d1c2
TG		 1245 u64 cycle_last;
1246 u64 mask;
16e8d74d
MT		 1247 u32 mult;
1248 u32 shift;
1249 } clock;
1250
cbcf2dd3
TG		 1251 u64 boot_ns;
1252 u64 nsec_base;
55dd00a7 1253 u64 wall_time_sec;
16e8d74d
MT		 1254};
1255
1256static struct pvclock_gtod_data pvclock_gtod_data;
1257
1258static void update_pvclock_gtod(struct timekeeper *tk)
1259{
1260 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1261 u64 boot_ns;
1262
876e7881 1263 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1264
1265 write_seqcount_begin(&vdata->seq);
1266
1267 /* copy pvclock gtod data */
876e7881
PZ		 1268 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1269 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1270 vdata->clock.mask = tk->tkr_mono.mask;
1271 vdata->clock.mult = tk->tkr_mono.mult;
1272 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1273
cbcf2dd3 1274 vdata->boot_ns = boot_ns;
876e7881 1275 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1276
55dd00a7
MT		 1277 vdata->wall_time_sec = tk->xtime_sec;
1278
16e8d74d
MT		 1279 write_seqcount_end(&vdata->seq);
1280}
1281#endif
1282
bab5bb39
NK		 1283void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1284{
1285 /*
1286 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1287 * vcpu_enter_guest. This function is only called from
1288 * the physical CPU that is running vcpu.
1289 */
1290 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1291}
16e8d74d 1292
18068523
GOC		 1293static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1294{
9ed3c444
AK		 1295 int version;
1296 int r;
50d0a0f9 1297 struct pvclock_wall_clock wc;
87aeb54f 1298 struct timespec64 boot;
18068523
GOC		 1299
1300 if (!wall_clock)
1301 return;
1302
9ed3c444
AK		 1303 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1304 if (r)
1305 return;
1306
1307 if (version & 1)
1308 ++version; /* first time write, random junk */
1309
1310 ++version;
18068523 1311
1dab1345
NK		 1312 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1313 return;
18068523 1314
50d0a0f9
GH		 1315 /*
1316 * The guest calculates current wall clock time by adding
34c238a1 1317 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1318 * wall clock specified here. guest system time equals host
1319 * system time for us, thus we must fill in host boot time here.
1320 */
87aeb54f 1321 getboottime64(&boot);
50d0a0f9 1322
4b648665 1323 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1324 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1325 boot = timespec64_sub(boot, ts);
4b648665 1326 }
87aeb54f 1327 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1328 wc.nsec = boot.tv_nsec;
1329 wc.version = version;
18068523
GOC		 1330
1331 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1332
1333 version++;
1334 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1335}
1336
50d0a0f9
GH		 1337static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1338{
b51012de
PB		 1339 do_shl32_div32(dividend, divisor);
1340 return dividend;
50d0a0f9
GH		 1341}
1342
3ae13faa 1343static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1344 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1345{
5f4e3f88 1346 uint64_t scaled64;
50d0a0f9
GH		 1347 int32_t shift = 0;
1348 uint64_t tps64;
1349 uint32_t tps32;
1350
3ae13faa
PB		 1351 tps64 = base_hz;
1352 scaled64 = scaled_hz;
50933623 1353 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1354 tps64 >>= 1;
1355 shift--;
1356 }
1357
1358 tps32 = (uint32_t)tps64;
50933623
JK		 1359 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1360 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1361 scaled64 >>= 1;
1362 else
1363 tps32 <<= 1;
50d0a0f9
GH		 1364 shift++;
1365 }
1366
5f4e3f88
ZA		 1367 *pshift = shift;
1368 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1369
3ae13faa
PB		 1370 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1371 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1372}
1373
d828199e 1374#ifdef CONFIG_X86_64
16e8d74d 1375static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1376#endif
16e8d74d 1377
c8076604 1378static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1379static unsigned long max_tsc_khz;
c8076604 1380
cc578287 1381static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1382{
cc578287
ZA		 1383 u64 v = (u64)khz * (1000000 + ppm);
1384 do_div(v, 1000000);
1385 return v;
1e993611
JR		 1386}
1387
381d585c
HZ		 1388static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1389{
1390 u64 ratio;
1391
1392 /* Guest TSC same frequency as host TSC? */
1393 if (!scale) {
1394 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1395 return 0;
1396 }
1397
1398 /* TSC scaling supported? */
1399 if (!kvm_has_tsc_control) {
1400 if (user_tsc_khz > tsc_khz) {
1401 vcpu->arch.tsc_catchup = 1;
1402 vcpu->arch.tsc_always_catchup = 1;
1403 return 0;
1404 } else {
1405 WARN(1, "user requested TSC rate below hardware speed\n");
1406 return -1;
1407 }
1408 }
1409
1410 /* TSC scaling required - calculate ratio */
1411 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1412 user_tsc_khz, tsc_khz);
1413
1414 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1415 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1416 user_tsc_khz);
1417 return -1;
1418 }
1419
1420 vcpu->arch.tsc_scaling_ratio = ratio;
1421 return 0;
1422}
1423
4941b8cb 1424static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1425{
cc578287
ZA		 1426 u32 thresh_lo, thresh_hi;
1427 int use_scaling = 0;
217fc9cf 1428
03ba32ca 1429 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1430 if (user_tsc_khz == 0) {
ad721883
HZ		 1431 /* set tsc_scaling_ratio to a safe value */
1432 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1433 return -1;
ad721883 1434 }
03ba32ca 1435
c285545f 1436 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1437 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1438 &vcpu->arch.virtual_tsc_shift,
1439 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1440 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1441
1442 /*
1443 * Compute the variation in TSC rate which is acceptable
1444 * within the range of tolerance and decide if the
1445 * rate being applied is within that bounds of the hardware
1446 * rate. If so, no scaling or compensation need be done.
1447 */
1448 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1449 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1450 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1451 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1452 use_scaling = 1;
1453 }
4941b8cb 1454 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1455}
1456
1457static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1458{
e26101b1 1459 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1460 vcpu->arch.virtual_tsc_mult,
1461 vcpu->arch.virtual_tsc_shift);
e26101b1 1462 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1463 return tsc;
1464}
1465
b0c39dc6
VK		 1466static inline int gtod_is_based_on_tsc(int mode)
1467{
1468 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1469}
1470
69b0049a 1471static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1472{
1473#ifdef CONFIG_X86_64
1474 bool vcpus_matched;
b48aa97e
MT		 1475 struct kvm_arch *ka = &vcpu->kvm->arch;
1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1477
1478 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1479 atomic_read(&vcpu->kvm->online_vcpus));
1480
7f187922
MT		 1481 /*
1482 * Once the masterclock is enabled, always perform request in
1483 * order to update it.
1484 *
1485 * In order to enable masterclock, the host clocksource must be TSC
1486 * and the vcpus need to have matched TSCs. When that happens,
1487 * perform request to enable masterclock.
1488 */
1489 if (ka->use_master_clock ||
b0c39dc6 1490 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1491 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1492
1493 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1494 atomic_read(&vcpu->kvm->online_vcpus),
1495 ka->use_master_clock, gtod->clock.vclock_mode);
1496#endif
1497}
1498
ba904635
WA		 1499static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1500{
e79f245d 1501 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1502 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1503}
1504
35181e86
HZ		 1505/*
1506 * Multiply tsc by a fixed point number represented by ratio.
1507 *
1508 * The most significant 64-N bits (mult) of ratio represent the
1509 * integral part of the fixed point number; the remaining N bits
1510 * (frac) represent the fractional part, ie. ratio represents a fixed
1511 * point number (mult + frac * 2^(-N)).
1512 *
1513 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1514 */
1515static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1516{
1517 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1518}
1519
1520u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1521{
1522 u64 _tsc = tsc;
1523 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1524
1525 if (ratio != kvm_default_tsc_scaling_ratio)
1526 _tsc = __scale_tsc(ratio, tsc);
1527
1528 return _tsc;
1529}
1530EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1531
07c1419a
HZ		 1532static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1533{
1534 u64 tsc;
1535
1536 tsc = kvm_scale_tsc(vcpu, rdtsc());
1537
1538 return target_tsc - tsc;
1539}
1540
4ba76538
HZ		 1541u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1542{
e79f245d
KA		 1543 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1544
1545 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1546}
1547EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1548
a545ab6a
LC		 1549static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1550{
1551 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1552 vcpu->arch.tsc_offset = offset;
1553}
1554
b0c39dc6
VK		 1555static inline bool kvm_check_tsc_unstable(void)
1556{
1557#ifdef CONFIG_X86_64
1558 /*
1559 * TSC is marked unstable when we're running on Hyper-V,
1560 * 'TSC page' clocksource is good.
1561 */
1562 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1563 return false;
1564#endif
1565 return check_tsc_unstable();
1566}
1567
8fe8ab46 1568void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1569{
1570 struct kvm *kvm = vcpu->kvm;
f38e098f 1571 u64 offset, ns, elapsed;
99e3e30a 1572 unsigned long flags;
b48aa97e 1573 bool matched;
0d3da0d2 1574 bool already_matched;
8fe8ab46 1575 u64 data = msr->data;
c5e8ec8e 1576 bool synchronizing = false;
99e3e30a 1577
038f8c11 1578 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1579 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1580 ns = ktime_get_boot_ns();
f38e098f 1581 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1582
03ba32ca 1583 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1584 if (data == 0 && msr->host_initiated) {
1585 /*
1586 * detection of vcpu initialization -- need to sync
1587 * with other vCPUs. This particularly helps to keep
1588 * kvm_clock stable after CPU hotplug
1589 */
1590 synchronizing = true;
1591 } else {
1592 u64 tsc_exp = kvm->arch.last_tsc_write +
1593 nsec_to_cycles(vcpu, elapsed);
1594 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1595 /*
1596 * Special case: TSC write with a small delta (1 second)
1597 * of virtual cycle time against real time is
1598 * interpreted as an attempt to synchronize the CPU.
1599 */
1600 synchronizing = data < tsc_exp + tsc_hz &&
1601 data + tsc_hz > tsc_exp;
1602 }
c5e8ec8e 1603 }
f38e098f
ZA		 1604
1605 /*
5d3cb0f6
ZA		 1606 * For a reliable TSC, we can match TSC offsets, and for an unstable
1607 * TSC, we add elapsed time in this computation. We could let the
1608 * compensation code attempt to catch up if we fall behind, but
1609 * it's better to try to match offsets from the beginning.
1610 */
c5e8ec8e 1611 if (synchronizing &&
5d3cb0f6 1612 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1613 if (!kvm_check_tsc_unstable()) {
e26101b1 1614 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1615 pr_debug("kvm: matched tsc offset for %llu\n", data);
1616 } else {
857e4099 1617 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1618 data += delta;
07c1419a 1619 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1620 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1621 }
b48aa97e 1622 matched = true;
0d3da0d2 1623 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1624 } else {
1625 /*
1626 * We split periods of matched TSC writes into generations.
1627 * For each generation, we track the original measured
1628 * nanosecond time, offset, and write, so if TSCs are in
1629 * sync, we can match exact offset, and if not, we can match
4a969980 1630 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1631 *
1632 * These values are tracked in kvm->arch.cur_xxx variables.
1633 */
1634 kvm->arch.cur_tsc_generation++;
1635 kvm->arch.cur_tsc_nsec = ns;
1636 kvm->arch.cur_tsc_write = data;
1637 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1638 matched = false;
0d3da0d2 1639 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1640 kvm->arch.cur_tsc_generation, data);
f38e098f 1641 }
e26101b1
ZA		 1642
1643 /*
1644 * We also track th most recent recorded KHZ, write and time to
1645 * allow the matching interval to be extended at each write.
1646 */
f38e098f
ZA		 1647 kvm->arch.last_tsc_nsec = ns;
1648 kvm->arch.last_tsc_write = data;
5d3cb0f6 1649 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1650
b183aa58 1651 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1652
1653 /* Keep track of which generation this VCPU has synchronized to */
1654 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1655 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1656 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1657
d6321d49 1658 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1659 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1660
a545ab6a 1661 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1662 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1663
1664 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1665 if (!matched) {
b48aa97e 1666 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1667 } else if (!already_matched) {
1668 kvm->arch.nr_vcpus_matched_tsc++;
1669 }
b48aa97e
MT		 1670
1671 kvm_track_tsc_matching(vcpu);
1672 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1673}
e26101b1 1674
99e3e30a
ZA		 1675EXPORT_SYMBOL_GPL(kvm_write_tsc);
1676
58ea6767
HZ		 1677static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1678 s64 adjustment)
1679{
ea26e4ec 1680 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1681}
1682
1683static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1684{
1685 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1686 WARN_ON(adjustment < 0);
1687 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1688 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1689}
1690
d828199e
MT		 1691#ifdef CONFIG_X86_64
1692
a5a1d1c2 1693static u64 read_tsc(void)
d828199e 1694{
a5a1d1c2 1695 u64 ret = (u64)rdtsc_ordered();
03b9730b 1696 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1697
1698 if (likely(ret >= last))
1699 return ret;
1700
1701 /*
1702 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1703 * predictable (it's just a function of time and the likely is
d828199e
MT		 1704 * very likely) and there's a data dependence, so force GCC
1705 * to generate a branch instead. I don't barrier() because
1706 * we don't actually need a barrier, and if this function
1707 * ever gets inlined it will generate worse code.
1708 */
1709 asm volatile ("");
1710 return last;
1711}
1712
b0c39dc6 1713static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1714{
1715 long v;
1716 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1717 u64 tsc_pg_val;
1718
1719 switch (gtod->clock.vclock_mode) {
1720 case VCLOCK_HVCLOCK:
1721 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1722 tsc_timestamp);
1723 if (tsc_pg_val != U64_MAX) {
1724 /* TSC page valid */
1725 *mode = VCLOCK_HVCLOCK;
1726 v = (tsc_pg_val - gtod->clock.cycle_last) &
1727 gtod->clock.mask;
1728 } else {
1729 /* TSC page invalid */
1730 *mode = VCLOCK_NONE;
1731 }
1732 break;
1733 case VCLOCK_TSC:
1734 *mode = VCLOCK_TSC;
1735 *tsc_timestamp = read_tsc();
1736 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1737 gtod->clock.mask;
1738 break;
1739 default:
1740 *mode = VCLOCK_NONE;
1741 }
d828199e 1742
b0c39dc6
VK		 1743 if (*mode == VCLOCK_NONE)
1744 *tsc_timestamp = v = 0;
d828199e 1745
d828199e
MT		 1746 return v * gtod->clock.mult;
1747}
1748
b0c39dc6 1749static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1750{
cbcf2dd3 1751 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1752 unsigned long seq;
d828199e 1753 int mode;
cbcf2dd3 1754 u64 ns;
d828199e 1755
d828199e
MT		 1756 do {
1757 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1758 ns = gtod->nsec_base;
b0c39dc6 1759 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1760 ns >>= gtod->clock.shift;
cbcf2dd3 1761 ns += gtod->boot_ns;
d828199e 1762 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1763 *t = ns;
d828199e
MT		 1764
1765 return mode;
1766}
1767
899a31f5 1768static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1769{
1770 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1771 unsigned long seq;
1772 int mode;
1773 u64 ns;
1774
1775 do {
1776 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1777 ts->tv_sec = gtod->wall_time_sec;
1778 ns = gtod->nsec_base;
b0c39dc6 1779 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1780 ns >>= gtod->clock.shift;
1781 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1782
1783 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1784 ts->tv_nsec = ns;
1785
1786 return mode;
1787}
1788
b0c39dc6
VK		 1789/* returns true if host is using TSC based clocksource */
1790static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1791{
d828199e 1792 /* checked again under seqlock below */
b0c39dc6 1793 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1794 return false;
1795
b0c39dc6
VK		 1796 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1797 tsc_timestamp));
d828199e 1798}
55dd00a7 1799
b0c39dc6 1800/* returns true if host is using TSC based clocksource */
899a31f5 1801static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1802 u64 *tsc_timestamp)
55dd00a7
MT		 1803{
1804 /* checked again under seqlock below */
b0c39dc6 1805 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1806 return false;
1807
b0c39dc6 1808 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1809}
d828199e
MT		 1810#endif
1811
1812/*
1813 *
b48aa97e
MT		 1814 * Assuming a stable TSC across physical CPUS, and a stable TSC
1815 * across virtual CPUs, the following condition is possible.
1816 * Each numbered line represents an event visible to both
d828199e
MT		 1817 * CPUs at the next numbered event.
1818 *
1819 * "timespecX" represents host monotonic time. "tscX" represents
1820 * RDTSC value.
1821 *
1822 * VCPU0 on CPU0 | VCPU1 on CPU1
1823 *
1824 * 1. read timespec0,tsc0
1825 * 2. | timespec1 = timespec0 + N
1826 * | tsc1 = tsc0 + M
1827 * 3. transition to guest | transition to guest
1828 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1829 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1830 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1831 *
1832 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1833 *
1834 * - ret0 < ret1
1835 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1836 * ...
1837 * - 0 < N - M => M < N
1838 *
1839 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1840 * always the case (the difference between two distinct xtime instances
1841 * might be smaller then the difference between corresponding TSC reads,
1842 * when updating guest vcpus pvclock areas).
1843 *
1844 * To avoid that problem, do not allow visibility of distinct
1845 * system_timestamp/tsc_timestamp values simultaneously: use a master
1846 * copy of host monotonic time values. Update that master copy
1847 * in lockstep.
1848 *
b48aa97e 1849 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1850 *
1851 */
1852
1853static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1854{
1855#ifdef CONFIG_X86_64
1856 struct kvm_arch *ka = &kvm->arch;
1857 int vclock_mode;
b48aa97e
MT		 1858 bool host_tsc_clocksource, vcpus_matched;
1859
1860 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1861 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1862
1863 /*
1864 * If the host uses TSC clock, then passthrough TSC as stable
1865 * to the guest.
1866 */
b48aa97e 1867 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1868 &ka->master_kernel_ns,
1869 &ka->master_cycle_now);
1870
16a96021 1871 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1872 && !ka->backwards_tsc_observed
54750f2c 1873 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1874
d828199e
MT		 1875 if (ka->use_master_clock)
1876 atomic_set(&kvm_guest_has_master_clock, 1);
1877
1878 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1879 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1880 vcpus_matched);
d828199e
MT		 1881#endif
1882}
1883
2860c4b1
PB		 1884void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1885{
1886 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1887}
1888
2e762ff7
MT		 1889static void kvm_gen_update_masterclock(struct kvm *kvm)
1890{
1891#ifdef CONFIG_X86_64
1892 int i;
1893 struct kvm_vcpu *vcpu;
1894 struct kvm_arch *ka = &kvm->arch;
1895
1896 spin_lock(&ka->pvclock_gtod_sync_lock);
1897 kvm_make_mclock_inprogress_request(kvm);
1898 /* no guest entries from this point */
1899 pvclock_update_vm_gtod_copy(kvm);
1900
1901 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1902 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1903
1904 /* guest entries allowed */
1905 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1906 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1907
1908 spin_unlock(&ka->pvclock_gtod_sync_lock);
1909#endif
1910}
1911
e891a32e 1912u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1913{
108b249c 1914 struct kvm_arch *ka = &kvm->arch;
8b953440 1915 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1916 u64 ret;
108b249c 1917
8b953440
PB		 1918 spin_lock(&ka->pvclock_gtod_sync_lock);
1919 if (!ka->use_master_clock) {
1920 spin_unlock(&ka->pvclock_gtod_sync_lock);
1921 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1922 }
1923
8b953440
PB		 1924 hv_clock.tsc_timestamp = ka->master_cycle_now;
1925 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1926 spin_unlock(&ka->pvclock_gtod_sync_lock);
1927
e2c2206a
WL		 1928 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1929 get_cpu();
1930
e70b57a6
WL		 1931 if (__this_cpu_read(cpu_tsc_khz)) {
1932 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1933 &hv_clock.tsc_shift,
1934 &hv_clock.tsc_to_system_mul);
1935 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1936 } else
1937 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1938
1939 put_cpu();
1940
1941 return ret;
108b249c
PB		 1942}
1943
0d6dd2ff
PB		 1944static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1945{
1946 struct kvm_vcpu_arch *vcpu = &v->arch;
1947 struct pvclock_vcpu_time_info guest_hv_clock;
1948
4e335d9e 1949 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1950 &guest_hv_clock, sizeof(guest_hv_clock))))
1951 return;
1952
1953 /* This VCPU is paused, but it's legal for a guest to read another
1954 * VCPU's kvmclock, so we really have to follow the specification where
1955 * it says that version is odd if data is being modified, and even after
1956 * it is consistent.
1957 *
1958 * Version field updates must be kept separate. This is because
1959 * kvm_write_guest_cached might use a "rep movs" instruction, and
1960 * writes within a string instruction are weakly ordered. So there
1961 * are three writes overall.
1962 *
1963 * As a small optimization, only write the version field in the first
1964 * and third write. The vcpu->pv_time cache is still valid, because the
1965 * version field is the first in the struct.
1966 */
1967 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1968
51c4b8bb
LA		 1969 if (guest_hv_clock.version & 1)
1970 ++guest_hv_clock.version; /* first time write, random junk */
1971
0d6dd2ff 1972 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1973 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1974 &vcpu->hv_clock,
1975 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1976
1977 smp_wmb();
1978
1979 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1980 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1981
1982 if (vcpu->pvclock_set_guest_stopped_request) {
1983 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1984 vcpu->pvclock_set_guest_stopped_request = false;
1985 }
1986
1987 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1988
4e335d9e
PB		 1989 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1990 &vcpu->hv_clock,
1991 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1992
1993 smp_wmb();
1994
1995 vcpu->hv_clock.version++;
4e335d9e
PB		 1996 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1997 &vcpu->hv_clock,
1998 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1999}
2000
34c238a1 2001static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2002{
78db6a50 2003 unsigned long flags, tgt_tsc_khz;
18068523 2004 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2005 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2006 s64 kernel_ns;
d828199e 2007 u64 tsc_timestamp, host_tsc;
51d59c6b 2008 u8 pvclock_flags;
d828199e
MT		 2009 bool use_master_clock;
2010
2011 kernel_ns = 0;
2012 host_tsc = 0;
18068523 2013
d828199e
MT		 2014 /*
2015 * If the host uses TSC clock, then passthrough TSC as stable
2016 * to the guest.
2017 */
2018 spin_lock(&ka->pvclock_gtod_sync_lock);
2019 use_master_clock = ka->use_master_clock;
2020 if (use_master_clock) {
2021 host_tsc = ka->master_cycle_now;
2022 kernel_ns = ka->master_kernel_ns;
2023 }
2024 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2025
2026 /* Keep irq disabled to prevent changes to the clock */
2027 local_irq_save(flags);
78db6a50
PB		 2028 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2029 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2030 local_irq_restore(flags);
2031 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2032 return 1;
2033 }
d828199e 2034 if (!use_master_clock) {
4ea1636b 2035 host_tsc = rdtsc();
108b249c 2036 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2037 }
2038
4ba76538 2039 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2040
c285545f
ZA		 2041 /*
2042 * We may have to catch up the TSC to match elapsed wall clock
2043 * time for two reasons, even if kvmclock is used.
2044 * 1) CPU could have been running below the maximum TSC rate
2045 * 2) Broken TSC compensation resets the base at each VCPU
2046 * entry to avoid unknown leaps of TSC even when running
2047 * again on the same CPU. This may cause apparent elapsed
2048 * time to disappear, and the guest to stand still or run
2049 * very slowly.
2050 */
2051 if (vcpu->tsc_catchup) {
2052 u64 tsc = compute_guest_tsc(v, kernel_ns);
2053 if (tsc > tsc_timestamp) {
f1e2b260 2054 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2055 tsc_timestamp = tsc;
2056 }
50d0a0f9
GH		 2057 }
2058
18068523
GOC		 2059 local_irq_restore(flags);
2060
0d6dd2ff 2061 /* With all the info we got, fill in the values */
18068523 2062
78db6a50
PB		 2063 if (kvm_has_tsc_control)
2064 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2065
2066 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2067 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2068 &vcpu->hv_clock.tsc_shift,
2069 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2070 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2071 }
2072
1d5f066e 2073 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2074 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2075 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2076
d828199e 2077 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2078 pvclock_flags = 0;
d828199e
MT		 2079 if (use_master_clock)
2080 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2081
78c0337a
MT		 2082 vcpu->hv_clock.flags = pvclock_flags;
2083
095cf55d
PB		 2084 if (vcpu->pv_time_enabled)
2085 kvm_setup_pvclock_page(v);
2086 if (v == kvm_get_vcpu(v->kvm, 0))
2087 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2088 return 0;
c8076604
GH		 2089}
2090
0061d53d
MT		 2091/*
2092 * kvmclock updates which are isolated to a given vcpu, such as
2093 * vcpu->cpu migration, should not allow system_timestamp from
2094 * the rest of the vcpus to remain static. Otherwise ntp frequency
2095 * correction applies to one vcpu's system_timestamp but not
2096 * the others.
2097 *
2098 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2099 * We need to rate-limit these requests though, as they can
2100 * considerably slow guests that have a large number of vcpus.
2101 * The time for a remote vcpu to update its kvmclock is bound
2102 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2103 */
2104
7e44e449
AJ		 2105#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2106
2107static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2108{
2109 int i;
7e44e449
AJ		 2110 struct delayed_work *dwork = to_delayed_work(work);
2111 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2112 kvmclock_update_work);
2113 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2114 struct kvm_vcpu *vcpu;
2115
2116 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2117 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2118 kvm_vcpu_kick(vcpu);
2119 }
2120}
2121
7e44e449
AJ		 2122static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2123{
2124 struct kvm *kvm = v->kvm;
2125
105b21bb 2126 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2127 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2128 KVMCLOCK_UPDATE_DELAY);
2129}
2130
332967a3
AJ		 2131#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2132
2133static void kvmclock_sync_fn(struct work_struct *work)
2134{
2135 struct delayed_work *dwork = to_delayed_work(work);
2136 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2137 kvmclock_sync_work);
2138 struct kvm *kvm = container_of(ka, struct kvm, arch);
2139
630994b3
MT		 2140 if (!kvmclock_periodic_sync)
2141 return;
2142
332967a3
AJ		 2143 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2144 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2145 KVMCLOCK_SYNC_PERIOD);
2146}
2147
9ffd986c 2148static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2149{
890ca9ae
HY		 2150 u64 mcg_cap = vcpu->arch.mcg_cap;
2151 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2152 u32 msr = msr_info->index;
2153 u64 data = msr_info->data;
890ca9ae 2154
15c4a640 2155 switch (msr) {
15c4a640 2156 case MSR_IA32_MCG_STATUS:
890ca9ae 2157 vcpu->arch.mcg_status = data;
15c4a640 2158 break;
c7ac679c 2159 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2160 if (!(mcg_cap & MCG_CTL_P))
2161 return 1;
2162 if (data != 0 && data != ~(u64)0)
2163 return -1;
2164 vcpu->arch.mcg_ctl = data;
2165 break;
2166 default:
2167 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2168 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2169 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2170 /* only 0 or all 1s can be written to IA32_MCi_CTL
2171 * some Linux kernels though clear bit 10 in bank 4 to
2172 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2173 * this to avoid an uncatched #GP in the guest
2174 */
890ca9ae 2175 if ((offset & 0x3) == 0 &&
114be429 2176 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2177 return -1;
9ffd986c
WL		 2178 if (!msr_info->host_initiated &&
2179 (offset & 0x3) == 1 && data != 0)
2180 return -1;
890ca9ae
HY		 2181 vcpu->arch.mce_banks[offset] = data;
2182 break;
2183 }
2184 return 1;
2185 }
2186 return 0;
2187}
2188
ffde22ac
ES		 2189static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2190{
2191 struct kvm *kvm = vcpu->kvm;
2192 int lm = is_long_mode(vcpu);
2193 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2194 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2195 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2196 : kvm->arch.xen_hvm_config.blob_size_32;
2197 u32 page_num = data & ~PAGE_MASK;
2198 u64 page_addr = data & PAGE_MASK;
2199 u8 *page;
2200 int r;
2201
2202 r = -E2BIG;
2203 if (page_num >= blob_size)
2204 goto out;
2205 r = -ENOMEM;
ff5c2c03
SL		 2206 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2207 if (IS_ERR(page)) {
2208 r = PTR_ERR(page);
ffde22ac 2209 goto out;
ff5c2c03 2210 }
54bf36aa 2211 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2212 goto out_free;
2213 r = 0;
2214out_free:
2215 kfree(page);
2216out:
2217 return r;
2218}
2219
344d9588
GN		 2220static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2221{
2222 gpa_t gpa = data & ~0x3f;
2223
52a5c155
WL		 2224 /* Bits 3:5 are reserved, Should be zero */
2225 if (data & 0x38)
344d9588
GN		 2226 return 1;
2227
2228 vcpu->arch.apf.msr_val = data;
2229
2230 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2231 kvm_clear_async_pf_completion_queue(vcpu);
2232 kvm_async_pf_hash_reset(vcpu);
2233 return 0;
2234 }
2235
4e335d9e 2236 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2237 sizeof(u32)))
344d9588
GN		 2238 return 1;
2239
6adba527 2240 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2241 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2242 kvm_async_pf_wakeup_all(vcpu);
2243 return 0;
2244}
2245
12f9a48f
GC		 2246static void kvmclock_reset(struct kvm_vcpu *vcpu)
2247{
0b79459b 2248 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2249}
2250
f38a7b75
WL		 2251static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2252{
2253 ++vcpu->stat.tlb_flush;
2254 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2255}
2256
c9aaa895
GC		 2257static void record_steal_time(struct kvm_vcpu *vcpu)
2258{
2259 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2260 return;
2261
4e335d9e 2262 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2263 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2264 return;
2265
f38a7b75
WL		 2266 /*
2267 * Doing a TLB flush here, on the guest's behalf, can avoid
2268 * expensive IPIs.
2269 */
2270 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2271 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2272
35f3fae1
WL		 2273 if (vcpu->arch.st.steal.version & 1)
2274 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2275
2276 vcpu->arch.st.steal.version += 1;
2277
4e335d9e 2278 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2279 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2280
2281 smp_wmb();
2282
c54cdf14
LC		 2283 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2284 vcpu->arch.st.last_steal;
2285 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2286
4e335d9e 2287 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2288 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2289
2290 smp_wmb();
2291
2292 vcpu->arch.st.steal.version += 1;
c9aaa895 2293
4e335d9e 2294 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2295 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2296}
2297
8fe8ab46 2298int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2299{
5753785f 2300 bool pr = false;
8fe8ab46
WA		 2301 u32 msr = msr_info->index;
2302 u64 data = msr_info->data;
5753785f 2303
15c4a640 2304 switch (msr) {
2e32b719 2305 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2306 case MSR_IA32_UCODE_WRITE:
2307 case MSR_VM_HSAVE_PA:
2308 case MSR_AMD64_PATCH_LOADER:
2309 case MSR_AMD64_BU_CFG2:
405a353a 2310 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2311 break;
2312
518e7b94
WL		 2313 case MSR_IA32_UCODE_REV:
2314 if (msr_info->host_initiated)
2315 vcpu->arch.microcode_version = data;
2316 break;
15c4a640 2317 case MSR_EFER:
b69e8cae 2318 return set_efer(vcpu, data);
8f1589d9
AP		 2319 case MSR_K7_HWCR:
2320 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2321 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2322 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2323 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2324 if (data != 0) {
a737f256
CD		 2325 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2326 data);
8f1589d9
AP		 2327 return 1;
2328 }
15c4a640 2329 break;
f7c6d140
AP		 2330 case MSR_FAM10H_MMIO_CONF_BASE:
2331 if (data != 0) {
a737f256
CD		 2332 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2333 "0x%llx\n", data);
f7c6d140
AP		 2334 return 1;
2335 }
15c4a640 2336 break;
b5e2fec0
AG		 2337 case MSR_IA32_DEBUGCTLMSR:
2338 if (!data) {
2339 /* We support the non-activated case already */
2340 break;
2341 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2342 /* Values other than LBR and BTF are vendor-specific,
2343 thus reserved and should throw a #GP */
2344 return 1;
2345 }
a737f256
CD		 2346 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2347 __func__, data);
b5e2fec0 2348 break;
9ba075a6 2349 case 0x200 ... 0x2ff:
ff53604b 2350 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2351 case MSR_IA32_APICBASE:
58cb628d 2352 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2353 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2354 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2355 case MSR_IA32_TSCDEADLINE:
2356 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2357 break;
ba904635 2358 case MSR_IA32_TSC_ADJUST:
d6321d49 2359 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2360 if (!msr_info->host_initiated) {
d913b904 2361 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2362 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2363 }
2364 vcpu->arch.ia32_tsc_adjust_msr = data;
2365 }
2366 break;
15c4a640 2367 case MSR_IA32_MISC_ENABLE:
ad312c7c 2368 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2369 break;
64d60670
PB		 2370 case MSR_IA32_SMBASE:
2371 if (!msr_info->host_initiated)
2372 return 1;
2373 vcpu->arch.smbase = data;
2374 break;
dd259935
PB		 2375 case MSR_IA32_TSC:
2376 kvm_write_tsc(vcpu, msr_info);
2377 break;
52797bf9
LA		 2378 case MSR_SMI_COUNT:
2379 if (!msr_info->host_initiated)
2380 return 1;
2381 vcpu->arch.smi_count = data;
2382 break;
11c6bffa 2383 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2384 case MSR_KVM_WALL_CLOCK:
2385 vcpu->kvm->arch.wall_clock = data;
2386 kvm_write_wall_clock(vcpu->kvm, data);
2387 break;
11c6bffa 2388 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2389 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2390 struct kvm_arch *ka = &vcpu->kvm->arch;
2391
12f9a48f 2392 kvmclock_reset(vcpu);
18068523 2393
54750f2c
MT		 2394 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2395 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2396
2397 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2398 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2399
2400 ka->boot_vcpu_runs_old_kvmclock = tmp;
2401 }
2402
18068523 2403 vcpu->arch.time = data;
0061d53d 2404 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2405
2406 /* we verify if the enable bit is set... */
2407 if (!(data & 1))
2408 break;
2409
4e335d9e 2410 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2411 &vcpu->arch.pv_time, data & ~1ULL,
2412 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2413 vcpu->arch.pv_time_enabled = false;
2414 else
2415 vcpu->arch.pv_time_enabled = true;
32cad84f 2416
18068523
GOC		 2417 break;
2418 }
344d9588
GN		 2419 case MSR_KVM_ASYNC_PF_EN:
2420 if (kvm_pv_enable_async_pf(vcpu, data))
2421 return 1;
2422 break;
c9aaa895
GC		 2423 case MSR_KVM_STEAL_TIME:
2424
2425 if (unlikely(!sched_info_on()))
2426 return 1;
2427
2428 if (data & KVM_STEAL_RESERVED_MASK)
2429 return 1;
2430
4e335d9e 2431 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2432 data & KVM_STEAL_VALID_BITS,
2433 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2434 return 1;
2435
2436 vcpu->arch.st.msr_val = data;
2437
2438 if (!(data & KVM_MSR_ENABLED))
2439 break;
2440
c9aaa895
GC		 2441 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2442
2443 break;
ae7a2a3f
MT		 2444 case MSR_KVM_PV_EOI_EN:
2445 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2446 return 1;
2447 break;
c9aaa895 2448
890ca9ae
HY		 2449 case MSR_IA32_MCG_CTL:
2450 case MSR_IA32_MCG_STATUS:
81760dcc 2451 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2452 return set_msr_mce(vcpu, msr_info);
71db6023 2453
6912ac32
WH		 2454 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2455 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2456 pr = true; /* fall through */
2457 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2458 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2459 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2460 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2461
2462 if (pr || data != 0)
a737f256
CD		 2463 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2464 "0x%x data 0x%llx\n", msr, data);
5753785f 2465 break;
84e0cefa
JS		 2466 case MSR_K7_CLK_CTL:
2467 /*
2468 * Ignore all writes to this no longer documented MSR.
2469 * Writes are only relevant for old K7 processors,
2470 * all pre-dating SVM, but a recommended workaround from
4a969980 2471 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2472 * affected processor models on the command line, hence
2473 * the need to ignore the workaround.
2474 */
2475 break;
55cd8e5a 2476 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2477 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2478 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2479 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2480 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2481 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2482 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2483 return kvm_hv_set_msr_common(vcpu, msr, data,
2484 msr_info->host_initiated);
91c9c3ed 2485 case MSR_IA32_BBL_CR_CTL3:
2486 /* Drop writes to this legacy MSR -- see rdmsr
2487 * counterpart for further detail.
2488 */
fab0aa3b
EM		 2489 if (report_ignored_msrs)
2490 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2491 msr, data);
91c9c3ed 2492 break;
2b036c6b 2493 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2494 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2495 return 1;
2496 vcpu->arch.osvw.length = data;
2497 break;
2498 case MSR_AMD64_OSVW_STATUS:
d6321d49 2499 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2500 return 1;
2501 vcpu->arch.osvw.status = data;
2502 break;
db2336a8
KH		 2503 case MSR_PLATFORM_INFO:
2504 if (!msr_info->host_initiated ||
2505 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2506 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2507 cpuid_fault_enabled(vcpu)))
2508 return 1;
2509 vcpu->arch.msr_platform_info = data;
2510 break;
2511 case MSR_MISC_FEATURES_ENABLES:
2512 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2513 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2514 !supports_cpuid_fault(vcpu)))
2515 return 1;
2516 vcpu->arch.msr_misc_features_enables = data;
2517 break;
15c4a640 2518 default:
ffde22ac
ES		 2519 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2520 return xen_hvm_config(vcpu, data);
c6702c9d 2521 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2522 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2523 if (!ignore_msrs) {
ae0f5499 2524 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2525 msr, data);
ed85c068
AP		 2526 return 1;
2527 } else {
fab0aa3b
EM		 2528 if (report_ignored_msrs)
2529 vcpu_unimpl(vcpu,
2530 "ignored wrmsr: 0x%x data 0x%llx\n",
2531 msr, data);
ed85c068
AP		 2532 break;
2533 }
15c4a640
CO		 2534 }
2535 return 0;
2536}
2537EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2538
2539
2540/*
2541 * Reads an msr value (of 'msr_index') into 'pdata'.
2542 * Returns 0 on success, non-0 otherwise.
2543 * Assumes vcpu_load() was already called.
2544 */
609e36d3 2545int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2546{
609e36d3 2547 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2548}
ff651cb6 2549EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2550
890ca9ae 2551static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2552{
2553 u64 data;
890ca9ae
HY		 2554 u64 mcg_cap = vcpu->arch.mcg_cap;
2555 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2556
2557 switch (msr) {
15c4a640
CO		 2558 case MSR_IA32_P5_MC_ADDR:
2559 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2560 data = 0;
2561 break;
15c4a640 2562 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2563 data = vcpu->arch.mcg_cap;
2564 break;
c7ac679c 2565 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2566 if (!(mcg_cap & MCG_CTL_P))
2567 return 1;
2568 data = vcpu->arch.mcg_ctl;
2569 break;
2570 case MSR_IA32_MCG_STATUS:
2571 data = vcpu->arch.mcg_status;
2572 break;
2573 default:
2574 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2575 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2576 u32 offset = msr - MSR_IA32_MC0_CTL;
2577 data = vcpu->arch.mce_banks[offset];
2578 break;
2579 }
2580 return 1;
2581 }
2582 *pdata = data;
2583 return 0;
2584}
2585
609e36d3 2586int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2587{
609e36d3 2588 switch (msr_info->index) {
890ca9ae 2589 case MSR_IA32_PLATFORM_ID:
15c4a640 2590 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2591 case MSR_IA32_DEBUGCTLMSR:
2592 case MSR_IA32_LASTBRANCHFROMIP:
2593 case MSR_IA32_LASTBRANCHTOIP:
2594 case MSR_IA32_LASTINTFROMIP:
2595 case MSR_IA32_LASTINTTOIP:
60af2ecd 2596 case MSR_K8_SYSCFG:
3afb1121
PB		 2597 case MSR_K8_TSEG_ADDR:
2598 case MSR_K8_TSEG_MASK:
60af2ecd 2599 case MSR_K7_HWCR:
61a6bd67 2600 case MSR_VM_HSAVE_PA:
1fdbd48c 2601 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2602 case MSR_AMD64_NB_CFG:
f7c6d140 2603 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2604 case MSR_AMD64_BU_CFG2:
0c2df2a1 2605 case MSR_IA32_PERF_CTL:
405a353a 2606 case MSR_AMD64_DC_CFG:
609e36d3 2607 msr_info->data = 0;
15c4a640 2608 break;
c51eb52b 2609 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2610 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2611 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2612 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2613 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2614 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2615 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2616 msr_info->data = 0;
5753785f 2617 break;
742bc670 2618 case MSR_IA32_UCODE_REV:
518e7b94 2619 msr_info->data = vcpu->arch.microcode_version;
742bc670 2620 break;
dd259935
PB		 2621 case MSR_IA32_TSC:
2622 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2623 break;
9ba075a6 2624 case MSR_MTRRcap:
9ba075a6 2625 case 0x200 ... 0x2ff:
ff53604b 2626 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2627 case 0xcd: /* fsb frequency */
609e36d3 2628 msr_info->data = 3;
15c4a640 2629 break;
7b914098
JS		 2630 /*
2631 * MSR_EBC_FREQUENCY_ID
2632 * Conservative value valid for even the basic CPU models.
2633 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2634 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2635 * and 266MHz for model 3, or 4. Set Core Clock
2636 * Frequency to System Bus Frequency Ratio to 1 (bits
2637 * 31:24) even though these are only valid for CPU
2638 * models > 2, however guests may end up dividing or
2639 * multiplying by zero otherwise.
2640 */
2641 case MSR_EBC_FREQUENCY_ID:
609e36d3 2642 msr_info->data = 1 << 24;
7b914098 2643 break;
15c4a640 2644 case MSR_IA32_APICBASE:
609e36d3 2645 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2646 break;
0105d1a5 2647 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2648 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2649 break;
a3e06bbe 2650 case MSR_IA32_TSCDEADLINE:
609e36d3 2651 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2652 break;
ba904635 2653 case MSR_IA32_TSC_ADJUST:
609e36d3 2654 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2655 break;
15c4a640 2656 case MSR_IA32_MISC_ENABLE:
609e36d3 2657 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2658 break;
64d60670
PB		 2659 case MSR_IA32_SMBASE:
2660 if (!msr_info->host_initiated)
2661 return 1;
2662 msr_info->data = vcpu->arch.smbase;
15c4a640 2663 break;
52797bf9
LA		 2664 case MSR_SMI_COUNT:
2665 msr_info->data = vcpu->arch.smi_count;
2666 break;
847f0ad8
AG		 2667 case MSR_IA32_PERF_STATUS:
2668 /* TSC increment by tick */
609e36d3 2669 msr_info->data = 1000ULL;
847f0ad8 2670 /* CPU multiplier */
b0996ae4 2671 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2672 break;
15c4a640 2673 case MSR_EFER:
609e36d3 2674 msr_info->data = vcpu->arch.efer;
15c4a640 2675 break;
18068523 2676 case MSR_KVM_WALL_CLOCK:
11c6bffa 2677 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2678 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2679 break;
2680 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2681 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2682 msr_info->data = vcpu->arch.time;
18068523 2683 break;
344d9588 2684 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2685 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2686 break;
c9aaa895 2687 case MSR_KVM_STEAL_TIME:
609e36d3 2688 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2689 break;
1d92128f 2690 case MSR_KVM_PV_EOI_EN:
609e36d3 2691 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2692 break;
890ca9ae
HY		 2693 case MSR_IA32_P5_MC_ADDR:
2694 case MSR_IA32_P5_MC_TYPE:
2695 case MSR_IA32_MCG_CAP:
2696 case MSR_IA32_MCG_CTL:
2697 case MSR_IA32_MCG_STATUS:
81760dcc 2698 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2699 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2700 case MSR_K7_CLK_CTL:
2701 /*
2702 * Provide expected ramp-up count for K7. All other
2703 * are set to zero, indicating minimum divisors for
2704 * every field.
2705 *
2706 * This prevents guest kernels on AMD host with CPU
2707 * type 6, model 8 and higher from exploding due to
2708 * the rdmsr failing.
2709 */
609e36d3 2710 msr_info->data = 0x20000000;
84e0cefa 2711 break;
55cd8e5a 2712 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2713 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2714 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2715 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2716 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2717 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2718 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2719 return kvm_hv_get_msr_common(vcpu,
2720 msr_info->index, &msr_info->data);
55cd8e5a 2721 break;
91c9c3ed 2722 case MSR_IA32_BBL_CR_CTL3:
2723 /* This legacy MSR exists but isn't fully documented in current
2724 * silicon. It is however accessed by winxp in very narrow
2725 * scenarios where it sets bit #19, itself documented as
2726 * a "reserved" bit. Best effort attempt to source coherent
2727 * read data here should the balance of the register be
2728 * interpreted by the guest:
2729 *
2730 * L2 cache control register 3: 64GB range, 256KB size,
2731 * enabled, latency 0x1, configured
2732 */
609e36d3 2733 msr_info->data = 0xbe702111;
91c9c3ed 2734 break;
2b036c6b 2735 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2736 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2737 return 1;
609e36d3 2738 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2739 break;
2740 case MSR_AMD64_OSVW_STATUS:
d6321d49 2741 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2742 return 1;
609e36d3 2743 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2744 break;
db2336a8
KH		 2745 case MSR_PLATFORM_INFO:
2746 msr_info->data = vcpu->arch.msr_platform_info;
2747 break;
2748 case MSR_MISC_FEATURES_ENABLES:
2749 msr_info->data = vcpu->arch.msr_misc_features_enables;
2750 break;
15c4a640 2751 default:
c6702c9d 2752 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2753 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2754 if (!ignore_msrs) {
ae0f5499
BD		 2755 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2756 msr_info->index);
ed85c068
AP		 2757 return 1;
2758 } else {
fab0aa3b
EM		 2759 if (report_ignored_msrs)
2760 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2761 msr_info->index);
609e36d3 2762 msr_info->data = 0;
ed85c068
AP		 2763 }
2764 break;
15c4a640 2765 }
15c4a640
CO		 2766 return 0;
2767}
2768EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2769
313a3dc7
CO		 2770/*
2771 * Read or write a bunch of msrs. All parameters are kernel addresses.
2772 *
2773 * @return number of msrs set successfully.
2774 */
2775static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2776 struct kvm_msr_entry *entries,
2777 int (*do_msr)(struct kvm_vcpu *vcpu,
2778 unsigned index, u64 *data))
2779{
801e459a 2780 int i;
313a3dc7 2781
313a3dc7
CO		 2782 for (i = 0; i < msrs->nmsrs; ++i)
2783 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2784 break;
2785
313a3dc7
CO		 2786 return i;
2787}
2788
2789/*
2790 * Read or write a bunch of msrs. Parameters are user addresses.
2791 *
2792 * @return number of msrs set successfully.
2793 */
2794static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2795 int (*do_msr)(struct kvm_vcpu *vcpu,
2796 unsigned index, u64 *data),
2797 int writeback)
2798{
2799 struct kvm_msrs msrs;
2800 struct kvm_msr_entry *entries;
2801 int r, n;
2802 unsigned size;
2803
2804 r = -EFAULT;
2805 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2806 goto out;
2807
2808 r = -E2BIG;
2809 if (msrs.nmsrs >= MAX_IO_MSRS)
2810 goto out;
2811
313a3dc7 2812 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2813 entries = memdup_user(user_msrs->entries, size);
2814 if (IS_ERR(entries)) {
2815 r = PTR_ERR(entries);
313a3dc7 2816 goto out;
ff5c2c03 2817 }
313a3dc7
CO		 2818
2819 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2820 if (r < 0)
2821 goto out_free;
2822
2823 r = -EFAULT;
2824 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2825 goto out_free;
2826
2827 r = n;
2828
2829out_free:
7a73c028 2830 kfree(entries);
313a3dc7
CO		 2831out:
2832 return r;
2833}
2834
4d5422ce
WL		 2835static inline bool kvm_can_mwait_in_guest(void)
2836{
2837 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2838 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2839 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2840}
2841
784aa3d7 2842int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2843{
4d5422ce 2844 int r = 0;
018d00d2
ZX		 2845
2846 switch (ext) {
2847 case KVM_CAP_IRQCHIP:
2848 case KVM_CAP_HLT:
2849 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2850 case KVM_CAP_SET_TSS_ADDR:
07716717 2851 case KVM_CAP_EXT_CPUID:
9c15bb1d 2852 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2853 case KVM_CAP_CLOCKSOURCE:
7837699f 2854 case KVM_CAP_PIT:
a28e4f5a 2855 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2856 case KVM_CAP_MP_STATE:
ed848624 2857 case KVM_CAP_SYNC_MMU:
a355c85c 2858 case KVM_CAP_USER_NMI:
52d939a0 2859 case KVM_CAP_REINJECT_CONTROL:
4925663a 2860 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2861 case KVM_CAP_IOEVENTFD:
f848a5a8 2862 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2863 case KVM_CAP_PIT2:
e9f42757 2864 case KVM_CAP_PIT_STATE2:
b927a3ce 2865 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2866 case KVM_CAP_XEN_HVM:
3cfc3092 2867 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2868 case KVM_CAP_HYPERV:
10388a07 2869 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2870 case KVM_CAP_HYPERV_SPIN:
5c919412 2871 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2872 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2873 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2874 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2875 case KVM_CAP_HYPERV_TLBFLUSH:
ab9f4ecb 2876 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2877 case KVM_CAP_DEBUGREGS:
d2be1651 2878 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2879 case KVM_CAP_XSAVE:
344d9588 2880 case KVM_CAP_ASYNC_PF:
92a1f12d 2881 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2882 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2883 case KVM_CAP_READONLY_MEM:
5f66b620 2884 case KVM_CAP_HYPERV_TIME:
100943c5 2885 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2886 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2887 case KVM_CAP_ENABLE_CAP_VM:
2888 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2889 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2890 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2891 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2892 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2893 r = 1;
2894 break;
01643c51
KH		 2895 case KVM_CAP_SYNC_REGS:
2896 r = KVM_SYNC_X86_VALID_FIELDS;
2897 break;
e3fd9a93
PB		 2898 case KVM_CAP_ADJUST_CLOCK:
2899 r = KVM_CLOCK_TSC_STABLE;
2900 break;
4d5422ce 2901 case KVM_CAP_X86_DISABLE_EXITS:
b31c114b 2902 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2903 if(kvm_can_mwait_in_guest())
2904 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2905 break;
6d396b55
PB		 2906 case KVM_CAP_X86_SMM:
2907 /* SMBASE is usually relocated above 1M on modern chipsets,
2908 * and SMM handlers might indeed rely on 4G segment limits,
2909 * so do not report SMM to be available if real mode is
2910 * emulated via vm86 mode. Still, do not go to great lengths
2911 * to avoid userspace's usage of the feature, because it is a
2912 * fringe case that is not enabled except via specific settings
2913 * of the module parameters.
2914 */
2915 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2916 break;
774ead3a
AK		 2917 case KVM_CAP_VAPIC:
2918 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2919 break;
f725230a 2920 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2921 r = KVM_SOFT_MAX_VCPUS;
2922 break;
2923 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2924 r = KVM_MAX_VCPUS;
2925 break;
a988b910 2926 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2927 r = KVM_USER_MEM_SLOTS;
a988b910 2928 break;
a68a6a72
MT		 2929 case KVM_CAP_PV_MMU: /* obsolete */
2930 r = 0;
2f333bcb 2931 break;
890ca9ae
HY		 2932 case KVM_CAP_MCE:
2933 r = KVM_MAX_MCE_BANKS;
2934 break;
2d5b5a66 2935 case KVM_CAP_XCRS:
d366bf7e 2936 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2937 break;
92a1f12d
JR		 2938 case KVM_CAP_TSC_CONTROL:
2939 r = kvm_has_tsc_control;
2940 break;
37131313
RK		 2941 case KVM_CAP_X2APIC_API:
2942 r = KVM_X2APIC_API_VALID_FLAGS;
2943 break;
018d00d2 2944 default:
018d00d2
ZX		 2945 break;
2946 }
2947 return r;
2948
2949}
2950
043405e1
CO		 2951long kvm_arch_dev_ioctl(struct file *filp,
2952 unsigned int ioctl, unsigned long arg)
2953{
2954 void __user *argp = (void __user *)arg;
2955 long r;
2956
2957 switch (ioctl) {
2958 case KVM_GET_MSR_INDEX_LIST: {
2959 struct kvm_msr_list __user *user_msr_list = argp;
2960 struct kvm_msr_list msr_list;
2961 unsigned n;
2962
2963 r = -EFAULT;
2964 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2965 goto out;
2966 n = msr_list.nmsrs;
62ef68bb 2967 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2968 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2969 goto out;
2970 r = -E2BIG;
e125e7b6 2971 if (n < msr_list.nmsrs)
043405e1
CO		 2972 goto out;
2973 r = -EFAULT;
2974 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2975 num_msrs_to_save * sizeof(u32)))
2976 goto out;
e125e7b6 2977 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2978 &emulated_msrs,
62ef68bb 2979 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2980 goto out;
2981 r = 0;
2982 break;
2983 }
9c15bb1d
BP		 2984 case KVM_GET_SUPPORTED_CPUID:
2985 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2986 struct kvm_cpuid2 __user *cpuid_arg = argp;
2987 struct kvm_cpuid2 cpuid;
2988
2989 r = -EFAULT;
2990 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2991 goto out;
9c15bb1d
BP		 2992
2993 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2994 ioctl);
674eea0f
AK		 2995 if (r)
2996 goto out;
2997
2998 r = -EFAULT;
2999 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3000 goto out;
3001 r = 0;
3002 break;
3003 }
890ca9ae 3004 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3005 r = -EFAULT;
c45dcc71
AR		 3006 if (copy_to_user(argp, &kvm_mce_cap_supported,
3007 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3008 goto out;
3009 r = 0;
3010 break;
801e459a
TL		 3011 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3012 struct kvm_msr_list __user *user_msr_list = argp;
3013 struct kvm_msr_list msr_list;
3014 unsigned int n;
3015
3016 r = -EFAULT;
3017 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3018 goto out;
3019 n = msr_list.nmsrs;
3020 msr_list.nmsrs = num_msr_based_features;
3021 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3022 goto out;
3023 r = -E2BIG;
3024 if (n < msr_list.nmsrs)
3025 goto out;
3026 r = -EFAULT;
3027 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3028 num_msr_based_features * sizeof(u32)))
3029 goto out;
3030 r = 0;
3031 break;
3032 }
3033 case KVM_GET_MSRS:
3034 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3035 break;
890ca9ae 3036 }
043405e1
CO		 3037 default:
3038 r = -EINVAL;
3039 }
3040out:
3041 return r;
3042}
3043
f5f48ee1
SY		 3044static void wbinvd_ipi(void *garbage)
3045{
3046 wbinvd();
3047}
3048
3049static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3050{
e0f0bbc5 3051 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3052}
3053
313a3dc7
CO		 3054void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3055{
f5f48ee1
SY		 3056 /* Address WBINVD may be executed by guest */
3057 if (need_emulate_wbinvd(vcpu)) {
3058 if (kvm_x86_ops->has_wbinvd_exit())
3059 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3060 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3061 smp_call_function_single(vcpu->cpu,
3062 wbinvd_ipi, NULL, 1);
3063 }
3064
313a3dc7 3065 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3066
0dd6a6ed
ZA		 3067 /* Apply any externally detected TSC adjustments (due to suspend) */
3068 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3069 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3070 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3071 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3072 }
8f6055cb 3073
b0c39dc6 3074 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3075 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3076 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3077 if (tsc_delta < 0)
3078 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3079
b0c39dc6 3080 if (kvm_check_tsc_unstable()) {
07c1419a 3081 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3082 vcpu->arch.last_guest_tsc);
a545ab6a 3083 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3084 vcpu->arch.tsc_catchup = 1;
c285545f 3085 }
a749e247
PB		 3086
3087 if (kvm_lapic_hv_timer_in_use(vcpu))
3088 kvm_lapic_restart_hv_timer(vcpu);
3089
d98d07ca
MT		 3090 /*
3091 * On a host with synchronized TSC, there is no need to update
3092 * kvmclock on vcpu->cpu migration
3093 */
3094 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3095 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3096 if (vcpu->cpu != cpu)
1bd2009e 3097 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3098 vcpu->cpu = cpu;
6b7d7e76 3099 }
c9aaa895 3100
c9aaa895 3101 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3102}
3103
0b9f6c46
PX		 3104static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3105{
3106 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3107 return;
3108
fa55eedd 3109 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3110
4e335d9e 3111 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3112 &vcpu->arch.st.steal.preempted,
3113 offsetof(struct kvm_steal_time, preempted),
3114 sizeof(vcpu->arch.st.steal.preempted));
3115}
3116
313a3dc7
CO		 3117void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3118{
cc0d907c 3119 int idx;
de63ad4c
LM		 3120
3121 if (vcpu->preempted)
3122 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3123
931f261b
AA		 3124 /*
3125 * Disable page faults because we're in atomic context here.
3126 * kvm_write_guest_offset_cached() would call might_fault()
3127 * that relies on pagefault_disable() to tell if there's a
3128 * bug. NOTE: the write to guest memory may not go through if
3129 * during postcopy live migration or if there's heavy guest
3130 * paging.
3131 */
3132 pagefault_disable();
cc0d907c
AA		 3133 /*
3134 * kvm_memslots() will be called by
3135 * kvm_write_guest_offset_cached() so take the srcu lock.
3136 */
3137 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3138 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3139 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3140 pagefault_enable();
02daab21 3141 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3142 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3143 /*
3144 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3145 * on every vmexit, but if not, we might have a stale dr6 from the
3146 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3147 */
3148 set_debugreg(0, 6);
313a3dc7
CO		 3149}
3150
313a3dc7
CO		 3151static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3152 struct kvm_lapic_state *s)
3153{
fa59cc00 3154 if (vcpu->arch.apicv_active)
d62caabb
AS		 3155 kvm_x86_ops->sync_pir_to_irr(vcpu);
3156
a92e2543 3157 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3158}
3159
3160static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3161 struct kvm_lapic_state *s)
3162{
a92e2543
RK		 3163 int r;
3164
3165 r = kvm_apic_set_state(vcpu, s);
3166 if (r)
3167 return r;
cb142eb7 3168 update_cr8_intercept(vcpu);
313a3dc7
CO		 3169
3170 return 0;
3171}
3172
127a457a
MG		 3173static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3174{
3175 return (!lapic_in_kernel(vcpu) ||
3176 kvm_apic_accept_pic_intr(vcpu));
3177}
3178
782d422b
MG		 3179/*
3180 * if userspace requested an interrupt window, check that the
3181 * interrupt window is open.
3182 *
3183 * No need to exit to userspace if we already have an interrupt queued.
3184 */
3185static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3186{
3187 return kvm_arch_interrupt_allowed(vcpu) &&
3188 !kvm_cpu_has_interrupt(vcpu) &&
3189 !kvm_event_needs_reinjection(vcpu) &&
3190 kvm_cpu_accept_dm_intr(vcpu);
3191}
3192
f77bc6a4
ZX		 3193static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3194 struct kvm_interrupt *irq)
3195{
02cdb50f 3196 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3197 return -EINVAL;
1c1a9ce9
SR		 3198
3199 if (!irqchip_in_kernel(vcpu->kvm)) {
3200 kvm_queue_interrupt(vcpu, irq->irq, false);
3201 kvm_make_request(KVM_REQ_EVENT, vcpu);
3202 return 0;
3203 }
3204
3205 /*
3206 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3207 * fail for in-kernel 8259.
3208 */
3209 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3210 return -ENXIO;
f77bc6a4 3211
1c1a9ce9
SR		 3212 if (vcpu->arch.pending_external_vector != -1)
3213 return -EEXIST;
f77bc6a4 3214
1c1a9ce9 3215 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3216 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3217 return 0;
3218}
3219
c4abb7c9
JK		 3220static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3221{
c4abb7c9 3222 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3223
3224 return 0;
3225}
3226
f077825a
PB		 3227static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3228{
64d60670
PB		 3229 kvm_make_request(KVM_REQ_SMI, vcpu);
3230
f077825a
PB		 3231 return 0;
3232}
3233
b209749f
AK		 3234static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3235 struct kvm_tpr_access_ctl *tac)
3236{
3237 if (tac->flags)
3238 return -EINVAL;
3239 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3240 return 0;
3241}
3242
890ca9ae
HY		 3243static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3244 u64 mcg_cap)
3245{
3246 int r;
3247 unsigned bank_num = mcg_cap & 0xff, bank;
3248
3249 r = -EINVAL;
a9e38c3e 3250 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3251 goto out;
c45dcc71 3252 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3253 goto out;
3254 r = 0;
3255 vcpu->arch.mcg_cap = mcg_cap;
3256 /* Init IA32_MCG_CTL to all 1s */
3257 if (mcg_cap & MCG_CTL_P)
3258 vcpu->arch.mcg_ctl = ~(u64)0;
3259 /* Init IA32_MCi_CTL to all 1s */
3260 for (bank = 0; bank < bank_num; bank++)
3261 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3262
3263 if (kvm_x86_ops->setup_mce)
3264 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3265out:
3266 return r;
3267}
3268
3269static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3270 struct kvm_x86_mce *mce)
3271{
3272 u64 mcg_cap = vcpu->arch.mcg_cap;
3273 unsigned bank_num = mcg_cap & 0xff;
3274 u64 *banks = vcpu->arch.mce_banks;
3275
3276 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3277 return -EINVAL;
3278 /*
3279 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3280 * reporting is disabled
3281 */
3282 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3283 vcpu->arch.mcg_ctl != ~(u64)0)
3284 return 0;
3285 banks += 4 * mce->bank;
3286 /*
3287 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3288 * reporting is disabled for the bank
3289 */
3290 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3291 return 0;
3292 if (mce->status & MCI_STATUS_UC) {
3293 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3294 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3295 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3296 return 0;
3297 }
3298 if (banks[1] & MCI_STATUS_VAL)
3299 mce->status |= MCI_STATUS_OVER;
3300 banks[2] = mce->addr;
3301 banks[3] = mce->misc;
3302 vcpu->arch.mcg_status = mce->mcg_status;
3303 banks[1] = mce->status;
3304 kvm_queue_exception(vcpu, MC_VECTOR);
3305 } else if (!(banks[1] & MCI_STATUS_VAL)
3306 || !(banks[1] & MCI_STATUS_UC)) {
3307 if (banks[1] & MCI_STATUS_VAL)
3308 mce->status |= MCI_STATUS_OVER;
3309 banks[2] = mce->addr;
3310 banks[3] = mce->misc;
3311 banks[1] = mce->status;
3312 } else
3313 banks[1] |= MCI_STATUS_OVER;
3314 return 0;
3315}
3316
3cfc3092
JK		 3317static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3318 struct kvm_vcpu_events *events)
3319{
7460fb4a 3320 process_nmi(vcpu);
664f8e26
WL		 3321 /*
3322 * FIXME: pass injected and pending separately. This is only
3323 * needed for nested virtualization, whose state cannot be
3324 * migrated yet. For now we can combine them.
3325 */
03b82a30 3326 events->exception.injected =
664f8e26
WL		 3327 (vcpu->arch.exception.pending ||
3328 vcpu->arch.exception.injected) &&
03b82a30 3329 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3330 events->exception.nr = vcpu->arch.exception.nr;
3331 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3332 events->exception.pad = 0;
3cfc3092
JK		 3333 events->exception.error_code = vcpu->arch.exception.error_code;
3334
03b82a30 3335 events->interrupt.injected =
04140b41 3336 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3337 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3338 events->interrupt.soft = 0;
37ccdcbe 3339 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3340
3341 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3342 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3343 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3344 events->nmi.pad = 0;
3cfc3092 3345
66450a21 3346 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3347
f077825a
PB		 3348 events->smi.smm = is_smm(vcpu);
3349 events->smi.pending = vcpu->arch.smi_pending;
3350 events->smi.smm_inside_nmi =
3351 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3352 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3353
dab4b911 3354 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3355 | KVM_VCPUEVENT_VALID_SHADOW
3356 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3357 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3358}
3359
6ef4e07e
XG		 3360static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3361
3cfc3092
JK		 3362static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3363 struct kvm_vcpu_events *events)
3364{
dab4b911 3365 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3366 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3367 | KVM_VCPUEVENT_VALID_SHADOW
3368 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3369 return -EINVAL;
3370
78e546c8 3371 if (events->exception.injected &&
28d06353
JM		 3372 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3373 is_guest_mode(vcpu)))
78e546c8
PB		 3374 return -EINVAL;
3375
28bf2888
DH		 3376 /* INITs are latched while in SMM */
3377 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3378 (events->smi.smm || events->smi.pending) &&
3379 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3380 return -EINVAL;
3381
7460fb4a 3382 process_nmi(vcpu);
664f8e26 3383 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3384 vcpu->arch.exception.pending = events->exception.injected;
3385 vcpu->arch.exception.nr = events->exception.nr;
3386 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3387 vcpu->arch.exception.error_code = events->exception.error_code;
3388
04140b41 3389 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3390 vcpu->arch.interrupt.nr = events->interrupt.nr;
3391 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3392 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3393 kvm_x86_ops->set_interrupt_shadow(vcpu,
3394 events->interrupt.shadow);
3cfc3092
JK		 3395
3396 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3397 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3398 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3399 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3400
66450a21 3401 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3402 lapic_in_kernel(vcpu))
66450a21 3403 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3404
f077825a 3405 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3406 u32 hflags = vcpu->arch.hflags;
f077825a 3407 if (events->smi.smm)
6ef4e07e 3408 hflags |= HF_SMM_MASK;
f077825a 3409 else
6ef4e07e
XG		 3410 hflags &= ~HF_SMM_MASK;
3411 kvm_set_hflags(vcpu, hflags);
3412
f077825a 3413 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3414
3415 if (events->smi.smm) {
3416 if (events->smi.smm_inside_nmi)
3417 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3418 else
f4ef1910
WL		 3419 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3420 if (lapic_in_kernel(vcpu)) {
3421 if (events->smi.latched_init)
3422 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3423 else
3424 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3425 }
f077825a
PB		 3426 }
3427 }
3428
3842d135
AK		 3429 kvm_make_request(KVM_REQ_EVENT, vcpu);
3430
3cfc3092
JK		 3431 return 0;
3432}
3433
a1efbe77
JK		 3434static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3435 struct kvm_debugregs *dbgregs)
3436{
73aaf249
JK		 3437 unsigned long val;
3438
a1efbe77 3439 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3440 kvm_get_dr(vcpu, 6, &val);
73aaf249 3441 dbgregs->dr6 = val;
a1efbe77
JK		 3442 dbgregs->dr7 = vcpu->arch.dr7;
3443 dbgregs->flags = 0;
97e69aa6 3444 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3445}
3446
3447static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3448 struct kvm_debugregs *dbgregs)
3449{
3450 if (dbgregs->flags)
3451 return -EINVAL;
3452
d14bdb55
PB		 3453 if (dbgregs->dr6 & ~0xffffffffull)
3454 return -EINVAL;
3455 if (dbgregs->dr7 & ~0xffffffffull)
3456 return -EINVAL;
3457
a1efbe77 3458 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3459 kvm_update_dr0123(vcpu);
a1efbe77 3460 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3461 kvm_update_dr6(vcpu);
a1efbe77 3462 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3463 kvm_update_dr7(vcpu);
a1efbe77 3464
a1efbe77
JK		 3465 return 0;
3466}
3467
df1daba7
PB		 3468#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3469
3470static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3471{
c47ada30 3472 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3473 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3474 u64 valid;
3475
3476 /*
3477 * Copy legacy XSAVE area, to avoid complications with CPUID
3478 * leaves 0 and 1 in the loop below.
3479 */
3480 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3481
3482 /* Set XSTATE_BV */
00c87e9a 3483 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3484 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3485
3486 /*
3487 * Copy each region from the possibly compacted offset to the
3488 * non-compacted offset.
3489 */
d91cab78 3490 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3491 while (valid) {
3492 u64 feature = valid & -valid;
3493 int index = fls64(feature) - 1;
3494 void *src = get_xsave_addr(xsave, feature);
3495
3496 if (src) {
3497 u32 size, offset, ecx, edx;
3498 cpuid_count(XSTATE_CPUID, index,
3499 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3500 if (feature == XFEATURE_MASK_PKRU)
3501 memcpy(dest + offset, &vcpu->arch.pkru,
3502 sizeof(vcpu->arch.pkru));
3503 else
3504 memcpy(dest + offset, src, size);
3505
df1daba7
PB		 3506 }
3507
3508 valid -= feature;
3509 }
3510}
3511
3512static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3513{
c47ada30 3514 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3515 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3516 u64 valid;
3517
3518 /*
3519 * Copy legacy XSAVE area, to avoid complications with CPUID
3520 * leaves 0 and 1 in the loop below.
3521 */
3522 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3523
3524 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3525 xsave->header.xfeatures = xstate_bv;
782511b0 3526 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3527 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3528
3529 /*
3530 * Copy each region from the non-compacted offset to the
3531 * possibly compacted offset.
3532 */
d91cab78 3533 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3534 while (valid) {
3535 u64 feature = valid & -valid;
3536 int index = fls64(feature) - 1;
3537 void *dest = get_xsave_addr(xsave, feature);
3538
3539 if (dest) {
3540 u32 size, offset, ecx, edx;
3541 cpuid_count(XSTATE_CPUID, index,
3542 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3543 if (feature == XFEATURE_MASK_PKRU)
3544 memcpy(&vcpu->arch.pkru, src + offset,
3545 sizeof(vcpu->arch.pkru));
3546 else
3547 memcpy(dest, src + offset, size);
ee4100da 3548 }
df1daba7
PB		 3549
3550 valid -= feature;
3551 }
3552}
3553
2d5b5a66
SY		 3554static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3555 struct kvm_xsave *guest_xsave)
3556{
d366bf7e 3557 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3558 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3559 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3560 } else {
2d5b5a66 3561 memcpy(guest_xsave->region,
7366ed77 3562 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3563 sizeof(struct fxregs_state));
2d5b5a66 3564 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3565 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3566 }
3567}
3568
a575813b
WL		 3569#define XSAVE_MXCSR_OFFSET 24
3570
2d5b5a66
SY		 3571static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3572 struct kvm_xsave *guest_xsave)
3573{
3574 u64 xstate_bv =
3575 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3576 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3577
d366bf7e 3578 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3579 /*
3580 * Here we allow setting states that are not present in
3581 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3582 * with old userspace.
3583 */
a575813b
WL		 3584 if (xstate_bv & ~kvm_supported_xcr0() ||
3585 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3586 return -EINVAL;
df1daba7 3587 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3588 } else {
a575813b
WL		 3589 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3590 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3591 return -EINVAL;
7366ed77 3592 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3593 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3594 }
3595 return 0;
3596}
3597
3598static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3599 struct kvm_xcrs *guest_xcrs)
3600{
d366bf7e 3601 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3602 guest_xcrs->nr_xcrs = 0;
3603 return;
3604 }
3605
3606 guest_xcrs->nr_xcrs = 1;
3607 guest_xcrs->flags = 0;
3608 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3609 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3610}
3611
3612static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3613 struct kvm_xcrs *guest_xcrs)
3614{
3615 int i, r = 0;
3616
d366bf7e 3617 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3618 return -EINVAL;
3619
3620 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3621 return -EINVAL;
3622
3623 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3624 /* Only support XCR0 currently */
c67a04cb 3625 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3626 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3627 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3628 break;
3629 }
3630 if (r)
3631 r = -EINVAL;
3632 return r;
3633}
3634
1c0b28c2
EM		 3635/*
3636 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3637 * stopped by the hypervisor. This function will be called from the host only.
3638 * EINVAL is returned when the host attempts to set the flag for a guest that
3639 * does not support pv clocks.
3640 */
3641static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3642{
0b79459b 3643 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3644 return -EINVAL;
51d59c6b 3645 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3646 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3647 return 0;
3648}
3649
5c919412
AS		 3650static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3651 struct kvm_enable_cap *cap)
3652{
3653 if (cap->flags)
3654 return -EINVAL;
3655
3656 switch (cap->cap) {
efc479e6
RK		 3657 case KVM_CAP_HYPERV_SYNIC2:
3658 if (cap->args[0])
3659 return -EINVAL;
5c919412 3660 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3661 if (!irqchip_in_kernel(vcpu->kvm))
3662 return -EINVAL;
efc479e6
RK		 3663 return kvm_hv_activate_synic(vcpu, cap->cap ==
3664 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3665 default:
3666 return -EINVAL;
3667 }
3668}
3669
313a3dc7
CO		 3670long kvm_arch_vcpu_ioctl(struct file *filp,
3671 unsigned int ioctl, unsigned long arg)
3672{
3673 struct kvm_vcpu *vcpu = filp->private_data;
3674 void __user *argp = (void __user *)arg;
3675 int r;
d1ac91d8
AK		 3676 union {
3677 struct kvm_lapic_state *lapic;
3678 struct kvm_xsave *xsave;
3679 struct kvm_xcrs *xcrs;
3680 void *buffer;
3681 } u;
3682
9b062471
CD		 3683 vcpu_load(vcpu);
3684
d1ac91d8 3685 u.buffer = NULL;
313a3dc7
CO		 3686 switch (ioctl) {
3687 case KVM_GET_LAPIC: {
2204ae3c 3688 r = -EINVAL;
bce87cce 3689 if (!lapic_in_kernel(vcpu))
2204ae3c 3690 goto out;
d1ac91d8 3691 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3692
b772ff36 3693 r = -ENOMEM;
d1ac91d8 3694 if (!u.lapic)
b772ff36 3695 goto out;
d1ac91d8 3696 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3697 if (r)
3698 goto out;
3699 r = -EFAULT;
d1ac91d8 3700 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3701 goto out;
3702 r = 0;
3703 break;
3704 }
3705 case KVM_SET_LAPIC: {
2204ae3c 3706 r = -EINVAL;
bce87cce 3707 if (!lapic_in_kernel(vcpu))
2204ae3c 3708 goto out;
ff5c2c03 3709 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3710 if (IS_ERR(u.lapic)) {
3711 r = PTR_ERR(u.lapic);
3712 goto out_nofree;
3713 }
ff5c2c03 3714
d1ac91d8 3715 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3716 break;
3717 }
f77bc6a4
ZX		 3718 case KVM_INTERRUPT: {
3719 struct kvm_interrupt irq;
3720
3721 r = -EFAULT;
3722 if (copy_from_user(&irq, argp, sizeof irq))
3723 goto out;
3724 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3725 break;
3726 }
c4abb7c9
JK		 3727 case KVM_NMI: {
3728 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3729 break;
3730 }
f077825a
PB		 3731 case KVM_SMI: {
3732 r = kvm_vcpu_ioctl_smi(vcpu);
3733 break;
3734 }
313a3dc7
CO		 3735 case KVM_SET_CPUID: {
3736 struct kvm_cpuid __user *cpuid_arg = argp;
3737 struct kvm_cpuid cpuid;
3738
3739 r = -EFAULT;
3740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3741 goto out;
3742 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3743 break;
3744 }
07716717
DK		 3745 case KVM_SET_CPUID2: {
3746 struct kvm_cpuid2 __user *cpuid_arg = argp;
3747 struct kvm_cpuid2 cpuid;
3748
3749 r = -EFAULT;
3750 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3751 goto out;
3752 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3753 cpuid_arg->entries);
07716717
DK		 3754 break;
3755 }
3756 case KVM_GET_CPUID2: {
3757 struct kvm_cpuid2 __user *cpuid_arg = argp;
3758 struct kvm_cpuid2 cpuid;
3759
3760 r = -EFAULT;
3761 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3762 goto out;
3763 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3764 cpuid_arg->entries);
07716717
DK		 3765 if (r)
3766 goto out;
3767 r = -EFAULT;
3768 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3769 goto out;
3770 r = 0;
3771 break;
3772 }
801e459a
TL		 3773 case KVM_GET_MSRS: {
3774 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3775 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3776 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3777 break;
801e459a
TL		 3778 }
3779 case KVM_SET_MSRS: {
3780 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3781 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3782 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3783 break;
801e459a 3784 }
b209749f
AK		 3785 case KVM_TPR_ACCESS_REPORTING: {
3786 struct kvm_tpr_access_ctl tac;
3787
3788 r = -EFAULT;
3789 if (copy_from_user(&tac, argp, sizeof tac))
3790 goto out;
3791 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3792 if (r)
3793 goto out;
3794 r = -EFAULT;
3795 if (copy_to_user(argp, &tac, sizeof tac))
3796 goto out;
3797 r = 0;
3798 break;
3799 };
b93463aa
AK		 3800 case KVM_SET_VAPIC_ADDR: {
3801 struct kvm_vapic_addr va;
7301d6ab 3802 int idx;
b93463aa
AK		 3803
3804 r = -EINVAL;
35754c98 3805 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3806 goto out;
3807 r = -EFAULT;
3808 if (copy_from_user(&va, argp, sizeof va))
3809 goto out;
7301d6ab 3810 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3811 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3812 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3813 break;
3814 }
890ca9ae
HY		 3815 case KVM_X86_SETUP_MCE: {
3816 u64 mcg_cap;
3817
3818 r = -EFAULT;
3819 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3820 goto out;
3821 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3822 break;
3823 }
3824 case KVM_X86_SET_MCE: {
3825 struct kvm_x86_mce mce;
3826
3827 r = -EFAULT;
3828 if (copy_from_user(&mce, argp, sizeof mce))
3829 goto out;
3830 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3831 break;
3832 }
3cfc3092
JK		 3833 case KVM_GET_VCPU_EVENTS: {
3834 struct kvm_vcpu_events events;
3835
3836 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3837
3838 r = -EFAULT;
3839 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3840 break;
3841 r = 0;
3842 break;
3843 }
3844 case KVM_SET_VCPU_EVENTS: {
3845 struct kvm_vcpu_events events;
3846
3847 r = -EFAULT;
3848 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3849 break;
3850
3851 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3852 break;
3853 }
a1efbe77
JK		 3854 case KVM_GET_DEBUGREGS: {
3855 struct kvm_debugregs dbgregs;
3856
3857 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3858
3859 r = -EFAULT;
3860 if (copy_to_user(argp, &dbgregs,
3861 sizeof(struct kvm_debugregs)))
3862 break;
3863 r = 0;
3864 break;
3865 }
3866 case KVM_SET_DEBUGREGS: {
3867 struct kvm_debugregs dbgregs;
3868
3869 r = -EFAULT;
3870 if (copy_from_user(&dbgregs, argp,
3871 sizeof(struct kvm_debugregs)))
3872 break;
3873
3874 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3875 break;
3876 }
2d5b5a66 3877 case KVM_GET_XSAVE: {
d1ac91d8 3878 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3879 r = -ENOMEM;
d1ac91d8 3880 if (!u.xsave)
2d5b5a66
SY		 3881 break;
3882
d1ac91d8 3883 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3884
3885 r = -EFAULT;
d1ac91d8 3886 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3887 break;
3888 r = 0;
3889 break;
3890 }
3891 case KVM_SET_XSAVE: {
ff5c2c03 3892 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3893 if (IS_ERR(u.xsave)) {
3894 r = PTR_ERR(u.xsave);
3895 goto out_nofree;
3896 }
2d5b5a66 3897
d1ac91d8 3898 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3899 break;
3900 }
3901 case KVM_GET_XCRS: {
d1ac91d8 3902 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3903 r = -ENOMEM;
d1ac91d8 3904 if (!u.xcrs)
2d5b5a66
SY		 3905 break;
3906
d1ac91d8 3907 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3908
3909 r = -EFAULT;
d1ac91d8 3910 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3911 sizeof(struct kvm_xcrs)))
3912 break;
3913 r = 0;
3914 break;
3915 }
3916 case KVM_SET_XCRS: {
ff5c2c03 3917 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3918 if (IS_ERR(u.xcrs)) {
3919 r = PTR_ERR(u.xcrs);
3920 goto out_nofree;
3921 }
2d5b5a66 3922
d1ac91d8 3923 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3924 break;
3925 }
92a1f12d
JR		 3926 case KVM_SET_TSC_KHZ: {
3927 u32 user_tsc_khz;
3928
3929 r = -EINVAL;
92a1f12d
JR		 3930 user_tsc_khz = (u32)arg;
3931
3932 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3933 goto out;
3934
cc578287
ZA		 3935 if (user_tsc_khz == 0)
3936 user_tsc_khz = tsc_khz;
3937
381d585c
HZ		 3938 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3939 r = 0;
92a1f12d 3940
92a1f12d
JR		 3941 goto out;
3942 }
3943 case KVM_GET_TSC_KHZ: {
cc578287 3944 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3945 goto out;
3946 }
1c0b28c2
EM		 3947 case KVM_KVMCLOCK_CTRL: {
3948 r = kvm_set_guest_paused(vcpu);
3949 goto out;
3950 }
5c919412
AS		 3951 case KVM_ENABLE_CAP: {
3952 struct kvm_enable_cap cap;
3953
3954 r = -EFAULT;
3955 if (copy_from_user(&cap, argp, sizeof(cap)))
3956 goto out;
3957 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3958 break;
3959 }
313a3dc7
CO		 3960 default:
3961 r = -EINVAL;
3962 }
3963out:
d1ac91d8 3964 kfree(u.buffer);
9b062471
CD		 3965out_nofree:
3966 vcpu_put(vcpu);
313a3dc7
CO		 3967 return r;
3968}
3969
1499fa80 3970vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 3971{
3972 return VM_FAULT_SIGBUS;
3973}
3974
1fe779f8
CO		 3975static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3976{
3977 int ret;
3978
3979 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3980 return -EINVAL;
1fe779f8
CO		 3981 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3982 return ret;
3983}
3984
b927a3ce
SY		 3985static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3986 u64 ident_addr)
3987{
2ac52ab8 3988 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3989}
3990
1fe779f8
CO		 3991static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3992 u32 kvm_nr_mmu_pages)
3993{
3994 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3995 return -EINVAL;
3996
79fac95e 3997 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3998
3999 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4000 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4001
79fac95e 4002 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4003 return 0;
4004}
4005
4006static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4007{
39de71ec 4008 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4009}
4010
1fe779f8
CO		 4011static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4012{
90bca052 4013 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4014 int r;
4015
4016 r = 0;
4017 switch (chip->chip_id) {
4018 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4019 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4020 sizeof(struct kvm_pic_state));
4021 break;
4022 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4023 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4024 sizeof(struct kvm_pic_state));
4025 break;
4026 case KVM_IRQCHIP_IOAPIC:
33392b49 4027 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4028 break;
4029 default:
4030 r = -EINVAL;
4031 break;
4032 }
4033 return r;
4034}
4035
4036static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4037{
90bca052 4038 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4039 int r;
4040
4041 r = 0;
4042 switch (chip->chip_id) {
4043 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4044 spin_lock(&pic->lock);
4045 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4046 sizeof(struct kvm_pic_state));
90bca052 4047 spin_unlock(&pic->lock);
1fe779f8
CO		 4048 break;
4049 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4050 spin_lock(&pic->lock);
4051 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4052 sizeof(struct kvm_pic_state));
90bca052 4053 spin_unlock(&pic->lock);
1fe779f8
CO		 4054 break;
4055 case KVM_IRQCHIP_IOAPIC:
33392b49 4056 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4057 break;
4058 default:
4059 r = -EINVAL;
4060 break;
4061 }
90bca052 4062 kvm_pic_update_irq(pic);
1fe779f8
CO		 4063 return r;
4064}
4065
e0f63cb9
SY		 4066static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4067{
34f3941c
RK		 4068 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4069
4070 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4071
4072 mutex_lock(&kps->lock);
4073 memcpy(ps, &kps->channels, sizeof(*ps));
4074 mutex_unlock(&kps->lock);
2da29bcc 4075 return 0;
e0f63cb9
SY		 4076}
4077
4078static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4079{
0185604c 4080 int i;
09edea72
RK		 4081 struct kvm_pit *pit = kvm->arch.vpit;
4082
4083 mutex_lock(&pit->pit_state.lock);
34f3941c 4084 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4085 for (i = 0; i < 3; i++)
09edea72
RK		 4086 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4087 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4088 return 0;
e9f42757
BK		 4089}
4090
4091static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4092{
e9f42757
BK		 4093 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4094 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4095 sizeof(ps->channels));
4096 ps->flags = kvm->arch.vpit->pit_state.flags;
4097 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4098 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4099 return 0;
e9f42757
BK		 4100}
4101
4102static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4103{
2da29bcc 4104 int start = 0;
0185604c 4105 int i;
e9f42757 4106 u32 prev_legacy, cur_legacy;
09edea72
RK		 4107 struct kvm_pit *pit = kvm->arch.vpit;
4108
4109 mutex_lock(&pit->pit_state.lock);
4110 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4111 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4112 if (!prev_legacy && cur_legacy)
4113 start = 1;
09edea72
RK		 4114 memcpy(&pit->pit_state.channels, &ps->channels,
4115 sizeof(pit->pit_state.channels));
4116 pit->pit_state.flags = ps->flags;
0185604c 4117 for (i = 0; i < 3; i++)
09edea72 4118 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4119 start && i == 0);
09edea72 4120 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4121 return 0;
e0f63cb9
SY		 4122}
4123
52d939a0
MT		 4124static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4125 struct kvm_reinject_control *control)
4126{
71474e2f
RK		 4127 struct kvm_pit *pit = kvm->arch.vpit;
4128
4129 if (!pit)
52d939a0 4130 return -ENXIO;
b39c90b6 4131
71474e2f
RK		 4132 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4133 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4134 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4135 */
4136 mutex_lock(&pit->pit_state.lock);
4137 kvm_pit_set_reinject(pit, control->pit_reinject);
4138 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4139
52d939a0
MT		 4140 return 0;
4141}
4142
95d4c16c 4143/**
60c34612
TY		 4144 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4145 * @kvm: kvm instance
4146 * @log: slot id and address to which we copy the log
95d4c16c 4147 *
e108ff2f
PB		 4148 * Steps 1-4 below provide general overview of dirty page logging. See
4149 * kvm_get_dirty_log_protect() function description for additional details.
4150 *
4151 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4152 * always flush the TLB (step 4) even if previous step failed and the dirty
4153 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4154 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4155 * writes will be marked dirty for next log read.
95d4c16c 4156 *
60c34612
TY		 4157 * 1. Take a snapshot of the bit and clear it if needed.
4158 * 2. Write protect the corresponding page.
e108ff2f
PB		 4159 * 3. Copy the snapshot to the userspace.
4160 * 4. Flush TLB's if needed.
5bb064dc 4161 */
60c34612 4162int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4163{
60c34612 4164 bool is_dirty = false;
e108ff2f 4165 int r;
5bb064dc 4166
79fac95e 4167 mutex_lock(&kvm->slots_lock);
5bb064dc 4168
88178fd4
KH		 4169 /*
4170 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4171 */
4172 if (kvm_x86_ops->flush_log_dirty)
4173 kvm_x86_ops->flush_log_dirty(kvm);
4174
e108ff2f 4175 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4176
4177 /*
4178 * All the TLBs can be flushed out of mmu lock, see the comments in
4179 * kvm_mmu_slot_remove_write_access().
4180 */
e108ff2f 4181 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4182 if (is_dirty)
4183 kvm_flush_remote_tlbs(kvm);
4184
79fac95e 4185 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4186 return r;
4187}
4188
aa2fbe6d
YZ		 4189int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4190 bool line_status)
23d43cf9
CD		 4191{
4192 if (!irqchip_in_kernel(kvm))
4193 return -ENXIO;
4194
4195 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4196 irq_event->irq, irq_event->level,
4197 line_status);
23d43cf9
CD		 4198 return 0;
4199}
4200
90de4a18
NA		 4201static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4202 struct kvm_enable_cap *cap)
4203{
4204 int r;
4205
4206 if (cap->flags)
4207 return -EINVAL;
4208
4209 switch (cap->cap) {
4210 case KVM_CAP_DISABLE_QUIRKS:
4211 kvm->arch.disabled_quirks = cap->args[0];
4212 r = 0;
4213 break;
49df6397
SR		 4214 case KVM_CAP_SPLIT_IRQCHIP: {
4215 mutex_lock(&kvm->lock);
b053b2ae
SR		 4216 r = -EINVAL;
4217 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4218 goto split_irqchip_unlock;
49df6397
SR		 4219 r = -EEXIST;
4220 if (irqchip_in_kernel(kvm))
4221 goto split_irqchip_unlock;
557abc40 4222 if (kvm->created_vcpus)
49df6397
SR		 4223 goto split_irqchip_unlock;
4224 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4225 if (r)
49df6397
SR		 4226 goto split_irqchip_unlock;
4227 /* Pairs with irqchip_in_kernel. */
4228 smp_wmb();
49776faf 4229 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4230 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4231 r = 0;
4232split_irqchip_unlock:
4233 mutex_unlock(&kvm->lock);
4234 break;
4235 }
37131313
RK		 4236 case KVM_CAP_X2APIC_API:
4237 r = -EINVAL;
4238 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4239 break;
4240
4241 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4242 kvm->arch.x2apic_format = true;
c519265f
RK		 4243 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4244 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4245
4246 r = 0;
4247 break;
4d5422ce
WL		 4248 case KVM_CAP_X86_DISABLE_EXITS:
4249 r = -EINVAL;
4250 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4251 break;
4252
4253 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4254 kvm_can_mwait_in_guest())
4255 kvm->arch.mwait_in_guest = true;
caa057a2
WL		 4256 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL)
4257 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4258 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4259 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4260 r = 0;
4261 break;
90de4a18
NA		 4262 default:
4263 r = -EINVAL;
4264 break;
4265 }
4266 return r;
4267}
4268
1fe779f8
CO		 4269long kvm_arch_vm_ioctl(struct file *filp,
4270 unsigned int ioctl, unsigned long arg)
4271{
4272 struct kvm *kvm = filp->private_data;
4273 void __user *argp = (void __user *)arg;
367e1319 4274 int r = -ENOTTY;
f0d66275
DH		 4275 /*
4276 * This union makes it completely explicit to gcc-3.x
4277 * that these two variables' stack usage should be
4278 * combined, not added together.
4279 */
4280 union {
4281 struct kvm_pit_state ps;
e9f42757 4282 struct kvm_pit_state2 ps2;
c5ff41ce 4283 struct kvm_pit_config pit_config;
f0d66275 4284 } u;
1fe779f8
CO		 4285
4286 switch (ioctl) {
4287 case KVM_SET_TSS_ADDR:
4288 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4289 break;
b927a3ce
SY		 4290 case KVM_SET_IDENTITY_MAP_ADDR: {
4291 u64 ident_addr;
4292
1af1ac91
DH		 4293 mutex_lock(&kvm->lock);
4294 r = -EINVAL;
4295 if (kvm->created_vcpus)
4296 goto set_identity_unlock;
b927a3ce
SY		 4297 r = -EFAULT;
4298 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4299 goto set_identity_unlock;
b927a3ce 4300 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4301set_identity_unlock:
4302 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4303 break;
4304 }
1fe779f8
CO		 4305 case KVM_SET_NR_MMU_PAGES:
4306 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4307 break;
4308 case KVM_GET_NR_MMU_PAGES:
4309 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4310 break;
3ddea128 4311 case KVM_CREATE_IRQCHIP: {
3ddea128 4312 mutex_lock(&kvm->lock);
09941366 4313
3ddea128 4314 r = -EEXIST;
35e6eaa3 4315 if (irqchip_in_kernel(kvm))
3ddea128 4316 goto create_irqchip_unlock;
09941366 4317
3e515705 4318 r = -EINVAL;
557abc40 4319 if (kvm->created_vcpus)
3e515705 4320 goto create_irqchip_unlock;
09941366
RK		 4321
4322 r = kvm_pic_init(kvm);
4323 if (r)
3ddea128 4324 goto create_irqchip_unlock;
09941366
RK		 4325
4326 r = kvm_ioapic_init(kvm);
4327 if (r) {
09941366 4328 kvm_pic_destroy(kvm);
3ddea128 4329 goto create_irqchip_unlock;
09941366
RK		 4330 }
4331
399ec807
AK		 4332 r = kvm_setup_default_irq_routing(kvm);
4333 if (r) {
72bb2fcd 4334 kvm_ioapic_destroy(kvm);
09941366 4335 kvm_pic_destroy(kvm);
71ba994c 4336 goto create_irqchip_unlock;
399ec807 4337 }
49776faf 4338 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4339 smp_wmb();
49776faf 4340 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4341 create_irqchip_unlock:
4342 mutex_unlock(&kvm->lock);
1fe779f8 4343 break;
3ddea128 4344 }
7837699f 4345 case KVM_CREATE_PIT:
c5ff41ce
JK		 4346 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4347 goto create_pit;
4348 case KVM_CREATE_PIT2:
4349 r = -EFAULT;
4350 if (copy_from_user(&u.pit_config, argp,
4351 sizeof(struct kvm_pit_config)))
4352 goto out;
4353 create_pit:
250715a6 4354 mutex_lock(&kvm->lock);
269e05e4
AK		 4355 r = -EEXIST;
4356 if (kvm->arch.vpit)
4357 goto create_pit_unlock;
7837699f 4358 r = -ENOMEM;
c5ff41ce 4359 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4360 if (kvm->arch.vpit)
4361 r = 0;
269e05e4 4362 create_pit_unlock:
250715a6 4363 mutex_unlock(&kvm->lock);
7837699f 4364 break;
1fe779f8
CO		 4365 case KVM_GET_IRQCHIP: {
4366 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4367 struct kvm_irqchip *chip;
1fe779f8 4368
ff5c2c03
SL		 4369 chip = memdup_user(argp, sizeof(*chip));
4370 if (IS_ERR(chip)) {
4371 r = PTR_ERR(chip);
1fe779f8 4372 goto out;
ff5c2c03
SL		 4373 }
4374
1fe779f8 4375 r = -ENXIO;
826da321 4376 if (!irqchip_kernel(kvm))
f0d66275
DH		 4377 goto get_irqchip_out;
4378 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4379 if (r)
f0d66275 4380 goto get_irqchip_out;
1fe779f8 4381 r = -EFAULT;
f0d66275
DH		 4382 if (copy_to_user(argp, chip, sizeof *chip))
4383 goto get_irqchip_out;
1fe779f8 4384 r = 0;
f0d66275
DH		 4385 get_irqchip_out:
4386 kfree(chip);
1fe779f8
CO		 4387 break;
4388 }
4389 case KVM_SET_IRQCHIP: {
4390 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4391 struct kvm_irqchip *chip;
1fe779f8 4392
ff5c2c03
SL		 4393 chip = memdup_user(argp, sizeof(*chip));
4394 if (IS_ERR(chip)) {
4395 r = PTR_ERR(chip);
1fe779f8 4396 goto out;
ff5c2c03
SL		 4397 }
4398
1fe779f8 4399 r = -ENXIO;
826da321 4400 if (!irqchip_kernel(kvm))
f0d66275
DH		 4401 goto set_irqchip_out;
4402 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4403 if (r)
f0d66275 4404 goto set_irqchip_out;
1fe779f8 4405 r = 0;
f0d66275
DH		 4406 set_irqchip_out:
4407 kfree(chip);
1fe779f8
CO		 4408 break;
4409 }
e0f63cb9 4410 case KVM_GET_PIT: {
e0f63cb9 4411 r = -EFAULT;
f0d66275 4412 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4413 goto out;
4414 r = -ENXIO;
4415 if (!kvm->arch.vpit)
4416 goto out;
f0d66275 4417 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4418 if (r)
4419 goto out;
4420 r = -EFAULT;
f0d66275 4421 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4422 goto out;
4423 r = 0;
4424 break;
4425 }
4426 case KVM_SET_PIT: {
e0f63cb9 4427 r = -EFAULT;
f0d66275 4428 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4429 goto out;
4430 r = -ENXIO;
4431 if (!kvm->arch.vpit)
4432 goto out;
f0d66275 4433 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4434 break;
4435 }
e9f42757
BK		 4436 case KVM_GET_PIT2: {
4437 r = -ENXIO;
4438 if (!kvm->arch.vpit)
4439 goto out;
4440 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4441 if (r)
4442 goto out;
4443 r = -EFAULT;
4444 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4445 goto out;
4446 r = 0;
4447 break;
4448 }
4449 case KVM_SET_PIT2: {
4450 r = -EFAULT;
4451 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4452 goto out;
4453 r = -ENXIO;
4454 if (!kvm->arch.vpit)
4455 goto out;
4456 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4457 break;
4458 }
52d939a0
MT		 4459 case KVM_REINJECT_CONTROL: {
4460 struct kvm_reinject_control control;
4461 r = -EFAULT;
4462 if (copy_from_user(&control, argp, sizeof(control)))
4463 goto out;
4464 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4465 break;
4466 }
d71ba788
PB		 4467 case KVM_SET_BOOT_CPU_ID:
4468 r = 0;
4469 mutex_lock(&kvm->lock);
557abc40 4470 if (kvm->created_vcpus)
d71ba788
PB		 4471 r = -EBUSY;
4472 else
4473 kvm->arch.bsp_vcpu_id = arg;
4474 mutex_unlock(&kvm->lock);
4475 break;
ffde22ac 4476 case KVM_XEN_HVM_CONFIG: {
51776043 4477 struct kvm_xen_hvm_config xhc;
ffde22ac 4478 r = -EFAULT;
51776043 4479 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4480 goto out;
4481 r = -EINVAL;
51776043 4482 if (xhc.flags)
ffde22ac 4483 goto out;
51776043 4484 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4485 r = 0;
4486 break;
4487 }
afbcf7ab 4488 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4489 struct kvm_clock_data user_ns;
4490 u64 now_ns;
afbcf7ab
GC		 4491
4492 r = -EFAULT;
4493 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4494 goto out;
4495
4496 r = -EINVAL;
4497 if (user_ns.flags)
4498 goto out;
4499
4500 r = 0;
0bc48bea
RK		 4501 /*
4502 * TODO: userspace has to take care of races with VCPU_RUN, so
4503 * kvm_gen_update_masterclock() can be cut down to locked
4504 * pvclock_update_vm_gtod_copy().
4505 */
4506 kvm_gen_update_masterclock(kvm);
e891a32e 4507 now_ns = get_kvmclock_ns(kvm);
108b249c 4508 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4509 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4510 break;
4511 }
4512 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4513 struct kvm_clock_data user_ns;
4514 u64 now_ns;
4515
e891a32e 4516 now_ns = get_kvmclock_ns(kvm);
108b249c 4517 user_ns.clock = now_ns;
e3fd9a93 4518 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4519 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4520
4521 r = -EFAULT;
4522 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4523 goto out;
4524 r = 0;
4525 break;
4526 }
90de4a18
NA		 4527 case KVM_ENABLE_CAP: {
4528 struct kvm_enable_cap cap;
afbcf7ab 4529
90de4a18
NA		 4530 r = -EFAULT;
4531 if (copy_from_user(&cap, argp, sizeof(cap)))
4532 goto out;
4533 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4534 break;
4535 }
5acc5c06
BS		 4536 case KVM_MEMORY_ENCRYPT_OP: {
4537 r = -ENOTTY;
4538 if (kvm_x86_ops->mem_enc_op)
4539 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4540 break;
4541 }
69eaedee
BS		 4542 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4543 struct kvm_enc_region region;
4544
4545 r = -EFAULT;
4546 if (copy_from_user(&region, argp, sizeof(region)))
4547 goto out;
4548
4549 r = -ENOTTY;
4550 if (kvm_x86_ops->mem_enc_reg_region)
4551 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4552 break;
4553 }
4554 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4555 struct kvm_enc_region region;
4556
4557 r = -EFAULT;
4558 if (copy_from_user(&region, argp, sizeof(region)))
4559 goto out;
4560
4561 r = -ENOTTY;
4562 if (kvm_x86_ops->mem_enc_unreg_region)
4563 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4564 break;
4565 }
faeb7833
RK		 4566 case KVM_HYPERV_EVENTFD: {
4567 struct kvm_hyperv_eventfd hvevfd;
4568
4569 r = -EFAULT;
4570 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4571 goto out;
4572 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4573 break;
4574 }
1fe779f8 4575 default:
ad6260da 4576 r = -ENOTTY;
1fe779f8
CO		 4577 }
4578out:
4579 return r;
4580}
4581
a16b043c 4582static void kvm_init_msr_list(void)
043405e1
CO		 4583{
4584 u32 dummy[2];
4585 unsigned i, j;
4586
62ef68bb 4587 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4588 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4589 continue;
93c4adc7
PB		 4590
4591 /*
4592 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4593 * to the guests in some cases.
93c4adc7
PB		 4594 */
4595 switch (msrs_to_save[i]) {
4596 case MSR_IA32_BNDCFGS:
4597 if (!kvm_x86_ops->mpx_supported())
4598 continue;
4599 break;
9dbe6cf9
PB		 4600 case MSR_TSC_AUX:
4601 if (!kvm_x86_ops->rdtscp_supported())
4602 continue;
4603 break;
93c4adc7
PB		 4604 default:
4605 break;
4606 }
4607
043405e1
CO		 4608 if (j < i)
4609 msrs_to_save[j] = msrs_to_save[i];
4610 j++;
4611 }
4612 num_msrs_to_save = j;
62ef68bb
PB		 4613
4614 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4615 switch (emulated_msrs[i]) {
6d396b55
PB		 4616 case MSR_IA32_SMBASE:
4617 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4618 continue;
4619 break;
62ef68bb
PB		 4620 default:
4621 break;
4622 }
4623
4624 if (j < i)
4625 emulated_msrs[j] = emulated_msrs[i];
4626 j++;
4627 }
4628 num_emulated_msrs = j;
801e459a
TL		 4629
4630 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4631 struct kvm_msr_entry msr;
4632
4633 msr.index = msr_based_features[i];
66421c1e 4634 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4635 continue;
4636
4637 if (j < i)
4638 msr_based_features[j] = msr_based_features[i];
4639 j++;
4640 }
4641 num_msr_based_features = j;
043405e1
CO		 4642}
4643
bda9020e
MT		 4644static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4645 const void *v)
bbd9b64e 4646{
70252a10
AK		 4647 int handled = 0;
4648 int n;
4649
4650 do {
4651 n = min(len, 8);
bce87cce 4652 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4653 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4654 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4655 break;
4656 handled += n;
4657 addr += n;
4658 len -= n;
4659 v += n;
4660 } while (len);
bbd9b64e 4661
70252a10 4662 return handled;
bbd9b64e
CO		 4663}
4664
bda9020e 4665static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4666{
70252a10
AK		 4667 int handled = 0;
4668 int n;
4669
4670 do {
4671 n = min(len, 8);
bce87cce 4672 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4673 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4674 addr, n, v))
4675 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4676 break;
e39d200f 4677 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4678 handled += n;
4679 addr += n;
4680 len -= n;
4681 v += n;
4682 } while (len);
bbd9b64e 4683
70252a10 4684 return handled;
bbd9b64e
CO		 4685}
4686
2dafc6c2
GN		 4687static void kvm_set_segment(struct kvm_vcpu *vcpu,
4688 struct kvm_segment *var, int seg)
4689{
4690 kvm_x86_ops->set_segment(vcpu, var, seg);
4691}
4692
4693void kvm_get_segment(struct kvm_vcpu *vcpu,
4694 struct kvm_segment *var, int seg)
4695{
4696 kvm_x86_ops->get_segment(vcpu, var, seg);
4697}
4698
54987b7a
PB		 4699gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4700 struct x86_exception *exception)
02f59dc9
JR		 4701{
4702 gpa_t t_gpa;
02f59dc9
JR		 4703
4704 BUG_ON(!mmu_is_nested(vcpu));
4705
4706 /* NPT walks are always user-walks */
4707 access |= PFERR_USER_MASK;
54987b7a 4708 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4709
4710 return t_gpa;
4711}
4712
ab9ae313
AK		 4713gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4714 struct x86_exception *exception)
1871c602
GN		 4715{
4716 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4717 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4718}
4719
ab9ae313
AK		 4720 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4721 struct x86_exception *exception)
1871c602
GN		 4722{
4723 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4724 access |= PFERR_FETCH_MASK;
ab9ae313 4725 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4726}
4727
ab9ae313
AK		 4728gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4729 struct x86_exception *exception)
1871c602
GN		 4730{
4731 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4732 access |= PFERR_WRITE_MASK;
ab9ae313 4733 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4734}
4735
4736/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4737gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4738 struct x86_exception *exception)
1871c602 4739{
ab9ae313 4740 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4741}
4742
4743static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4744 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4745 struct x86_exception *exception)
bbd9b64e
CO		 4746{
4747 void *data = val;
10589a46 4748 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4749
4750 while (bytes) {
14dfe855 4751 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4752 exception);
bbd9b64e 4753 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4754 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4755 int ret;
4756
bcc55cba 4757 if (gpa == UNMAPPED_GVA)
ab9ae313 4758 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4759 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4760 offset, toread);
10589a46 4761 if (ret < 0) {
c3cd7ffa 4762 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4763 goto out;
4764 }
bbd9b64e 4765
77c2002e
IE		 4766 bytes -= toread;
4767 data += toread;
4768 addr += toread;
bbd9b64e 4769 }
10589a46 4770out:
10589a46 4771 return r;
bbd9b64e 4772}
77c2002e 4773
1871c602 4774/* used for instruction fetching */
0f65dd70
AK		 4775static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4776 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4777 struct x86_exception *exception)
1871c602 4778{
0f65dd70 4779 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4780 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4781 unsigned offset;
4782 int ret;
0f65dd70 4783
44583cba
PB		 4784 /* Inline kvm_read_guest_virt_helper for speed. */
4785 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4786 exception);
4787 if (unlikely(gpa == UNMAPPED_GVA))
4788 return X86EMUL_PROPAGATE_FAULT;
4789
4790 offset = addr & (PAGE_SIZE-1);
4791 if (WARN_ON(offset + bytes > PAGE_SIZE))
4792 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4793 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4794 offset, bytes);
44583cba
PB		 4795 if (unlikely(ret < 0))
4796 return X86EMUL_IO_NEEDED;
4797
4798 return X86EMUL_CONTINUE;
1871c602
GN		 4799}
4800
ce14e868 4801int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 4802 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4803 struct x86_exception *exception)
1871c602
GN		 4804{
4805 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4806
1871c602 4807 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4808 exception);
1871c602 4809}
064aea77 4810EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4811
ce14e868
PB		 4812static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4813 gva_t addr, void *val, unsigned int bytes,
4814 struct x86_exception *exception)
1871c602 4815{
0f65dd70 4816 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4817 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4818}
4819
7a036a6f
RK		 4820static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4821 unsigned long addr, void *val, unsigned int bytes)
4822{
4823 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4824 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4825
4826 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4827}
4828
ce14e868
PB		 4829static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4830 struct kvm_vcpu *vcpu, u32 access,
4831 struct x86_exception *exception)
77c2002e
IE		 4832{
4833 void *data = val;
4834 int r = X86EMUL_CONTINUE;
4835
4836 while (bytes) {
14dfe855 4837 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 4838 access,
ab9ae313 4839 exception);
77c2002e
IE		 4840 unsigned offset = addr & (PAGE_SIZE-1);
4841 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4842 int ret;
4843
bcc55cba 4844 if (gpa == UNMAPPED_GVA)
ab9ae313 4845 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4846 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4847 if (ret < 0) {
c3cd7ffa 4848 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4849 goto out;
4850 }
4851
4852 bytes -= towrite;
4853 data += towrite;
4854 addr += towrite;
4855 }
4856out:
4857 return r;
4858}
ce14e868
PB		 4859
4860static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
4861 unsigned int bytes, struct x86_exception *exception)
4862{
4863 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4864
4865 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4866 PFERR_WRITE_MASK, exception);
4867}
4868
4869int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4870 unsigned int bytes, struct x86_exception *exception)
4871{
4872 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4873 PFERR_WRITE_MASK, exception);
4874}
6a4d7550 4875EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4876
082d06ed
WL		 4877int handle_ud(struct kvm_vcpu *vcpu)
4878{
6c86eedc 4879 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4880 enum emulation_result er;
6c86eedc
WL		 4881 char sig[5]; /* ud2; .ascii "kvm" */
4882 struct x86_exception e;
4883
4884 if (force_emulation_prefix &&
4885 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt,
4886 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 &&
4887 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4888 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4889 emul_type = 0;
4890 }
082d06ed 4891
6c86eedc 4892 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4893 if (er == EMULATE_USER_EXIT)
4894 return 0;
4895 if (er != EMULATE_DONE)
4896 kvm_queue_exception(vcpu, UD_VECTOR);
4897 return 1;
4898}
4899EXPORT_SYMBOL_GPL(handle_ud);
4900
0f89b207
TL		 4901static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4902 gpa_t gpa, bool write)
4903{
4904 /* For APIC access vmexit */
4905 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4906 return 1;
4907
4908 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4909 trace_vcpu_match_mmio(gva, gpa, write, true);
4910 return 1;
4911 }
4912
4913 return 0;
4914}
4915
af7cc7d1
XG		 4916static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4917 gpa_t *gpa, struct x86_exception *exception,
4918 bool write)
4919{
97d64b78
AK		 4920 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4921 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4922
be94f6b7
HH		 4923 /*
4924 * currently PKRU is only applied to ept enabled guest so
4925 * there is no pkey in EPT page table for L1 guest or EPT
4926 * shadow page table for L2 guest.
4927 */
97d64b78 4928 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4929 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4930 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4931 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4932 (gva & (PAGE_SIZE - 1));
4f022648 4933 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4934 return 1;
4935 }
4936
af7cc7d1
XG		 4937 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4938
4939 if (*gpa == UNMAPPED_GVA)
4940 return -1;
4941
0f89b207 4942 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4943}
4944
3200f405 4945int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4946 const void *val, int bytes)
bbd9b64e
CO		 4947{
4948 int ret;
4949
54bf36aa 4950 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4951 if (ret < 0)
bbd9b64e 4952 return 0;
0eb05bf2 4953 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4954 return 1;
4955}
4956
77d197b2
XG		 4957struct read_write_emulator_ops {
4958 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4959 int bytes);
4960 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4961 void *val, int bytes);
4962 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4963 int bytes, void *val);
4964 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4965 void *val, int bytes);
4966 bool write;
4967};
4968
4969static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4970{
4971 if (vcpu->mmio_read_completed) {
77d197b2 4972 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4973 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4974 vcpu->mmio_read_completed = 0;
4975 return 1;
4976 }
4977
4978 return 0;
4979}
4980
4981static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4982 void *val, int bytes)
4983{
54bf36aa 4984 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4985}
4986
4987static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4988 void *val, int bytes)
4989{
4990 return emulator_write_phys(vcpu, gpa, val, bytes);
4991}
4992
4993static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4994{
e39d200f 4995 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4996 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4997}
4998
4999static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5000 void *val, int bytes)
5001{
e39d200f 5002 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5003 return X86EMUL_IO_NEEDED;
5004}
5005
5006static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5007 void *val, int bytes)
5008{
f78146b0
AK		 5009 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5010
87da7e66 5011 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5012 return X86EMUL_CONTINUE;
5013}
5014
0fbe9b0b 5015static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5016 .read_write_prepare = read_prepare,
5017 .read_write_emulate = read_emulate,
5018 .read_write_mmio = vcpu_mmio_read,
5019 .read_write_exit_mmio = read_exit_mmio,
5020};
5021
0fbe9b0b 5022static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5023 .read_write_emulate = write_emulate,
5024 .read_write_mmio = write_mmio,
5025 .read_write_exit_mmio = write_exit_mmio,
5026 .write = true,
5027};
5028
22388a3c
XG		 5029static int emulator_read_write_onepage(unsigned long addr, void *val,
5030 unsigned int bytes,
5031 struct x86_exception *exception,
5032 struct kvm_vcpu *vcpu,
0fbe9b0b 5033 const struct read_write_emulator_ops *ops)
bbd9b64e 5034{
af7cc7d1
XG		 5035 gpa_t gpa;
5036 int handled, ret;
22388a3c 5037 bool write = ops->write;
f78146b0 5038 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5039 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5040
5041 /*
5042 * If the exit was due to a NPF we may already have a GPA.
5043 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5044 * Note, this cannot be used on string operations since string
5045 * operation using rep will only have the initial GPA from the NPF
5046 * occurred.
5047 */
5048 if (vcpu->arch.gpa_available &&
5049 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5050 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5051 gpa = vcpu->arch.gpa_val;
5052 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5053 } else {
5054 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5055 if (ret < 0)
5056 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5057 }
10589a46 5058
618232e2 5059 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5060 return X86EMUL_CONTINUE;
5061
bbd9b64e
CO		 5062 /*
5063 * Is this MMIO handled locally?
5064 */
22388a3c 5065 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5066 if (handled == bytes)
bbd9b64e 5067 return X86EMUL_CONTINUE;
bbd9b64e 5068
70252a10
AK		 5069 gpa += handled;
5070 bytes -= handled;
5071 val += handled;
5072
87da7e66
XG		 5073 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5074 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5075 frag->gpa = gpa;
5076 frag->data = val;
5077 frag->len = bytes;
f78146b0 5078 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5079}
5080
52eb5a6d
XL		 5081static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5082 unsigned long addr,
22388a3c
XG		 5083 void *val, unsigned int bytes,
5084 struct x86_exception *exception,
0fbe9b0b 5085 const struct read_write_emulator_ops *ops)
bbd9b64e 5086{
0f65dd70 5087 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5088 gpa_t gpa;
5089 int rc;
5090
5091 if (ops->read_write_prepare &&
5092 ops->read_write_prepare(vcpu, val, bytes))
5093 return X86EMUL_CONTINUE;
5094
5095 vcpu->mmio_nr_fragments = 0;
0f65dd70 5096
bbd9b64e
CO		 5097 /* Crossing a page boundary? */
5098 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5099 int now;
bbd9b64e
CO		 5100
5101 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5102 rc = emulator_read_write_onepage(addr, val, now, exception,
5103 vcpu, ops);
5104
bbd9b64e
CO		 5105 if (rc != X86EMUL_CONTINUE)
5106 return rc;
5107 addr += now;
bac15531
NA		 5108 if (ctxt->mode != X86EMUL_MODE_PROT64)
5109 addr = (u32)addr;
bbd9b64e
CO		 5110 val += now;
5111 bytes -= now;
5112 }
22388a3c 5113
f78146b0
AK		 5114 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5115 vcpu, ops);
5116 if (rc != X86EMUL_CONTINUE)
5117 return rc;
5118
5119 if (!vcpu->mmio_nr_fragments)
5120 return rc;
5121
5122 gpa = vcpu->mmio_fragments[0].gpa;
5123
5124 vcpu->mmio_needed = 1;
5125 vcpu->mmio_cur_fragment = 0;
5126
87da7e66 5127 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5128 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5129 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5130 vcpu->run->mmio.phys_addr = gpa;
5131
5132 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5133}
5134
5135static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5136 unsigned long addr,
5137 void *val,
5138 unsigned int bytes,
5139 struct x86_exception *exception)
5140{
5141 return emulator_read_write(ctxt, addr, val, bytes,
5142 exception, &read_emultor);
5143}
5144
52eb5a6d 5145static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5146 unsigned long addr,
5147 const void *val,
5148 unsigned int bytes,
5149 struct x86_exception *exception)
5150{
5151 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5152 exception, &write_emultor);
bbd9b64e 5153}
bbd9b64e 5154
daea3e73
AK		 5155#define CMPXCHG_TYPE(t, ptr, old, new) \
5156 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5157
5158#ifdef CONFIG_X86_64
5159# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5160#else
5161# define CMPXCHG64(ptr, old, new) \
9749a6c0 5162 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5163#endif
5164
0f65dd70
AK		 5165static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5166 unsigned long addr,
bbd9b64e
CO		 5167 const void *old,
5168 const void *new,
5169 unsigned int bytes,
0f65dd70 5170 struct x86_exception *exception)
bbd9b64e 5171{
0f65dd70 5172 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5173 gpa_t gpa;
5174 struct page *page;
5175 char *kaddr;
5176 bool exchanged;
2bacc55c 5177
daea3e73
AK		 5178 /* guests cmpxchg8b have to be emulated atomically */
5179 if (bytes > 8 || (bytes & (bytes - 1)))
5180 goto emul_write;
10589a46 5181
daea3e73 5182 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5183
daea3e73
AK		 5184 if (gpa == UNMAPPED_GVA ||
5185 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5186 goto emul_write;
2bacc55c 5187
daea3e73
AK		 5188 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5189 goto emul_write;
72dc67a6 5190
54bf36aa 5191 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5192 if (is_error_page(page))
c19b8bd6 5193 goto emul_write;
72dc67a6 5194
8fd75e12 5195 kaddr = kmap_atomic(page);
daea3e73
AK		 5196 kaddr += offset_in_page(gpa);
5197 switch (bytes) {
5198 case 1:
5199 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5200 break;
5201 case 2:
5202 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5203 break;
5204 case 4:
5205 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5206 break;
5207 case 8:
5208 exchanged = CMPXCHG64(kaddr, old, new);
5209 break;
5210 default:
5211 BUG();
2bacc55c 5212 }
8fd75e12 5213 kunmap_atomic(kaddr);
daea3e73
AK		 5214 kvm_release_page_dirty(page);
5215
5216 if (!exchanged)
5217 return X86EMUL_CMPXCHG_FAILED;
5218
54bf36aa 5219 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5220 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5221
5222 return X86EMUL_CONTINUE;
4a5f48f6 5223
3200f405 5224emul_write:
daea3e73 5225 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5226
0f65dd70 5227 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5228}
5229
cf8f70bf
GN		 5230static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5231{
cbfc6c91 5232 int r = 0, i;
cf8f70bf 5233
cbfc6c91
WL		 5234 for (i = 0; i < vcpu->arch.pio.count; i++) {
5235 if (vcpu->arch.pio.in)
5236 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5237 vcpu->arch.pio.size, pd);
5238 else
5239 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5240 vcpu->arch.pio.port, vcpu->arch.pio.size,
5241 pd);
5242 if (r)
5243 break;
5244 pd += vcpu->arch.pio.size;
5245 }
cf8f70bf
GN		 5246 return r;
5247}
5248
6f6fbe98
XG		 5249static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5250 unsigned short port, void *val,
5251 unsigned int count, bool in)
cf8f70bf 5252{
cf8f70bf 5253 vcpu->arch.pio.port = port;
6f6fbe98 5254 vcpu->arch.pio.in = in;
7972995b 5255 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5256 vcpu->arch.pio.size = size;
5257
5258 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5259 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5260 return 1;
5261 }
5262
5263 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5264 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5265 vcpu->run->io.size = size;
5266 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5267 vcpu->run->io.count = count;
5268 vcpu->run->io.port = port;
5269
5270 return 0;
5271}
5272
6f6fbe98
XG		 5273static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5274 int size, unsigned short port, void *val,
5275 unsigned int count)
cf8f70bf 5276{
ca1d4a9e 5277 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5278 int ret;
ca1d4a9e 5279
6f6fbe98
XG		 5280 if (vcpu->arch.pio.count)
5281 goto data_avail;
cf8f70bf 5282
cbfc6c91
WL		 5283 memset(vcpu->arch.pio_data, 0, size * count);
5284
6f6fbe98
XG		 5285 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5286 if (ret) {
5287data_avail:
5288 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5289 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5290 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5291 return 1;
5292 }
5293
cf8f70bf
GN		 5294 return 0;
5295}
5296
6f6fbe98
XG		 5297static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5298 int size, unsigned short port,
5299 const void *val, unsigned int count)
5300{
5301 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5302
5303 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5304 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5305 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5306}
5307
bbd9b64e
CO		 5308static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5309{
5310 return kvm_x86_ops->get_segment_base(vcpu, seg);
5311}
5312
3cb16fe7 5313static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5314{
3cb16fe7 5315 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5316}
5317
ae6a2375 5318static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5319{
5320 if (!need_emulate_wbinvd(vcpu))
5321 return X86EMUL_CONTINUE;
5322
5323 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5324 int cpu = get_cpu();
5325
5326 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5327 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5328 wbinvd_ipi, NULL, 1);
2eec7343 5329 put_cpu();
f5f48ee1 5330 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5331 } else
5332 wbinvd();
f5f48ee1
SY		 5333 return X86EMUL_CONTINUE;
5334}
5cb56059
JS		 5335
5336int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5337{
6affcbed
KH		 5338 kvm_emulate_wbinvd_noskip(vcpu);
5339 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5340}
f5f48ee1
SY		 5341EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5342
5cb56059
JS		 5343
5344
bcaf5cc5
AK		 5345static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5346{
5cb56059 5347 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5348}
5349
52eb5a6d
XL		 5350static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5351 unsigned long *dest)
bbd9b64e 5352{
16f8a6f9 5353 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5354}
5355
52eb5a6d
XL		 5356static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5357 unsigned long value)
bbd9b64e 5358{
338dbc97 5359
717746e3 5360 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5361}
5362
52a46617 5363static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5364{
52a46617 5365 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5366}
5367
717746e3 5368static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5369{
717746e3 5370 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5371 unsigned long value;
5372
5373 switch (cr) {
5374 case 0:
5375 value = kvm_read_cr0(vcpu);
5376 break;
5377 case 2:
5378 value = vcpu->arch.cr2;
5379 break;
5380 case 3:
9f8fe504 5381 value = kvm_read_cr3(vcpu);
52a46617
GN		 5382 break;
5383 case 4:
5384 value = kvm_read_cr4(vcpu);
5385 break;
5386 case 8:
5387 value = kvm_get_cr8(vcpu);
5388 break;
5389 default:
a737f256 5390 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5391 return 0;
5392 }
5393
5394 return value;
5395}
5396
717746e3 5397static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5398{
717746e3 5399 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5400 int res = 0;
5401
52a46617
GN		 5402 switch (cr) {
5403 case 0:
49a9b07e 5404 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5405 break;
5406 case 2:
5407 vcpu->arch.cr2 = val;
5408 break;
5409 case 3:
2390218b 5410 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5411 break;
5412 case 4:
a83b29c6 5413 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5414 break;
5415 case 8:
eea1cff9 5416 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5417 break;
5418 default:
a737f256 5419 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5420 res = -1;
52a46617 5421 }
0f12244f
GN		 5422
5423 return res;
52a46617
GN		 5424}
5425
717746e3 5426static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5427{
717746e3 5428 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5429}
5430
4bff1e86 5431static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5432{
4bff1e86 5433 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5434}
5435
4bff1e86 5436static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5437{
4bff1e86 5438 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5439}
5440
1ac9d0cf
AK		 5441static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5442{
5443 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5444}
5445
5446static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5447{
5448 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5449}
5450
4bff1e86
AK		 5451static unsigned long emulator_get_cached_segment_base(
5452 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5453{
4bff1e86 5454 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5455}
5456
1aa36616
AK		 5457static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5458 struct desc_struct *desc, u32 *base3,
5459 int seg)
2dafc6c2
GN		 5460{
5461 struct kvm_segment var;
5462
4bff1e86 5463 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5464 *selector = var.selector;
2dafc6c2 5465
378a8b09
GN		 5466 if (var.unusable) {
5467 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5468 if (base3)
5469 *base3 = 0;
2dafc6c2 5470 return false;
378a8b09 5471 }
2dafc6c2
GN		 5472
5473 if (var.g)
5474 var.limit >>= 12;
5475 set_desc_limit(desc, var.limit);
5476 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5477#ifdef CONFIG_X86_64
5478 if (base3)
5479 *base3 = var.base >> 32;
5480#endif
2dafc6c2
GN		 5481 desc->type = var.type;
5482 desc->s = var.s;
5483 desc->dpl = var.dpl;
5484 desc->p = var.present;
5485 desc->avl = var.avl;
5486 desc->l = var.l;
5487 desc->d = var.db;
5488 desc->g = var.g;
5489
5490 return true;
5491}
5492
1aa36616
AK		 5493static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5494 struct desc_struct *desc, u32 base3,
5495 int seg)
2dafc6c2 5496{
4bff1e86 5497 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5498 struct kvm_segment var;
5499
1aa36616 5500 var.selector = selector;
2dafc6c2 5501 var.base = get_desc_base(desc);
5601d05b
GN		 5502#ifdef CONFIG_X86_64
5503 var.base |= ((u64)base3) << 32;
5504#endif
2dafc6c2
GN		 5505 var.limit = get_desc_limit(desc);
5506 if (desc->g)
5507 var.limit = (var.limit << 12) | 0xfff;
5508 var.type = desc->type;
2dafc6c2
GN		 5509 var.dpl = desc->dpl;
5510 var.db = desc->d;
5511 var.s = desc->s;
5512 var.l = desc->l;
5513 var.g = desc->g;
5514 var.avl = desc->avl;
5515 var.present = desc->p;
5516 var.unusable = !var.present;
5517 var.padding = 0;
5518
5519 kvm_set_segment(vcpu, &var, seg);
5520 return;
5521}
5522
717746e3
AK		 5523static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5524 u32 msr_index, u64 *pdata)
5525{
609e36d3
PB		 5526 struct msr_data msr;
5527 int r;
5528
5529 msr.index = msr_index;
5530 msr.host_initiated = false;
5531 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5532 if (r)
5533 return r;
5534
5535 *pdata = msr.data;
5536 return 0;
717746e3
AK		 5537}
5538
5539static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5540 u32 msr_index, u64 data)
5541{
8fe8ab46
WA		 5542 struct msr_data msr;
5543
5544 msr.data = data;
5545 msr.index = msr_index;
5546 msr.host_initiated = false;
5547 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5548}
5549
64d60670
PB		 5550static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5551{
5552 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5553
5554 return vcpu->arch.smbase;
5555}
5556
5557static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5558{
5559 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5560
5561 vcpu->arch.smbase = smbase;
5562}
5563
67f4d428
NA		 5564static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5565 u32 pmc)
5566{
c6702c9d 5567 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5568}
5569
222d21aa
AK		 5570static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5571 u32 pmc, u64 *pdata)
5572{
c6702c9d 5573 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5574}
5575
6c3287f7
AK		 5576static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5577{
5578 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5579}
5580
2953538e 5581static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5582 struct x86_instruction_info *info,
c4f035c6
AK		 5583 enum x86_intercept_stage stage)
5584{
2953538e 5585 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5586}
5587
e911eb3b
YZ		 5588static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5589 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5590{
e911eb3b 5591 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5592}
5593
dd856efa
AK		 5594static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5595{
5596 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5597}
5598
5599static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5600{
5601 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5602}
5603
801806d9
NA		 5604static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5605{
5606 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5607}
5608
6ed071f0
LP		 5609static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5610{
5611 return emul_to_vcpu(ctxt)->arch.hflags;
5612}
5613
5614static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5615{
5616 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5617}
5618
0234bf88
LP		 5619static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5620{
5621 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5622}
5623
0225fb50 5624static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5625 .read_gpr = emulator_read_gpr,
5626 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5627 .read_std = emulator_read_std,
5628 .write_std = emulator_write_std,
7a036a6f 5629 .read_phys = kvm_read_guest_phys_system,
1871c602 5630 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5631 .read_emulated = emulator_read_emulated,
5632 .write_emulated = emulator_write_emulated,
5633 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5634 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5635 .pio_in_emulated = emulator_pio_in_emulated,
5636 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5637 .get_segment = emulator_get_segment,
5638 .set_segment = emulator_set_segment,
5951c442 5639 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5640 .get_gdt = emulator_get_gdt,
160ce1f1 5641 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5642 .set_gdt = emulator_set_gdt,
5643 .set_idt = emulator_set_idt,
52a46617
GN		 5644 .get_cr = emulator_get_cr,
5645 .set_cr = emulator_set_cr,
9c537244 5646 .cpl = emulator_get_cpl,
35aa5375
GN		 5647 .get_dr = emulator_get_dr,
5648 .set_dr = emulator_set_dr,
64d60670
PB		 5649 .get_smbase = emulator_get_smbase,
5650 .set_smbase = emulator_set_smbase,
717746e3
AK		 5651 .set_msr = emulator_set_msr,
5652 .get_msr = emulator_get_msr,
67f4d428 5653 .check_pmc = emulator_check_pmc,
222d21aa 5654 .read_pmc = emulator_read_pmc,
6c3287f7 5655 .halt = emulator_halt,
bcaf5cc5 5656 .wbinvd = emulator_wbinvd,
d6aa1000 5657 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5658 .intercept = emulator_intercept,
bdb42f5a 5659 .get_cpuid = emulator_get_cpuid,
801806d9 5660 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5661 .get_hflags = emulator_get_hflags,
5662 .set_hflags = emulator_set_hflags,
0234bf88 5663 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5664};
5665
95cb2295
GN		 5666static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5667{
37ccdcbe 5668 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5669 /*
5670 * an sti; sti; sequence only disable interrupts for the first
5671 * instruction. So, if the last instruction, be it emulated or
5672 * not, left the system with the INT_STI flag enabled, it
5673 * means that the last instruction is an sti. We should not
5674 * leave the flag on in this case. The same goes for mov ss
5675 */
37ccdcbe
PB		 5676 if (int_shadow & mask)
5677 mask = 0;
6addfc42 5678 if (unlikely(int_shadow || mask)) {
95cb2295 5679 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5680 if (!mask)
5681 kvm_make_request(KVM_REQ_EVENT, vcpu);
5682 }
95cb2295
GN		 5683}
5684
ef54bcfe 5685static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5686{
5687 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5688 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5689 return kvm_propagate_fault(vcpu, &ctxt->exception);
5690
5691 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5692 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5693 ctxt->exception.error_code);
54b8486f 5694 else
da9cb575 5695 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5696 return false;
54b8486f
GN		 5697}
5698
8ec4722d
MG		 5699static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5700{
adf52235 5701 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5702 int cs_db, cs_l;
5703
8ec4722d
MG		 5704 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5705
adf52235 5706 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5707 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5708
adf52235
TY		 5709 ctxt->eip = kvm_rip_read(vcpu);
5710 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5711 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5712 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5713 cs_db ? X86EMUL_MODE_PROT32 :
5714 X86EMUL_MODE_PROT16;
a584539b 5715 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5716 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5717 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5718
dd856efa 5719 init_decode_cache(ctxt);
7ae441ea 5720 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5721}
5722
71f9833b 5723int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5724{
9d74191a 5725 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5726 int ret;
5727
5728 init_emulate_ctxt(vcpu);
5729
9dac77fa
AK		 5730 ctxt->op_bytes = 2;
5731 ctxt->ad_bytes = 2;
5732 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5733 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5734
5735 if (ret != X86EMUL_CONTINUE)
5736 return EMULATE_FAIL;
5737
9dac77fa 5738 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5739 kvm_rip_write(vcpu, ctxt->eip);
5740 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5741
63995653
MG		 5742 return EMULATE_DONE;
5743}
5744EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5745
e2366171 5746static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5747{
fc3a9157
JR		 5748 int r = EMULATE_DONE;
5749
6d77dbfc
GN		 5750 ++vcpu->stat.insn_emulation_fail;
5751 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5752
5753 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5754 return EMULATE_FAIL;
5755
a2b9e6c1 5756 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5757 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5758 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5759 vcpu->run->internal.ndata = 0;
1f4dcb3b 5760 r = EMULATE_USER_EXIT;
fc3a9157 5761 }
e2366171 5762
6d77dbfc 5763 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5764
5765 return r;
6d77dbfc
GN		 5766}
5767
93c05d3e 5768static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5769 bool write_fault_to_shadow_pgtable,
5770 int emulation_type)
a6f177ef 5771{
95b3cf69 5772 gpa_t gpa = cr2;
ba049e93 5773 kvm_pfn_t pfn;
a6f177ef 5774
991eebf9
GN		 5775 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5776 return false;
5777
95b3cf69
XG		 5778 if (!vcpu->arch.mmu.direct_map) {
5779 /*
5780 * Write permission should be allowed since only
5781 * write access need to be emulated.
5782 */
5783 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5784
95b3cf69
XG		 5785 /*
5786 * If the mapping is invalid in guest, let cpu retry
5787 * it to generate fault.
5788 */
5789 if (gpa == UNMAPPED_GVA)
5790 return true;
5791 }
a6f177ef 5792
8e3d9d06
XG		 5793 /*
5794 * Do not retry the unhandleable instruction if it faults on the
5795 * readonly host memory, otherwise it will goto a infinite loop:
5796 * retry instruction -> write #PF -> emulation fail -> retry
5797 * instruction -> ...
5798 */
5799 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5800
5801 /*
5802 * If the instruction failed on the error pfn, it can not be fixed,
5803 * report the error to userspace.
5804 */
5805 if (is_error_noslot_pfn(pfn))
5806 return false;
5807
5808 kvm_release_pfn_clean(pfn);
5809
5810 /* The instructions are well-emulated on direct mmu. */
5811 if (vcpu->arch.mmu.direct_map) {
5812 unsigned int indirect_shadow_pages;
5813
5814 spin_lock(&vcpu->kvm->mmu_lock);
5815 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5816 spin_unlock(&vcpu->kvm->mmu_lock);
5817
5818 if (indirect_shadow_pages)
5819 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5820
a6f177ef 5821 return true;
8e3d9d06 5822 }
a6f177ef 5823
95b3cf69
XG		 5824 /*
5825 * if emulation was due to access to shadowed page table
5826 * and it failed try to unshadow page and re-enter the
5827 * guest to let CPU execute the instruction.
5828 */
5829 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5830
5831 /*
5832 * If the access faults on its page table, it can not
5833 * be fixed by unprotecting shadow page and it should
5834 * be reported to userspace.
5835 */
5836 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5837}
5838
1cb3f3ae
XG		 5839static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5840 unsigned long cr2, int emulation_type)
5841{
5842 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5843 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5844
5845 last_retry_eip = vcpu->arch.last_retry_eip;
5846 last_retry_addr = vcpu->arch.last_retry_addr;
5847
5848 /*
5849 * If the emulation is caused by #PF and it is non-page_table
5850 * writing instruction, it means the VM-EXIT is caused by shadow
5851 * page protected, we can zap the shadow page and retry this
5852 * instruction directly.
5853 *
5854 * Note: if the guest uses a non-page-table modifying instruction
5855 * on the PDE that points to the instruction, then we will unmap
5856 * the instruction and go to an infinite loop. So, we cache the
5857 * last retried eip and the last fault address, if we meet the eip
5858 * and the address again, we can break out of the potential infinite
5859 * loop.
5860 */
5861 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5862
5863 if (!(emulation_type & EMULTYPE_RETRY))
5864 return false;
5865
5866 if (x86_page_table_writing_insn(ctxt))
5867 return false;
5868
5869 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5870 return false;
5871
5872 vcpu->arch.last_retry_eip = ctxt->eip;
5873 vcpu->arch.last_retry_addr = cr2;
5874
5875 if (!vcpu->arch.mmu.direct_map)
5876 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5877
22368028 5878 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5879
5880 return true;
5881}
5882
716d51ab
GN		 5883static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5884static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5885
64d60670 5886static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5887{
64d60670 5888 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5889 /* This is a good place to trace that we are exiting SMM. */
5890 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5891
c43203ca
PB		 5892 /* Process a latched INIT or SMI, if any. */
5893 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5894 }
699023e2
PB		 5895
5896 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5897}
5898
5899static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5900{
5901 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5902
a584539b 5903 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5904
5905 if (changed & HF_SMM_MASK)
5906 kvm_smm_changed(vcpu);
a584539b
PB		 5907}
5908
4a1e10d5
PB		 5909static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5910 unsigned long *db)
5911{
5912 u32 dr6 = 0;
5913 int i;
5914 u32 enable, rwlen;
5915
5916 enable = dr7;
5917 rwlen = dr7 >> 16;
5918 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5919 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5920 dr6 |= (1 << i);
5921 return dr6;
5922}
5923
c8401dda 5924static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5925{
5926 struct kvm_run *kvm_run = vcpu->run;
5927
c8401dda
PB		 5928 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5929 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5930 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5931 kvm_run->debug.arch.exception = DB_VECTOR;
5932 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5933 *r = EMULATE_USER_EXIT;
5934 } else {
5935 /*
5936 * "Certain debug exceptions may clear bit 0-3. The
5937 * remaining contents of the DR6 register are never
5938 * cleared by the processor".
5939 */
5940 vcpu->arch.dr6 &= ~15;
5941 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5942 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5943 }
5944}
5945
6affcbed
KH		 5946int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5947{
5948 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5949 int r = EMULATE_DONE;
5950
5951 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5952
5953 /*
5954 * rflags is the old, "raw" value of the flags. The new value has
5955 * not been saved yet.
5956 *
5957 * This is correct even for TF set by the guest, because "the
5958 * processor will not generate this exception after the instruction
5959 * that sets the TF flag".
5960 */
5961 if (unlikely(rflags & X86_EFLAGS_TF))
5962 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5963 return r == EMULATE_DONE;
5964}
5965EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5966
4a1e10d5
PB		 5967static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5968{
4a1e10d5
PB		 5969 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5970 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5971 struct kvm_run *kvm_run = vcpu->run;
5972 unsigned long eip = kvm_get_linear_rip(vcpu);
5973 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5974 vcpu->arch.guest_debug_dr7,
5975 vcpu->arch.eff_db);
5976
5977 if (dr6 != 0) {
6f43ed01 5978 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5979 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5980 kvm_run->debug.arch.exception = DB_VECTOR;
5981 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5982 *r = EMULATE_USER_EXIT;
5983 return true;
5984 }
5985 }
5986
4161a569
NA		 5987 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5988 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5989 unsigned long eip = kvm_get_linear_rip(vcpu);
5990 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5991 vcpu->arch.dr7,
5992 vcpu->arch.db);
5993
5994 if (dr6 != 0) {
5995 vcpu->arch.dr6 &= ~15;
6f43ed01 5996 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5997 kvm_queue_exception(vcpu, DB_VECTOR);
5998 *r = EMULATE_DONE;
5999 return true;
6000 }
6001 }
6002
6003 return false;
6004}
6005
04789b66
LA		 6006static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6007{
2d7921c4
AM		 6008 switch (ctxt->opcode_len) {
6009 case 1:
6010 switch (ctxt->b) {
6011 case 0xe4: /* IN */
6012 case 0xe5:
6013 case 0xec:
6014 case 0xed:
6015 case 0xe6: /* OUT */
6016 case 0xe7:
6017 case 0xee:
6018 case 0xef:
6019 case 0x6c: /* INS */
6020 case 0x6d:
6021 case 0x6e: /* OUTS */
6022 case 0x6f:
6023 return true;
6024 }
6025 break;
6026 case 2:
6027 switch (ctxt->b) {
6028 case 0x33: /* RDPMC */
6029 return true;
6030 }
6031 break;
04789b66
LA		 6032 }
6033
6034 return false;
6035}
6036
51d8b661
AP		 6037int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6038 unsigned long cr2,
dc25e89e
AP		 6039 int emulation_type,
6040 void *insn,
6041 int insn_len)
bbd9b64e 6042{
95cb2295 6043 int r;
9d74191a 6044 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6045 bool writeback = true;
93c05d3e 6046 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6047
93c05d3e
XG		 6048 /*
6049 * Clear write_fault_to_shadow_pgtable here to ensure it is
6050 * never reused.
6051 */
6052 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6053 kvm_clear_exception_queue(vcpu);
8d7d8102 6054
571008da 6055 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6056 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6057
6058 /*
6059 * We will reenter on the same instruction since
6060 * we do not set complete_userspace_io. This does not
6061 * handle watchpoints yet, those would be handled in
6062 * the emulate_ops.
6063 */
d391f120
VK		 6064 if (!(emulation_type & EMULTYPE_SKIP) &&
6065 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6066 return r;
6067
9d74191a
TY		 6068 ctxt->interruptibility = 0;
6069 ctxt->have_exception = false;
e0ad0b47 6070 ctxt->exception.vector = -1;
9d74191a 6071 ctxt->perm_ok = false;
bbd9b64e 6072
b51e974f 6073 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6074
9d74191a 6075 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6076
e46479f8 6077 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6078 ++vcpu->stat.insn_emulation;
1d2887e2 6079 if (r != EMULATION_OK) {
4005996e
AK		 6080 if (emulation_type & EMULTYPE_TRAP_UD)
6081 return EMULATE_FAIL;
991eebf9
GN		 6082 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6083 emulation_type))
bbd9b64e 6084 return EMULATE_DONE;
6ea6e843
PB		 6085 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6086 return EMULATE_DONE;
6d77dbfc
GN		 6087 if (emulation_type & EMULTYPE_SKIP)
6088 return EMULATE_FAIL;
e2366171 6089 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6090 }
6091 }
6092
04789b66
LA		 6093 if ((emulation_type & EMULTYPE_VMWARE) &&
6094 !is_vmware_backdoor_opcode(ctxt))
6095 return EMULATE_FAIL;
6096
ba8afb6b 6097 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6098 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6099 if (ctxt->eflags & X86_EFLAGS_RF)
6100 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6101 return EMULATE_DONE;
6102 }
6103
1cb3f3ae
XG		 6104 if (retry_instruction(ctxt, cr2, emulation_type))
6105 return EMULATE_DONE;
6106
7ae441ea 6107 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6108 changes registers values during IO operation */
7ae441ea
GN		 6109 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6110 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6111 emulator_invalidate_register_cache(ctxt);
7ae441ea 6112 }
4d2179e1 6113
5cd21917 6114restart:
0f89b207
TL		 6115 /* Save the faulting GPA (cr2) in the address field */
6116 ctxt->exception.address = cr2;
6117
9d74191a 6118 r = x86_emulate_insn(ctxt);
bbd9b64e 6119
775fde86
JR		 6120 if (r == EMULATION_INTERCEPTED)
6121 return EMULATE_DONE;
6122
d2ddd1c4 6123 if (r == EMULATION_FAILED) {
991eebf9
GN		 6124 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6125 emulation_type))
c3cd7ffa
GN		 6126 return EMULATE_DONE;
6127
e2366171 6128 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6129 }
6130
9d74191a 6131 if (ctxt->have_exception) {
d2ddd1c4 6132 r = EMULATE_DONE;
ef54bcfe
PB		 6133 if (inject_emulated_exception(vcpu))
6134 return r;
d2ddd1c4 6135 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6136 if (!vcpu->arch.pio.in) {
6137 /* FIXME: return into emulator if single-stepping. */
3457e419 6138 vcpu->arch.pio.count = 0;
0912c977 6139 } else {
7ae441ea 6140 writeback = false;
716d51ab
GN		 6141 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6142 }
ac0a48c3 6143 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6144 } else if (vcpu->mmio_needed) {
6145 if (!vcpu->mmio_is_write)
6146 writeback = false;
ac0a48c3 6147 r = EMULATE_USER_EXIT;
716d51ab 6148 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6149 } else if (r == EMULATION_RESTART)
5cd21917 6150 goto restart;
d2ddd1c4
GN		 6151 else
6152 r = EMULATE_DONE;
f850e2e6 6153
7ae441ea 6154 if (writeback) {
6addfc42 6155 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6156 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6157 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6158 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6159 if (r == EMULATE_DONE &&
6160 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6161 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6162 if (!ctxt->have_exception ||
6163 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6164 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6165
6166 /*
6167 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6168 * do nothing, and it will be requested again as soon as
6169 * the shadow expires. But we still need to check here,
6170 * because POPF has no interrupt shadow.
6171 */
6172 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6173 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6174 } else
6175 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6176
6177 return r;
de7d789a 6178}
51d8b661 6179EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6180
dca7f128
SC		 6181static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6182 unsigned short port)
de7d789a 6183{
cf8f70bf 6184 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6185 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6186 size, port, &val, 1);
cf8f70bf 6187 /* do not return to emulator after return from userspace */
7972995b 6188 vcpu->arch.pio.count = 0;
de7d789a
CO		 6189 return ret;
6190}
de7d789a 6191
8370c3d0
TL		 6192static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6193{
6194 unsigned long val;
6195
6196 /* We should only ever be called with arch.pio.count equal to 1 */
6197 BUG_ON(vcpu->arch.pio.count != 1);
6198
6199 /* For size less than 4 we merge, else we zero extend */
6200 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6201 : 0;
6202
6203 /*
6204 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6205 * the copy and tracing
6206 */
6207 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6208 vcpu->arch.pio.port, &val, 1);
6209 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6210
6211 return 1;
6212}
6213
dca7f128
SC		 6214static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6215 unsigned short port)
8370c3d0
TL		 6216{
6217 unsigned long val;
6218 int ret;
6219
6220 /* For size less than 4 we merge, else we zero extend */
6221 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6222
6223 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6224 &val, 1);
6225 if (ret) {
6226 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6227 return ret;
6228 }
6229
6230 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6231
6232 return 0;
6233}
dca7f128
SC		 6234
6235int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6236{
6237 int ret = kvm_skip_emulated_instruction(vcpu);
6238
6239 /*
6240 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6241 * KVM_EXIT_DEBUG here.
6242 */
6243 if (in)
6244 return kvm_fast_pio_in(vcpu, size, port) && ret;
6245 else
6246 return kvm_fast_pio_out(vcpu, size, port) && ret;
6247}
6248EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6249
251a5fd6 6250static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6251{
0a3aee0d 6252 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6253 return 0;
8cfdc000
ZA		 6254}
6255
6256static void tsc_khz_changed(void *data)
c8076604 6257{
8cfdc000
ZA		 6258 struct cpufreq_freqs *freq = data;
6259 unsigned long khz = 0;
6260
6261 if (data)
6262 khz = freq->new;
6263 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6264 khz = cpufreq_quick_get(raw_smp_processor_id());
6265 if (!khz)
6266 khz = tsc_khz;
0a3aee0d 6267 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6268}
6269
5fa4ec9c 6270#ifdef CONFIG_X86_64
0092e434
VK		 6271static void kvm_hyperv_tsc_notifier(void)
6272{
0092e434
VK		 6273 struct kvm *kvm;
6274 struct kvm_vcpu *vcpu;
6275 int cpu;
6276
6277 spin_lock(&kvm_lock);
6278 list_for_each_entry(kvm, &vm_list, vm_list)
6279 kvm_make_mclock_inprogress_request(kvm);
6280
6281 hyperv_stop_tsc_emulation();
6282
6283 /* TSC frequency always matches when on Hyper-V */
6284 for_each_present_cpu(cpu)
6285 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6286 kvm_max_guest_tsc_khz = tsc_khz;
6287
6288 list_for_each_entry(kvm, &vm_list, vm_list) {
6289 struct kvm_arch *ka = &kvm->arch;
6290
6291 spin_lock(&ka->pvclock_gtod_sync_lock);
6292
6293 pvclock_update_vm_gtod_copy(kvm);
6294
6295 kvm_for_each_vcpu(cpu, vcpu, kvm)
6296 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6297
6298 kvm_for_each_vcpu(cpu, vcpu, kvm)
6299 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6300
6301 spin_unlock(&ka->pvclock_gtod_sync_lock);
6302 }
6303 spin_unlock(&kvm_lock);
0092e434 6304}
5fa4ec9c 6305#endif
0092e434 6306
c8076604
GH		 6307static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6308 void *data)
6309{
6310 struct cpufreq_freqs *freq = data;
6311 struct kvm *kvm;
6312 struct kvm_vcpu *vcpu;
6313 int i, send_ipi = 0;
6314
8cfdc000
ZA		 6315 /*
6316 * We allow guests to temporarily run on slowing clocks,
6317 * provided we notify them after, or to run on accelerating
6318 * clocks, provided we notify them before. Thus time never
6319 * goes backwards.
6320 *
6321 * However, we have a problem. We can't atomically update
6322 * the frequency of a given CPU from this function; it is
6323 * merely a notifier, which can be called from any CPU.
6324 * Changing the TSC frequency at arbitrary points in time
6325 * requires a recomputation of local variables related to
6326 * the TSC for each VCPU. We must flag these local variables
6327 * to be updated and be sure the update takes place with the
6328 * new frequency before any guests proceed.
6329 *
6330 * Unfortunately, the combination of hotplug CPU and frequency
6331 * change creates an intractable locking scenario; the order
6332 * of when these callouts happen is undefined with respect to
6333 * CPU hotplug, and they can race with each other. As such,
6334 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6335 * undefined; you can actually have a CPU frequency change take
6336 * place in between the computation of X and the setting of the
6337 * variable. To protect against this problem, all updates of
6338 * the per_cpu tsc_khz variable are done in an interrupt
6339 * protected IPI, and all callers wishing to update the value
6340 * must wait for a synchronous IPI to complete (which is trivial
6341 * if the caller is on the CPU already). This establishes the
6342 * necessary total order on variable updates.
6343 *
6344 * Note that because a guest time update may take place
6345 * anytime after the setting of the VCPU's request bit, the
6346 * correct TSC value must be set before the request. However,
6347 * to ensure the update actually makes it to any guest which
6348 * starts running in hardware virtualization between the set
6349 * and the acquisition of the spinlock, we must also ping the
6350 * CPU after setting the request bit.
6351 *
6352 */
6353
c8076604
GH		 6354 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6355 return 0;
6356 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6357 return 0;
8cfdc000
ZA		 6358
6359 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6360
2f303b74 6361 spin_lock(&kvm_lock);
c8076604 6362 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6363 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6364 if (vcpu->cpu != freq->cpu)
6365 continue;
c285545f 6366 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6367 if (vcpu->cpu != smp_processor_id())
8cfdc000 6368 send_ipi = 1;
c8076604
GH		 6369 }
6370 }
2f303b74 6371 spin_unlock(&kvm_lock);
c8076604
GH		 6372
6373 if (freq->old < freq->new && send_ipi) {
6374 /*
6375 * We upscale the frequency. Must make the guest
6376 * doesn't see old kvmclock values while running with
6377 * the new frequency, otherwise we risk the guest sees
6378 * time go backwards.
6379 *
6380 * In case we update the frequency for another cpu
6381 * (which might be in guest context) send an interrupt
6382 * to kick the cpu out of guest context. Next time
6383 * guest context is entered kvmclock will be updated,
6384 * so the guest will not see stale values.
6385 */
8cfdc000 6386 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6387 }
6388 return 0;
6389}
6390
6391static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6392 .notifier_call = kvmclock_cpufreq_notifier
6393};
6394
251a5fd6 6395static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6396{
251a5fd6
SAS		 6397 tsc_khz_changed(NULL);
6398 return 0;
8cfdc000
ZA		 6399}
6400
b820cc0c
ZA		 6401static void kvm_timer_init(void)
6402{
c285545f 6403 max_tsc_khz = tsc_khz;
460dd42e 6404
b820cc0c 6405 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6406#ifdef CONFIG_CPU_FREQ
6407 struct cpufreq_policy policy;
758f588d
BP		 6408 int cpu;
6409
c285545f 6410 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6411 cpu = get_cpu();
6412 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6413 if (policy.cpuinfo.max_freq)
6414 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6415 put_cpu();
c285545f 6416#endif
b820cc0c
ZA		 6417 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6418 CPUFREQ_TRANSITION_NOTIFIER);
6419 }
c285545f 6420 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6421
73c1b41e 6422 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6423 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6424}
6425
dd60d217
AK		 6426DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6427EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6428
f5132b01 6429int kvm_is_in_guest(void)
ff9d07a0 6430{
086c9855 6431 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6432}
6433
6434static int kvm_is_user_mode(void)
6435{
6436 int user_mode = 3;
dcf46b94 6437
086c9855
AS		 6438 if (__this_cpu_read(current_vcpu))
6439 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6440
ff9d07a0
ZY		 6441 return user_mode != 0;
6442}
6443
6444static unsigned long kvm_get_guest_ip(void)
6445{
6446 unsigned long ip = 0;
dcf46b94 6447
086c9855
AS		 6448 if (__this_cpu_read(current_vcpu))
6449 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6450
ff9d07a0
ZY		 6451 return ip;
6452}
6453
6454static struct perf_guest_info_callbacks kvm_guest_cbs = {
6455 .is_in_guest = kvm_is_in_guest,
6456 .is_user_mode = kvm_is_user_mode,
6457 .get_guest_ip = kvm_get_guest_ip,
6458};
6459
ce88decf
XG		 6460static void kvm_set_mmio_spte_mask(void)
6461{
6462 u64 mask;
6463 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6464
6465 /*
6466 * Set the reserved bits and the present bit of an paging-structure
6467 * entry to generate page fault with PFER.RSV = 1.
6468 */
885032b9 6469 /* Mask the reserved physical address bits. */
d1431483 6470 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6471
885032b9 6472 /* Set the present bit. */
ce88decf
XG		 6473 mask |= 1ull;
6474
6475#ifdef CONFIG_X86_64
6476 /*
6477 * If reserved bit is not supported, clear the present bit to disable
6478 * mmio page fault.
6479 */
6480 if (maxphyaddr == 52)
6481 mask &= ~1ull;
6482#endif
6483
dcdca5fe 6484 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6485}
6486
16e8d74d
MT		 6487#ifdef CONFIG_X86_64
6488static void pvclock_gtod_update_fn(struct work_struct *work)
6489{
d828199e
MT		 6490 struct kvm *kvm;
6491
6492 struct kvm_vcpu *vcpu;
6493 int i;
6494
2f303b74 6495 spin_lock(&kvm_lock);
d828199e
MT		 6496 list_for_each_entry(kvm, &vm_list, vm_list)
6497 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6498 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6499 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6500 spin_unlock(&kvm_lock);
16e8d74d
MT		 6501}
6502
6503static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6504
6505/*
6506 * Notification about pvclock gtod data update.
6507 */
6508static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6509 void *priv)
6510{
6511 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6512 struct timekeeper *tk = priv;
6513
6514 update_pvclock_gtod(tk);
6515
6516 /* disable master clock if host does not trust, or does not
b0c39dc6 6517 * use, TSC based clocksource.
16e8d74d 6518 */
b0c39dc6 6519 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6520 atomic_read(&kvm_guest_has_master_clock) != 0)
6521 queue_work(system_long_wq, &pvclock_gtod_work);
6522
6523 return 0;
6524}
6525
6526static struct notifier_block pvclock_gtod_notifier = {
6527 .notifier_call = pvclock_gtod_notify,
6528};
6529#endif
6530
f8c16bba 6531int kvm_arch_init(void *opaque)
043405e1 6532{
b820cc0c 6533 int r;
6b61edf7 6534 struct kvm_x86_ops *ops = opaque;
f8c16bba 6535
f8c16bba
ZX		 6536 if (kvm_x86_ops) {
6537 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6538 r = -EEXIST;
6539 goto out;
f8c16bba
ZX		 6540 }
6541
6542 if (!ops->cpu_has_kvm_support()) {
6543 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6544 r = -EOPNOTSUPP;
6545 goto out;
f8c16bba
ZX		 6546 }
6547 if (ops->disabled_by_bios()) {
6548 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6549 r = -EOPNOTSUPP;
6550 goto out;
f8c16bba
ZX		 6551 }
6552
013f6a5d
MT		 6553 r = -ENOMEM;
6554 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6555 if (!shared_msrs) {
6556 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6557 goto out;
6558 }
6559
97db56ce
AK		 6560 r = kvm_mmu_module_init();
6561 if (r)
013f6a5d 6562 goto out_free_percpu;
97db56ce 6563
ce88decf 6564 kvm_set_mmio_spte_mask();
97db56ce 6565
f8c16bba 6566 kvm_x86_ops = ops;
920c8377 6567
7b52345e 6568 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6569 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6570 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6571 kvm_timer_init();
c8076604 6572
ff9d07a0
ZY		 6573 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6574
d366bf7e 6575 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6576 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6577
c5cc421b 6578 kvm_lapic_init();
16e8d74d
MT		 6579#ifdef CONFIG_X86_64
6580 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6581
5fa4ec9c 6582 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6583 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6584#endif
6585
f8c16bba 6586 return 0;
56c6d28a 6587
013f6a5d
MT		 6588out_free_percpu:
6589 free_percpu(shared_msrs);
56c6d28a 6590out:
56c6d28a 6591 return r;
043405e1 6592}
8776e519 6593
f8c16bba
ZX		 6594void kvm_arch_exit(void)
6595{
0092e434 6596#ifdef CONFIG_X86_64
5fa4ec9c 6597 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6598 clear_hv_tscchange_cb();
6599#endif
cef84c30 6600 kvm_lapic_exit();
ff9d07a0
ZY		 6601 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6602
888d256e
JK		 6603 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6604 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6605 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6606 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6607#ifdef CONFIG_X86_64
6608 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6609#endif
f8c16bba 6610 kvm_x86_ops = NULL;
56c6d28a 6611 kvm_mmu_module_exit();
013f6a5d 6612 free_percpu(shared_msrs);
56c6d28a 6613}
f8c16bba 6614
5cb56059 6615int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6616{
6617 ++vcpu->stat.halt_exits;
35754c98 6618 if (lapic_in_kernel(vcpu)) {
a4535290 6619 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6620 return 1;
6621 } else {
6622 vcpu->run->exit_reason = KVM_EXIT_HLT;
6623 return 0;
6624 }
6625}
5cb56059
JS		 6626EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6627
6628int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6629{
6affcbed
KH		 6630 int ret = kvm_skip_emulated_instruction(vcpu);
6631 /*
6632 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6633 * KVM_EXIT_DEBUG here.
6634 */
6635 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6636}
8776e519
HB		 6637EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6638
8ef81a9a 6639#ifdef CONFIG_X86_64
55dd00a7
MT		 6640static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6641 unsigned long clock_type)
6642{
6643 struct kvm_clock_pairing clock_pairing;
899a31f5 6644 struct timespec64 ts;
80fbd89c 6645 u64 cycle;
55dd00a7
MT		 6646 int ret;
6647
6648 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6649 return -KVM_EOPNOTSUPP;
6650
6651 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6652 return -KVM_EOPNOTSUPP;
6653
6654 clock_pairing.sec = ts.tv_sec;
6655 clock_pairing.nsec = ts.tv_nsec;
6656 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6657 clock_pairing.flags = 0;
6658
6659 ret = 0;
6660 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6661 sizeof(struct kvm_clock_pairing)))
6662 ret = -KVM_EFAULT;
6663
6664 return ret;
6665}
8ef81a9a 6666#endif
55dd00a7 6667
6aef266c
SV		 6668/*
6669 * kvm_pv_kick_cpu_op: Kick a vcpu.
6670 *
6671 * @apicid - apicid of vcpu to be kicked.
6672 */
6673static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6674{
24d2166b 6675 struct kvm_lapic_irq lapic_irq;
6aef266c 6676
24d2166b
R		 6677 lapic_irq.shorthand = 0;
6678 lapic_irq.dest_mode = 0;
ebd28fcb 6679 lapic_irq.level = 0;
24d2166b 6680 lapic_irq.dest_id = apicid;
93bbf0b8 6681 lapic_irq.msi_redir_hint = false;
6aef266c 6682
24d2166b 6683 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6684 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6685}
6686
d62caabb
AS		 6687void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6688{
6689 vcpu->arch.apicv_active = false;
6690 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6691}
6692
8776e519
HB		 6693int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6694{
6695 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6696 int op_64_bit;
8776e519 6697
6356ee0c
MR		 6698 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6699 if (!kvm_hv_hypercall(vcpu))
6700 return 0;
6701 goto out;
6702 }
55cd8e5a 6703
5fdbf976
MT		 6704 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6705 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6706 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6707 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6708 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6709
229456fc 6710 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6711
a449c7aa
NA		 6712 op_64_bit = is_64_bit_mode(vcpu);
6713 if (!op_64_bit) {
8776e519
HB		 6714 nr &= 0xFFFFFFFF;
6715 a0 &= 0xFFFFFFFF;
6716 a1 &= 0xFFFFFFFF;
6717 a2 &= 0xFFFFFFFF;
6718 a3 &= 0xFFFFFFFF;
6719 }
6720
07708c4a
JK		 6721 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6722 ret = -KVM_EPERM;
6356ee0c 6723 goto out_error;
07708c4a
JK		 6724 }
6725
8776e519 6726 switch (nr) {
b93463aa
AK		 6727 case KVM_HC_VAPIC_POLL_IRQ:
6728 ret = 0;
6729 break;
6aef266c
SV		 6730 case KVM_HC_KICK_CPU:
6731 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6732 ret = 0;
6733 break;
8ef81a9a 6734#ifdef CONFIG_X86_64
55dd00a7
MT		 6735 case KVM_HC_CLOCK_PAIRING:
6736 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6737 break;
8ef81a9a 6738#endif
8776e519
HB		 6739 default:
6740 ret = -KVM_ENOSYS;
6741 break;
6742 }
6356ee0c 6743out_error:
a449c7aa
NA		 6744 if (!op_64_bit)
6745 ret = (u32)ret;
5fdbf976 6746 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c
MR		 6747
6748out:
f11c3a8d 6749 ++vcpu->stat.hypercalls;
6356ee0c 6750 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6751}
6752EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6753
b6785def 6754static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6755{
d6aa1000 6756 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6757 char instruction[3];
5fdbf976 6758 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6759
8776e519 6760 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6761
ce2e852e
DV		 6762 return emulator_write_emulated(ctxt, rip, instruction, 3,
6763 &ctxt->exception);
8776e519
HB		 6764}
6765
851ba692 6766static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6767{
782d422b
MG		 6768 return vcpu->run->request_interrupt_window &&
6769 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6770}
6771
851ba692 6772static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6773{
851ba692
AK		 6774 struct kvm_run *kvm_run = vcpu->run;
6775
91586a3b 6776 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6777 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6778 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6779 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6780 kvm_run->ready_for_interrupt_injection =
6781 pic_in_kernel(vcpu->kvm) ||
782d422b 6782 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6783}
6784
95ba8273
GN		 6785static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6786{
6787 int max_irr, tpr;
6788
6789 if (!kvm_x86_ops->update_cr8_intercept)
6790 return;
6791
bce87cce 6792 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6793 return;
6794
d62caabb
AS		 6795 if (vcpu->arch.apicv_active)
6796 return;
6797
8db3baa2
GN		 6798 if (!vcpu->arch.apic->vapic_addr)
6799 max_irr = kvm_lapic_find_highest_irr(vcpu);
6800 else
6801 max_irr = -1;
95ba8273
GN		 6802
6803 if (max_irr != -1)
6804 max_irr >>= 4;
6805
6806 tpr = kvm_lapic_get_cr8(vcpu);
6807
6808 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6809}
6810
b6b8a145 6811static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6812{
b6b8a145
JK		 6813 int r;
6814
95ba8273 6815 /* try to reinject previous events if any */
664f8e26 6816
1a680e35
LA		 6817 if (vcpu->arch.exception.injected)
6818 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6819 /*
a042c26f
LA		 6820 * Do not inject an NMI or interrupt if there is a pending
6821 * exception. Exceptions and interrupts are recognized at
6822 * instruction boundaries, i.e. the start of an instruction.
6823 * Trap-like exceptions, e.g. #DB, have higher priority than
6824 * NMIs and interrupts, i.e. traps are recognized before an
6825 * NMI/interrupt that's pending on the same instruction.
6826 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6827 * priority, but are only generated (pended) during instruction
6828 * execution, i.e. a pending fault-like exception means the
6829 * fault occurred on the *previous* instruction and must be
6830 * serviced prior to recognizing any new events in order to
6831 * fully complete the previous instruction.
664f8e26 6832 */
1a680e35
LA		 6833 else if (!vcpu->arch.exception.pending) {
6834 if (vcpu->arch.nmi_injected)
664f8e26 6835 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6836 else if (vcpu->arch.interrupt.injected)
664f8e26 6837 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6838 }
6839
1a680e35
LA		 6840 /*
6841 * Call check_nested_events() even if we reinjected a previous event
6842 * in order for caller to determine if it should require immediate-exit
6843 * from L2 to L1 due to pending L1 events which require exit
6844 * from L2 to L1.
6845 */
664f8e26
WL		 6846 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6847 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6848 if (r != 0)
6849 return r;
6850 }
6851
6852 /* try to inject new event if pending */
b59bb7bd 6853 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6854 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6855 vcpu->arch.exception.has_error_code,
6856 vcpu->arch.exception.error_code);
d6e8c854 6857
1a680e35 6858 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6859 vcpu->arch.exception.pending = false;
6860 vcpu->arch.exception.injected = true;
6861
d6e8c854
NA		 6862 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6863 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6864 X86_EFLAGS_RF);
6865
6bdf0662
NA		 6866 if (vcpu->arch.exception.nr == DB_VECTOR &&
6867 (vcpu->arch.dr7 & DR7_GD)) {
6868 vcpu->arch.dr7 &= ~DR7_GD;
6869 kvm_update_dr7(vcpu);
6870 }
6871
cfcd20e5 6872 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6873 }
6874
6875 /* Don't consider new event if we re-injected an event */
6876 if (kvm_event_needs_reinjection(vcpu))
6877 return 0;
6878
6879 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6880 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6881 vcpu->arch.smi_pending = false;
52797bf9 6882 ++vcpu->arch.smi_count;
ee2cd4b7 6883 enter_smm(vcpu);
c43203ca 6884 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6885 --vcpu->arch.nmi_pending;
6886 vcpu->arch.nmi_injected = true;
6887 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6888 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6889 /*
6890 * Because interrupts can be injected asynchronously, we are
6891 * calling check_nested_events again here to avoid a race condition.
6892 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6893 * proposal and current concerns. Perhaps we should be setting
6894 * KVM_REQ_EVENT only on certain events and not unconditionally?
6895 */
6896 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6897 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6898 if (r != 0)
6899 return r;
6900 }
95ba8273 6901 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6902 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6903 false);
6904 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6905 }
6906 }
ee2cd4b7 6907
b6b8a145 6908 return 0;
95ba8273
GN		 6909}
6910
7460fb4a
AK		 6911static void process_nmi(struct kvm_vcpu *vcpu)
6912{
6913 unsigned limit = 2;
6914
6915 /*
6916 * x86 is limited to one NMI running, and one NMI pending after it.
6917 * If an NMI is already in progress, limit further NMIs to just one.
6918 * Otherwise, allow two (and we'll inject the first one immediately).
6919 */
6920 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6921 limit = 1;
6922
6923 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6924 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6925 kvm_make_request(KVM_REQ_EVENT, vcpu);
6926}
6927
ee2cd4b7 6928static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6929{
6930 u32 flags = 0;
6931 flags |= seg->g << 23;
6932 flags |= seg->db << 22;
6933 flags |= seg->l << 21;
6934 flags |= seg->avl << 20;
6935 flags |= seg->present << 15;
6936 flags |= seg->dpl << 13;
6937 flags |= seg->s << 12;
6938 flags |= seg->type << 8;
6939 return flags;
6940}
6941
ee2cd4b7 6942static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6943{
6944 struct kvm_segment seg;
6945 int offset;
6946
6947 kvm_get_segment(vcpu, &seg, n);
6948 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6949
6950 if (n < 3)
6951 offset = 0x7f84 + n * 12;
6952 else
6953 offset = 0x7f2c + (n - 3) * 12;
6954
6955 put_smstate(u32, buf, offset + 8, seg.base);
6956 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6957 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6958}
6959
efbb288a 6960#ifdef CONFIG_X86_64
ee2cd4b7 6961static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6962{
6963 struct kvm_segment seg;
6964 int offset;
6965 u16 flags;
6966
6967 kvm_get_segment(vcpu, &seg, n);
6968 offset = 0x7e00 + n * 16;
6969
ee2cd4b7 6970 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6971 put_smstate(u16, buf, offset, seg.selector);
6972 put_smstate(u16, buf, offset + 2, flags);
6973 put_smstate(u32, buf, offset + 4, seg.limit);
6974 put_smstate(u64, buf, offset + 8, seg.base);
6975}
efbb288a 6976#endif
660a5d51 6977
ee2cd4b7 6978static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6979{
6980 struct desc_ptr dt;
6981 struct kvm_segment seg;
6982 unsigned long val;
6983 int i;
6984
6985 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6986 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6987 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6988 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6989
6990 for (i = 0; i < 8; i++)
6991 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6992
6993 kvm_get_dr(vcpu, 6, &val);
6994 put_smstate(u32, buf, 0x7fcc, (u32)val);
6995 kvm_get_dr(vcpu, 7, &val);
6996 put_smstate(u32, buf, 0x7fc8, (u32)val);
6997
6998 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6999 put_smstate(u32, buf, 0x7fc4, seg.selector);
7000 put_smstate(u32, buf, 0x7f64, seg.base);
7001 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7002 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7003
7004 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7005 put_smstate(u32, buf, 0x7fc0, seg.selector);
7006 put_smstate(u32, buf, 0x7f80, seg.base);
7007 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7008 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7009
7010 kvm_x86_ops->get_gdt(vcpu, &dt);
7011 put_smstate(u32, buf, 0x7f74, dt.address);
7012 put_smstate(u32, buf, 0x7f70, dt.size);
7013
7014 kvm_x86_ops->get_idt(vcpu, &dt);
7015 put_smstate(u32, buf, 0x7f58, dt.address);
7016 put_smstate(u32, buf, 0x7f54, dt.size);
7017
7018 for (i = 0; i < 6; i++)
ee2cd4b7 7019 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7020
7021 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7022
7023 /* revision id */
7024 put_smstate(u32, buf, 0x7efc, 0x00020000);
7025 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7026}
7027
ee2cd4b7 7028static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7029{
7030#ifdef CONFIG_X86_64
7031 struct desc_ptr dt;
7032 struct kvm_segment seg;
7033 unsigned long val;
7034 int i;
7035
7036 for (i = 0; i < 16; i++)
7037 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7038
7039 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7040 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7041
7042 kvm_get_dr(vcpu, 6, &val);
7043 put_smstate(u64, buf, 0x7f68, val);
7044 kvm_get_dr(vcpu, 7, &val);
7045 put_smstate(u64, buf, 0x7f60, val);
7046
7047 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7048 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7049 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7050
7051 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7052
7053 /* revision id */
7054 put_smstate(u32, buf, 0x7efc, 0x00020064);
7055
7056 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7057
7058 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7059 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7060 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7061 put_smstate(u32, buf, 0x7e94, seg.limit);
7062 put_smstate(u64, buf, 0x7e98, seg.base);
7063
7064 kvm_x86_ops->get_idt(vcpu, &dt);
7065 put_smstate(u32, buf, 0x7e84, dt.size);
7066 put_smstate(u64, buf, 0x7e88, dt.address);
7067
7068 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7069 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7070 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7071 put_smstate(u32, buf, 0x7e74, seg.limit);
7072 put_smstate(u64, buf, 0x7e78, seg.base);
7073
7074 kvm_x86_ops->get_gdt(vcpu, &dt);
7075 put_smstate(u32, buf, 0x7e64, dt.size);
7076 put_smstate(u64, buf, 0x7e68, dt.address);
7077
7078 for (i = 0; i < 6; i++)
ee2cd4b7 7079 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7080#else
7081 WARN_ON_ONCE(1);
7082#endif
7083}
7084
ee2cd4b7 7085static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7086{
660a5d51 7087 struct kvm_segment cs, ds;
18c3626e 7088 struct desc_ptr dt;
660a5d51
PB		 7089 char buf[512];
7090 u32 cr0;
7091
660a5d51 7092 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7093 memset(buf, 0, 512);
d6321d49 7094 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7095 enter_smm_save_state_64(vcpu, buf);
660a5d51 7096 else
ee2cd4b7 7097 enter_smm_save_state_32(vcpu, buf);
660a5d51 7098
0234bf88
LP		 7099 /*
7100 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7101 * vCPU state (e.g. leave guest mode) after we've saved the state into
7102 * the SMM state-save area.
7103 */
7104 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7105
7106 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7107 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7108
7109 if (kvm_x86_ops->get_nmi_mask(vcpu))
7110 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7111 else
7112 kvm_x86_ops->set_nmi_mask(vcpu, true);
7113
7114 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7115 kvm_rip_write(vcpu, 0x8000);
7116
7117 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7118 kvm_x86_ops->set_cr0(vcpu, cr0);
7119 vcpu->arch.cr0 = cr0;
7120
7121 kvm_x86_ops->set_cr4(vcpu, 0);
7122
18c3626e
PB		 7123 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7124 dt.address = dt.size = 0;
7125 kvm_x86_ops->set_idt(vcpu, &dt);
7126
660a5d51
PB		 7127 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7128
7129 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7130 cs.base = vcpu->arch.smbase;
7131
7132 ds.selector = 0;
7133 ds.base = 0;
7134
7135 cs.limit = ds.limit = 0xffffffff;
7136 cs.type = ds.type = 0x3;
7137 cs.dpl = ds.dpl = 0;
7138 cs.db = ds.db = 0;
7139 cs.s = ds.s = 1;
7140 cs.l = ds.l = 0;
7141 cs.g = ds.g = 1;
7142 cs.avl = ds.avl = 0;
7143 cs.present = ds.present = 1;
7144 cs.unusable = ds.unusable = 0;
7145 cs.padding = ds.padding = 0;
7146
7147 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7148 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7149 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7150 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7151 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7152 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7153
d6321d49 7154 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7155 kvm_x86_ops->set_efer(vcpu, 0);
7156
7157 kvm_update_cpuid(vcpu);
7158 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7159}
7160
ee2cd4b7 7161static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7162{
7163 vcpu->arch.smi_pending = true;
7164 kvm_make_request(KVM_REQ_EVENT, vcpu);
7165}
7166
2860c4b1
PB		 7167void kvm_make_scan_ioapic_request(struct kvm *kvm)
7168{
7169 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7170}
7171
3d81bc7e 7172static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7173{
3d81bc7e
YZ		 7174 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7175 return;
c7c9c56c 7176
6308630b 7177 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7178
b053b2ae 7179 if (irqchip_split(vcpu->kvm))
6308630b 7180 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7181 else {
fa59cc00 7182 if (vcpu->arch.apicv_active)
d62caabb 7183 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7184 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7185 }
e40ff1d6
LA		 7186
7187 if (is_guest_mode(vcpu))
7188 vcpu->arch.load_eoi_exitmap_pending = true;
7189 else
7190 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7191}
7192
7193static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7194{
7195 u64 eoi_exit_bitmap[4];
7196
7197 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7198 return;
7199
5c919412
AS		 7200 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7201 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7202 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7203}
7204
b1394e74
RK		 7205void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7206 unsigned long start, unsigned long end)
7207{
7208 unsigned long apic_address;
7209
7210 /*
7211 * The physical address of apic access page is stored in the VMCS.
7212 * Update it when it becomes invalid.
7213 */
7214 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7215 if (start <= apic_address && apic_address < end)
7216 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7217}
7218
4256f43f
TC		 7219void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7220{
c24ae0dc
TC		 7221 struct page *page = NULL;
7222
35754c98 7223 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7224 return;
7225
4256f43f
TC		 7226 if (!kvm_x86_ops->set_apic_access_page_addr)
7227 return;
7228
c24ae0dc 7229 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7230 if (is_error_page(page))
7231 return;
c24ae0dc
TC		 7232 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7233
7234 /*
7235 * Do not pin apic access page in memory, the MMU notifier
7236 * will call us again if it is migrated or swapped out.
7237 */
7238 put_page(page);
4256f43f
TC		 7239}
7240EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7241
9357d939 7242/*
362c698f 7243 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7244 * exiting to the userspace. Otherwise, the value will be returned to the
7245 * userspace.
7246 */
851ba692 7247static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7248{
7249 int r;
62a193ed
MG		 7250 bool req_int_win =
7251 dm_request_for_irq_injection(vcpu) &&
7252 kvm_cpu_accept_dm_intr(vcpu);
7253
730dca42 7254 bool req_immediate_exit = false;
b6c7a5dc 7255
2fa6e1e1 7256 if (kvm_request_pending(vcpu)) {
a8eeb04a 7257 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7258 kvm_mmu_unload(vcpu);
a8eeb04a 7259 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7260 __kvm_migrate_timers(vcpu);
d828199e
MT		 7261 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7262 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7263 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7264 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7265 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7266 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7267 if (unlikely(r))
7268 goto out;
7269 }
a8eeb04a 7270 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7271 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7272 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7273 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7274 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7275 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7276 r = 0;
7277 goto out;
7278 }
a8eeb04a 7279 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7280 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7281 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7282 r = 0;
7283 goto out;
7284 }
af585b92
GN		 7285 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7286 /* Page is swapped out. Do synthetic halt */
7287 vcpu->arch.apf.halted = true;
7288 r = 1;
7289 goto out;
7290 }
c9aaa895
GC		 7291 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7292 record_steal_time(vcpu);
64d60670
PB		 7293 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7294 process_smi(vcpu);
7460fb4a
AK		 7295 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7296 process_nmi(vcpu);
f5132b01 7297 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7298 kvm_pmu_handle_event(vcpu);
f5132b01 7299 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7300 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7301 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7302 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7303 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7304 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7305 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7306 vcpu->run->eoi.vector =
7307 vcpu->arch.pending_ioapic_eoi;
7308 r = 0;
7309 goto out;
7310 }
7311 }
3d81bc7e
YZ		 7312 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7313 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7314 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7315 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7316 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7317 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7318 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7319 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7320 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7321 r = 0;
7322 goto out;
7323 }
e516cebb
AS		 7324 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7325 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7326 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7327 r = 0;
7328 goto out;
7329 }
db397571
AS		 7330 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7331 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7332 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7333 r = 0;
7334 goto out;
7335 }
f3b138c5
AS		 7336
7337 /*
7338 * KVM_REQ_HV_STIMER has to be processed after
7339 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7340 * depend on the guest clock being up-to-date
7341 */
1f4b34f8
AS		 7342 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7343 kvm_hv_process_stimers(vcpu);
2f52d58c 7344 }
b93463aa 7345
b463a6f7 7346 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7347 ++vcpu->stat.req_event;
66450a21
JK		 7348 kvm_apic_accept_events(vcpu);
7349 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7350 r = 1;
7351 goto out;
7352 }
7353
b6b8a145
JK		 7354 if (inject_pending_event(vcpu, req_int_win) != 0)
7355 req_immediate_exit = true;
321c5658 7356 else {
cc3d967f 7357 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7358 *
cc3d967f
LP		 7359 * SMIs have three cases:
7360 * 1) They can be nested, and then there is nothing to
7361 * do here because RSM will cause a vmexit anyway.
7362 * 2) There is an ISA-specific reason why SMI cannot be
7363 * injected, and the moment when this changes can be
7364 * intercepted.
7365 * 3) Or the SMI can be pending because
7366 * inject_pending_event has completed the injection
7367 * of an IRQ or NMI from the previous vmexit, and
7368 * then we request an immediate exit to inject the
7369 * SMI.
c43203ca
PB		 7370 */
7371 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7372 if (!kvm_x86_ops->enable_smi_window(vcpu))
7373 req_immediate_exit = true;
321c5658
YS		 7374 if (vcpu->arch.nmi_pending)
7375 kvm_x86_ops->enable_nmi_window(vcpu);
7376 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7377 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7378 WARN_ON(vcpu->arch.exception.pending);
321c5658 7379 }
b463a6f7
AK		 7380
7381 if (kvm_lapic_enabled(vcpu)) {
7382 update_cr8_intercept(vcpu);
7383 kvm_lapic_sync_to_vapic(vcpu);
7384 }
7385 }
7386
d8368af8
AK		 7387 r = kvm_mmu_reload(vcpu);
7388 if (unlikely(r)) {
d905c069 7389 goto cancel_injection;
d8368af8
AK		 7390 }
7391
b6c7a5dc
HB		 7392 preempt_disable();
7393
7394 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7395
7396 /*
7397 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7398 * IPI are then delayed after guest entry, which ensures that they
7399 * result in virtual interrupt delivery.
7400 */
7401 local_irq_disable();
6b7e2d09
XG		 7402 vcpu->mode = IN_GUEST_MODE;
7403
01b71917
MT		 7404 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7405
0f127d12 7406 /*
b95234c8 7407 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7408 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7409 *
7410 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7411 * pairs with the memory barrier implicit in pi_test_and_set_on
7412 * (see vmx_deliver_posted_interrupt).
7413 *
7414 * 3) This also orders the write to mode from any reads to the page
7415 * tables done while the VCPU is running. Please see the comment
7416 * in kvm_flush_remote_tlbs.
6b7e2d09 7417 */
01b71917 7418 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7419
b95234c8
PB		 7420 /*
7421 * This handles the case where a posted interrupt was
7422 * notified with kvm_vcpu_kick.
7423 */
fa59cc00
LA		 7424 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7425 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7426
2fa6e1e1 7427 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7428 || need_resched() || signal_pending(current)) {
6b7e2d09 7429 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7430 smp_wmb();
6c142801
AK		 7431 local_irq_enable();
7432 preempt_enable();
01b71917 7433 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7434 r = 1;
d905c069 7435 goto cancel_injection;
6c142801
AK		 7436 }
7437
fc5b7f3b
DM		 7438 kvm_load_guest_xcr0(vcpu);
7439
c43203ca
PB		 7440 if (req_immediate_exit) {
7441 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7442 smp_send_reschedule(vcpu->cpu);
c43203ca 7443 }
d6185f20 7444
8b89fe1f 7445 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7446 if (lapic_timer_advance_ns)
7447 wait_lapic_expire(vcpu);
6edaa530 7448 guest_enter_irqoff();
b6c7a5dc 7449
42dbaa5a 7450 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7451 set_debugreg(0, 7);
7452 set_debugreg(vcpu->arch.eff_db[0], 0);
7453 set_debugreg(vcpu->arch.eff_db[1], 1);
7454 set_debugreg(vcpu->arch.eff_db[2], 2);
7455 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7456 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7457 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7458 }
b6c7a5dc 7459
851ba692 7460 kvm_x86_ops->run(vcpu);
b6c7a5dc 7461
c77fb5fe
PB		 7462 /*
7463 * Do this here before restoring debug registers on the host. And
7464 * since we do this before handling the vmexit, a DR access vmexit
7465 * can (a) read the correct value of the debug registers, (b) set
7466 * KVM_DEBUGREG_WONT_EXIT again.
7467 */
7468 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7469 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7470 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7471 kvm_update_dr0123(vcpu);
7472 kvm_update_dr6(vcpu);
7473 kvm_update_dr7(vcpu);
7474 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7475 }
7476
24f1e32c
FW		 7477 /*
7478 * If the guest has used debug registers, at least dr7
7479 * will be disabled while returning to the host.
7480 * If we don't have active breakpoints in the host, we don't
7481 * care about the messed up debug address registers. But if
7482 * we have some of them active, restore the old state.
7483 */
59d8eb53 7484 if (hw_breakpoint_active())
24f1e32c 7485 hw_breakpoint_restore();
42dbaa5a 7486
4ba76538 7487 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7488
6b7e2d09 7489 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7490 smp_wmb();
a547c6db 7491
fc5b7f3b
DM		 7492 kvm_put_guest_xcr0(vcpu);
7493
dd60d217 7494 kvm_before_interrupt(vcpu);
a547c6db 7495 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7496 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7497
7498 ++vcpu->stat.exits;
7499
f2485b3e 7500 guest_exit_irqoff();
b6c7a5dc 7501
f2485b3e 7502 local_irq_enable();
b6c7a5dc
HB		 7503 preempt_enable();
7504
f656ce01 7505 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7506
b6c7a5dc
HB		 7507 /*
7508 * Profile KVM exit RIPs:
7509 */
7510 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7511 unsigned long rip = kvm_rip_read(vcpu);
7512 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7513 }
7514
cc578287
ZA		 7515 if (unlikely(vcpu->arch.tsc_always_catchup))
7516 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7517
5cfb1d5a
MT		 7518 if (vcpu->arch.apic_attention)
7519 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7520
618232e2 7521 vcpu->arch.gpa_available = false;
851ba692 7522 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7523 return r;
7524
7525cancel_injection:
7526 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7527 if (unlikely(vcpu->arch.apic_attention))
7528 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7529out:
7530 return r;
7531}
b6c7a5dc 7532
362c698f
PB		 7533static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7534{
bf9f6ac8
FW		 7535 if (!kvm_arch_vcpu_runnable(vcpu) &&
7536 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7537 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7538 kvm_vcpu_block(vcpu);
7539 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7540
7541 if (kvm_x86_ops->post_block)
7542 kvm_x86_ops->post_block(vcpu);
7543
9c8fd1ba
PB		 7544 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7545 return 1;
7546 }
362c698f
PB		 7547
7548 kvm_apic_accept_events(vcpu);
7549 switch(vcpu->arch.mp_state) {
7550 case KVM_MP_STATE_HALTED:
7551 vcpu->arch.pv.pv_unhalted = false;
7552 vcpu->arch.mp_state =
7553 KVM_MP_STATE_RUNNABLE;
7554 case KVM_MP_STATE_RUNNABLE:
7555 vcpu->arch.apf.halted = false;
7556 break;
7557 case KVM_MP_STATE_INIT_RECEIVED:
7558 break;
7559 default:
7560 return -EINTR;
7561 break;
7562 }
7563 return 1;
7564}
09cec754 7565
5d9bc648
PB		 7566static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7567{
0ad3bed6
PB		 7568 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7569 kvm_x86_ops->check_nested_events(vcpu, false);
7570
5d9bc648
PB		 7571 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7572 !vcpu->arch.apf.halted);
7573}
7574
362c698f 7575static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7576{
7577 int r;
f656ce01 7578 struct kvm *kvm = vcpu->kvm;
d7690175 7579
f656ce01 7580 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7581
362c698f 7582 for (;;) {
58f800d5 7583 if (kvm_vcpu_running(vcpu)) {
851ba692 7584 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7585 } else {
362c698f 7586 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7587 }
7588
09cec754
GN		 7589 if (r <= 0)
7590 break;
7591
72875d8a 7592 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7593 if (kvm_cpu_has_pending_timer(vcpu))
7594 kvm_inject_pending_timer_irqs(vcpu);
7595
782d422b
MG		 7596 if (dm_request_for_irq_injection(vcpu) &&
7597 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7598 r = 0;
7599 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7600 ++vcpu->stat.request_irq_exits;
362c698f 7601 break;
09cec754 7602 }
af585b92
GN		 7603
7604 kvm_check_async_pf_completion(vcpu);
7605
09cec754
GN		 7606 if (signal_pending(current)) {
7607 r = -EINTR;
851ba692 7608 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7609 ++vcpu->stat.signal_exits;
362c698f 7610 break;
09cec754
GN		 7611 }
7612 if (need_resched()) {
f656ce01 7613 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7614 cond_resched();
f656ce01 7615 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7616 }
b6c7a5dc
HB		 7617 }
7618
f656ce01 7619 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7620
7621 return r;
7622}
7623
716d51ab
GN		 7624static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7625{
7626 int r;
7627 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7628 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7629 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7630 if (r != EMULATE_DONE)
7631 return 0;
7632 return 1;
7633}
7634
7635static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7636{
7637 BUG_ON(!vcpu->arch.pio.count);
7638
7639 return complete_emulated_io(vcpu);
7640}
7641
f78146b0
AK		 7642/*
7643 * Implements the following, as a state machine:
7644 *
7645 * read:
7646 * for each fragment
87da7e66
XG		 7647 * for each mmio piece in the fragment
7648 * write gpa, len
7649 * exit
7650 * copy data
f78146b0
AK		 7651 * execute insn
7652 *
7653 * write:
7654 * for each fragment
87da7e66
XG		 7655 * for each mmio piece in the fragment
7656 * write gpa, len
7657 * copy data
7658 * exit
f78146b0 7659 */
716d51ab 7660static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7661{
7662 struct kvm_run *run = vcpu->run;
f78146b0 7663 struct kvm_mmio_fragment *frag;
87da7e66 7664 unsigned len;
5287f194 7665
716d51ab 7666 BUG_ON(!vcpu->mmio_needed);
5287f194 7667
716d51ab 7668 /* Complete previous fragment */
87da7e66
XG		 7669 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7670 len = min(8u, frag->len);
716d51ab 7671 if (!vcpu->mmio_is_write)
87da7e66
XG		 7672 memcpy(frag->data, run->mmio.data, len);
7673
7674 if (frag->len <= 8) {
7675 /* Switch to the next fragment. */
7676 frag++;
7677 vcpu->mmio_cur_fragment++;
7678 } else {
7679 /* Go forward to the next mmio piece. */
7680 frag->data += len;
7681 frag->gpa += len;
7682 frag->len -= len;
7683 }
7684
a08d3b3b 7685 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7686 vcpu->mmio_needed = 0;
0912c977
PB		 7687
7688 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7689 if (vcpu->mmio_is_write)
716d51ab
GN		 7690 return 1;
7691 vcpu->mmio_read_completed = 1;
7692 return complete_emulated_io(vcpu);
7693 }
87da7e66 7694
716d51ab
GN		 7695 run->exit_reason = KVM_EXIT_MMIO;
7696 run->mmio.phys_addr = frag->gpa;
7697 if (vcpu->mmio_is_write)
87da7e66
XG		 7698 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7699 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7700 run->mmio.is_write = vcpu->mmio_is_write;
7701 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7702 return 0;
5287f194
AK		 7703}
7704
b6c7a5dc
HB		 7705int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7706{
7707 int r;
b6c7a5dc 7708
accb757d 7709 vcpu_load(vcpu);
20b7035c 7710 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7711 kvm_load_guest_fpu(vcpu);
7712
a4535290 7713 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7714 if (kvm_run->immediate_exit) {
7715 r = -EINTR;
7716 goto out;
7717 }
b6c7a5dc 7718 kvm_vcpu_block(vcpu);
66450a21 7719 kvm_apic_accept_events(vcpu);
72875d8a 7720 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7721 r = -EAGAIN;
a0595000
JS		 7722 if (signal_pending(current)) {
7723 r = -EINTR;
7724 vcpu->run->exit_reason = KVM_EXIT_INTR;
7725 ++vcpu->stat.signal_exits;
7726 }
ac9f6dc0 7727 goto out;
b6c7a5dc
HB		 7728 }
7729
01643c51
KH		 7730 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7731 r = -EINVAL;
7732 goto out;
7733 }
7734
7735 if (vcpu->run->kvm_dirty_regs) {
7736 r = sync_regs(vcpu);
7737 if (r != 0)
7738 goto out;
7739 }
7740
b6c7a5dc 7741 /* re-sync apic's tpr */
35754c98 7742 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7743 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7744 r = -EINVAL;
7745 goto out;
7746 }
7747 }
b6c7a5dc 7748
716d51ab
GN		 7749 if (unlikely(vcpu->arch.complete_userspace_io)) {
7750 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7751 vcpu->arch.complete_userspace_io = NULL;
7752 r = cui(vcpu);
7753 if (r <= 0)
5663d8f9 7754 goto out;
716d51ab
GN		 7755 } else
7756 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7757
460df4c1
PB		 7758 if (kvm_run->immediate_exit)
7759 r = -EINTR;
7760 else
7761 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7762
7763out:
5663d8f9 7764 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7765 if (vcpu->run->kvm_valid_regs)
7766 store_regs(vcpu);
f1d86e46 7767 post_kvm_run_save(vcpu);
20b7035c 7768 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7769
accb757d 7770 vcpu_put(vcpu);
b6c7a5dc
HB		 7771 return r;
7772}
7773
01643c51 7774static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7775{
7ae441ea
GN		 7776 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7777 /*
7778 * We are here if userspace calls get_regs() in the middle of
7779 * instruction emulation. Registers state needs to be copied
4a969980 7780 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7781 * that usually, but some bad designed PV devices (vmware
7782 * backdoor interface) need this to work
7783 */
dd856efa 7784 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7785 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7786 }
5fdbf976
MT		 7787 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7788 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7789 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7790 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7791 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7792 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7793 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7794 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7795#ifdef CONFIG_X86_64
5fdbf976
MT		 7796 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7797 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7798 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7799 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7800 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7801 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7802 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7803 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7804#endif
7805
5fdbf976 7806 regs->rip = kvm_rip_read(vcpu);
91586a3b 7807 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7808}
b6c7a5dc 7809
01643c51
KH		 7810int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7811{
7812 vcpu_load(vcpu);
7813 __get_regs(vcpu, regs);
1fc9b76b 7814 vcpu_put(vcpu);
b6c7a5dc
HB		 7815 return 0;
7816}
7817
01643c51 7818static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7819{
7ae441ea
GN		 7820 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7821 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7822
5fdbf976
MT		 7823 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7824 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7825 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7826 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7827 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7828 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7829 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7830 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7831#ifdef CONFIG_X86_64
5fdbf976
MT		 7832 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7833 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7834 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7835 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7836 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7837 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7838 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7839 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7840#endif
7841
5fdbf976 7842 kvm_rip_write(vcpu, regs->rip);
d73235d1 7843 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7844
b4f14abd
JK		 7845 vcpu->arch.exception.pending = false;
7846
3842d135 7847 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7848}
3842d135 7849
01643c51
KH		 7850int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7851{
7852 vcpu_load(vcpu);
7853 __set_regs(vcpu, regs);
875656fe 7854 vcpu_put(vcpu);
b6c7a5dc
HB		 7855 return 0;
7856}
7857
b6c7a5dc
HB		 7858void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7859{
7860 struct kvm_segment cs;
7861
3e6e0aab 7862 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7863 *db = cs.db;
7864 *l = cs.l;
7865}
7866EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7867
01643c51 7868static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7869{
89a27f4d 7870 struct desc_ptr dt;
b6c7a5dc 7871
3e6e0aab
GT		 7872 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7873 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7874 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7875 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7876 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7877 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7878
3e6e0aab
GT		 7879 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7880 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7881
7882 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7883 sregs->idt.limit = dt.size;
7884 sregs->idt.base = dt.address;
b6c7a5dc 7885 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7886 sregs->gdt.limit = dt.size;
7887 sregs->gdt.base = dt.address;
b6c7a5dc 7888
4d4ec087 7889 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7890 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7891 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7892 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7893 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7894 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7895 sregs->apic_base = kvm_get_apic_base(vcpu);
7896
923c61bb 7897 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7898
04140b41 7899 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7900 set_bit(vcpu->arch.interrupt.nr,
7901 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7902}
16d7a191 7903
01643c51
KH		 7904int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7905 struct kvm_sregs *sregs)
7906{
7907 vcpu_load(vcpu);
7908 __get_sregs(vcpu, sregs);
bcdec41c 7909 vcpu_put(vcpu);
b6c7a5dc
HB		 7910 return 0;
7911}
7912
62d9f0db
MT		 7913int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7914 struct kvm_mp_state *mp_state)
7915{
fd232561
CD		 7916 vcpu_load(vcpu);
7917
66450a21 7918 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7919 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7920 vcpu->arch.pv.pv_unhalted)
7921 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7922 else
7923 mp_state->mp_state = vcpu->arch.mp_state;
7924
fd232561 7925 vcpu_put(vcpu);
62d9f0db
MT		 7926 return 0;
7927}
7928
7929int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7930 struct kvm_mp_state *mp_state)
7931{
e83dff5e
CD		 7932 int ret = -EINVAL;
7933
7934 vcpu_load(vcpu);
7935
bce87cce 7936 if (!lapic_in_kernel(vcpu) &&
66450a21 7937 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7938 goto out;
66450a21 7939
28bf2888
DH		 7940 /* INITs are latched while in SMM */
7941 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7942 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7943 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7944 goto out;
28bf2888 7945
66450a21
JK		 7946 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7947 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7948 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7949 } else
7950 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7951 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7952
7953 ret = 0;
7954out:
7955 vcpu_put(vcpu);
7956 return ret;
62d9f0db
MT		 7957}
7958
7f3d35fd
KW		 7959int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7960 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7961{
9d74191a 7962 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7963 int ret;
e01c2426 7964
8ec4722d 7965 init_emulate_ctxt(vcpu);
c697518a 7966
7f3d35fd 7967 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7968 has_error_code, error_code);
c697518a 7969
c697518a 7970 if (ret)
19d04437 7971 return EMULATE_FAIL;
37817f29 7972
9d74191a
TY		 7973 kvm_rip_write(vcpu, ctxt->eip);
7974 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7975 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7976 return EMULATE_DONE;
37817f29
IE		 7977}
7978EXPORT_SYMBOL_GPL(kvm_task_switch);
7979
3140c156 7980static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 7981{
37b95951 7982 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7983 /*
7984 * When EFER.LME and CR0.PG are set, the processor is in
7985 * 64-bit mode (though maybe in a 32-bit code segment).
7986 * CR4.PAE and EFER.LMA must be set.
7987 */
37b95951 7988 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7989 || !(sregs->efer & EFER_LMA))
7990 return -EINVAL;
7991 } else {
7992 /*
7993 * Not in 64-bit mode: EFER.LMA is clear and the code
7994 * segment cannot be 64-bit.
7995 */
7996 if (sregs->efer & EFER_LMA || sregs->cs.l)
7997 return -EINVAL;
7998 }
7999
8000 return 0;
8001}
8002
01643c51 8003static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8004{
58cb628d 8005 struct msr_data apic_base_msr;
b6c7a5dc 8006 int mmu_reset_needed = 0;
63f42e02 8007 int pending_vec, max_bits, idx;
89a27f4d 8008 struct desc_ptr dt;
b4ef9d4e
CD		 8009 int ret = -EINVAL;
8010
d6321d49
RK		 8011 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8012 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 8013 goto out;
6d1068b3 8014
f2981033 8015 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8016 goto out;
f2981033 8017
d3802286
JM		 8018 apic_base_msr.data = sregs->apic_base;
8019 apic_base_msr.host_initiated = true;
8020 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8021 goto out;
6d1068b3 8022
89a27f4d
GN		 8023 dt.size = sregs->idt.limit;
8024 dt.address = sregs->idt.base;
b6c7a5dc 8025 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8026 dt.size = sregs->gdt.limit;
8027 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8028 kvm_x86_ops->set_gdt(vcpu, &dt);
8029
ad312c7c 8030 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8031 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8032 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8033 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8034
2d3ad1f4 8035 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8036
f6801dff 8037 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8038 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8039
4d4ec087 8040 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8041 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8042 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8043
fc78f519 8044 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 8045 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 8046 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 8047 kvm_update_cpuid(vcpu);
63f42e02
XG		 8048
8049 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8050 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8051 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8052 mmu_reset_needed = 1;
8053 }
63f42e02 8054 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8055
8056 if (mmu_reset_needed)
8057 kvm_mmu_reset_context(vcpu);
8058
a50abc3b 8059 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8060 pending_vec = find_first_bit(
8061 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8062 if (pending_vec < max_bits) {
66fd3f7f 8063 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8064 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8065 }
8066
3e6e0aab
GT		 8067 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8068 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8069 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8070 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8071 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8072 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8073
3e6e0aab
GT		 8074 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8075 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8076
5f0269f5
ME		 8077 update_cr8_intercept(vcpu);
8078
9c3e4aab 8079 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8080 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8081 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8082 !is_protmode(vcpu))
9c3e4aab
MT		 8083 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8084
3842d135
AK		 8085 kvm_make_request(KVM_REQ_EVENT, vcpu);
8086
b4ef9d4e
CD		 8087 ret = 0;
8088out:
01643c51
KH		 8089 return ret;
8090}
8091
8092int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8093 struct kvm_sregs *sregs)
8094{
8095 int ret;
8096
8097 vcpu_load(vcpu);
8098 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8099 vcpu_put(vcpu);
8100 return ret;
b6c7a5dc
HB		 8101}
8102
d0bfb940
JK		 8103int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8104 struct kvm_guest_debug *dbg)
b6c7a5dc 8105{
355be0b9 8106 unsigned long rflags;
ae675ef0 8107 int i, r;
b6c7a5dc 8108
66b56562
CD		 8109 vcpu_load(vcpu);
8110
4f926bf2
JK		 8111 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8112 r = -EBUSY;
8113 if (vcpu->arch.exception.pending)
2122ff5e 8114 goto out;
4f926bf2
JK		 8115 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8116 kvm_queue_exception(vcpu, DB_VECTOR);
8117 else
8118 kvm_queue_exception(vcpu, BP_VECTOR);
8119 }
8120
91586a3b
JK		 8121 /*
8122 * Read rflags as long as potentially injected trace flags are still
8123 * filtered out.
8124 */
8125 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8126
8127 vcpu->guest_debug = dbg->control;
8128 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8129 vcpu->guest_debug = 0;
8130
8131 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8132 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8133 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8134 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8135 } else {
8136 for (i = 0; i < KVM_NR_DB_REGS; i++)
8137 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8138 }
c8639010 8139 kvm_update_dr7(vcpu);
ae675ef0 8140
f92653ee
JK		 8141 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8142 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8143 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8144
91586a3b
JK		 8145 /*
8146 * Trigger an rflags update that will inject or remove the trace
8147 * flags.
8148 */
8149 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8150
a96036b8 8151 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8152
4f926bf2 8153 r = 0;
d0bfb940 8154
2122ff5e 8155out:
66b56562 8156 vcpu_put(vcpu);
b6c7a5dc
HB		 8157 return r;
8158}
8159
8b006791
ZX		 8160/*
8161 * Translate a guest virtual address to a guest physical address.
8162 */
8163int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8164 struct kvm_translation *tr)
8165{
8166 unsigned long vaddr = tr->linear_address;
8167 gpa_t gpa;
f656ce01 8168 int idx;
8b006791 8169
1da5b61d
CD		 8170 vcpu_load(vcpu);
8171
f656ce01 8172 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8173 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8174 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8175 tr->physical_address = gpa;
8176 tr->valid = gpa != UNMAPPED_GVA;
8177 tr->writeable = 1;
8178 tr->usermode = 0;
8b006791 8179
1da5b61d 8180 vcpu_put(vcpu);
8b006791
ZX		 8181 return 0;
8182}
8183
d0752060
HB		 8184int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8185{
1393123e 8186 struct fxregs_state *fxsave;
d0752060 8187
1393123e 8188 vcpu_load(vcpu);
d0752060 8189
1393123e 8190 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8191 memcpy(fpu->fpr, fxsave->st_space, 128);
8192 fpu->fcw = fxsave->cwd;
8193 fpu->fsw = fxsave->swd;
8194 fpu->ftwx = fxsave->twd;
8195 fpu->last_opcode = fxsave->fop;
8196 fpu->last_ip = fxsave->rip;
8197 fpu->last_dp = fxsave->rdp;
8198 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8199
1393123e 8200 vcpu_put(vcpu);
d0752060
HB		 8201 return 0;
8202}
8203
8204int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8205{
6a96bc7f
CD		 8206 struct fxregs_state *fxsave;
8207
8208 vcpu_load(vcpu);
8209
8210 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8211
d0752060
HB		 8212 memcpy(fxsave->st_space, fpu->fpr, 128);
8213 fxsave->cwd = fpu->fcw;
8214 fxsave->swd = fpu->fsw;
8215 fxsave->twd = fpu->ftwx;
8216 fxsave->fop = fpu->last_opcode;
8217 fxsave->rip = fpu->last_ip;
8218 fxsave->rdp = fpu->last_dp;
8219 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8220
6a96bc7f 8221 vcpu_put(vcpu);
d0752060
HB		 8222 return 0;
8223}
8224
01643c51
KH		 8225static void store_regs(struct kvm_vcpu *vcpu)
8226{
8227 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8228
8229 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8230 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8231
8232 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8233 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8234
8235 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8236 kvm_vcpu_ioctl_x86_get_vcpu_events(
8237 vcpu, &vcpu->run->s.regs.events);
8238}
8239
8240static int sync_regs(struct kvm_vcpu *vcpu)
8241{
8242 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8243 return -EINVAL;
8244
8245 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8246 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8247 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8248 }
8249 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8250 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8251 return -EINVAL;
8252 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8253 }
8254 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8255 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8256 vcpu, &vcpu->run->s.regs.events))
8257 return -EINVAL;
8258 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8259 }
8260
8261 return 0;
8262}
8263
0ee6a517 8264static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8265{
bf935b0b 8266 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8267 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8268 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8269 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8270
2acf923e
DC		 8271 /*
8272 * Ensure guest xcr0 is valid for loading
8273 */
d91cab78 8274 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8275
ad312c7c 8276 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8277}
d0752060 8278
f775b13e 8279/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8280void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8281{
f775b13e
RR		 8282 preempt_disable();
8283 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8284 /* PKRU is separately restored in kvm_x86_ops->run. */
8285 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8286 ~XFEATURE_MASK_PKRU);
f775b13e 8287 preempt_enable();
0c04851c 8288 trace_kvm_fpu(1);
d0752060 8289}
d0752060 8290
f775b13e 8291/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8292void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8293{
f775b13e 8294 preempt_disable();
4f836347 8295 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8296 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8297 preempt_enable();
f096ed85 8298 ++vcpu->stat.fpu_reload;
0c04851c 8299 trace_kvm_fpu(0);
d0752060 8300}
e9b11c17
ZX		 8301
8302void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8303{
bd768e14
IY		 8304 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8305
12f9a48f 8306 kvmclock_reset(vcpu);
7f1ea208 8307
e9b11c17 8308 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8309 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8310}
8311
8312struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8313 unsigned int id)
8314{
c447e76b
LL		 8315 struct kvm_vcpu *vcpu;
8316
b0c39dc6 8317 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8318 printk_once(KERN_WARNING
8319 "kvm: SMP vm created on host with unstable TSC; "
8320 "guest TSC will not be reliable\n");
c447e76b
LL		 8321
8322 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8323
c447e76b 8324 return vcpu;
26e5215f 8325}
e9b11c17 8326
26e5215f
AK		 8327int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8328{
19efffa2 8329 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8330 vcpu_load(vcpu);
d28bc9dd 8331 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8332 kvm_mmu_setup(vcpu);
e9b11c17 8333 vcpu_put(vcpu);
ec7660cc 8334 return 0;
e9b11c17
ZX		 8335}
8336
31928aa5 8337void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8338{
8fe8ab46 8339 struct msr_data msr;
332967a3 8340 struct kvm *kvm = vcpu->kvm;
42897d86 8341
d3457c87
RK		 8342 kvm_hv_vcpu_postcreate(vcpu);
8343
ec7660cc 8344 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8345 return;
ec7660cc 8346 vcpu_load(vcpu);
8fe8ab46
WA		 8347 msr.data = 0x0;
8348 msr.index = MSR_IA32_TSC;
8349 msr.host_initiated = true;
8350 kvm_write_tsc(vcpu, &msr);
42897d86 8351 vcpu_put(vcpu);
ec7660cc 8352 mutex_unlock(&vcpu->mutex);
42897d86 8353
630994b3
MT		 8354 if (!kvmclock_periodic_sync)
8355 return;
8356
332967a3
AJ		 8357 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8358 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8359}
8360
d40ccc62 8361void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8362{
344d9588
GN		 8363 vcpu->arch.apf.msr_val = 0;
8364
ec7660cc 8365 vcpu_load(vcpu);
e9b11c17
ZX		 8366 kvm_mmu_unload(vcpu);
8367 vcpu_put(vcpu);
8368
8369 kvm_x86_ops->vcpu_free(vcpu);
8370}
8371
d28bc9dd 8372void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8373{
b7e31be3
RK		 8374 kvm_lapic_reset(vcpu, init_event);
8375
e69fab5d
PB		 8376 vcpu->arch.hflags = 0;
8377
c43203ca 8378 vcpu->arch.smi_pending = 0;
52797bf9 8379 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8380 atomic_set(&vcpu->arch.nmi_queued, 0);
8381 vcpu->arch.nmi_pending = 0;
448fa4a9 8382 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8383 kvm_clear_interrupt_queue(vcpu);
8384 kvm_clear_exception_queue(vcpu);
664f8e26 8385 vcpu->arch.exception.pending = false;
448fa4a9 8386
42dbaa5a 8387 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8388 kvm_update_dr0123(vcpu);
6f43ed01 8389 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8390 kvm_update_dr6(vcpu);
42dbaa5a 8391 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8392 kvm_update_dr7(vcpu);
42dbaa5a 8393
1119022c
NA		 8394 vcpu->arch.cr2 = 0;
8395
3842d135 8396 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8397 vcpu->arch.apf.msr_val = 0;
c9aaa895 8398 vcpu->arch.st.msr_val = 0;
3842d135 8399
12f9a48f
GC		 8400 kvmclock_reset(vcpu);
8401
af585b92
GN		 8402 kvm_clear_async_pf_completion_queue(vcpu);
8403 kvm_async_pf_hash_reset(vcpu);
8404 vcpu->arch.apf.halted = false;
3842d135 8405
a554d207
WL		 8406 if (kvm_mpx_supported()) {
8407 void *mpx_state_buffer;
8408
8409 /*
8410 * To avoid have the INIT path from kvm_apic_has_events() that be
8411 * called with loaded FPU and does not let userspace fix the state.
8412 */
f775b13e
RR		 8413 if (init_event)
8414 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8415 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8416 XFEATURE_MASK_BNDREGS);
8417 if (mpx_state_buffer)
8418 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8419 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8420 XFEATURE_MASK_BNDCSR);
8421 if (mpx_state_buffer)
8422 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8423 if (init_event)
8424 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8425 }
8426
64d60670 8427 if (!init_event) {
d28bc9dd 8428 kvm_pmu_reset(vcpu);
64d60670 8429 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8430
8431 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8432 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8433
8434 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8435 }
f5132b01 8436
66f7b72e
JS		 8437 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8438 vcpu->arch.regs_avail = ~0;
8439 vcpu->arch.regs_dirty = ~0;
8440
a554d207
WL		 8441 vcpu->arch.ia32_xss = 0;
8442
d28bc9dd 8443 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8444}
8445
2b4a273b 8446void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8447{
8448 struct kvm_segment cs;
8449
8450 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8451 cs.selector = vector << 8;
8452 cs.base = vector << 12;
8453 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8454 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8455}
8456
13a34e06 8457int kvm_arch_hardware_enable(void)
e9b11c17 8458{
ca84d1a2
ZA		 8459 struct kvm *kvm;
8460 struct kvm_vcpu *vcpu;
8461 int i;
0dd6a6ed
ZA		 8462 int ret;
8463 u64 local_tsc;
8464 u64 max_tsc = 0;
8465 bool stable, backwards_tsc = false;
18863bdd
AK		 8466
8467 kvm_shared_msr_cpu_online();
13a34e06 8468 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8469 if (ret != 0)
8470 return ret;
8471
4ea1636b 8472 local_tsc = rdtsc();
b0c39dc6 8473 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8474 list_for_each_entry(kvm, &vm_list, vm_list) {
8475 kvm_for_each_vcpu(i, vcpu, kvm) {
8476 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8477 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8478 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8479 backwards_tsc = true;
8480 if (vcpu->arch.last_host_tsc > max_tsc)
8481 max_tsc = vcpu->arch.last_host_tsc;
8482 }
8483 }
8484 }
8485
8486 /*
8487 * Sometimes, even reliable TSCs go backwards. This happens on
8488 * platforms that reset TSC during suspend or hibernate actions, but
8489 * maintain synchronization. We must compensate. Fortunately, we can
8490 * detect that condition here, which happens early in CPU bringup,
8491 * before any KVM threads can be running. Unfortunately, we can't
8492 * bring the TSCs fully up to date with real time, as we aren't yet far
8493 * enough into CPU bringup that we know how much real time has actually
108b249c 8494 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8495 * variables that haven't been updated yet.
8496 *
8497 * So we simply find the maximum observed TSC above, then record the
8498 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8499 * the adjustment will be applied. Note that we accumulate
8500 * adjustments, in case multiple suspend cycles happen before some VCPU
8501 * gets a chance to run again. In the event that no KVM threads get a
8502 * chance to run, we will miss the entire elapsed period, as we'll have
8503 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8504 * loose cycle time. This isn't too big a deal, since the loss will be
8505 * uniform across all VCPUs (not to mention the scenario is extremely
8506 * unlikely). It is possible that a second hibernate recovery happens
8507 * much faster than a first, causing the observed TSC here to be
8508 * smaller; this would require additional padding adjustment, which is
8509 * why we set last_host_tsc to the local tsc observed here.
8510 *
8511 * N.B. - this code below runs only on platforms with reliable TSC,
8512 * as that is the only way backwards_tsc is set above. Also note
8513 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8514 * have the same delta_cyc adjustment applied if backwards_tsc
8515 * is detected. Note further, this adjustment is only done once,
8516 * as we reset last_host_tsc on all VCPUs to stop this from being
8517 * called multiple times (one for each physical CPU bringup).
8518 *
4a969980 8519 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8520 * will be compensated by the logic in vcpu_load, which sets the TSC to
8521 * catchup mode. This will catchup all VCPUs to real time, but cannot
8522 * guarantee that they stay in perfect synchronization.
8523 */
8524 if (backwards_tsc) {
8525 u64 delta_cyc = max_tsc - local_tsc;
8526 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8527 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8528 kvm_for_each_vcpu(i, vcpu, kvm) {
8529 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8530 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8531 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8532 }
8533
8534 /*
8535 * We have to disable TSC offset matching.. if you were
8536 * booting a VM while issuing an S4 host suspend....
8537 * you may have some problem. Solving this issue is
8538 * left as an exercise to the reader.
8539 */
8540 kvm->arch.last_tsc_nsec = 0;
8541 kvm->arch.last_tsc_write = 0;
8542 }
8543
8544 }
8545 return 0;
e9b11c17
ZX		 8546}
8547
13a34e06 8548void kvm_arch_hardware_disable(void)
e9b11c17 8549{
13a34e06
RK		 8550 kvm_x86_ops->hardware_disable();
8551 drop_user_return_notifiers();
e9b11c17
ZX		 8552}
8553
8554int kvm_arch_hardware_setup(void)
8555{
9e9c3fe4
NA		 8556 int r;
8557
8558 r = kvm_x86_ops->hardware_setup();
8559 if (r != 0)
8560 return r;
8561
35181e86
HZ		 8562 if (kvm_has_tsc_control) {
8563 /*
8564 * Make sure the user can only configure tsc_khz values that
8565 * fit into a signed integer.
8566 * A min value is not calculated needed because it will always
8567 * be 1 on all machines.
8568 */
8569 u64 max = min(0x7fffffffULL,
8570 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8571 kvm_max_guest_tsc_khz = max;
8572
ad721883 8573 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8574 }
ad721883 8575
9e9c3fe4
NA		 8576 kvm_init_msr_list();
8577 return 0;
e9b11c17
ZX		 8578}
8579
8580void kvm_arch_hardware_unsetup(void)
8581{
8582 kvm_x86_ops->hardware_unsetup();
8583}
8584
8585void kvm_arch_check_processor_compat(void *rtn)
8586{
8587 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8588}
8589
8590bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8591{
8592 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8593}
8594EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8595
8596bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8597{
8598 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8599}
8600
54e9818f 8601struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8602EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8603
e9b11c17
ZX		 8604int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8605{
8606 struct page *page;
e9b11c17
ZX		 8607 int r;
8608
b2a05fef 8609 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8610 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8611 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8612 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8613 else
a4535290 8614 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8615
8616 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8617 if (!page) {
8618 r = -ENOMEM;
8619 goto fail;
8620 }
ad312c7c 8621 vcpu->arch.pio_data = page_address(page);
e9b11c17 8622
cc578287 8623 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8624
e9b11c17
ZX		 8625 r = kvm_mmu_create(vcpu);
8626 if (r < 0)
8627 goto fail_free_pio_data;
8628
26de7988 8629 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8630 r = kvm_create_lapic(vcpu);
8631 if (r < 0)
8632 goto fail_mmu_destroy;
54e9818f
GN		 8633 } else
8634 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8635
890ca9ae
HY		 8636 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8637 GFP_KERNEL);
8638 if (!vcpu->arch.mce_banks) {
8639 r = -ENOMEM;
443c39bc 8640 goto fail_free_lapic;
890ca9ae
HY		 8641 }
8642 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8643
f1797359
WY		 8644 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8645 r = -ENOMEM;
f5f48ee1 8646 goto fail_free_mce_banks;
f1797359 8647 }
f5f48ee1 8648
0ee6a517 8649 fx_init(vcpu);
66f7b72e 8650
4344ee98 8651 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8652
5a4f55cd
EK		 8653 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8654
74545705
RK		 8655 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8656
af585b92 8657 kvm_async_pf_hash_reset(vcpu);
f5132b01 8658 kvm_pmu_init(vcpu);
af585b92 8659
1c1a9ce9 8660 vcpu->arch.pending_external_vector = -1;
de63ad4c 8661 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8662
5c919412
AS		 8663 kvm_hv_vcpu_init(vcpu);
8664
e9b11c17 8665 return 0;
0ee6a517 8666
f5f48ee1
SY		 8667fail_free_mce_banks:
8668 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8669fail_free_lapic:
8670 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8671fail_mmu_destroy:
8672 kvm_mmu_destroy(vcpu);
8673fail_free_pio_data:
ad312c7c 8674 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8675fail:
8676 return r;
8677}
8678
8679void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8680{
f656ce01
MT		 8681 int idx;
8682
1f4b34f8 8683 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8684 kvm_pmu_destroy(vcpu);
36cb93fd 8685 kfree(vcpu->arch.mce_banks);
e9b11c17 8686 kvm_free_lapic(vcpu);
f656ce01 8687 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8688 kvm_mmu_destroy(vcpu);
f656ce01 8689 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8690 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8691 if (!lapic_in_kernel(vcpu))
54e9818f 8692 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8693}
d19a9cd2 8694
e790d9ef
RK		 8695void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8696{
ae97a3b8 8697 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8698}
8699
e08b9637 8700int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8701{
e08b9637
CO		 8702 if (type)
8703 return -EINVAL;
8704
6ef768fa 8705 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8706 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8707 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8708 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8709 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8710
5550af4d
SY		 8711 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8712 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8713 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8714 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8715 &kvm->arch.irq_sources_bitmap);
5550af4d 8716
038f8c11 8717 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8718 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8719 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8720
108b249c 8721 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8722 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8723
7e44e449 8724 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8725 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8726
cbc0236a 8727 kvm_hv_init_vm(kvm);
0eb05bf2 8728 kvm_page_track_init(kvm);
13d268ca 8729 kvm_mmu_init_vm(kvm);
0eb05bf2 8730
03543133
SS		 8731 if (kvm_x86_ops->vm_init)
8732 return kvm_x86_ops->vm_init(kvm);
8733
d89f5eff 8734 return 0;
d19a9cd2
ZX		 8735}
8736
8737static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8738{
ec7660cc 8739 vcpu_load(vcpu);
d19a9cd2
ZX		 8740 kvm_mmu_unload(vcpu);
8741 vcpu_put(vcpu);
8742}
8743
8744static void kvm_free_vcpus(struct kvm *kvm)
8745{
8746 unsigned int i;
988a2cae 8747 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8748
8749 /*
8750 * Unpin any mmu pages first.
8751 */
af585b92
GN		 8752 kvm_for_each_vcpu(i, vcpu, kvm) {
8753 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8754 kvm_unload_vcpu_mmu(vcpu);
af585b92 8755 }
988a2cae
GN		 8756 kvm_for_each_vcpu(i, vcpu, kvm)
8757 kvm_arch_vcpu_free(vcpu);
8758
8759 mutex_lock(&kvm->lock);
8760 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8761 kvm->vcpus[i] = NULL;
d19a9cd2 8762
988a2cae
GN		 8763 atomic_set(&kvm->online_vcpus, 0);
8764 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8765}
8766
ad8ba2cd
SY		 8767void kvm_arch_sync_events(struct kvm *kvm)
8768{
332967a3 8769 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8770 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8771 kvm_free_pit(kvm);
ad8ba2cd
SY		 8772}
8773
1d8007bd 8774int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8775{
8776 int i, r;
25188b99 8777 unsigned long hva;
f0d648bd
PB		 8778 struct kvm_memslots *slots = kvm_memslots(kvm);
8779 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8780
8781 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8782 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8783 return -EINVAL;
9da0e4d5 8784
f0d648bd
PB		 8785 slot = id_to_memslot(slots, id);
8786 if (size) {
b21629da 8787 if (slot->npages)
f0d648bd
PB		 8788 return -EEXIST;
8789
8790 /*
8791 * MAP_SHARED to prevent internal slot pages from being moved
8792 * by fork()/COW.
8793 */
8794 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8795 MAP_SHARED | MAP_ANONYMOUS, 0);
8796 if (IS_ERR((void *)hva))
8797 return PTR_ERR((void *)hva);
8798 } else {
8799 if (!slot->npages)
8800 return 0;
8801
8802 hva = 0;
8803 }
8804
8805 old = *slot;
9da0e4d5 8806 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8807 struct kvm_userspace_memory_region m;
9da0e4d5 8808
1d8007bd
PB		 8809 m.slot = id | (i << 16);
8810 m.flags = 0;
8811 m.guest_phys_addr = gpa;
f0d648bd 8812 m.userspace_addr = hva;
1d8007bd 8813 m.memory_size = size;
9da0e4d5
PB		 8814 r = __kvm_set_memory_region(kvm, &m);
8815 if (r < 0)
8816 return r;
8817 }
8818
103c763c
EB		 8819 if (!size)
8820 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8821
9da0e4d5
PB		 8822 return 0;
8823}
8824EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8825
1d8007bd 8826int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8827{
8828 int r;
8829
8830 mutex_lock(&kvm->slots_lock);
1d8007bd 8831 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8832 mutex_unlock(&kvm->slots_lock);
8833
8834 return r;
8835}
8836EXPORT_SYMBOL_GPL(x86_set_memory_region);
8837
d19a9cd2
ZX		 8838void kvm_arch_destroy_vm(struct kvm *kvm)
8839{
27469d29
AH		 8840 if (current->mm == kvm->mm) {
8841 /*
8842 * Free memory regions allocated on behalf of userspace,
8843 * unless the the memory map has changed due to process exit
8844 * or fd copying.
8845 */
1d8007bd
PB		 8846 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8847 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8848 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8849 }
03543133
SS		 8850 if (kvm_x86_ops->vm_destroy)
8851 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8852 kvm_pic_destroy(kvm);
8853 kvm_ioapic_destroy(kvm);
d19a9cd2 8854 kvm_free_vcpus(kvm);
af1bae54 8855 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8856 kvm_mmu_uninit_vm(kvm);
2beb6dad 8857 kvm_page_track_cleanup(kvm);
cbc0236a 8858 kvm_hv_destroy_vm(kvm);
d19a9cd2 8859}
0de10343 8860
5587027c 8861void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8862 struct kvm_memory_slot *dont)
8863{
8864 int i;
8865
d89cc617
TY		 8866 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8867 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8868 kvfree(free->arch.rmap[i]);
d89cc617 8869 free->arch.rmap[i] = NULL;
77d11309 8870 }
d89cc617
TY		 8871 if (i == 0)
8872 continue;
8873
8874 if (!dont || free->arch.lpage_info[i - 1] !=
8875 dont->arch.lpage_info[i - 1]) {
548ef284 8876 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8877 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8878 }
8879 }
21ebbeda
XG		 8880
8881 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8882}
8883
5587027c
AK		 8884int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8885 unsigned long npages)
db3fe4eb
TY		 8886{
8887 int i;
8888
d89cc617 8889 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8890 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8891 unsigned long ugfn;
8892 int lpages;
d89cc617 8893 int level = i + 1;
db3fe4eb
TY		 8894
8895 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8896 slot->base_gfn, level) + 1;
8897
d89cc617 8898 slot->arch.rmap[i] =
a7c3e901 8899 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8900 if (!slot->arch.rmap[i])
77d11309 8901 goto out_free;
d89cc617
TY		 8902 if (i == 0)
8903 continue;
77d11309 8904
a7c3e901 8905 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8906 if (!linfo)
db3fe4eb
TY		 8907 goto out_free;
8908
92f94f1e
XG		 8909 slot->arch.lpage_info[i - 1] = linfo;
8910
db3fe4eb 8911 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8912 linfo[0].disallow_lpage = 1;
db3fe4eb 8913 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8914 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8915 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8916 /*
8917 * If the gfn and userspace address are not aligned wrt each
8918 * other, or if explicitly asked to, disable large page
8919 * support for this slot
8920 */
8921 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8922 !kvm_largepages_enabled()) {
8923 unsigned long j;
8924
8925 for (j = 0; j < lpages; ++j)
92f94f1e 8926 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8927 }
8928 }
8929
21ebbeda
XG		 8930 if (kvm_page_track_create_memslot(slot, npages))
8931 goto out_free;
8932
db3fe4eb
TY		 8933 return 0;
8934
8935out_free:
d89cc617 8936 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8937 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8938 slot->arch.rmap[i] = NULL;
8939 if (i == 0)
8940 continue;
8941
548ef284 8942 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8943 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8944 }
8945 return -ENOMEM;
8946}
8947
15f46015 8948void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8949{
e6dff7d1
TY		 8950 /*
8951 * memslots->generation has been incremented.
8952 * mmio generation may have reached its maximum value.
8953 */
54bf36aa 8954 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8955}
8956
f7784b8e
MT		 8957int kvm_arch_prepare_memory_region(struct kvm *kvm,
8958 struct kvm_memory_slot *memslot,
09170a49 8959 const struct kvm_userspace_memory_region *mem,
7b6195a9 8960 enum kvm_mr_change change)
0de10343 8961{
f7784b8e
MT		 8962 return 0;
8963}
8964
88178fd4
KH		 8965static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8966 struct kvm_memory_slot *new)
8967{
8968 /* Still write protect RO slot */
8969 if (new->flags & KVM_MEM_READONLY) {
8970 kvm_mmu_slot_remove_write_access(kvm, new);
8971 return;
8972 }
8973
8974 /*
8975 * Call kvm_x86_ops dirty logging hooks when they are valid.
8976 *
8977 * kvm_x86_ops->slot_disable_log_dirty is called when:
8978 *
8979 * - KVM_MR_CREATE with dirty logging is disabled
8980 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8981 *
8982 * The reason is, in case of PML, we need to set D-bit for any slots
8983 * with dirty logging disabled in order to eliminate unnecessary GPA
8984 * logging in PML buffer (and potential PML buffer full VMEXT). This
8985 * guarantees leaving PML enabled during guest's lifetime won't have
8986 * any additonal overhead from PML when guest is running with dirty
8987 * logging disabled for memory slots.
8988 *
8989 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8990 * to dirty logging mode.
8991 *
8992 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8993 *
8994 * In case of write protect:
8995 *
8996 * Write protect all pages for dirty logging.
8997 *
8998 * All the sptes including the large sptes which point to this
8999 * slot are set to readonly. We can not create any new large
9000 * spte on this slot until the end of the logging.
9001 *
9002 * See the comments in fast_page_fault().
9003 */
9004 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9005 if (kvm_x86_ops->slot_enable_log_dirty)
9006 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9007 else
9008 kvm_mmu_slot_remove_write_access(kvm, new);
9009 } else {
9010 if (kvm_x86_ops->slot_disable_log_dirty)
9011 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9012 }
9013}
9014
f7784b8e 9015void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9016 const struct kvm_userspace_memory_region *mem,
8482644a 9017 const struct kvm_memory_slot *old,
f36f3f28 9018 const struct kvm_memory_slot *new,
8482644a 9019 enum kvm_mr_change change)
f7784b8e 9020{
8482644a 9021 int nr_mmu_pages = 0;
f7784b8e 9022
48c0e4e9
XG		 9023 if (!kvm->arch.n_requested_mmu_pages)
9024 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9025
48c0e4e9 9026 if (nr_mmu_pages)
0de10343 9027 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9028
3ea3b7fa
WL		 9029 /*
9030 * Dirty logging tracks sptes in 4k granularity, meaning that large
9031 * sptes have to be split. If live migration is successful, the guest
9032 * in the source machine will be destroyed and large sptes will be
9033 * created in the destination. However, if the guest continues to run
9034 * in the source machine (for example if live migration fails), small
9035 * sptes will remain around and cause bad performance.
9036 *
9037 * Scan sptes if dirty logging has been stopped, dropping those
9038 * which can be collapsed into a single large-page spte. Later
9039 * page faults will create the large-page sptes.
9040 */
9041 if ((change != KVM_MR_DELETE) &&
9042 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9043 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9044 kvm_mmu_zap_collapsible_sptes(kvm, new);
9045
c972f3b1 9046 /*
88178fd4 9047 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9048 *
88178fd4
KH		 9049 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9050 * been zapped so no dirty logging staff is needed for old slot. For
9051 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9052 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9053 *
9054 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9055 */
88178fd4 9056 if (change != KVM_MR_DELETE)
f36f3f28 9057 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9058}
1d737c8a 9059
2df72e9b 9060void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9061{
6ca18b69 9062 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9063}
9064
2df72e9b
MT		 9065void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9066 struct kvm_memory_slot *slot)
9067{
ae7cd873 9068 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9069}
9070
5d9bc648
PB		 9071static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9072{
9073 if (!list_empty_careful(&vcpu->async_pf.done))
9074 return true;
9075
9076 if (kvm_apic_has_events(vcpu))
9077 return true;
9078
9079 if (vcpu->arch.pv.pv_unhalted)
9080 return true;
9081
a5f01f8e
WL		 9082 if (vcpu->arch.exception.pending)
9083 return true;
9084
47a66eed
Z		 9085 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9086 (vcpu->arch.nmi_pending &&
9087 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9088 return true;
9089
47a66eed
Z		 9090 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9091 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9092 return true;
9093
5d9bc648
PB		 9094 if (kvm_arch_interrupt_allowed(vcpu) &&
9095 kvm_cpu_has_interrupt(vcpu))
9096 return true;
9097
1f4b34f8
AS		 9098 if (kvm_hv_has_stimer_pending(vcpu))
9099 return true;
9100
5d9bc648
PB		 9101 return false;
9102}
9103
1d737c8a
ZX		 9104int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9105{
5d9bc648 9106 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9107}
5736199a 9108
199b5763
LM		 9109bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9110{
de63ad4c 9111 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9112}
9113
b6d33834 9114int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9115{
b6d33834 9116 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9117}
78646121
GN		 9118
9119int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9120{
9121 return kvm_x86_ops->interrupt_allowed(vcpu);
9122}
229456fc 9123
82b32774 9124unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9125{
82b32774
NA		 9126 if (is_64_bit_mode(vcpu))
9127 return kvm_rip_read(vcpu);
9128 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9129 kvm_rip_read(vcpu));
9130}
9131EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9132
82b32774
NA		 9133bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9134{
9135 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9136}
9137EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9138
94fe45da
JK		 9139unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9140{
9141 unsigned long rflags;
9142
9143 rflags = kvm_x86_ops->get_rflags(vcpu);
9144 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9145 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9146 return rflags;
9147}
9148EXPORT_SYMBOL_GPL(kvm_get_rflags);
9149
6addfc42 9150static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9151{
9152 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9153 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9154 rflags |= X86_EFLAGS_TF;
94fe45da 9155 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9156}
9157
9158void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9159{
9160 __kvm_set_rflags(vcpu, rflags);
3842d135 9161 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9162}
9163EXPORT_SYMBOL_GPL(kvm_set_rflags);
9164
56028d08
GN		 9165void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9166{
9167 int r;
9168
fb67e14f 9169 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9170 work->wakeup_all)
56028d08
GN		 9171 return;
9172
9173 r = kvm_mmu_reload(vcpu);
9174 if (unlikely(r))
9175 return;
9176
fb67e14f
XG		 9177 if (!vcpu->arch.mmu.direct_map &&
9178 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9179 return;
9180
56028d08
GN		 9181 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9182}
9183
af585b92
GN		 9184static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9185{
9186 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9187}
9188
9189static inline u32 kvm_async_pf_next_probe(u32 key)
9190{
9191 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9192}
9193
9194static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9195{
9196 u32 key = kvm_async_pf_hash_fn(gfn);
9197
9198 while (vcpu->arch.apf.gfns[key] != ~0)
9199 key = kvm_async_pf_next_probe(key);
9200
9201 vcpu->arch.apf.gfns[key] = gfn;
9202}
9203
9204static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9205{
9206 int i;
9207 u32 key = kvm_async_pf_hash_fn(gfn);
9208
9209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9210 (vcpu->arch.apf.gfns[key] != gfn &&
9211 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9212 key = kvm_async_pf_next_probe(key);
9213
9214 return key;
9215}
9216
9217bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9218{
9219 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9220}
9221
9222static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9223{
9224 u32 i, j, k;
9225
9226 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9227 while (true) {
9228 vcpu->arch.apf.gfns[i] = ~0;
9229 do {
9230 j = kvm_async_pf_next_probe(j);
9231 if (vcpu->arch.apf.gfns[j] == ~0)
9232 return;
9233 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9234 /*
9235 * k lies cyclically in ]i,j]
9236 * | i.k.j |
9237 * |....j i.k.| or |.k..j i...|
9238 */
9239 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9240 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9241 i = j;
9242 }
9243}
9244
7c90705b
GN		 9245static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9246{
4e335d9e
PB		 9247
9248 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9249 sizeof(val));
7c90705b
GN		 9250}
9251
9a6e7c39
WL		 9252static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9253{
9254
9255 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9256 sizeof(u32));
9257}
9258
af585b92
GN		 9259void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9260 struct kvm_async_pf *work)
9261{
6389ee94
AK		 9262 struct x86_exception fault;
9263
7c90705b 9264 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9265 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9266
9267 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9268 (vcpu->arch.apf.send_user_only &&
9269 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9270 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9271 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9272 fault.vector = PF_VECTOR;
9273 fault.error_code_valid = true;
9274 fault.error_code = 0;
9275 fault.nested_page_fault = false;
9276 fault.address = work->arch.token;
adfe20fb 9277 fault.async_page_fault = true;
6389ee94 9278 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9279 }
af585b92
GN		 9280}
9281
9282void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9283 struct kvm_async_pf *work)
9284{
6389ee94 9285 struct x86_exception fault;
9a6e7c39 9286 u32 val;
6389ee94 9287
f2e10669 9288 if (work->wakeup_all)
7c90705b
GN		 9289 work->arch.token = ~0; /* broadcast wakeup */
9290 else
9291 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9292 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9293
9a6e7c39
WL		 9294 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9295 !apf_get_user(vcpu, &val)) {
9296 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9297 vcpu->arch.exception.pending &&
9298 vcpu->arch.exception.nr == PF_VECTOR &&
9299 !apf_put_user(vcpu, 0)) {
9300 vcpu->arch.exception.injected = false;
9301 vcpu->arch.exception.pending = false;
9302 vcpu->arch.exception.nr = 0;
9303 vcpu->arch.exception.has_error_code = false;
9304 vcpu->arch.exception.error_code = 0;
9305 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9306 fault.vector = PF_VECTOR;
9307 fault.error_code_valid = true;
9308 fault.error_code = 0;
9309 fault.nested_page_fault = false;
9310 fault.address = work->arch.token;
9311 fault.async_page_fault = true;
9312 kvm_inject_page_fault(vcpu, &fault);
9313 }
7c90705b 9314 }
e6d53e3b 9315 vcpu->arch.apf.halted = false;
a4fa1635 9316 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9317}
9318
9319bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9320{
9321 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9322 return true;
9323 else
9bc1f09f 9324 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9325}
9326
5544eb9b
PB		 9327void kvm_arch_start_assignment(struct kvm *kvm)
9328{
9329 atomic_inc(&kvm->arch.assigned_device_count);
9330}
9331EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9332
9333void kvm_arch_end_assignment(struct kvm *kvm)
9334{
9335 atomic_dec(&kvm->arch.assigned_device_count);
9336}
9337EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9338
9339bool kvm_arch_has_assigned_device(struct kvm *kvm)
9340{
9341 return atomic_read(&kvm->arch.assigned_device_count);
9342}
9343EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9344
e0f0bbc5
AW		 9345void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9346{
9347 atomic_inc(&kvm->arch.noncoherent_dma_count);
9348}
9349EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9350
9351void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9352{
9353 atomic_dec(&kvm->arch.noncoherent_dma_count);
9354}
9355EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9356
9357bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9358{
9359 return atomic_read(&kvm->arch.noncoherent_dma_count);
9360}
9361EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9362
14717e20
AW		 9363bool kvm_arch_has_irq_bypass(void)
9364{
9365 return kvm_x86_ops->update_pi_irte != NULL;
9366}
9367
87276880
FW		 9368int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9369 struct irq_bypass_producer *prod)
9370{
9371 struct kvm_kernel_irqfd *irqfd =
9372 container_of(cons, struct kvm_kernel_irqfd, consumer);
9373
14717e20 9374 irqfd->producer = prod;
87276880 9375
14717e20
AW		 9376 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9377 prod->irq, irqfd->gsi, 1);
87276880
FW		 9378}
9379
9380void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9381 struct irq_bypass_producer *prod)
9382{
9383 int ret;
9384 struct kvm_kernel_irqfd *irqfd =
9385 container_of(cons, struct kvm_kernel_irqfd, consumer);
9386
87276880
FW		 9387 WARN_ON(irqfd->producer != prod);
9388 irqfd->producer = NULL;
9389
9390 /*
9391 * When producer of consumer is unregistered, we change back to
9392 * remapped mode, so we can re-use the current implementation
bb3541f1 9393 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9394 * int this case doesn't want to receive the interrupts.
9395 */
9396 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9397 if (ret)
9398 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9399 " fails: %d\n", irqfd->consumer.token, ret);
9400}
9401
9402int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9403 uint32_t guest_irq, bool set)
9404{
9405 if (!kvm_x86_ops->update_pi_irte)
9406 return -EINVAL;
9407
9408 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9409}
9410
52004014
FW		 9411bool kvm_vector_hashing_enabled(void)
9412{
9413 return vector_hashing;
9414}
9415EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9416
229456fc 9417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9423EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9424EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9425EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9426EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9427EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9428EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9429EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9430EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9431EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9432EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9433EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9434EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9435EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)