projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
x86: KVM: svm: eliminate hardcoded RIP advancement from vmrun_interception()
[linux-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
0c5f81da 54#include <linux/sched/isolation.h>
d0ec49d4 55#include <linux/mem_encrypt.h>
3905f9ad 56
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
b0c39dc6 68#include <asm/mshyperv.h>
0092e434 69#include <asm/hypervisor.h>
bf8c55d8 70#include <asm/intel_pt.h>
dd2cb348 71#include <clocksource/hyperv_timer.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
c3941d9e
SC		 138/*
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
143 */
144static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 145module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 146
52004014
FW		 147static bool __read_mostly vector_hashing = true;
148module_param(vector_hashing, bool, S_IRUGO);
149
c4ae60e4
LA		 150bool __read_mostly enable_vmware_backdoor = false;
151module_param(enable_vmware_backdoor, bool, S_IRUGO);
152EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
153
6c86eedc
WL		 154static bool __read_mostly force_emulation_prefix = false;
155module_param(force_emulation_prefix, bool, S_IRUGO);
156
0c5f81da
WL		 157int __read_mostly pi_inject_timer = -1;
158module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
159
18863bdd
AK		 160#define KVM_NR_SHARED_MSRS 16
161
162struct kvm_shared_msrs_global {
163 int nr;
2bf78fa7 164 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 165};
166
167struct kvm_shared_msrs {
168 struct user_return_notifier urn;
169 bool registered;
2bf78fa7
SY		 170 struct kvm_shared_msr_values {
171 u64 host;
172 u64 curr;
173 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 174};
175
176static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 177static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 178
417bc304 179struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 190 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 195 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 202 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 203 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 204 { "req_event", VCPU_STAT(req_event) },
c595ceee 205 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 213 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 215 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 218 { NULL }
219};
220
2acf923e
DC		 221u64 __read_mostly host_xcr0;
222
b666a4b6
MO		 223struct kmem_cache *x86_fpu_cache;
224EXPORT_SYMBOL_GPL(x86_fpu_cache);
225
b6785def 226static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 227
af585b92
GN		 228static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229{
230 int i;
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
233}
234
18863bdd
AK		 235static void kvm_on_user_return(struct user_return_notifier *urn)
236{
237 unsigned slot;
18863bdd
AK		 238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 240 struct kvm_shared_msr_values *values;
1650b4eb
IA		 241 unsigned long flags;
242
243 /*
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
246 */
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
251 }
252 local_irq_restore(flags);
18863bdd 253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
18863bdd
AK		 258 }
259 }
18863bdd
AK		 260}
261
2bf78fa7 262static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 263{
18863bdd 264 u64 value;
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 267
2bf78fa7
SY		 268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
272 return;
273 }
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
277}
278
279void kvm_define_shared_msr(unsigned slot, u32 msr)
280{
0123be42 281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 282 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 285}
286EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
287
288static void kvm_shared_msr_cpu_online(void)
289{
290 unsigned i;
18863bdd
AK		 291
292 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 293 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 294}
295
8b3c3104 296int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 300 int err;
18863bdd 301
2bf78fa7 302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 303 return 0;
2bf78fa7 304 smsr->values[slot].curr = value;
8b3c3104
AH		 305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
306 if (err)
307 return 1;
308
18863bdd
AK		 309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
313 }
8b3c3104 314 return 0;
18863bdd
AK		 315}
316EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
317
13a34e06 318static void drop_user_return_notifiers(void)
3548bab5 319{
013f6a5d
MT		 320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 322
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
325}
326
6866b83e
CO		 327u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
328{
8a5a87d9 329 return vcpu->arch.apic_base;
6866b83e
CO		 330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_base);
332
58871649
JM		 333enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
334{
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
336}
337EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
338
58cb628d
JK		 339int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
340{
58871649
JM		 341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 345
58871649 346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 347 return 1;
58871649
JM		 348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
350 return 1;
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 return 1;
353 }
58cb628d
JK		 354
355 kvm_lapic_set_base(vcpu, msr_info->data);
356 return 0;
6866b83e
CO		 357}
358EXPORT_SYMBOL_GPL(kvm_set_apic_base);
359
2605fc21 360asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 361{
362 /* Fault while not rebooting. We want the trace. */
363 BUG();
364}
365EXPORT_SYMBOL_GPL(kvm_spurious_fault);
366
3fd28fce
ED		 367#define EXCPT_BENIGN 0
368#define EXCPT_CONTRIBUTORY 1
369#define EXCPT_PF 2
370
371static int exception_class(int vector)
372{
373 switch (vector) {
374 case PF_VECTOR:
375 return EXCPT_PF;
376 case DE_VECTOR:
377 case TS_VECTOR:
378 case NP_VECTOR:
379 case SS_VECTOR:
380 case GP_VECTOR:
381 return EXCPT_CONTRIBUTORY;
382 default:
383 break;
384 }
385 return EXCPT_BENIGN;
386}
387
d6e8c854
NA		 388#define EXCPT_FAULT 0
389#define EXCPT_TRAP 1
390#define EXCPT_ABORT 2
391#define EXCPT_INTERRUPT 3
392
393static int exception_type(int vector)
394{
395 unsigned int mask;
396
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
399
400 mask = 1 << vector;
401
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
404 return EXCPT_TRAP;
405
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
407 return EXCPT_ABORT;
408
409 /* Reserved exceptions will result in fault */
410 return EXCPT_FAULT;
411}
412
da998b46
JM		 413void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
414{
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
418
419 if (!has_payload)
420 return;
421
422 switch (nr) {
f10c729f
JM		 423 case DB_VECTOR:
424 /*
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
428 */
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
430 /*
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
432 */
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
435 /*
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
442 */
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
444 break;
da998b46
JM		 445 case PF_VECTOR:
446 vcpu->arch.cr2 = payload;
447 break;
448 }
449
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
452}
453EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
454
3fd28fce 455static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 456 unsigned nr, bool has_error, u32 error_code,
91e86d22 457 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 458{
459 u32 prev_nr;
460 int class1, class2;
461
3842d135
AK		 462 kvm_make_request(KVM_REQ_EVENT, vcpu);
463
664f8e26 464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 465 queue:
3ffb2468
NA		 466 if (has_error && !is_protmode(vcpu))
467 has_error = false;
664f8e26
WL		 468 if (reinject) {
469 /*
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
475 * need reinjection.
476 */
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
91e86d22
JM		 479 if (WARN_ON_ONCE(has_payload)) {
480 /*
481 * A reinjected event has already
482 * delivered its payload.
483 */
484 has_payload = false;
485 payload = 0;
486 }
664f8e26
WL		 487 } else {
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
490 }
3fd28fce
ED		 491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
da998b46
JM		 496 /*
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 506 */
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 510 return;
511 }
512
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
a8eeb04a 517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 518 return;
519 }
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 524 /*
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
528 */
3fd28fce 529 vcpu->arch.exception.pending = true;
664f8e26 530 vcpu->arch.exception.injected = false;
3fd28fce
ED		 531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
c851436a
JM		 534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 536 } else
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
539 exception */
540 goto queue;
541}
542
298101da
AK		 543void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
91e86d22 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 546}
547EXPORT_SYMBOL_GPL(kvm_queue_exception);
548
ce7ddec4
JR		 549void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
550{
91e86d22 551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 552}
553EXPORT_SYMBOL_GPL(kvm_requeue_exception);
554
f10c729f
JM		 555static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
559}
560
da998b46
JM		 561static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
563{
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
566}
567
6affcbed 568int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 569{
db8fcefa
AP		 570 if (err)
571 kvm_inject_gp(vcpu, 0);
572 else
6affcbed
KH		 573 return kvm_skip_emulated_instruction(vcpu);
574
575 return 1;
db8fcefa
AP		 576}
577EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 578
6389ee94 579void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 580{
581 ++vcpu->stat.pf_guest;
adfe20fb
WL		 582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 584 if (vcpu->arch.exception.nested_apf) {
adfe20fb 585 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
587 } else {
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
589 fault->address);
590 }
c3c91fee 591}
27d6c865 592EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 593
ef54bcfe 594static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 595{
6389ee94
AK		 596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 598 else
44dd3ffa 599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 600
601 return fault->nested_page_fault;
d4f8cf66
JR		 602}
603
3419ffc8
SY		 604void kvm_inject_nmi(struct kvm_vcpu *vcpu)
605{
7460fb4a
AK		 606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 608}
609EXPORT_SYMBOL_GPL(kvm_inject_nmi);
610
298101da
AK		 611void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
91e86d22 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 614}
615EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
616
ce7ddec4
JR		 617void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
618{
91e86d22 619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 620}
621EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
622
0a79b009
AK		 623/*
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
626 */
627bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 628{
0a79b009
AK		 629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
630 return true;
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
632 return false;
298101da 633}
0a79b009 634EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 635
16f8a6f9
NA		 636bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
637{
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
639 return true;
640
641 kvm_queue_exception(vcpu, UD_VECTOR);
642 return false;
643}
644EXPORT_SYMBOL_GPL(kvm_require_dr);
645
ec92fe44
JR		 646/*
647 * This function will be used to read from the physical memory of the currently
54bf36aa 648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 649 * can read from guest physical or from the guest's guest physical memory.
650 */
651int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
653 u32 access)
654{
54987b7a 655 struct x86_exception exception;
ec92fe44
JR		 656 gfn_t real_gfn;
657 gpa_t ngpa;
658
659 ngpa = gfn_to_gpa(ngfn);
54987b7a 660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 661 if (real_gfn == UNMAPPED_GVA)
662 return -EFAULT;
663
664 real_gfn = gpa_to_gfn(real_gfn);
665
54bf36aa 666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 667}
668EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
669
69b0049a 670static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 671 void *data, int offset, int len, u32 access)
672{
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
675}
676
a03490ed
CO		 677/*
678 * Load the pae pdptrs. Return true is they are all valid.
679 */
ff03a073 680int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 681{
682 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
683 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
684 int i;
685 int ret;
ff03a073 686 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 687
ff03a073
JR		 688 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
689 offset * sizeof(u64), sizeof(pdpte),
690 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 691 if (ret < 0) {
692 ret = 0;
693 goto out;
694 }
695 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 696 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 697 (pdpte[i] &
44dd3ffa 698 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 699 ret = 0;
700 goto out;
701 }
702 }
703 ret = 1;
704
ff03a073 705 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 706 __set_bit(VCPU_EXREG_PDPTR,
707 (unsigned long *)&vcpu->arch.regs_avail);
708 __set_bit(VCPU_EXREG_PDPTR,
709 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 710out:
a03490ed
CO		 711
712 return ret;
713}
cc4b6871 714EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 715
9ed38ffa 716bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 717{
ff03a073 718 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 719 bool changed = true;
3d06b8bf
JR		 720 int offset;
721 gfn_t gfn;
d835dfec
AK		 722 int r;
723
bf03d4f9 724 if (!is_pae_paging(vcpu))
d835dfec
AK		 725 return false;
726
6de4f3ad
AK		 727 if (!test_bit(VCPU_EXREG_PDPTR,
728 (unsigned long *)&vcpu->arch.regs_avail))
729 return true;
730
a512177e
PB		 731 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
732 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 733 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
734 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 735 if (r < 0)
736 goto out;
ff03a073 737 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 738out:
d835dfec
AK		 739
740 return changed;
741}
9ed38ffa 742EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 743
49a9b07e 744int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 745{
aad82703 746 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 747 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 748
f9a48e6a
AK		 749 cr0 |= X86_CR0_ET;
750
ab344828 751#ifdef CONFIG_X86_64
0f12244f
GN		 752 if (cr0 & 0xffffffff00000000UL)
753 return 1;
ab344828
GN		 754#endif
755
756 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 757
0f12244f
GN		 758 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
759 return 1;
a03490ed 760
0f12244f
GN		 761 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
762 return 1;
a03490ed
CO		 763
764 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
765#ifdef CONFIG_X86_64
f6801dff 766 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 767 int cs_db, cs_l;
768
0f12244f
GN		 769 if (!is_pae(vcpu))
770 return 1;
a03490ed 771 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 772 if (cs_l)
773 return 1;
a03490ed
CO		 774 } else
775#endif
ff03a073 776 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 777 kvm_read_cr3(vcpu)))
0f12244f 778 return 1;
a03490ed
CO		 779 }
780
ad756a16
MJ		 781 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
782 return 1;
783
a03490ed 784 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 785
d170c419 786 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 787 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 788 kvm_async_pf_hash_reset(vcpu);
789 }
e5f3f027 790
aad82703
SY		 791 if ((cr0 ^ old_cr0) & update_bits)
792 kvm_mmu_reset_context(vcpu);
b18d5431 793
879ae188
LE		 794 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
795 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
796 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 797 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
798
0f12244f
GN		 799 return 0;
800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 802
2d3ad1f4 803void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 804{
49a9b07e 805 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 806}
2d3ad1f4 807EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 808
1811d979 809void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 810{
811 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
812 !vcpu->guest_xcr0_loaded) {
813 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 814 if (vcpu->arch.xcr0 != host_xcr0)
815 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 816 vcpu->guest_xcr0_loaded = 1;
817 }
818}
1811d979 819EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 820
1811d979 821void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 822{
823 if (vcpu->guest_xcr0_loaded) {
824 if (vcpu->arch.xcr0 != host_xcr0)
825 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
826 vcpu->guest_xcr0_loaded = 0;
827 }
828}
1811d979 829EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 830
69b0049a 831static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 832{
56c103ec
LJ		 833 u64 xcr0 = xcr;
834 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 835 u64 valid_bits;
2acf923e
DC		 836
837 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
838 if (index != XCR_XFEATURE_ENABLED_MASK)
839 return 1;
d91cab78 840 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 841 return 1;
d91cab78 842 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 843 return 1;
46c34cb0
PB		 844
845 /*
846 * Do not allow the guest to set bits that we do not support
847 * saving. However, xcr0 bit 0 is always set, even if the
848 * emulated CPU does not support XSAVE (see fx_init).
849 */
d91cab78 850 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 851 if (xcr0 & ~valid_bits)
2acf923e 852 return 1;
46c34cb0 853
d91cab78
DH		 854 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
855 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 856 return 1;
857
d91cab78
DH		 858 if (xcr0 & XFEATURE_MASK_AVX512) {
859 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 860 return 1;
d91cab78 861 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 862 return 1;
863 }
2acf923e 864 vcpu->arch.xcr0 = xcr0;
56c103ec 865
d91cab78 866 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 867 kvm_update_cpuid(vcpu);
2acf923e
DC		 868 return 0;
869}
870
871int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
872{
764bcbc5
Z		 873 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
874 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 875 kvm_inject_gp(vcpu, 0);
876 return 1;
877 }
878 return 0;
879}
880EXPORT_SYMBOL_GPL(kvm_set_xcr);
881
a83b29c6 882int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 883{
fc78f519 884 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 885 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 886 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 887
0f12244f
GN		 888 if (cr4 & CR4_RESERVED_BITS)
889 return 1;
a03490ed 890
d6321d49 891 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 892 return 1;
893
d6321d49 894 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 895 return 1;
896
d6321d49 897 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 898 return 1;
899
d6321d49 900 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 901 return 1;
902
d6321d49 903 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 904 return 1;
905
fd8cb433 906 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 907 return 1;
908
ae3e61e1
PB		 909 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
910 return 1;
911
a03490ed 912 if (is_long_mode(vcpu)) {
0f12244f
GN		 913 if (!(cr4 & X86_CR4_PAE))
914 return 1;
a2edf57f
AK		 915 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
916 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 917 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
918 kvm_read_cr3(vcpu)))
0f12244f
GN		 919 return 1;
920
ad756a16 921 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 922 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 923 return 1;
924
925 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
926 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
927 return 1;
928 }
929
5e1746d6 930 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 931 return 1;
a03490ed 932
ad756a16
MJ		 933 if (((cr4 ^ old_cr4) & pdptr_bits) ||
934 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 935 kvm_mmu_reset_context(vcpu);
0f12244f 936
b9baba86 937 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 938 kvm_update_cpuid(vcpu);
2acf923e 939
0f12244f
GN		 940 return 0;
941}
2d3ad1f4 942EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 943
2390218b 944int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 945{
ade61e28 946 bool skip_tlb_flush = false;
ac146235 947#ifdef CONFIG_X86_64
c19986fe
JS		 948 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
949
ade61e28 950 if (pcid_enabled) {
208320ba
JS		 951 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
952 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 953 }
ac146235 954#endif
9d88fca7 955
9f8fe504 956 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 957 if (!skip_tlb_flush) {
958 kvm_mmu_sync_roots(vcpu);
ade61e28 959 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 960 }
0f12244f 961 return 0;
d835dfec
AK		 962 }
963
d1cd3ce9 964 if (is_long_mode(vcpu) &&
a780a3ea 965 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 966 return 1;
bf03d4f9
PB		 967 else if (is_pae_paging(vcpu) &&
968 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 969 return 1;
a03490ed 970
ade61e28 971 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 972 vcpu->arch.cr3 = cr3;
aff48baa 973 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 974
0f12244f
GN		 975 return 0;
976}
2d3ad1f4 977EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 978
eea1cff9 979int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 980{
0f12244f
GN		 981 if (cr8 & CR8_RESERVED_BITS)
982 return 1;
35754c98 983 if (lapic_in_kernel(vcpu))
a03490ed
CO		 984 kvm_lapic_set_tpr(vcpu, cr8);
985 else
ad312c7c 986 vcpu->arch.cr8 = cr8;
0f12244f
GN		 987 return 0;
988}
2d3ad1f4 989EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 990
2d3ad1f4 991unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 992{
35754c98 993 if (lapic_in_kernel(vcpu))
a03490ed
CO		 994 return kvm_lapic_get_cr8(vcpu);
995 else
ad312c7c 996 return vcpu->arch.cr8;
a03490ed 997}
2d3ad1f4 998EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 999
ae561ede
NA		 1000static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1001{
1002 int i;
1003
1004 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1005 for (i = 0; i < KVM_NR_DB_REGS; i++)
1006 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1007 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1008 }
1009}
1010
73aaf249
JK		 1011static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1012{
1013 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1014 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1015}
1016
c8639010
JK		 1017static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1018{
1019 unsigned long dr7;
1020
1021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1022 dr7 = vcpu->arch.guest_debug_dr7;
1023 else
1024 dr7 = vcpu->arch.dr7;
1025 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1026 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1027 if (dr7 & DR7_BP_EN_MASK)
1028 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1029}
1030
6f43ed01
NA		 1031static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1032{
1033 u64 fixed = DR6_FIXED_1;
1034
d6321d49 1035 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1036 fixed |= DR6_RTM;
1037 return fixed;
1038}
1039
338dbc97 1040static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1041{
1042 switch (dr) {
1043 case 0 ... 3:
1044 vcpu->arch.db[dr] = val;
1045 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1046 vcpu->arch.eff_db[dr] = val;
1047 break;
1048 case 4:
020df079
GN		 1049 /* fall through */
1050 case 6:
338dbc97
GN		 1051 if (val & 0xffffffff00000000ULL)
1052 return -1; /* #GP */
6f43ed01 1053 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1054 kvm_update_dr6(vcpu);
020df079
GN		 1055 break;
1056 case 5:
020df079
GN		 1057 /* fall through */
1058 default: /* 7 */
338dbc97
GN		 1059 if (val & 0xffffffff00000000ULL)
1060 return -1; /* #GP */
020df079 1061 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1062 kvm_update_dr7(vcpu);
020df079
GN		 1063 break;
1064 }
1065
1066 return 0;
1067}
338dbc97
GN		 1068
1069int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1070{
16f8a6f9 1071 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1072 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1073 return 1;
1074 }
1075 return 0;
338dbc97 1076}
020df079
GN		 1077EXPORT_SYMBOL_GPL(kvm_set_dr);
1078
16f8a6f9 1079int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1080{
1081 switch (dr) {
1082 case 0 ... 3:
1083 *val = vcpu->arch.db[dr];
1084 break;
1085 case 4:
020df079
GN		 1086 /* fall through */
1087 case 6:
73aaf249
JK		 1088 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089 *val = vcpu->arch.dr6;
1090 else
1091 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1092 break;
1093 case 5:
020df079
GN		 1094 /* fall through */
1095 default: /* 7 */
1096 *val = vcpu->arch.dr7;
1097 break;
1098 }
338dbc97
GN		 1099 return 0;
1100}
020df079
GN		 1101EXPORT_SYMBOL_GPL(kvm_get_dr);
1102
022cd0e8
AK		 1103bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1104{
de3cd117 1105 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1106 u64 data;
1107 int err;
1108
c6702c9d 1109 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1110 if (err)
1111 return err;
de3cd117
SC		 1112 kvm_rax_write(vcpu, (u32)data);
1113 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1114 return err;
1115}
1116EXPORT_SYMBOL_GPL(kvm_rdpmc);
1117
043405e1
CO		 1118/*
1119 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1120 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1121 *
1122 * This list is modified at module load time to reflect the
e3267cbb 1123 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1124 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1125 * may depend on host virtualization features rather than host cpu features.
043405e1 1126 */
e3267cbb 1127
043405e1
CO		 1128static u32 msrs_to_save[] = {
1129 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1130 MSR_STAR,
043405e1
CO		 1131#ifdef CONFIG_X86_64
1132 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1133#endif
b3897a49 1134 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1135 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1136 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1137 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1138 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1139 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1140 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1141 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1142 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
043405e1
CO		 1143};
1144
1145static unsigned num_msrs_to_save;
1146
62ef68bb
PB		 1147static u32 emulated_msrs[] = {
1148 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1149 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1150 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1151 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1152 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1153 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1154 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1155 HV_X64_MSR_RESET,
11c4b1ca 1156 HV_X64_MSR_VP_INDEX,
9eec50b8 1157 HV_X64_MSR_VP_RUNTIME,
5c919412 1158 HV_X64_MSR_SCONTROL,
1f4b34f8 1159 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1160 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1161 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1162 HV_X64_MSR_TSC_EMULATION_STATUS,
1163
1164 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1165 MSR_KVM_PV_EOI_EN,
1166
ba904635 1167 MSR_IA32_TSC_ADJUST,
a3e06bbe 1168 MSR_IA32_TSCDEADLINE,
2bdb76c0 1169 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1170 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1171 MSR_IA32_MCG_STATUS,
1172 MSR_IA32_MCG_CTL,
c45dcc71 1173 MSR_IA32_MCG_EXT_CTL,
64d60670 1174 MSR_IA32_SMBASE,
52797bf9 1175 MSR_SMI_COUNT,
db2336a8
KH		 1176 MSR_PLATFORM_INFO,
1177 MSR_MISC_FEATURES_ENABLES,
bc226f07 1178 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1179 MSR_IA32_POWER_CTL,
191c8137 1180
95c5c7c7
PB		 1181 /*
1182 * The following list leaves out MSRs whose values are determined
1183 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1184 * We always support the "true" VMX control MSRs, even if the host
1185 * processor does not, so I am putting these registers here rather
1186 * than in msrs_to_save.
1187 */
1188 MSR_IA32_VMX_BASIC,
1189 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1190 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1191 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1192 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1193 MSR_IA32_VMX_MISC,
1194 MSR_IA32_VMX_CR0_FIXED0,
1195 MSR_IA32_VMX_CR4_FIXED0,
1196 MSR_IA32_VMX_VMCS_ENUM,
1197 MSR_IA32_VMX_PROCBASED_CTLS2,
1198 MSR_IA32_VMX_EPT_VPID_CAP,
1199 MSR_IA32_VMX_VMFUNC,
1200
191c8137 1201 MSR_K7_HWCR,
2d5ba19b 1202 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1203};
1204
62ef68bb
PB		 1205static unsigned num_emulated_msrs;
1206
801e459a
TL		 1207/*
1208 * List of msr numbers which are used to expose MSR-based features that
1209 * can be used by a hypervisor to validate requested CPU features.
1210 */
1211static u32 msr_based_features[] = {
1389309c
PB		 1212 MSR_IA32_VMX_BASIC,
1213 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1214 MSR_IA32_VMX_PINBASED_CTLS,
1215 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1216 MSR_IA32_VMX_PROCBASED_CTLS,
1217 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1218 MSR_IA32_VMX_EXIT_CTLS,
1219 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1220 MSR_IA32_VMX_ENTRY_CTLS,
1221 MSR_IA32_VMX_MISC,
1222 MSR_IA32_VMX_CR0_FIXED0,
1223 MSR_IA32_VMX_CR0_FIXED1,
1224 MSR_IA32_VMX_CR4_FIXED0,
1225 MSR_IA32_VMX_CR4_FIXED1,
1226 MSR_IA32_VMX_VMCS_ENUM,
1227 MSR_IA32_VMX_PROCBASED_CTLS2,
1228 MSR_IA32_VMX_EPT_VPID_CAP,
1229 MSR_IA32_VMX_VMFUNC,
1230
d1d93fa9 1231 MSR_F10H_DECFG,
518e7b94 1232 MSR_IA32_UCODE_REV,
cd283252 1233 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1234};
1235
1236static unsigned int num_msr_based_features;
1237
4d22c17c 1238static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1239{
4d22c17c 1240 u64 data = 0;
5b76a3cf 1241
4d22c17c
XL		 1242 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1243 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf
PB		 1244
1245 /*
1246 * If we're doing cache flushes (either "always" or "cond")
1247 * we will do one whenever the guest does a vmlaunch/vmresume.
1248 * If an outer hypervisor is doing the cache flush for us
1249 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1250 * capability to the guest too, and if EPT is disabled we're not
1251 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1252 * require a nested hypervisor to do a flush of its own.
1253 */
1254 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1255 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1256
0c54914d
PB		 1257 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1258 data |= ARCH_CAP_RDCL_NO;
1259 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1260 data |= ARCH_CAP_SSB_NO;
1261 if (!boot_cpu_has_bug(X86_BUG_MDS))
1262 data |= ARCH_CAP_MDS_NO;
1263
5b76a3cf
PB		 1264 return data;
1265}
5b76a3cf 1266
66421c1e
WL		 1267static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1268{
1269 switch (msr->index) {
cd283252 1270 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1271 msr->data = kvm_get_arch_capabilities();
1272 break;
1273 case MSR_IA32_UCODE_REV:
cd283252 1274 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1275 break;
66421c1e
WL		 1276 default:
1277 if (kvm_x86_ops->get_msr_feature(msr))
1278 return 1;
1279 }
1280 return 0;
1281}
1282
801e459a
TL		 1283static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1284{
1285 struct kvm_msr_entry msr;
66421c1e 1286 int r;
801e459a
TL		 1287
1288 msr.index = index;
66421c1e
WL		 1289 r = kvm_get_msr_feature(&msr);
1290 if (r)
1291 return r;
801e459a
TL		 1292
1293 *data = msr.data;
1294
1295 return 0;
1296}
1297
11988499 1298static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1299{
1b4d56b8 1300 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1301 return false;
1b2fd70c 1302
1b4d56b8 1303 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1304 return false;
d8017474 1305
0a629563
SC		 1306 if (efer & (EFER_LME | EFER_LMA) &&
1307 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1308 return false;
1309
1310 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1311 return false;
d8017474 1312
384bb783 1313 return true;
11988499
SC		 1314
1315}
1316bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1317{
1318 if (efer & efer_reserved_bits)
1319 return false;
1320
1321 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1322}
1323EXPORT_SYMBOL_GPL(kvm_valid_efer);
1324
11988499 1325static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1326{
1327 u64 old_efer = vcpu->arch.efer;
11988499 1328 u64 efer = msr_info->data;
384bb783 1329
11988499 1330 if (efer & efer_reserved_bits)
66f61c92 1331 return 1;
384bb783 1332
11988499
SC		 1333 if (!msr_info->host_initiated) {
1334 if (!__kvm_valid_efer(vcpu, efer))
1335 return 1;
1336
1337 if (is_paging(vcpu) &&
1338 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1339 return 1;
1340 }
384bb783 1341
15c4a640 1342 efer &= ~EFER_LMA;
f6801dff 1343 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1344
a3d204e2
SY		 1345 kvm_x86_ops->set_efer(vcpu, efer);
1346
aad82703
SY		 1347 /* Update reserved bits */
1348 if ((efer ^ old_efer) & EFER_NX)
1349 kvm_mmu_reset_context(vcpu);
1350
b69e8cae 1351 return 0;
15c4a640
CO		 1352}
1353
f2b4b7dd
JR		 1354void kvm_enable_efer_bits(u64 mask)
1355{
1356 efer_reserved_bits &= ~mask;
1357}
1358EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1359
15c4a640
CO		 1360/*
1361 * Writes msr value into into the appropriate "register".
1362 * Returns 0 on success, non-0 otherwise.
1363 * Assumes vcpu_load() was already called.
1364 */
8fe8ab46 1365int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1366{
854e8bb1
NA		 1367 switch (msr->index) {
1368 case MSR_FS_BASE:
1369 case MSR_GS_BASE:
1370 case MSR_KERNEL_GS_BASE:
1371 case MSR_CSTAR:
1372 case MSR_LSTAR:
fd8cb433 1373 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1374 return 1;
1375 break;
1376 case MSR_IA32_SYSENTER_EIP:
1377 case MSR_IA32_SYSENTER_ESP:
1378 /*
1379 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1380 * non-canonical address is written on Intel but not on
1381 * AMD (which ignores the top 32-bits, because it does
1382 * not implement 64-bit SYSENTER).
1383 *
1384 * 64-bit code should hence be able to write a non-canonical
1385 * value on AMD. Making the address canonical ensures that
1386 * vmentry does not fail on Intel after writing a non-canonical
1387 * value, and that something deterministic happens if the guest
1388 * invokes 64-bit SYSENTER.
1389 */
fd8cb433 1390 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1391 }
8fe8ab46 1392 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1393}
854e8bb1 1394EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1395
313a3dc7
CO		 1396/*
1397 * Adapt set_msr() to msr_io()'s calling convention
1398 */
609e36d3
PB		 1399static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1400{
1401 struct msr_data msr;
1402 int r;
1403
1404 msr.index = index;
1405 msr.host_initiated = true;
1406 r = kvm_get_msr(vcpu, &msr);
1407 if (r)
1408 return r;
1409
1410 *data = msr.data;
1411 return 0;
1412}
1413
313a3dc7
CO		 1414static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1415{
8fe8ab46
WA		 1416 struct msr_data msr;
1417
1418 msr.data = *data;
1419 msr.index = index;
1420 msr.host_initiated = true;
1421 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1422}
1423
16e8d74d
MT		 1424#ifdef CONFIG_X86_64
1425struct pvclock_gtod_data {
1426 seqcount_t seq;
1427
1428 struct { /* extract of a clocksource struct */
1429 int vclock_mode;
a5a1d1c2
TG		 1430 u64 cycle_last;
1431 u64 mask;
16e8d74d
MT		 1432 u32 mult;
1433 u32 shift;
1434 } clock;
1435
cbcf2dd3
TG		 1436 u64 boot_ns;
1437 u64 nsec_base;
55dd00a7 1438 u64 wall_time_sec;
16e8d74d
MT		 1439};
1440
1441static struct pvclock_gtod_data pvclock_gtod_data;
1442
1443static void update_pvclock_gtod(struct timekeeper *tk)
1444{
1445 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1446 u64 boot_ns;
1447
876e7881 1448 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1449
1450 write_seqcount_begin(&vdata->seq);
1451
1452 /* copy pvclock gtod data */
876e7881
PZ		 1453 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1454 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1455 vdata->clock.mask = tk->tkr_mono.mask;
1456 vdata->clock.mult = tk->tkr_mono.mult;
1457 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1458
cbcf2dd3 1459 vdata->boot_ns = boot_ns;
876e7881 1460 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1461
55dd00a7
MT		 1462 vdata->wall_time_sec = tk->xtime_sec;
1463
16e8d74d
MT		 1464 write_seqcount_end(&vdata->seq);
1465}
1466#endif
1467
bab5bb39
NK		 1468void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1469{
bab5bb39 1470 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1471 kvm_vcpu_kick(vcpu);
bab5bb39 1472}
16e8d74d 1473
18068523
GOC		 1474static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1475{
9ed3c444
AK		 1476 int version;
1477 int r;
50d0a0f9 1478 struct pvclock_wall_clock wc;
87aeb54f 1479 struct timespec64 boot;
18068523
GOC		 1480
1481 if (!wall_clock)
1482 return;
1483
9ed3c444
AK		 1484 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1485 if (r)
1486 return;
1487
1488 if (version & 1)
1489 ++version; /* first time write, random junk */
1490
1491 ++version;
18068523 1492
1dab1345
NK		 1493 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1494 return;
18068523 1495
50d0a0f9
GH		 1496 /*
1497 * The guest calculates current wall clock time by adding
34c238a1 1498 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1499 * wall clock specified here. guest system time equals host
1500 * system time for us, thus we must fill in host boot time here.
1501 */
87aeb54f 1502 getboottime64(&boot);
50d0a0f9 1503
4b648665 1504 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1505 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1506 boot = timespec64_sub(boot, ts);
4b648665 1507 }
87aeb54f 1508 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1509 wc.nsec = boot.tv_nsec;
1510 wc.version = version;
18068523
GOC		 1511
1512 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1513
1514 version++;
1515 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1516}
1517
50d0a0f9
GH		 1518static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1519{
b51012de
PB		 1520 do_shl32_div32(dividend, divisor);
1521 return dividend;
50d0a0f9
GH		 1522}
1523
3ae13faa 1524static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1525 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1526{
5f4e3f88 1527 uint64_t scaled64;
50d0a0f9
GH		 1528 int32_t shift = 0;
1529 uint64_t tps64;
1530 uint32_t tps32;
1531
3ae13faa
PB		 1532 tps64 = base_hz;
1533 scaled64 = scaled_hz;
50933623 1534 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1535 tps64 >>= 1;
1536 shift--;
1537 }
1538
1539 tps32 = (uint32_t)tps64;
50933623
JK		 1540 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1541 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1542 scaled64 >>= 1;
1543 else
1544 tps32 <<= 1;
50d0a0f9
GH		 1545 shift++;
1546 }
1547
5f4e3f88
ZA		 1548 *pshift = shift;
1549 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1550}
1551
d828199e 1552#ifdef CONFIG_X86_64
16e8d74d 1553static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1554#endif
16e8d74d 1555
c8076604 1556static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1557static unsigned long max_tsc_khz;
c8076604 1558
cc578287 1559static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1560{
cc578287
ZA		 1561 u64 v = (u64)khz * (1000000 + ppm);
1562 do_div(v, 1000000);
1563 return v;
1e993611
JR		 1564}
1565
381d585c
HZ		 1566static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1567{
1568 u64 ratio;
1569
1570 /* Guest TSC same frequency as host TSC? */
1571 if (!scale) {
1572 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1573 return 0;
1574 }
1575
1576 /* TSC scaling supported? */
1577 if (!kvm_has_tsc_control) {
1578 if (user_tsc_khz > tsc_khz) {
1579 vcpu->arch.tsc_catchup = 1;
1580 vcpu->arch.tsc_always_catchup = 1;
1581 return 0;
1582 } else {
3f16a5c3 1583 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1584 return -1;
1585 }
1586 }
1587
1588 /* TSC scaling required - calculate ratio */
1589 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1590 user_tsc_khz, tsc_khz);
1591
1592 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1593 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1594 user_tsc_khz);
381d585c
HZ		 1595 return -1;
1596 }
1597
1598 vcpu->arch.tsc_scaling_ratio = ratio;
1599 return 0;
1600}
1601
4941b8cb 1602static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1603{
cc578287
ZA		 1604 u32 thresh_lo, thresh_hi;
1605 int use_scaling = 0;
217fc9cf 1606
03ba32ca 1607 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1608 if (user_tsc_khz == 0) {
ad721883
HZ		 1609 /* set tsc_scaling_ratio to a safe value */
1610 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1611 return -1;
ad721883 1612 }
03ba32ca 1613
c285545f 1614 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1615 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1616 &vcpu->arch.virtual_tsc_shift,
1617 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1618 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1619
1620 /*
1621 * Compute the variation in TSC rate which is acceptable
1622 * within the range of tolerance and decide if the
1623 * rate being applied is within that bounds of the hardware
1624 * rate. If so, no scaling or compensation need be done.
1625 */
1626 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1627 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1628 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1629 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1630 use_scaling = 1;
1631 }
4941b8cb 1632 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1633}
1634
1635static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1636{
e26101b1 1637 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1638 vcpu->arch.virtual_tsc_mult,
1639 vcpu->arch.virtual_tsc_shift);
e26101b1 1640 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1641 return tsc;
1642}
1643
b0c39dc6
VK		 1644static inline int gtod_is_based_on_tsc(int mode)
1645{
1646 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1647}
1648
69b0049a 1649static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1650{
1651#ifdef CONFIG_X86_64
1652 bool vcpus_matched;
b48aa97e
MT		 1653 struct kvm_arch *ka = &vcpu->kvm->arch;
1654 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1655
1656 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1657 atomic_read(&vcpu->kvm->online_vcpus));
1658
7f187922
MT		 1659 /*
1660 * Once the masterclock is enabled, always perform request in
1661 * order to update it.
1662 *
1663 * In order to enable masterclock, the host clocksource must be TSC
1664 * and the vcpus need to have matched TSCs. When that happens,
1665 * perform request to enable masterclock.
1666 */
1667 if (ka->use_master_clock ||
b0c39dc6 1668 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1669 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1670
1671 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1672 atomic_read(&vcpu->kvm->online_vcpus),
1673 ka->use_master_clock, gtod->clock.vclock_mode);
1674#endif
1675}
1676
ba904635
WA		 1677static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1678{
e79f245d 1679 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1680 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1681}
1682
35181e86
HZ		 1683/*
1684 * Multiply tsc by a fixed point number represented by ratio.
1685 *
1686 * The most significant 64-N bits (mult) of ratio represent the
1687 * integral part of the fixed point number; the remaining N bits
1688 * (frac) represent the fractional part, ie. ratio represents a fixed
1689 * point number (mult + frac * 2^(-N)).
1690 *
1691 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1692 */
1693static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1694{
1695 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1696}
1697
1698u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1699{
1700 u64 _tsc = tsc;
1701 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1702
1703 if (ratio != kvm_default_tsc_scaling_ratio)
1704 _tsc = __scale_tsc(ratio, tsc);
1705
1706 return _tsc;
1707}
1708EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1709
07c1419a
HZ		 1710static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1711{
1712 u64 tsc;
1713
1714 tsc = kvm_scale_tsc(vcpu, rdtsc());
1715
1716 return target_tsc - tsc;
1717}
1718
4ba76538
HZ		 1719u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1720{
e79f245d
KA		 1721 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1722
1723 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1724}
1725EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1726
a545ab6a
LC		 1727static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1728{
326e7425 1729 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1730}
1731
b0c39dc6
VK		 1732static inline bool kvm_check_tsc_unstable(void)
1733{
1734#ifdef CONFIG_X86_64
1735 /*
1736 * TSC is marked unstable when we're running on Hyper-V,
1737 * 'TSC page' clocksource is good.
1738 */
1739 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1740 return false;
1741#endif
1742 return check_tsc_unstable();
1743}
1744
8fe8ab46 1745void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1746{
1747 struct kvm *kvm = vcpu->kvm;
f38e098f 1748 u64 offset, ns, elapsed;
99e3e30a 1749 unsigned long flags;
b48aa97e 1750 bool matched;
0d3da0d2 1751 bool already_matched;
8fe8ab46 1752 u64 data = msr->data;
c5e8ec8e 1753 bool synchronizing = false;
99e3e30a 1754
038f8c11 1755 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1756 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1757 ns = ktime_get_boottime_ns();
f38e098f 1758 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1759
03ba32ca 1760 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1761 if (data == 0 && msr->host_initiated) {
1762 /*
1763 * detection of vcpu initialization -- need to sync
1764 * with other vCPUs. This particularly helps to keep
1765 * kvm_clock stable after CPU hotplug
1766 */
1767 synchronizing = true;
1768 } else {
1769 u64 tsc_exp = kvm->arch.last_tsc_write +
1770 nsec_to_cycles(vcpu, elapsed);
1771 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1772 /*
1773 * Special case: TSC write with a small delta (1 second)
1774 * of virtual cycle time against real time is
1775 * interpreted as an attempt to synchronize the CPU.
1776 */
1777 synchronizing = data < tsc_exp + tsc_hz &&
1778 data + tsc_hz > tsc_exp;
1779 }
c5e8ec8e 1780 }
f38e098f
ZA		 1781
1782 /*
5d3cb0f6
ZA		 1783 * For a reliable TSC, we can match TSC offsets, and for an unstable
1784 * TSC, we add elapsed time in this computation. We could let the
1785 * compensation code attempt to catch up if we fall behind, but
1786 * it's better to try to match offsets from the beginning.
1787 */
c5e8ec8e 1788 if (synchronizing &&
5d3cb0f6 1789 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1790 if (!kvm_check_tsc_unstable()) {
e26101b1 1791 offset = kvm->arch.cur_tsc_offset;
f38e098f 1792 } else {
857e4099 1793 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1794 data += delta;
07c1419a 1795 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1796 }
b48aa97e 1797 matched = true;
0d3da0d2 1798 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1799 } else {
1800 /*
1801 * We split periods of matched TSC writes into generations.
1802 * For each generation, we track the original measured
1803 * nanosecond time, offset, and write, so if TSCs are in
1804 * sync, we can match exact offset, and if not, we can match
4a969980 1805 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1806 *
1807 * These values are tracked in kvm->arch.cur_xxx variables.
1808 */
1809 kvm->arch.cur_tsc_generation++;
1810 kvm->arch.cur_tsc_nsec = ns;
1811 kvm->arch.cur_tsc_write = data;
1812 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1813 matched = false;
f38e098f 1814 }
e26101b1
ZA		 1815
1816 /*
1817 * We also track th most recent recorded KHZ, write and time to
1818 * allow the matching interval to be extended at each write.
1819 */
f38e098f
ZA		 1820 kvm->arch.last_tsc_nsec = ns;
1821 kvm->arch.last_tsc_write = data;
5d3cb0f6 1822 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1823
b183aa58 1824 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1825
1826 /* Keep track of which generation this VCPU has synchronized to */
1827 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1828 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1829 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1830
d6321d49 1831 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1832 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1833
a545ab6a 1834 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1835 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1836
1837 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1838 if (!matched) {
b48aa97e 1839 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1840 } else if (!already_matched) {
1841 kvm->arch.nr_vcpus_matched_tsc++;
1842 }
b48aa97e
MT		 1843
1844 kvm_track_tsc_matching(vcpu);
1845 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1846}
e26101b1 1847
99e3e30a
ZA		 1848EXPORT_SYMBOL_GPL(kvm_write_tsc);
1849
58ea6767
HZ		 1850static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1851 s64 adjustment)
1852{
326e7425
LS		 1853 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1854 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1855}
1856
1857static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1858{
1859 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1860 WARN_ON(adjustment < 0);
1861 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1862 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1863}
1864
d828199e
MT		 1865#ifdef CONFIG_X86_64
1866
a5a1d1c2 1867static u64 read_tsc(void)
d828199e 1868{
a5a1d1c2 1869 u64 ret = (u64)rdtsc_ordered();
03b9730b 1870 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1871
1872 if (likely(ret >= last))
1873 return ret;
1874
1875 /*
1876 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1877 * predictable (it's just a function of time and the likely is
d828199e
MT		 1878 * very likely) and there's a data dependence, so force GCC
1879 * to generate a branch instead. I don't barrier() because
1880 * we don't actually need a barrier, and if this function
1881 * ever gets inlined it will generate worse code.
1882 */
1883 asm volatile ("");
1884 return last;
1885}
1886
b0c39dc6 1887static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1888{
1889 long v;
1890 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1891 u64 tsc_pg_val;
1892
1893 switch (gtod->clock.vclock_mode) {
1894 case VCLOCK_HVCLOCK:
1895 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1896 tsc_timestamp);
1897 if (tsc_pg_val != U64_MAX) {
1898 /* TSC page valid */
1899 *mode = VCLOCK_HVCLOCK;
1900 v = (tsc_pg_val - gtod->clock.cycle_last) &
1901 gtod->clock.mask;
1902 } else {
1903 /* TSC page invalid */
1904 *mode = VCLOCK_NONE;
1905 }
1906 break;
1907 case VCLOCK_TSC:
1908 *mode = VCLOCK_TSC;
1909 *tsc_timestamp = read_tsc();
1910 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1911 gtod->clock.mask;
1912 break;
1913 default:
1914 *mode = VCLOCK_NONE;
1915 }
d828199e 1916
b0c39dc6
VK		 1917 if (*mode == VCLOCK_NONE)
1918 *tsc_timestamp = v = 0;
d828199e 1919
d828199e
MT		 1920 return v * gtod->clock.mult;
1921}
1922
b0c39dc6 1923static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1924{
cbcf2dd3 1925 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1926 unsigned long seq;
d828199e 1927 int mode;
cbcf2dd3 1928 u64 ns;
d828199e 1929
d828199e
MT		 1930 do {
1931 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1932 ns = gtod->nsec_base;
b0c39dc6 1933 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1934 ns >>= gtod->clock.shift;
cbcf2dd3 1935 ns += gtod->boot_ns;
d828199e 1936 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1937 *t = ns;
d828199e
MT		 1938
1939 return mode;
1940}
1941
899a31f5 1942static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1943{
1944 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1945 unsigned long seq;
1946 int mode;
1947 u64 ns;
1948
1949 do {
1950 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1951 ts->tv_sec = gtod->wall_time_sec;
1952 ns = gtod->nsec_base;
b0c39dc6 1953 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1954 ns >>= gtod->clock.shift;
1955 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1956
1957 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1958 ts->tv_nsec = ns;
1959
1960 return mode;
1961}
1962
b0c39dc6
VK		 1963/* returns true if host is using TSC based clocksource */
1964static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1965{
d828199e 1966 /* checked again under seqlock below */
b0c39dc6 1967 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1968 return false;
1969
b0c39dc6
VK		 1970 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1971 tsc_timestamp));
d828199e 1972}
55dd00a7 1973
b0c39dc6 1974/* returns true if host is using TSC based clocksource */
899a31f5 1975static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1976 u64 *tsc_timestamp)
55dd00a7
MT		 1977{
1978 /* checked again under seqlock below */
b0c39dc6 1979 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1980 return false;
1981
b0c39dc6 1982 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1983}
d828199e
MT		 1984#endif
1985
1986/*
1987 *
b48aa97e
MT		 1988 * Assuming a stable TSC across physical CPUS, and a stable TSC
1989 * across virtual CPUs, the following condition is possible.
1990 * Each numbered line represents an event visible to both
d828199e
MT		 1991 * CPUs at the next numbered event.
1992 *
1993 * "timespecX" represents host monotonic time. "tscX" represents
1994 * RDTSC value.
1995 *
1996 * VCPU0 on CPU0 | VCPU1 on CPU1
1997 *
1998 * 1. read timespec0,tsc0
1999 * 2. | timespec1 = timespec0 + N
2000 * | tsc1 = tsc0 + M
2001 * 3. transition to guest | transition to guest
2002 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2003 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2004 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2005 *
2006 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2007 *
2008 * - ret0 < ret1
2009 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2010 * ...
2011 * - 0 < N - M => M < N
2012 *
2013 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2014 * always the case (the difference between two distinct xtime instances
2015 * might be smaller then the difference between corresponding TSC reads,
2016 * when updating guest vcpus pvclock areas).
2017 *
2018 * To avoid that problem, do not allow visibility of distinct
2019 * system_timestamp/tsc_timestamp values simultaneously: use a master
2020 * copy of host monotonic time values. Update that master copy
2021 * in lockstep.
2022 *
b48aa97e 2023 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2024 *
2025 */
2026
2027static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2028{
2029#ifdef CONFIG_X86_64
2030 struct kvm_arch *ka = &kvm->arch;
2031 int vclock_mode;
b48aa97e
MT		 2032 bool host_tsc_clocksource, vcpus_matched;
2033
2034 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2035 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2036
2037 /*
2038 * If the host uses TSC clock, then passthrough TSC as stable
2039 * to the guest.
2040 */
b48aa97e 2041 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2042 &ka->master_kernel_ns,
2043 &ka->master_cycle_now);
2044
16a96021 2045 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2046 && !ka->backwards_tsc_observed
54750f2c 2047 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2048
d828199e
MT		 2049 if (ka->use_master_clock)
2050 atomic_set(&kvm_guest_has_master_clock, 1);
2051
2052 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2053 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2054 vcpus_matched);
d828199e
MT		 2055#endif
2056}
2057
2860c4b1
PB		 2058void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2059{
2060 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2061}
2062
2e762ff7
MT		 2063static void kvm_gen_update_masterclock(struct kvm *kvm)
2064{
2065#ifdef CONFIG_X86_64
2066 int i;
2067 struct kvm_vcpu *vcpu;
2068 struct kvm_arch *ka = &kvm->arch;
2069
2070 spin_lock(&ka->pvclock_gtod_sync_lock);
2071 kvm_make_mclock_inprogress_request(kvm);
2072 /* no guest entries from this point */
2073 pvclock_update_vm_gtod_copy(kvm);
2074
2075 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2077
2078 /* guest entries allowed */
2079 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2080 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2081
2082 spin_unlock(&ka->pvclock_gtod_sync_lock);
2083#endif
2084}
2085
e891a32e 2086u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2087{
108b249c 2088 struct kvm_arch *ka = &kvm->arch;
8b953440 2089 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2090 u64 ret;
108b249c 2091
8b953440
PB		 2092 spin_lock(&ka->pvclock_gtod_sync_lock);
2093 if (!ka->use_master_clock) {
2094 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2095 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2096 }
2097
8b953440
PB		 2098 hv_clock.tsc_timestamp = ka->master_cycle_now;
2099 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2100 spin_unlock(&ka->pvclock_gtod_sync_lock);
2101
e2c2206a
WL		 2102 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2103 get_cpu();
2104
e70b57a6
WL		 2105 if (__this_cpu_read(cpu_tsc_khz)) {
2106 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2107 &hv_clock.tsc_shift,
2108 &hv_clock.tsc_to_system_mul);
2109 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2110 } else
9285ec4c 2111 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2112
2113 put_cpu();
2114
2115 return ret;
108b249c
PB		 2116}
2117
0d6dd2ff
PB		 2118static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2119{
2120 struct kvm_vcpu_arch *vcpu = &v->arch;
2121 struct pvclock_vcpu_time_info guest_hv_clock;
2122
4e335d9e 2123 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2124 &guest_hv_clock, sizeof(guest_hv_clock))))
2125 return;
2126
2127 /* This VCPU is paused, but it's legal for a guest to read another
2128 * VCPU's kvmclock, so we really have to follow the specification where
2129 * it says that version is odd if data is being modified, and even after
2130 * it is consistent.
2131 *
2132 * Version field updates must be kept separate. This is because
2133 * kvm_write_guest_cached might use a "rep movs" instruction, and
2134 * writes within a string instruction are weakly ordered. So there
2135 * are three writes overall.
2136 *
2137 * As a small optimization, only write the version field in the first
2138 * and third write. The vcpu->pv_time cache is still valid, because the
2139 * version field is the first in the struct.
2140 */
2141 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2142
51c4b8bb
LA		 2143 if (guest_hv_clock.version & 1)
2144 ++guest_hv_clock.version; /* first time write, random junk */
2145
0d6dd2ff 2146 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2147 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2148 &vcpu->hv_clock,
2149 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2150
2151 smp_wmb();
2152
2153 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2154 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2155
2156 if (vcpu->pvclock_set_guest_stopped_request) {
2157 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2158 vcpu->pvclock_set_guest_stopped_request = false;
2159 }
2160
2161 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2162
4e335d9e
PB		 2163 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2164 &vcpu->hv_clock,
2165 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2166
2167 smp_wmb();
2168
2169 vcpu->hv_clock.version++;
4e335d9e
PB		 2170 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2171 &vcpu->hv_clock,
2172 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2173}
2174
34c238a1 2175static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2176{
78db6a50 2177 unsigned long flags, tgt_tsc_khz;
18068523 2178 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2179 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2180 s64 kernel_ns;
d828199e 2181 u64 tsc_timestamp, host_tsc;
51d59c6b 2182 u8 pvclock_flags;
d828199e
MT		 2183 bool use_master_clock;
2184
2185 kernel_ns = 0;
2186 host_tsc = 0;
18068523 2187
d828199e
MT		 2188 /*
2189 * If the host uses TSC clock, then passthrough TSC as stable
2190 * to the guest.
2191 */
2192 spin_lock(&ka->pvclock_gtod_sync_lock);
2193 use_master_clock = ka->use_master_clock;
2194 if (use_master_clock) {
2195 host_tsc = ka->master_cycle_now;
2196 kernel_ns = ka->master_kernel_ns;
2197 }
2198 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2199
2200 /* Keep irq disabled to prevent changes to the clock */
2201 local_irq_save(flags);
78db6a50
PB		 2202 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2203 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2204 local_irq_restore(flags);
2205 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2206 return 1;
2207 }
d828199e 2208 if (!use_master_clock) {
4ea1636b 2209 host_tsc = rdtsc();
9285ec4c 2210 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2211 }
2212
4ba76538 2213 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2214
c285545f
ZA		 2215 /*
2216 * We may have to catch up the TSC to match elapsed wall clock
2217 * time for two reasons, even if kvmclock is used.
2218 * 1) CPU could have been running below the maximum TSC rate
2219 * 2) Broken TSC compensation resets the base at each VCPU
2220 * entry to avoid unknown leaps of TSC even when running
2221 * again on the same CPU. This may cause apparent elapsed
2222 * time to disappear, and the guest to stand still or run
2223 * very slowly.
2224 */
2225 if (vcpu->tsc_catchup) {
2226 u64 tsc = compute_guest_tsc(v, kernel_ns);
2227 if (tsc > tsc_timestamp) {
f1e2b260 2228 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2229 tsc_timestamp = tsc;
2230 }
50d0a0f9
GH		 2231 }
2232
18068523
GOC		 2233 local_irq_restore(flags);
2234
0d6dd2ff 2235 /* With all the info we got, fill in the values */
18068523 2236
78db6a50
PB		 2237 if (kvm_has_tsc_control)
2238 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2239
2240 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2241 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2242 &vcpu->hv_clock.tsc_shift,
2243 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2244 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2245 }
2246
1d5f066e 2247 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2248 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2249 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2250
d828199e 2251 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2252 pvclock_flags = 0;
d828199e
MT		 2253 if (use_master_clock)
2254 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2255
78c0337a
MT		 2256 vcpu->hv_clock.flags = pvclock_flags;
2257
095cf55d
PB		 2258 if (vcpu->pv_time_enabled)
2259 kvm_setup_pvclock_page(v);
2260 if (v == kvm_get_vcpu(v->kvm, 0))
2261 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2262 return 0;
c8076604
GH		 2263}
2264
0061d53d
MT		 2265/*
2266 * kvmclock updates which are isolated to a given vcpu, such as
2267 * vcpu->cpu migration, should not allow system_timestamp from
2268 * the rest of the vcpus to remain static. Otherwise ntp frequency
2269 * correction applies to one vcpu's system_timestamp but not
2270 * the others.
2271 *
2272 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2273 * We need to rate-limit these requests though, as they can
2274 * considerably slow guests that have a large number of vcpus.
2275 * The time for a remote vcpu to update its kvmclock is bound
2276 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2277 */
2278
7e44e449
AJ		 2279#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2280
2281static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2282{
2283 int i;
7e44e449
AJ		 2284 struct delayed_work *dwork = to_delayed_work(work);
2285 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2286 kvmclock_update_work);
2287 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2288 struct kvm_vcpu *vcpu;
2289
2290 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2291 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2292 kvm_vcpu_kick(vcpu);
2293 }
2294}
2295
7e44e449
AJ		 2296static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2297{
2298 struct kvm *kvm = v->kvm;
2299
105b21bb 2300 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2301 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2302 KVMCLOCK_UPDATE_DELAY);
2303}
2304
332967a3
AJ		 2305#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2306
2307static void kvmclock_sync_fn(struct work_struct *work)
2308{
2309 struct delayed_work *dwork = to_delayed_work(work);
2310 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2311 kvmclock_sync_work);
2312 struct kvm *kvm = container_of(ka, struct kvm, arch);
2313
630994b3
MT		 2314 if (!kvmclock_periodic_sync)
2315 return;
2316
332967a3
AJ		 2317 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2318 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2319 KVMCLOCK_SYNC_PERIOD);
2320}
2321
191c8137
BP		 2322/*
2323 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2324 */
2325static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2326{
2327 /* McStatusWrEn enabled? */
2328 if (guest_cpuid_is_amd(vcpu))
2329 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2330
2331 return false;
2332}
2333
9ffd986c 2334static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2335{
890ca9ae
HY		 2336 u64 mcg_cap = vcpu->arch.mcg_cap;
2337 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2338 u32 msr = msr_info->index;
2339 u64 data = msr_info->data;
890ca9ae 2340
15c4a640 2341 switch (msr) {
15c4a640 2342 case MSR_IA32_MCG_STATUS:
890ca9ae 2343 vcpu->arch.mcg_status = data;
15c4a640 2344 break;
c7ac679c 2345 case MSR_IA32_MCG_CTL:
44883f01
PB		 2346 if (!(mcg_cap & MCG_CTL_P) &&
2347 (data || !msr_info->host_initiated))
890ca9ae
HY		 2348 return 1;
2349 if (data != 0 && data != ~(u64)0)
44883f01 2350 return 1;
890ca9ae
HY		 2351 vcpu->arch.mcg_ctl = data;
2352 break;
2353 default:
2354 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2355 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2356 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2357 /* only 0 or all 1s can be written to IA32_MCi_CTL
2358 * some Linux kernels though clear bit 10 in bank 4 to
2359 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2360 * this to avoid an uncatched #GP in the guest
2361 */
890ca9ae 2362 if ((offset & 0x3) == 0 &&
114be429 2363 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2364 return -1;
191c8137
BP		 2365
2366 /* MCi_STATUS */
9ffd986c 2367 if (!msr_info->host_initiated &&
191c8137
BP		 2368 (offset & 0x3) == 1 && data != 0) {
2369 if (!can_set_mci_status(vcpu))
2370 return -1;
2371 }
2372
890ca9ae
HY		 2373 vcpu->arch.mce_banks[offset] = data;
2374 break;
2375 }
2376 return 1;
2377 }
2378 return 0;
2379}
2380
ffde22ac
ES		 2381static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2382{
2383 struct kvm *kvm = vcpu->kvm;
2384 int lm = is_long_mode(vcpu);
2385 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2386 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2387 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2388 : kvm->arch.xen_hvm_config.blob_size_32;
2389 u32 page_num = data & ~PAGE_MASK;
2390 u64 page_addr = data & PAGE_MASK;
2391 u8 *page;
2392 int r;
2393
2394 r = -E2BIG;
2395 if (page_num >= blob_size)
2396 goto out;
2397 r = -ENOMEM;
ff5c2c03
SL		 2398 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2399 if (IS_ERR(page)) {
2400 r = PTR_ERR(page);
ffde22ac 2401 goto out;
ff5c2c03 2402 }
54bf36aa 2403 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2404 goto out_free;
2405 r = 0;
2406out_free:
2407 kfree(page);
2408out:
2409 return r;
2410}
2411
344d9588
GN		 2412static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2413{
2414 gpa_t gpa = data & ~0x3f;
2415
52a5c155
WL		 2416 /* Bits 3:5 are reserved, Should be zero */
2417 if (data & 0x38)
344d9588
GN		 2418 return 1;
2419
2420 vcpu->arch.apf.msr_val = data;
2421
2422 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2423 kvm_clear_async_pf_completion_queue(vcpu);
2424 kvm_async_pf_hash_reset(vcpu);
2425 return 0;
2426 }
2427
4e335d9e 2428 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2429 sizeof(u32)))
344d9588
GN		 2430 return 1;
2431
6adba527 2432 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2433 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2434 kvm_async_pf_wakeup_all(vcpu);
2435 return 0;
2436}
2437
12f9a48f
GC		 2438static void kvmclock_reset(struct kvm_vcpu *vcpu)
2439{
0b79459b 2440 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2441}
2442
f38a7b75
WL		 2443static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2444{
2445 ++vcpu->stat.tlb_flush;
2446 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2447}
2448
c9aaa895
GC		 2449static void record_steal_time(struct kvm_vcpu *vcpu)
2450{
2451 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2452 return;
2453
4e335d9e 2454 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2455 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2456 return;
2457
f38a7b75
WL		 2458 /*
2459 * Doing a TLB flush here, on the guest's behalf, can avoid
2460 * expensive IPIs.
2461 */
2462 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2463 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2464
35f3fae1
WL		 2465 if (vcpu->arch.st.steal.version & 1)
2466 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2467
2468 vcpu->arch.st.steal.version += 1;
2469
4e335d9e 2470 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2471 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2472
2473 smp_wmb();
2474
c54cdf14
LC		 2475 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2476 vcpu->arch.st.last_steal;
2477 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2478
4e335d9e 2479 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2480 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2481
2482 smp_wmb();
2483
2484 vcpu->arch.st.steal.version += 1;
c9aaa895 2485
4e335d9e 2486 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2487 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2488}
2489
8fe8ab46 2490int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2491{
5753785f 2492 bool pr = false;
8fe8ab46
WA		 2493 u32 msr = msr_info->index;
2494 u64 data = msr_info->data;
5753785f 2495
15c4a640 2496 switch (msr) {
2e32b719 2497 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2498 case MSR_IA32_UCODE_WRITE:
2499 case MSR_VM_HSAVE_PA:
2500 case MSR_AMD64_PATCH_LOADER:
2501 case MSR_AMD64_BU_CFG2:
405a353a 2502 case MSR_AMD64_DC_CFG:
0e1b869f 2503 case MSR_F15H_EX_CFG:
2e32b719
BP		 2504 break;
2505
518e7b94
WL		 2506 case MSR_IA32_UCODE_REV:
2507 if (msr_info->host_initiated)
2508 vcpu->arch.microcode_version = data;
2509 break;
0cf9135b
SC		 2510 case MSR_IA32_ARCH_CAPABILITIES:
2511 if (!msr_info->host_initiated)
2512 return 1;
2513 vcpu->arch.arch_capabilities = data;
2514 break;
15c4a640 2515 case MSR_EFER:
11988499 2516 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2517 case MSR_K7_HWCR:
2518 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2519 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2520 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2521
2522 /* Handle McStatusWrEn */
2523 if (data == BIT_ULL(18)) {
2524 vcpu->arch.msr_hwcr = data;
2525 } else if (data != 0) {
a737f256
CD		 2526 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2527 data);
8f1589d9
AP		 2528 return 1;
2529 }
15c4a640 2530 break;
f7c6d140
AP		 2531 case MSR_FAM10H_MMIO_CONF_BASE:
2532 if (data != 0) {
a737f256
CD		 2533 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2534 "0x%llx\n", data);
f7c6d140
AP		 2535 return 1;
2536 }
15c4a640 2537 break;
b5e2fec0
AG		 2538 case MSR_IA32_DEBUGCTLMSR:
2539 if (!data) {
2540 /* We support the non-activated case already */
2541 break;
2542 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2543 /* Values other than LBR and BTF are vendor-specific,
2544 thus reserved and should throw a #GP */
2545 return 1;
2546 }
a737f256
CD		 2547 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2548 __func__, data);
b5e2fec0 2549 break;
9ba075a6 2550 case 0x200 ... 0x2ff:
ff53604b 2551 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2552 case MSR_IA32_APICBASE:
58cb628d 2553 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2554 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2555 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2556 case MSR_IA32_TSCDEADLINE:
2557 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2558 break;
ba904635 2559 case MSR_IA32_TSC_ADJUST:
d6321d49 2560 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2561 if (!msr_info->host_initiated) {
d913b904 2562 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2563 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2564 }
2565 vcpu->arch.ia32_tsc_adjust_msr = data;
2566 }
2567 break;
15c4a640 2568 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2569 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2570 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2571 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2572 return 1;
2573 vcpu->arch.ia32_misc_enable_msr = data;
2574 kvm_update_cpuid(vcpu);
2575 } else {
2576 vcpu->arch.ia32_misc_enable_msr = data;
2577 }
15c4a640 2578 break;
64d60670
PB		 2579 case MSR_IA32_SMBASE:
2580 if (!msr_info->host_initiated)
2581 return 1;
2582 vcpu->arch.smbase = data;
2583 break;
73f624f4
PB		 2584 case MSR_IA32_POWER_CTL:
2585 vcpu->arch.msr_ia32_power_ctl = data;
2586 break;
dd259935
PB		 2587 case MSR_IA32_TSC:
2588 kvm_write_tsc(vcpu, msr_info);
2589 break;
52797bf9
LA		 2590 case MSR_SMI_COUNT:
2591 if (!msr_info->host_initiated)
2592 return 1;
2593 vcpu->arch.smi_count = data;
2594 break;
11c6bffa 2595 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2596 case MSR_KVM_WALL_CLOCK:
2597 vcpu->kvm->arch.wall_clock = data;
2598 kvm_write_wall_clock(vcpu->kvm, data);
2599 break;
11c6bffa 2600 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2601 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2602 struct kvm_arch *ka = &vcpu->kvm->arch;
2603
12f9a48f 2604 kvmclock_reset(vcpu);
18068523 2605
54750f2c
MT		 2606 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2607 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2608
2609 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2610 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2611
2612 ka->boot_vcpu_runs_old_kvmclock = tmp;
2613 }
2614
18068523 2615 vcpu->arch.time = data;
0061d53d 2616 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2617
2618 /* we verify if the enable bit is set... */
2619 if (!(data & 1))
2620 break;
2621
4e335d9e 2622 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2623 &vcpu->arch.pv_time, data & ~1ULL,
2624 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2625 vcpu->arch.pv_time_enabled = false;
2626 else
2627 vcpu->arch.pv_time_enabled = true;
32cad84f 2628
18068523
GOC		 2629 break;
2630 }
344d9588
GN		 2631 case MSR_KVM_ASYNC_PF_EN:
2632 if (kvm_pv_enable_async_pf(vcpu, data))
2633 return 1;
2634 break;
c9aaa895
GC		 2635 case MSR_KVM_STEAL_TIME:
2636
2637 if (unlikely(!sched_info_on()))
2638 return 1;
2639
2640 if (data & KVM_STEAL_RESERVED_MASK)
2641 return 1;
2642
4e335d9e 2643 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2644 data & KVM_STEAL_VALID_BITS,
2645 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2646 return 1;
2647
2648 vcpu->arch.st.msr_val = data;
2649
2650 if (!(data & KVM_MSR_ENABLED))
2651 break;
2652
c9aaa895
GC		 2653 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2654
2655 break;
ae7a2a3f 2656 case MSR_KVM_PV_EOI_EN:
72bbf935 2657 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2658 return 1;
2659 break;
c9aaa895 2660
2d5ba19b
MT		 2661 case MSR_KVM_POLL_CONTROL:
2662 /* only enable bit supported */
2663 if (data & (-1ULL << 1))
2664 return 1;
2665
2666 vcpu->arch.msr_kvm_poll_control = data;
2667 break;
2668
890ca9ae
HY		 2669 case MSR_IA32_MCG_CTL:
2670 case MSR_IA32_MCG_STATUS:
81760dcc 2671 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2672 return set_msr_mce(vcpu, msr_info);
71db6023 2673
6912ac32
WH		 2674 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2675 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2676 pr = true; /* fall through */
2677 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2678 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2679 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2680 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2681
2682 if (pr || data != 0)
a737f256
CD		 2683 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2684 "0x%x data 0x%llx\n", msr, data);
5753785f 2685 break;
84e0cefa
JS		 2686 case MSR_K7_CLK_CTL:
2687 /*
2688 * Ignore all writes to this no longer documented MSR.
2689 * Writes are only relevant for old K7 processors,
2690 * all pre-dating SVM, but a recommended workaround from
4a969980 2691 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2692 * affected processor models on the command line, hence
2693 * the need to ignore the workaround.
2694 */
2695 break;
55cd8e5a 2696 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2697 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2698 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2699 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2700 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2701 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2702 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2703 return kvm_hv_set_msr_common(vcpu, msr, data,
2704 msr_info->host_initiated);
91c9c3ed 2705 case MSR_IA32_BBL_CR_CTL3:
2706 /* Drop writes to this legacy MSR -- see rdmsr
2707 * counterpart for further detail.
2708 */
fab0aa3b
EM		 2709 if (report_ignored_msrs)
2710 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2711 msr, data);
91c9c3ed 2712 break;
2b036c6b 2713 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2714 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2715 return 1;
2716 vcpu->arch.osvw.length = data;
2717 break;
2718 case MSR_AMD64_OSVW_STATUS:
d6321d49 2719 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2720 return 1;
2721 vcpu->arch.osvw.status = data;
2722 break;
db2336a8
KH		 2723 case MSR_PLATFORM_INFO:
2724 if (!msr_info->host_initiated ||
db2336a8
KH		 2725 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2726 cpuid_fault_enabled(vcpu)))
2727 return 1;
2728 vcpu->arch.msr_platform_info = data;
2729 break;
2730 case MSR_MISC_FEATURES_ENABLES:
2731 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2732 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2733 !supports_cpuid_fault(vcpu)))
2734 return 1;
2735 vcpu->arch.msr_misc_features_enables = data;
2736 break;
15c4a640 2737 default:
ffde22ac
ES		 2738 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2739 return xen_hvm_config(vcpu, data);
c6702c9d 2740 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2741 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2742 if (!ignore_msrs) {
ae0f5499 2743 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2744 msr, data);
ed85c068
AP		 2745 return 1;
2746 } else {
fab0aa3b
EM		 2747 if (report_ignored_msrs)
2748 vcpu_unimpl(vcpu,
2749 "ignored wrmsr: 0x%x data 0x%llx\n",
2750 msr, data);
ed85c068
AP		 2751 break;
2752 }
15c4a640
CO		 2753 }
2754 return 0;
2755}
2756EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2757
2758
2759/*
2760 * Reads an msr value (of 'msr_index') into 'pdata'.
2761 * Returns 0 on success, non-0 otherwise.
2762 * Assumes vcpu_load() was already called.
2763 */
609e36d3 2764int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2765{
609e36d3 2766 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2767}
ff651cb6 2768EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2769
44883f01 2770static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2771{
2772 u64 data;
890ca9ae
HY		 2773 u64 mcg_cap = vcpu->arch.mcg_cap;
2774 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2775
2776 switch (msr) {
15c4a640
CO		 2777 case MSR_IA32_P5_MC_ADDR:
2778 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2779 data = 0;
2780 break;
15c4a640 2781 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2782 data = vcpu->arch.mcg_cap;
2783 break;
c7ac679c 2784 case MSR_IA32_MCG_CTL:
44883f01 2785 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2786 return 1;
2787 data = vcpu->arch.mcg_ctl;
2788 break;
2789 case MSR_IA32_MCG_STATUS:
2790 data = vcpu->arch.mcg_status;
2791 break;
2792 default:
2793 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2794 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2795 u32 offset = msr - MSR_IA32_MC0_CTL;
2796 data = vcpu->arch.mce_banks[offset];
2797 break;
2798 }
2799 return 1;
2800 }
2801 *pdata = data;
2802 return 0;
2803}
2804
609e36d3 2805int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2806{
609e36d3 2807 switch (msr_info->index) {
890ca9ae 2808 case MSR_IA32_PLATFORM_ID:
15c4a640 2809 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2810 case MSR_IA32_DEBUGCTLMSR:
2811 case MSR_IA32_LASTBRANCHFROMIP:
2812 case MSR_IA32_LASTBRANCHTOIP:
2813 case MSR_IA32_LASTINTFROMIP:
2814 case MSR_IA32_LASTINTTOIP:
60af2ecd 2815 case MSR_K8_SYSCFG:
3afb1121
PB		 2816 case MSR_K8_TSEG_ADDR:
2817 case MSR_K8_TSEG_MASK:
61a6bd67 2818 case MSR_VM_HSAVE_PA:
1fdbd48c 2819 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2820 case MSR_AMD64_NB_CFG:
f7c6d140 2821 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2822 case MSR_AMD64_BU_CFG2:
0c2df2a1 2823 case MSR_IA32_PERF_CTL:
405a353a 2824 case MSR_AMD64_DC_CFG:
0e1b869f 2825 case MSR_F15H_EX_CFG:
609e36d3 2826 msr_info->data = 0;
15c4a640 2827 break;
c51eb52b 2828 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2829 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2830 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2831 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2832 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2833 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2834 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2835 msr_info->data = 0;
5753785f 2836 break;
742bc670 2837 case MSR_IA32_UCODE_REV:
518e7b94 2838 msr_info->data = vcpu->arch.microcode_version;
742bc670 2839 break;
0cf9135b
SC		 2840 case MSR_IA32_ARCH_CAPABILITIES:
2841 if (!msr_info->host_initiated &&
2842 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2843 return 1;
2844 msr_info->data = vcpu->arch.arch_capabilities;
2845 break;
73f624f4
PB		 2846 case MSR_IA32_POWER_CTL:
2847 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2848 break;
dd259935
PB		 2849 case MSR_IA32_TSC:
2850 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2851 break;
9ba075a6 2852 case MSR_MTRRcap:
9ba075a6 2853 case 0x200 ... 0x2ff:
ff53604b 2854 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2855 case 0xcd: /* fsb frequency */
609e36d3 2856 msr_info->data = 3;
15c4a640 2857 break;
7b914098
JS		 2858 /*
2859 * MSR_EBC_FREQUENCY_ID
2860 * Conservative value valid for even the basic CPU models.
2861 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2862 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2863 * and 266MHz for model 3, or 4. Set Core Clock
2864 * Frequency to System Bus Frequency Ratio to 1 (bits
2865 * 31:24) even though these are only valid for CPU
2866 * models > 2, however guests may end up dividing or
2867 * multiplying by zero otherwise.
2868 */
2869 case MSR_EBC_FREQUENCY_ID:
609e36d3 2870 msr_info->data = 1 << 24;
7b914098 2871 break;
15c4a640 2872 case MSR_IA32_APICBASE:
609e36d3 2873 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2874 break;
0105d1a5 2875 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2876 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2877 break;
a3e06bbe 2878 case MSR_IA32_TSCDEADLINE:
609e36d3 2879 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2880 break;
ba904635 2881 case MSR_IA32_TSC_ADJUST:
609e36d3 2882 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2883 break;
15c4a640 2884 case MSR_IA32_MISC_ENABLE:
609e36d3 2885 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2886 break;
64d60670
PB		 2887 case MSR_IA32_SMBASE:
2888 if (!msr_info->host_initiated)
2889 return 1;
2890 msr_info->data = vcpu->arch.smbase;
15c4a640 2891 break;
52797bf9
LA		 2892 case MSR_SMI_COUNT:
2893 msr_info->data = vcpu->arch.smi_count;
2894 break;
847f0ad8
AG		 2895 case MSR_IA32_PERF_STATUS:
2896 /* TSC increment by tick */
609e36d3 2897 msr_info->data = 1000ULL;
847f0ad8 2898 /* CPU multiplier */
b0996ae4 2899 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2900 break;
15c4a640 2901 case MSR_EFER:
609e36d3 2902 msr_info->data = vcpu->arch.efer;
15c4a640 2903 break;
18068523 2904 case MSR_KVM_WALL_CLOCK:
11c6bffa 2905 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2906 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2907 break;
2908 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2909 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2910 msr_info->data = vcpu->arch.time;
18068523 2911 break;
344d9588 2912 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2913 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2914 break;
c9aaa895 2915 case MSR_KVM_STEAL_TIME:
609e36d3 2916 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2917 break;
1d92128f 2918 case MSR_KVM_PV_EOI_EN:
609e36d3 2919 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2920 break;
2d5ba19b
MT		 2921 case MSR_KVM_POLL_CONTROL:
2922 msr_info->data = vcpu->arch.msr_kvm_poll_control;
2923 break;
890ca9ae
HY		 2924 case MSR_IA32_P5_MC_ADDR:
2925 case MSR_IA32_P5_MC_TYPE:
2926 case MSR_IA32_MCG_CAP:
2927 case MSR_IA32_MCG_CTL:
2928 case MSR_IA32_MCG_STATUS:
81760dcc 2929 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2930 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2931 msr_info->host_initiated);
84e0cefa
JS		 2932 case MSR_K7_CLK_CTL:
2933 /*
2934 * Provide expected ramp-up count for K7. All other
2935 * are set to zero, indicating minimum divisors for
2936 * every field.
2937 *
2938 * This prevents guest kernels on AMD host with CPU
2939 * type 6, model 8 and higher from exploding due to
2940 * the rdmsr failing.
2941 */
609e36d3 2942 msr_info->data = 0x20000000;
84e0cefa 2943 break;
55cd8e5a 2944 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2945 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2946 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2947 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2948 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2949 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2950 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2951 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2952 msr_info->index, &msr_info->data,
2953 msr_info->host_initiated);
55cd8e5a 2954 break;
91c9c3ed 2955 case MSR_IA32_BBL_CR_CTL3:
2956 /* This legacy MSR exists but isn't fully documented in current
2957 * silicon. It is however accessed by winxp in very narrow
2958 * scenarios where it sets bit #19, itself documented as
2959 * a "reserved" bit. Best effort attempt to source coherent
2960 * read data here should the balance of the register be
2961 * interpreted by the guest:
2962 *
2963 * L2 cache control register 3: 64GB range, 256KB size,
2964 * enabled, latency 0x1, configured
2965 */
609e36d3 2966 msr_info->data = 0xbe702111;
91c9c3ed 2967 break;
2b036c6b 2968 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2969 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2970 return 1;
609e36d3 2971 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2972 break;
2973 case MSR_AMD64_OSVW_STATUS:
d6321d49 2974 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2975 return 1;
609e36d3 2976 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2977 break;
db2336a8 2978 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2979 if (!msr_info->host_initiated &&
2980 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2981 return 1;
db2336a8
KH		 2982 msr_info->data = vcpu->arch.msr_platform_info;
2983 break;
2984 case MSR_MISC_FEATURES_ENABLES:
2985 msr_info->data = vcpu->arch.msr_misc_features_enables;
2986 break;
191c8137
BP		 2987 case MSR_K7_HWCR:
2988 msr_info->data = vcpu->arch.msr_hwcr;
2989 break;
15c4a640 2990 default:
c6702c9d 2991 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2992 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2993 if (!ignore_msrs) {
ae0f5499
BD		 2994 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2995 msr_info->index);
ed85c068
AP		 2996 return 1;
2997 } else {
fab0aa3b
EM		 2998 if (report_ignored_msrs)
2999 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3000 msr_info->index);
609e36d3 3001 msr_info->data = 0;
ed85c068
AP		 3002 }
3003 break;
15c4a640 3004 }
15c4a640
CO		 3005 return 0;
3006}
3007EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3008
313a3dc7
CO		 3009/*
3010 * Read or write a bunch of msrs. All parameters are kernel addresses.
3011 *
3012 * @return number of msrs set successfully.
3013 */
3014static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3015 struct kvm_msr_entry *entries,
3016 int (*do_msr)(struct kvm_vcpu *vcpu,
3017 unsigned index, u64 *data))
3018{
801e459a 3019 int i;
313a3dc7 3020
313a3dc7
CO		 3021 for (i = 0; i < msrs->nmsrs; ++i)
3022 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3023 break;
3024
313a3dc7
CO		 3025 return i;
3026}
3027
3028/*
3029 * Read or write a bunch of msrs. Parameters are user addresses.
3030 *
3031 * @return number of msrs set successfully.
3032 */
3033static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3034 int (*do_msr)(struct kvm_vcpu *vcpu,
3035 unsigned index, u64 *data),
3036 int writeback)
3037{
3038 struct kvm_msrs msrs;
3039 struct kvm_msr_entry *entries;
3040 int r, n;
3041 unsigned size;
3042
3043 r = -EFAULT;
0e96f31e 3044 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3045 goto out;
3046
3047 r = -E2BIG;
3048 if (msrs.nmsrs >= MAX_IO_MSRS)
3049 goto out;
3050
313a3dc7 3051 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3052 entries = memdup_user(user_msrs->entries, size);
3053 if (IS_ERR(entries)) {
3054 r = PTR_ERR(entries);
313a3dc7 3055 goto out;
ff5c2c03 3056 }
313a3dc7
CO		 3057
3058 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3059 if (r < 0)
3060 goto out_free;
3061
3062 r = -EFAULT;
3063 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3064 goto out_free;
3065
3066 r = n;
3067
3068out_free:
7a73c028 3069 kfree(entries);
313a3dc7
CO		 3070out:
3071 return r;
3072}
3073
4d5422ce
WL		 3074static inline bool kvm_can_mwait_in_guest(void)
3075{
3076 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3077 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3078 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3079}
3080
784aa3d7 3081int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3082{
4d5422ce 3083 int r = 0;
018d00d2
ZX		 3084
3085 switch (ext) {
3086 case KVM_CAP_IRQCHIP:
3087 case KVM_CAP_HLT:
3088 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3089 case KVM_CAP_SET_TSS_ADDR:
07716717 3090 case KVM_CAP_EXT_CPUID:
9c15bb1d 3091 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3092 case KVM_CAP_CLOCKSOURCE:
7837699f 3093 case KVM_CAP_PIT:
a28e4f5a 3094 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3095 case KVM_CAP_MP_STATE:
ed848624 3096 case KVM_CAP_SYNC_MMU:
a355c85c 3097 case KVM_CAP_USER_NMI:
52d939a0 3098 case KVM_CAP_REINJECT_CONTROL:
4925663a 3099 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3100 case KVM_CAP_IOEVENTFD:
f848a5a8 3101 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3102 case KVM_CAP_PIT2:
e9f42757 3103 case KVM_CAP_PIT_STATE2:
b927a3ce 3104 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3105 case KVM_CAP_XEN_HVM:
3cfc3092 3106 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3107 case KVM_CAP_HYPERV:
10388a07 3108 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3109 case KVM_CAP_HYPERV_SPIN:
5c919412 3110 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3111 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3112 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3113 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3114 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3115 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3116 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3117 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3118 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3119 case KVM_CAP_DEBUGREGS:
d2be1651 3120 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3121 case KVM_CAP_XSAVE:
344d9588 3122 case KVM_CAP_ASYNC_PF:
92a1f12d 3123 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3124 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3125 case KVM_CAP_READONLY_MEM:
5f66b620 3126 case KVM_CAP_HYPERV_TIME:
100943c5 3127 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3128 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3129 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3130 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3131 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3132 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3133 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3134 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3135 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3136 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3137 r = 1;
3138 break;
01643c51
KH		 3139 case KVM_CAP_SYNC_REGS:
3140 r = KVM_SYNC_X86_VALID_FIELDS;
3141 break;
e3fd9a93
PB		 3142 case KVM_CAP_ADJUST_CLOCK:
3143 r = KVM_CLOCK_TSC_STABLE;
3144 break;
4d5422ce 3145 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3146 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3147 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3148 if(kvm_can_mwait_in_guest())
3149 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3150 break;
6d396b55
PB		 3151 case KVM_CAP_X86_SMM:
3152 /* SMBASE is usually relocated above 1M on modern chipsets,
3153 * and SMM handlers might indeed rely on 4G segment limits,
3154 * so do not report SMM to be available if real mode is
3155 * emulated via vm86 mode. Still, do not go to great lengths
3156 * to avoid userspace's usage of the feature, because it is a
3157 * fringe case that is not enabled except via specific settings
3158 * of the module parameters.
3159 */
bc226f07 3160 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3161 break;
774ead3a
AK		 3162 case KVM_CAP_VAPIC:
3163 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3164 break;
f725230a 3165 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3166 r = KVM_SOFT_MAX_VCPUS;
3167 break;
3168 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3169 r = KVM_MAX_VCPUS;
3170 break;
a86cb413
TH		 3171 case KVM_CAP_MAX_VCPU_ID:
3172 r = KVM_MAX_VCPU_ID;
3173 break;
a68a6a72
MT		 3174 case KVM_CAP_PV_MMU: /* obsolete */
3175 r = 0;
2f333bcb 3176 break;
890ca9ae
HY		 3177 case KVM_CAP_MCE:
3178 r = KVM_MAX_MCE_BANKS;
3179 break;
2d5b5a66 3180 case KVM_CAP_XCRS:
d366bf7e 3181 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3182 break;
92a1f12d
JR		 3183 case KVM_CAP_TSC_CONTROL:
3184 r = kvm_has_tsc_control;
3185 break;
37131313
RK		 3186 case KVM_CAP_X2APIC_API:
3187 r = KVM_X2APIC_API_VALID_FLAGS;
3188 break;
8fcc4b59
JM		 3189 case KVM_CAP_NESTED_STATE:
3190 r = kvm_x86_ops->get_nested_state ?
be43c440 3191 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3192 break;
018d00d2 3193 default:
018d00d2
ZX		 3194 break;
3195 }
3196 return r;
3197
3198}
3199
043405e1
CO		 3200long kvm_arch_dev_ioctl(struct file *filp,
3201 unsigned int ioctl, unsigned long arg)
3202{
3203 void __user *argp = (void __user *)arg;
3204 long r;
3205
3206 switch (ioctl) {
3207 case KVM_GET_MSR_INDEX_LIST: {
3208 struct kvm_msr_list __user *user_msr_list = argp;
3209 struct kvm_msr_list msr_list;
3210 unsigned n;
3211
3212 r = -EFAULT;
0e96f31e 3213 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3214 goto out;
3215 n = msr_list.nmsrs;
62ef68bb 3216 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3217 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3218 goto out;
3219 r = -E2BIG;
e125e7b6 3220 if (n < msr_list.nmsrs)
043405e1
CO		 3221 goto out;
3222 r = -EFAULT;
3223 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3224 num_msrs_to_save * sizeof(u32)))
3225 goto out;
e125e7b6 3226 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3227 &emulated_msrs,
62ef68bb 3228 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3229 goto out;
3230 r = 0;
3231 break;
3232 }
9c15bb1d
BP		 3233 case KVM_GET_SUPPORTED_CPUID:
3234 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3235 struct kvm_cpuid2 __user *cpuid_arg = argp;
3236 struct kvm_cpuid2 cpuid;
3237
3238 r = -EFAULT;
0e96f31e 3239 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3240 goto out;
9c15bb1d
BP		 3241
3242 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3243 ioctl);
674eea0f
AK		 3244 if (r)
3245 goto out;
3246
3247 r = -EFAULT;
0e96f31e 3248 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3249 goto out;
3250 r = 0;
3251 break;
3252 }
890ca9ae 3253 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3254 r = -EFAULT;
c45dcc71
AR		 3255 if (copy_to_user(argp, &kvm_mce_cap_supported,
3256 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3257 goto out;
3258 r = 0;
3259 break;
801e459a
TL		 3260 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3261 struct kvm_msr_list __user *user_msr_list = argp;
3262 struct kvm_msr_list msr_list;
3263 unsigned int n;
3264
3265 r = -EFAULT;
3266 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3267 goto out;
3268 n = msr_list.nmsrs;
3269 msr_list.nmsrs = num_msr_based_features;
3270 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3271 goto out;
3272 r = -E2BIG;
3273 if (n < msr_list.nmsrs)
3274 goto out;
3275 r = -EFAULT;
3276 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3277 num_msr_based_features * sizeof(u32)))
3278 goto out;
3279 r = 0;
3280 break;
3281 }
3282 case KVM_GET_MSRS:
3283 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3284 break;
890ca9ae 3285 }
043405e1
CO		 3286 default:
3287 r = -EINVAL;
3288 }
3289out:
3290 return r;
3291}
3292
f5f48ee1
SY		 3293static void wbinvd_ipi(void *garbage)
3294{
3295 wbinvd();
3296}
3297
3298static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3299{
e0f0bbc5 3300 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3301}
3302
313a3dc7
CO		 3303void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3304{
f5f48ee1
SY		 3305 /* Address WBINVD may be executed by guest */
3306 if (need_emulate_wbinvd(vcpu)) {
3307 if (kvm_x86_ops->has_wbinvd_exit())
3308 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3309 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3310 smp_call_function_single(vcpu->cpu,
3311 wbinvd_ipi, NULL, 1);
3312 }
3313
313a3dc7 3314 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3315
e7517324
WL		 3316 fpregs_assert_state_consistent();
3317 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3318 switch_fpu_return();
3319
0dd6a6ed
ZA		 3320 /* Apply any externally detected TSC adjustments (due to suspend) */
3321 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3322 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3323 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3324 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3325 }
8f6055cb 3326
b0c39dc6 3327 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3328 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3329 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3330 if (tsc_delta < 0)
3331 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3332
b0c39dc6 3333 if (kvm_check_tsc_unstable()) {
07c1419a 3334 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3335 vcpu->arch.last_guest_tsc);
a545ab6a 3336 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3337 vcpu->arch.tsc_catchup = 1;
c285545f 3338 }
a749e247
PB		 3339
3340 if (kvm_lapic_hv_timer_in_use(vcpu))
3341 kvm_lapic_restart_hv_timer(vcpu);
3342
d98d07ca
MT		 3343 /*
3344 * On a host with synchronized TSC, there is no need to update
3345 * kvmclock on vcpu->cpu migration
3346 */
3347 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3348 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3349 if (vcpu->cpu != cpu)
1bd2009e 3350 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3351 vcpu->cpu = cpu;
6b7d7e76 3352 }
c9aaa895 3353
c9aaa895 3354 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3355}
3356
0b9f6c46
PX		 3357static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3358{
3359 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3360 return;
3361
fa55eedd 3362 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3363
4e335d9e 3364 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3365 &vcpu->arch.st.steal.preempted,
3366 offsetof(struct kvm_steal_time, preempted),
3367 sizeof(vcpu->arch.st.steal.preempted));
3368}
3369
313a3dc7
CO		 3370void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3371{
cc0d907c 3372 int idx;
de63ad4c
LM		 3373
3374 if (vcpu->preempted)
3375 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3376
931f261b
AA		 3377 /*
3378 * Disable page faults because we're in atomic context here.
3379 * kvm_write_guest_offset_cached() would call might_fault()
3380 * that relies on pagefault_disable() to tell if there's a
3381 * bug. NOTE: the write to guest memory may not go through if
3382 * during postcopy live migration or if there's heavy guest
3383 * paging.
3384 */
3385 pagefault_disable();
cc0d907c
AA		 3386 /*
3387 * kvm_memslots() will be called by
3388 * kvm_write_guest_offset_cached() so take the srcu lock.
3389 */
3390 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3391 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3392 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3393 pagefault_enable();
02daab21 3394 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3395 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3396 /*
f9dcf08e
RK		 3397 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3398 * on every vmexit, but if not, we might have a stale dr6 from the
3399 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3400 */
f9dcf08e 3401 set_debugreg(0, 6);
313a3dc7
CO		 3402}
3403
313a3dc7
CO		 3404static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3405 struct kvm_lapic_state *s)
3406{
fa59cc00 3407 if (vcpu->arch.apicv_active)
d62caabb
AS		 3408 kvm_x86_ops->sync_pir_to_irr(vcpu);
3409
a92e2543 3410 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3411}
3412
3413static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3414 struct kvm_lapic_state *s)
3415{
a92e2543
RK		 3416 int r;
3417
3418 r = kvm_apic_set_state(vcpu, s);
3419 if (r)
3420 return r;
cb142eb7 3421 update_cr8_intercept(vcpu);
313a3dc7
CO		 3422
3423 return 0;
3424}
3425
127a457a
MG		 3426static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3427{
3428 return (!lapic_in_kernel(vcpu) ||
3429 kvm_apic_accept_pic_intr(vcpu));
3430}
3431
782d422b
MG		 3432/*
3433 * if userspace requested an interrupt window, check that the
3434 * interrupt window is open.
3435 *
3436 * No need to exit to userspace if we already have an interrupt queued.
3437 */
3438static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3439{
3440 return kvm_arch_interrupt_allowed(vcpu) &&
3441 !kvm_cpu_has_interrupt(vcpu) &&
3442 !kvm_event_needs_reinjection(vcpu) &&
3443 kvm_cpu_accept_dm_intr(vcpu);
3444}
3445
f77bc6a4
ZX		 3446static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3447 struct kvm_interrupt *irq)
3448{
02cdb50f 3449 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3450 return -EINVAL;
1c1a9ce9
SR		 3451
3452 if (!irqchip_in_kernel(vcpu->kvm)) {
3453 kvm_queue_interrupt(vcpu, irq->irq, false);
3454 kvm_make_request(KVM_REQ_EVENT, vcpu);
3455 return 0;
3456 }
3457
3458 /*
3459 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3460 * fail for in-kernel 8259.
3461 */
3462 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3463 return -ENXIO;
f77bc6a4 3464
1c1a9ce9
SR		 3465 if (vcpu->arch.pending_external_vector != -1)
3466 return -EEXIST;
f77bc6a4 3467
1c1a9ce9 3468 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3469 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3470 return 0;
3471}
3472
c4abb7c9
JK		 3473static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3474{
c4abb7c9 3475 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3476
3477 return 0;
3478}
3479
f077825a
PB		 3480static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3481{
64d60670
PB		 3482 kvm_make_request(KVM_REQ_SMI, vcpu);
3483
f077825a
PB		 3484 return 0;
3485}
3486
b209749f
AK		 3487static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3488 struct kvm_tpr_access_ctl *tac)
3489{
3490 if (tac->flags)
3491 return -EINVAL;
3492 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3493 return 0;
3494}
3495
890ca9ae
HY		 3496static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3497 u64 mcg_cap)
3498{
3499 int r;
3500 unsigned bank_num = mcg_cap & 0xff, bank;
3501
3502 r = -EINVAL;
a9e38c3e 3503 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3504 goto out;
c45dcc71 3505 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3506 goto out;
3507 r = 0;
3508 vcpu->arch.mcg_cap = mcg_cap;
3509 /* Init IA32_MCG_CTL to all 1s */
3510 if (mcg_cap & MCG_CTL_P)
3511 vcpu->arch.mcg_ctl = ~(u64)0;
3512 /* Init IA32_MCi_CTL to all 1s */
3513 for (bank = 0; bank < bank_num; bank++)
3514 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3515
3516 if (kvm_x86_ops->setup_mce)
3517 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3518out:
3519 return r;
3520}
3521
3522static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3523 struct kvm_x86_mce *mce)
3524{
3525 u64 mcg_cap = vcpu->arch.mcg_cap;
3526 unsigned bank_num = mcg_cap & 0xff;
3527 u64 *banks = vcpu->arch.mce_banks;
3528
3529 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3530 return -EINVAL;
3531 /*
3532 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3533 * reporting is disabled
3534 */
3535 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3536 vcpu->arch.mcg_ctl != ~(u64)0)
3537 return 0;
3538 banks += 4 * mce->bank;
3539 /*
3540 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3541 * reporting is disabled for the bank
3542 */
3543 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3544 return 0;
3545 if (mce->status & MCI_STATUS_UC) {
3546 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3547 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3548 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3549 return 0;
3550 }
3551 if (banks[1] & MCI_STATUS_VAL)
3552 mce->status |= MCI_STATUS_OVER;
3553 banks[2] = mce->addr;
3554 banks[3] = mce->misc;
3555 vcpu->arch.mcg_status = mce->mcg_status;
3556 banks[1] = mce->status;
3557 kvm_queue_exception(vcpu, MC_VECTOR);
3558 } else if (!(banks[1] & MCI_STATUS_VAL)
3559 || !(banks[1] & MCI_STATUS_UC)) {
3560 if (banks[1] & MCI_STATUS_VAL)
3561 mce->status |= MCI_STATUS_OVER;
3562 banks[2] = mce->addr;
3563 banks[3] = mce->misc;
3564 banks[1] = mce->status;
3565 } else
3566 banks[1] |= MCI_STATUS_OVER;
3567 return 0;
3568}
3569
3cfc3092
JK		 3570static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3571 struct kvm_vcpu_events *events)
3572{
7460fb4a 3573 process_nmi(vcpu);
59073aaf 3574
664f8e26 3575 /*
59073aaf
JM		 3576 * The API doesn't provide the instruction length for software
3577 * exceptions, so don't report them. As long as the guest RIP
3578 * isn't advanced, we should expect to encounter the exception
3579 * again.
664f8e26 3580 */
59073aaf
JM		 3581 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3582 events->exception.injected = 0;
3583 events->exception.pending = 0;
3584 } else {
3585 events->exception.injected = vcpu->arch.exception.injected;
3586 events->exception.pending = vcpu->arch.exception.pending;
3587 /*
3588 * For ABI compatibility, deliberately conflate
3589 * pending and injected exceptions when
3590 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3591 */
3592 if (!vcpu->kvm->arch.exception_payload_enabled)
3593 events->exception.injected |=
3594 vcpu->arch.exception.pending;
3595 }
3cfc3092
JK		 3596 events->exception.nr = vcpu->arch.exception.nr;
3597 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3598 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3599 events->exception_has_payload = vcpu->arch.exception.has_payload;
3600 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3601
03b82a30 3602 events->interrupt.injected =
04140b41 3603 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3604 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3605 events->interrupt.soft = 0;
37ccdcbe 3606 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3607
3608 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3609 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3610 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3611 events->nmi.pad = 0;
3cfc3092 3612
66450a21 3613 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3614
f077825a
PB		 3615 events->smi.smm = is_smm(vcpu);
3616 events->smi.pending = vcpu->arch.smi_pending;
3617 events->smi.smm_inside_nmi =
3618 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3619 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3620
dab4b911 3621 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3622 | KVM_VCPUEVENT_VALID_SHADOW
3623 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3624 if (vcpu->kvm->arch.exception_payload_enabled)
3625 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3626
97e69aa6 3627 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3628}
3629
c5833c7a 3630static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3631
3cfc3092
JK		 3632static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3633 struct kvm_vcpu_events *events)
3634{
dab4b911 3635 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3636 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3637 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3638 | KVM_VCPUEVENT_VALID_SMM
3639 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3640 return -EINVAL;
3641
59073aaf
JM		 3642 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3643 if (!vcpu->kvm->arch.exception_payload_enabled)
3644 return -EINVAL;
3645 if (events->exception.pending)
3646 events->exception.injected = 0;
3647 else
3648 events->exception_has_payload = 0;
3649 } else {
3650 events->exception.pending = 0;
3651 events->exception_has_payload = 0;
3652 }
3653
3654 if ((events->exception.injected || events->exception.pending) &&
3655 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3656 return -EINVAL;
3657
28bf2888
DH		 3658 /* INITs are latched while in SMM */
3659 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3660 (events->smi.smm || events->smi.pending) &&
3661 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3662 return -EINVAL;
3663
7460fb4a 3664 process_nmi(vcpu);
59073aaf
JM		 3665 vcpu->arch.exception.injected = events->exception.injected;
3666 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3667 vcpu->arch.exception.nr = events->exception.nr;
3668 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3669 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3670 vcpu->arch.exception.has_payload = events->exception_has_payload;
3671 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3672
04140b41 3673 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3674 vcpu->arch.interrupt.nr = events->interrupt.nr;
3675 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3676 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3677 kvm_x86_ops->set_interrupt_shadow(vcpu,
3678 events->interrupt.shadow);
3cfc3092
JK		 3679
3680 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3681 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3682 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3683 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3684
66450a21 3685 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3686 lapic_in_kernel(vcpu))
66450a21 3687 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3688
f077825a 3689 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3690 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3691 if (events->smi.smm)
3692 vcpu->arch.hflags |= HF_SMM_MASK;
3693 else
3694 vcpu->arch.hflags &= ~HF_SMM_MASK;
3695 kvm_smm_changed(vcpu);
3696 }
6ef4e07e 3697
f077825a 3698 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3699
3700 if (events->smi.smm) {
3701 if (events->smi.smm_inside_nmi)
3702 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3703 else
f4ef1910
WL		 3704 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3705 if (lapic_in_kernel(vcpu)) {
3706 if (events->smi.latched_init)
3707 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3708 else
3709 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3710 }
f077825a
PB		 3711 }
3712 }
3713
3842d135
AK		 3714 kvm_make_request(KVM_REQ_EVENT, vcpu);
3715
3cfc3092
JK		 3716 return 0;
3717}
3718
a1efbe77
JK		 3719static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3720 struct kvm_debugregs *dbgregs)
3721{
73aaf249
JK		 3722 unsigned long val;
3723
a1efbe77 3724 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3725 kvm_get_dr(vcpu, 6, &val);
73aaf249 3726 dbgregs->dr6 = val;
a1efbe77
JK		 3727 dbgregs->dr7 = vcpu->arch.dr7;
3728 dbgregs->flags = 0;
97e69aa6 3729 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3730}
3731
3732static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3733 struct kvm_debugregs *dbgregs)
3734{
3735 if (dbgregs->flags)
3736 return -EINVAL;
3737
d14bdb55
PB		 3738 if (dbgregs->dr6 & ~0xffffffffull)
3739 return -EINVAL;
3740 if (dbgregs->dr7 & ~0xffffffffull)
3741 return -EINVAL;
3742
a1efbe77 3743 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3744 kvm_update_dr0123(vcpu);
a1efbe77 3745 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3746 kvm_update_dr6(vcpu);
a1efbe77 3747 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3748 kvm_update_dr7(vcpu);
a1efbe77 3749
a1efbe77
JK		 3750 return 0;
3751}
3752
df1daba7
PB		 3753#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3754
3755static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3756{
b666a4b6 3757 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3758 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3759 u64 valid;
3760
3761 /*
3762 * Copy legacy XSAVE area, to avoid complications with CPUID
3763 * leaves 0 and 1 in the loop below.
3764 */
3765 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3766
3767 /* Set XSTATE_BV */
00c87e9a 3768 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3769 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3770
3771 /*
3772 * Copy each region from the possibly compacted offset to the
3773 * non-compacted offset.
3774 */
d91cab78 3775 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3776 while (valid) {
abd16d68
SAS		 3777 u64 xfeature_mask = valid & -valid;
3778 int xfeature_nr = fls64(xfeature_mask) - 1;
3779 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3780
3781 if (src) {
3782 u32 size, offset, ecx, edx;
abd16d68 3783 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3784 &size, &offset, &ecx, &edx);
abd16d68 3785 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3786 memcpy(dest + offset, &vcpu->arch.pkru,
3787 sizeof(vcpu->arch.pkru));
3788 else
3789 memcpy(dest + offset, src, size);
3790
df1daba7
PB		 3791 }
3792
abd16d68 3793 valid -= xfeature_mask;
df1daba7
PB		 3794 }
3795}
3796
3797static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3798{
b666a4b6 3799 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3800 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3801 u64 valid;
3802
3803 /*
3804 * Copy legacy XSAVE area, to avoid complications with CPUID
3805 * leaves 0 and 1 in the loop below.
3806 */
3807 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3808
3809 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3810 xsave->header.xfeatures = xstate_bv;
782511b0 3811 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3812 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3813
3814 /*
3815 * Copy each region from the non-compacted offset to the
3816 * possibly compacted offset.
3817 */
d91cab78 3818 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3819 while (valid) {
abd16d68
SAS		 3820 u64 xfeature_mask = valid & -valid;
3821 int xfeature_nr = fls64(xfeature_mask) - 1;
3822 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3823
3824 if (dest) {
3825 u32 size, offset, ecx, edx;
abd16d68 3826 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3827 &size, &offset, &ecx, &edx);
abd16d68 3828 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3829 memcpy(&vcpu->arch.pkru, src + offset,
3830 sizeof(vcpu->arch.pkru));
3831 else
3832 memcpy(dest, src + offset, size);
ee4100da 3833 }
df1daba7 3834
abd16d68 3835 valid -= xfeature_mask;
df1daba7
PB		 3836 }
3837}
3838
2d5b5a66
SY		 3839static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3840 struct kvm_xsave *guest_xsave)
3841{
d366bf7e 3842 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3843 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3844 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3845 } else {
2d5b5a66 3846 memcpy(guest_xsave->region,
b666a4b6 3847 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3848 sizeof(struct fxregs_state));
2d5b5a66 3849 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3850 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3851 }
3852}
3853
a575813b
WL		 3854#define XSAVE_MXCSR_OFFSET 24
3855
2d5b5a66
SY		 3856static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3857 struct kvm_xsave *guest_xsave)
3858{
3859 u64 xstate_bv =
3860 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3861 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3862
d366bf7e 3863 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3864 /*
3865 * Here we allow setting states that are not present in
3866 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3867 * with old userspace.
3868 */
a575813b
WL		 3869 if (xstate_bv & ~kvm_supported_xcr0() ||
3870 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3871 return -EINVAL;
df1daba7 3872 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3873 } else {
a575813b
WL		 3874 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3875 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3876 return -EINVAL;
b666a4b6 3877 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3878 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3879 }
3880 return 0;
3881}
3882
3883static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3884 struct kvm_xcrs *guest_xcrs)
3885{
d366bf7e 3886 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3887 guest_xcrs->nr_xcrs = 0;
3888 return;
3889 }
3890
3891 guest_xcrs->nr_xcrs = 1;
3892 guest_xcrs->flags = 0;
3893 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3894 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3895}
3896
3897static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3898 struct kvm_xcrs *guest_xcrs)
3899{
3900 int i, r = 0;
3901
d366bf7e 3902 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3903 return -EINVAL;
3904
3905 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3906 return -EINVAL;
3907
3908 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3909 /* Only support XCR0 currently */
c67a04cb 3910 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3911 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3912 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3913 break;
3914 }
3915 if (r)
3916 r = -EINVAL;
3917 return r;
3918}
3919
1c0b28c2
EM		 3920/*
3921 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3922 * stopped by the hypervisor. This function will be called from the host only.
3923 * EINVAL is returned when the host attempts to set the flag for a guest that
3924 * does not support pv clocks.
3925 */
3926static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3927{
0b79459b 3928 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3929 return -EINVAL;
51d59c6b 3930 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3931 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3932 return 0;
3933}
3934
5c919412
AS		 3935static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3936 struct kvm_enable_cap *cap)
3937{
57b119da
VK		 3938 int r;
3939 uint16_t vmcs_version;
3940 void __user *user_ptr;
3941
5c919412
AS		 3942 if (cap->flags)
3943 return -EINVAL;
3944
3945 switch (cap->cap) {
efc479e6
RK		 3946 case KVM_CAP_HYPERV_SYNIC2:
3947 if (cap->args[0])
3948 return -EINVAL;
b2869f28
GS		 3949 /* fall through */
3950
5c919412 3951 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3952 if (!irqchip_in_kernel(vcpu->kvm))
3953 return -EINVAL;
efc479e6
RK		 3954 return kvm_hv_activate_synic(vcpu, cap->cap ==
3955 KVM_CAP_HYPERV_SYNIC2);
57b119da 3956 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3957 if (!kvm_x86_ops->nested_enable_evmcs)
3958 return -ENOTTY;
57b119da
VK		 3959 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3960 if (!r) {
3961 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3962 if (copy_to_user(user_ptr, &vmcs_version,
3963 sizeof(vmcs_version)))
3964 r = -EFAULT;
3965 }
3966 return r;
3967
5c919412
AS		 3968 default:
3969 return -EINVAL;
3970 }
3971}
3972
313a3dc7
CO		 3973long kvm_arch_vcpu_ioctl(struct file *filp,
3974 unsigned int ioctl, unsigned long arg)
3975{
3976 struct kvm_vcpu *vcpu = filp->private_data;
3977 void __user *argp = (void __user *)arg;
3978 int r;
d1ac91d8
AK		 3979 union {
3980 struct kvm_lapic_state *lapic;
3981 struct kvm_xsave *xsave;
3982 struct kvm_xcrs *xcrs;
3983 void *buffer;
3984 } u;
3985
9b062471
CD		 3986 vcpu_load(vcpu);
3987
d1ac91d8 3988 u.buffer = NULL;
313a3dc7
CO		 3989 switch (ioctl) {
3990 case KVM_GET_LAPIC: {
2204ae3c 3991 r = -EINVAL;
bce87cce 3992 if (!lapic_in_kernel(vcpu))
2204ae3c 3993 goto out;
254272ce
BG		 3994 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3995 GFP_KERNEL_ACCOUNT);
313a3dc7 3996
b772ff36 3997 r = -ENOMEM;
d1ac91d8 3998 if (!u.lapic)
b772ff36 3999 goto out;
d1ac91d8 4000 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 4001 if (r)
4002 goto out;
4003 r = -EFAULT;
d1ac91d8 4004 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 4005 goto out;
4006 r = 0;
4007 break;
4008 }
4009 case KVM_SET_LAPIC: {
2204ae3c 4010 r = -EINVAL;
bce87cce 4011 if (!lapic_in_kernel(vcpu))
2204ae3c 4012 goto out;
ff5c2c03 4013 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 4014 if (IS_ERR(u.lapic)) {
4015 r = PTR_ERR(u.lapic);
4016 goto out_nofree;
4017 }
ff5c2c03 4018
d1ac91d8 4019 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4020 break;
4021 }
f77bc6a4
ZX		 4022 case KVM_INTERRUPT: {
4023 struct kvm_interrupt irq;
4024
4025 r = -EFAULT;
0e96f31e 4026 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4027 goto out;
4028 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4029 break;
4030 }
c4abb7c9
JK		 4031 case KVM_NMI: {
4032 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4033 break;
4034 }
f077825a
PB		 4035 case KVM_SMI: {
4036 r = kvm_vcpu_ioctl_smi(vcpu);
4037 break;
4038 }
313a3dc7
CO		 4039 case KVM_SET_CPUID: {
4040 struct kvm_cpuid __user *cpuid_arg = argp;
4041 struct kvm_cpuid cpuid;
4042
4043 r = -EFAULT;
0e96f31e 4044 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4045 goto out;
4046 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4047 break;
4048 }
07716717
DK		 4049 case KVM_SET_CPUID2: {
4050 struct kvm_cpuid2 __user *cpuid_arg = argp;
4051 struct kvm_cpuid2 cpuid;
4052
4053 r = -EFAULT;
0e96f31e 4054 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4055 goto out;
4056 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4057 cpuid_arg->entries);
07716717
DK		 4058 break;
4059 }
4060 case KVM_GET_CPUID2: {
4061 struct kvm_cpuid2 __user *cpuid_arg = argp;
4062 struct kvm_cpuid2 cpuid;
4063
4064 r = -EFAULT;
0e96f31e 4065 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4066 goto out;
4067 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4068 cpuid_arg->entries);
07716717
DK		 4069 if (r)
4070 goto out;
4071 r = -EFAULT;
0e96f31e 4072 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4073 goto out;
4074 r = 0;
4075 break;
4076 }
801e459a
TL		 4077 case KVM_GET_MSRS: {
4078 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4079 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4080 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4081 break;
801e459a
TL		 4082 }
4083 case KVM_SET_MSRS: {
4084 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4085 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4086 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4087 break;
801e459a 4088 }
b209749f
AK		 4089 case KVM_TPR_ACCESS_REPORTING: {
4090 struct kvm_tpr_access_ctl tac;
4091
4092 r = -EFAULT;
0e96f31e 4093 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4094 goto out;
4095 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4096 if (r)
4097 goto out;
4098 r = -EFAULT;
0e96f31e 4099 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4100 goto out;
4101 r = 0;
4102 break;
4103 };
b93463aa
AK		 4104 case KVM_SET_VAPIC_ADDR: {
4105 struct kvm_vapic_addr va;
7301d6ab 4106 int idx;
b93463aa
AK		 4107
4108 r = -EINVAL;
35754c98 4109 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4110 goto out;
4111 r = -EFAULT;
0e96f31e 4112 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4113 goto out;
7301d6ab 4114 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4115 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4116 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4117 break;
4118 }
890ca9ae
HY		 4119 case KVM_X86_SETUP_MCE: {
4120 u64 mcg_cap;
4121
4122 r = -EFAULT;
0e96f31e 4123 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4124 goto out;
4125 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4126 break;
4127 }
4128 case KVM_X86_SET_MCE: {
4129 struct kvm_x86_mce mce;
4130
4131 r = -EFAULT;
0e96f31e 4132 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4133 goto out;
4134 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4135 break;
4136 }
3cfc3092
JK		 4137 case KVM_GET_VCPU_EVENTS: {
4138 struct kvm_vcpu_events events;
4139
4140 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4141
4142 r = -EFAULT;
4143 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4144 break;
4145 r = 0;
4146 break;
4147 }
4148 case KVM_SET_VCPU_EVENTS: {
4149 struct kvm_vcpu_events events;
4150
4151 r = -EFAULT;
4152 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4153 break;
4154
4155 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4156 break;
4157 }
a1efbe77
JK		 4158 case KVM_GET_DEBUGREGS: {
4159 struct kvm_debugregs dbgregs;
4160
4161 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4162
4163 r = -EFAULT;
4164 if (copy_to_user(argp, &dbgregs,
4165 sizeof(struct kvm_debugregs)))
4166 break;
4167 r = 0;
4168 break;
4169 }
4170 case KVM_SET_DEBUGREGS: {
4171 struct kvm_debugregs dbgregs;
4172
4173 r = -EFAULT;
4174 if (copy_from_user(&dbgregs, argp,
4175 sizeof(struct kvm_debugregs)))
4176 break;
4177
4178 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4179 break;
4180 }
2d5b5a66 4181 case KVM_GET_XSAVE: {
254272ce 4182 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4183 r = -ENOMEM;
d1ac91d8 4184 if (!u.xsave)
2d5b5a66
SY		 4185 break;
4186
d1ac91d8 4187 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4188
4189 r = -EFAULT;
d1ac91d8 4190 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4191 break;
4192 r = 0;
4193 break;
4194 }
4195 case KVM_SET_XSAVE: {
ff5c2c03 4196 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4197 if (IS_ERR(u.xsave)) {
4198 r = PTR_ERR(u.xsave);
4199 goto out_nofree;
4200 }
2d5b5a66 4201
d1ac91d8 4202 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4203 break;
4204 }
4205 case KVM_GET_XCRS: {
254272ce 4206 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4207 r = -ENOMEM;
d1ac91d8 4208 if (!u.xcrs)
2d5b5a66
SY		 4209 break;
4210
d1ac91d8 4211 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4212
4213 r = -EFAULT;
d1ac91d8 4214 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4215 sizeof(struct kvm_xcrs)))
4216 break;
4217 r = 0;
4218 break;
4219 }
4220 case KVM_SET_XCRS: {
ff5c2c03 4221 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4222 if (IS_ERR(u.xcrs)) {
4223 r = PTR_ERR(u.xcrs);
4224 goto out_nofree;
4225 }
2d5b5a66 4226
d1ac91d8 4227 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4228 break;
4229 }
92a1f12d
JR		 4230 case KVM_SET_TSC_KHZ: {
4231 u32 user_tsc_khz;
4232
4233 r = -EINVAL;
92a1f12d
JR		 4234 user_tsc_khz = (u32)arg;
4235
4236 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4237 goto out;
4238
cc578287
ZA		 4239 if (user_tsc_khz == 0)
4240 user_tsc_khz = tsc_khz;
4241
381d585c
HZ		 4242 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4243 r = 0;
92a1f12d 4244
92a1f12d
JR		 4245 goto out;
4246 }
4247 case KVM_GET_TSC_KHZ: {
cc578287 4248 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4249 goto out;
4250 }
1c0b28c2
EM		 4251 case KVM_KVMCLOCK_CTRL: {
4252 r = kvm_set_guest_paused(vcpu);
4253 goto out;
4254 }
5c919412
AS		 4255 case KVM_ENABLE_CAP: {
4256 struct kvm_enable_cap cap;
4257
4258 r = -EFAULT;
4259 if (copy_from_user(&cap, argp, sizeof(cap)))
4260 goto out;
4261 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4262 break;
4263 }
8fcc4b59
JM		 4264 case KVM_GET_NESTED_STATE: {
4265 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4266 u32 user_data_size;
4267
4268 r = -EINVAL;
4269 if (!kvm_x86_ops->get_nested_state)
4270 break;
4271
4272 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4273 r = -EFAULT;
8fcc4b59 4274 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4275 break;
8fcc4b59
JM		 4276
4277 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4278 user_data_size);
4279 if (r < 0)
26b471c7 4280 break;
8fcc4b59
JM		 4281
4282 if (r > user_data_size) {
4283 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4284 r = -EFAULT;
4285 else
4286 r = -E2BIG;
4287 break;
8fcc4b59 4288 }
26b471c7 4289
8fcc4b59
JM		 4290 r = 0;
4291 break;
4292 }
4293 case KVM_SET_NESTED_STATE: {
4294 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4295 struct kvm_nested_state kvm_state;
4296
4297 r = -EINVAL;
4298 if (!kvm_x86_ops->set_nested_state)
4299 break;
4300
26b471c7 4301 r = -EFAULT;
8fcc4b59 4302 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4303 break;
8fcc4b59 4304
26b471c7 4305 r = -EINVAL;
8fcc4b59 4306 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4307 break;
8fcc4b59
JM		 4308
4309 if (kvm_state.flags &
8cab6507
VK		 4310 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4311 | KVM_STATE_NESTED_EVMCS))
26b471c7 4312 break;
8fcc4b59
JM		 4313
4314 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4315 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4316 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4317 break;
8fcc4b59
JM		 4318
4319 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4320 break;
4321 }
2bc39970
VK		 4322 case KVM_GET_SUPPORTED_HV_CPUID: {
4323 struct kvm_cpuid2 __user *cpuid_arg = argp;
4324 struct kvm_cpuid2 cpuid;
4325
4326 r = -EFAULT;
4327 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4328 goto out;
4329
4330 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4331 cpuid_arg->entries);
4332 if (r)
4333 goto out;
4334
4335 r = -EFAULT;
4336 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4337 goto out;
4338 r = 0;
4339 break;
4340 }
313a3dc7
CO		 4341 default:
4342 r = -EINVAL;
4343 }
4344out:
d1ac91d8 4345 kfree(u.buffer);
9b062471
CD		 4346out_nofree:
4347 vcpu_put(vcpu);
313a3dc7
CO		 4348 return r;
4349}
4350
1499fa80 4351vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4352{
4353 return VM_FAULT_SIGBUS;
4354}
4355
1fe779f8
CO		 4356static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4357{
4358 int ret;
4359
4360 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4361 return -EINVAL;
1fe779f8
CO		 4362 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4363 return ret;
4364}
4365
b927a3ce
SY		 4366static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4367 u64 ident_addr)
4368{
2ac52ab8 4369 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4370}
4371
1fe779f8 4372static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4373 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4374{
4375 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4376 return -EINVAL;
4377
79fac95e 4378 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4379
4380 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4381 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4382
79fac95e 4383 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4384 return 0;
4385}
4386
bc8a3d89 4387static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4388{
39de71ec 4389 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4390}
4391
1fe779f8
CO		 4392static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4393{
90bca052 4394 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4395 int r;
4396
4397 r = 0;
4398 switch (chip->chip_id) {
4399 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4400 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4401 sizeof(struct kvm_pic_state));
4402 break;
4403 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4404 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4405 sizeof(struct kvm_pic_state));
4406 break;
4407 case KVM_IRQCHIP_IOAPIC:
33392b49 4408 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4409 break;
4410 default:
4411 r = -EINVAL;
4412 break;
4413 }
4414 return r;
4415}
4416
4417static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4418{
90bca052 4419 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4420 int r;
4421
4422 r = 0;
4423 switch (chip->chip_id) {
4424 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4425 spin_lock(&pic->lock);
4426 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4427 sizeof(struct kvm_pic_state));
90bca052 4428 spin_unlock(&pic->lock);
1fe779f8
CO		 4429 break;
4430 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4431 spin_lock(&pic->lock);
4432 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4433 sizeof(struct kvm_pic_state));
90bca052 4434 spin_unlock(&pic->lock);
1fe779f8
CO		 4435 break;
4436 case KVM_IRQCHIP_IOAPIC:
33392b49 4437 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4438 break;
4439 default:
4440 r = -EINVAL;
4441 break;
4442 }
90bca052 4443 kvm_pic_update_irq(pic);
1fe779f8
CO		 4444 return r;
4445}
4446
e0f63cb9
SY		 4447static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4448{
34f3941c
RK		 4449 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4450
4451 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4452
4453 mutex_lock(&kps->lock);
4454 memcpy(ps, &kps->channels, sizeof(*ps));
4455 mutex_unlock(&kps->lock);
2da29bcc 4456 return 0;
e0f63cb9
SY		 4457}
4458
4459static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4460{
0185604c 4461 int i;
09edea72
RK		 4462 struct kvm_pit *pit = kvm->arch.vpit;
4463
4464 mutex_lock(&pit->pit_state.lock);
34f3941c 4465 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4466 for (i = 0; i < 3; i++)
09edea72
RK		 4467 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4468 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4469 return 0;
e9f42757
BK		 4470}
4471
4472static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4473{
e9f42757
BK		 4474 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4475 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4476 sizeof(ps->channels));
4477 ps->flags = kvm->arch.vpit->pit_state.flags;
4478 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4479 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4480 return 0;
e9f42757
BK		 4481}
4482
4483static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4484{
2da29bcc 4485 int start = 0;
0185604c 4486 int i;
e9f42757 4487 u32 prev_legacy, cur_legacy;
09edea72
RK		 4488 struct kvm_pit *pit = kvm->arch.vpit;
4489
4490 mutex_lock(&pit->pit_state.lock);
4491 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4492 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4493 if (!prev_legacy && cur_legacy)
4494 start = 1;
09edea72
RK		 4495 memcpy(&pit->pit_state.channels, &ps->channels,
4496 sizeof(pit->pit_state.channels));
4497 pit->pit_state.flags = ps->flags;
0185604c 4498 for (i = 0; i < 3; i++)
09edea72 4499 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4500 start && i == 0);
09edea72 4501 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4502 return 0;
e0f63cb9
SY		 4503}
4504
52d939a0
MT		 4505static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4506 struct kvm_reinject_control *control)
4507{
71474e2f
RK		 4508 struct kvm_pit *pit = kvm->arch.vpit;
4509
4510 if (!pit)
52d939a0 4511 return -ENXIO;
b39c90b6 4512
71474e2f
RK		 4513 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4514 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4515 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4516 */
4517 mutex_lock(&pit->pit_state.lock);
4518 kvm_pit_set_reinject(pit, control->pit_reinject);
4519 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4520
52d939a0
MT		 4521 return 0;
4522}
4523
95d4c16c 4524/**
60c34612
TY		 4525 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4526 * @kvm: kvm instance
4527 * @log: slot id and address to which we copy the log
95d4c16c 4528 *
e108ff2f
PB		 4529 * Steps 1-4 below provide general overview of dirty page logging. See
4530 * kvm_get_dirty_log_protect() function description for additional details.
4531 *
4532 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4533 * always flush the TLB (step 4) even if previous step failed and the dirty
4534 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4535 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4536 * writes will be marked dirty for next log read.
95d4c16c 4537 *
60c34612
TY		 4538 * 1. Take a snapshot of the bit and clear it if needed.
4539 * 2. Write protect the corresponding page.
e108ff2f
PB		 4540 * 3. Copy the snapshot to the userspace.
4541 * 4. Flush TLB's if needed.
5bb064dc 4542 */
60c34612 4543int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4544{
8fe65a82 4545 bool flush = false;
e108ff2f 4546 int r;
5bb064dc 4547
79fac95e 4548 mutex_lock(&kvm->slots_lock);
5bb064dc 4549
88178fd4
KH		 4550 /*
4551 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4552 */
4553 if (kvm_x86_ops->flush_log_dirty)
4554 kvm_x86_ops->flush_log_dirty(kvm);
4555
8fe65a82 4556 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4557
4558 /*
4559 * All the TLBs can be flushed out of mmu lock, see the comments in
4560 * kvm_mmu_slot_remove_write_access().
4561 */
e108ff2f 4562 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4563 if (flush)
2a31b9db
PB		 4564 kvm_flush_remote_tlbs(kvm);
4565
4566 mutex_unlock(&kvm->slots_lock);
4567 return r;
4568}
4569
4570int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4571{
4572 bool flush = false;
4573 int r;
4574
4575 mutex_lock(&kvm->slots_lock);
4576
4577 /*
4578 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4579 */
4580 if (kvm_x86_ops->flush_log_dirty)
4581 kvm_x86_ops->flush_log_dirty(kvm);
4582
4583 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4584
4585 /*
4586 * All the TLBs can be flushed out of mmu lock, see the comments in
4587 * kvm_mmu_slot_remove_write_access().
4588 */
4589 lockdep_assert_held(&kvm->slots_lock);
4590 if (flush)
198c74f4
XG		 4591 kvm_flush_remote_tlbs(kvm);
4592
79fac95e 4593 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4594 return r;
4595}
4596
aa2fbe6d
YZ		 4597int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4598 bool line_status)
23d43cf9
CD		 4599{
4600 if (!irqchip_in_kernel(kvm))
4601 return -ENXIO;
4602
4603 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4604 irq_event->irq, irq_event->level,
4605 line_status);
23d43cf9
CD		 4606 return 0;
4607}
4608
e5d83c74
PB		 4609int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4610 struct kvm_enable_cap *cap)
90de4a18
NA		 4611{
4612 int r;
4613
4614 if (cap->flags)
4615 return -EINVAL;
4616
4617 switch (cap->cap) {
4618 case KVM_CAP_DISABLE_QUIRKS:
4619 kvm->arch.disabled_quirks = cap->args[0];
4620 r = 0;
4621 break;
49df6397
SR		 4622 case KVM_CAP_SPLIT_IRQCHIP: {
4623 mutex_lock(&kvm->lock);
b053b2ae
SR		 4624 r = -EINVAL;
4625 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4626 goto split_irqchip_unlock;
49df6397
SR		 4627 r = -EEXIST;
4628 if (irqchip_in_kernel(kvm))
4629 goto split_irqchip_unlock;
557abc40 4630 if (kvm->created_vcpus)
49df6397
SR		 4631 goto split_irqchip_unlock;
4632 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4633 if (r)
49df6397
SR		 4634 goto split_irqchip_unlock;
4635 /* Pairs with irqchip_in_kernel. */
4636 smp_wmb();
49776faf 4637 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4638 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4639 r = 0;
4640split_irqchip_unlock:
4641 mutex_unlock(&kvm->lock);
4642 break;
4643 }
37131313
RK		 4644 case KVM_CAP_X2APIC_API:
4645 r = -EINVAL;
4646 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4647 break;
4648
4649 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4650 kvm->arch.x2apic_format = true;
c519265f
RK		 4651 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4652 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4653
4654 r = 0;
4655 break;
4d5422ce
WL		 4656 case KVM_CAP_X86_DISABLE_EXITS:
4657 r = -EINVAL;
4658 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4659 break;
4660
4661 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4662 kvm_can_mwait_in_guest())
4663 kvm->arch.mwait_in_guest = true;
766d3571 4664 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4665 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4666 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4667 kvm->arch.pause_in_guest = true;
b5170063
WL		 4668 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4669 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4670 r = 0;
4671 break;
6fbbde9a
DS		 4672 case KVM_CAP_MSR_PLATFORM_INFO:
4673 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4674 r = 0;
c4f55198
JM		 4675 break;
4676 case KVM_CAP_EXCEPTION_PAYLOAD:
4677 kvm->arch.exception_payload_enabled = cap->args[0];
4678 r = 0;
6fbbde9a 4679 break;
90de4a18
NA		 4680 default:
4681 r = -EINVAL;
4682 break;
4683 }
4684 return r;
4685}
4686
1fe779f8
CO		 4687long kvm_arch_vm_ioctl(struct file *filp,
4688 unsigned int ioctl, unsigned long arg)
4689{
4690 struct kvm *kvm = filp->private_data;
4691 void __user *argp = (void __user *)arg;
367e1319 4692 int r = -ENOTTY;
f0d66275
DH		 4693 /*
4694 * This union makes it completely explicit to gcc-3.x
4695 * that these two variables' stack usage should be
4696 * combined, not added together.
4697 */
4698 union {
4699 struct kvm_pit_state ps;
e9f42757 4700 struct kvm_pit_state2 ps2;
c5ff41ce 4701 struct kvm_pit_config pit_config;
f0d66275 4702 } u;
1fe779f8
CO		 4703
4704 switch (ioctl) {
4705 case KVM_SET_TSS_ADDR:
4706 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4707 break;
b927a3ce
SY		 4708 case KVM_SET_IDENTITY_MAP_ADDR: {
4709 u64 ident_addr;
4710
1af1ac91
DH		 4711 mutex_lock(&kvm->lock);
4712 r = -EINVAL;
4713 if (kvm->created_vcpus)
4714 goto set_identity_unlock;
b927a3ce 4715 r = -EFAULT;
0e96f31e 4716 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4717 goto set_identity_unlock;
b927a3ce 4718 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4719set_identity_unlock:
4720 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4721 break;
4722 }
1fe779f8
CO		 4723 case KVM_SET_NR_MMU_PAGES:
4724 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4725 break;
4726 case KVM_GET_NR_MMU_PAGES:
4727 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4728 break;
3ddea128 4729 case KVM_CREATE_IRQCHIP: {
3ddea128 4730 mutex_lock(&kvm->lock);
09941366 4731
3ddea128 4732 r = -EEXIST;
35e6eaa3 4733 if (irqchip_in_kernel(kvm))
3ddea128 4734 goto create_irqchip_unlock;
09941366 4735
3e515705 4736 r = -EINVAL;
557abc40 4737 if (kvm->created_vcpus)
3e515705 4738 goto create_irqchip_unlock;
09941366
RK		 4739
4740 r = kvm_pic_init(kvm);
4741 if (r)
3ddea128 4742 goto create_irqchip_unlock;
09941366
RK		 4743
4744 r = kvm_ioapic_init(kvm);
4745 if (r) {
09941366 4746 kvm_pic_destroy(kvm);
3ddea128 4747 goto create_irqchip_unlock;
09941366
RK		 4748 }
4749
399ec807
AK		 4750 r = kvm_setup_default_irq_routing(kvm);
4751 if (r) {
72bb2fcd 4752 kvm_ioapic_destroy(kvm);
09941366 4753 kvm_pic_destroy(kvm);
71ba994c 4754 goto create_irqchip_unlock;
399ec807 4755 }
49776faf 4756 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4757 smp_wmb();
49776faf 4758 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4759 create_irqchip_unlock:
4760 mutex_unlock(&kvm->lock);
1fe779f8 4761 break;
3ddea128 4762 }
7837699f 4763 case KVM_CREATE_PIT:
c5ff41ce
JK		 4764 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4765 goto create_pit;
4766 case KVM_CREATE_PIT2:
4767 r = -EFAULT;
4768 if (copy_from_user(&u.pit_config, argp,
4769 sizeof(struct kvm_pit_config)))
4770 goto out;
4771 create_pit:
250715a6 4772 mutex_lock(&kvm->lock);
269e05e4
AK		 4773 r = -EEXIST;
4774 if (kvm->arch.vpit)
4775 goto create_pit_unlock;
7837699f 4776 r = -ENOMEM;
c5ff41ce 4777 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4778 if (kvm->arch.vpit)
4779 r = 0;
269e05e4 4780 create_pit_unlock:
250715a6 4781 mutex_unlock(&kvm->lock);
7837699f 4782 break;
1fe779f8
CO		 4783 case KVM_GET_IRQCHIP: {
4784 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4785 struct kvm_irqchip *chip;
1fe779f8 4786
ff5c2c03
SL		 4787 chip = memdup_user(argp, sizeof(*chip));
4788 if (IS_ERR(chip)) {
4789 r = PTR_ERR(chip);
1fe779f8 4790 goto out;
ff5c2c03
SL		 4791 }
4792
1fe779f8 4793 r = -ENXIO;
826da321 4794 if (!irqchip_kernel(kvm))
f0d66275
DH		 4795 goto get_irqchip_out;
4796 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4797 if (r)
f0d66275 4798 goto get_irqchip_out;
1fe779f8 4799 r = -EFAULT;
0e96f31e 4800 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4801 goto get_irqchip_out;
1fe779f8 4802 r = 0;
f0d66275
DH		 4803 get_irqchip_out:
4804 kfree(chip);
1fe779f8
CO		 4805 break;
4806 }
4807 case KVM_SET_IRQCHIP: {
4808 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4809 struct kvm_irqchip *chip;
1fe779f8 4810
ff5c2c03
SL		 4811 chip = memdup_user(argp, sizeof(*chip));
4812 if (IS_ERR(chip)) {
4813 r = PTR_ERR(chip);
1fe779f8 4814 goto out;
ff5c2c03
SL		 4815 }
4816
1fe779f8 4817 r = -ENXIO;
826da321 4818 if (!irqchip_kernel(kvm))
f0d66275
DH		 4819 goto set_irqchip_out;
4820 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4821 if (r)
f0d66275 4822 goto set_irqchip_out;
1fe779f8 4823 r = 0;
f0d66275
DH		 4824 set_irqchip_out:
4825 kfree(chip);
1fe779f8
CO		 4826 break;
4827 }
e0f63cb9 4828 case KVM_GET_PIT: {
e0f63cb9 4829 r = -EFAULT;
f0d66275 4830 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4831 goto out;
4832 r = -ENXIO;
4833 if (!kvm->arch.vpit)
4834 goto out;
f0d66275 4835 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4836 if (r)
4837 goto out;
4838 r = -EFAULT;
f0d66275 4839 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4840 goto out;
4841 r = 0;
4842 break;
4843 }
4844 case KVM_SET_PIT: {
e0f63cb9 4845 r = -EFAULT;
0e96f31e 4846 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4847 goto out;
4848 r = -ENXIO;
4849 if (!kvm->arch.vpit)
4850 goto out;
f0d66275 4851 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4852 break;
4853 }
e9f42757
BK		 4854 case KVM_GET_PIT2: {
4855 r = -ENXIO;
4856 if (!kvm->arch.vpit)
4857 goto out;
4858 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4859 if (r)
4860 goto out;
4861 r = -EFAULT;
4862 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4863 goto out;
4864 r = 0;
4865 break;
4866 }
4867 case KVM_SET_PIT2: {
4868 r = -EFAULT;
4869 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4870 goto out;
4871 r = -ENXIO;
4872 if (!kvm->arch.vpit)
4873 goto out;
4874 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4875 break;
4876 }
52d939a0
MT		 4877 case KVM_REINJECT_CONTROL: {
4878 struct kvm_reinject_control control;
4879 r = -EFAULT;
4880 if (copy_from_user(&control, argp, sizeof(control)))
4881 goto out;
4882 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4883 break;
4884 }
d71ba788
PB		 4885 case KVM_SET_BOOT_CPU_ID:
4886 r = 0;
4887 mutex_lock(&kvm->lock);
557abc40 4888 if (kvm->created_vcpus)
d71ba788
PB		 4889 r = -EBUSY;
4890 else
4891 kvm->arch.bsp_vcpu_id = arg;
4892 mutex_unlock(&kvm->lock);
4893 break;
ffde22ac 4894 case KVM_XEN_HVM_CONFIG: {
51776043 4895 struct kvm_xen_hvm_config xhc;
ffde22ac 4896 r = -EFAULT;
51776043 4897 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4898 goto out;
4899 r = -EINVAL;
51776043 4900 if (xhc.flags)
ffde22ac 4901 goto out;
51776043 4902 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4903 r = 0;
4904 break;
4905 }
afbcf7ab 4906 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4907 struct kvm_clock_data user_ns;
4908 u64 now_ns;
afbcf7ab
GC		 4909
4910 r = -EFAULT;
4911 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4912 goto out;
4913
4914 r = -EINVAL;
4915 if (user_ns.flags)
4916 goto out;
4917
4918 r = 0;
0bc48bea
RK		 4919 /*
4920 * TODO: userspace has to take care of races with VCPU_RUN, so
4921 * kvm_gen_update_masterclock() can be cut down to locked
4922 * pvclock_update_vm_gtod_copy().
4923 */
4924 kvm_gen_update_masterclock(kvm);
e891a32e 4925 now_ns = get_kvmclock_ns(kvm);
108b249c 4926 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4927 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4928 break;
4929 }
4930 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4931 struct kvm_clock_data user_ns;
4932 u64 now_ns;
4933
e891a32e 4934 now_ns = get_kvmclock_ns(kvm);
108b249c 4935 user_ns.clock = now_ns;
e3fd9a93 4936 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4937 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4938
4939 r = -EFAULT;
4940 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4941 goto out;
4942 r = 0;
4943 break;
4944 }
5acc5c06
BS		 4945 case KVM_MEMORY_ENCRYPT_OP: {
4946 r = -ENOTTY;
4947 if (kvm_x86_ops->mem_enc_op)
4948 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4949 break;
4950 }
69eaedee
BS		 4951 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4952 struct kvm_enc_region region;
4953
4954 r = -EFAULT;
4955 if (copy_from_user(&region, argp, sizeof(region)))
4956 goto out;
4957
4958 r = -ENOTTY;
4959 if (kvm_x86_ops->mem_enc_reg_region)
4960 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4961 break;
4962 }
4963 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4964 struct kvm_enc_region region;
4965
4966 r = -EFAULT;
4967 if (copy_from_user(&region, argp, sizeof(region)))
4968 goto out;
4969
4970 r = -ENOTTY;
4971 if (kvm_x86_ops->mem_enc_unreg_region)
4972 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4973 break;
4974 }
faeb7833
RK		 4975 case KVM_HYPERV_EVENTFD: {
4976 struct kvm_hyperv_eventfd hvevfd;
4977
4978 r = -EFAULT;
4979 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4980 goto out;
4981 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4982 break;
4983 }
66bb8a06
EH		 4984 case KVM_SET_PMU_EVENT_FILTER:
4985 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
4986 break;
1fe779f8 4987 default:
ad6260da 4988 r = -ENOTTY;
1fe779f8
CO		 4989 }
4990out:
4991 return r;
4992}
4993
a16b043c 4994static void kvm_init_msr_list(void)
043405e1
CO		 4995{
4996 u32 dummy[2];
4997 unsigned i, j;
4998
62ef68bb 4999 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 5000 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5001 continue;
93c4adc7
PB		 5002
5003 /*
5004 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 5005 * to the guests in some cases.
93c4adc7
PB		 5006 */
5007 switch (msrs_to_save[i]) {
5008 case MSR_IA32_BNDCFGS:
503234b3 5009 if (!kvm_mpx_supported())
93c4adc7
PB		 5010 continue;
5011 break;
9dbe6cf9
PB		 5012 case MSR_TSC_AUX:
5013 if (!kvm_x86_ops->rdtscp_supported())
5014 continue;
5015 break;
bf8c55d8
CP		 5016 case MSR_IA32_RTIT_CTL:
5017 case MSR_IA32_RTIT_STATUS:
5018 if (!kvm_x86_ops->pt_supported())
5019 continue;
5020 break;
5021 case MSR_IA32_RTIT_CR3_MATCH:
5022 if (!kvm_x86_ops->pt_supported() ||
5023 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5024 continue;
5025 break;
5026 case MSR_IA32_RTIT_OUTPUT_BASE:
5027 case MSR_IA32_RTIT_OUTPUT_MASK:
5028 if (!kvm_x86_ops->pt_supported() ||
5029 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5030 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5031 continue;
5032 break;
5033 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5034 if (!kvm_x86_ops->pt_supported() ||
5035 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5036 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5037 continue;
5038 break;
5039 }
93c4adc7
PB		 5040 default:
5041 break;
5042 }
5043
043405e1
CO		 5044 if (j < i)
5045 msrs_to_save[j] = msrs_to_save[i];
5046 j++;
5047 }
5048 num_msrs_to_save = j;
62ef68bb
PB		 5049
5050 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 5051 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5052 continue;
62ef68bb
PB		 5053
5054 if (j < i)
5055 emulated_msrs[j] = emulated_msrs[i];
5056 j++;
5057 }
5058 num_emulated_msrs = j;
801e459a
TL		 5059
5060 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5061 struct kvm_msr_entry msr;
5062
5063 msr.index = msr_based_features[i];
66421c1e 5064 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5065 continue;
5066
5067 if (j < i)
5068 msr_based_features[j] = msr_based_features[i];
5069 j++;
5070 }
5071 num_msr_based_features = j;
043405e1
CO		 5072}
5073
bda9020e
MT		 5074static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5075 const void *v)
bbd9b64e 5076{
70252a10
AK		 5077 int handled = 0;
5078 int n;
5079
5080 do {
5081 n = min(len, 8);
bce87cce 5082 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5083 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5084 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5085 break;
5086 handled += n;
5087 addr += n;
5088 len -= n;
5089 v += n;
5090 } while (len);
bbd9b64e 5091
70252a10 5092 return handled;
bbd9b64e
CO		 5093}
5094
bda9020e 5095static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5096{
70252a10
AK		 5097 int handled = 0;
5098 int n;
5099
5100 do {
5101 n = min(len, 8);
bce87cce 5102 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5103 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5104 addr, n, v))
5105 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5106 break;
e39d200f 5107 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5108 handled += n;
5109 addr += n;
5110 len -= n;
5111 v += n;
5112 } while (len);
bbd9b64e 5113
70252a10 5114 return handled;
bbd9b64e
CO		 5115}
5116
2dafc6c2
GN		 5117static void kvm_set_segment(struct kvm_vcpu *vcpu,
5118 struct kvm_segment *var, int seg)
5119{
5120 kvm_x86_ops->set_segment(vcpu, var, seg);
5121}
5122
5123void kvm_get_segment(struct kvm_vcpu *vcpu,
5124 struct kvm_segment *var, int seg)
5125{
5126 kvm_x86_ops->get_segment(vcpu, var, seg);
5127}
5128
54987b7a
PB		 5129gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5130 struct x86_exception *exception)
02f59dc9
JR		 5131{
5132 gpa_t t_gpa;
02f59dc9
JR		 5133
5134 BUG_ON(!mmu_is_nested(vcpu));
5135
5136 /* NPT walks are always user-walks */
5137 access |= PFERR_USER_MASK;
44dd3ffa 5138 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5139
5140 return t_gpa;
5141}
5142
ab9ae313
AK		 5143gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5144 struct x86_exception *exception)
1871c602
GN		 5145{
5146 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5147 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5148}
5149
ab9ae313
AK		 5150 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5151 struct x86_exception *exception)
1871c602
GN		 5152{
5153 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5154 access |= PFERR_FETCH_MASK;
ab9ae313 5155 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5156}
5157
ab9ae313
AK		 5158gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5159 struct x86_exception *exception)
1871c602
GN		 5160{
5161 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5162 access |= PFERR_WRITE_MASK;
ab9ae313 5163 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5164}
5165
5166/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5167gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5168 struct x86_exception *exception)
1871c602 5169{
ab9ae313 5170 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5171}
5172
5173static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5174 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5175 struct x86_exception *exception)
bbd9b64e
CO		 5176{
5177 void *data = val;
10589a46 5178 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5179
5180 while (bytes) {
14dfe855 5181 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5182 exception);
bbd9b64e 5183 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5184 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5185 int ret;
5186
bcc55cba 5187 if (gpa == UNMAPPED_GVA)
ab9ae313 5188 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5189 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5190 offset, toread);
10589a46 5191 if (ret < 0) {
c3cd7ffa 5192 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5193 goto out;
5194 }
bbd9b64e 5195
77c2002e
IE		 5196 bytes -= toread;
5197 data += toread;
5198 addr += toread;
bbd9b64e 5199 }
10589a46 5200out:
10589a46 5201 return r;
bbd9b64e 5202}
77c2002e 5203
1871c602 5204/* used for instruction fetching */
0f65dd70
AK		 5205static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5206 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5207 struct x86_exception *exception)
1871c602 5208{
0f65dd70 5209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5210 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5211 unsigned offset;
5212 int ret;
0f65dd70 5213
44583cba
PB		 5214 /* Inline kvm_read_guest_virt_helper for speed. */
5215 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5216 exception);
5217 if (unlikely(gpa == UNMAPPED_GVA))
5218 return X86EMUL_PROPAGATE_FAULT;
5219
5220 offset = addr & (PAGE_SIZE-1);
5221 if (WARN_ON(offset + bytes > PAGE_SIZE))
5222 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5223 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5224 offset, bytes);
44583cba
PB		 5225 if (unlikely(ret < 0))
5226 return X86EMUL_IO_NEEDED;
5227
5228 return X86EMUL_CONTINUE;
1871c602
GN		 5229}
5230
ce14e868 5231int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5232 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5233 struct x86_exception *exception)
1871c602
GN		 5234{
5235 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5236
353c0956
PB		 5237 /*
5238 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5239 * is returned, but our callers are not ready for that and they blindly
5240 * call kvm_inject_page_fault. Ensure that they at least do not leak
5241 * uninitialized kernel stack memory into cr2 and error code.
5242 */
5243 memset(exception, 0, sizeof(*exception));
1871c602 5244 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5245 exception);
1871c602 5246}
064aea77 5247EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5248
ce14e868
PB		 5249static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5250 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5251 struct x86_exception *exception, bool system)
1871c602 5252{
0f65dd70 5253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5254 u32 access = 0;
5255
5256 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5257 access |= PFERR_USER_MASK;
5258
5259 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5260}
5261
7a036a6f
RK		 5262static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5263 unsigned long addr, void *val, unsigned int bytes)
5264{
5265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5266 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5267
5268 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5269}
5270
ce14e868
PB		 5271static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5272 struct kvm_vcpu *vcpu, u32 access,
5273 struct x86_exception *exception)
77c2002e
IE		 5274{
5275 void *data = val;
5276 int r = X86EMUL_CONTINUE;
5277
5278 while (bytes) {
14dfe855 5279 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5280 access,
ab9ae313 5281 exception);
77c2002e
IE		 5282 unsigned offset = addr & (PAGE_SIZE-1);
5283 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5284 int ret;
5285
bcc55cba 5286 if (gpa == UNMAPPED_GVA)
ab9ae313 5287 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5288 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5289 if (ret < 0) {
c3cd7ffa 5290 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5291 goto out;
5292 }
5293
5294 bytes -= towrite;
5295 data += towrite;
5296 addr += towrite;
5297 }
5298out:
5299 return r;
5300}
ce14e868
PB		 5301
5302static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5303 unsigned int bytes, struct x86_exception *exception,
5304 bool system)
ce14e868
PB		 5305{
5306 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5307 u32 access = PFERR_WRITE_MASK;
5308
5309 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5310 access |= PFERR_USER_MASK;
ce14e868
PB		 5311
5312 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5313 access, exception);
ce14e868
PB		 5314}
5315
5316int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5317 unsigned int bytes, struct x86_exception *exception)
5318{
c595ceee
PB		 5319 /* kvm_write_guest_virt_system can pull in tons of pages. */
5320 vcpu->arch.l1tf_flush_l1d = true;
5321
ce14e868
PB		 5322 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5323 PFERR_WRITE_MASK, exception);
5324}
6a4d7550 5325EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5326
082d06ed
WL		 5327int handle_ud(struct kvm_vcpu *vcpu)
5328{
6c86eedc 5329 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5330 enum emulation_result er;
6c86eedc
WL		 5331 char sig[5]; /* ud2; .ascii "kvm" */
5332 struct x86_exception e;
5333
5334 if (force_emulation_prefix &&
3c9fa24c
PB		 5335 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5336 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5337 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5338 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5339 emul_type = 0;
5340 }
082d06ed 5341
0ce97a2b 5342 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5343 if (er == EMULATE_USER_EXIT)
5344 return 0;
5345 if (er != EMULATE_DONE)
5346 kvm_queue_exception(vcpu, UD_VECTOR);
5347 return 1;
5348}
5349EXPORT_SYMBOL_GPL(handle_ud);
5350
0f89b207
TL		 5351static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5352 gpa_t gpa, bool write)
5353{
5354 /* For APIC access vmexit */
5355 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5356 return 1;
5357
5358 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5359 trace_vcpu_match_mmio(gva, gpa, write, true);
5360 return 1;
5361 }
5362
5363 return 0;
5364}
5365
af7cc7d1
XG		 5366static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5367 gpa_t *gpa, struct x86_exception *exception,
5368 bool write)
5369{
97d64b78
AK		 5370 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5371 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5372
be94f6b7
HH		 5373 /*
5374 * currently PKRU is only applied to ept enabled guest so
5375 * there is no pkey in EPT page table for L1 guest or EPT
5376 * shadow page table for L2 guest.
5377 */
97d64b78 5378 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5379 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5380 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5381 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5382 (gva & (PAGE_SIZE - 1));
4f022648 5383 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5384 return 1;
5385 }
5386
af7cc7d1
XG		 5387 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5388
5389 if (*gpa == UNMAPPED_GVA)
5390 return -1;
5391
0f89b207 5392 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5393}
5394
3200f405 5395int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5396 const void *val, int bytes)
bbd9b64e
CO		 5397{
5398 int ret;
5399
54bf36aa 5400 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5401 if (ret < 0)
bbd9b64e 5402 return 0;
0eb05bf2 5403 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5404 return 1;
5405}
5406
77d197b2
XG		 5407struct read_write_emulator_ops {
5408 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5409 int bytes);
5410 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5411 void *val, int bytes);
5412 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5413 int bytes, void *val);
5414 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5415 void *val, int bytes);
5416 bool write;
5417};
5418
5419static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5420{
5421 if (vcpu->mmio_read_completed) {
77d197b2 5422 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5423 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5424 vcpu->mmio_read_completed = 0;
5425 return 1;
5426 }
5427
5428 return 0;
5429}
5430
5431static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5432 void *val, int bytes)
5433{
54bf36aa 5434 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5435}
5436
5437static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5438 void *val, int bytes)
5439{
5440 return emulator_write_phys(vcpu, gpa, val, bytes);
5441}
5442
5443static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5444{
e39d200f 5445 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5446 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5447}
5448
5449static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5450 void *val, int bytes)
5451{
e39d200f 5452 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5453 return X86EMUL_IO_NEEDED;
5454}
5455
5456static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5457 void *val, int bytes)
5458{
f78146b0
AK		 5459 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5460
87da7e66 5461 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5462 return X86EMUL_CONTINUE;
5463}
5464
0fbe9b0b 5465static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5466 .read_write_prepare = read_prepare,
5467 .read_write_emulate = read_emulate,
5468 .read_write_mmio = vcpu_mmio_read,
5469 .read_write_exit_mmio = read_exit_mmio,
5470};
5471
0fbe9b0b 5472static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5473 .read_write_emulate = write_emulate,
5474 .read_write_mmio = write_mmio,
5475 .read_write_exit_mmio = write_exit_mmio,
5476 .write = true,
5477};
5478
22388a3c
XG		 5479static int emulator_read_write_onepage(unsigned long addr, void *val,
5480 unsigned int bytes,
5481 struct x86_exception *exception,
5482 struct kvm_vcpu *vcpu,
0fbe9b0b 5483 const struct read_write_emulator_ops *ops)
bbd9b64e 5484{
af7cc7d1
XG		 5485 gpa_t gpa;
5486 int handled, ret;
22388a3c 5487 bool write = ops->write;
f78146b0 5488 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5489 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5490
5491 /*
5492 * If the exit was due to a NPF we may already have a GPA.
5493 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5494 * Note, this cannot be used on string operations since string
5495 * operation using rep will only have the initial GPA from the NPF
5496 * occurred.
5497 */
5498 if (vcpu->arch.gpa_available &&
5499 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5500 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5501 gpa = vcpu->arch.gpa_val;
5502 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5503 } else {
5504 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5505 if (ret < 0)
5506 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5507 }
10589a46 5508
618232e2 5509 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5510 return X86EMUL_CONTINUE;
5511
bbd9b64e
CO		 5512 /*
5513 * Is this MMIO handled locally?
5514 */
22388a3c 5515 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5516 if (handled == bytes)
bbd9b64e 5517 return X86EMUL_CONTINUE;
bbd9b64e 5518
70252a10
AK		 5519 gpa += handled;
5520 bytes -= handled;
5521 val += handled;
5522
87da7e66
XG		 5523 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5524 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5525 frag->gpa = gpa;
5526 frag->data = val;
5527 frag->len = bytes;
f78146b0 5528 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5529}
5530
52eb5a6d
XL		 5531static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5532 unsigned long addr,
22388a3c
XG		 5533 void *val, unsigned int bytes,
5534 struct x86_exception *exception,
0fbe9b0b 5535 const struct read_write_emulator_ops *ops)
bbd9b64e 5536{
0f65dd70 5537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5538 gpa_t gpa;
5539 int rc;
5540
5541 if (ops->read_write_prepare &&
5542 ops->read_write_prepare(vcpu, val, bytes))
5543 return X86EMUL_CONTINUE;
5544
5545 vcpu->mmio_nr_fragments = 0;
0f65dd70 5546
bbd9b64e
CO		 5547 /* Crossing a page boundary? */
5548 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5549 int now;
bbd9b64e
CO		 5550
5551 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5552 rc = emulator_read_write_onepage(addr, val, now, exception,
5553 vcpu, ops);
5554
bbd9b64e
CO		 5555 if (rc != X86EMUL_CONTINUE)
5556 return rc;
5557 addr += now;
bac15531
NA		 5558 if (ctxt->mode != X86EMUL_MODE_PROT64)
5559 addr = (u32)addr;
bbd9b64e
CO		 5560 val += now;
5561 bytes -= now;
5562 }
22388a3c 5563
f78146b0
AK		 5564 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5565 vcpu, ops);
5566 if (rc != X86EMUL_CONTINUE)
5567 return rc;
5568
5569 if (!vcpu->mmio_nr_fragments)
5570 return rc;
5571
5572 gpa = vcpu->mmio_fragments[0].gpa;
5573
5574 vcpu->mmio_needed = 1;
5575 vcpu->mmio_cur_fragment = 0;
5576
87da7e66 5577 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5578 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5579 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5580 vcpu->run->mmio.phys_addr = gpa;
5581
5582 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5583}
5584
5585static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5586 unsigned long addr,
5587 void *val,
5588 unsigned int bytes,
5589 struct x86_exception *exception)
5590{
5591 return emulator_read_write(ctxt, addr, val, bytes,
5592 exception, &read_emultor);
5593}
5594
52eb5a6d 5595static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5596 unsigned long addr,
5597 const void *val,
5598 unsigned int bytes,
5599 struct x86_exception *exception)
5600{
5601 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5602 exception, &write_emultor);
bbd9b64e 5603}
bbd9b64e 5604
daea3e73
AK		 5605#define CMPXCHG_TYPE(t, ptr, old, new) \
5606 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5607
5608#ifdef CONFIG_X86_64
5609# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5610#else
5611# define CMPXCHG64(ptr, old, new) \
9749a6c0 5612 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5613#endif
5614
0f65dd70
AK		 5615static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5616 unsigned long addr,
bbd9b64e
CO		 5617 const void *old,
5618 const void *new,
5619 unsigned int bytes,
0f65dd70 5620 struct x86_exception *exception)
bbd9b64e 5621{
42e35f80 5622 struct kvm_host_map map;
0f65dd70 5623 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5624 gpa_t gpa;
daea3e73
AK		 5625 char *kaddr;
5626 bool exchanged;
2bacc55c 5627
daea3e73
AK		 5628 /* guests cmpxchg8b have to be emulated atomically */
5629 if (bytes > 8 || (bytes & (bytes - 1)))
5630 goto emul_write;
10589a46 5631
daea3e73 5632 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5633
daea3e73
AK		 5634 if (gpa == UNMAPPED_GVA ||
5635 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5636 goto emul_write;
2bacc55c 5637
daea3e73
AK		 5638 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5639 goto emul_write;
72dc67a6 5640
42e35f80 5641 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5642 goto emul_write;
72dc67a6 5643
42e35f80
KA		 5644 kaddr = map.hva + offset_in_page(gpa);
5645
daea3e73
AK		 5646 switch (bytes) {
5647 case 1:
5648 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5649 break;
5650 case 2:
5651 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5652 break;
5653 case 4:
5654 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5655 break;
5656 case 8:
5657 exchanged = CMPXCHG64(kaddr, old, new);
5658 break;
5659 default:
5660 BUG();
2bacc55c 5661 }
42e35f80
KA		 5662
5663 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5664
5665 if (!exchanged)
5666 return X86EMUL_CMPXCHG_FAILED;
5667
0eb05bf2 5668 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5669
5670 return X86EMUL_CONTINUE;
4a5f48f6 5671
3200f405 5672emul_write:
daea3e73 5673 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5674
0f65dd70 5675 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5676}
5677
cf8f70bf
GN		 5678static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5679{
cbfc6c91 5680 int r = 0, i;
cf8f70bf 5681
cbfc6c91
WL		 5682 for (i = 0; i < vcpu->arch.pio.count; i++) {
5683 if (vcpu->arch.pio.in)
5684 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5685 vcpu->arch.pio.size, pd);
5686 else
5687 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5688 vcpu->arch.pio.port, vcpu->arch.pio.size,
5689 pd);
5690 if (r)
5691 break;
5692 pd += vcpu->arch.pio.size;
5693 }
cf8f70bf
GN		 5694 return r;
5695}
5696
6f6fbe98
XG		 5697static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5698 unsigned short port, void *val,
5699 unsigned int count, bool in)
cf8f70bf 5700{
cf8f70bf 5701 vcpu->arch.pio.port = port;
6f6fbe98 5702 vcpu->arch.pio.in = in;
7972995b 5703 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5704 vcpu->arch.pio.size = size;
5705
5706 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5707 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5708 return 1;
5709 }
5710
5711 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5712 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5713 vcpu->run->io.size = size;
5714 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5715 vcpu->run->io.count = count;
5716 vcpu->run->io.port = port;
5717
5718 return 0;
5719}
5720
6f6fbe98
XG		 5721static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5722 int size, unsigned short port, void *val,
5723 unsigned int count)
cf8f70bf 5724{
ca1d4a9e 5725 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5726 int ret;
ca1d4a9e 5727
6f6fbe98
XG		 5728 if (vcpu->arch.pio.count)
5729 goto data_avail;
cf8f70bf 5730
cbfc6c91
WL		 5731 memset(vcpu->arch.pio_data, 0, size * count);
5732
6f6fbe98
XG		 5733 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5734 if (ret) {
5735data_avail:
5736 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5737 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5738 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5739 return 1;
5740 }
5741
cf8f70bf
GN		 5742 return 0;
5743}
5744
6f6fbe98
XG		 5745static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5746 int size, unsigned short port,
5747 const void *val, unsigned int count)
5748{
5749 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5750
5751 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5752 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5753 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5754}
5755
bbd9b64e
CO		 5756static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5757{
5758 return kvm_x86_ops->get_segment_base(vcpu, seg);
5759}
5760
3cb16fe7 5761static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5762{
3cb16fe7 5763 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5764}
5765
ae6a2375 5766static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5767{
5768 if (!need_emulate_wbinvd(vcpu))
5769 return X86EMUL_CONTINUE;
5770
5771 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5772 int cpu = get_cpu();
5773
5774 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5775 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5776 wbinvd_ipi, NULL, 1);
2eec7343 5777 put_cpu();
f5f48ee1 5778 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5779 } else
5780 wbinvd();
f5f48ee1
SY		 5781 return X86EMUL_CONTINUE;
5782}
5cb56059
JS		 5783
5784int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5785{
6affcbed
KH		 5786 kvm_emulate_wbinvd_noskip(vcpu);
5787 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5788}
f5f48ee1
SY		 5789EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5790
5cb56059
JS		 5791
5792
bcaf5cc5
AK		 5793static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5794{
5cb56059 5795 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5796}
5797
52eb5a6d
XL		 5798static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5799 unsigned long *dest)
bbd9b64e 5800{
16f8a6f9 5801 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5802}
5803
52eb5a6d
XL		 5804static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5805 unsigned long value)
bbd9b64e 5806{
338dbc97 5807
717746e3 5808 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5809}
5810
52a46617 5811static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5812{
52a46617 5813 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5814}
5815
717746e3 5816static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5817{
717746e3 5818 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5819 unsigned long value;
5820
5821 switch (cr) {
5822 case 0:
5823 value = kvm_read_cr0(vcpu);
5824 break;
5825 case 2:
5826 value = vcpu->arch.cr2;
5827 break;
5828 case 3:
9f8fe504 5829 value = kvm_read_cr3(vcpu);
52a46617
GN		 5830 break;
5831 case 4:
5832 value = kvm_read_cr4(vcpu);
5833 break;
5834 case 8:
5835 value = kvm_get_cr8(vcpu);
5836 break;
5837 default:
a737f256 5838 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5839 return 0;
5840 }
5841
5842 return value;
5843}
5844
717746e3 5845static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5846{
717746e3 5847 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5848 int res = 0;
5849
52a46617
GN		 5850 switch (cr) {
5851 case 0:
49a9b07e 5852 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5853 break;
5854 case 2:
5855 vcpu->arch.cr2 = val;
5856 break;
5857 case 3:
2390218b 5858 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5859 break;
5860 case 4:
a83b29c6 5861 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5862 break;
5863 case 8:
eea1cff9 5864 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5865 break;
5866 default:
a737f256 5867 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5868 res = -1;
52a46617 5869 }
0f12244f
GN		 5870
5871 return res;
52a46617
GN		 5872}
5873
717746e3 5874static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5875{
717746e3 5876 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5877}
5878
4bff1e86 5879static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5880{
4bff1e86 5881 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5882}
5883
4bff1e86 5884static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5885{
4bff1e86 5886 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5887}
5888
1ac9d0cf
AK		 5889static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5890{
5891 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5892}
5893
5894static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5895{
5896 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5897}
5898
4bff1e86
AK		 5899static unsigned long emulator_get_cached_segment_base(
5900 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5901{
4bff1e86 5902 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5903}
5904
1aa36616
AK		 5905static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5906 struct desc_struct *desc, u32 *base3,
5907 int seg)
2dafc6c2
GN		 5908{
5909 struct kvm_segment var;
5910
4bff1e86 5911 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5912 *selector = var.selector;
2dafc6c2 5913
378a8b09
GN		 5914 if (var.unusable) {
5915 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5916 if (base3)
5917 *base3 = 0;
2dafc6c2 5918 return false;
378a8b09 5919 }
2dafc6c2
GN		 5920
5921 if (var.g)
5922 var.limit >>= 12;
5923 set_desc_limit(desc, var.limit);
5924 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5925#ifdef CONFIG_X86_64
5926 if (base3)
5927 *base3 = var.base >> 32;
5928#endif
2dafc6c2
GN		 5929 desc->type = var.type;
5930 desc->s = var.s;
5931 desc->dpl = var.dpl;
5932 desc->p = var.present;
5933 desc->avl = var.avl;
5934 desc->l = var.l;
5935 desc->d = var.db;
5936 desc->g = var.g;
5937
5938 return true;
5939}
5940
1aa36616
AK		 5941static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5942 struct desc_struct *desc, u32 base3,
5943 int seg)
2dafc6c2 5944{
4bff1e86 5945 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5946 struct kvm_segment var;
5947
1aa36616 5948 var.selector = selector;
2dafc6c2 5949 var.base = get_desc_base(desc);
5601d05b
GN		 5950#ifdef CONFIG_X86_64
5951 var.base |= ((u64)base3) << 32;
5952#endif
2dafc6c2
GN		 5953 var.limit = get_desc_limit(desc);
5954 if (desc->g)
5955 var.limit = (var.limit << 12) | 0xfff;
5956 var.type = desc->type;
2dafc6c2
GN		 5957 var.dpl = desc->dpl;
5958 var.db = desc->d;
5959 var.s = desc->s;
5960 var.l = desc->l;
5961 var.g = desc->g;
5962 var.avl = desc->avl;
5963 var.present = desc->p;
5964 var.unusable = !var.present;
5965 var.padding = 0;
5966
5967 kvm_set_segment(vcpu, &var, seg);
5968 return;
5969}
5970
717746e3
AK		 5971static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5972 u32 msr_index, u64 *pdata)
5973{
609e36d3
PB		 5974 struct msr_data msr;
5975 int r;
5976
5977 msr.index = msr_index;
5978 msr.host_initiated = false;
5979 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5980 if (r)
5981 return r;
5982
5983 *pdata = msr.data;
5984 return 0;
717746e3
AK		 5985}
5986
5987static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5988 u32 msr_index, u64 data)
5989{
8fe8ab46
WA		 5990 struct msr_data msr;
5991
5992 msr.data = data;
5993 msr.index = msr_index;
5994 msr.host_initiated = false;
5995 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5996}
5997
64d60670
PB		 5998static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5999{
6000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6001
6002 return vcpu->arch.smbase;
6003}
6004
6005static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6006{
6007 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6008
6009 vcpu->arch.smbase = smbase;
6010}
6011
67f4d428
NA		 6012static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6013 u32 pmc)
6014{
c6702c9d 6015 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6016}
6017
222d21aa
AK		 6018static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6019 u32 pmc, u64 *pdata)
6020{
c6702c9d 6021 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6022}
6023
6c3287f7
AK		 6024static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6025{
6026 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6027}
6028
2953538e 6029static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6030 struct x86_instruction_info *info,
c4f035c6
AK		 6031 enum x86_intercept_stage stage)
6032{
2953538e 6033 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6034}
6035
e911eb3b
YZ		 6036static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6037 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6038{
e911eb3b 6039 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6040}
6041
dd856efa
AK		 6042static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6043{
6044 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6045}
6046
6047static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6048{
6049 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6050}
6051
801806d9
NA		 6052static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6053{
6054 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6055}
6056
6ed071f0
LP		 6057static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6058{
6059 return emul_to_vcpu(ctxt)->arch.hflags;
6060}
6061
6062static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6063{
c5833c7a 6064 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6065}
6066
ed19321f
SC		 6067static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6068 const char *smstate)
0234bf88 6069{
ed19321f 6070 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6071}
6072
c5833c7a
SC		 6073static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6074{
6075 kvm_smm_changed(emul_to_vcpu(ctxt));
6076}
6077
02d4160f
VK		 6078static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6079{
6080 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6081}
6082
0225fb50 6083static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6084 .read_gpr = emulator_read_gpr,
6085 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6086 .read_std = emulator_read_std,
6087 .write_std = emulator_write_std,
7a036a6f 6088 .read_phys = kvm_read_guest_phys_system,
1871c602 6089 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6090 .read_emulated = emulator_read_emulated,
6091 .write_emulated = emulator_write_emulated,
6092 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6093 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6094 .pio_in_emulated = emulator_pio_in_emulated,
6095 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6096 .get_segment = emulator_get_segment,
6097 .set_segment = emulator_set_segment,
5951c442 6098 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6099 .get_gdt = emulator_get_gdt,
160ce1f1 6100 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6101 .set_gdt = emulator_set_gdt,
6102 .set_idt = emulator_set_idt,
52a46617
GN		 6103 .get_cr = emulator_get_cr,
6104 .set_cr = emulator_set_cr,
9c537244 6105 .cpl = emulator_get_cpl,
35aa5375
GN		 6106 .get_dr = emulator_get_dr,
6107 .set_dr = emulator_set_dr,
64d60670
PB		 6108 .get_smbase = emulator_get_smbase,
6109 .set_smbase = emulator_set_smbase,
717746e3
AK		 6110 .set_msr = emulator_set_msr,
6111 .get_msr = emulator_get_msr,
67f4d428 6112 .check_pmc = emulator_check_pmc,
222d21aa 6113 .read_pmc = emulator_read_pmc,
6c3287f7 6114 .halt = emulator_halt,
bcaf5cc5 6115 .wbinvd = emulator_wbinvd,
d6aa1000 6116 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6117 .intercept = emulator_intercept,
bdb42f5a 6118 .get_cpuid = emulator_get_cpuid,
801806d9 6119 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6120 .get_hflags = emulator_get_hflags,
6121 .set_hflags = emulator_set_hflags,
0234bf88 6122 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6123 .post_leave_smm = emulator_post_leave_smm,
02d4160f 6124 .set_xcr = emulator_set_xcr,
bbd9b64e
CO		 6125};
6126
95cb2295
GN		 6127static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6128{
37ccdcbe 6129 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6130 /*
6131 * an sti; sti; sequence only disable interrupts for the first
6132 * instruction. So, if the last instruction, be it emulated or
6133 * not, left the system with the INT_STI flag enabled, it
6134 * means that the last instruction is an sti. We should not
6135 * leave the flag on in this case. The same goes for mov ss
6136 */
37ccdcbe
PB		 6137 if (int_shadow & mask)
6138 mask = 0;
6addfc42 6139 if (unlikely(int_shadow || mask)) {
95cb2295 6140 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6141 if (!mask)
6142 kvm_make_request(KVM_REQ_EVENT, vcpu);
6143 }
95cb2295
GN		 6144}
6145
ef54bcfe 6146static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6147{
6148 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6149 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6150 return kvm_propagate_fault(vcpu, &ctxt->exception);
6151
6152 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6153 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6154 ctxt->exception.error_code);
54b8486f 6155 else
da9cb575 6156 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6157 return false;
54b8486f
GN		 6158}
6159
8ec4722d
MG		 6160static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6161{
adf52235 6162 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6163 int cs_db, cs_l;
6164
8ec4722d
MG		 6165 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6166
adf52235 6167 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6168 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6169
adf52235
TY		 6170 ctxt->eip = kvm_rip_read(vcpu);
6171 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6172 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6173 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6174 cs_db ? X86EMUL_MODE_PROT32 :
6175 X86EMUL_MODE_PROT16;
a584539b 6176 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6177 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6178 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6179
dd856efa 6180 init_decode_cache(ctxt);
7ae441ea 6181 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6182}
6183
71f9833b 6184int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6185{
9d74191a 6186 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6187 int ret;
6188
6189 init_emulate_ctxt(vcpu);
6190
9dac77fa
AK		 6191 ctxt->op_bytes = 2;
6192 ctxt->ad_bytes = 2;
6193 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6194 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6195
6196 if (ret != X86EMUL_CONTINUE)
6197 return EMULATE_FAIL;
6198
9dac77fa 6199 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6200 kvm_rip_write(vcpu, ctxt->eip);
6201 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6202
63995653
MG		 6203 return EMULATE_DONE;
6204}
6205EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6206
e2366171 6207static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6208{
fc3a9157
JR		 6209 int r = EMULATE_DONE;
6210
6d77dbfc
GN		 6211 ++vcpu->stat.insn_emulation_fail;
6212 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6213
6214 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6215 return EMULATE_FAIL;
6216
a2b9e6c1 6217 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6218 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6219 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6220 vcpu->run->internal.ndata = 0;
1f4dcb3b 6221 r = EMULATE_USER_EXIT;
fc3a9157 6222 }
e2366171 6223
6d77dbfc 6224 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6225
6226 return r;
6d77dbfc
GN		 6227}
6228
93c05d3e 6229static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6230 bool write_fault_to_shadow_pgtable,
6231 int emulation_type)
a6f177ef 6232{
95b3cf69 6233 gpa_t gpa = cr2;
ba049e93 6234 kvm_pfn_t pfn;
a6f177ef 6235
384bf221 6236 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6237 return false;
6238
6c3dfeb6
SC		 6239 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6240 return false;
6241
44dd3ffa 6242 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6243 /*
6244 * Write permission should be allowed since only
6245 * write access need to be emulated.
6246 */
6247 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6248
95b3cf69
XG		 6249 /*
6250 * If the mapping is invalid in guest, let cpu retry
6251 * it to generate fault.
6252 */
6253 if (gpa == UNMAPPED_GVA)
6254 return true;
6255 }
a6f177ef 6256
8e3d9d06
XG		 6257 /*
6258 * Do not retry the unhandleable instruction if it faults on the
6259 * readonly host memory, otherwise it will goto a infinite loop:
6260 * retry instruction -> write #PF -> emulation fail -> retry
6261 * instruction -> ...
6262 */
6263 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6264
6265 /*
6266 * If the instruction failed on the error pfn, it can not be fixed,
6267 * report the error to userspace.
6268 */
6269 if (is_error_noslot_pfn(pfn))
6270 return false;
6271
6272 kvm_release_pfn_clean(pfn);
6273
6274 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6275 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6276 unsigned int indirect_shadow_pages;
6277
6278 spin_lock(&vcpu->kvm->mmu_lock);
6279 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6280 spin_unlock(&vcpu->kvm->mmu_lock);
6281
6282 if (indirect_shadow_pages)
6283 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6284
a6f177ef 6285 return true;
8e3d9d06 6286 }
a6f177ef 6287
95b3cf69
XG		 6288 /*
6289 * if emulation was due to access to shadowed page table
6290 * and it failed try to unshadow page and re-enter the
6291 * guest to let CPU execute the instruction.
6292 */
6293 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6294
6295 /*
6296 * If the access faults on its page table, it can not
6297 * be fixed by unprotecting shadow page and it should
6298 * be reported to userspace.
6299 */
6300 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6301}
6302
1cb3f3ae
XG		 6303static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6304 unsigned long cr2, int emulation_type)
6305{
6306 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6307 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6308
6309 last_retry_eip = vcpu->arch.last_retry_eip;
6310 last_retry_addr = vcpu->arch.last_retry_addr;
6311
6312 /*
6313 * If the emulation is caused by #PF and it is non-page_table
6314 * writing instruction, it means the VM-EXIT is caused by shadow
6315 * page protected, we can zap the shadow page and retry this
6316 * instruction directly.
6317 *
6318 * Note: if the guest uses a non-page-table modifying instruction
6319 * on the PDE that points to the instruction, then we will unmap
6320 * the instruction and go to an infinite loop. So, we cache the
6321 * last retried eip and the last fault address, if we meet the eip
6322 * and the address again, we can break out of the potential infinite
6323 * loop.
6324 */
6325 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6326
384bf221 6327 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6328 return false;
6329
6c3dfeb6
SC		 6330 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6331 return false;
6332
1cb3f3ae
XG		 6333 if (x86_page_table_writing_insn(ctxt))
6334 return false;
6335
6336 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6337 return false;
6338
6339 vcpu->arch.last_retry_eip = ctxt->eip;
6340 vcpu->arch.last_retry_addr = cr2;
6341
44dd3ffa 6342 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6343 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6344
22368028 6345 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6346
6347 return true;
6348}
6349
716d51ab
GN		 6350static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6351static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6352
64d60670 6353static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6354{
64d60670 6355 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6356 /* This is a good place to trace that we are exiting SMM. */
6357 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6358
c43203ca
PB		 6359 /* Process a latched INIT or SMI, if any. */
6360 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6361 }
699023e2
PB		 6362
6363 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6364}
6365
4a1e10d5
PB		 6366static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6367 unsigned long *db)
6368{
6369 u32 dr6 = 0;
6370 int i;
6371 u32 enable, rwlen;
6372
6373 enable = dr7;
6374 rwlen = dr7 >> 16;
6375 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6376 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6377 dr6 |= (1 << i);
6378 return dr6;
6379}
6380
c8401dda 6381static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6382{
6383 struct kvm_run *kvm_run = vcpu->run;
6384
c8401dda
PB		 6385 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6386 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6387 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6388 kvm_run->debug.arch.exception = DB_VECTOR;
6389 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6390 *r = EMULATE_USER_EXIT;
6391 } else {
f10c729f 6392 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6393 }
6394}
6395
6affcbed
KH		 6396int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6397{
6398 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
f8ea7c60 6399 int r;
6affcbed 6400
f8ea7c60
VK		 6401 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6402 if (unlikely(r != EMULATE_DONE))
6403 return 0;
c8401dda
PB		 6404
6405 /*
6406 * rflags is the old, "raw" value of the flags. The new value has
6407 * not been saved yet.
6408 *
6409 * This is correct even for TF set by the guest, because "the
6410 * processor will not generate this exception after the instruction
6411 * that sets the TF flag".
6412 */
6413 if (unlikely(rflags & X86_EFLAGS_TF))
6414 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6415 return r == EMULATE_DONE;
6416}
6417EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6418
4a1e10d5
PB		 6419static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6420{
4a1e10d5
PB		 6421 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6422 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6423 struct kvm_run *kvm_run = vcpu->run;
6424 unsigned long eip = kvm_get_linear_rip(vcpu);
6425 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6426 vcpu->arch.guest_debug_dr7,
6427 vcpu->arch.eff_db);
6428
6429 if (dr6 != 0) {
6f43ed01 6430 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6431 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6432 kvm_run->debug.arch.exception = DB_VECTOR;
6433 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6434 *r = EMULATE_USER_EXIT;
6435 return true;
6436 }
6437 }
6438
4161a569
NA		 6439 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6440 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6441 unsigned long eip = kvm_get_linear_rip(vcpu);
6442 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6443 vcpu->arch.dr7,
6444 vcpu->arch.db);
6445
6446 if (dr6 != 0) {
1fc5d194 6447 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6448 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6449 kvm_queue_exception(vcpu, DB_VECTOR);
6450 *r = EMULATE_DONE;
6451 return true;
6452 }
6453 }
6454
6455 return false;
6456}
6457
04789b66
LA		 6458static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6459{
2d7921c4
AM		 6460 switch (ctxt->opcode_len) {
6461 case 1:
6462 switch (ctxt->b) {
6463 case 0xe4: /* IN */
6464 case 0xe5:
6465 case 0xec:
6466 case 0xed:
6467 case 0xe6: /* OUT */
6468 case 0xe7:
6469 case 0xee:
6470 case 0xef:
6471 case 0x6c: /* INS */
6472 case 0x6d:
6473 case 0x6e: /* OUTS */
6474 case 0x6f:
6475 return true;
6476 }
6477 break;
6478 case 2:
6479 switch (ctxt->b) {
6480 case 0x33: /* RDPMC */
6481 return true;
6482 }
6483 break;
04789b66
LA		 6484 }
6485
6486 return false;
6487}
6488
51d8b661
AP		 6489int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6490 unsigned long cr2,
dc25e89e
AP		 6491 int emulation_type,
6492 void *insn,
6493 int insn_len)
bbd9b64e 6494{
95cb2295 6495 int r;
9d74191a 6496 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6497 bool writeback = true;
93c05d3e 6498 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6499
c595ceee
PB		 6500 vcpu->arch.l1tf_flush_l1d = true;
6501
93c05d3e
XG		 6502 /*
6503 * Clear write_fault_to_shadow_pgtable here to ensure it is
6504 * never reused.
6505 */
6506 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6507 kvm_clear_exception_queue(vcpu);
8d7d8102 6508
571008da 6509 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6510 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6511
6512 /*
6513 * We will reenter on the same instruction since
6514 * we do not set complete_userspace_io. This does not
6515 * handle watchpoints yet, those would be handled in
6516 * the emulate_ops.
6517 */
d391f120
VK		 6518 if (!(emulation_type & EMULTYPE_SKIP) &&
6519 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6520 return r;
6521
9d74191a
TY		 6522 ctxt->interruptibility = 0;
6523 ctxt->have_exception = false;
e0ad0b47 6524 ctxt->exception.vector = -1;
9d74191a 6525 ctxt->perm_ok = false;
bbd9b64e 6526
b51e974f 6527 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6528
9d74191a 6529 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6530
e46479f8 6531 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6532 ++vcpu->stat.insn_emulation;
1d2887e2 6533 if (r != EMULATION_OK) {
4005996e
AK		 6534 if (emulation_type & EMULTYPE_TRAP_UD)
6535 return EMULATE_FAIL;
991eebf9
GN		 6536 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6537 emulation_type))
bbd9b64e 6538 return EMULATE_DONE;
6ea6e843
PB		 6539 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6540 return EMULATE_DONE;
6d77dbfc
GN		 6541 if (emulation_type & EMULTYPE_SKIP)
6542 return EMULATE_FAIL;
e2366171 6543 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6544 }
6545 }
6546
04789b66
LA		 6547 if ((emulation_type & EMULTYPE_VMWARE) &&
6548 !is_vmware_backdoor_opcode(ctxt))
6549 return EMULATE_FAIL;
6550
ba8afb6b 6551 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6552 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6553 if (ctxt->eflags & X86_EFLAGS_RF)
6554 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
97413d29 6555 kvm_x86_ops->set_interrupt_shadow(vcpu, 0);
ba8afb6b
GN		 6556 return EMULATE_DONE;
6557 }
6558
1cb3f3ae
XG		 6559 if (retry_instruction(ctxt, cr2, emulation_type))
6560 return EMULATE_DONE;
6561
7ae441ea 6562 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6563 changes registers values during IO operation */
7ae441ea
GN		 6564 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6565 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6566 emulator_invalidate_register_cache(ctxt);
7ae441ea 6567 }
4d2179e1 6568
5cd21917 6569restart:
0f89b207
TL		 6570 /* Save the faulting GPA (cr2) in the address field */
6571 ctxt->exception.address = cr2;
6572
9d74191a 6573 r = x86_emulate_insn(ctxt);
bbd9b64e 6574
775fde86
JR		 6575 if (r == EMULATION_INTERCEPTED)
6576 return EMULATE_DONE;
6577
d2ddd1c4 6578 if (r == EMULATION_FAILED) {
991eebf9
GN		 6579 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6580 emulation_type))
c3cd7ffa
GN		 6581 return EMULATE_DONE;
6582
e2366171 6583 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6584 }
6585
9d74191a 6586 if (ctxt->have_exception) {
d2ddd1c4 6587 r = EMULATE_DONE;
ef54bcfe
PB		 6588 if (inject_emulated_exception(vcpu))
6589 return r;
d2ddd1c4 6590 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6591 if (!vcpu->arch.pio.in) {
6592 /* FIXME: return into emulator if single-stepping. */
3457e419 6593 vcpu->arch.pio.count = 0;
0912c977 6594 } else {
7ae441ea 6595 writeback = false;
716d51ab
GN		 6596 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6597 }
ac0a48c3 6598 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6599 } else if (vcpu->mmio_needed) {
6600 if (!vcpu->mmio_is_write)
6601 writeback = false;
ac0a48c3 6602 r = EMULATE_USER_EXIT;
716d51ab 6603 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6604 } else if (r == EMULATION_RESTART)
5cd21917 6605 goto restart;
d2ddd1c4
GN		 6606 else
6607 r = EMULATE_DONE;
f850e2e6 6608
7ae441ea 6609 if (writeback) {
6addfc42 6610 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6611 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6612 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6613 kvm_rip_write(vcpu, ctxt->eip);
5cc244a2 6614 if (r == EMULATE_DONE && ctxt->tf)
c8401dda 6615 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6616 if (!ctxt->have_exception ||
6617 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6618 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6619
6620 /*
6621 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6622 * do nothing, and it will be requested again as soon as
6623 * the shadow expires. But we still need to check here,
6624 * because POPF has no interrupt shadow.
6625 */
6626 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6627 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6628 } else
6629 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6630
6631 return r;
de7d789a 6632}
c60658d1
SC		 6633
6634int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6635{
6636 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6637}
6638EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6639
6640int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6641 void *insn, int insn_len)
6642{
6643 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6644}
6645EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6646
8764ed55
SC		 6647static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6648{
6649 vcpu->arch.pio.count = 0;
6650 return 1;
6651}
6652
45def77e
SC		 6653static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6654{
6655 vcpu->arch.pio.count = 0;
6656
6657 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6658 return 1;
6659
6660 return kvm_skip_emulated_instruction(vcpu);
6661}
6662
dca7f128
SC		 6663static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6664 unsigned short port)
de7d789a 6665{
de3cd117 6666 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6667 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6668 size, port, &val, 1);
8764ed55
SC		 6669 if (ret)
6670 return ret;
45def77e 6671
8764ed55
SC		 6672 /*
6673 * Workaround userspace that relies on old KVM behavior of %rip being
6674 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6675 */
6676 if (port == 0x7e &&
6677 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6678 vcpu->arch.complete_userspace_io =
6679 complete_fast_pio_out_port_0x7e;
6680 kvm_skip_emulated_instruction(vcpu);
6681 } else {
45def77e
SC		 6682 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6683 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6684 }
8764ed55 6685 return 0;
de7d789a 6686}
de7d789a 6687
8370c3d0
TL		 6688static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6689{
6690 unsigned long val;
6691
6692 /* We should only ever be called with arch.pio.count equal to 1 */
6693 BUG_ON(vcpu->arch.pio.count != 1);
6694
45def77e
SC		 6695 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6696 vcpu->arch.pio.count = 0;
6697 return 1;
6698 }
6699
8370c3d0 6700 /* For size less than 4 we merge, else we zero extend */
de3cd117 6701 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6702
6703 /*
6704 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6705 * the copy and tracing
6706 */
6707 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6708 vcpu->arch.pio.port, &val, 1);
de3cd117 6709 kvm_rax_write(vcpu, val);
8370c3d0 6710
45def77e 6711 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6712}
6713
dca7f128
SC		 6714static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6715 unsigned short port)
8370c3d0
TL		 6716{
6717 unsigned long val;
6718 int ret;
6719
6720 /* For size less than 4 we merge, else we zero extend */
de3cd117 6721 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6722
6723 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6724 &val, 1);
6725 if (ret) {
de3cd117 6726 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6727 return ret;
6728 }
6729
45def77e 6730 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6731 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6732
6733 return 0;
6734}
dca7f128
SC		 6735
6736int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6737{
45def77e 6738 int ret;
dca7f128 6739
dca7f128 6740 if (in)
45def77e 6741 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6742 else
45def77e
SC		 6743 ret = kvm_fast_pio_out(vcpu, size, port);
6744 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6745}
6746EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6747
251a5fd6 6748static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6749{
0a3aee0d 6750 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6751 return 0;
8cfdc000
ZA		 6752}
6753
6754static void tsc_khz_changed(void *data)
c8076604 6755{
8cfdc000
ZA		 6756 struct cpufreq_freqs *freq = data;
6757 unsigned long khz = 0;
6758
6759 if (data)
6760 khz = freq->new;
6761 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6762 khz = cpufreq_quick_get(raw_smp_processor_id());
6763 if (!khz)
6764 khz = tsc_khz;
0a3aee0d 6765 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6766}
6767
5fa4ec9c 6768#ifdef CONFIG_X86_64
0092e434
VK		 6769static void kvm_hyperv_tsc_notifier(void)
6770{
0092e434
VK		 6771 struct kvm *kvm;
6772 struct kvm_vcpu *vcpu;
6773 int cpu;
6774
0d9ce162 6775 mutex_lock(&kvm_lock);
0092e434
VK		 6776 list_for_each_entry(kvm, &vm_list, vm_list)
6777 kvm_make_mclock_inprogress_request(kvm);
6778
6779 hyperv_stop_tsc_emulation();
6780
6781 /* TSC frequency always matches when on Hyper-V */
6782 for_each_present_cpu(cpu)
6783 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6784 kvm_max_guest_tsc_khz = tsc_khz;
6785
6786 list_for_each_entry(kvm, &vm_list, vm_list) {
6787 struct kvm_arch *ka = &kvm->arch;
6788
6789 spin_lock(&ka->pvclock_gtod_sync_lock);
6790
6791 pvclock_update_vm_gtod_copy(kvm);
6792
6793 kvm_for_each_vcpu(cpu, vcpu, kvm)
6794 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6795
6796 kvm_for_each_vcpu(cpu, vcpu, kvm)
6797 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6798
6799 spin_unlock(&ka->pvclock_gtod_sync_lock);
6800 }
0d9ce162 6801 mutex_unlock(&kvm_lock);
0092e434 6802}
5fa4ec9c 6803#endif
0092e434 6804
df24014a 6805static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 6806{
c8076604
GH		 6807 struct kvm *kvm;
6808 struct kvm_vcpu *vcpu;
6809 int i, send_ipi = 0;
6810
8cfdc000
ZA		 6811 /*
6812 * We allow guests to temporarily run on slowing clocks,
6813 * provided we notify them after, or to run on accelerating
6814 * clocks, provided we notify them before. Thus time never
6815 * goes backwards.
6816 *
6817 * However, we have a problem. We can't atomically update
6818 * the frequency of a given CPU from this function; it is
6819 * merely a notifier, which can be called from any CPU.
6820 * Changing the TSC frequency at arbitrary points in time
6821 * requires a recomputation of local variables related to
6822 * the TSC for each VCPU. We must flag these local variables
6823 * to be updated and be sure the update takes place with the
6824 * new frequency before any guests proceed.
6825 *
6826 * Unfortunately, the combination of hotplug CPU and frequency
6827 * change creates an intractable locking scenario; the order
6828 * of when these callouts happen is undefined with respect to
6829 * CPU hotplug, and they can race with each other. As such,
6830 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6831 * undefined; you can actually have a CPU frequency change take
6832 * place in between the computation of X and the setting of the
6833 * variable. To protect against this problem, all updates of
6834 * the per_cpu tsc_khz variable are done in an interrupt
6835 * protected IPI, and all callers wishing to update the value
6836 * must wait for a synchronous IPI to complete (which is trivial
6837 * if the caller is on the CPU already). This establishes the
6838 * necessary total order on variable updates.
6839 *
6840 * Note that because a guest time update may take place
6841 * anytime after the setting of the VCPU's request bit, the
6842 * correct TSC value must be set before the request. However,
6843 * to ensure the update actually makes it to any guest which
6844 * starts running in hardware virtualization between the set
6845 * and the acquisition of the spinlock, we must also ping the
6846 * CPU after setting the request bit.
6847 *
6848 */
6849
df24014a 6850 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6851
0d9ce162 6852 mutex_lock(&kvm_lock);
c8076604 6853 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6854 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 6855 if (vcpu->cpu != cpu)
c8076604 6856 continue;
c285545f 6857 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 6858 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 6859 send_ipi = 1;
c8076604
GH		 6860 }
6861 }
0d9ce162 6862 mutex_unlock(&kvm_lock);
c8076604
GH		 6863
6864 if (freq->old < freq->new && send_ipi) {
6865 /*
6866 * We upscale the frequency. Must make the guest
6867 * doesn't see old kvmclock values while running with
6868 * the new frequency, otherwise we risk the guest sees
6869 * time go backwards.
6870 *
6871 * In case we update the frequency for another cpu
6872 * (which might be in guest context) send an interrupt
6873 * to kick the cpu out of guest context. Next time
6874 * guest context is entered kvmclock will be updated,
6875 * so the guest will not see stale values.
6876 */
df24014a 6877 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6878 }
df24014a
VK		 6879}
6880
6881static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6882 void *data)
6883{
6884 struct cpufreq_freqs *freq = data;
6885 int cpu;
6886
6887 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6888 return 0;
6889 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6890 return 0;
6891
6892 for_each_cpu(cpu, freq->policy->cpus)
6893 __kvmclock_cpufreq_notifier(freq, cpu);
6894
c8076604
GH		 6895 return 0;
6896}
6897
6898static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6899 .notifier_call = kvmclock_cpufreq_notifier
6900};
6901
251a5fd6 6902static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6903{
251a5fd6
SAS		 6904 tsc_khz_changed(NULL);
6905 return 0;
8cfdc000
ZA		 6906}
6907
b820cc0c
ZA		 6908static void kvm_timer_init(void)
6909{
c285545f 6910 max_tsc_khz = tsc_khz;
460dd42e 6911
b820cc0c 6912 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6913#ifdef CONFIG_CPU_FREQ
6914 struct cpufreq_policy policy;
758f588d
BP		 6915 int cpu;
6916
c285545f 6917 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6918 cpu = get_cpu();
6919 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6920 if (policy.cpuinfo.max_freq)
6921 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6922 put_cpu();
c285545f 6923#endif
b820cc0c
ZA		 6924 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6925 CPUFREQ_TRANSITION_NOTIFIER);
6926 }
460dd42e 6927
73c1b41e 6928 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6929 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6930}
6931
dd60d217
AK		 6932DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6933EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6934
f5132b01 6935int kvm_is_in_guest(void)
ff9d07a0 6936{
086c9855 6937 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6938}
6939
6940static int kvm_is_user_mode(void)
6941{
6942 int user_mode = 3;
dcf46b94 6943
086c9855
AS		 6944 if (__this_cpu_read(current_vcpu))
6945 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6946
ff9d07a0
ZY		 6947 return user_mode != 0;
6948}
6949
6950static unsigned long kvm_get_guest_ip(void)
6951{
6952 unsigned long ip = 0;
dcf46b94 6953
086c9855
AS		 6954 if (__this_cpu_read(current_vcpu))
6955 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6956
ff9d07a0
ZY		 6957 return ip;
6958}
6959
8479e04e
LK		 6960static void kvm_handle_intel_pt_intr(void)
6961{
6962 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6963
6964 kvm_make_request(KVM_REQ_PMI, vcpu);
6965 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6966 (unsigned long *)&vcpu->arch.pmu.global_status);
6967}
6968
ff9d07a0
ZY		 6969static struct perf_guest_info_callbacks kvm_guest_cbs = {
6970 .is_in_guest = kvm_is_in_guest,
6971 .is_user_mode = kvm_is_user_mode,
6972 .get_guest_ip = kvm_get_guest_ip,
8479e04e 6973 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 6974};
6975
16e8d74d
MT		 6976#ifdef CONFIG_X86_64
6977static void pvclock_gtod_update_fn(struct work_struct *work)
6978{
d828199e
MT		 6979 struct kvm *kvm;
6980
6981 struct kvm_vcpu *vcpu;
6982 int i;
6983
0d9ce162 6984 mutex_lock(&kvm_lock);
d828199e
MT		 6985 list_for_each_entry(kvm, &vm_list, vm_list)
6986 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6987 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6988 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 6989 mutex_unlock(&kvm_lock);
16e8d74d
MT		 6990}
6991
6992static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6993
6994/*
6995 * Notification about pvclock gtod data update.
6996 */
6997static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6998 void *priv)
6999{
7000 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7001 struct timekeeper *tk = priv;
7002
7003 update_pvclock_gtod(tk);
7004
7005 /* disable master clock if host does not trust, or does not
b0c39dc6 7006 * use, TSC based clocksource.
16e8d74d 7007 */
b0c39dc6 7008 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 7009 atomic_read(&kvm_guest_has_master_clock) != 0)
7010 queue_work(system_long_wq, &pvclock_gtod_work);
7011
7012 return 0;
7013}
7014
7015static struct notifier_block pvclock_gtod_notifier = {
7016 .notifier_call = pvclock_gtod_notify,
7017};
7018#endif
7019
f8c16bba 7020int kvm_arch_init(void *opaque)
043405e1 7021{
b820cc0c 7022 int r;
6b61edf7 7023 struct kvm_x86_ops *ops = opaque;
f8c16bba 7024
f8c16bba
ZX		 7025 if (kvm_x86_ops) {
7026 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7027 r = -EEXIST;
7028 goto out;
f8c16bba
ZX		 7029 }
7030
7031 if (!ops->cpu_has_kvm_support()) {
7032 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7033 r = -EOPNOTSUPP;
7034 goto out;
f8c16bba
ZX		 7035 }
7036 if (ops->disabled_by_bios()) {
7037 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7038 r = -EOPNOTSUPP;
7039 goto out;
f8c16bba
ZX		 7040 }
7041
b666a4b6
MO		 7042 /*
7043 * KVM explicitly assumes that the guest has an FPU and
7044 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7045 * vCPU's FPU state as a fxregs_state struct.
7046 */
7047 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7048 printk(KERN_ERR "kvm: inadequate fpu\n");
7049 r = -EOPNOTSUPP;
7050 goto out;
7051 }
7052
013f6a5d 7053 r = -ENOMEM;
ed8e4812 7054 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7055 __alignof__(struct fpu), SLAB_ACCOUNT,
7056 NULL);
7057 if (!x86_fpu_cache) {
7058 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7059 goto out;
7060 }
7061
013f6a5d
MT		 7062 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7063 if (!shared_msrs) {
7064 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7065 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7066 }
7067
97db56ce
AK		 7068 r = kvm_mmu_module_init();
7069 if (r)
013f6a5d 7070 goto out_free_percpu;
97db56ce 7071
f8c16bba 7072 kvm_x86_ops = ops;
920c8377 7073
7b52345e 7074 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7075 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7076 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7077 kvm_timer_init();
c8076604 7078
ff9d07a0
ZY		 7079 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7080
d366bf7e 7081 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7082 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7083
c5cc421b 7084 kvm_lapic_init();
0c5f81da
WL		 7085 if (pi_inject_timer == -1)
7086 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
16e8d74d
MT		 7087#ifdef CONFIG_X86_64
7088 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7089
5fa4ec9c 7090 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7091 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7092#endif
7093
f8c16bba 7094 return 0;
56c6d28a 7095
013f6a5d
MT		 7096out_free_percpu:
7097 free_percpu(shared_msrs);
b666a4b6
MO		 7098out_free_x86_fpu_cache:
7099 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7100out:
56c6d28a 7101 return r;
043405e1 7102}
8776e519 7103
f8c16bba
ZX		 7104void kvm_arch_exit(void)
7105{
0092e434 7106#ifdef CONFIG_X86_64
5fa4ec9c 7107 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7108 clear_hv_tscchange_cb();
7109#endif
cef84c30 7110 kvm_lapic_exit();
ff9d07a0
ZY		 7111 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7112
888d256e
JK		 7113 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7114 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7115 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7116 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7117#ifdef CONFIG_X86_64
7118 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7119#endif
f8c16bba 7120 kvm_x86_ops = NULL;
56c6d28a 7121 kvm_mmu_module_exit();
013f6a5d 7122 free_percpu(shared_msrs);
b666a4b6 7123 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7124}
f8c16bba 7125
5cb56059 7126int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7127{
7128 ++vcpu->stat.halt_exits;
35754c98 7129 if (lapic_in_kernel(vcpu)) {
a4535290 7130 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7131 return 1;
7132 } else {
7133 vcpu->run->exit_reason = KVM_EXIT_HLT;
7134 return 0;
7135 }
7136}
5cb56059
JS		 7137EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7138
7139int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7140{
6affcbed
KH		 7141 int ret = kvm_skip_emulated_instruction(vcpu);
7142 /*
7143 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7144 * KVM_EXIT_DEBUG here.
7145 */
7146 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7147}
8776e519
HB		 7148EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7149
8ef81a9a 7150#ifdef CONFIG_X86_64
55dd00a7
MT		 7151static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7152 unsigned long clock_type)
7153{
7154 struct kvm_clock_pairing clock_pairing;
899a31f5 7155 struct timespec64 ts;
80fbd89c 7156 u64 cycle;
55dd00a7
MT		 7157 int ret;
7158
7159 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7160 return -KVM_EOPNOTSUPP;
7161
7162 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7163 return -KVM_EOPNOTSUPP;
7164
7165 clock_pairing.sec = ts.tv_sec;
7166 clock_pairing.nsec = ts.tv_nsec;
7167 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7168 clock_pairing.flags = 0;
bcbfbd8e 7169 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7170
7171 ret = 0;
7172 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7173 sizeof(struct kvm_clock_pairing)))
7174 ret = -KVM_EFAULT;
7175
7176 return ret;
7177}
8ef81a9a 7178#endif
55dd00a7 7179
6aef266c
SV		 7180/*
7181 * kvm_pv_kick_cpu_op: Kick a vcpu.
7182 *
7183 * @apicid - apicid of vcpu to be kicked.
7184 */
7185static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7186{
24d2166b 7187 struct kvm_lapic_irq lapic_irq;
6aef266c 7188
24d2166b
R		 7189 lapic_irq.shorthand = 0;
7190 lapic_irq.dest_mode = 0;
ebd28fcb 7191 lapic_irq.level = 0;
24d2166b 7192 lapic_irq.dest_id = apicid;
93bbf0b8 7193 lapic_irq.msi_redir_hint = false;
6aef266c 7194
24d2166b 7195 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7196 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7197}
7198
d62caabb
AS		 7199void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7200{
f7589cca
PB		 7201 if (!lapic_in_kernel(vcpu)) {
7202 WARN_ON_ONCE(vcpu->arch.apicv_active);
7203 return;
7204 }
7205 if (!vcpu->arch.apicv_active)
7206 return;
7207
d62caabb
AS		 7208 vcpu->arch.apicv_active = false;
7209 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7210}
7211
71506297
WL		 7212static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7213{
7214 struct kvm_vcpu *target = NULL;
7215 struct kvm_apic_map *map;
7216
7217 rcu_read_lock();
7218 map = rcu_dereference(kvm->arch.apic_map);
7219
7220 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7221 target = map->phys_map[dest_id]->vcpu;
7222
7223 rcu_read_unlock();
7224
266e85a5 7225 if (target && READ_ONCE(target->ready))
71506297
WL		 7226 kvm_vcpu_yield_to(target);
7227}
7228
8776e519
HB		 7229int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7230{
7231 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7232 int op_64_bit;
8776e519 7233
696ca779
RK		 7234 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7235 return kvm_hv_hypercall(vcpu);
55cd8e5a 7236
de3cd117
SC		 7237 nr = kvm_rax_read(vcpu);
7238 a0 = kvm_rbx_read(vcpu);
7239 a1 = kvm_rcx_read(vcpu);
7240 a2 = kvm_rdx_read(vcpu);
7241 a3 = kvm_rsi_read(vcpu);
8776e519 7242
229456fc 7243 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7244
a449c7aa
NA		 7245 op_64_bit = is_64_bit_mode(vcpu);
7246 if (!op_64_bit) {
8776e519
HB		 7247 nr &= 0xFFFFFFFF;
7248 a0 &= 0xFFFFFFFF;
7249 a1 &= 0xFFFFFFFF;
7250 a2 &= 0xFFFFFFFF;
7251 a3 &= 0xFFFFFFFF;
7252 }
7253
07708c4a
JK		 7254 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7255 ret = -KVM_EPERM;
696ca779 7256 goto out;
07708c4a
JK		 7257 }
7258
8776e519 7259 switch (nr) {
b93463aa
AK		 7260 case KVM_HC_VAPIC_POLL_IRQ:
7261 ret = 0;
7262 break;
6aef266c
SV		 7263 case KVM_HC_KICK_CPU:
7264 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
266e85a5 7265 kvm_sched_yield(vcpu->kvm, a1);
6aef266c
SV		 7266 ret = 0;
7267 break;
8ef81a9a 7268#ifdef CONFIG_X86_64
55dd00a7
MT		 7269 case KVM_HC_CLOCK_PAIRING:
7270 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7271 break;
1ed199a4 7272#endif
4180bf1b
WL		 7273 case KVM_HC_SEND_IPI:
7274 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7275 break;
71506297
WL		 7276 case KVM_HC_SCHED_YIELD:
7277 kvm_sched_yield(vcpu->kvm, a0);
7278 ret = 0;
7279 break;
8776e519
HB		 7280 default:
7281 ret = -KVM_ENOSYS;
7282 break;
7283 }
696ca779 7284out:
a449c7aa
NA		 7285 if (!op_64_bit)
7286 ret = (u32)ret;
de3cd117 7287 kvm_rax_write(vcpu, ret);
6356ee0c 7288
f11c3a8d 7289 ++vcpu->stat.hypercalls;
6356ee0c 7290 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7291}
7292EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7293
b6785def 7294static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7295{
d6aa1000 7296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7297 char instruction[3];
5fdbf976 7298 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7299
8776e519 7300 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7301
ce2e852e
DV		 7302 return emulator_write_emulated(ctxt, rip, instruction, 3,
7303 &ctxt->exception);
8776e519
HB		 7304}
7305
851ba692 7306static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7307{
782d422b
MG		 7308 return vcpu->run->request_interrupt_window &&
7309 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7310}
7311
851ba692 7312static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7313{
851ba692
AK		 7314 struct kvm_run *kvm_run = vcpu->run;
7315
91586a3b 7316 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7317 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7318 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7319 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7320 kvm_run->ready_for_interrupt_injection =
7321 pic_in_kernel(vcpu->kvm) ||
782d422b 7322 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7323}
7324
95ba8273
GN		 7325static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7326{
7327 int max_irr, tpr;
7328
7329 if (!kvm_x86_ops->update_cr8_intercept)
7330 return;
7331
bce87cce 7332 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7333 return;
7334
d62caabb
AS		 7335 if (vcpu->arch.apicv_active)
7336 return;
7337
8db3baa2
GN		 7338 if (!vcpu->arch.apic->vapic_addr)
7339 max_irr = kvm_lapic_find_highest_irr(vcpu);
7340 else
7341 max_irr = -1;
95ba8273
GN		 7342
7343 if (max_irr != -1)
7344 max_irr >>= 4;
7345
7346 tpr = kvm_lapic_get_cr8(vcpu);
7347
7348 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7349}
7350
b6b8a145 7351static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7352{
b6b8a145
JK		 7353 int r;
7354
95ba8273 7355 /* try to reinject previous events if any */
664f8e26 7356
1a680e35
LA		 7357 if (vcpu->arch.exception.injected)
7358 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7359 /*
a042c26f
LA		 7360 * Do not inject an NMI or interrupt if there is a pending
7361 * exception. Exceptions and interrupts are recognized at
7362 * instruction boundaries, i.e. the start of an instruction.
7363 * Trap-like exceptions, e.g. #DB, have higher priority than
7364 * NMIs and interrupts, i.e. traps are recognized before an
7365 * NMI/interrupt that's pending on the same instruction.
7366 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7367 * priority, but are only generated (pended) during instruction
7368 * execution, i.e. a pending fault-like exception means the
7369 * fault occurred on the *previous* instruction and must be
7370 * serviced prior to recognizing any new events in order to
7371 * fully complete the previous instruction.
664f8e26 7372 */
1a680e35
LA		 7373 else if (!vcpu->arch.exception.pending) {
7374 if (vcpu->arch.nmi_injected)
664f8e26 7375 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7376 else if (vcpu->arch.interrupt.injected)
664f8e26 7377 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7378 }
7379
1a680e35
LA		 7380 /*
7381 * Call check_nested_events() even if we reinjected a previous event
7382 * in order for caller to determine if it should require immediate-exit
7383 * from L2 to L1 due to pending L1 events which require exit
7384 * from L2 to L1.
7385 */
664f8e26
WL		 7386 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7387 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7388 if (r != 0)
7389 return r;
7390 }
7391
7392 /* try to inject new event if pending */
b59bb7bd 7393 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7394 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7395 vcpu->arch.exception.has_error_code,
7396 vcpu->arch.exception.error_code);
d6e8c854 7397
1a680e35 7398 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7399 vcpu->arch.exception.pending = false;
7400 vcpu->arch.exception.injected = true;
7401
d6e8c854
NA		 7402 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7403 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7404 X86_EFLAGS_RF);
7405
f10c729f
JM		 7406 if (vcpu->arch.exception.nr == DB_VECTOR) {
7407 /*
7408 * This code assumes that nSVM doesn't use
7409 * check_nested_events(). If it does, the
7410 * DR6/DR7 changes should happen before L1
7411 * gets a #VMEXIT for an intercepted #DB in
7412 * L2. (Under VMX, on the other hand, the
7413 * DR6/DR7 changes should not happen in the
7414 * event of a VM-exit to L1 for an intercepted
7415 * #DB in L2.)
7416 */
7417 kvm_deliver_exception_payload(vcpu);
7418 if (vcpu->arch.dr7 & DR7_GD) {
7419 vcpu->arch.dr7 &= ~DR7_GD;
7420 kvm_update_dr7(vcpu);
7421 }
6bdf0662
NA		 7422 }
7423
cfcd20e5 7424 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7425 }
7426
7427 /* Don't consider new event if we re-injected an event */
7428 if (kvm_event_needs_reinjection(vcpu))
7429 return 0;
7430
7431 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7432 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7433 vcpu->arch.smi_pending = false;
52797bf9 7434 ++vcpu->arch.smi_count;
ee2cd4b7 7435 enter_smm(vcpu);
c43203ca 7436 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7437 --vcpu->arch.nmi_pending;
7438 vcpu->arch.nmi_injected = true;
7439 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7440 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7441 /*
7442 * Because interrupts can be injected asynchronously, we are
7443 * calling check_nested_events again here to avoid a race condition.
7444 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7445 * proposal and current concerns. Perhaps we should be setting
7446 * KVM_REQ_EVENT only on certain events and not unconditionally?
7447 */
7448 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7449 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7450 if (r != 0)
7451 return r;
7452 }
95ba8273 7453 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7454 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7455 false);
7456 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7457 }
7458 }
ee2cd4b7 7459
b6b8a145 7460 return 0;
95ba8273
GN		 7461}
7462
7460fb4a
AK		 7463static void process_nmi(struct kvm_vcpu *vcpu)
7464{
7465 unsigned limit = 2;
7466
7467 /*
7468 * x86 is limited to one NMI running, and one NMI pending after it.
7469 * If an NMI is already in progress, limit further NMIs to just one.
7470 * Otherwise, allow two (and we'll inject the first one immediately).
7471 */
7472 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7473 limit = 1;
7474
7475 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7476 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7477 kvm_make_request(KVM_REQ_EVENT, vcpu);
7478}
7479
ee2cd4b7 7480static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7481{
7482 u32 flags = 0;
7483 flags |= seg->g << 23;
7484 flags |= seg->db << 22;
7485 flags |= seg->l << 21;
7486 flags |= seg->avl << 20;
7487 flags |= seg->present << 15;
7488 flags |= seg->dpl << 13;
7489 flags |= seg->s << 12;
7490 flags |= seg->type << 8;
7491 return flags;
7492}
7493
ee2cd4b7 7494static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7495{
7496 struct kvm_segment seg;
7497 int offset;
7498
7499 kvm_get_segment(vcpu, &seg, n);
7500 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7501
7502 if (n < 3)
7503 offset = 0x7f84 + n * 12;
7504 else
7505 offset = 0x7f2c + (n - 3) * 12;
7506
7507 put_smstate(u32, buf, offset + 8, seg.base);
7508 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7509 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7510}
7511
efbb288a 7512#ifdef CONFIG_X86_64
ee2cd4b7 7513static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7514{
7515 struct kvm_segment seg;
7516 int offset;
7517 u16 flags;
7518
7519 kvm_get_segment(vcpu, &seg, n);
7520 offset = 0x7e00 + n * 16;
7521
ee2cd4b7 7522 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7523 put_smstate(u16, buf, offset, seg.selector);
7524 put_smstate(u16, buf, offset + 2, flags);
7525 put_smstate(u32, buf, offset + 4, seg.limit);
7526 put_smstate(u64, buf, offset + 8, seg.base);
7527}
efbb288a 7528#endif
660a5d51 7529
ee2cd4b7 7530static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7531{
7532 struct desc_ptr dt;
7533 struct kvm_segment seg;
7534 unsigned long val;
7535 int i;
7536
7537 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7538 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7539 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7540 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7541
7542 for (i = 0; i < 8; i++)
7543 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7544
7545 kvm_get_dr(vcpu, 6, &val);
7546 put_smstate(u32, buf, 0x7fcc, (u32)val);
7547 kvm_get_dr(vcpu, 7, &val);
7548 put_smstate(u32, buf, 0x7fc8, (u32)val);
7549
7550 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7551 put_smstate(u32, buf, 0x7fc4, seg.selector);
7552 put_smstate(u32, buf, 0x7f64, seg.base);
7553 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7554 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7555
7556 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7557 put_smstate(u32, buf, 0x7fc0, seg.selector);
7558 put_smstate(u32, buf, 0x7f80, seg.base);
7559 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7560 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7561
7562 kvm_x86_ops->get_gdt(vcpu, &dt);
7563 put_smstate(u32, buf, 0x7f74, dt.address);
7564 put_smstate(u32, buf, 0x7f70, dt.size);
7565
7566 kvm_x86_ops->get_idt(vcpu, &dt);
7567 put_smstate(u32, buf, 0x7f58, dt.address);
7568 put_smstate(u32, buf, 0x7f54, dt.size);
7569
7570 for (i = 0; i < 6; i++)
ee2cd4b7 7571 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7572
7573 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7574
7575 /* revision id */
7576 put_smstate(u32, buf, 0x7efc, 0x00020000);
7577 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7578}
7579
b68f3cc7 7580#ifdef CONFIG_X86_64
ee2cd4b7 7581static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7582{
660a5d51
PB		 7583 struct desc_ptr dt;
7584 struct kvm_segment seg;
7585 unsigned long val;
7586 int i;
7587
7588 for (i = 0; i < 16; i++)
7589 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7590
7591 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7592 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7593
7594 kvm_get_dr(vcpu, 6, &val);
7595 put_smstate(u64, buf, 0x7f68, val);
7596 kvm_get_dr(vcpu, 7, &val);
7597 put_smstate(u64, buf, 0x7f60, val);
7598
7599 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7600 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7601 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7602
7603 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7604
7605 /* revision id */
7606 put_smstate(u32, buf, 0x7efc, 0x00020064);
7607
7608 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7609
7610 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7611 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7612 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7613 put_smstate(u32, buf, 0x7e94, seg.limit);
7614 put_smstate(u64, buf, 0x7e98, seg.base);
7615
7616 kvm_x86_ops->get_idt(vcpu, &dt);
7617 put_smstate(u32, buf, 0x7e84, dt.size);
7618 put_smstate(u64, buf, 0x7e88, dt.address);
7619
7620 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7621 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7622 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7623 put_smstate(u32, buf, 0x7e74, seg.limit);
7624 put_smstate(u64, buf, 0x7e78, seg.base);
7625
7626 kvm_x86_ops->get_gdt(vcpu, &dt);
7627 put_smstate(u32, buf, 0x7e64, dt.size);
7628 put_smstate(u64, buf, 0x7e68, dt.address);
7629
7630 for (i = 0; i < 6; i++)
ee2cd4b7 7631 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7632}
b68f3cc7 7633#endif
660a5d51 7634
ee2cd4b7 7635static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7636{
660a5d51 7637 struct kvm_segment cs, ds;
18c3626e 7638 struct desc_ptr dt;
660a5d51
PB		 7639 char buf[512];
7640 u32 cr0;
7641
660a5d51 7642 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7643 memset(buf, 0, 512);
b68f3cc7 7644#ifdef CONFIG_X86_64
d6321d49 7645 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7646 enter_smm_save_state_64(vcpu, buf);
660a5d51 7647 else
b68f3cc7 7648#endif
ee2cd4b7 7649 enter_smm_save_state_32(vcpu, buf);
660a5d51 7650
0234bf88
LP		 7651 /*
7652 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7653 * vCPU state (e.g. leave guest mode) after we've saved the state into
7654 * the SMM state-save area.
7655 */
7656 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7657
7658 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7659 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7660
7661 if (kvm_x86_ops->get_nmi_mask(vcpu))
7662 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7663 else
7664 kvm_x86_ops->set_nmi_mask(vcpu, true);
7665
7666 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7667 kvm_rip_write(vcpu, 0x8000);
7668
7669 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7670 kvm_x86_ops->set_cr0(vcpu, cr0);
7671 vcpu->arch.cr0 = cr0;
7672
7673 kvm_x86_ops->set_cr4(vcpu, 0);
7674
18c3626e
PB		 7675 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7676 dt.address = dt.size = 0;
7677 kvm_x86_ops->set_idt(vcpu, &dt);
7678
660a5d51
PB		 7679 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7680
7681 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7682 cs.base = vcpu->arch.smbase;
7683
7684 ds.selector = 0;
7685 ds.base = 0;
7686
7687 cs.limit = ds.limit = 0xffffffff;
7688 cs.type = ds.type = 0x3;
7689 cs.dpl = ds.dpl = 0;
7690 cs.db = ds.db = 0;
7691 cs.s = ds.s = 1;
7692 cs.l = ds.l = 0;
7693 cs.g = ds.g = 1;
7694 cs.avl = ds.avl = 0;
7695 cs.present = ds.present = 1;
7696 cs.unusable = ds.unusable = 0;
7697 cs.padding = ds.padding = 0;
7698
7699 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7700 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7701 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7702 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7703 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7704 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7705
b68f3cc7 7706#ifdef CONFIG_X86_64
d6321d49 7707 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7708 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7709#endif
660a5d51
PB		 7710
7711 kvm_update_cpuid(vcpu);
7712 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7713}
7714
ee2cd4b7 7715static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7716{
7717 vcpu->arch.smi_pending = true;
7718 kvm_make_request(KVM_REQ_EVENT, vcpu);
7719}
7720
2860c4b1
PB		 7721void kvm_make_scan_ioapic_request(struct kvm *kvm)
7722{
7723 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7724}
7725
3d81bc7e 7726static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7727{
dcbd3e49 7728 if (!kvm_apic_present(vcpu))
3d81bc7e 7729 return;
c7c9c56c 7730
6308630b 7731 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7732
b053b2ae 7733 if (irqchip_split(vcpu->kvm))
6308630b 7734 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7735 else {
fa59cc00 7736 if (vcpu->arch.apicv_active)
d62caabb 7737 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7738 if (ioapic_in_kernel(vcpu->kvm))
7739 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7740 }
e40ff1d6
LA		 7741
7742 if (is_guest_mode(vcpu))
7743 vcpu->arch.load_eoi_exitmap_pending = true;
7744 else
7745 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7746}
7747
7748static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7749{
7750 u64 eoi_exit_bitmap[4];
7751
7752 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7753 return;
7754
5c919412
AS		 7755 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7756 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7757 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7758}
7759
93065ac7
MH		 7760int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7761 unsigned long start, unsigned long end,
7762 bool blockable)
b1394e74
RK		 7763{
7764 unsigned long apic_address;
7765
7766 /*
7767 * The physical address of apic access page is stored in the VMCS.
7768 * Update it when it becomes invalid.
7769 */
7770 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7771 if (start <= apic_address && apic_address < end)
7772 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7773
7774 return 0;
b1394e74
RK		 7775}
7776
4256f43f
TC		 7777void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7778{
c24ae0dc
TC		 7779 struct page *page = NULL;
7780
35754c98 7781 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7782 return;
7783
4256f43f
TC		 7784 if (!kvm_x86_ops->set_apic_access_page_addr)
7785 return;
7786
c24ae0dc 7787 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7788 if (is_error_page(page))
7789 return;
c24ae0dc
TC		 7790 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7791
7792 /*
7793 * Do not pin apic access page in memory, the MMU notifier
7794 * will call us again if it is migrated or swapped out.
7795 */
7796 put_page(page);
4256f43f
TC		 7797}
7798EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7799
d264ee0c
SC		 7800void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7801{
7802 smp_send_reschedule(vcpu->cpu);
7803}
7804EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7805
9357d939 7806/*
362c698f 7807 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7808 * exiting to the userspace. Otherwise, the value will be returned to the
7809 * userspace.
7810 */
851ba692 7811static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7812{
7813 int r;
62a193ed
MG		 7814 bool req_int_win =
7815 dm_request_for_irq_injection(vcpu) &&
7816 kvm_cpu_accept_dm_intr(vcpu);
7817
730dca42 7818 bool req_immediate_exit = false;
b6c7a5dc 7819
2fa6e1e1 7820 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7821 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7822 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7823 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7824 kvm_mmu_unload(vcpu);
a8eeb04a 7825 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7826 __kvm_migrate_timers(vcpu);
d828199e
MT		 7827 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7828 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7829 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7830 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7831 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7832 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7833 if (unlikely(r))
7834 goto out;
7835 }
a8eeb04a 7836 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7837 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7838 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7839 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7840 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7841 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7842 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7843 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7844 r = 0;
7845 goto out;
7846 }
a8eeb04a 7847 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7848 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7849 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7850 r = 0;
7851 goto out;
7852 }
af585b92
GN		 7853 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7854 /* Page is swapped out. Do synthetic halt */
7855 vcpu->arch.apf.halted = true;
7856 r = 1;
7857 goto out;
7858 }
c9aaa895
GC		 7859 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7860 record_steal_time(vcpu);
64d60670
PB		 7861 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7862 process_smi(vcpu);
7460fb4a
AK		 7863 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7864 process_nmi(vcpu);
f5132b01 7865 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7866 kvm_pmu_handle_event(vcpu);
f5132b01 7867 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7868 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7869 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7870 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7871 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7872 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7873 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7874 vcpu->run->eoi.vector =
7875 vcpu->arch.pending_ioapic_eoi;
7876 r = 0;
7877 goto out;
7878 }
7879 }
3d81bc7e
YZ		 7880 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7881 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7882 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7883 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7884 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7885 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7886 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7887 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7888 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7889 r = 0;
7890 goto out;
7891 }
e516cebb
AS		 7892 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7893 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7894 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7895 r = 0;
7896 goto out;
7897 }
db397571
AS		 7898 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7899 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7900 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7901 r = 0;
7902 goto out;
7903 }
f3b138c5
AS		 7904
7905 /*
7906 * KVM_REQ_HV_STIMER has to be processed after
7907 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7908 * depend on the guest clock being up-to-date
7909 */
1f4b34f8
AS		 7910 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7911 kvm_hv_process_stimers(vcpu);
2f52d58c 7912 }
b93463aa 7913
b463a6f7 7914 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7915 ++vcpu->stat.req_event;
66450a21
JK		 7916 kvm_apic_accept_events(vcpu);
7917 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7918 r = 1;
7919 goto out;
7920 }
7921
b6b8a145
JK		 7922 if (inject_pending_event(vcpu, req_int_win) != 0)
7923 req_immediate_exit = true;
321c5658 7924 else {
cc3d967f 7925 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7926 *
cc3d967f
LP		 7927 * SMIs have three cases:
7928 * 1) They can be nested, and then there is nothing to
7929 * do here because RSM will cause a vmexit anyway.
7930 * 2) There is an ISA-specific reason why SMI cannot be
7931 * injected, and the moment when this changes can be
7932 * intercepted.
7933 * 3) Or the SMI can be pending because
7934 * inject_pending_event has completed the injection
7935 * of an IRQ or NMI from the previous vmexit, and
7936 * then we request an immediate exit to inject the
7937 * SMI.
c43203ca
PB		 7938 */
7939 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7940 if (!kvm_x86_ops->enable_smi_window(vcpu))
7941 req_immediate_exit = true;
321c5658
YS		 7942 if (vcpu->arch.nmi_pending)
7943 kvm_x86_ops->enable_nmi_window(vcpu);
7944 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7945 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7946 WARN_ON(vcpu->arch.exception.pending);
321c5658 7947 }
b463a6f7
AK		 7948
7949 if (kvm_lapic_enabled(vcpu)) {
7950 update_cr8_intercept(vcpu);
7951 kvm_lapic_sync_to_vapic(vcpu);
7952 }
7953 }
7954
d8368af8
AK		 7955 r = kvm_mmu_reload(vcpu);
7956 if (unlikely(r)) {
d905c069 7957 goto cancel_injection;
d8368af8
AK		 7958 }
7959
b6c7a5dc
HB		 7960 preempt_disable();
7961
7962 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7963
7964 /*
7965 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7966 * IPI are then delayed after guest entry, which ensures that they
7967 * result in virtual interrupt delivery.
7968 */
7969 local_irq_disable();
6b7e2d09
XG		 7970 vcpu->mode = IN_GUEST_MODE;
7971
01b71917
MT		 7972 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7973
0f127d12 7974 /*
b95234c8 7975 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7976 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 7977 *
81b01667 7978 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 7979 * pairs with the memory barrier implicit in pi_test_and_set_on
7980 * (see vmx_deliver_posted_interrupt).
7981 *
7982 * 3) This also orders the write to mode from any reads to the page
7983 * tables done while the VCPU is running. Please see the comment
7984 * in kvm_flush_remote_tlbs.
6b7e2d09 7985 */
01b71917 7986 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7987
b95234c8
PB		 7988 /*
7989 * This handles the case where a posted interrupt was
7990 * notified with kvm_vcpu_kick.
7991 */
fa59cc00
LA		 7992 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7993 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7994
2fa6e1e1 7995 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7996 || need_resched() || signal_pending(current)) {
6b7e2d09 7997 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7998 smp_wmb();
6c142801
AK		 7999 local_irq_enable();
8000 preempt_enable();
01b71917 8001 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 8002 r = 1;
d905c069 8003 goto cancel_injection;
6c142801
AK		 8004 }
8005
c43203ca
PB		 8006 if (req_immediate_exit) {
8007 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 8008 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 8009 }
d6185f20 8010
8b89fe1f 8011 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 8012 guest_enter_irqoff();
b6c7a5dc 8013
e7517324
WL		 8014 /* The preempt notifier should have taken care of the FPU already. */
8015 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
5f409e20 8016
42dbaa5a 8017 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 8018 set_debugreg(0, 7);
8019 set_debugreg(vcpu->arch.eff_db[0], 0);
8020 set_debugreg(vcpu->arch.eff_db[1], 1);
8021 set_debugreg(vcpu->arch.eff_db[2], 2);
8022 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 8023 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 8024 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 8025 }
b6c7a5dc 8026
851ba692 8027 kvm_x86_ops->run(vcpu);
b6c7a5dc 8028
c77fb5fe
PB		 8029 /*
8030 * Do this here before restoring debug registers on the host. And
8031 * since we do this before handling the vmexit, a DR access vmexit
8032 * can (a) read the correct value of the debug registers, (b) set
8033 * KVM_DEBUGREG_WONT_EXIT again.
8034 */
8035 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8036 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8037 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8038 kvm_update_dr0123(vcpu);
8039 kvm_update_dr6(vcpu);
8040 kvm_update_dr7(vcpu);
8041 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8042 }
8043
24f1e32c
FW		 8044 /*
8045 * If the guest has used debug registers, at least dr7
8046 * will be disabled while returning to the host.
8047 * If we don't have active breakpoints in the host, we don't
8048 * care about the messed up debug address registers. But if
8049 * we have some of them active, restore the old state.
8050 */
59d8eb53 8051 if (hw_breakpoint_active())
24f1e32c 8052 hw_breakpoint_restore();
42dbaa5a 8053
4ba76538 8054 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8055
6b7e2d09 8056 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8057 smp_wmb();
a547c6db 8058
95b5a48c 8059 kvm_x86_ops->handle_exit_irqoff(vcpu);
b6c7a5dc 8060
d7a08882
SC		 8061 /*
8062 * Consume any pending interrupts, including the possible source of
8063 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8064 * An instruction is required after local_irq_enable() to fully unblock
8065 * interrupts on processors that implement an interrupt shadow, the
8066 * stat.exits increment will do nicely.
8067 */
8068 kvm_before_interrupt(vcpu);
8069 local_irq_enable();
b6c7a5dc 8070 ++vcpu->stat.exits;
d7a08882
SC		 8071 local_irq_disable();
8072 kvm_after_interrupt(vcpu);
b6c7a5dc 8073
f2485b3e 8074 guest_exit_irqoff();
ec0671d5
WL		 8075 if (lapic_in_kernel(vcpu)) {
8076 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8077 if (delta != S64_MIN) {
8078 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8079 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8080 }
8081 }
b6c7a5dc 8082
f2485b3e 8083 local_irq_enable();
b6c7a5dc
HB		 8084 preempt_enable();
8085
f656ce01 8086 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8087
b6c7a5dc
HB		 8088 /*
8089 * Profile KVM exit RIPs:
8090 */
8091 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8092 unsigned long rip = kvm_rip_read(vcpu);
8093 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8094 }
8095
cc578287
ZA		 8096 if (unlikely(vcpu->arch.tsc_always_catchup))
8097 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8098
5cfb1d5a
MT		 8099 if (vcpu->arch.apic_attention)
8100 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8101
618232e2 8102 vcpu->arch.gpa_available = false;
851ba692 8103 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8104 return r;
8105
8106cancel_injection:
8107 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8108 if (unlikely(vcpu->arch.apic_attention))
8109 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8110out:
8111 return r;
8112}
b6c7a5dc 8113
362c698f
PB		 8114static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8115{
bf9f6ac8
FW		 8116 if (!kvm_arch_vcpu_runnable(vcpu) &&
8117 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8118 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8119 kvm_vcpu_block(vcpu);
8120 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8121
8122 if (kvm_x86_ops->post_block)
8123 kvm_x86_ops->post_block(vcpu);
8124
9c8fd1ba
PB		 8125 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8126 return 1;
8127 }
362c698f
PB		 8128
8129 kvm_apic_accept_events(vcpu);
8130 switch(vcpu->arch.mp_state) {
8131 case KVM_MP_STATE_HALTED:
8132 vcpu->arch.pv.pv_unhalted = false;
8133 vcpu->arch.mp_state =
8134 KVM_MP_STATE_RUNNABLE;
b2869f28 8135 /* fall through */
362c698f
PB		 8136 case KVM_MP_STATE_RUNNABLE:
8137 vcpu->arch.apf.halted = false;
8138 break;
8139 case KVM_MP_STATE_INIT_RECEIVED:
8140 break;
8141 default:
8142 return -EINTR;
8143 break;
8144 }
8145 return 1;
8146}
09cec754 8147
5d9bc648
PB		 8148static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8149{
0ad3bed6
PB		 8150 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8151 kvm_x86_ops->check_nested_events(vcpu, false);
8152
5d9bc648
PB		 8153 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8154 !vcpu->arch.apf.halted);
8155}
8156
362c698f 8157static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8158{
8159 int r;
f656ce01 8160 struct kvm *kvm = vcpu->kvm;
d7690175 8161
f656ce01 8162 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8163 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8164
362c698f 8165 for (;;) {
58f800d5 8166 if (kvm_vcpu_running(vcpu)) {
851ba692 8167 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8168 } else {
362c698f 8169 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8170 }
8171
09cec754
GN		 8172 if (r <= 0)
8173 break;
8174
72875d8a 8175 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8176 if (kvm_cpu_has_pending_timer(vcpu))
8177 kvm_inject_pending_timer_irqs(vcpu);
8178
782d422b
MG		 8179 if (dm_request_for_irq_injection(vcpu) &&
8180 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8181 r = 0;
8182 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8183 ++vcpu->stat.request_irq_exits;
362c698f 8184 break;
09cec754 8185 }
af585b92
GN		 8186
8187 kvm_check_async_pf_completion(vcpu);
8188
09cec754
GN		 8189 if (signal_pending(current)) {
8190 r = -EINTR;
851ba692 8191 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8192 ++vcpu->stat.signal_exits;
362c698f 8193 break;
09cec754
GN		 8194 }
8195 if (need_resched()) {
f656ce01 8196 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8197 cond_resched();
f656ce01 8198 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8199 }
b6c7a5dc
HB		 8200 }
8201
f656ce01 8202 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8203
8204 return r;
8205}
8206
716d51ab
GN		 8207static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8208{
8209 int r;
8210 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8211 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8212 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8213 if (r != EMULATE_DONE)
8214 return 0;
8215 return 1;
8216}
8217
8218static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8219{
8220 BUG_ON(!vcpu->arch.pio.count);
8221
8222 return complete_emulated_io(vcpu);
8223}
8224
f78146b0
AK		 8225/*
8226 * Implements the following, as a state machine:
8227 *
8228 * read:
8229 * for each fragment
87da7e66
XG		 8230 * for each mmio piece in the fragment
8231 * write gpa, len
8232 * exit
8233 * copy data
f78146b0
AK		 8234 * execute insn
8235 *
8236 * write:
8237 * for each fragment
87da7e66
XG		 8238 * for each mmio piece in the fragment
8239 * write gpa, len
8240 * copy data
8241 * exit
f78146b0 8242 */
716d51ab 8243static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8244{
8245 struct kvm_run *run = vcpu->run;
f78146b0 8246 struct kvm_mmio_fragment *frag;
87da7e66 8247 unsigned len;
5287f194 8248
716d51ab 8249 BUG_ON(!vcpu->mmio_needed);
5287f194 8250
716d51ab 8251 /* Complete previous fragment */
87da7e66
XG		 8252 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8253 len = min(8u, frag->len);
716d51ab 8254 if (!vcpu->mmio_is_write)
87da7e66
XG		 8255 memcpy(frag->data, run->mmio.data, len);
8256
8257 if (frag->len <= 8) {
8258 /* Switch to the next fragment. */
8259 frag++;
8260 vcpu->mmio_cur_fragment++;
8261 } else {
8262 /* Go forward to the next mmio piece. */
8263 frag->data += len;
8264 frag->gpa += len;
8265 frag->len -= len;
8266 }
8267
a08d3b3b 8268 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8269 vcpu->mmio_needed = 0;
0912c977
PB		 8270
8271 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8272 if (vcpu->mmio_is_write)
716d51ab
GN		 8273 return 1;
8274 vcpu->mmio_read_completed = 1;
8275 return complete_emulated_io(vcpu);
8276 }
87da7e66 8277
716d51ab
GN		 8278 run->exit_reason = KVM_EXIT_MMIO;
8279 run->mmio.phys_addr = frag->gpa;
8280 if (vcpu->mmio_is_write)
87da7e66
XG		 8281 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8282 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8283 run->mmio.is_write = vcpu->mmio_is_write;
8284 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8285 return 0;
5287f194
AK		 8286}
8287
822f312d
SAS		 8288/* Swap (qemu) user FPU context for the guest FPU context. */
8289static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8290{
5f409e20
RR		 8291 fpregs_lock();
8292
d9a710e5 8293 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
822f312d 8294 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8295 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8296 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8297
8298 fpregs_mark_activate();
8299 fpregs_unlock();
8300
822f312d
SAS		 8301 trace_kvm_fpu(1);
8302}
8303
8304/* When vcpu_run ends, restore user space FPU context. */
8305static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8306{
5f409e20
RR		 8307 fpregs_lock();
8308
b666a4b6 8309 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
d9a710e5 8310 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
5f409e20
RR		 8311
8312 fpregs_mark_activate();
8313 fpregs_unlock();
8314
822f312d
SAS		 8315 ++vcpu->stat.fpu_reload;
8316 trace_kvm_fpu(0);
8317}
8318
b6c7a5dc
HB		 8319int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8320{
8321 int r;
b6c7a5dc 8322
accb757d 8323 vcpu_load(vcpu);
20b7035c 8324 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8325 kvm_load_guest_fpu(vcpu);
8326
a4535290 8327 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8328 if (kvm_run->immediate_exit) {
8329 r = -EINTR;
8330 goto out;
8331 }
b6c7a5dc 8332 kvm_vcpu_block(vcpu);
66450a21 8333 kvm_apic_accept_events(vcpu);
72875d8a 8334 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8335 r = -EAGAIN;
a0595000
JS		 8336 if (signal_pending(current)) {
8337 r = -EINTR;
8338 vcpu->run->exit_reason = KVM_EXIT_INTR;
8339 ++vcpu->stat.signal_exits;
8340 }
ac9f6dc0 8341 goto out;
b6c7a5dc
HB		 8342 }
8343
01643c51
KH		 8344 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8345 r = -EINVAL;
8346 goto out;
8347 }
8348
8349 if (vcpu->run->kvm_dirty_regs) {
8350 r = sync_regs(vcpu);
8351 if (r != 0)
8352 goto out;
8353 }
8354
b6c7a5dc 8355 /* re-sync apic's tpr */
35754c98 8356 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8357 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8358 r = -EINVAL;
8359 goto out;
8360 }
8361 }
b6c7a5dc 8362
716d51ab
GN		 8363 if (unlikely(vcpu->arch.complete_userspace_io)) {
8364 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8365 vcpu->arch.complete_userspace_io = NULL;
8366 r = cui(vcpu);
8367 if (r <= 0)
5663d8f9 8368 goto out;
716d51ab
GN		 8369 } else
8370 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8371
460df4c1
PB		 8372 if (kvm_run->immediate_exit)
8373 r = -EINTR;
8374 else
8375 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8376
8377out:
5663d8f9 8378 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8379 if (vcpu->run->kvm_valid_regs)
8380 store_regs(vcpu);
f1d86e46 8381 post_kvm_run_save(vcpu);
20b7035c 8382 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8383
accb757d 8384 vcpu_put(vcpu);
b6c7a5dc
HB		 8385 return r;
8386}
8387
01643c51 8388static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8389{
7ae441ea
GN		 8390 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8391 /*
8392 * We are here if userspace calls get_regs() in the middle of
8393 * instruction emulation. Registers state needs to be copied
4a969980 8394 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8395 * that usually, but some bad designed PV devices (vmware
8396 * backdoor interface) need this to work
8397 */
dd856efa 8398 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8399 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8400 }
de3cd117
SC		 8401 regs->rax = kvm_rax_read(vcpu);
8402 regs->rbx = kvm_rbx_read(vcpu);
8403 regs->rcx = kvm_rcx_read(vcpu);
8404 regs->rdx = kvm_rdx_read(vcpu);
8405 regs->rsi = kvm_rsi_read(vcpu);
8406 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8407 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8408 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8409#ifdef CONFIG_X86_64
de3cd117
SC		 8410 regs->r8 = kvm_r8_read(vcpu);
8411 regs->r9 = kvm_r9_read(vcpu);
8412 regs->r10 = kvm_r10_read(vcpu);
8413 regs->r11 = kvm_r11_read(vcpu);
8414 regs->r12 = kvm_r12_read(vcpu);
8415 regs->r13 = kvm_r13_read(vcpu);
8416 regs->r14 = kvm_r14_read(vcpu);
8417 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8418#endif
8419
5fdbf976 8420 regs->rip = kvm_rip_read(vcpu);
91586a3b 8421 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8422}
b6c7a5dc 8423
01643c51
KH		 8424int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8425{
8426 vcpu_load(vcpu);
8427 __get_regs(vcpu, regs);
1fc9b76b 8428 vcpu_put(vcpu);
b6c7a5dc
HB		 8429 return 0;
8430}
8431
01643c51 8432static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8433{
7ae441ea
GN		 8434 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8435 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8436
de3cd117
SC		 8437 kvm_rax_write(vcpu, regs->rax);
8438 kvm_rbx_write(vcpu, regs->rbx);
8439 kvm_rcx_write(vcpu, regs->rcx);
8440 kvm_rdx_write(vcpu, regs->rdx);
8441 kvm_rsi_write(vcpu, regs->rsi);
8442 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8443 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8444 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8445#ifdef CONFIG_X86_64
de3cd117
SC		 8446 kvm_r8_write(vcpu, regs->r8);
8447 kvm_r9_write(vcpu, regs->r9);
8448 kvm_r10_write(vcpu, regs->r10);
8449 kvm_r11_write(vcpu, regs->r11);
8450 kvm_r12_write(vcpu, regs->r12);
8451 kvm_r13_write(vcpu, regs->r13);
8452 kvm_r14_write(vcpu, regs->r14);
8453 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8454#endif
8455
5fdbf976 8456 kvm_rip_write(vcpu, regs->rip);
d73235d1 8457 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8458
b4f14abd
JK		 8459 vcpu->arch.exception.pending = false;
8460
3842d135 8461 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8462}
3842d135 8463
01643c51
KH		 8464int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8465{
8466 vcpu_load(vcpu);
8467 __set_regs(vcpu, regs);
875656fe 8468 vcpu_put(vcpu);
b6c7a5dc
HB		 8469 return 0;
8470}
8471
b6c7a5dc
HB		 8472void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8473{
8474 struct kvm_segment cs;
8475
3e6e0aab 8476 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8477 *db = cs.db;
8478 *l = cs.l;
8479}
8480EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8481
01643c51 8482static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8483{
89a27f4d 8484 struct desc_ptr dt;
b6c7a5dc 8485
3e6e0aab
GT		 8486 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8487 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8488 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8489 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8490 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8491 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8492
3e6e0aab
GT		 8493 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8494 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8495
8496 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8497 sregs->idt.limit = dt.size;
8498 sregs->idt.base = dt.address;
b6c7a5dc 8499 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8500 sregs->gdt.limit = dt.size;
8501 sregs->gdt.base = dt.address;
b6c7a5dc 8502
4d4ec087 8503 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8504 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8505 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8506 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8507 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8508 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8509 sregs->apic_base = kvm_get_apic_base(vcpu);
8510
0e96f31e 8511 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8512
04140b41 8513 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8514 set_bit(vcpu->arch.interrupt.nr,
8515 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8516}
16d7a191 8517
01643c51
KH		 8518int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8519 struct kvm_sregs *sregs)
8520{
8521 vcpu_load(vcpu);
8522 __get_sregs(vcpu, sregs);
bcdec41c 8523 vcpu_put(vcpu);
b6c7a5dc
HB		 8524 return 0;
8525}
8526
62d9f0db
MT		 8527int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8528 struct kvm_mp_state *mp_state)
8529{
fd232561
CD		 8530 vcpu_load(vcpu);
8531
66450a21 8532 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8533 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8534 vcpu->arch.pv.pv_unhalted)
8535 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8536 else
8537 mp_state->mp_state = vcpu->arch.mp_state;
8538
fd232561 8539 vcpu_put(vcpu);
62d9f0db
MT		 8540 return 0;
8541}
8542
8543int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8544 struct kvm_mp_state *mp_state)
8545{
e83dff5e
CD		 8546 int ret = -EINVAL;
8547
8548 vcpu_load(vcpu);
8549
bce87cce 8550 if (!lapic_in_kernel(vcpu) &&
66450a21 8551 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8552 goto out;
66450a21 8553
28bf2888
DH		 8554 /* INITs are latched while in SMM */
8555 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8556 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8557 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8558 goto out;
28bf2888 8559
66450a21
JK		 8560 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8561 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8562 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8563 } else
8564 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8565 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8566
8567 ret = 0;
8568out:
8569 vcpu_put(vcpu);
8570 return ret;
62d9f0db
MT		 8571}
8572
7f3d35fd
KW		 8573int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8574 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8575{
9d74191a 8576 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8577 int ret;
e01c2426 8578
8ec4722d 8579 init_emulate_ctxt(vcpu);
c697518a 8580
7f3d35fd 8581 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8582 has_error_code, error_code);
c697518a 8583
c697518a 8584 if (ret)
19d04437 8585 return EMULATE_FAIL;
37817f29 8586
9d74191a
TY		 8587 kvm_rip_write(vcpu, ctxt->eip);
8588 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8589 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8590 return EMULATE_DONE;
37817f29
IE		 8591}
8592EXPORT_SYMBOL_GPL(kvm_task_switch);
8593
3140c156 8594static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8595{
74fec5b9
TL		 8596 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8597 (sregs->cr4 & X86_CR4_OSXSAVE))
8598 return -EINVAL;
8599
37b95951 8600 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8601 /*
8602 * When EFER.LME and CR0.PG are set, the processor is in
8603 * 64-bit mode (though maybe in a 32-bit code segment).
8604 * CR4.PAE and EFER.LMA must be set.
8605 */
37b95951 8606 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8607 || !(sregs->efer & EFER_LMA))
8608 return -EINVAL;
8609 } else {
8610 /*
8611 * Not in 64-bit mode: EFER.LMA is clear and the code
8612 * segment cannot be 64-bit.
8613 */
8614 if (sregs->efer & EFER_LMA || sregs->cs.l)
8615 return -EINVAL;
8616 }
8617
8618 return 0;
8619}
8620
01643c51 8621static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8622{
58cb628d 8623 struct msr_data apic_base_msr;
b6c7a5dc 8624 int mmu_reset_needed = 0;
c4d21882 8625 int cpuid_update_needed = 0;
63f42e02 8626 int pending_vec, max_bits, idx;
89a27f4d 8627 struct desc_ptr dt;
b4ef9d4e
CD		 8628 int ret = -EINVAL;
8629
f2981033 8630 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8631 goto out;
f2981033 8632
d3802286
JM		 8633 apic_base_msr.data = sregs->apic_base;
8634 apic_base_msr.host_initiated = true;
8635 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8636 goto out;
6d1068b3 8637
89a27f4d
GN		 8638 dt.size = sregs->idt.limit;
8639 dt.address = sregs->idt.base;
b6c7a5dc 8640 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8641 dt.size = sregs->gdt.limit;
8642 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8643 kvm_x86_ops->set_gdt(vcpu, &dt);
8644
ad312c7c 8645 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8646 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8647 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8648 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8649
2d3ad1f4 8650 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8651
f6801dff 8652 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8653 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8654
4d4ec087 8655 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8656 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8657 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8658
fc78f519 8659 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8660 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8661 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8662 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8663 if (cpuid_update_needed)
00b27a3e 8664 kvm_update_cpuid(vcpu);
63f42e02
XG		 8665
8666 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8667 if (is_pae_paging(vcpu)) {
9f8fe504 8668 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8669 mmu_reset_needed = 1;
8670 }
63f42e02 8671 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8672
8673 if (mmu_reset_needed)
8674 kvm_mmu_reset_context(vcpu);
8675
a50abc3b 8676 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8677 pending_vec = find_first_bit(
8678 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8679 if (pending_vec < max_bits) {
66fd3f7f 8680 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8681 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8682 }
8683
3e6e0aab
GT		 8684 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8685 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8686 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8687 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8688 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8689 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8690
3e6e0aab
GT		 8691 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8692 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8693
5f0269f5
ME		 8694 update_cr8_intercept(vcpu);
8695
9c3e4aab 8696 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8697 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8698 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8699 !is_protmode(vcpu))
9c3e4aab
MT		 8700 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8701
3842d135
AK		 8702 kvm_make_request(KVM_REQ_EVENT, vcpu);
8703
b4ef9d4e
CD		 8704 ret = 0;
8705out:
01643c51
KH		 8706 return ret;
8707}
8708
8709int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8710 struct kvm_sregs *sregs)
8711{
8712 int ret;
8713
8714 vcpu_load(vcpu);
8715 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8716 vcpu_put(vcpu);
8717 return ret;
b6c7a5dc
HB		 8718}
8719
d0bfb940
JK		 8720int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8721 struct kvm_guest_debug *dbg)
b6c7a5dc 8722{
355be0b9 8723 unsigned long rflags;
ae675ef0 8724 int i, r;
b6c7a5dc 8725
66b56562
CD		 8726 vcpu_load(vcpu);
8727
4f926bf2
JK		 8728 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8729 r = -EBUSY;
8730 if (vcpu->arch.exception.pending)
2122ff5e 8731 goto out;
4f926bf2
JK		 8732 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8733 kvm_queue_exception(vcpu, DB_VECTOR);
8734 else
8735 kvm_queue_exception(vcpu, BP_VECTOR);
8736 }
8737
91586a3b
JK		 8738 /*
8739 * Read rflags as long as potentially injected trace flags are still
8740 * filtered out.
8741 */
8742 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8743
8744 vcpu->guest_debug = dbg->control;
8745 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8746 vcpu->guest_debug = 0;
8747
8748 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8749 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8750 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8751 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8752 } else {
8753 for (i = 0; i < KVM_NR_DB_REGS; i++)
8754 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8755 }
c8639010 8756 kvm_update_dr7(vcpu);
ae675ef0 8757
f92653ee
JK		 8758 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8759 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8760 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8761
91586a3b
JK		 8762 /*
8763 * Trigger an rflags update that will inject or remove the trace
8764 * flags.
8765 */
8766 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8767
a96036b8 8768 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8769
4f926bf2 8770 r = 0;
d0bfb940 8771
2122ff5e 8772out:
66b56562 8773 vcpu_put(vcpu);
b6c7a5dc
HB		 8774 return r;
8775}
8776
8b006791
ZX		 8777/*
8778 * Translate a guest virtual address to a guest physical address.
8779 */
8780int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8781 struct kvm_translation *tr)
8782{
8783 unsigned long vaddr = tr->linear_address;
8784 gpa_t gpa;
f656ce01 8785 int idx;
8b006791 8786
1da5b61d
CD		 8787 vcpu_load(vcpu);
8788
f656ce01 8789 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8790 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8791 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8792 tr->physical_address = gpa;
8793 tr->valid = gpa != UNMAPPED_GVA;
8794 tr->writeable = 1;
8795 tr->usermode = 0;
8b006791 8796
1da5b61d 8797 vcpu_put(vcpu);
8b006791
ZX		 8798 return 0;
8799}
8800
d0752060
HB		 8801int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8802{
1393123e 8803 struct fxregs_state *fxsave;
d0752060 8804
1393123e 8805 vcpu_load(vcpu);
d0752060 8806
b666a4b6 8807 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8808 memcpy(fpu->fpr, fxsave->st_space, 128);
8809 fpu->fcw = fxsave->cwd;
8810 fpu->fsw = fxsave->swd;
8811 fpu->ftwx = fxsave->twd;
8812 fpu->last_opcode = fxsave->fop;
8813 fpu->last_ip = fxsave->rip;
8814 fpu->last_dp = fxsave->rdp;
0e96f31e 8815 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8816
1393123e 8817 vcpu_put(vcpu);
d0752060
HB		 8818 return 0;
8819}
8820
8821int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8822{
6a96bc7f
CD		 8823 struct fxregs_state *fxsave;
8824
8825 vcpu_load(vcpu);
8826
b666a4b6 8827 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8828
d0752060
HB		 8829 memcpy(fxsave->st_space, fpu->fpr, 128);
8830 fxsave->cwd = fpu->fcw;
8831 fxsave->swd = fpu->fsw;
8832 fxsave->twd = fpu->ftwx;
8833 fxsave->fop = fpu->last_opcode;
8834 fxsave->rip = fpu->last_ip;
8835 fxsave->rdp = fpu->last_dp;
0e96f31e 8836 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8837
6a96bc7f 8838 vcpu_put(vcpu);
d0752060
HB		 8839 return 0;
8840}
8841
01643c51
KH		 8842static void store_regs(struct kvm_vcpu *vcpu)
8843{
8844 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8845
8846 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8847 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8848
8849 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8850 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8851
8852 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8853 kvm_vcpu_ioctl_x86_get_vcpu_events(
8854 vcpu, &vcpu->run->s.regs.events);
8855}
8856
8857static int sync_regs(struct kvm_vcpu *vcpu)
8858{
8859 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8860 return -EINVAL;
8861
8862 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8863 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8864 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8865 }
8866 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8867 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8868 return -EINVAL;
8869 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8870 }
8871 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8872 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8873 vcpu, &vcpu->run->s.regs.events))
8874 return -EINVAL;
8875 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8876 }
8877
8878 return 0;
8879}
8880
0ee6a517 8881static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8882{
b666a4b6 8883 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8884 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8885 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8886 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8887
2acf923e
DC		 8888 /*
8889 * Ensure guest xcr0 is valid for loading
8890 */
d91cab78 8891 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8892
ad312c7c 8893 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8894}
d0752060 8895
e9b11c17
ZX		 8896void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8897{
bd768e14
IY		 8898 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8899
12f9a48f 8900 kvmclock_reset(vcpu);
7f1ea208 8901
e9b11c17 8902 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8903 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8904}
8905
8906struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8907 unsigned int id)
8908{
c447e76b
LL		 8909 struct kvm_vcpu *vcpu;
8910
b0c39dc6 8911 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8912 printk_once(KERN_WARNING
8913 "kvm: SMP vm created on host with unstable TSC; "
8914 "guest TSC will not be reliable\n");
c447e76b
LL		 8915
8916 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8917
c447e76b 8918 return vcpu;
26e5215f 8919}
e9b11c17 8920
26e5215f
AK		 8921int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8922{
0cf9135b 8923 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 8924 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8925 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8926 vcpu_load(vcpu);
d28bc9dd 8927 kvm_vcpu_reset(vcpu, false);
e1732991 8928 kvm_init_mmu(vcpu, false);
e9b11c17 8929 vcpu_put(vcpu);
ec7660cc 8930 return 0;
e9b11c17
ZX		 8931}
8932
31928aa5 8933void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8934{
8fe8ab46 8935 struct msr_data msr;
332967a3 8936 struct kvm *kvm = vcpu->kvm;
42897d86 8937
d3457c87
RK		 8938 kvm_hv_vcpu_postcreate(vcpu);
8939
ec7660cc 8940 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8941 return;
ec7660cc 8942 vcpu_load(vcpu);
8fe8ab46
WA		 8943 msr.data = 0x0;
8944 msr.index = MSR_IA32_TSC;
8945 msr.host_initiated = true;
8946 kvm_write_tsc(vcpu, &msr);
42897d86 8947 vcpu_put(vcpu);
2d5ba19b
MT		 8948
8949 /* poll control enabled by default */
8950 vcpu->arch.msr_kvm_poll_control = 1;
8951
ec7660cc 8952 mutex_unlock(&vcpu->mutex);
42897d86 8953
630994b3
MT		 8954 if (!kvmclock_periodic_sync)
8955 return;
8956
332967a3
AJ		 8957 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8958 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8959}
8960
d40ccc62 8961void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8962{
344d9588
GN		 8963 vcpu->arch.apf.msr_val = 0;
8964
ec7660cc 8965 vcpu_load(vcpu);
e9b11c17
ZX		 8966 kvm_mmu_unload(vcpu);
8967 vcpu_put(vcpu);
8968
8969 kvm_x86_ops->vcpu_free(vcpu);
8970}
8971
d28bc9dd 8972void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8973{
b7e31be3
RK		 8974 kvm_lapic_reset(vcpu, init_event);
8975
e69fab5d
PB		 8976 vcpu->arch.hflags = 0;
8977
c43203ca 8978 vcpu->arch.smi_pending = 0;
52797bf9 8979 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8980 atomic_set(&vcpu->arch.nmi_queued, 0);
8981 vcpu->arch.nmi_pending = 0;
448fa4a9 8982 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8983 kvm_clear_interrupt_queue(vcpu);
8984 kvm_clear_exception_queue(vcpu);
664f8e26 8985 vcpu->arch.exception.pending = false;
448fa4a9 8986
42dbaa5a 8987 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8988 kvm_update_dr0123(vcpu);
6f43ed01 8989 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8990 kvm_update_dr6(vcpu);
42dbaa5a 8991 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8992 kvm_update_dr7(vcpu);
42dbaa5a 8993
1119022c
NA		 8994 vcpu->arch.cr2 = 0;
8995
3842d135 8996 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8997 vcpu->arch.apf.msr_val = 0;
c9aaa895 8998 vcpu->arch.st.msr_val = 0;
3842d135 8999
12f9a48f
GC		 9000 kvmclock_reset(vcpu);
9001
af585b92
GN		 9002 kvm_clear_async_pf_completion_queue(vcpu);
9003 kvm_async_pf_hash_reset(vcpu);
9004 vcpu->arch.apf.halted = false;
3842d135 9005
a554d207
WL		 9006 if (kvm_mpx_supported()) {
9007 void *mpx_state_buffer;
9008
9009 /*
9010 * To avoid have the INIT path from kvm_apic_has_events() that be
9011 * called with loaded FPU and does not let userspace fix the state.
9012 */
f775b13e
RR		 9013 if (init_event)
9014 kvm_put_guest_fpu(vcpu);
b666a4b6 9015 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9016 XFEATURE_BNDREGS);
a554d207
WL		 9017 if (mpx_state_buffer)
9018 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 9019 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9020 XFEATURE_BNDCSR);
a554d207
WL		 9021 if (mpx_state_buffer)
9022 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 9023 if (init_event)
9024 kvm_load_guest_fpu(vcpu);
a554d207
WL		 9025 }
9026
64d60670 9027 if (!init_event) {
d28bc9dd 9028 kvm_pmu_reset(vcpu);
64d60670 9029 vcpu->arch.smbase = 0x30000;
db2336a8 9030
db2336a8 9031 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9032
9033 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9034 }
f5132b01 9035
66f7b72e
JS		 9036 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9037 vcpu->arch.regs_avail = ~0;
9038 vcpu->arch.regs_dirty = ~0;
9039
a554d207
WL		 9040 vcpu->arch.ia32_xss = 0;
9041
d28bc9dd 9042 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9043}
9044
2b4a273b 9045void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9046{
9047 struct kvm_segment cs;
9048
9049 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9050 cs.selector = vector << 8;
9051 cs.base = vector << 12;
9052 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9053 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9054}
9055
13a34e06 9056int kvm_arch_hardware_enable(void)
e9b11c17 9057{
ca84d1a2
ZA		 9058 struct kvm *kvm;
9059 struct kvm_vcpu *vcpu;
9060 int i;
0dd6a6ed
ZA		 9061 int ret;
9062 u64 local_tsc;
9063 u64 max_tsc = 0;
9064 bool stable, backwards_tsc = false;
18863bdd
AK		 9065
9066 kvm_shared_msr_cpu_online();
13a34e06 9067 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9068 if (ret != 0)
9069 return ret;
9070
4ea1636b 9071 local_tsc = rdtsc();
b0c39dc6 9072 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9073 list_for_each_entry(kvm, &vm_list, vm_list) {
9074 kvm_for_each_vcpu(i, vcpu, kvm) {
9075 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9077 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9078 backwards_tsc = true;
9079 if (vcpu->arch.last_host_tsc > max_tsc)
9080 max_tsc = vcpu->arch.last_host_tsc;
9081 }
9082 }
9083 }
9084
9085 /*
9086 * Sometimes, even reliable TSCs go backwards. This happens on
9087 * platforms that reset TSC during suspend or hibernate actions, but
9088 * maintain synchronization. We must compensate. Fortunately, we can
9089 * detect that condition here, which happens early in CPU bringup,
9090 * before any KVM threads can be running. Unfortunately, we can't
9091 * bring the TSCs fully up to date with real time, as we aren't yet far
9092 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9093 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9094 * variables that haven't been updated yet.
9095 *
9096 * So we simply find the maximum observed TSC above, then record the
9097 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9098 * the adjustment will be applied. Note that we accumulate
9099 * adjustments, in case multiple suspend cycles happen before some VCPU
9100 * gets a chance to run again. In the event that no KVM threads get a
9101 * chance to run, we will miss the entire elapsed period, as we'll have
9102 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9103 * loose cycle time. This isn't too big a deal, since the loss will be
9104 * uniform across all VCPUs (not to mention the scenario is extremely
9105 * unlikely). It is possible that a second hibernate recovery happens
9106 * much faster than a first, causing the observed TSC here to be
9107 * smaller; this would require additional padding adjustment, which is
9108 * why we set last_host_tsc to the local tsc observed here.
9109 *
9110 * N.B. - this code below runs only on platforms with reliable TSC,
9111 * as that is the only way backwards_tsc is set above. Also note
9112 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9113 * have the same delta_cyc adjustment applied if backwards_tsc
9114 * is detected. Note further, this adjustment is only done once,
9115 * as we reset last_host_tsc on all VCPUs to stop this from being
9116 * called multiple times (one for each physical CPU bringup).
9117 *
4a969980 9118 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9119 * will be compensated by the logic in vcpu_load, which sets the TSC to
9120 * catchup mode. This will catchup all VCPUs to real time, but cannot
9121 * guarantee that they stay in perfect synchronization.
9122 */
9123 if (backwards_tsc) {
9124 u64 delta_cyc = max_tsc - local_tsc;
9125 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9126 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9127 kvm_for_each_vcpu(i, vcpu, kvm) {
9128 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9129 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9130 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9131 }
9132
9133 /*
9134 * We have to disable TSC offset matching.. if you were
9135 * booting a VM while issuing an S4 host suspend....
9136 * you may have some problem. Solving this issue is
9137 * left as an exercise to the reader.
9138 */
9139 kvm->arch.last_tsc_nsec = 0;
9140 kvm->arch.last_tsc_write = 0;
9141 }
9142
9143 }
9144 return 0;
e9b11c17
ZX		 9145}
9146
13a34e06 9147void kvm_arch_hardware_disable(void)
e9b11c17 9148{
13a34e06
RK		 9149 kvm_x86_ops->hardware_disable();
9150 drop_user_return_notifiers();
e9b11c17
ZX		 9151}
9152
9153int kvm_arch_hardware_setup(void)
9154{
9e9c3fe4
NA		 9155 int r;
9156
9157 r = kvm_x86_ops->hardware_setup();
9158 if (r != 0)
9159 return r;
9160
35181e86
HZ		 9161 if (kvm_has_tsc_control) {
9162 /*
9163 * Make sure the user can only configure tsc_khz values that
9164 * fit into a signed integer.
273ba457 9165 * A min value is not calculated because it will always
35181e86
HZ		 9166 * be 1 on all machines.
9167 */
9168 u64 max = min(0x7fffffffULL,
9169 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9170 kvm_max_guest_tsc_khz = max;
9171
ad721883 9172 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9173 }
ad721883 9174
9e9c3fe4
NA		 9175 kvm_init_msr_list();
9176 return 0;
e9b11c17
ZX		 9177}
9178
9179void kvm_arch_hardware_unsetup(void)
9180{
9181 kvm_x86_ops->hardware_unsetup();
9182}
9183
f257d6dc 9184int kvm_arch_check_processor_compat(void)
e9b11c17 9185{
f257d6dc 9186 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9187}
9188
9189bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9190{
9191 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9192}
9193EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9194
9195bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9196{
9197 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9198}
9199
54e9818f 9200struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9201EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9202
e9b11c17
ZX		 9203int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9204{
9205 struct page *page;
e9b11c17
ZX		 9206 int r;
9207
9aabc88f 9208 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9209 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9210 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9211 else
a4535290 9212 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9213
9214 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9215 if (!page) {
9216 r = -ENOMEM;
9217 goto fail;
9218 }
ad312c7c 9219 vcpu->arch.pio_data = page_address(page);
e9b11c17 9220
cc578287 9221 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9222
e9b11c17
ZX		 9223 r = kvm_mmu_create(vcpu);
9224 if (r < 0)
9225 goto fail_free_pio_data;
9226
26de7988 9227 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9228 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9229 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9230 if (r < 0)
9231 goto fail_mmu_destroy;
54e9818f
GN		 9232 } else
9233 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9234
890ca9ae 9235 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9236 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9237 if (!vcpu->arch.mce_banks) {
9238 r = -ENOMEM;
443c39bc 9239 goto fail_free_lapic;
890ca9ae
HY		 9240 }
9241 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9242
254272ce
BG		 9243 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9244 GFP_KERNEL_ACCOUNT)) {
f1797359 9245 r = -ENOMEM;
f5f48ee1 9246 goto fail_free_mce_banks;
f1797359 9247 }
f5f48ee1 9248
0ee6a517 9249 fx_init(vcpu);
66f7b72e 9250
4344ee98 9251 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9252
5a4f55cd
EK		 9253 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9254
74545705
RK		 9255 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9256
af585b92 9257 kvm_async_pf_hash_reset(vcpu);
f5132b01 9258 kvm_pmu_init(vcpu);
af585b92 9259
1c1a9ce9 9260 vcpu->arch.pending_external_vector = -1;
de63ad4c 9261 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9262
5c919412
AS		 9263 kvm_hv_vcpu_init(vcpu);
9264
e9b11c17 9265 return 0;
0ee6a517 9266
f5f48ee1
SY		 9267fail_free_mce_banks:
9268 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9269fail_free_lapic:
9270 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9271fail_mmu_destroy:
9272 kvm_mmu_destroy(vcpu);
9273fail_free_pio_data:
ad312c7c 9274 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9275fail:
9276 return r;
9277}
9278
9279void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9280{
f656ce01
MT		 9281 int idx;
9282
1f4b34f8 9283 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9284 kvm_pmu_destroy(vcpu);
36cb93fd 9285 kfree(vcpu->arch.mce_banks);
e9b11c17 9286 kvm_free_lapic(vcpu);
f656ce01 9287 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9288 kvm_mmu_destroy(vcpu);
f656ce01 9289 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9290 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9291 if (!lapic_in_kernel(vcpu))
54e9818f 9292 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9293}
d19a9cd2 9294
e790d9ef
RK		 9295void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9296{
c595ceee 9297 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9298 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9299}
9300
e08b9637 9301int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9302{
e08b9637
CO		 9303 if (type)
9304 return -EINVAL;
9305
6ef768fa 9306 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9307 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9308 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9309 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9310
5550af4d
SY		 9311 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9312 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9313 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9314 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9315 &kvm->arch.irq_sources_bitmap);
5550af4d 9316
038f8c11 9317 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9318 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9319 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9320
9285ec4c 9321 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9322 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9323
6fbbde9a
DS		 9324 kvm->arch.guest_can_read_msr_platform_info = true;
9325
7e44e449 9326 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9327 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9328
cbc0236a 9329 kvm_hv_init_vm(kvm);
0eb05bf2 9330 kvm_page_track_init(kvm);
13d268ca 9331 kvm_mmu_init_vm(kvm);
0eb05bf2 9332
03543133
SS		 9333 if (kvm_x86_ops->vm_init)
9334 return kvm_x86_ops->vm_init(kvm);
9335
d89f5eff 9336 return 0;
d19a9cd2
ZX		 9337}
9338
9339static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9340{
ec7660cc 9341 vcpu_load(vcpu);
d19a9cd2
ZX		 9342 kvm_mmu_unload(vcpu);
9343 vcpu_put(vcpu);
9344}
9345
9346static void kvm_free_vcpus(struct kvm *kvm)
9347{
9348 unsigned int i;
988a2cae 9349 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9350
9351 /*
9352 * Unpin any mmu pages first.
9353 */
af585b92
GN		 9354 kvm_for_each_vcpu(i, vcpu, kvm) {
9355 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9356 kvm_unload_vcpu_mmu(vcpu);
af585b92 9357 }
988a2cae
GN		 9358 kvm_for_each_vcpu(i, vcpu, kvm)
9359 kvm_arch_vcpu_free(vcpu);
9360
9361 mutex_lock(&kvm->lock);
9362 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9363 kvm->vcpus[i] = NULL;
d19a9cd2 9364
988a2cae
GN		 9365 atomic_set(&kvm->online_vcpus, 0);
9366 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9367}
9368
ad8ba2cd
SY		 9369void kvm_arch_sync_events(struct kvm *kvm)
9370{
332967a3 9371 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9372 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9373 kvm_free_pit(kvm);
ad8ba2cd
SY		 9374}
9375
1d8007bd 9376int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9377{
9378 int i, r;
25188b99 9379 unsigned long hva;
f0d648bd
PB		 9380 struct kvm_memslots *slots = kvm_memslots(kvm);
9381 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9382
9383 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9384 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9385 return -EINVAL;
9da0e4d5 9386
f0d648bd
PB		 9387 slot = id_to_memslot(slots, id);
9388 if (size) {
b21629da 9389 if (slot->npages)
f0d648bd
PB		 9390 return -EEXIST;
9391
9392 /*
9393 * MAP_SHARED to prevent internal slot pages from being moved
9394 * by fork()/COW.
9395 */
9396 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9397 MAP_SHARED | MAP_ANONYMOUS, 0);
9398 if (IS_ERR((void *)hva))
9399 return PTR_ERR((void *)hva);
9400 } else {
9401 if (!slot->npages)
9402 return 0;
9403
9404 hva = 0;
9405 }
9406
9407 old = *slot;
9da0e4d5 9408 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9409 struct kvm_userspace_memory_region m;
9da0e4d5 9410
1d8007bd
PB		 9411 m.slot = id | (i << 16);
9412 m.flags = 0;
9413 m.guest_phys_addr = gpa;
f0d648bd 9414 m.userspace_addr = hva;
1d8007bd 9415 m.memory_size = size;
9da0e4d5
PB		 9416 r = __kvm_set_memory_region(kvm, &m);
9417 if (r < 0)
9418 return r;
9419 }
9420
103c763c
EB		 9421 if (!size)
9422 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9423
9da0e4d5
PB		 9424 return 0;
9425}
9426EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9427
1d8007bd 9428int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9429{
9430 int r;
9431
9432 mutex_lock(&kvm->slots_lock);
1d8007bd 9433 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9434 mutex_unlock(&kvm->slots_lock);
9435
9436 return r;
9437}
9438EXPORT_SYMBOL_GPL(x86_set_memory_region);
9439
d19a9cd2
ZX		 9440void kvm_arch_destroy_vm(struct kvm *kvm)
9441{
27469d29
AH		 9442 if (current->mm == kvm->mm) {
9443 /*
9444 * Free memory regions allocated on behalf of userspace,
9445 * unless the the memory map has changed due to process exit
9446 * or fd copying.
9447 */
1d8007bd
PB		 9448 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9449 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9450 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9451 }
03543133
SS		 9452 if (kvm_x86_ops->vm_destroy)
9453 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9454 kvm_pic_destroy(kvm);
9455 kvm_ioapic_destroy(kvm);
d19a9cd2 9456 kvm_free_vcpus(kvm);
af1bae54 9457 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9458 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9459 kvm_mmu_uninit_vm(kvm);
2beb6dad 9460 kvm_page_track_cleanup(kvm);
cbc0236a 9461 kvm_hv_destroy_vm(kvm);
d19a9cd2 9462}
0de10343 9463
5587027c 9464void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9465 struct kvm_memory_slot *dont)
9466{
9467 int i;
9468
d89cc617
TY		 9469 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9470 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9471 kvfree(free->arch.rmap[i]);
d89cc617 9472 free->arch.rmap[i] = NULL;
77d11309 9473 }
d89cc617
TY		 9474 if (i == 0)
9475 continue;
9476
9477 if (!dont || free->arch.lpage_info[i - 1] !=
9478 dont->arch.lpage_info[i - 1]) {
548ef284 9479 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9480 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9481 }
9482 }
21ebbeda
XG		 9483
9484 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9485}
9486
5587027c
AK		 9487int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9488 unsigned long npages)
db3fe4eb
TY		 9489{
9490 int i;
9491
d89cc617 9492 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9493 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9494 unsigned long ugfn;
9495 int lpages;
d89cc617 9496 int level = i + 1;
db3fe4eb
TY		 9497
9498 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9499 slot->base_gfn, level) + 1;
9500
d89cc617 9501 slot->arch.rmap[i] =
778e1cdd 9502 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9503 GFP_KERNEL_ACCOUNT);
d89cc617 9504 if (!slot->arch.rmap[i])
77d11309 9505 goto out_free;
d89cc617
TY		 9506 if (i == 0)
9507 continue;
77d11309 9508
254272ce 9509 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9510 if (!linfo)
db3fe4eb
TY		 9511 goto out_free;
9512
92f94f1e
XG		 9513 slot->arch.lpage_info[i - 1] = linfo;
9514
db3fe4eb 9515 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9516 linfo[0].disallow_lpage = 1;
db3fe4eb 9517 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9518 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9519 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9520 /*
9521 * If the gfn and userspace address are not aligned wrt each
9522 * other, or if explicitly asked to, disable large page
9523 * support for this slot
9524 */
9525 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9526 !kvm_largepages_enabled()) {
9527 unsigned long j;
9528
9529 for (j = 0; j < lpages; ++j)
92f94f1e 9530 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9531 }
9532 }
9533
21ebbeda
XG		 9534 if (kvm_page_track_create_memslot(slot, npages))
9535 goto out_free;
9536
db3fe4eb
TY		 9537 return 0;
9538
9539out_free:
d89cc617 9540 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9541 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9542 slot->arch.rmap[i] = NULL;
9543 if (i == 0)
9544 continue;
9545
548ef284 9546 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9547 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9548 }
9549 return -ENOMEM;
9550}
9551
15248258 9552void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9553{
e6dff7d1
TY		 9554 /*
9555 * memslots->generation has been incremented.
9556 * mmio generation may have reached its maximum value.
9557 */
15248258 9558 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9559}
9560
f7784b8e
MT		 9561int kvm_arch_prepare_memory_region(struct kvm *kvm,
9562 struct kvm_memory_slot *memslot,
09170a49 9563 const struct kvm_userspace_memory_region *mem,
7b6195a9 9564 enum kvm_mr_change change)
0de10343 9565{
f7784b8e
MT		 9566 return 0;
9567}
9568
88178fd4
KH		 9569static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9570 struct kvm_memory_slot *new)
9571{
9572 /* Still write protect RO slot */
9573 if (new->flags & KVM_MEM_READONLY) {
9574 kvm_mmu_slot_remove_write_access(kvm, new);
9575 return;
9576 }
9577
9578 /*
9579 * Call kvm_x86_ops dirty logging hooks when they are valid.
9580 *
9581 * kvm_x86_ops->slot_disable_log_dirty is called when:
9582 *
9583 * - KVM_MR_CREATE with dirty logging is disabled
9584 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9585 *
9586 * The reason is, in case of PML, we need to set D-bit for any slots
9587 * with dirty logging disabled in order to eliminate unnecessary GPA
9588 * logging in PML buffer (and potential PML buffer full VMEXT). This
9589 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9590 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9591 * logging disabled for memory slots.
9592 *
9593 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9594 * to dirty logging mode.
9595 *
9596 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9597 *
9598 * In case of write protect:
9599 *
9600 * Write protect all pages for dirty logging.
9601 *
9602 * All the sptes including the large sptes which point to this
9603 * slot are set to readonly. We can not create any new large
9604 * spte on this slot until the end of the logging.
9605 *
9606 * See the comments in fast_page_fault().
9607 */
9608 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9609 if (kvm_x86_ops->slot_enable_log_dirty)
9610 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9611 else
9612 kvm_mmu_slot_remove_write_access(kvm, new);
9613 } else {
9614 if (kvm_x86_ops->slot_disable_log_dirty)
9615 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9616 }
9617}
9618
f7784b8e 9619void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9620 const struct kvm_userspace_memory_region *mem,
8482644a 9621 const struct kvm_memory_slot *old,
f36f3f28 9622 const struct kvm_memory_slot *new,
8482644a 9623 enum kvm_mr_change change)
f7784b8e 9624{
48c0e4e9 9625 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9626 kvm_mmu_change_mmu_pages(kvm,
9627 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9628
3ea3b7fa
WL		 9629 /*
9630 * Dirty logging tracks sptes in 4k granularity, meaning that large
9631 * sptes have to be split. If live migration is successful, the guest
9632 * in the source machine will be destroyed and large sptes will be
9633 * created in the destination. However, if the guest continues to run
9634 * in the source machine (for example if live migration fails), small
9635 * sptes will remain around and cause bad performance.
9636 *
9637 * Scan sptes if dirty logging has been stopped, dropping those
9638 * which can be collapsed into a single large-page spte. Later
9639 * page faults will create the large-page sptes.
9640 */
9641 if ((change != KVM_MR_DELETE) &&
9642 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9643 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9644 kvm_mmu_zap_collapsible_sptes(kvm, new);
9645
c972f3b1 9646 /*
88178fd4 9647 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9648 *
88178fd4
KH		 9649 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9650 * been zapped so no dirty logging staff is needed for old slot. For
9651 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9652 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9653 *
9654 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9655 */
88178fd4 9656 if (change != KVM_MR_DELETE)
f36f3f28 9657 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9658}
1d737c8a 9659
2df72e9b 9660void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9661{
7390de1e 9662 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9663}
9664
2df72e9b
MT		 9665void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9666 struct kvm_memory_slot *slot)
9667{
ae7cd873 9668 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9669}
9670
e6c67d8c
LA		 9671static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9672{
9673 return (is_guest_mode(vcpu) &&
9674 kvm_x86_ops->guest_apic_has_interrupt &&
9675 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9676}
9677
5d9bc648
PB		 9678static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9679{
9680 if (!list_empty_careful(&vcpu->async_pf.done))
9681 return true;
9682
9683 if (kvm_apic_has_events(vcpu))
9684 return true;
9685
9686 if (vcpu->arch.pv.pv_unhalted)
9687 return true;
9688
a5f01f8e
WL		 9689 if (vcpu->arch.exception.pending)
9690 return true;
9691
47a66eed
Z		 9692 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9693 (vcpu->arch.nmi_pending &&
9694 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9695 return true;
9696
47a66eed
Z		 9697 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9698 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9699 return true;
9700
5d9bc648 9701 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9702 (kvm_cpu_has_interrupt(vcpu) ||
9703 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9704 return true;
9705
1f4b34f8
AS		 9706 if (kvm_hv_has_stimer_pending(vcpu))
9707 return true;
9708
5d9bc648
PB		 9709 return false;
9710}
9711
1d737c8a
ZX		 9712int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9713{
5d9bc648 9714 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9715}
5736199a 9716
17e433b5
WL		 9717bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9718{
9719 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9720 return true;
9721
9722 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9723 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9724 kvm_test_request(KVM_REQ_EVENT, vcpu))
9725 return true;
9726
9727 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9728 return true;
9729
9730 return false;
9731}
9732
199b5763
LM		 9733bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9734{
de63ad4c 9735 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9736}
9737
b6d33834 9738int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9739{
b6d33834 9740 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9741}
78646121
GN		 9742
9743int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9744{
9745 return kvm_x86_ops->interrupt_allowed(vcpu);
9746}
229456fc 9747
82b32774 9748unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9749{
82b32774
NA		 9750 if (is_64_bit_mode(vcpu))
9751 return kvm_rip_read(vcpu);
9752 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9753 kvm_rip_read(vcpu));
9754}
9755EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9756
82b32774
NA		 9757bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9758{
9759 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9760}
9761EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9762
94fe45da
JK		 9763unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9764{
9765 unsigned long rflags;
9766
9767 rflags = kvm_x86_ops->get_rflags(vcpu);
9768 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9769 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9770 return rflags;
9771}
9772EXPORT_SYMBOL_GPL(kvm_get_rflags);
9773
6addfc42 9774static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9775{
9776 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9777 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9778 rflags |= X86_EFLAGS_TF;
94fe45da 9779 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9780}
9781
9782void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9783{
9784 __kvm_set_rflags(vcpu, rflags);
3842d135 9785 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9786}
9787EXPORT_SYMBOL_GPL(kvm_set_rflags);
9788
56028d08
GN		 9789void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9790{
9791 int r;
9792
44dd3ffa 9793 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9794 work->wakeup_all)
56028d08
GN		 9795 return;
9796
9797 r = kvm_mmu_reload(vcpu);
9798 if (unlikely(r))
9799 return;
9800
44dd3ffa
VK		 9801 if (!vcpu->arch.mmu->direct_map &&
9802 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9803 return;
9804
44dd3ffa 9805 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9806}
9807
af585b92
GN		 9808static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9809{
9810 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9811}
9812
9813static inline u32 kvm_async_pf_next_probe(u32 key)
9814{
9815 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9816}
9817
9818static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9819{
9820 u32 key = kvm_async_pf_hash_fn(gfn);
9821
9822 while (vcpu->arch.apf.gfns[key] != ~0)
9823 key = kvm_async_pf_next_probe(key);
9824
9825 vcpu->arch.apf.gfns[key] = gfn;
9826}
9827
9828static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9829{
9830 int i;
9831 u32 key = kvm_async_pf_hash_fn(gfn);
9832
9833 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9834 (vcpu->arch.apf.gfns[key] != gfn &&
9835 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9836 key = kvm_async_pf_next_probe(key);
9837
9838 return key;
9839}
9840
9841bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9842{
9843 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9844}
9845
9846static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9847{
9848 u32 i, j, k;
9849
9850 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9851 while (true) {
9852 vcpu->arch.apf.gfns[i] = ~0;
9853 do {
9854 j = kvm_async_pf_next_probe(j);
9855 if (vcpu->arch.apf.gfns[j] == ~0)
9856 return;
9857 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9858 /*
9859 * k lies cyclically in ]i,j]
9860 * | i.k.j |
9861 * |....j i.k.| or |.k..j i...|
9862 */
9863 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9864 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9865 i = j;
9866 }
9867}
9868
7c90705b
GN		 9869static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9870{
4e335d9e
PB		 9871
9872 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9873 sizeof(val));
7c90705b
GN		 9874}
9875
9a6e7c39
WL		 9876static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9877{
9878
9879 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9880 sizeof(u32));
9881}
9882
1dfdb45e
PB		 9883static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9884{
9885 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9886 return false;
9887
9888 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9889 (vcpu->arch.apf.send_user_only &&
9890 kvm_x86_ops->get_cpl(vcpu) == 0))
9891 return false;
9892
9893 return true;
9894}
9895
9896bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9897{
9898 if (unlikely(!lapic_in_kernel(vcpu) ||
9899 kvm_event_needs_reinjection(vcpu) ||
9900 vcpu->arch.exception.pending))
9901 return false;
9902
9903 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
9904 return false;
9905
9906 /*
9907 * If interrupts are off we cannot even use an artificial
9908 * halt state.
9909 */
9910 return kvm_x86_ops->interrupt_allowed(vcpu);
9911}
9912
af585b92
GN		 9913void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9914 struct kvm_async_pf *work)
9915{
6389ee94
AK		 9916 struct x86_exception fault;
9917
7c90705b 9918 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9919 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 9920
1dfdb45e
PB		 9921 if (kvm_can_deliver_async_pf(vcpu) &&
9922 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9923 fault.vector = PF_VECTOR;
9924 fault.error_code_valid = true;
9925 fault.error_code = 0;
9926 fault.nested_page_fault = false;
9927 fault.address = work->arch.token;
adfe20fb 9928 fault.async_page_fault = true;
6389ee94 9929 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 9930 } else {
9931 /*
9932 * It is not possible to deliver a paravirtualized asynchronous
9933 * page fault, but putting the guest in an artificial halt state
9934 * can be beneficial nevertheless: if an interrupt arrives, we
9935 * can deliver it timely and perhaps the guest will schedule
9936 * another process. When the instruction that triggered a page
9937 * fault is retried, hopefully the page will be ready in the host.
9938 */
9939 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 9940 }
af585b92
GN		 9941}
9942
9943void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9944 struct kvm_async_pf *work)
9945{
6389ee94 9946 struct x86_exception fault;
9a6e7c39 9947 u32 val;
6389ee94 9948
f2e10669 9949 if (work->wakeup_all)
7c90705b
GN		 9950 work->arch.token = ~0; /* broadcast wakeup */
9951 else
9952 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9953 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9954
9a6e7c39
WL		 9955 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9956 !apf_get_user(vcpu, &val)) {
9957 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9958 vcpu->arch.exception.pending &&
9959 vcpu->arch.exception.nr == PF_VECTOR &&
9960 !apf_put_user(vcpu, 0)) {
9961 vcpu->arch.exception.injected = false;
9962 vcpu->arch.exception.pending = false;
9963 vcpu->arch.exception.nr = 0;
9964 vcpu->arch.exception.has_error_code = false;
9965 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9966 vcpu->arch.exception.has_payload = false;
9967 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9968 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9969 fault.vector = PF_VECTOR;
9970 fault.error_code_valid = true;
9971 fault.error_code = 0;
9972 fault.nested_page_fault = false;
9973 fault.address = work->arch.token;
9974 fault.async_page_fault = true;
9975 kvm_inject_page_fault(vcpu, &fault);
9976 }
7c90705b 9977 }
e6d53e3b 9978 vcpu->arch.apf.halted = false;
a4fa1635 9979 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9980}
9981
9982bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9983{
9984 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9985 return true;
9986 else
9bc1f09f 9987 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9988}
9989
5544eb9b
PB		 9990void kvm_arch_start_assignment(struct kvm *kvm)
9991{
9992 atomic_inc(&kvm->arch.assigned_device_count);
9993}
9994EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9995
9996void kvm_arch_end_assignment(struct kvm *kvm)
9997{
9998 atomic_dec(&kvm->arch.assigned_device_count);
9999}
10000EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10001
10002bool kvm_arch_has_assigned_device(struct kvm *kvm)
10003{
10004 return atomic_read(&kvm->arch.assigned_device_count);
10005}
10006EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10007
e0f0bbc5
AW		 10008void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10009{
10010 atomic_inc(&kvm->arch.noncoherent_dma_count);
10011}
10012EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10013
10014void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10015{
10016 atomic_dec(&kvm->arch.noncoherent_dma_count);
10017}
10018EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10019
10020bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10021{
10022 return atomic_read(&kvm->arch.noncoherent_dma_count);
10023}
10024EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10025
14717e20
AW		 10026bool kvm_arch_has_irq_bypass(void)
10027{
10028 return kvm_x86_ops->update_pi_irte != NULL;
10029}
10030
87276880
FW		 10031int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10032 struct irq_bypass_producer *prod)
10033{
10034 struct kvm_kernel_irqfd *irqfd =
10035 container_of(cons, struct kvm_kernel_irqfd, consumer);
10036
14717e20 10037 irqfd->producer = prod;
87276880 10038
14717e20
AW		 10039 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10040 prod->irq, irqfd->gsi, 1);
87276880
FW		 10041}
10042
10043void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10044 struct irq_bypass_producer *prod)
10045{
10046 int ret;
10047 struct kvm_kernel_irqfd *irqfd =
10048 container_of(cons, struct kvm_kernel_irqfd, consumer);
10049
87276880
FW		 10050 WARN_ON(irqfd->producer != prod);
10051 irqfd->producer = NULL;
10052
10053 /*
10054 * When producer of consumer is unregistered, we change back to
10055 * remapped mode, so we can re-use the current implementation
bb3541f1 10056 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10057 * int this case doesn't want to receive the interrupts.
10058 */
10059 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10060 if (ret)
10061 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10062 " fails: %d\n", irqfd->consumer.token, ret);
10063}
10064
10065int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10066 uint32_t guest_irq, bool set)
10067{
10068 if (!kvm_x86_ops->update_pi_irte)
10069 return -EINVAL;
10070
10071 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10072}
10073
52004014
FW		 10074bool kvm_vector_hashing_enabled(void)
10075{
10076 return vector_hashing;
10077}
10078EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10079
2d5ba19b
MT		 10080bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10081{
10082 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10083}
10084EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10085
10086
229456fc 10087EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10088EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10089EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10090EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10091EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10092EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10093EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10094EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10095EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10096EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 10097EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10098EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10099EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10100EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 10101EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 10102EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10103EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10104EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10105EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)