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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
52004014
FW		 126static bool __read_mostly vector_hashing = true;
127module_param(vector_hashing, bool, S_IRUGO);
128
893590c7 129static bool __read_mostly backwards_tsc_observed = false;
16a96021 130
18863bdd
AK		 131#define KVM_NR_SHARED_MSRS 16
132
133struct kvm_shared_msrs_global {
134 int nr;
2bf78fa7 135 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 136};
137
138struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
2bf78fa7
SY		 141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 145};
146
147static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 148static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 149
417bc304 150struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 161 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 164 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 165 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 166 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 167 { "request_irq", VCPU_STAT(request_irq_exits) },
168 { "irq_exits", VCPU_STAT(irq_exits) },
169 { "host_state_reload", VCPU_STAT(host_state_reload) },
170 { "efer_reload", VCPU_STAT(efer_reload) },
171 { "fpu_reload", VCPU_STAT(fpu_reload) },
172 { "insn_emulation", VCPU_STAT(insn_emulation) },
173 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 174 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 175 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 176 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
177 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
178 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
179 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
180 { "mmu_flooded", VM_STAT(mmu_flooded) },
181 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 182 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 183 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 184 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 185 { "largepages", VM_STAT(lpages) },
417bc304
HB		 186 { NULL }
187};
188
2acf923e
DC		 189u64 __read_mostly host_xcr0;
190
b6785def 191static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 192
af585b92
GN		 193static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
194{
195 int i;
196 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
197 vcpu->arch.apf.gfns[i] = ~0;
198}
199
18863bdd
AK		 200static void kvm_on_user_return(struct user_return_notifier *urn)
201{
202 unsigned slot;
18863bdd
AK		 203 struct kvm_shared_msrs *locals
204 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 205 struct kvm_shared_msr_values *values;
18863bdd
AK		 206
207 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 208 values = &locals->values[slot];
209 if (values->host != values->curr) {
210 wrmsrl(shared_msrs_global.msrs[slot], values->host);
211 values->curr = values->host;
18863bdd
AK		 212 }
213 }
214 locals->registered = false;
215 user_return_notifier_unregister(urn);
216}
217
2bf78fa7 218static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 219{
18863bdd 220 u64 value;
013f6a5d
MT		 221 unsigned int cpu = smp_processor_id();
222 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 223
2bf78fa7
SY		 224 /* only read, and nobody should modify it at this time,
225 * so don't need lock */
226 if (slot >= shared_msrs_global.nr) {
227 printk(KERN_ERR "kvm: invalid MSR slot!");
228 return;
229 }
230 rdmsrl_safe(msr, &value);
231 smsr->values[slot].host = value;
232 smsr->values[slot].curr = value;
233}
234
235void kvm_define_shared_msr(unsigned slot, u32 msr)
236{
0123be42 237 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 238 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 239 if (slot >= shared_msrs_global.nr)
240 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 241}
242EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
243
244static void kvm_shared_msr_cpu_online(void)
245{
246 unsigned i;
18863bdd
AK		 247
248 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 249 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 250}
251
8b3c3104 252int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 253{
013f6a5d
MT		 254 unsigned int cpu = smp_processor_id();
255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 256 int err;
18863bdd 257
2bf78fa7 258 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 259 return 0;
2bf78fa7 260 smsr->values[slot].curr = value;
8b3c3104
AH		 261 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
262 if (err)
263 return 1;
264
18863bdd
AK		 265 if (!smsr->registered) {
266 smsr->urn.on_user_return = kvm_on_user_return;
267 user_return_notifier_register(&smsr->urn);
268 smsr->registered = true;
269 }
8b3c3104 270 return 0;
18863bdd
AK		 271}
272EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
273
13a34e06 274static void drop_user_return_notifiers(void)
3548bab5 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 278
279 if (smsr->registered)
280 kvm_on_user_return(&smsr->urn);
281}
282
6866b83e
CO		 283u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
284{
8a5a87d9 285 return vcpu->arch.apic_base;
6866b83e
CO		 286}
287EXPORT_SYMBOL_GPL(kvm_get_apic_base);
288
58cb628d
JK		 289int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
290{
291 u64 old_state = vcpu->arch.apic_base &
292 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
293 u64 new_state = msr_info->data &
294 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
295 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
296 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
297
298 if (!msr_info->host_initiated &&
299 ((msr_info->data & reserved_bits) != 0 ||
300 new_state == X2APIC_ENABLE ||
301 (new_state == MSR_IA32_APICBASE_ENABLE &&
302 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
303 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
304 old_state == 0)))
305 return 1;
306
307 kvm_lapic_set_base(vcpu, msr_info->data);
308 return 0;
6866b83e
CO		 309}
310EXPORT_SYMBOL_GPL(kvm_set_apic_base);
311
2605fc21 312asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 313{
314 /* Fault while not rebooting. We want the trace. */
315 BUG();
316}
317EXPORT_SYMBOL_GPL(kvm_spurious_fault);
318
3fd28fce
ED		 319#define EXCPT_BENIGN 0
320#define EXCPT_CONTRIBUTORY 1
321#define EXCPT_PF 2
322
323static int exception_class(int vector)
324{
325 switch (vector) {
326 case PF_VECTOR:
327 return EXCPT_PF;
328 case DE_VECTOR:
329 case TS_VECTOR:
330 case NP_VECTOR:
331 case SS_VECTOR:
332 case GP_VECTOR:
333 return EXCPT_CONTRIBUTORY;
334 default:
335 break;
336 }
337 return EXCPT_BENIGN;
338}
339
d6e8c854
NA		 340#define EXCPT_FAULT 0
341#define EXCPT_TRAP 1
342#define EXCPT_ABORT 2
343#define EXCPT_INTERRUPT 3
344
345static int exception_type(int vector)
346{
347 unsigned int mask;
348
349 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
350 return EXCPT_INTERRUPT;
351
352 mask = 1 << vector;
353
354 /* #DB is trap, as instruction watchpoints are handled elsewhere */
355 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
356 return EXCPT_TRAP;
357
358 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
359 return EXCPT_ABORT;
360
361 /* Reserved exceptions will result in fault */
362 return EXCPT_FAULT;
363}
364
3fd28fce 365static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 366 unsigned nr, bool has_error, u32 error_code,
367 bool reinject)
3fd28fce
ED		 368{
369 u32 prev_nr;
370 int class1, class2;
371
3842d135
AK		 372 kvm_make_request(KVM_REQ_EVENT, vcpu);
373
3fd28fce
ED		 374 if (!vcpu->arch.exception.pending) {
375 queue:
3ffb2468
NA		 376 if (has_error && !is_protmode(vcpu))
377 has_error = false;
3fd28fce
ED		 378 vcpu->arch.exception.pending = true;
379 vcpu->arch.exception.has_error_code = has_error;
380 vcpu->arch.exception.nr = nr;
381 vcpu->arch.exception.error_code = error_code;
3f0fd292 382 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 383 return;
384 }
385
386 /* to check exception */
387 prev_nr = vcpu->arch.exception.nr;
388 if (prev_nr == DF_VECTOR) {
389 /* triple fault -> shutdown */
a8eeb04a 390 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 391 return;
392 }
393 class1 = exception_class(prev_nr);
394 class2 = exception_class(nr);
395 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
396 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
397 /* generate double fault per SDM Table 5-5 */
398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = true;
400 vcpu->arch.exception.nr = DF_VECTOR;
401 vcpu->arch.exception.error_code = 0;
402 } else
403 /* replace previous exception with a new one in a hope
404 that instruction re-execution will regenerate lost
405 exception */
406 goto queue;
407}
408
298101da
AK		 409void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
410{
ce7ddec4 411 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 412}
413EXPORT_SYMBOL_GPL(kvm_queue_exception);
414
ce7ddec4
JR		 415void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
416{
417 kvm_multiple_exception(vcpu, nr, false, 0, true);
418}
419EXPORT_SYMBOL_GPL(kvm_requeue_exception);
420
db8fcefa 421void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 422{
db8fcefa
AP		 423 if (err)
424 kvm_inject_gp(vcpu, 0);
425 else
426 kvm_x86_ops->skip_emulated_instruction(vcpu);
427}
428EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 429
6389ee94 430void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 431{
432 ++vcpu->stat.pf_guest;
6389ee94
AK		 433 vcpu->arch.cr2 = fault->address;
434 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 435}
27d6c865 436EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 437
ef54bcfe 438static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 439{
6389ee94
AK		 440 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
441 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 442 else
6389ee94 443 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 444
445 return fault->nested_page_fault;
d4f8cf66
JR		 446}
447
3419ffc8
SY		 448void kvm_inject_nmi(struct kvm_vcpu *vcpu)
449{
7460fb4a
AK		 450 atomic_inc(&vcpu->arch.nmi_queued);
451 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 452}
453EXPORT_SYMBOL_GPL(kvm_inject_nmi);
454
298101da
AK		 455void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
456{
ce7ddec4 457 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 458}
459EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
460
ce7ddec4
JR		 461void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
462{
463 kvm_multiple_exception(vcpu, nr, true, error_code, true);
464}
465EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
466
0a79b009
AK		 467/*
468 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
469 * a #GP and return false.
470 */
471bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 472{
0a79b009
AK		 473 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
474 return true;
475 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
476 return false;
298101da 477}
0a79b009 478EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 479
16f8a6f9
NA		 480bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
481{
482 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
483 return true;
484
485 kvm_queue_exception(vcpu, UD_VECTOR);
486 return false;
487}
488EXPORT_SYMBOL_GPL(kvm_require_dr);
489
ec92fe44
JR		 490/*
491 * This function will be used to read from the physical memory of the currently
54bf36aa 492 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 493 * can read from guest physical or from the guest's guest physical memory.
494 */
495int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
496 gfn_t ngfn, void *data, int offset, int len,
497 u32 access)
498{
54987b7a 499 struct x86_exception exception;
ec92fe44
JR		 500 gfn_t real_gfn;
501 gpa_t ngpa;
502
503 ngpa = gfn_to_gpa(ngfn);
54987b7a 504 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 505 if (real_gfn == UNMAPPED_GVA)
506 return -EFAULT;
507
508 real_gfn = gpa_to_gfn(real_gfn);
509
54bf36aa 510 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 511}
512EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
513
69b0049a 514static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 515 void *data, int offset, int len, u32 access)
516{
517 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
518 data, offset, len, access);
519}
520
a03490ed
CO		 521/*
522 * Load the pae pdptrs. Return true is they are all valid.
523 */
ff03a073 524int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 525{
526 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
527 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
528 int i;
529 int ret;
ff03a073 530 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 531
ff03a073
JR		 532 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
533 offset * sizeof(u64), sizeof(pdpte),
534 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 535 if (ret < 0) {
536 ret = 0;
537 goto out;
538 }
539 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 540 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 541 (pdpte[i] &
542 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 543 ret = 0;
544 goto out;
545 }
546 }
547 ret = 1;
548
ff03a073 549 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 550 __set_bit(VCPU_EXREG_PDPTR,
551 (unsigned long *)&vcpu->arch.regs_avail);
552 __set_bit(VCPU_EXREG_PDPTR,
553 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 554out:
a03490ed
CO		 555
556 return ret;
557}
cc4b6871 558EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 559
d835dfec
AK		 560static bool pdptrs_changed(struct kvm_vcpu *vcpu)
561{
ff03a073 562 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 563 bool changed = true;
3d06b8bf
JR		 564 int offset;
565 gfn_t gfn;
d835dfec
AK		 566 int r;
567
568 if (is_long_mode(vcpu) || !is_pae(vcpu))
569 return false;
570
6de4f3ad
AK		 571 if (!test_bit(VCPU_EXREG_PDPTR,
572 (unsigned long *)&vcpu->arch.regs_avail))
573 return true;
574
9f8fe504
AK		 575 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
576 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 577 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
578 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 579 if (r < 0)
580 goto out;
ff03a073 581 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 582out:
d835dfec
AK		 583
584 return changed;
585}
586
49a9b07e 587int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 588{
aad82703 589 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 590 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 591
f9a48e6a
AK		 592 cr0 |= X86_CR0_ET;
593
ab344828 594#ifdef CONFIG_X86_64
0f12244f
GN		 595 if (cr0 & 0xffffffff00000000UL)
596 return 1;
ab344828
GN		 597#endif
598
599 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 600
0f12244f
GN		 601 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
602 return 1;
a03490ed 603
0f12244f
GN		 604 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
605 return 1;
a03490ed
CO		 606
607 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
608#ifdef CONFIG_X86_64
f6801dff 609 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 610 int cs_db, cs_l;
611
0f12244f
GN		 612 if (!is_pae(vcpu))
613 return 1;
a03490ed 614 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 615 if (cs_l)
616 return 1;
a03490ed
CO		 617 } else
618#endif
ff03a073 619 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 620 kvm_read_cr3(vcpu)))
0f12244f 621 return 1;
a03490ed
CO		 622 }
623
ad756a16
MJ		 624 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
625 return 1;
626
a03490ed 627 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 628
d170c419 629 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 630 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 631 kvm_async_pf_hash_reset(vcpu);
632 }
e5f3f027 633
aad82703
SY		 634 if ((cr0 ^ old_cr0) & update_bits)
635 kvm_mmu_reset_context(vcpu);
b18d5431 636
879ae188
LE		 637 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
638 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
639 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 640 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
641
0f12244f
GN		 642 return 0;
643}
2d3ad1f4 644EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 645
2d3ad1f4 646void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 647{
49a9b07e 648 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 649}
2d3ad1f4 650EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 651
42bdf991
MT		 652static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
653{
654 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
655 !vcpu->guest_xcr0_loaded) {
656 /* kvm_set_xcr() also depends on this */
657 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
658 vcpu->guest_xcr0_loaded = 1;
659 }
660}
661
662static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
663{
664 if (vcpu->guest_xcr0_loaded) {
665 if (vcpu->arch.xcr0 != host_xcr0)
666 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
667 vcpu->guest_xcr0_loaded = 0;
668 }
669}
670
69b0049a 671static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 672{
56c103ec
LJ		 673 u64 xcr0 = xcr;
674 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 675 u64 valid_bits;
2acf923e
DC		 676
677 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
678 if (index != XCR_XFEATURE_ENABLED_MASK)
679 return 1;
d91cab78 680 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 681 return 1;
d91cab78 682 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 683 return 1;
46c34cb0
PB		 684
685 /*
686 * Do not allow the guest to set bits that we do not support
687 * saving. However, xcr0 bit 0 is always set, even if the
688 * emulated CPU does not support XSAVE (see fx_init).
689 */
d91cab78 690 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 691 if (xcr0 & ~valid_bits)
2acf923e 692 return 1;
46c34cb0 693
d91cab78
DH		 694 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
695 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 696 return 1;
697
d91cab78
DH		 698 if (xcr0 & XFEATURE_MASK_AVX512) {
699 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 700 return 1;
d91cab78 701 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 702 return 1;
703 }
2acf923e 704 vcpu->arch.xcr0 = xcr0;
56c103ec 705
d91cab78 706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 707 kvm_update_cpuid(vcpu);
2acf923e
DC		 708 return 0;
709}
710
711int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
712{
764bcbc5
Z		 713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 715 kvm_inject_gp(vcpu, 0);
716 return 1;
717 }
718 return 0;
719}
720EXPORT_SYMBOL_GPL(kvm_set_xcr);
721
a83b29c6 722int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 723{
fc78f519 724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 726 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 727
0f12244f
GN		 728 if (cr4 & CR4_RESERVED_BITS)
729 return 1;
a03490ed 730
2acf923e
DC		 731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
732 return 1;
733
c68b734f
YW		 734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
735 return 1;
736
97ec8c06
FW		 737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
738 return 1;
739
afcbf13f 740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 741 return 1;
742
b9baba86
HH		 743 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
744 return 1;
745
a03490ed 746 if (is_long_mode(vcpu)) {
0f12244f
GN		 747 if (!(cr4 & X86_CR4_PAE))
748 return 1;
a2edf57f
AK		 749 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
750 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 751 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
752 kvm_read_cr3(vcpu)))
0f12244f
GN		 753 return 1;
754
ad756a16
MJ		 755 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
756 if (!guest_cpuid_has_pcid(vcpu))
757 return 1;
758
759 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
760 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
761 return 1;
762 }
763
5e1746d6 764 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 765 return 1;
a03490ed 766
ad756a16
MJ		 767 if (((cr4 ^ old_cr4) & pdptr_bits) ||
768 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 769 kvm_mmu_reset_context(vcpu);
0f12244f 770
b9baba86 771 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 772 kvm_update_cpuid(vcpu);
2acf923e 773
0f12244f
GN		 774 return 0;
775}
2d3ad1f4 776EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 777
2390218b 778int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 779{
ac146235 780#ifdef CONFIG_X86_64
9d88fca7 781 cr3 &= ~CR3_PCID_INVD;
ac146235 782#endif
9d88fca7 783
9f8fe504 784 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 785 kvm_mmu_sync_roots(vcpu);
77c3913b 786 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 787 return 0;
d835dfec
AK		 788 }
789
a03490ed 790 if (is_long_mode(vcpu)) {
d9f89b88
JK		 791 if (cr3 & CR3_L_MODE_RESERVED_BITS)
792 return 1;
793 } else if (is_pae(vcpu) && is_paging(vcpu) &&
794 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 795 return 1;
a03490ed 796
0f12244f 797 vcpu->arch.cr3 = cr3;
aff48baa 798 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 799 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 803
eea1cff9 804int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 805{
0f12244f
GN		 806 if (cr8 & CR8_RESERVED_BITS)
807 return 1;
35754c98 808 if (lapic_in_kernel(vcpu))
a03490ed
CO		 809 kvm_lapic_set_tpr(vcpu, cr8);
810 else
ad312c7c 811 vcpu->arch.cr8 = cr8;
0f12244f
GN		 812 return 0;
813}
2d3ad1f4 814EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 815
2d3ad1f4 816unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 817{
35754c98 818 if (lapic_in_kernel(vcpu))
a03490ed
CO		 819 return kvm_lapic_get_cr8(vcpu);
820 else
ad312c7c 821 return vcpu->arch.cr8;
a03490ed 822}
2d3ad1f4 823EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 824
ae561ede
NA		 825static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
826{
827 int i;
828
829 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
830 for (i = 0; i < KVM_NR_DB_REGS; i++)
831 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
833 }
834}
835
73aaf249
JK		 836static void kvm_update_dr6(struct kvm_vcpu *vcpu)
837{
838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
839 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
840}
841
c8639010
JK		 842static void kvm_update_dr7(struct kvm_vcpu *vcpu)
843{
844 unsigned long dr7;
845
846 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
847 dr7 = vcpu->arch.guest_debug_dr7;
848 else
849 dr7 = vcpu->arch.dr7;
850 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 851 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
852 if (dr7 & DR7_BP_EN_MASK)
853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 854}
855
6f43ed01
NA		 856static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
857{
858 u64 fixed = DR6_FIXED_1;
859
860 if (!guest_cpuid_has_rtm(vcpu))
861 fixed |= DR6_RTM;
862 return fixed;
863}
864
338dbc97 865static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 866{
867 switch (dr) {
868 case 0 ... 3:
869 vcpu->arch.db[dr] = val;
870 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
871 vcpu->arch.eff_db[dr] = val;
872 break;
873 case 4:
020df079
GN		 874 /* fall through */
875 case 6:
338dbc97
GN		 876 if (val & 0xffffffff00000000ULL)
877 return -1; /* #GP */
6f43ed01 878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 879 kvm_update_dr6(vcpu);
020df079
GN		 880 break;
881 case 5:
020df079
GN		 882 /* fall through */
883 default: /* 7 */
338dbc97
GN		 884 if (val & 0xffffffff00000000ULL)
885 return -1; /* #GP */
020df079 886 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 887 kvm_update_dr7(vcpu);
020df079
GN		 888 break;
889 }
890
891 return 0;
892}
338dbc97
GN		 893
894int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
895{
16f8a6f9 896 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 897 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 898 return 1;
899 }
900 return 0;
338dbc97 901}
020df079
GN		 902EXPORT_SYMBOL_GPL(kvm_set_dr);
903
16f8a6f9 904int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 905{
906 switch (dr) {
907 case 0 ... 3:
908 *val = vcpu->arch.db[dr];
909 break;
910 case 4:
020df079
GN		 911 /* fall through */
912 case 6:
73aaf249
JK		 913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
914 *val = vcpu->arch.dr6;
915 else
916 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 917 break;
918 case 5:
020df079
GN		 919 /* fall through */
920 default: /* 7 */
921 *val = vcpu->arch.dr7;
922 break;
923 }
338dbc97
GN		 924 return 0;
925}
020df079
GN		 926EXPORT_SYMBOL_GPL(kvm_get_dr);
927
022cd0e8
AK		 928bool kvm_rdpmc(struct kvm_vcpu *vcpu)
929{
930 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
931 u64 data;
932 int err;
933
c6702c9d 934 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 935 if (err)
936 return err;
937 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
938 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
939 return err;
940}
941EXPORT_SYMBOL_GPL(kvm_rdpmc);
942
043405e1
CO		 943/*
944 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
945 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
946 *
947 * This list is modified at module load time to reflect the
e3267cbb 948 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 949 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
950 * may depend on host virtualization features rather than host cpu features.
043405e1 951 */
e3267cbb 952
043405e1
CO		 953static u32 msrs_to_save[] = {
954 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 955 MSR_STAR,
043405e1
CO		 956#ifdef CONFIG_X86_64
957 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
958#endif
b3897a49 959 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 960 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 961};
962
963static unsigned num_msrs_to_save;
964
62ef68bb
PB		 965static u32 emulated_msrs[] = {
966 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
967 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
968 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
969 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 970 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
971 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 972 HV_X64_MSR_RESET,
11c4b1ca 973 HV_X64_MSR_VP_INDEX,
9eec50b8 974 HV_X64_MSR_VP_RUNTIME,
5c919412 975 HV_X64_MSR_SCONTROL,
1f4b34f8 976 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 977 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
978 MSR_KVM_PV_EOI_EN,
979
ba904635 980 MSR_IA32_TSC_ADJUST,
a3e06bbe 981 MSR_IA32_TSCDEADLINE,
043405e1 982 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 983 MSR_IA32_MCG_STATUS,
984 MSR_IA32_MCG_CTL,
64d60670 985 MSR_IA32_SMBASE,
043405e1
CO		 986};
987
62ef68bb
PB		 988static unsigned num_emulated_msrs;
989
384bb783 990bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 991{
b69e8cae 992 if (efer & efer_reserved_bits)
384bb783 993 return false;
15c4a640 994
1b2fd70c
AG		 995 if (efer & EFER_FFXSR) {
996 struct kvm_cpuid_entry2 *feat;
997
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 999 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1000 return false;
1b2fd70c
AG		 1001 }
1002
d8017474
AG		 1003 if (efer & EFER_SVME) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1007 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1008 return false;
d8017474
AG		 1009 }
1010
384bb783
JK		 1011 return true;
1012}
1013EXPORT_SYMBOL_GPL(kvm_valid_efer);
1014
1015static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1016{
1017 u64 old_efer = vcpu->arch.efer;
1018
1019 if (!kvm_valid_efer(vcpu, efer))
1020 return 1;
1021
1022 if (is_paging(vcpu)
1023 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1024 return 1;
1025
15c4a640 1026 efer &= ~EFER_LMA;
f6801dff 1027 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1028
a3d204e2
SY		 1029 kvm_x86_ops->set_efer(vcpu, efer);
1030
aad82703
SY		 1031 /* Update reserved bits */
1032 if ((efer ^ old_efer) & EFER_NX)
1033 kvm_mmu_reset_context(vcpu);
1034
b69e8cae 1035 return 0;
15c4a640
CO		 1036}
1037
f2b4b7dd
JR		 1038void kvm_enable_efer_bits(u64 mask)
1039{
1040 efer_reserved_bits &= ~mask;
1041}
1042EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1043
15c4a640
CO		 1044/*
1045 * Writes msr value into into the appropriate "register".
1046 * Returns 0 on success, non-0 otherwise.
1047 * Assumes vcpu_load() was already called.
1048 */
8fe8ab46 1049int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1050{
854e8bb1
NA		 1051 switch (msr->index) {
1052 case MSR_FS_BASE:
1053 case MSR_GS_BASE:
1054 case MSR_KERNEL_GS_BASE:
1055 case MSR_CSTAR:
1056 case MSR_LSTAR:
1057 if (is_noncanonical_address(msr->data))
1058 return 1;
1059 break;
1060 case MSR_IA32_SYSENTER_EIP:
1061 case MSR_IA32_SYSENTER_ESP:
1062 /*
1063 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1064 * non-canonical address is written on Intel but not on
1065 * AMD (which ignores the top 32-bits, because it does
1066 * not implement 64-bit SYSENTER).
1067 *
1068 * 64-bit code should hence be able to write a non-canonical
1069 * value on AMD. Making the address canonical ensures that
1070 * vmentry does not fail on Intel after writing a non-canonical
1071 * value, and that something deterministic happens if the guest
1072 * invokes 64-bit SYSENTER.
1073 */
1074 msr->data = get_canonical(msr->data);
1075 }
8fe8ab46 1076 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1077}
854e8bb1 1078EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1079
313a3dc7
CO		 1080/*
1081 * Adapt set_msr() to msr_io()'s calling convention
1082 */
609e36d3
PB		 1083static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1084{
1085 struct msr_data msr;
1086 int r;
1087
1088 msr.index = index;
1089 msr.host_initiated = true;
1090 r = kvm_get_msr(vcpu, &msr);
1091 if (r)
1092 return r;
1093
1094 *data = msr.data;
1095 return 0;
1096}
1097
313a3dc7
CO		 1098static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1099{
8fe8ab46
WA		 1100 struct msr_data msr;
1101
1102 msr.data = *data;
1103 msr.index = index;
1104 msr.host_initiated = true;
1105 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1106}
1107
16e8d74d
MT		 1108#ifdef CONFIG_X86_64
1109struct pvclock_gtod_data {
1110 seqcount_t seq;
1111
1112 struct { /* extract of a clocksource struct */
1113 int vclock_mode;
1114 cycle_t cycle_last;
1115 cycle_t mask;
1116 u32 mult;
1117 u32 shift;
1118 } clock;
1119
cbcf2dd3
TG		 1120 u64 boot_ns;
1121 u64 nsec_base;
16e8d74d
MT		 1122};
1123
1124static struct pvclock_gtod_data pvclock_gtod_data;
1125
1126static void update_pvclock_gtod(struct timekeeper *tk)
1127{
1128 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1129 u64 boot_ns;
1130
876e7881 1131 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1132
1133 write_seqcount_begin(&vdata->seq);
1134
1135 /* copy pvclock gtod data */
876e7881
PZ		 1136 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1137 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1138 vdata->clock.mask = tk->tkr_mono.mask;
1139 vdata->clock.mult = tk->tkr_mono.mult;
1140 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1141
cbcf2dd3 1142 vdata->boot_ns = boot_ns;
876e7881 1143 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1144
1145 write_seqcount_end(&vdata->seq);
1146}
1147#endif
1148
bab5bb39
NK		 1149void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1150{
1151 /*
1152 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1153 * vcpu_enter_guest. This function is only called from
1154 * the physical CPU that is running vcpu.
1155 */
1156 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1157}
16e8d74d 1158
18068523
GOC		 1159static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1160{
9ed3c444
AK		 1161 int version;
1162 int r;
50d0a0f9 1163 struct pvclock_wall_clock wc;
923de3cf 1164 struct timespec boot;
18068523
GOC		 1165
1166 if (!wall_clock)
1167 return;
1168
9ed3c444
AK		 1169 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1170 if (r)
1171 return;
1172
1173 if (version & 1)
1174 ++version; /* first time write, random junk */
1175
1176 ++version;
18068523 1177
1dab1345
NK		 1178 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1179 return;
18068523 1180
50d0a0f9
GH		 1181 /*
1182 * The guest calculates current wall clock time by adding
34c238a1 1183 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1184 * wall clock specified here. guest system time equals host
1185 * system time for us, thus we must fill in host boot time here.
1186 */
923de3cf 1187 getboottime(&boot);
50d0a0f9 1188
4b648665
BR		 1189 if (kvm->arch.kvmclock_offset) {
1190 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1191 boot = timespec_sub(boot, ts);
1192 }
50d0a0f9
GH		 1193 wc.sec = boot.tv_sec;
1194 wc.nsec = boot.tv_nsec;
1195 wc.version = version;
18068523
GOC		 1196
1197 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1198
1199 version++;
1200 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1201}
1202
50d0a0f9
GH		 1203static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1204{
b51012de
PB		 1205 do_shl32_div32(dividend, divisor);
1206 return dividend;
50d0a0f9
GH		 1207}
1208
3ae13faa 1209static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1210 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1211{
5f4e3f88 1212 uint64_t scaled64;
50d0a0f9
GH		 1213 int32_t shift = 0;
1214 uint64_t tps64;
1215 uint32_t tps32;
1216
3ae13faa
PB		 1217 tps64 = base_hz;
1218 scaled64 = scaled_hz;
50933623 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1220 tps64 >>= 1;
1221 shift--;
1222 }
1223
1224 tps32 = (uint32_t)tps64;
50933623
JK		 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1227 scaled64 >>= 1;
1228 else
1229 tps32 <<= 1;
50d0a0f9
GH		 1230 shift++;
1231 }
1232
5f4e3f88
ZA		 1233 *pshift = shift;
1234 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1235
3ae13faa
PB		 1236 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1237 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1238}
1239
d828199e 1240#ifdef CONFIG_X86_64
16e8d74d 1241static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1242#endif
16e8d74d 1243
c8076604 1244static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1245static unsigned long max_tsc_khz;
c8076604 1246
cc578287 1247static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1248{
cc578287
ZA		 1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1251}
1252
cc578287 1253static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1254{
cc578287
ZA		 1255 u64 v = (u64)khz * (1000000 + ppm);
1256 do_div(v, 1000000);
1257 return v;
1e993611
JR		 1258}
1259
381d585c
HZ		 1260static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261{
1262 u64 ratio;
1263
1264 /* Guest TSC same frequency as host TSC? */
1265 if (!scale) {
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 return 0;
1268 }
1269
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1275 return 0;
1276 } else {
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1278 return -1;
1279 }
1280 }
1281
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1285
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1288 user_tsc_khz);
1289 return -1;
1290 }
1291
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1293 return 0;
1294}
1295
4941b8cb 1296static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1297{
cc578287
ZA		 1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
217fc9cf 1300
03ba32ca 1301 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1302 if (user_tsc_khz == 0) {
ad721883
HZ		 1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1305 return -1;
ad721883 1306 }
03ba32ca 1307
c285545f 1308 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1309 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1312 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1313
1314 /*
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1319 */
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1322 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1324 use_scaling = 1;
1325 }
4941b8cb 1326 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1327}
1328
1329static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330{
e26101b1 1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
e26101b1 1334 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1335 return tsc;
1336}
1337
69b0049a 1338static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1339{
1340#ifdef CONFIG_X86_64
1341 bool vcpus_matched;
b48aa97e
MT		 1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1347
7f187922
MT		 1348 /*
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1351 *
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1355 */
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1363#endif
1364}
1365
ba904635
WA		 1366static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367{
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370}
1371
35181e86
HZ		 1372/*
1373 * Multiply tsc by a fixed point number represented by ratio.
1374 *
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1379 *
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 */
1382static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383{
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1385}
1386
1387u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1388{
1389 u64 _tsc = tsc;
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1394
1395 return _tsc;
1396}
1397EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398
07c1419a
HZ		 1399static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400{
1401 u64 tsc;
1402
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404
1405 return target_tsc - tsc;
1406}
1407
4ba76538
HZ		 1408u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409{
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411}
1412EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413
8fe8ab46 1414void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1415{
1416 struct kvm *kvm = vcpu->kvm;
f38e098f 1417 u64 offset, ns, elapsed;
99e3e30a 1418 unsigned long flags;
02626b6a 1419 s64 usdiff;
b48aa97e 1420 bool matched;
0d3da0d2 1421 bool already_matched;
8fe8ab46 1422 u64 data = msr->data;
99e3e30a 1423
038f8c11 1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1425 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1426 ns = get_kernel_ns();
f38e098f 1427 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1428
03ba32ca 1429 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1430 int faulted = 0;
1431
03ba32ca
MT		 1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1434#ifdef CONFIG_X86_64
03ba32ca 1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1436#else
03ba32ca 1437 /* do_div() only does unsigned */
8915aa27
MT		 1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1441 "3:\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1444 " jmp 3b\n"
1445 ".previous\n"
1446
1447 _ASM_EXTABLE(1b, 4b)
1448
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1451
5d3cb0f6 1452#endif
03ba32ca
MT		 1453 do_div(elapsed, 1000);
1454 usdiff -= elapsed;
1455 if (usdiff < 0)
1456 usdiff = -usdiff;
8915aa27
MT		 1457
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 if (faulted)
1460 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1461 } else
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1463
1464 /*
5d3cb0f6
ZA		 1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1468 *
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1473 */
02626b6a 1474 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1476 if (!check_tsc_unstable()) {
e26101b1 1477 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 } else {
857e4099 1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1481 data += delta;
07c1419a 1482 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1484 }
b48aa97e 1485 matched = true;
0d3da0d2 1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1487 } else {
1488 /*
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
4a969980 1493 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1494 *
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1496 */
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1501 matched = false;
0d3da0d2 1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1503 kvm->arch.cur_tsc_generation, data);
f38e098f 1504 }
e26101b1
ZA		 1505
1506 /*
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1509 */
f38e098f
ZA		 1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
5d3cb0f6 1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1513
b183aa58 1514 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1515
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520
ba904635
WA		 1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1525
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1527 if (!matched) {
b48aa97e 1528 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1531 }
b48aa97e
MT		 1532
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1535}
e26101b1 1536
99e3e30a
ZA		 1537EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538
58ea6767
HZ		 1539static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1540 s64 adjustment)
1541{
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1543}
1544
1545static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546{
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551}
1552
d828199e
MT		 1553#ifdef CONFIG_X86_64
1554
1555static cycle_t read_tsc(void)
1556{
03b9730b
AL		 1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1559
1560 if (likely(ret >= last))
1561 return ret;
1562
1563 /*
1564 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1565 * predictable (it's just a function of time and the likely is
d828199e
MT		 1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1570 */
1571 asm volatile ("");
1572 return last;
1573}
1574
1575static inline u64 vgettsc(cycle_t *cycle_now)
1576{
1577 long v;
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579
1580 *cycle_now = read_tsc();
1581
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1584}
1585
cbcf2dd3 1586static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1587{
cbcf2dd3 1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1589 unsigned long seq;
d828199e 1590 int mode;
cbcf2dd3 1591 u64 ns;
d828199e 1592
d828199e
MT		 1593 do {
1594 seq = read_seqcount_begin(&gtod->seq);
1595 mode = gtod->clock.vclock_mode;
cbcf2dd3 1596 ns = gtod->nsec_base;
d828199e
MT		 1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
cbcf2dd3 1599 ns += gtod->boot_ns;
d828199e 1600 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1601 *t = ns;
d828199e
MT		 1602
1603 return mode;
1604}
1605
1606/* returns true if host is using tsc clocksource */
1607static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608{
d828199e
MT		 1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1611 return false;
1612
cbcf2dd3 1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1614}
1615#endif
1616
1617/*
1618 *
b48aa97e
MT		 1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
d828199e
MT		 1622 * CPUs at the next numbered event.
1623 *
1624 * "timespecX" represents host monotonic time. "tscX" represents
1625 * RDTSC value.
1626 *
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 *
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1631 * | tsc1 = tsc0 + M
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 *
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1638 *
1639 * - ret0 < ret1
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * ...
1642 * - 0 < N - M => M < N
1643 *
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1648 *
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1652 * in lockstep.
1653 *
b48aa97e 1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1655 *
1656 */
1657
1658static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659{
1660#ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1662 int vclock_mode;
b48aa97e
MT		 1663 bool host_tsc_clocksource, vcpus_matched;
1664
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1667
1668 /*
1669 * If the host uses TSC clock, then passthrough TSC as stable
1670 * to the guest.
1671 */
b48aa97e 1672 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1675
16a96021 1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1679
d828199e
MT		 1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1682
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1685 vcpus_matched);
d828199e
MT		 1686#endif
1687}
1688
2860c4b1
PB		 1689void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1690{
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1692}
1693
2e762ff7
MT		 1694static void kvm_gen_update_masterclock(struct kvm *kvm)
1695{
1696#ifdef CONFIG_X86_64
1697 int i;
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1700
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1705
1706 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1708
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1712
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1714#endif
1715}
1716
34c238a1 1717static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1718{
78db6a50 1719 unsigned long flags, tgt_tsc_khz;
18068523 1720 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1721 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1722 s64 kernel_ns;
d828199e 1723 u64 tsc_timestamp, host_tsc;
0b79459b 1724 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1725 u8 pvclock_flags;
d828199e
MT		 1726 bool use_master_clock;
1727
1728 kernel_ns = 0;
1729 host_tsc = 0;
18068523 1730
d828199e
MT		 1731 /*
1732 * If the host uses TSC clock, then passthrough TSC as stable
1733 * to the guest.
1734 */
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1740 }
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1742
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
78db6a50
PB		 1745 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1746 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1749 return 1;
1750 }
d828199e 1751 if (!use_master_clock) {
4ea1636b 1752 host_tsc = rdtsc();
d828199e
MT		 1753 kernel_ns = get_kernel_ns();
1754 }
1755
4ba76538 1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1757
c285545f
ZA		 1758 /*
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1766 * very slowly.
1767 */
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
f1e2b260 1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1772 tsc_timestamp = tsc;
1773 }
50d0a0f9
GH		 1774 }
1775
18068523
GOC		 1776 local_irq_restore(flags);
1777
0b79459b 1778 if (!vcpu->pv_time_enabled)
c285545f 1779 return 0;
18068523 1780
78db6a50
PB		 1781 if (kvm_has_tsc_control)
1782 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1783
1784 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1785 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1786 &vcpu->hv_clock.tsc_shift,
1787 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1788 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1789 }
1790
1791 /* With all the info we got, fill in the values */
1d5f066e 1792 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1793 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1794 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1795
09a0c3f1
OH		 1796 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1797 &guest_hv_clock, sizeof(guest_hv_clock))))
1798 return 0;
1799
5dca0d91
RK		 1800 /* This VCPU is paused, but it's legal for a guest to read another
1801 * VCPU's kvmclock, so we really have to follow the specification where
1802 * it says that version is odd if data is being modified, and even after
1803 * it is consistent.
1804 *
1805 * Version field updates must be kept separate. This is because
1806 * kvm_write_guest_cached might use a "rep movs" instruction, and
1807 * writes within a string instruction are weakly ordered. So there
1808 * are three writes overall.
1809 *
1810 * As a small optimization, only write the version field in the first
1811 * and third write. The vcpu->pv_time cache is still valid, because the
1812 * version field is the first in the struct.
18068523 1813 */
5dca0d91
RK		 1814 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1815
1816 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1818 &vcpu->hv_clock,
1819 sizeof(vcpu->hv_clock.version));
1820
1821 smp_wmb();
78c0337a
MT		 1822
1823 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1824 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1825
1826 if (vcpu->pvclock_set_guest_stopped_request) {
1827 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1828 vcpu->pvclock_set_guest_stopped_request = false;
1829 }
1830
d828199e
MT		 1831 /* If the host uses TSC clocksource, then it is stable */
1832 if (use_master_clock)
1833 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1834
78c0337a
MT		 1835 vcpu->hv_clock.flags = pvclock_flags;
1836
ce1a5e60
DM		 1837 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1838
0b79459b
AH		 1839 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1840 &vcpu->hv_clock,
1841 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1842
1843 smp_wmb();
1844
1845 vcpu->hv_clock.version++;
1846 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1847 &vcpu->hv_clock,
1848 sizeof(vcpu->hv_clock.version));
8cfdc000 1849 return 0;
c8076604
GH		 1850}
1851
0061d53d
MT		 1852/*
1853 * kvmclock updates which are isolated to a given vcpu, such as
1854 * vcpu->cpu migration, should not allow system_timestamp from
1855 * the rest of the vcpus to remain static. Otherwise ntp frequency
1856 * correction applies to one vcpu's system_timestamp but not
1857 * the others.
1858 *
1859 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1860 * We need to rate-limit these requests though, as they can
1861 * considerably slow guests that have a large number of vcpus.
1862 * The time for a remote vcpu to update its kvmclock is bound
1863 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1864 */
1865
7e44e449
AJ		 1866#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1867
1868static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1869{
1870 int i;
7e44e449
AJ		 1871 struct delayed_work *dwork = to_delayed_work(work);
1872 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1873 kvmclock_update_work);
1874 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1875 struct kvm_vcpu *vcpu;
1876
1877 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1879 kvm_vcpu_kick(vcpu);
1880 }
1881}
1882
7e44e449
AJ		 1883static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1884{
1885 struct kvm *kvm = v->kvm;
1886
105b21bb 1887 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1888 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1889 KVMCLOCK_UPDATE_DELAY);
1890}
1891
332967a3
AJ		 1892#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1893
1894static void kvmclock_sync_fn(struct work_struct *work)
1895{
1896 struct delayed_work *dwork = to_delayed_work(work);
1897 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1898 kvmclock_sync_work);
1899 struct kvm *kvm = container_of(ka, struct kvm, arch);
1900
630994b3
MT		 1901 if (!kvmclock_periodic_sync)
1902 return;
1903
332967a3
AJ		 1904 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1905 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1906 KVMCLOCK_SYNC_PERIOD);
1907}
1908
890ca9ae 1909static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1910{
890ca9ae
HY		 1911 u64 mcg_cap = vcpu->arch.mcg_cap;
1912 unsigned bank_num = mcg_cap & 0xff;
1913
15c4a640 1914 switch (msr) {
15c4a640 1915 case MSR_IA32_MCG_STATUS:
890ca9ae 1916 vcpu->arch.mcg_status = data;
15c4a640 1917 break;
c7ac679c 1918 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1919 if (!(mcg_cap & MCG_CTL_P))
1920 return 1;
1921 if (data != 0 && data != ~(u64)0)
1922 return -1;
1923 vcpu->arch.mcg_ctl = data;
1924 break;
1925 default:
1926 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1927 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1928 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1929 /* only 0 or all 1s can be written to IA32_MCi_CTL
1930 * some Linux kernels though clear bit 10 in bank 4 to
1931 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1932 * this to avoid an uncatched #GP in the guest
1933 */
890ca9ae 1934 if ((offset & 0x3) == 0 &&
114be429 1935 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1936 return -1;
1937 vcpu->arch.mce_banks[offset] = data;
1938 break;
1939 }
1940 return 1;
1941 }
1942 return 0;
1943}
1944
ffde22ac
ES		 1945static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1946{
1947 struct kvm *kvm = vcpu->kvm;
1948 int lm = is_long_mode(vcpu);
1949 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1950 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1951 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1952 : kvm->arch.xen_hvm_config.blob_size_32;
1953 u32 page_num = data & ~PAGE_MASK;
1954 u64 page_addr = data & PAGE_MASK;
1955 u8 *page;
1956 int r;
1957
1958 r = -E2BIG;
1959 if (page_num >= blob_size)
1960 goto out;
1961 r = -ENOMEM;
ff5c2c03
SL		 1962 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1963 if (IS_ERR(page)) {
1964 r = PTR_ERR(page);
ffde22ac 1965 goto out;
ff5c2c03 1966 }
54bf36aa 1967 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1968 goto out_free;
1969 r = 0;
1970out_free:
1971 kfree(page);
1972out:
1973 return r;
1974}
1975
344d9588
GN		 1976static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1977{
1978 gpa_t gpa = data & ~0x3f;
1979
4a969980 1980 /* Bits 2:5 are reserved, Should be zero */
6adba527 1981 if (data & 0x3c)
344d9588
GN		 1982 return 1;
1983
1984 vcpu->arch.apf.msr_val = data;
1985
1986 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1987 kvm_clear_async_pf_completion_queue(vcpu);
1988 kvm_async_pf_hash_reset(vcpu);
1989 return 0;
1990 }
1991
8f964525
AH		 1992 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1993 sizeof(u32)))
344d9588
GN		 1994 return 1;
1995
6adba527 1996 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1997 kvm_async_pf_wakeup_all(vcpu);
1998 return 0;
1999}
2000
12f9a48f
GC		 2001static void kvmclock_reset(struct kvm_vcpu *vcpu)
2002{
0b79459b 2003 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2004}
2005
c9aaa895
GC		 2006static void record_steal_time(struct kvm_vcpu *vcpu)
2007{
2008 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2009 return;
2010
2011 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2012 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2013 return;
2014
35f3fae1
WL		 2015 if (vcpu->arch.st.steal.version & 1)
2016 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2017
2018 vcpu->arch.st.steal.version += 1;
2019
2020 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2021 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2022
2023 smp_wmb();
2024
c54cdf14
LC		 2025 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2026 vcpu->arch.st.last_steal;
2027 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2028
2029 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2030 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2031
2032 smp_wmb();
2033
2034 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2035
2036 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2037 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2038}
2039
8fe8ab46 2040int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2041{
5753785f 2042 bool pr = false;
8fe8ab46
WA		 2043 u32 msr = msr_info->index;
2044 u64 data = msr_info->data;
5753785f 2045
15c4a640 2046 switch (msr) {
2e32b719
BP		 2047 case MSR_AMD64_NB_CFG:
2048 case MSR_IA32_UCODE_REV:
2049 case MSR_IA32_UCODE_WRITE:
2050 case MSR_VM_HSAVE_PA:
2051 case MSR_AMD64_PATCH_LOADER:
2052 case MSR_AMD64_BU_CFG2:
2053 break;
2054
15c4a640 2055 case MSR_EFER:
b69e8cae 2056 return set_efer(vcpu, data);
8f1589d9
AP		 2057 case MSR_K7_HWCR:
2058 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2059 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2060 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2061 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2062 if (data != 0) {
a737f256
CD		 2063 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2064 data);
8f1589d9
AP		 2065 return 1;
2066 }
15c4a640 2067 break;
f7c6d140
AP		 2068 case MSR_FAM10H_MMIO_CONF_BASE:
2069 if (data != 0) {
a737f256
CD		 2070 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2071 "0x%llx\n", data);
f7c6d140
AP		 2072 return 1;
2073 }
15c4a640 2074 break;
b5e2fec0
AG		 2075 case MSR_IA32_DEBUGCTLMSR:
2076 if (!data) {
2077 /* We support the non-activated case already */
2078 break;
2079 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2080 /* Values other than LBR and BTF are vendor-specific,
2081 thus reserved and should throw a #GP */
2082 return 1;
2083 }
a737f256
CD		 2084 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2085 __func__, data);
b5e2fec0 2086 break;
9ba075a6 2087 case 0x200 ... 0x2ff:
ff53604b 2088 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2089 case MSR_IA32_APICBASE:
58cb628d 2090 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2091 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2092 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2093 case MSR_IA32_TSCDEADLINE:
2094 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2095 break;
ba904635
WA		 2096 case MSR_IA32_TSC_ADJUST:
2097 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2098 if (!msr_info->host_initiated) {
d913b904 2099 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2100 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2101 }
2102 vcpu->arch.ia32_tsc_adjust_msr = data;
2103 }
2104 break;
15c4a640 2105 case MSR_IA32_MISC_ENABLE:
ad312c7c 2106 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2107 break;
64d60670
PB		 2108 case MSR_IA32_SMBASE:
2109 if (!msr_info->host_initiated)
2110 return 1;
2111 vcpu->arch.smbase = data;
2112 break;
11c6bffa 2113 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2114 case MSR_KVM_WALL_CLOCK:
2115 vcpu->kvm->arch.wall_clock = data;
2116 kvm_write_wall_clock(vcpu->kvm, data);
2117 break;
11c6bffa 2118 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2119 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2120 u64 gpa_offset;
54750f2c
MT		 2121 struct kvm_arch *ka = &vcpu->kvm->arch;
2122
12f9a48f 2123 kvmclock_reset(vcpu);
18068523 2124
54750f2c
MT		 2125 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2126 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2127
2128 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2129 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2130 &vcpu->requests);
2131
2132 ka->boot_vcpu_runs_old_kvmclock = tmp;
2133 }
2134
18068523 2135 vcpu->arch.time = data;
0061d53d 2136 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2137
2138 /* we verify if the enable bit is set... */
2139 if (!(data & 1))
2140 break;
2141
0b79459b 2142 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2143
0b79459b 2144 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2145 &vcpu->arch.pv_time, data & ~1ULL,
2146 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2147 vcpu->arch.pv_time_enabled = false;
2148 else
2149 vcpu->arch.pv_time_enabled = true;
32cad84f 2150
18068523
GOC		 2151 break;
2152 }
344d9588
GN		 2153 case MSR_KVM_ASYNC_PF_EN:
2154 if (kvm_pv_enable_async_pf(vcpu, data))
2155 return 1;
2156 break;
c9aaa895
GC		 2157 case MSR_KVM_STEAL_TIME:
2158
2159 if (unlikely(!sched_info_on()))
2160 return 1;
2161
2162 if (data & KVM_STEAL_RESERVED_MASK)
2163 return 1;
2164
2165 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2166 data & KVM_STEAL_VALID_BITS,
2167 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2168 return 1;
2169
2170 vcpu->arch.st.msr_val = data;
2171
2172 if (!(data & KVM_MSR_ENABLED))
2173 break;
2174
c9aaa895
GC		 2175 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2176
2177 break;
ae7a2a3f
MT		 2178 case MSR_KVM_PV_EOI_EN:
2179 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2180 return 1;
2181 break;
c9aaa895 2182
890ca9ae
HY		 2183 case MSR_IA32_MCG_CTL:
2184 case MSR_IA32_MCG_STATUS:
81760dcc 2185 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2186 return set_msr_mce(vcpu, msr, data);
71db6023 2187
6912ac32
WH		 2188 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2189 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2190 pr = true; /* fall through */
2191 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2192 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2193 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2194 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2195
2196 if (pr || data != 0)
a737f256
CD		 2197 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2198 "0x%x data 0x%llx\n", msr, data);
5753785f 2199 break;
84e0cefa
JS		 2200 case MSR_K7_CLK_CTL:
2201 /*
2202 * Ignore all writes to this no longer documented MSR.
2203 * Writes are only relevant for old K7 processors,
2204 * all pre-dating SVM, but a recommended workaround from
4a969980 2205 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2206 * affected processor models on the command line, hence
2207 * the need to ignore the workaround.
2208 */
2209 break;
55cd8e5a 2210 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2211 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2212 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2213 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2214 return kvm_hv_set_msr_common(vcpu, msr, data,
2215 msr_info->host_initiated);
91c9c3ed 2216 case MSR_IA32_BBL_CR_CTL3:
2217 /* Drop writes to this legacy MSR -- see rdmsr
2218 * counterpart for further detail.
2219 */
a737f256 2220 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2221 break;
2b036c6b
BO		 2222 case MSR_AMD64_OSVW_ID_LENGTH:
2223 if (!guest_cpuid_has_osvw(vcpu))
2224 return 1;
2225 vcpu->arch.osvw.length = data;
2226 break;
2227 case MSR_AMD64_OSVW_STATUS:
2228 if (!guest_cpuid_has_osvw(vcpu))
2229 return 1;
2230 vcpu->arch.osvw.status = data;
2231 break;
15c4a640 2232 default:
ffde22ac
ES		 2233 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2234 return xen_hvm_config(vcpu, data);
c6702c9d 2235 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2236 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2237 if (!ignore_msrs) {
a737f256
CD		 2238 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2239 msr, data);
ed85c068
AP		 2240 return 1;
2241 } else {
a737f256
CD		 2242 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2243 msr, data);
ed85c068
AP		 2244 break;
2245 }
15c4a640
CO		 2246 }
2247 return 0;
2248}
2249EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2250
2251
2252/*
2253 * Reads an msr value (of 'msr_index') into 'pdata'.
2254 * Returns 0 on success, non-0 otherwise.
2255 * Assumes vcpu_load() was already called.
2256 */
609e36d3 2257int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2258{
609e36d3 2259 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2260}
ff651cb6 2261EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2262
890ca9ae 2263static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2264{
2265 u64 data;
890ca9ae
HY		 2266 u64 mcg_cap = vcpu->arch.mcg_cap;
2267 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2268
2269 switch (msr) {
15c4a640
CO		 2270 case MSR_IA32_P5_MC_ADDR:
2271 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2272 data = 0;
2273 break;
15c4a640 2274 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2275 data = vcpu->arch.mcg_cap;
2276 break;
c7ac679c 2277 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2278 if (!(mcg_cap & MCG_CTL_P))
2279 return 1;
2280 data = vcpu->arch.mcg_ctl;
2281 break;
2282 case MSR_IA32_MCG_STATUS:
2283 data = vcpu->arch.mcg_status;
2284 break;
2285 default:
2286 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2287 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2288 u32 offset = msr - MSR_IA32_MC0_CTL;
2289 data = vcpu->arch.mce_banks[offset];
2290 break;
2291 }
2292 return 1;
2293 }
2294 *pdata = data;
2295 return 0;
2296}
2297
609e36d3 2298int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2299{
609e36d3 2300 switch (msr_info->index) {
890ca9ae 2301 case MSR_IA32_PLATFORM_ID:
15c4a640 2302 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2303 case MSR_IA32_DEBUGCTLMSR:
2304 case MSR_IA32_LASTBRANCHFROMIP:
2305 case MSR_IA32_LASTBRANCHTOIP:
2306 case MSR_IA32_LASTINTFROMIP:
2307 case MSR_IA32_LASTINTTOIP:
60af2ecd 2308 case MSR_K8_SYSCFG:
3afb1121
PB		 2309 case MSR_K8_TSEG_ADDR:
2310 case MSR_K8_TSEG_MASK:
60af2ecd 2311 case MSR_K7_HWCR:
61a6bd67 2312 case MSR_VM_HSAVE_PA:
1fdbd48c 2313 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2314 case MSR_AMD64_NB_CFG:
f7c6d140 2315 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2316 case MSR_AMD64_BU_CFG2:
0c2df2a1 2317 case MSR_IA32_PERF_CTL:
609e36d3 2318 msr_info->data = 0;
15c4a640 2319 break;
6912ac32
WH		 2320 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2321 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2322 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2323 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2324 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2325 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2326 msr_info->data = 0;
5753785f 2327 break;
742bc670 2328 case MSR_IA32_UCODE_REV:
609e36d3 2329 msr_info->data = 0x100000000ULL;
742bc670 2330 break;
9ba075a6 2331 case MSR_MTRRcap:
9ba075a6 2332 case 0x200 ... 0x2ff:
ff53604b 2333 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2334 case 0xcd: /* fsb frequency */
609e36d3 2335 msr_info->data = 3;
15c4a640 2336 break;
7b914098
JS		 2337 /*
2338 * MSR_EBC_FREQUENCY_ID
2339 * Conservative value valid for even the basic CPU models.
2340 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2341 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2342 * and 266MHz for model 3, or 4. Set Core Clock
2343 * Frequency to System Bus Frequency Ratio to 1 (bits
2344 * 31:24) even though these are only valid for CPU
2345 * models > 2, however guests may end up dividing or
2346 * multiplying by zero otherwise.
2347 */
2348 case MSR_EBC_FREQUENCY_ID:
609e36d3 2349 msr_info->data = 1 << 24;
7b914098 2350 break;
15c4a640 2351 case MSR_IA32_APICBASE:
609e36d3 2352 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2353 break;
0105d1a5 2354 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2355 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2356 break;
a3e06bbe 2357 case MSR_IA32_TSCDEADLINE:
609e36d3 2358 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2359 break;
ba904635 2360 case MSR_IA32_TSC_ADJUST:
609e36d3 2361 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2362 break;
15c4a640 2363 case MSR_IA32_MISC_ENABLE:
609e36d3 2364 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2365 break;
64d60670
PB		 2366 case MSR_IA32_SMBASE:
2367 if (!msr_info->host_initiated)
2368 return 1;
2369 msr_info->data = vcpu->arch.smbase;
15c4a640 2370 break;
847f0ad8
AG		 2371 case MSR_IA32_PERF_STATUS:
2372 /* TSC increment by tick */
609e36d3 2373 msr_info->data = 1000ULL;
847f0ad8 2374 /* CPU multiplier */
b0996ae4 2375 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2376 break;
15c4a640 2377 case MSR_EFER:
609e36d3 2378 msr_info->data = vcpu->arch.efer;
15c4a640 2379 break;
18068523 2380 case MSR_KVM_WALL_CLOCK:
11c6bffa 2381 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2382 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2383 break;
2384 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2385 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2386 msr_info->data = vcpu->arch.time;
18068523 2387 break;
344d9588 2388 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2389 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2390 break;
c9aaa895 2391 case MSR_KVM_STEAL_TIME:
609e36d3 2392 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2393 break;
1d92128f 2394 case MSR_KVM_PV_EOI_EN:
609e36d3 2395 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2396 break;
890ca9ae
HY		 2397 case MSR_IA32_P5_MC_ADDR:
2398 case MSR_IA32_P5_MC_TYPE:
2399 case MSR_IA32_MCG_CAP:
2400 case MSR_IA32_MCG_CTL:
2401 case MSR_IA32_MCG_STATUS:
81760dcc 2402 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2403 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2404 case MSR_K7_CLK_CTL:
2405 /*
2406 * Provide expected ramp-up count for K7. All other
2407 * are set to zero, indicating minimum divisors for
2408 * every field.
2409 *
2410 * This prevents guest kernels on AMD host with CPU
2411 * type 6, model 8 and higher from exploding due to
2412 * the rdmsr failing.
2413 */
609e36d3 2414 msr_info->data = 0x20000000;
84e0cefa 2415 break;
55cd8e5a 2416 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2417 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2418 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2419 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2420 return kvm_hv_get_msr_common(vcpu,
2421 msr_info->index, &msr_info->data);
55cd8e5a 2422 break;
91c9c3ed 2423 case MSR_IA32_BBL_CR_CTL3:
2424 /* This legacy MSR exists but isn't fully documented in current
2425 * silicon. It is however accessed by winxp in very narrow
2426 * scenarios where it sets bit #19, itself documented as
2427 * a "reserved" bit. Best effort attempt to source coherent
2428 * read data here should the balance of the register be
2429 * interpreted by the guest:
2430 *
2431 * L2 cache control register 3: 64GB range, 256KB size,
2432 * enabled, latency 0x1, configured
2433 */
609e36d3 2434 msr_info->data = 0xbe702111;
91c9c3ed 2435 break;
2b036c6b
BO		 2436 case MSR_AMD64_OSVW_ID_LENGTH:
2437 if (!guest_cpuid_has_osvw(vcpu))
2438 return 1;
609e36d3 2439 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2440 break;
2441 case MSR_AMD64_OSVW_STATUS:
2442 if (!guest_cpuid_has_osvw(vcpu))
2443 return 1;
609e36d3 2444 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2445 break;
15c4a640 2446 default:
c6702c9d 2447 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2448 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2449 if (!ignore_msrs) {
609e36d3 2450 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2451 return 1;
2452 } else {
609e36d3
PB		 2453 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2454 msr_info->data = 0;
ed85c068
AP		 2455 }
2456 break;
15c4a640 2457 }
15c4a640
CO		 2458 return 0;
2459}
2460EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2461
313a3dc7
CO		 2462/*
2463 * Read or write a bunch of msrs. All parameters are kernel addresses.
2464 *
2465 * @return number of msrs set successfully.
2466 */
2467static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2468 struct kvm_msr_entry *entries,
2469 int (*do_msr)(struct kvm_vcpu *vcpu,
2470 unsigned index, u64 *data))
2471{
f656ce01 2472 int i, idx;
313a3dc7 2473
f656ce01 2474 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2475 for (i = 0; i < msrs->nmsrs; ++i)
2476 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2477 break;
f656ce01 2478 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2479
313a3dc7
CO		 2480 return i;
2481}
2482
2483/*
2484 * Read or write a bunch of msrs. Parameters are user addresses.
2485 *
2486 * @return number of msrs set successfully.
2487 */
2488static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2489 int (*do_msr)(struct kvm_vcpu *vcpu,
2490 unsigned index, u64 *data),
2491 int writeback)
2492{
2493 struct kvm_msrs msrs;
2494 struct kvm_msr_entry *entries;
2495 int r, n;
2496 unsigned size;
2497
2498 r = -EFAULT;
2499 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2500 goto out;
2501
2502 r = -E2BIG;
2503 if (msrs.nmsrs >= MAX_IO_MSRS)
2504 goto out;
2505
313a3dc7 2506 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2507 entries = memdup_user(user_msrs->entries, size);
2508 if (IS_ERR(entries)) {
2509 r = PTR_ERR(entries);
313a3dc7 2510 goto out;
ff5c2c03 2511 }
313a3dc7
CO		 2512
2513 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2514 if (r < 0)
2515 goto out_free;
2516
2517 r = -EFAULT;
2518 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2519 goto out_free;
2520
2521 r = n;
2522
2523out_free:
7a73c028 2524 kfree(entries);
313a3dc7
CO		 2525out:
2526 return r;
2527}
2528
784aa3d7 2529int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2530{
2531 int r;
2532
2533 switch (ext) {
2534 case KVM_CAP_IRQCHIP:
2535 case KVM_CAP_HLT:
2536 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2537 case KVM_CAP_SET_TSS_ADDR:
07716717 2538 case KVM_CAP_EXT_CPUID:
9c15bb1d 2539 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2540 case KVM_CAP_CLOCKSOURCE:
7837699f 2541 case KVM_CAP_PIT:
a28e4f5a 2542 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2543 case KVM_CAP_MP_STATE:
ed848624 2544 case KVM_CAP_SYNC_MMU:
a355c85c 2545 case KVM_CAP_USER_NMI:
52d939a0 2546 case KVM_CAP_REINJECT_CONTROL:
4925663a 2547 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2548 case KVM_CAP_IOEVENTFD:
f848a5a8 2549 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2550 case KVM_CAP_PIT2:
e9f42757 2551 case KVM_CAP_PIT_STATE2:
b927a3ce 2552 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2553 case KVM_CAP_XEN_HVM:
afbcf7ab 2554 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2555 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2556 case KVM_CAP_HYPERV:
10388a07 2557 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2558 case KVM_CAP_HYPERV_SPIN:
5c919412 2559 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2560 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2561 case KVM_CAP_DEBUGREGS:
d2be1651 2562 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2563 case KVM_CAP_XSAVE:
344d9588 2564 case KVM_CAP_ASYNC_PF:
92a1f12d 2565 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2566 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2567 case KVM_CAP_READONLY_MEM:
5f66b620 2568 case KVM_CAP_HYPERV_TIME:
100943c5 2569 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2570 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2571 case KVM_CAP_ENABLE_CAP_VM:
2572 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2573 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2574 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2575#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2576 case KVM_CAP_ASSIGN_DEV_IRQ:
2577 case KVM_CAP_PCI_2_3:
2578#endif
018d00d2
ZX		 2579 r = 1;
2580 break;
6d396b55
PB		 2581 case KVM_CAP_X86_SMM:
2582 /* SMBASE is usually relocated above 1M on modern chipsets,
2583 * and SMM handlers might indeed rely on 4G segment limits,
2584 * so do not report SMM to be available if real mode is
2585 * emulated via vm86 mode. Still, do not go to great lengths
2586 * to avoid userspace's usage of the feature, because it is a
2587 * fringe case that is not enabled except via specific settings
2588 * of the module parameters.
2589 */
2590 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2591 break;
542472b5
LV		 2592 case KVM_CAP_COALESCED_MMIO:
2593 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2594 break;
774ead3a
AK		 2595 case KVM_CAP_VAPIC:
2596 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2597 break;
f725230a 2598 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2599 r = KVM_SOFT_MAX_VCPUS;
2600 break;
2601 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2602 r = KVM_MAX_VCPUS;
2603 break;
a988b910 2604 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2605 r = KVM_USER_MEM_SLOTS;
a988b910 2606 break;
a68a6a72
MT		 2607 case KVM_CAP_PV_MMU: /* obsolete */
2608 r = 0;
2f333bcb 2609 break;
4cee4b72 2610#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2611 case KVM_CAP_IOMMU:
a1b60c1c 2612 r = iommu_present(&pci_bus_type);
62c476c7 2613 break;
4cee4b72 2614#endif
890ca9ae
HY		 2615 case KVM_CAP_MCE:
2616 r = KVM_MAX_MCE_BANKS;
2617 break;
2d5b5a66 2618 case KVM_CAP_XCRS:
d366bf7e 2619 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2620 break;
92a1f12d
JR		 2621 case KVM_CAP_TSC_CONTROL:
2622 r = kvm_has_tsc_control;
2623 break;
018d00d2
ZX		 2624 default:
2625 r = 0;
2626 break;
2627 }
2628 return r;
2629
2630}
2631
043405e1
CO		 2632long kvm_arch_dev_ioctl(struct file *filp,
2633 unsigned int ioctl, unsigned long arg)
2634{
2635 void __user *argp = (void __user *)arg;
2636 long r;
2637
2638 switch (ioctl) {
2639 case KVM_GET_MSR_INDEX_LIST: {
2640 struct kvm_msr_list __user *user_msr_list = argp;
2641 struct kvm_msr_list msr_list;
2642 unsigned n;
2643
2644 r = -EFAULT;
2645 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2646 goto out;
2647 n = msr_list.nmsrs;
62ef68bb 2648 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2649 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2650 goto out;
2651 r = -E2BIG;
e125e7b6 2652 if (n < msr_list.nmsrs)
043405e1
CO		 2653 goto out;
2654 r = -EFAULT;
2655 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2656 num_msrs_to_save * sizeof(u32)))
2657 goto out;
e125e7b6 2658 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2659 &emulated_msrs,
62ef68bb 2660 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2661 goto out;
2662 r = 0;
2663 break;
2664 }
9c15bb1d
BP		 2665 case KVM_GET_SUPPORTED_CPUID:
2666 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2667 struct kvm_cpuid2 __user *cpuid_arg = argp;
2668 struct kvm_cpuid2 cpuid;
2669
2670 r = -EFAULT;
2671 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2672 goto out;
9c15bb1d
BP		 2673
2674 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2675 ioctl);
674eea0f
AK		 2676 if (r)
2677 goto out;
2678
2679 r = -EFAULT;
2680 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2681 goto out;
2682 r = 0;
2683 break;
2684 }
890ca9ae
HY		 2685 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2686 u64 mce_cap;
2687
2688 mce_cap = KVM_MCE_CAP_SUPPORTED;
2689 r = -EFAULT;
2690 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2691 goto out;
2692 r = 0;
2693 break;
2694 }
043405e1
CO		 2695 default:
2696 r = -EINVAL;
2697 }
2698out:
2699 return r;
2700}
2701
f5f48ee1
SY		 2702static void wbinvd_ipi(void *garbage)
2703{
2704 wbinvd();
2705}
2706
2707static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2708{
e0f0bbc5 2709 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2710}
2711
2860c4b1
PB		 2712static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2713{
2714 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2715}
2716
313a3dc7
CO		 2717void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2718{
f5f48ee1
SY		 2719 /* Address WBINVD may be executed by guest */
2720 if (need_emulate_wbinvd(vcpu)) {
2721 if (kvm_x86_ops->has_wbinvd_exit())
2722 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2723 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2724 smp_call_function_single(vcpu->cpu,
2725 wbinvd_ipi, NULL, 1);
2726 }
2727
313a3dc7 2728 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2729
0dd6a6ed
ZA		 2730 /* Apply any externally detected TSC adjustments (due to suspend) */
2731 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2732 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2733 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2734 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2735 }
8f6055cb 2736
48434c20 2737 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2738 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2739 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2740 if (tsc_delta < 0)
2741 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2742 if (check_tsc_unstable()) {
07c1419a 2743 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2744 vcpu->arch.last_guest_tsc);
2745 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2746 vcpu->arch.tsc_catchup = 1;
c285545f 2747 }
d98d07ca
MT		 2748 /*
2749 * On a host with synchronized TSC, there is no need to update
2750 * kvmclock on vcpu->cpu migration
2751 */
2752 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2753 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2754 if (vcpu->cpu != cpu)
2755 kvm_migrate_timers(vcpu);
e48672fa 2756 vcpu->cpu = cpu;
6b7d7e76 2757 }
c9aaa895 2758
c9aaa895 2759 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2760}
2761
2762void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2763{
02daab21 2764 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2765 kvm_put_guest_fpu(vcpu);
4ea1636b 2766 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2767}
2768
313a3dc7
CO		 2769static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2770 struct kvm_lapic_state *s)
2771{
d62caabb
AS		 2772 if (vcpu->arch.apicv_active)
2773 kvm_x86_ops->sync_pir_to_irr(vcpu);
2774
ad312c7c 2775 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2776
2777 return 0;
2778}
2779
2780static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2781 struct kvm_lapic_state *s)
2782{
64eb0620 2783 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2784 update_cr8_intercept(vcpu);
313a3dc7
CO		 2785
2786 return 0;
2787}
2788
127a457a
MG		 2789static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2790{
2791 return (!lapic_in_kernel(vcpu) ||
2792 kvm_apic_accept_pic_intr(vcpu));
2793}
2794
782d422b
MG		 2795/*
2796 * if userspace requested an interrupt window, check that the
2797 * interrupt window is open.
2798 *
2799 * No need to exit to userspace if we already have an interrupt queued.
2800 */
2801static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2802{
2803 return kvm_arch_interrupt_allowed(vcpu) &&
2804 !kvm_cpu_has_interrupt(vcpu) &&
2805 !kvm_event_needs_reinjection(vcpu) &&
2806 kvm_cpu_accept_dm_intr(vcpu);
2807}
2808
f77bc6a4
ZX		 2809static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2810 struct kvm_interrupt *irq)
2811{
02cdb50f 2812 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2813 return -EINVAL;
1c1a9ce9
SR		 2814
2815 if (!irqchip_in_kernel(vcpu->kvm)) {
2816 kvm_queue_interrupt(vcpu, irq->irq, false);
2817 kvm_make_request(KVM_REQ_EVENT, vcpu);
2818 return 0;
2819 }
2820
2821 /*
2822 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2823 * fail for in-kernel 8259.
2824 */
2825 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2826 return -ENXIO;
f77bc6a4 2827
1c1a9ce9
SR		 2828 if (vcpu->arch.pending_external_vector != -1)
2829 return -EEXIST;
f77bc6a4 2830
1c1a9ce9 2831 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2832 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2833 return 0;
2834}
2835
c4abb7c9
JK		 2836static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2837{
c4abb7c9 2838 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2839
2840 return 0;
2841}
2842
f077825a
PB		 2843static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2844{
64d60670
PB		 2845 kvm_make_request(KVM_REQ_SMI, vcpu);
2846
f077825a
PB		 2847 return 0;
2848}
2849
b209749f
AK		 2850static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2851 struct kvm_tpr_access_ctl *tac)
2852{
2853 if (tac->flags)
2854 return -EINVAL;
2855 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2856 return 0;
2857}
2858
890ca9ae
HY		 2859static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2860 u64 mcg_cap)
2861{
2862 int r;
2863 unsigned bank_num = mcg_cap & 0xff, bank;
2864
2865 r = -EINVAL;
a9e38c3e 2866 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2867 goto out;
2868 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2869 goto out;
2870 r = 0;
2871 vcpu->arch.mcg_cap = mcg_cap;
2872 /* Init IA32_MCG_CTL to all 1s */
2873 if (mcg_cap & MCG_CTL_P)
2874 vcpu->arch.mcg_ctl = ~(u64)0;
2875 /* Init IA32_MCi_CTL to all 1s */
2876 for (bank = 0; bank < bank_num; bank++)
2877 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2878out:
2879 return r;
2880}
2881
2882static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2883 struct kvm_x86_mce *mce)
2884{
2885 u64 mcg_cap = vcpu->arch.mcg_cap;
2886 unsigned bank_num = mcg_cap & 0xff;
2887 u64 *banks = vcpu->arch.mce_banks;
2888
2889 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2890 return -EINVAL;
2891 /*
2892 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2893 * reporting is disabled
2894 */
2895 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2896 vcpu->arch.mcg_ctl != ~(u64)0)
2897 return 0;
2898 banks += 4 * mce->bank;
2899 /*
2900 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2901 * reporting is disabled for the bank
2902 */
2903 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2904 return 0;
2905 if (mce->status & MCI_STATUS_UC) {
2906 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2907 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2908 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2909 return 0;
2910 }
2911 if (banks[1] & MCI_STATUS_VAL)
2912 mce->status |= MCI_STATUS_OVER;
2913 banks[2] = mce->addr;
2914 banks[3] = mce->misc;
2915 vcpu->arch.mcg_status = mce->mcg_status;
2916 banks[1] = mce->status;
2917 kvm_queue_exception(vcpu, MC_VECTOR);
2918 } else if (!(banks[1] & MCI_STATUS_VAL)
2919 || !(banks[1] & MCI_STATUS_UC)) {
2920 if (banks[1] & MCI_STATUS_VAL)
2921 mce->status |= MCI_STATUS_OVER;
2922 banks[2] = mce->addr;
2923 banks[3] = mce->misc;
2924 banks[1] = mce->status;
2925 } else
2926 banks[1] |= MCI_STATUS_OVER;
2927 return 0;
2928}
2929
3cfc3092
JK		 2930static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2931 struct kvm_vcpu_events *events)
2932{
7460fb4a 2933 process_nmi(vcpu);
03b82a30
JK		 2934 events->exception.injected =
2935 vcpu->arch.exception.pending &&
2936 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2937 events->exception.nr = vcpu->arch.exception.nr;
2938 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2939 events->exception.pad = 0;
3cfc3092
JK		 2940 events->exception.error_code = vcpu->arch.exception.error_code;
2941
03b82a30
JK		 2942 events->interrupt.injected =
2943 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2944 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2945 events->interrupt.soft = 0;
37ccdcbe 2946 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2947
2948 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2949 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2950 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2951 events->nmi.pad = 0;
3cfc3092 2952
66450a21 2953 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2954
f077825a
PB		 2955 events->smi.smm = is_smm(vcpu);
2956 events->smi.pending = vcpu->arch.smi_pending;
2957 events->smi.smm_inside_nmi =
2958 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2959 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2960
dab4b911 2961 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2962 | KVM_VCPUEVENT_VALID_SHADOW
2963 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2964 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2965}
2966
2967static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2968 struct kvm_vcpu_events *events)
2969{
dab4b911 2970 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2971 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2972 | KVM_VCPUEVENT_VALID_SHADOW
2973 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2974 return -EINVAL;
2975
78e546c8
PB		 2976 if (events->exception.injected &&
2977 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
2978 return -EINVAL;
2979
7460fb4a 2980 process_nmi(vcpu);
3cfc3092
JK		 2981 vcpu->arch.exception.pending = events->exception.injected;
2982 vcpu->arch.exception.nr = events->exception.nr;
2983 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2984 vcpu->arch.exception.error_code = events->exception.error_code;
2985
2986 vcpu->arch.interrupt.pending = events->interrupt.injected;
2987 vcpu->arch.interrupt.nr = events->interrupt.nr;
2988 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2989 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2990 kvm_x86_ops->set_interrupt_shadow(vcpu,
2991 events->interrupt.shadow);
3cfc3092
JK		 2992
2993 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2994 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2995 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2996 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2997
66450a21 2998 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 2999 lapic_in_kernel(vcpu))
66450a21 3000 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3001
f077825a
PB		 3002 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3003 if (events->smi.smm)
3004 vcpu->arch.hflags |= HF_SMM_MASK;
3005 else
3006 vcpu->arch.hflags &= ~HF_SMM_MASK;
3007 vcpu->arch.smi_pending = events->smi.pending;
3008 if (events->smi.smm_inside_nmi)
3009 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3010 else
3011 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3012 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3013 if (events->smi.latched_init)
3014 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3015 else
3016 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3017 }
3018 }
3019
3842d135
AK		 3020 kvm_make_request(KVM_REQ_EVENT, vcpu);
3021
3cfc3092
JK		 3022 return 0;
3023}
3024
a1efbe77
JK		 3025static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3026 struct kvm_debugregs *dbgregs)
3027{
73aaf249
JK		 3028 unsigned long val;
3029
a1efbe77 3030 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3031 kvm_get_dr(vcpu, 6, &val);
73aaf249 3032 dbgregs->dr6 = val;
a1efbe77
JK		 3033 dbgregs->dr7 = vcpu->arch.dr7;
3034 dbgregs->flags = 0;
97e69aa6 3035 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3036}
3037
3038static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3039 struct kvm_debugregs *dbgregs)
3040{
3041 if (dbgregs->flags)
3042 return -EINVAL;
3043
d14bdb55
PB		 3044 if (dbgregs->dr6 & ~0xffffffffull)
3045 return -EINVAL;
3046 if (dbgregs->dr7 & ~0xffffffffull)
3047 return -EINVAL;
3048
a1efbe77 3049 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3050 kvm_update_dr0123(vcpu);
a1efbe77 3051 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3052 kvm_update_dr6(vcpu);
a1efbe77 3053 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3054 kvm_update_dr7(vcpu);
a1efbe77 3055
a1efbe77
JK		 3056 return 0;
3057}
3058
df1daba7
PB		 3059#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3060
3061static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3062{
c47ada30 3063 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3064 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3065 u64 valid;
3066
3067 /*
3068 * Copy legacy XSAVE area, to avoid complications with CPUID
3069 * leaves 0 and 1 in the loop below.
3070 */
3071 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3072
3073 /* Set XSTATE_BV */
3074 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3075
3076 /*
3077 * Copy each region from the possibly compacted offset to the
3078 * non-compacted offset.
3079 */
d91cab78 3080 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3081 while (valid) {
3082 u64 feature = valid & -valid;
3083 int index = fls64(feature) - 1;
3084 void *src = get_xsave_addr(xsave, feature);
3085
3086 if (src) {
3087 u32 size, offset, ecx, edx;
3088 cpuid_count(XSTATE_CPUID, index,
3089 &size, &offset, &ecx, &edx);
3090 memcpy(dest + offset, src, size);
3091 }
3092
3093 valid -= feature;
3094 }
3095}
3096
3097static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3098{
c47ada30 3099 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3100 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3101 u64 valid;
3102
3103 /*
3104 * Copy legacy XSAVE area, to avoid complications with CPUID
3105 * leaves 0 and 1 in the loop below.
3106 */
3107 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3108
3109 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3110 xsave->header.xfeatures = xstate_bv;
782511b0 3111 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3112 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3113
3114 /*
3115 * Copy each region from the non-compacted offset to the
3116 * possibly compacted offset.
3117 */
d91cab78 3118 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3119 while (valid) {
3120 u64 feature = valid & -valid;
3121 int index = fls64(feature) - 1;
3122 void *dest = get_xsave_addr(xsave, feature);
3123
3124 if (dest) {
3125 u32 size, offset, ecx, edx;
3126 cpuid_count(XSTATE_CPUID, index,
3127 &size, &offset, &ecx, &edx);
3128 memcpy(dest, src + offset, size);
ee4100da 3129 }
df1daba7
PB		 3130
3131 valid -= feature;
3132 }
3133}
3134
2d5b5a66
SY		 3135static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3136 struct kvm_xsave *guest_xsave)
3137{
d366bf7e 3138 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3139 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3140 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3141 } else {
2d5b5a66 3142 memcpy(guest_xsave->region,
7366ed77 3143 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3144 sizeof(struct fxregs_state));
2d5b5a66 3145 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3146 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3147 }
3148}
3149
3150static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3151 struct kvm_xsave *guest_xsave)
3152{
3153 u64 xstate_bv =
3154 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3155
d366bf7e 3156 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3157 /*
3158 * Here we allow setting states that are not present in
3159 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3160 * with old userspace.
3161 */
4ff41732 3162 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3163 return -EINVAL;
df1daba7 3164 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3165 } else {
d91cab78 3166 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3167 return -EINVAL;
7366ed77 3168 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3169 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3170 }
3171 return 0;
3172}
3173
3174static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3175 struct kvm_xcrs *guest_xcrs)
3176{
d366bf7e 3177 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3178 guest_xcrs->nr_xcrs = 0;
3179 return;
3180 }
3181
3182 guest_xcrs->nr_xcrs = 1;
3183 guest_xcrs->flags = 0;
3184 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3185 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3186}
3187
3188static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3189 struct kvm_xcrs *guest_xcrs)
3190{
3191 int i, r = 0;
3192
d366bf7e 3193 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3194 return -EINVAL;
3195
3196 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3197 return -EINVAL;
3198
3199 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3200 /* Only support XCR0 currently */
c67a04cb 3201 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3202 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3203 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3204 break;
3205 }
3206 if (r)
3207 r = -EINVAL;
3208 return r;
3209}
3210
1c0b28c2
EM		 3211/*
3212 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3213 * stopped by the hypervisor. This function will be called from the host only.
3214 * EINVAL is returned when the host attempts to set the flag for a guest that
3215 * does not support pv clocks.
3216 */
3217static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3218{
0b79459b 3219 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3220 return -EINVAL;
51d59c6b 3221 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3222 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3223 return 0;
3224}
3225
5c919412
AS		 3226static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3227 struct kvm_enable_cap *cap)
3228{
3229 if (cap->flags)
3230 return -EINVAL;
3231
3232 switch (cap->cap) {
3233 case KVM_CAP_HYPERV_SYNIC:
3234 return kvm_hv_activate_synic(vcpu);
3235 default:
3236 return -EINVAL;
3237 }
3238}
3239
313a3dc7
CO		 3240long kvm_arch_vcpu_ioctl(struct file *filp,
3241 unsigned int ioctl, unsigned long arg)
3242{
3243 struct kvm_vcpu *vcpu = filp->private_data;
3244 void __user *argp = (void __user *)arg;
3245 int r;
d1ac91d8
AK		 3246 union {
3247 struct kvm_lapic_state *lapic;
3248 struct kvm_xsave *xsave;
3249 struct kvm_xcrs *xcrs;
3250 void *buffer;
3251 } u;
3252
3253 u.buffer = NULL;
313a3dc7
CO		 3254 switch (ioctl) {
3255 case KVM_GET_LAPIC: {
2204ae3c 3256 r = -EINVAL;
bce87cce 3257 if (!lapic_in_kernel(vcpu))
2204ae3c 3258 goto out;
d1ac91d8 3259 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3260
b772ff36 3261 r = -ENOMEM;
d1ac91d8 3262 if (!u.lapic)
b772ff36 3263 goto out;
d1ac91d8 3264 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3265 if (r)
3266 goto out;
3267 r = -EFAULT;
d1ac91d8 3268 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3269 goto out;
3270 r = 0;
3271 break;
3272 }
3273 case KVM_SET_LAPIC: {
2204ae3c 3274 r = -EINVAL;
bce87cce 3275 if (!lapic_in_kernel(vcpu))
2204ae3c 3276 goto out;
ff5c2c03 3277 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3278 if (IS_ERR(u.lapic))
3279 return PTR_ERR(u.lapic);
ff5c2c03 3280
d1ac91d8 3281 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3282 break;
3283 }
f77bc6a4
ZX		 3284 case KVM_INTERRUPT: {
3285 struct kvm_interrupt irq;
3286
3287 r = -EFAULT;
3288 if (copy_from_user(&irq, argp, sizeof irq))
3289 goto out;
3290 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3291 break;
3292 }
c4abb7c9
JK		 3293 case KVM_NMI: {
3294 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3295 break;
3296 }
f077825a
PB		 3297 case KVM_SMI: {
3298 r = kvm_vcpu_ioctl_smi(vcpu);
3299 break;
3300 }
313a3dc7
CO		 3301 case KVM_SET_CPUID: {
3302 struct kvm_cpuid __user *cpuid_arg = argp;
3303 struct kvm_cpuid cpuid;
3304
3305 r = -EFAULT;
3306 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3307 goto out;
3308 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3309 break;
3310 }
07716717
DK		 3311 case KVM_SET_CPUID2: {
3312 struct kvm_cpuid2 __user *cpuid_arg = argp;
3313 struct kvm_cpuid2 cpuid;
3314
3315 r = -EFAULT;
3316 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3317 goto out;
3318 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3319 cpuid_arg->entries);
07716717
DK		 3320 break;
3321 }
3322 case KVM_GET_CPUID2: {
3323 struct kvm_cpuid2 __user *cpuid_arg = argp;
3324 struct kvm_cpuid2 cpuid;
3325
3326 r = -EFAULT;
3327 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3328 goto out;
3329 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3330 cpuid_arg->entries);
07716717
DK		 3331 if (r)
3332 goto out;
3333 r = -EFAULT;
3334 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3335 goto out;
3336 r = 0;
3337 break;
3338 }
313a3dc7 3339 case KVM_GET_MSRS:
609e36d3 3340 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3341 break;
3342 case KVM_SET_MSRS:
3343 r = msr_io(vcpu, argp, do_set_msr, 0);
3344 break;
b209749f
AK		 3345 case KVM_TPR_ACCESS_REPORTING: {
3346 struct kvm_tpr_access_ctl tac;
3347
3348 r = -EFAULT;
3349 if (copy_from_user(&tac, argp, sizeof tac))
3350 goto out;
3351 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3352 if (r)
3353 goto out;
3354 r = -EFAULT;
3355 if (copy_to_user(argp, &tac, sizeof tac))
3356 goto out;
3357 r = 0;
3358 break;
3359 };
b93463aa
AK		 3360 case KVM_SET_VAPIC_ADDR: {
3361 struct kvm_vapic_addr va;
3362
3363 r = -EINVAL;
35754c98 3364 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3365 goto out;
3366 r = -EFAULT;
3367 if (copy_from_user(&va, argp, sizeof va))
3368 goto out;
fda4e2e8 3369 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3370 break;
3371 }
890ca9ae
HY		 3372 case KVM_X86_SETUP_MCE: {
3373 u64 mcg_cap;
3374
3375 r = -EFAULT;
3376 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3377 goto out;
3378 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3379 break;
3380 }
3381 case KVM_X86_SET_MCE: {
3382 struct kvm_x86_mce mce;
3383
3384 r = -EFAULT;
3385 if (copy_from_user(&mce, argp, sizeof mce))
3386 goto out;
3387 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3388 break;
3389 }
3cfc3092
JK		 3390 case KVM_GET_VCPU_EVENTS: {
3391 struct kvm_vcpu_events events;
3392
3393 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3394
3395 r = -EFAULT;
3396 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3397 break;
3398 r = 0;
3399 break;
3400 }
3401 case KVM_SET_VCPU_EVENTS: {
3402 struct kvm_vcpu_events events;
3403
3404 r = -EFAULT;
3405 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3406 break;
3407
3408 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3409 break;
3410 }
a1efbe77
JK		 3411 case KVM_GET_DEBUGREGS: {
3412 struct kvm_debugregs dbgregs;
3413
3414 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3415
3416 r = -EFAULT;
3417 if (copy_to_user(argp, &dbgregs,
3418 sizeof(struct kvm_debugregs)))
3419 break;
3420 r = 0;
3421 break;
3422 }
3423 case KVM_SET_DEBUGREGS: {
3424 struct kvm_debugregs dbgregs;
3425
3426 r = -EFAULT;
3427 if (copy_from_user(&dbgregs, argp,
3428 sizeof(struct kvm_debugregs)))
3429 break;
3430
3431 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3432 break;
3433 }
2d5b5a66 3434 case KVM_GET_XSAVE: {
d1ac91d8 3435 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3436 r = -ENOMEM;
d1ac91d8 3437 if (!u.xsave)
2d5b5a66
SY		 3438 break;
3439
d1ac91d8 3440 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3441
3442 r = -EFAULT;
d1ac91d8 3443 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3444 break;
3445 r = 0;
3446 break;
3447 }
3448 case KVM_SET_XSAVE: {
ff5c2c03 3449 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3450 if (IS_ERR(u.xsave))
3451 return PTR_ERR(u.xsave);
2d5b5a66 3452
d1ac91d8 3453 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3454 break;
3455 }
3456 case KVM_GET_XCRS: {
d1ac91d8 3457 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3458 r = -ENOMEM;
d1ac91d8 3459 if (!u.xcrs)
2d5b5a66
SY		 3460 break;
3461
d1ac91d8 3462 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3463
3464 r = -EFAULT;
d1ac91d8 3465 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3466 sizeof(struct kvm_xcrs)))
3467 break;
3468 r = 0;
3469 break;
3470 }
3471 case KVM_SET_XCRS: {
ff5c2c03 3472 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3473 if (IS_ERR(u.xcrs))
3474 return PTR_ERR(u.xcrs);
2d5b5a66 3475
d1ac91d8 3476 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3477 break;
3478 }
92a1f12d
JR		 3479 case KVM_SET_TSC_KHZ: {
3480 u32 user_tsc_khz;
3481
3482 r = -EINVAL;
92a1f12d
JR		 3483 user_tsc_khz = (u32)arg;
3484
3485 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3486 goto out;
3487
cc578287
ZA		 3488 if (user_tsc_khz == 0)
3489 user_tsc_khz = tsc_khz;
3490
381d585c
HZ		 3491 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3492 r = 0;
92a1f12d 3493
92a1f12d
JR		 3494 goto out;
3495 }
3496 case KVM_GET_TSC_KHZ: {
cc578287 3497 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3498 goto out;
3499 }
1c0b28c2
EM		 3500 case KVM_KVMCLOCK_CTRL: {
3501 r = kvm_set_guest_paused(vcpu);
3502 goto out;
3503 }
5c919412
AS		 3504 case KVM_ENABLE_CAP: {
3505 struct kvm_enable_cap cap;
3506
3507 r = -EFAULT;
3508 if (copy_from_user(&cap, argp, sizeof(cap)))
3509 goto out;
3510 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3511 break;
3512 }
313a3dc7
CO		 3513 default:
3514 r = -EINVAL;
3515 }
3516out:
d1ac91d8 3517 kfree(u.buffer);
313a3dc7
CO		 3518 return r;
3519}
3520
5b1c1493
CO		 3521int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3522{
3523 return VM_FAULT_SIGBUS;
3524}
3525
1fe779f8
CO		 3526static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3527{
3528 int ret;
3529
3530 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3531 return -EINVAL;
1fe779f8
CO		 3532 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3533 return ret;
3534}
3535
b927a3ce
SY		 3536static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3537 u64 ident_addr)
3538{
3539 kvm->arch.ept_identity_map_addr = ident_addr;
3540 return 0;
3541}
3542
1fe779f8
CO		 3543static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3544 u32 kvm_nr_mmu_pages)
3545{
3546 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3547 return -EINVAL;
3548
79fac95e 3549 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3550
3551 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3552 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3553
79fac95e 3554 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3555 return 0;
3556}
3557
3558static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3559{
39de71ec 3560 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3561}
3562
1fe779f8
CO		 3563static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3564{
3565 int r;
3566
3567 r = 0;
3568 switch (chip->chip_id) {
3569 case KVM_IRQCHIP_PIC_MASTER:
3570 memcpy(&chip->chip.pic,
3571 &pic_irqchip(kvm)->pics[0],
3572 sizeof(struct kvm_pic_state));
3573 break;
3574 case KVM_IRQCHIP_PIC_SLAVE:
3575 memcpy(&chip->chip.pic,
3576 &pic_irqchip(kvm)->pics[1],
3577 sizeof(struct kvm_pic_state));
3578 break;
3579 case KVM_IRQCHIP_IOAPIC:
eba0226b 3580 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3581 break;
3582 default:
3583 r = -EINVAL;
3584 break;
3585 }
3586 return r;
3587}
3588
3589static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3590{
3591 int r;
3592
3593 r = 0;
3594 switch (chip->chip_id) {
3595 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3596 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3597 memcpy(&pic_irqchip(kvm)->pics[0],
3598 &chip->chip.pic,
3599 sizeof(struct kvm_pic_state));
f4f51050 3600 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3601 break;
3602 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3603 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3604 memcpy(&pic_irqchip(kvm)->pics[1],
3605 &chip->chip.pic,
3606 sizeof(struct kvm_pic_state));
f4f51050 3607 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3608 break;
3609 case KVM_IRQCHIP_IOAPIC:
eba0226b 3610 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3611 break;
3612 default:
3613 r = -EINVAL;
3614 break;
3615 }
3616 kvm_pic_update_irq(pic_irqchip(kvm));
3617 return r;
3618}
3619
e0f63cb9
SY		 3620static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3621{
34f3941c
RK		 3622 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3623
3624 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3625
3626 mutex_lock(&kps->lock);
3627 memcpy(ps, &kps->channels, sizeof(*ps));
3628 mutex_unlock(&kps->lock);
2da29bcc 3629 return 0;
e0f63cb9
SY		 3630}
3631
3632static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3633{
0185604c 3634 int i;
09edea72
RK		 3635 struct kvm_pit *pit = kvm->arch.vpit;
3636
3637 mutex_lock(&pit->pit_state.lock);
34f3941c 3638 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3639 for (i = 0; i < 3; i++)
09edea72
RK		 3640 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3641 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3642 return 0;
e9f42757
BK		 3643}
3644
3645static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3646{
e9f42757
BK		 3647 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3648 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3649 sizeof(ps->channels));
3650 ps->flags = kvm->arch.vpit->pit_state.flags;
3651 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3652 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3653 return 0;
e9f42757
BK		 3654}
3655
3656static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3657{
2da29bcc 3658 int start = 0;
0185604c 3659 int i;
e9f42757 3660 u32 prev_legacy, cur_legacy;
09edea72
RK		 3661 struct kvm_pit *pit = kvm->arch.vpit;
3662
3663 mutex_lock(&pit->pit_state.lock);
3664 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3665 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3666 if (!prev_legacy && cur_legacy)
3667 start = 1;
09edea72
RK		 3668 memcpy(&pit->pit_state.channels, &ps->channels,
3669 sizeof(pit->pit_state.channels));
3670 pit->pit_state.flags = ps->flags;
0185604c 3671 for (i = 0; i < 3; i++)
09edea72 3672 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3673 start && i == 0);
09edea72 3674 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3675 return 0;
e0f63cb9
SY		 3676}
3677
52d939a0
MT		 3678static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3679 struct kvm_reinject_control *control)
3680{
71474e2f
RK		 3681 struct kvm_pit *pit = kvm->arch.vpit;
3682
3683 if (!pit)
52d939a0 3684 return -ENXIO;
b39c90b6 3685
71474e2f
RK		 3686 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3687 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3688 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3689 */
3690 mutex_lock(&pit->pit_state.lock);
3691 kvm_pit_set_reinject(pit, control->pit_reinject);
3692 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3693
52d939a0
MT		 3694 return 0;
3695}
3696
95d4c16c 3697/**
60c34612
TY		 3698 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3699 * @kvm: kvm instance
3700 * @log: slot id and address to which we copy the log
95d4c16c 3701 *
e108ff2f
PB		 3702 * Steps 1-4 below provide general overview of dirty page logging. See
3703 * kvm_get_dirty_log_protect() function description for additional details.
3704 *
3705 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3706 * always flush the TLB (step 4) even if previous step failed and the dirty
3707 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3708 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3709 * writes will be marked dirty for next log read.
95d4c16c 3710 *
60c34612
TY		 3711 * 1. Take a snapshot of the bit and clear it if needed.
3712 * 2. Write protect the corresponding page.
e108ff2f
PB		 3713 * 3. Copy the snapshot to the userspace.
3714 * 4. Flush TLB's if needed.
5bb064dc 3715 */
60c34612 3716int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3717{
60c34612 3718 bool is_dirty = false;
e108ff2f 3719 int r;
5bb064dc 3720
79fac95e 3721 mutex_lock(&kvm->slots_lock);
5bb064dc 3722
88178fd4
KH		 3723 /*
3724 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3725 */
3726 if (kvm_x86_ops->flush_log_dirty)
3727 kvm_x86_ops->flush_log_dirty(kvm);
3728
e108ff2f 3729 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3730
3731 /*
3732 * All the TLBs can be flushed out of mmu lock, see the comments in
3733 * kvm_mmu_slot_remove_write_access().
3734 */
e108ff2f 3735 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3736 if (is_dirty)
3737 kvm_flush_remote_tlbs(kvm);
3738
79fac95e 3739 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3740 return r;
3741}
3742
aa2fbe6d
YZ		 3743int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3744 bool line_status)
23d43cf9
CD		 3745{
3746 if (!irqchip_in_kernel(kvm))
3747 return -ENXIO;
3748
3749 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3750 irq_event->irq, irq_event->level,
3751 line_status);
23d43cf9
CD		 3752 return 0;
3753}
3754
90de4a18
NA		 3755static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3756 struct kvm_enable_cap *cap)
3757{
3758 int r;
3759
3760 if (cap->flags)
3761 return -EINVAL;
3762
3763 switch (cap->cap) {
3764 case KVM_CAP_DISABLE_QUIRKS:
3765 kvm->arch.disabled_quirks = cap->args[0];
3766 r = 0;
3767 break;
49df6397
SR		 3768 case KVM_CAP_SPLIT_IRQCHIP: {
3769 mutex_lock(&kvm->lock);
b053b2ae
SR		 3770 r = -EINVAL;
3771 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3772 goto split_irqchip_unlock;
49df6397
SR		 3773 r = -EEXIST;
3774 if (irqchip_in_kernel(kvm))
3775 goto split_irqchip_unlock;
3776 if (atomic_read(&kvm->online_vcpus))
3777 goto split_irqchip_unlock;
3778 r = kvm_setup_empty_irq_routing(kvm);
3779 if (r)
3780 goto split_irqchip_unlock;
3781 /* Pairs with irqchip_in_kernel. */
3782 smp_wmb();
3783 kvm->arch.irqchip_split = true;
b053b2ae 3784 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3785 r = 0;
3786split_irqchip_unlock:
3787 mutex_unlock(&kvm->lock);
3788 break;
3789 }
90de4a18
NA		 3790 default:
3791 r = -EINVAL;
3792 break;
3793 }
3794 return r;
3795}
3796
1fe779f8
CO		 3797long kvm_arch_vm_ioctl(struct file *filp,
3798 unsigned int ioctl, unsigned long arg)
3799{
3800 struct kvm *kvm = filp->private_data;
3801 void __user *argp = (void __user *)arg;
367e1319 3802 int r = -ENOTTY;
f0d66275
DH		 3803 /*
3804 * This union makes it completely explicit to gcc-3.x
3805 * that these two variables' stack usage should be
3806 * combined, not added together.
3807 */
3808 union {
3809 struct kvm_pit_state ps;
e9f42757 3810 struct kvm_pit_state2 ps2;
c5ff41ce 3811 struct kvm_pit_config pit_config;
f0d66275 3812 } u;
1fe779f8
CO		 3813
3814 switch (ioctl) {
3815 case KVM_SET_TSS_ADDR:
3816 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3817 break;
b927a3ce
SY		 3818 case KVM_SET_IDENTITY_MAP_ADDR: {
3819 u64 ident_addr;
3820
3821 r = -EFAULT;
3822 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3823 goto out;
3824 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3825 break;
3826 }
1fe779f8
CO		 3827 case KVM_SET_NR_MMU_PAGES:
3828 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3829 break;
3830 case KVM_GET_NR_MMU_PAGES:
3831 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3832 break;
3ddea128
MT		 3833 case KVM_CREATE_IRQCHIP: {
3834 struct kvm_pic *vpic;
3835
3836 mutex_lock(&kvm->lock);
3837 r = -EEXIST;
3838 if (kvm->arch.vpic)
3839 goto create_irqchip_unlock;
3e515705
AK		 3840 r = -EINVAL;
3841 if (atomic_read(&kvm->online_vcpus))
3842 goto create_irqchip_unlock;
1fe779f8 3843 r = -ENOMEM;
3ddea128
MT		 3844 vpic = kvm_create_pic(kvm);
3845 if (vpic) {
1fe779f8
CO		 3846 r = kvm_ioapic_init(kvm);
3847 if (r) {
175504cd 3848 mutex_lock(&kvm->slots_lock);
71ba994c 3849 kvm_destroy_pic(vpic);
175504cd 3850 mutex_unlock(&kvm->slots_lock);
3ddea128 3851 goto create_irqchip_unlock;
1fe779f8
CO		 3852 }
3853 } else
3ddea128 3854 goto create_irqchip_unlock;
399ec807
AK		 3855 r = kvm_setup_default_irq_routing(kvm);
3856 if (r) {
175504cd 3857 mutex_lock(&kvm->slots_lock);
3ddea128 3858 mutex_lock(&kvm->irq_lock);
72bb2fcd 3859 kvm_ioapic_destroy(kvm);
71ba994c 3860 kvm_destroy_pic(vpic);
3ddea128 3861 mutex_unlock(&kvm->irq_lock);
175504cd 3862 mutex_unlock(&kvm->slots_lock);
71ba994c 3863 goto create_irqchip_unlock;
399ec807 3864 }
71ba994c
PB		 3865 /* Write kvm->irq_routing before kvm->arch.vpic. */
3866 smp_wmb();
3867 kvm->arch.vpic = vpic;
3ddea128
MT		 3868 create_irqchip_unlock:
3869 mutex_unlock(&kvm->lock);
1fe779f8 3870 break;
3ddea128 3871 }
7837699f 3872 case KVM_CREATE_PIT:
c5ff41ce
JK		 3873 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3874 goto create_pit;
3875 case KVM_CREATE_PIT2:
3876 r = -EFAULT;
3877 if (copy_from_user(&u.pit_config, argp,
3878 sizeof(struct kvm_pit_config)))
3879 goto out;
3880 create_pit:
79fac95e 3881 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3882 r = -EEXIST;
3883 if (kvm->arch.vpit)
3884 goto create_pit_unlock;
7837699f 3885 r = -ENOMEM;
c5ff41ce 3886 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3887 if (kvm->arch.vpit)
3888 r = 0;
269e05e4 3889 create_pit_unlock:
79fac95e 3890 mutex_unlock(&kvm->slots_lock);
7837699f 3891 break;
1fe779f8
CO		 3892 case KVM_GET_IRQCHIP: {
3893 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3894 struct kvm_irqchip *chip;
1fe779f8 3895
ff5c2c03
SL		 3896 chip = memdup_user(argp, sizeof(*chip));
3897 if (IS_ERR(chip)) {
3898 r = PTR_ERR(chip);
1fe779f8 3899 goto out;
ff5c2c03
SL		 3900 }
3901
1fe779f8 3902 r = -ENXIO;
49df6397 3903 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3904 goto get_irqchip_out;
3905 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3906 if (r)
f0d66275 3907 goto get_irqchip_out;
1fe779f8 3908 r = -EFAULT;
f0d66275
DH		 3909 if (copy_to_user(argp, chip, sizeof *chip))
3910 goto get_irqchip_out;
1fe779f8 3911 r = 0;
f0d66275
DH		 3912 get_irqchip_out:
3913 kfree(chip);
1fe779f8
CO		 3914 break;
3915 }
3916 case KVM_SET_IRQCHIP: {
3917 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3918 struct kvm_irqchip *chip;
1fe779f8 3919
ff5c2c03
SL		 3920 chip = memdup_user(argp, sizeof(*chip));
3921 if (IS_ERR(chip)) {
3922 r = PTR_ERR(chip);
1fe779f8 3923 goto out;
ff5c2c03
SL		 3924 }
3925
1fe779f8 3926 r = -ENXIO;
49df6397 3927 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3928 goto set_irqchip_out;
3929 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3930 if (r)
f0d66275 3931 goto set_irqchip_out;
1fe779f8 3932 r = 0;
f0d66275
DH		 3933 set_irqchip_out:
3934 kfree(chip);
1fe779f8
CO		 3935 break;
3936 }
e0f63cb9 3937 case KVM_GET_PIT: {
e0f63cb9 3938 r = -EFAULT;
f0d66275 3939 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3940 goto out;
3941 r = -ENXIO;
3942 if (!kvm->arch.vpit)
3943 goto out;
f0d66275 3944 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3945 if (r)
3946 goto out;
3947 r = -EFAULT;
f0d66275 3948 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3949 goto out;
3950 r = 0;
3951 break;
3952 }
3953 case KVM_SET_PIT: {
e0f63cb9 3954 r = -EFAULT;
f0d66275 3955 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3956 goto out;
3957 r = -ENXIO;
3958 if (!kvm->arch.vpit)
3959 goto out;
f0d66275 3960 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3961 break;
3962 }
e9f42757
BK		 3963 case KVM_GET_PIT2: {
3964 r = -ENXIO;
3965 if (!kvm->arch.vpit)
3966 goto out;
3967 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3968 if (r)
3969 goto out;
3970 r = -EFAULT;
3971 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3972 goto out;
3973 r = 0;
3974 break;
3975 }
3976 case KVM_SET_PIT2: {
3977 r = -EFAULT;
3978 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3979 goto out;
3980 r = -ENXIO;
3981 if (!kvm->arch.vpit)
3982 goto out;
3983 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3984 break;
3985 }
52d939a0
MT		 3986 case KVM_REINJECT_CONTROL: {
3987 struct kvm_reinject_control control;
3988 r = -EFAULT;
3989 if (copy_from_user(&control, argp, sizeof(control)))
3990 goto out;
3991 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3992 break;
3993 }
d71ba788
PB		 3994 case KVM_SET_BOOT_CPU_ID:
3995 r = 0;
3996 mutex_lock(&kvm->lock);
3997 if (atomic_read(&kvm->online_vcpus) != 0)
3998 r = -EBUSY;
3999 else
4000 kvm->arch.bsp_vcpu_id = arg;
4001 mutex_unlock(&kvm->lock);
4002 break;
ffde22ac
ES		 4003 case KVM_XEN_HVM_CONFIG: {
4004 r = -EFAULT;
4005 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4006 sizeof(struct kvm_xen_hvm_config)))
4007 goto out;
4008 r = -EINVAL;
4009 if (kvm->arch.xen_hvm_config.flags)
4010 goto out;
4011 r = 0;
4012 break;
4013 }
afbcf7ab 4014 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4015 struct kvm_clock_data user_ns;
4016 u64 now_ns;
4017 s64 delta;
4018
4019 r = -EFAULT;
4020 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4021 goto out;
4022
4023 r = -EINVAL;
4024 if (user_ns.flags)
4025 goto out;
4026
4027 r = 0;
395c6b0a 4028 local_irq_disable();
759379dd 4029 now_ns = get_kernel_ns();
afbcf7ab 4030 delta = user_ns.clock - now_ns;
395c6b0a 4031 local_irq_enable();
afbcf7ab 4032 kvm->arch.kvmclock_offset = delta;
2e762ff7 4033 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4034 break;
4035 }
4036 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4037 struct kvm_clock_data user_ns;
4038 u64 now_ns;
4039
395c6b0a 4040 local_irq_disable();
759379dd 4041 now_ns = get_kernel_ns();
afbcf7ab 4042 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4043 local_irq_enable();
afbcf7ab 4044 user_ns.flags = 0;
97e69aa6 4045 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4046
4047 r = -EFAULT;
4048 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4049 goto out;
4050 r = 0;
4051 break;
4052 }
90de4a18
NA		 4053 case KVM_ENABLE_CAP: {
4054 struct kvm_enable_cap cap;
afbcf7ab 4055
90de4a18
NA		 4056 r = -EFAULT;
4057 if (copy_from_user(&cap, argp, sizeof(cap)))
4058 goto out;
4059 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4060 break;
4061 }
1fe779f8 4062 default:
c274e03a 4063 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4064 }
4065out:
4066 return r;
4067}
4068
a16b043c 4069static void kvm_init_msr_list(void)
043405e1
CO		 4070{
4071 u32 dummy[2];
4072 unsigned i, j;
4073
62ef68bb 4074 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4075 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4076 continue;
93c4adc7
PB		 4077
4078 /*
4079 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4080 * to the guests in some cases.
93c4adc7
PB		 4081 */
4082 switch (msrs_to_save[i]) {
4083 case MSR_IA32_BNDCFGS:
4084 if (!kvm_x86_ops->mpx_supported())
4085 continue;
4086 break;
9dbe6cf9
PB		 4087 case MSR_TSC_AUX:
4088 if (!kvm_x86_ops->rdtscp_supported())
4089 continue;
4090 break;
93c4adc7
PB		 4091 default:
4092 break;
4093 }
4094
043405e1
CO		 4095 if (j < i)
4096 msrs_to_save[j] = msrs_to_save[i];
4097 j++;
4098 }
4099 num_msrs_to_save = j;
62ef68bb
PB		 4100
4101 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4102 switch (emulated_msrs[i]) {
6d396b55
PB		 4103 case MSR_IA32_SMBASE:
4104 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4105 continue;
4106 break;
62ef68bb
PB		 4107 default:
4108 break;
4109 }
4110
4111 if (j < i)
4112 emulated_msrs[j] = emulated_msrs[i];
4113 j++;
4114 }
4115 num_emulated_msrs = j;
043405e1
CO		 4116}
4117
bda9020e
MT		 4118static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4119 const void *v)
bbd9b64e 4120{
70252a10
AK		 4121 int handled = 0;
4122 int n;
4123
4124 do {
4125 n = min(len, 8);
bce87cce 4126 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4127 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4128 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4129 break;
4130 handled += n;
4131 addr += n;
4132 len -= n;
4133 v += n;
4134 } while (len);
bbd9b64e 4135
70252a10 4136 return handled;
bbd9b64e
CO		 4137}
4138
bda9020e 4139static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4140{
70252a10
AK		 4141 int handled = 0;
4142 int n;
4143
4144 do {
4145 n = min(len, 8);
bce87cce 4146 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4147 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4148 addr, n, v))
4149 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4150 break;
4151 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4152 handled += n;
4153 addr += n;
4154 len -= n;
4155 v += n;
4156 } while (len);
bbd9b64e 4157
70252a10 4158 return handled;
bbd9b64e
CO		 4159}
4160
2dafc6c2
GN		 4161static void kvm_set_segment(struct kvm_vcpu *vcpu,
4162 struct kvm_segment *var, int seg)
4163{
4164 kvm_x86_ops->set_segment(vcpu, var, seg);
4165}
4166
4167void kvm_get_segment(struct kvm_vcpu *vcpu,
4168 struct kvm_segment *var, int seg)
4169{
4170 kvm_x86_ops->get_segment(vcpu, var, seg);
4171}
4172
54987b7a
PB		 4173gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4174 struct x86_exception *exception)
02f59dc9
JR		 4175{
4176 gpa_t t_gpa;
02f59dc9
JR		 4177
4178 BUG_ON(!mmu_is_nested(vcpu));
4179
4180 /* NPT walks are always user-walks */
4181 access |= PFERR_USER_MASK;
54987b7a 4182 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4183
4184 return t_gpa;
4185}
4186
ab9ae313
AK		 4187gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4188 struct x86_exception *exception)
1871c602
GN		 4189{
4190 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4191 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4192}
4193
ab9ae313
AK		 4194 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4195 struct x86_exception *exception)
1871c602
GN		 4196{
4197 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4198 access |= PFERR_FETCH_MASK;
ab9ae313 4199 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4200}
4201
ab9ae313
AK		 4202gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4203 struct x86_exception *exception)
1871c602
GN		 4204{
4205 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4206 access |= PFERR_WRITE_MASK;
ab9ae313 4207 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4208}
4209
4210/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4211gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4212 struct x86_exception *exception)
1871c602 4213{
ab9ae313 4214 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4215}
4216
4217static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4218 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4219 struct x86_exception *exception)
bbd9b64e
CO		 4220{
4221 void *data = val;
10589a46 4222 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4223
4224 while (bytes) {
14dfe855 4225 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4226 exception);
bbd9b64e 4227 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4228 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4229 int ret;
4230
bcc55cba 4231 if (gpa == UNMAPPED_GVA)
ab9ae313 4232 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4233 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4234 offset, toread);
10589a46 4235 if (ret < 0) {
c3cd7ffa 4236 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4237 goto out;
4238 }
bbd9b64e 4239
77c2002e
IE		 4240 bytes -= toread;
4241 data += toread;
4242 addr += toread;
bbd9b64e 4243 }
10589a46 4244out:
10589a46 4245 return r;
bbd9b64e 4246}
77c2002e 4247
1871c602 4248/* used for instruction fetching */
0f65dd70
AK		 4249static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4250 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4251 struct x86_exception *exception)
1871c602 4252{
0f65dd70 4253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4254 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4255 unsigned offset;
4256 int ret;
0f65dd70 4257
44583cba
PB		 4258 /* Inline kvm_read_guest_virt_helper for speed. */
4259 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4260 exception);
4261 if (unlikely(gpa == UNMAPPED_GVA))
4262 return X86EMUL_PROPAGATE_FAULT;
4263
4264 offset = addr & (PAGE_SIZE-1);
4265 if (WARN_ON(offset + bytes > PAGE_SIZE))
4266 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4267 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4268 offset, bytes);
44583cba
PB		 4269 if (unlikely(ret < 0))
4270 return X86EMUL_IO_NEEDED;
4271
4272 return X86EMUL_CONTINUE;
1871c602
GN		 4273}
4274
064aea77 4275int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4276 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4277 struct x86_exception *exception)
1871c602 4278{
0f65dd70 4279 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4280 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4281
1871c602 4282 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4283 exception);
1871c602 4284}
064aea77 4285EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4286
0f65dd70
AK		 4287static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4288 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4289 struct x86_exception *exception)
1871c602 4290{
0f65dd70 4291 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4292 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4293}
4294
7a036a6f
RK		 4295static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4296 unsigned long addr, void *val, unsigned int bytes)
4297{
4298 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4299 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4300
4301 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4302}
4303
6a4d7550 4304int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4305 gva_t addr, void *val,
2dafc6c2 4306 unsigned int bytes,
bcc55cba 4307 struct x86_exception *exception)
77c2002e 4308{
0f65dd70 4309 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4310 void *data = val;
4311 int r = X86EMUL_CONTINUE;
4312
4313 while (bytes) {
14dfe855
JR		 4314 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4315 PFERR_WRITE_MASK,
ab9ae313 4316 exception);
77c2002e
IE		 4317 unsigned offset = addr & (PAGE_SIZE-1);
4318 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4319 int ret;
4320
bcc55cba 4321 if (gpa == UNMAPPED_GVA)
ab9ae313 4322 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4323 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4324 if (ret < 0) {
c3cd7ffa 4325 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4326 goto out;
4327 }
4328
4329 bytes -= towrite;
4330 data += towrite;
4331 addr += towrite;
4332 }
4333out:
4334 return r;
4335}
6a4d7550 4336EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4337
af7cc7d1
XG		 4338static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4339 gpa_t *gpa, struct x86_exception *exception,
4340 bool write)
4341{
97d64b78
AK		 4342 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4343 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4344
be94f6b7
HH		 4345 /*
4346 * currently PKRU is only applied to ept enabled guest so
4347 * there is no pkey in EPT page table for L1 guest or EPT
4348 * shadow page table for L2 guest.
4349 */
97d64b78 4350 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4351 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4352 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4353 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4354 (gva & (PAGE_SIZE - 1));
4f022648 4355 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4356 return 1;
4357 }
4358
af7cc7d1
XG		 4359 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4360
4361 if (*gpa == UNMAPPED_GVA)
4362 return -1;
4363
4364 /* For APIC access vmexit */
4365 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4366 return 1;
4367
4f022648
XG		 4368 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4369 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4370 return 1;
4f022648 4371 }
bebb106a 4372
af7cc7d1
XG		 4373 return 0;
4374}
4375
3200f405 4376int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4377 const void *val, int bytes)
bbd9b64e
CO		 4378{
4379 int ret;
4380
54bf36aa 4381 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4382 if (ret < 0)
bbd9b64e 4383 return 0;
0eb05bf2 4384 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4385 return 1;
4386}
4387
77d197b2
XG		 4388struct read_write_emulator_ops {
4389 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4390 int bytes);
4391 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4392 void *val, int bytes);
4393 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4394 int bytes, void *val);
4395 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4396 void *val, int bytes);
4397 bool write;
4398};
4399
4400static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4401{
4402 if (vcpu->mmio_read_completed) {
77d197b2 4403 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4404 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4405 vcpu->mmio_read_completed = 0;
4406 return 1;
4407 }
4408
4409 return 0;
4410}
4411
4412static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4413 void *val, int bytes)
4414{
54bf36aa 4415 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4416}
4417
4418static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4419 void *val, int bytes)
4420{
4421 return emulator_write_phys(vcpu, gpa, val, bytes);
4422}
4423
4424static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4425{
4426 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4427 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4428}
4429
4430static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4431 void *val, int bytes)
4432{
4433 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4434 return X86EMUL_IO_NEEDED;
4435}
4436
4437static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4438 void *val, int bytes)
4439{
f78146b0
AK		 4440 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4441
87da7e66 4442 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4443 return X86EMUL_CONTINUE;
4444}
4445
0fbe9b0b 4446static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4447 .read_write_prepare = read_prepare,
4448 .read_write_emulate = read_emulate,
4449 .read_write_mmio = vcpu_mmio_read,
4450 .read_write_exit_mmio = read_exit_mmio,
4451};
4452
0fbe9b0b 4453static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4454 .read_write_emulate = write_emulate,
4455 .read_write_mmio = write_mmio,
4456 .read_write_exit_mmio = write_exit_mmio,
4457 .write = true,
4458};
4459
22388a3c
XG		 4460static int emulator_read_write_onepage(unsigned long addr, void *val,
4461 unsigned int bytes,
4462 struct x86_exception *exception,
4463 struct kvm_vcpu *vcpu,
0fbe9b0b 4464 const struct read_write_emulator_ops *ops)
bbd9b64e 4465{
af7cc7d1
XG		 4466 gpa_t gpa;
4467 int handled, ret;
22388a3c 4468 bool write = ops->write;
f78146b0 4469 struct kvm_mmio_fragment *frag;
10589a46 4470
22388a3c 4471 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4472
af7cc7d1 4473 if (ret < 0)
bbd9b64e 4474 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4475
4476 /* For APIC access vmexit */
af7cc7d1 4477 if (ret)
bbd9b64e
CO		 4478 goto mmio;
4479
22388a3c 4480 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4481 return X86EMUL_CONTINUE;
4482
4483mmio:
4484 /*
4485 * Is this MMIO handled locally?
4486 */
22388a3c 4487 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4488 if (handled == bytes)
bbd9b64e 4489 return X86EMUL_CONTINUE;
bbd9b64e 4490
70252a10
AK		 4491 gpa += handled;
4492 bytes -= handled;
4493 val += handled;
4494
87da7e66
XG		 4495 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4496 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4497 frag->gpa = gpa;
4498 frag->data = val;
4499 frag->len = bytes;
f78146b0 4500 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4501}
4502
52eb5a6d
XL		 4503static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4504 unsigned long addr,
22388a3c
XG		 4505 void *val, unsigned int bytes,
4506 struct x86_exception *exception,
0fbe9b0b 4507 const struct read_write_emulator_ops *ops)
bbd9b64e 4508{
0f65dd70 4509 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4510 gpa_t gpa;
4511 int rc;
4512
4513 if (ops->read_write_prepare &&
4514 ops->read_write_prepare(vcpu, val, bytes))
4515 return X86EMUL_CONTINUE;
4516
4517 vcpu->mmio_nr_fragments = 0;
0f65dd70 4518
bbd9b64e
CO		 4519 /* Crossing a page boundary? */
4520 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4521 int now;
bbd9b64e
CO		 4522
4523 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4524 rc = emulator_read_write_onepage(addr, val, now, exception,
4525 vcpu, ops);
4526
bbd9b64e
CO		 4527 if (rc != X86EMUL_CONTINUE)
4528 return rc;
4529 addr += now;
bac15531
NA		 4530 if (ctxt->mode != X86EMUL_MODE_PROT64)
4531 addr = (u32)addr;
bbd9b64e
CO		 4532 val += now;
4533 bytes -= now;
4534 }
22388a3c 4535
f78146b0
AK		 4536 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4537 vcpu, ops);
4538 if (rc != X86EMUL_CONTINUE)
4539 return rc;
4540
4541 if (!vcpu->mmio_nr_fragments)
4542 return rc;
4543
4544 gpa = vcpu->mmio_fragments[0].gpa;
4545
4546 vcpu->mmio_needed = 1;
4547 vcpu->mmio_cur_fragment = 0;
4548
87da7e66 4549 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4550 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4551 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4552 vcpu->run->mmio.phys_addr = gpa;
4553
4554 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4555}
4556
4557static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4558 unsigned long addr,
4559 void *val,
4560 unsigned int bytes,
4561 struct x86_exception *exception)
4562{
4563 return emulator_read_write(ctxt, addr, val, bytes,
4564 exception, &read_emultor);
4565}
4566
52eb5a6d 4567static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4568 unsigned long addr,
4569 const void *val,
4570 unsigned int bytes,
4571 struct x86_exception *exception)
4572{
4573 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4574 exception, &write_emultor);
bbd9b64e 4575}
bbd9b64e 4576
daea3e73
AK		 4577#define CMPXCHG_TYPE(t, ptr, old, new) \
4578 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4579
4580#ifdef CONFIG_X86_64
4581# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4582#else
4583# define CMPXCHG64(ptr, old, new) \
9749a6c0 4584 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4585#endif
4586
0f65dd70
AK		 4587static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4588 unsigned long addr,
bbd9b64e
CO		 4589 const void *old,
4590 const void *new,
4591 unsigned int bytes,
0f65dd70 4592 struct x86_exception *exception)
bbd9b64e 4593{
0f65dd70 4594 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4595 gpa_t gpa;
4596 struct page *page;
4597 char *kaddr;
4598 bool exchanged;
2bacc55c 4599
daea3e73
AK		 4600 /* guests cmpxchg8b have to be emulated atomically */
4601 if (bytes > 8 || (bytes & (bytes - 1)))
4602 goto emul_write;
10589a46 4603
daea3e73 4604 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4605
daea3e73
AK		 4606 if (gpa == UNMAPPED_GVA ||
4607 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4608 goto emul_write;
2bacc55c 4609
daea3e73
AK		 4610 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4611 goto emul_write;
72dc67a6 4612
54bf36aa 4613 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4614 if (is_error_page(page))
c19b8bd6 4615 goto emul_write;
72dc67a6 4616
8fd75e12 4617 kaddr = kmap_atomic(page);
daea3e73
AK		 4618 kaddr += offset_in_page(gpa);
4619 switch (bytes) {
4620 case 1:
4621 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4622 break;
4623 case 2:
4624 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4625 break;
4626 case 4:
4627 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4628 break;
4629 case 8:
4630 exchanged = CMPXCHG64(kaddr, old, new);
4631 break;
4632 default:
4633 BUG();
2bacc55c 4634 }
8fd75e12 4635 kunmap_atomic(kaddr);
daea3e73
AK		 4636 kvm_release_page_dirty(page);
4637
4638 if (!exchanged)
4639 return X86EMUL_CMPXCHG_FAILED;
4640
54bf36aa 4641 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4642 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4643
4644 return X86EMUL_CONTINUE;
4a5f48f6 4645
3200f405 4646emul_write:
daea3e73 4647 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4648
0f65dd70 4649 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4650}
4651
cf8f70bf
GN		 4652static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4653{
4654 /* TODO: String I/O for in kernel device */
4655 int r;
4656
4657 if (vcpu->arch.pio.in)
e32edf4f 4658 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4659 vcpu->arch.pio.size, pd);
4660 else
e32edf4f 4661 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4662 vcpu->arch.pio.port, vcpu->arch.pio.size,
4663 pd);
4664 return r;
4665}
4666
6f6fbe98
XG		 4667static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4668 unsigned short port, void *val,
4669 unsigned int count, bool in)
cf8f70bf 4670{
cf8f70bf 4671 vcpu->arch.pio.port = port;
6f6fbe98 4672 vcpu->arch.pio.in = in;
7972995b 4673 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4674 vcpu->arch.pio.size = size;
4675
4676 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4677 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4678 return 1;
4679 }
4680
4681 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4682 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4683 vcpu->run->io.size = size;
4684 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4685 vcpu->run->io.count = count;
4686 vcpu->run->io.port = port;
4687
4688 return 0;
4689}
4690
6f6fbe98
XG		 4691static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4692 int size, unsigned short port, void *val,
4693 unsigned int count)
cf8f70bf 4694{
ca1d4a9e 4695 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4696 int ret;
ca1d4a9e 4697
6f6fbe98
XG		 4698 if (vcpu->arch.pio.count)
4699 goto data_avail;
cf8f70bf 4700
6f6fbe98
XG		 4701 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4702 if (ret) {
4703data_avail:
4704 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4705 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4706 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4707 return 1;
4708 }
4709
cf8f70bf
GN		 4710 return 0;
4711}
4712
6f6fbe98
XG		 4713static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4714 int size, unsigned short port,
4715 const void *val, unsigned int count)
4716{
4717 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4718
4719 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4720 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4721 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4722}
4723
bbd9b64e
CO		 4724static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4725{
4726 return kvm_x86_ops->get_segment_base(vcpu, seg);
4727}
4728
3cb16fe7 4729static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4730{
3cb16fe7 4731 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4732}
4733
5cb56059 4734int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4735{
4736 if (!need_emulate_wbinvd(vcpu))
4737 return X86EMUL_CONTINUE;
4738
4739 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4740 int cpu = get_cpu();
4741
4742 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4743 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4744 wbinvd_ipi, NULL, 1);
2eec7343 4745 put_cpu();
f5f48ee1 4746 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4747 } else
4748 wbinvd();
f5f48ee1
SY		 4749 return X86EMUL_CONTINUE;
4750}
5cb56059
JS		 4751
4752int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4753{
4754 kvm_x86_ops->skip_emulated_instruction(vcpu);
4755 return kvm_emulate_wbinvd_noskip(vcpu);
4756}
f5f48ee1
SY		 4757EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4758
5cb56059
JS		 4759
4760
bcaf5cc5
AK		 4761static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4762{
5cb56059 4763 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4764}
4765
52eb5a6d
XL		 4766static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4767 unsigned long *dest)
bbd9b64e 4768{
16f8a6f9 4769 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4770}
4771
52eb5a6d
XL		 4772static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4773 unsigned long value)
bbd9b64e 4774{
338dbc97 4775
717746e3 4776 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4777}
4778
52a46617 4779static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4780{
52a46617 4781 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4782}
4783
717746e3 4784static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4785{
717746e3 4786 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4787 unsigned long value;
4788
4789 switch (cr) {
4790 case 0:
4791 value = kvm_read_cr0(vcpu);
4792 break;
4793 case 2:
4794 value = vcpu->arch.cr2;
4795 break;
4796 case 3:
9f8fe504 4797 value = kvm_read_cr3(vcpu);
52a46617
GN		 4798 break;
4799 case 4:
4800 value = kvm_read_cr4(vcpu);
4801 break;
4802 case 8:
4803 value = kvm_get_cr8(vcpu);
4804 break;
4805 default:
a737f256 4806 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4807 return 0;
4808 }
4809
4810 return value;
4811}
4812
717746e3 4813static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4814{
717746e3 4815 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4816 int res = 0;
4817
52a46617
GN		 4818 switch (cr) {
4819 case 0:
49a9b07e 4820 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4821 break;
4822 case 2:
4823 vcpu->arch.cr2 = val;
4824 break;
4825 case 3:
2390218b 4826 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4827 break;
4828 case 4:
a83b29c6 4829 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4830 break;
4831 case 8:
eea1cff9 4832 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4833 break;
4834 default:
a737f256 4835 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4836 res = -1;
52a46617 4837 }
0f12244f
GN		 4838
4839 return res;
52a46617
GN		 4840}
4841
717746e3 4842static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4843{
717746e3 4844 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4845}
4846
4bff1e86 4847static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4848{
4bff1e86 4849 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4850}
4851
4bff1e86 4852static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4853{
4bff1e86 4854 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4855}
4856
1ac9d0cf
AK		 4857static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4858{
4859 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4860}
4861
4862static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4863{
4864 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4865}
4866
4bff1e86
AK		 4867static unsigned long emulator_get_cached_segment_base(
4868 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4869{
4bff1e86 4870 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4871}
4872
1aa36616
AK		 4873static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4874 struct desc_struct *desc, u32 *base3,
4875 int seg)
2dafc6c2
GN		 4876{
4877 struct kvm_segment var;
4878
4bff1e86 4879 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4880 *selector = var.selector;
2dafc6c2 4881
378a8b09
GN		 4882 if (var.unusable) {
4883 memset(desc, 0, sizeof(*desc));
2dafc6c2 4884 return false;
378a8b09 4885 }
2dafc6c2
GN		 4886
4887 if (var.g)
4888 var.limit >>= 12;
4889 set_desc_limit(desc, var.limit);
4890 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4891#ifdef CONFIG_X86_64
4892 if (base3)
4893 *base3 = var.base >> 32;
4894#endif
2dafc6c2
GN		 4895 desc->type = var.type;
4896 desc->s = var.s;
4897 desc->dpl = var.dpl;
4898 desc->p = var.present;
4899 desc->avl = var.avl;
4900 desc->l = var.l;
4901 desc->d = var.db;
4902 desc->g = var.g;
4903
4904 return true;
4905}
4906
1aa36616
AK		 4907static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4908 struct desc_struct *desc, u32 base3,
4909 int seg)
2dafc6c2 4910{
4bff1e86 4911 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4912 struct kvm_segment var;
4913
1aa36616 4914 var.selector = selector;
2dafc6c2 4915 var.base = get_desc_base(desc);
5601d05b
GN		 4916#ifdef CONFIG_X86_64
4917 var.base |= ((u64)base3) << 32;
4918#endif
2dafc6c2
GN		 4919 var.limit = get_desc_limit(desc);
4920 if (desc->g)
4921 var.limit = (var.limit << 12) | 0xfff;
4922 var.type = desc->type;
2dafc6c2
GN		 4923 var.dpl = desc->dpl;
4924 var.db = desc->d;
4925 var.s = desc->s;
4926 var.l = desc->l;
4927 var.g = desc->g;
4928 var.avl = desc->avl;
4929 var.present = desc->p;
4930 var.unusable = !var.present;
4931 var.padding = 0;
4932
4933 kvm_set_segment(vcpu, &var, seg);
4934 return;
4935}
4936
717746e3
AK		 4937static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4938 u32 msr_index, u64 *pdata)
4939{
609e36d3
PB		 4940 struct msr_data msr;
4941 int r;
4942
4943 msr.index = msr_index;
4944 msr.host_initiated = false;
4945 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4946 if (r)
4947 return r;
4948
4949 *pdata = msr.data;
4950 return 0;
717746e3
AK		 4951}
4952
4953static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4954 u32 msr_index, u64 data)
4955{
8fe8ab46
WA		 4956 struct msr_data msr;
4957
4958 msr.data = data;
4959 msr.index = msr_index;
4960 msr.host_initiated = false;
4961 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4962}
4963
64d60670
PB		 4964static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4965{
4966 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4967
4968 return vcpu->arch.smbase;
4969}
4970
4971static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4972{
4973 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4974
4975 vcpu->arch.smbase = smbase;
4976}
4977
67f4d428
NA		 4978static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4979 u32 pmc)
4980{
c6702c9d 4981 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4982}
4983
222d21aa
AK		 4984static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4985 u32 pmc, u64 *pdata)
4986{
c6702c9d 4987 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4988}
4989
6c3287f7
AK		 4990static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4991{
4992 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4993}
4994
5037f6f3
AK		 4995static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4996{
4997 preempt_disable();
5197b808 4998 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4999 /*
5000 * CR0.TS may reference the host fpu state, not the guest fpu state,
5001 * so it may be clear at this point.
5002 */
5003 clts();
5004}
5005
5006static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5007{
5008 preempt_enable();
5009}
5010
2953538e 5011static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5012 struct x86_instruction_info *info,
c4f035c6
AK		 5013 enum x86_intercept_stage stage)
5014{
2953538e 5015 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5016}
5017
0017f93a 5018static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5019 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5020{
0017f93a 5021 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5022}
5023
dd856efa
AK		 5024static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5025{
5026 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5027}
5028
5029static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5030{
5031 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5032}
5033
801806d9
NA		 5034static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5035{
5036 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5037}
5038
0225fb50 5039static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5040 .read_gpr = emulator_read_gpr,
5041 .write_gpr = emulator_write_gpr,
1871c602 5042 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5043 .write_std = kvm_write_guest_virt_system,
7a036a6f 5044 .read_phys = kvm_read_guest_phys_system,
1871c602 5045 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5046 .read_emulated = emulator_read_emulated,
5047 .write_emulated = emulator_write_emulated,
5048 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5049 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5050 .pio_in_emulated = emulator_pio_in_emulated,
5051 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5052 .get_segment = emulator_get_segment,
5053 .set_segment = emulator_set_segment,
5951c442 5054 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5055 .get_gdt = emulator_get_gdt,
160ce1f1 5056 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5057 .set_gdt = emulator_set_gdt,
5058 .set_idt = emulator_set_idt,
52a46617
GN		 5059 .get_cr = emulator_get_cr,
5060 .set_cr = emulator_set_cr,
9c537244 5061 .cpl = emulator_get_cpl,
35aa5375
GN		 5062 .get_dr = emulator_get_dr,
5063 .set_dr = emulator_set_dr,
64d60670
PB		 5064 .get_smbase = emulator_get_smbase,
5065 .set_smbase = emulator_set_smbase,
717746e3
AK		 5066 .set_msr = emulator_set_msr,
5067 .get_msr = emulator_get_msr,
67f4d428 5068 .check_pmc = emulator_check_pmc,
222d21aa 5069 .read_pmc = emulator_read_pmc,
6c3287f7 5070 .halt = emulator_halt,
bcaf5cc5 5071 .wbinvd = emulator_wbinvd,
d6aa1000 5072 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5073 .get_fpu = emulator_get_fpu,
5074 .put_fpu = emulator_put_fpu,
c4f035c6 5075 .intercept = emulator_intercept,
bdb42f5a 5076 .get_cpuid = emulator_get_cpuid,
801806d9 5077 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5078};
5079
95cb2295
GN		 5080static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5081{
37ccdcbe 5082 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5083 /*
5084 * an sti; sti; sequence only disable interrupts for the first
5085 * instruction. So, if the last instruction, be it emulated or
5086 * not, left the system with the INT_STI flag enabled, it
5087 * means that the last instruction is an sti. We should not
5088 * leave the flag on in this case. The same goes for mov ss
5089 */
37ccdcbe
PB		 5090 if (int_shadow & mask)
5091 mask = 0;
6addfc42 5092 if (unlikely(int_shadow || mask)) {
95cb2295 5093 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5094 if (!mask)
5095 kvm_make_request(KVM_REQ_EVENT, vcpu);
5096 }
95cb2295
GN		 5097}
5098
ef54bcfe 5099static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5100{
5101 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5102 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5103 return kvm_propagate_fault(vcpu, &ctxt->exception);
5104
5105 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5106 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5107 ctxt->exception.error_code);
54b8486f 5108 else
da9cb575 5109 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5110 return false;
54b8486f
GN		 5111}
5112
8ec4722d
MG		 5113static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5114{
adf52235 5115 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5116 int cs_db, cs_l;
5117
8ec4722d
MG		 5118 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5119
adf52235
TY		 5120 ctxt->eflags = kvm_get_rflags(vcpu);
5121 ctxt->eip = kvm_rip_read(vcpu);
5122 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5123 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5124 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5125 cs_db ? X86EMUL_MODE_PROT32 :
5126 X86EMUL_MODE_PROT16;
a584539b 5127 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5128 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5129 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5130 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5131
dd856efa 5132 init_decode_cache(ctxt);
7ae441ea 5133 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5134}
5135
71f9833b 5136int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5137{
9d74191a 5138 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5139 int ret;
5140
5141 init_emulate_ctxt(vcpu);
5142
9dac77fa
AK		 5143 ctxt->op_bytes = 2;
5144 ctxt->ad_bytes = 2;
5145 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5146 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5147
5148 if (ret != X86EMUL_CONTINUE)
5149 return EMULATE_FAIL;
5150
9dac77fa 5151 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5152 kvm_rip_write(vcpu, ctxt->eip);
5153 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5154
5155 if (irq == NMI_VECTOR)
7460fb4a 5156 vcpu->arch.nmi_pending = 0;
63995653
MG		 5157 else
5158 vcpu->arch.interrupt.pending = false;
5159
5160 return EMULATE_DONE;
5161}
5162EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5163
6d77dbfc
GN		 5164static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5165{
fc3a9157
JR		 5166 int r = EMULATE_DONE;
5167
6d77dbfc
GN		 5168 ++vcpu->stat.insn_emulation_fail;
5169 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5170 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5171 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5172 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5173 vcpu->run->internal.ndata = 0;
5174 r = EMULATE_FAIL;
5175 }
6d77dbfc 5176 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5177
5178 return r;
6d77dbfc
GN		 5179}
5180
93c05d3e 5181static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5182 bool write_fault_to_shadow_pgtable,
5183 int emulation_type)
a6f177ef 5184{
95b3cf69 5185 gpa_t gpa = cr2;
ba049e93 5186 kvm_pfn_t pfn;
a6f177ef 5187
991eebf9
GN		 5188 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5189 return false;
5190
95b3cf69
XG		 5191 if (!vcpu->arch.mmu.direct_map) {
5192 /*
5193 * Write permission should be allowed since only
5194 * write access need to be emulated.
5195 */
5196 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5197
95b3cf69
XG		 5198 /*
5199 * If the mapping is invalid in guest, let cpu retry
5200 * it to generate fault.
5201 */
5202 if (gpa == UNMAPPED_GVA)
5203 return true;
5204 }
a6f177ef 5205
8e3d9d06
XG		 5206 /*
5207 * Do not retry the unhandleable instruction if it faults on the
5208 * readonly host memory, otherwise it will goto a infinite loop:
5209 * retry instruction -> write #PF -> emulation fail -> retry
5210 * instruction -> ...
5211 */
5212 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5213
5214 /*
5215 * If the instruction failed on the error pfn, it can not be fixed,
5216 * report the error to userspace.
5217 */
5218 if (is_error_noslot_pfn(pfn))
5219 return false;
5220
5221 kvm_release_pfn_clean(pfn);
5222
5223 /* The instructions are well-emulated on direct mmu. */
5224 if (vcpu->arch.mmu.direct_map) {
5225 unsigned int indirect_shadow_pages;
5226
5227 spin_lock(&vcpu->kvm->mmu_lock);
5228 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5229 spin_unlock(&vcpu->kvm->mmu_lock);
5230
5231 if (indirect_shadow_pages)
5232 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5233
a6f177ef 5234 return true;
8e3d9d06 5235 }
a6f177ef 5236
95b3cf69
XG		 5237 /*
5238 * if emulation was due to access to shadowed page table
5239 * and it failed try to unshadow page and re-enter the
5240 * guest to let CPU execute the instruction.
5241 */
5242 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5243
5244 /*
5245 * If the access faults on its page table, it can not
5246 * be fixed by unprotecting shadow page and it should
5247 * be reported to userspace.
5248 */
5249 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5250}
5251
1cb3f3ae
XG		 5252static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5253 unsigned long cr2, int emulation_type)
5254{
5255 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5256 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5257
5258 last_retry_eip = vcpu->arch.last_retry_eip;
5259 last_retry_addr = vcpu->arch.last_retry_addr;
5260
5261 /*
5262 * If the emulation is caused by #PF and it is non-page_table
5263 * writing instruction, it means the VM-EXIT is caused by shadow
5264 * page protected, we can zap the shadow page and retry this
5265 * instruction directly.
5266 *
5267 * Note: if the guest uses a non-page-table modifying instruction
5268 * on the PDE that points to the instruction, then we will unmap
5269 * the instruction and go to an infinite loop. So, we cache the
5270 * last retried eip and the last fault address, if we meet the eip
5271 * and the address again, we can break out of the potential infinite
5272 * loop.
5273 */
5274 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5275
5276 if (!(emulation_type & EMULTYPE_RETRY))
5277 return false;
5278
5279 if (x86_page_table_writing_insn(ctxt))
5280 return false;
5281
5282 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5283 return false;
5284
5285 vcpu->arch.last_retry_eip = ctxt->eip;
5286 vcpu->arch.last_retry_addr = cr2;
5287
5288 if (!vcpu->arch.mmu.direct_map)
5289 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5290
22368028 5291 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5292
5293 return true;
5294}
5295
716d51ab
GN		 5296static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5297static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5298
64d60670 5299static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5300{
64d60670 5301 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5302 /* This is a good place to trace that we are exiting SMM. */
5303 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5304
64d60670
PB		 5305 if (unlikely(vcpu->arch.smi_pending)) {
5306 kvm_make_request(KVM_REQ_SMI, vcpu);
5307 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5308 } else {
5309 /* Process a latched INIT, if any. */
5310 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5311 }
5312 }
699023e2
PB		 5313
5314 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5315}
5316
5317static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5318{
5319 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5320
a584539b 5321 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5322
5323 if (changed & HF_SMM_MASK)
5324 kvm_smm_changed(vcpu);
a584539b
PB		 5325}
5326
4a1e10d5
PB		 5327static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5328 unsigned long *db)
5329{
5330 u32 dr6 = 0;
5331 int i;
5332 u32 enable, rwlen;
5333
5334 enable = dr7;
5335 rwlen = dr7 >> 16;
5336 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5337 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5338 dr6 |= (1 << i);
5339 return dr6;
5340}
5341
6addfc42 5342static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5343{
5344 struct kvm_run *kvm_run = vcpu->run;
5345
5346 /*
6addfc42
PB		 5347 * rflags is the old, "raw" value of the flags. The new value has
5348 * not been saved yet.
663f4c61
PB		 5349 *
5350 * This is correct even for TF set by the guest, because "the
5351 * processor will not generate this exception after the instruction
5352 * that sets the TF flag".
5353 */
663f4c61
PB		 5354 if (unlikely(rflags & X86_EFLAGS_TF)) {
5355 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5356 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5357 DR6_RTM;
663f4c61
PB		 5358 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5359 kvm_run->debug.arch.exception = DB_VECTOR;
5360 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5361 *r = EMULATE_USER_EXIT;
5362 } else {
5363 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5364 /*
5365 * "Certain debug exceptions may clear bit 0-3. The
5366 * remaining contents of the DR6 register are never
5367 * cleared by the processor".
5368 */
5369 vcpu->arch.dr6 &= ~15;
6f43ed01 5370 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5371 kvm_queue_exception(vcpu, DB_VECTOR);
5372 }
5373 }
5374}
5375
4a1e10d5
PB		 5376static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5377{
4a1e10d5
PB		 5378 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5379 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5380 struct kvm_run *kvm_run = vcpu->run;
5381 unsigned long eip = kvm_get_linear_rip(vcpu);
5382 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5383 vcpu->arch.guest_debug_dr7,
5384 vcpu->arch.eff_db);
5385
5386 if (dr6 != 0) {
6f43ed01 5387 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5388 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5389 kvm_run->debug.arch.exception = DB_VECTOR;
5390 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5391 *r = EMULATE_USER_EXIT;
5392 return true;
5393 }
5394 }
5395
4161a569
NA		 5396 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5397 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5398 unsigned long eip = kvm_get_linear_rip(vcpu);
5399 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5400 vcpu->arch.dr7,
5401 vcpu->arch.db);
5402
5403 if (dr6 != 0) {
5404 vcpu->arch.dr6 &= ~15;
6f43ed01 5405 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5406 kvm_queue_exception(vcpu, DB_VECTOR);
5407 *r = EMULATE_DONE;
5408 return true;
5409 }
5410 }
5411
5412 return false;
5413}
5414
51d8b661
AP		 5415int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5416 unsigned long cr2,
dc25e89e
AP		 5417 int emulation_type,
5418 void *insn,
5419 int insn_len)
bbd9b64e 5420{
95cb2295 5421 int r;
9d74191a 5422 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5423 bool writeback = true;
93c05d3e 5424 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5425
93c05d3e
XG		 5426 /*
5427 * Clear write_fault_to_shadow_pgtable here to ensure it is
5428 * never reused.
5429 */
5430 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5431 kvm_clear_exception_queue(vcpu);
8d7d8102 5432
571008da 5433 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5434 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5435
5436 /*
5437 * We will reenter on the same instruction since
5438 * we do not set complete_userspace_io. This does not
5439 * handle watchpoints yet, those would be handled in
5440 * the emulate_ops.
5441 */
5442 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5443 return r;
5444
9d74191a
TY		 5445 ctxt->interruptibility = 0;
5446 ctxt->have_exception = false;
e0ad0b47 5447 ctxt->exception.vector = -1;
9d74191a 5448 ctxt->perm_ok = false;
bbd9b64e 5449
b51e974f 5450 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5451
9d74191a 5452 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5453
e46479f8 5454 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5455 ++vcpu->stat.insn_emulation;
1d2887e2 5456 if (r != EMULATION_OK) {
4005996e
AK		 5457 if (emulation_type & EMULTYPE_TRAP_UD)
5458 return EMULATE_FAIL;
991eebf9
GN		 5459 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5460 emulation_type))
bbd9b64e 5461 return EMULATE_DONE;
6d77dbfc
GN		 5462 if (emulation_type & EMULTYPE_SKIP)
5463 return EMULATE_FAIL;
5464 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5465 }
5466 }
5467
ba8afb6b 5468 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5469 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5470 if (ctxt->eflags & X86_EFLAGS_RF)
5471 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5472 return EMULATE_DONE;
5473 }
5474
1cb3f3ae
XG		 5475 if (retry_instruction(ctxt, cr2, emulation_type))
5476 return EMULATE_DONE;
5477
7ae441ea 5478 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5479 changes registers values during IO operation */
7ae441ea
GN		 5480 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5481 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5482 emulator_invalidate_register_cache(ctxt);
7ae441ea 5483 }
4d2179e1 5484
5cd21917 5485restart:
9d74191a 5486 r = x86_emulate_insn(ctxt);
bbd9b64e 5487
775fde86
JR		 5488 if (r == EMULATION_INTERCEPTED)
5489 return EMULATE_DONE;
5490
d2ddd1c4 5491 if (r == EMULATION_FAILED) {
991eebf9
GN		 5492 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5493 emulation_type))
c3cd7ffa
GN		 5494 return EMULATE_DONE;
5495
6d77dbfc 5496 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5497 }
5498
9d74191a 5499 if (ctxt->have_exception) {
d2ddd1c4 5500 r = EMULATE_DONE;
ef54bcfe
PB		 5501 if (inject_emulated_exception(vcpu))
5502 return r;
d2ddd1c4 5503 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5504 if (!vcpu->arch.pio.in) {
5505 /* FIXME: return into emulator if single-stepping. */
3457e419 5506 vcpu->arch.pio.count = 0;
0912c977 5507 } else {
7ae441ea 5508 writeback = false;
716d51ab
GN		 5509 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5510 }
ac0a48c3 5511 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5512 } else if (vcpu->mmio_needed) {
5513 if (!vcpu->mmio_is_write)
5514 writeback = false;
ac0a48c3 5515 r = EMULATE_USER_EXIT;
716d51ab 5516 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5517 } else if (r == EMULATION_RESTART)
5cd21917 5518 goto restart;
d2ddd1c4
GN		 5519 else
5520 r = EMULATE_DONE;
f850e2e6 5521
7ae441ea 5522 if (writeback) {
6addfc42 5523 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5524 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5525 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5526 if (vcpu->arch.hflags != ctxt->emul_flags)
5527 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5528 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5529 if (r == EMULATE_DONE)
6addfc42 5530 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5531 if (!ctxt->have_exception ||
5532 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5533 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5534
5535 /*
5536 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5537 * do nothing, and it will be requested again as soon as
5538 * the shadow expires. But we still need to check here,
5539 * because POPF has no interrupt shadow.
5540 */
5541 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5542 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5543 } else
5544 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5545
5546 return r;
de7d789a 5547}
51d8b661 5548EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5549
cf8f70bf 5550int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5551{
cf8f70bf 5552 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5553 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5554 size, port, &val, 1);
cf8f70bf 5555 /* do not return to emulator after return from userspace */
7972995b 5556 vcpu->arch.pio.count = 0;
de7d789a
CO		 5557 return ret;
5558}
cf8f70bf 5559EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5560
8cfdc000
ZA		 5561static void tsc_bad(void *info)
5562{
0a3aee0d 5563 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5564}
5565
5566static void tsc_khz_changed(void *data)
c8076604 5567{
8cfdc000
ZA		 5568 struct cpufreq_freqs *freq = data;
5569 unsigned long khz = 0;
5570
5571 if (data)
5572 khz = freq->new;
5573 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5574 khz = cpufreq_quick_get(raw_smp_processor_id());
5575 if (!khz)
5576 khz = tsc_khz;
0a3aee0d 5577 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5578}
5579
c8076604
GH		 5580static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5581 void *data)
5582{
5583 struct cpufreq_freqs *freq = data;
5584 struct kvm *kvm;
5585 struct kvm_vcpu *vcpu;
5586 int i, send_ipi = 0;
5587
8cfdc000
ZA		 5588 /*
5589 * We allow guests to temporarily run on slowing clocks,
5590 * provided we notify them after, or to run on accelerating
5591 * clocks, provided we notify them before. Thus time never
5592 * goes backwards.
5593 *
5594 * However, we have a problem. We can't atomically update
5595 * the frequency of a given CPU from this function; it is
5596 * merely a notifier, which can be called from any CPU.
5597 * Changing the TSC frequency at arbitrary points in time
5598 * requires a recomputation of local variables related to
5599 * the TSC for each VCPU. We must flag these local variables
5600 * to be updated and be sure the update takes place with the
5601 * new frequency before any guests proceed.
5602 *
5603 * Unfortunately, the combination of hotplug CPU and frequency
5604 * change creates an intractable locking scenario; the order
5605 * of when these callouts happen is undefined with respect to
5606 * CPU hotplug, and they can race with each other. As such,
5607 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5608 * undefined; you can actually have a CPU frequency change take
5609 * place in between the computation of X and the setting of the
5610 * variable. To protect against this problem, all updates of
5611 * the per_cpu tsc_khz variable are done in an interrupt
5612 * protected IPI, and all callers wishing to update the value
5613 * must wait for a synchronous IPI to complete (which is trivial
5614 * if the caller is on the CPU already). This establishes the
5615 * necessary total order on variable updates.
5616 *
5617 * Note that because a guest time update may take place
5618 * anytime after the setting of the VCPU's request bit, the
5619 * correct TSC value must be set before the request. However,
5620 * to ensure the update actually makes it to any guest which
5621 * starts running in hardware virtualization between the set
5622 * and the acquisition of the spinlock, we must also ping the
5623 * CPU after setting the request bit.
5624 *
5625 */
5626
c8076604
GH		 5627 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5628 return 0;
5629 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5630 return 0;
8cfdc000
ZA		 5631
5632 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5633
2f303b74 5634 spin_lock(&kvm_lock);
c8076604 5635 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5636 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5637 if (vcpu->cpu != freq->cpu)
5638 continue;
c285545f 5639 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5640 if (vcpu->cpu != smp_processor_id())
8cfdc000 5641 send_ipi = 1;
c8076604
GH		 5642 }
5643 }
2f303b74 5644 spin_unlock(&kvm_lock);
c8076604
GH		 5645
5646 if (freq->old < freq->new && send_ipi) {
5647 /*
5648 * We upscale the frequency. Must make the guest
5649 * doesn't see old kvmclock values while running with
5650 * the new frequency, otherwise we risk the guest sees
5651 * time go backwards.
5652 *
5653 * In case we update the frequency for another cpu
5654 * (which might be in guest context) send an interrupt
5655 * to kick the cpu out of guest context. Next time
5656 * guest context is entered kvmclock will be updated,
5657 * so the guest will not see stale values.
5658 */
8cfdc000 5659 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5660 }
5661 return 0;
5662}
5663
5664static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5665 .notifier_call = kvmclock_cpufreq_notifier
5666};
5667
5668static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5669 unsigned long action, void *hcpu)
5670{
5671 unsigned int cpu = (unsigned long)hcpu;
5672
5673 switch (action) {
5674 case CPU_ONLINE:
5675 case CPU_DOWN_FAILED:
5676 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5677 break;
5678 case CPU_DOWN_PREPARE:
5679 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5680 break;
5681 }
5682 return NOTIFY_OK;
5683}
5684
5685static struct notifier_block kvmclock_cpu_notifier_block = {
5686 .notifier_call = kvmclock_cpu_notifier,
5687 .priority = -INT_MAX
c8076604
GH		 5688};
5689
b820cc0c
ZA		 5690static void kvm_timer_init(void)
5691{
5692 int cpu;
5693
c285545f 5694 max_tsc_khz = tsc_khz;
460dd42e
SB		 5695
5696 cpu_notifier_register_begin();
b820cc0c 5697 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5698#ifdef CONFIG_CPU_FREQ
5699 struct cpufreq_policy policy;
5700 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5701 cpu = get_cpu();
5702 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5703 if (policy.cpuinfo.max_freq)
5704 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5705 put_cpu();
c285545f 5706#endif
b820cc0c
ZA		 5707 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5708 CPUFREQ_TRANSITION_NOTIFIER);
5709 }
c285545f 5710 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5711 for_each_online_cpu(cpu)
5712 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5713
5714 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5715 cpu_notifier_register_done();
5716
b820cc0c
ZA		 5717}
5718
ff9d07a0
ZY		 5719static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5720
f5132b01 5721int kvm_is_in_guest(void)
ff9d07a0 5722{
086c9855 5723 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5724}
5725
5726static int kvm_is_user_mode(void)
5727{
5728 int user_mode = 3;
dcf46b94 5729
086c9855
AS		 5730 if (__this_cpu_read(current_vcpu))
5731 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5732
ff9d07a0
ZY		 5733 return user_mode != 0;
5734}
5735
5736static unsigned long kvm_get_guest_ip(void)
5737{
5738 unsigned long ip = 0;
dcf46b94 5739
086c9855
AS		 5740 if (__this_cpu_read(current_vcpu))
5741 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5742
ff9d07a0
ZY		 5743 return ip;
5744}
5745
5746static struct perf_guest_info_callbacks kvm_guest_cbs = {
5747 .is_in_guest = kvm_is_in_guest,
5748 .is_user_mode = kvm_is_user_mode,
5749 .get_guest_ip = kvm_get_guest_ip,
5750};
5751
5752void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5753{
086c9855 5754 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5755}
5756EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5757
5758void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5759{
086c9855 5760 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5761}
5762EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5763
ce88decf
XG		 5764static void kvm_set_mmio_spte_mask(void)
5765{
5766 u64 mask;
5767 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5768
5769 /*
5770 * Set the reserved bits and the present bit of an paging-structure
5771 * entry to generate page fault with PFER.RSV = 1.
5772 */
885032b9 5773 /* Mask the reserved physical address bits. */
d1431483 5774 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5775
5776 /* Bit 62 is always reserved for 32bit host. */
5777 mask |= 0x3ull << 62;
5778
5779 /* Set the present bit. */
ce88decf
XG		 5780 mask |= 1ull;
5781
5782#ifdef CONFIG_X86_64
5783 /*
5784 * If reserved bit is not supported, clear the present bit to disable
5785 * mmio page fault.
5786 */
5787 if (maxphyaddr == 52)
5788 mask &= ~1ull;
5789#endif
5790
5791 kvm_mmu_set_mmio_spte_mask(mask);
5792}
5793
16e8d74d
MT		 5794#ifdef CONFIG_X86_64
5795static void pvclock_gtod_update_fn(struct work_struct *work)
5796{
d828199e
MT		 5797 struct kvm *kvm;
5798
5799 struct kvm_vcpu *vcpu;
5800 int i;
5801
2f303b74 5802 spin_lock(&kvm_lock);
d828199e
MT		 5803 list_for_each_entry(kvm, &vm_list, vm_list)
5804 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5805 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5806 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5807 spin_unlock(&kvm_lock);
16e8d74d
MT		 5808}
5809
5810static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5811
5812/*
5813 * Notification about pvclock gtod data update.
5814 */
5815static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5816 void *priv)
5817{
5818 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5819 struct timekeeper *tk = priv;
5820
5821 update_pvclock_gtod(tk);
5822
5823 /* disable master clock if host does not trust, or does not
5824 * use, TSC clocksource
5825 */
5826 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5827 atomic_read(&kvm_guest_has_master_clock) != 0)
5828 queue_work(system_long_wq, &pvclock_gtod_work);
5829
5830 return 0;
5831}
5832
5833static struct notifier_block pvclock_gtod_notifier = {
5834 .notifier_call = pvclock_gtod_notify,
5835};
5836#endif
5837
f8c16bba 5838int kvm_arch_init(void *opaque)
043405e1 5839{
b820cc0c 5840 int r;
6b61edf7 5841 struct kvm_x86_ops *ops = opaque;
f8c16bba 5842
f8c16bba
ZX		 5843 if (kvm_x86_ops) {
5844 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5845 r = -EEXIST;
5846 goto out;
f8c16bba
ZX		 5847 }
5848
5849 if (!ops->cpu_has_kvm_support()) {
5850 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5851 r = -EOPNOTSUPP;
5852 goto out;
f8c16bba
ZX		 5853 }
5854 if (ops->disabled_by_bios()) {
5855 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5856 r = -EOPNOTSUPP;
5857 goto out;
f8c16bba
ZX		 5858 }
5859
013f6a5d
MT		 5860 r = -ENOMEM;
5861 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5862 if (!shared_msrs) {
5863 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5864 goto out;
5865 }
5866
97db56ce
AK		 5867 r = kvm_mmu_module_init();
5868 if (r)
013f6a5d 5869 goto out_free_percpu;
97db56ce 5870
ce88decf 5871 kvm_set_mmio_spte_mask();
97db56ce 5872
f8c16bba 5873 kvm_x86_ops = ops;
920c8377 5874
7b52345e 5875 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5876 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5877
b820cc0c 5878 kvm_timer_init();
c8076604 5879
ff9d07a0
ZY		 5880 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5881
d366bf7e 5882 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5883 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5884
c5cc421b 5885 kvm_lapic_init();
16e8d74d
MT		 5886#ifdef CONFIG_X86_64
5887 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5888#endif
5889
f8c16bba 5890 return 0;
56c6d28a 5891
013f6a5d
MT		 5892out_free_percpu:
5893 free_percpu(shared_msrs);
56c6d28a 5894out:
56c6d28a 5895 return r;
043405e1 5896}
8776e519 5897
f8c16bba
ZX		 5898void kvm_arch_exit(void)
5899{
ff9d07a0
ZY		 5900 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5901
888d256e
JK		 5902 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5903 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5904 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5905 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5906#ifdef CONFIG_X86_64
5907 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5908#endif
f8c16bba 5909 kvm_x86_ops = NULL;
56c6d28a 5910 kvm_mmu_module_exit();
013f6a5d 5911 free_percpu(shared_msrs);
56c6d28a 5912}
f8c16bba 5913
5cb56059 5914int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5915{
5916 ++vcpu->stat.halt_exits;
35754c98 5917 if (lapic_in_kernel(vcpu)) {
a4535290 5918 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5919 return 1;
5920 } else {
5921 vcpu->run->exit_reason = KVM_EXIT_HLT;
5922 return 0;
5923 }
5924}
5cb56059
JS		 5925EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5926
5927int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5928{
5929 kvm_x86_ops->skip_emulated_instruction(vcpu);
5930 return kvm_vcpu_halt(vcpu);
5931}
8776e519
HB		 5932EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5933
6aef266c
SV		 5934/*
5935 * kvm_pv_kick_cpu_op: Kick a vcpu.
5936 *
5937 * @apicid - apicid of vcpu to be kicked.
5938 */
5939static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5940{
24d2166b 5941 struct kvm_lapic_irq lapic_irq;
6aef266c 5942
24d2166b
R		 5943 lapic_irq.shorthand = 0;
5944 lapic_irq.dest_mode = 0;
5945 lapic_irq.dest_id = apicid;
93bbf0b8 5946 lapic_irq.msi_redir_hint = false;
6aef266c 5947
24d2166b 5948 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5949 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5950}
5951
d62caabb
AS		 5952void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5953{
5954 vcpu->arch.apicv_active = false;
5955 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5956}
5957
8776e519
HB		 5958int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5959{
5960 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5961 int op_64_bit, r = 1;
8776e519 5962
5cb56059
JS		 5963 kvm_x86_ops->skip_emulated_instruction(vcpu);
5964
55cd8e5a
GN		 5965 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5966 return kvm_hv_hypercall(vcpu);
5967
5fdbf976
MT		 5968 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5969 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5970 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5971 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5972 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5973
229456fc 5974 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5975
a449c7aa
NA		 5976 op_64_bit = is_64_bit_mode(vcpu);
5977 if (!op_64_bit) {
8776e519
HB		 5978 nr &= 0xFFFFFFFF;
5979 a0 &= 0xFFFFFFFF;
5980 a1 &= 0xFFFFFFFF;
5981 a2 &= 0xFFFFFFFF;
5982 a3 &= 0xFFFFFFFF;
5983 }
5984
07708c4a
JK		 5985 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5986 ret = -KVM_EPERM;
5987 goto out;
5988 }
5989
8776e519 5990 switch (nr) {
b93463aa
AK		 5991 case KVM_HC_VAPIC_POLL_IRQ:
5992 ret = 0;
5993 break;
6aef266c
SV		 5994 case KVM_HC_KICK_CPU:
5995 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5996 ret = 0;
5997 break;
8776e519
HB		 5998 default:
5999 ret = -KVM_ENOSYS;
6000 break;
6001 }
07708c4a 6002out:
a449c7aa
NA		 6003 if (!op_64_bit)
6004 ret = (u32)ret;
5fdbf976 6005 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6006 ++vcpu->stat.hypercalls;
2f333bcb 6007 return r;
8776e519
HB		 6008}
6009EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6010
b6785def 6011static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6012{
d6aa1000 6013 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6014 char instruction[3];
5fdbf976 6015 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6016
8776e519 6017 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6018
9d74191a 6019 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6020}
6021
851ba692 6022static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6023{
782d422b
MG		 6024 return vcpu->run->request_interrupt_window &&
6025 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6026}
6027
851ba692 6028static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6029{
851ba692
AK		 6030 struct kvm_run *kvm_run = vcpu->run;
6031
91586a3b 6032 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6033 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6034 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6035 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6036 kvm_run->ready_for_interrupt_injection =
6037 pic_in_kernel(vcpu->kvm) ||
782d422b 6038 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6039}
6040
95ba8273
GN		 6041static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6042{
6043 int max_irr, tpr;
6044
6045 if (!kvm_x86_ops->update_cr8_intercept)
6046 return;
6047
bce87cce 6048 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6049 return;
6050
d62caabb
AS		 6051 if (vcpu->arch.apicv_active)
6052 return;
6053
8db3baa2
GN		 6054 if (!vcpu->arch.apic->vapic_addr)
6055 max_irr = kvm_lapic_find_highest_irr(vcpu);
6056 else
6057 max_irr = -1;
95ba8273
GN		 6058
6059 if (max_irr != -1)
6060 max_irr >>= 4;
6061
6062 tpr = kvm_lapic_get_cr8(vcpu);
6063
6064 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6065}
6066
b6b8a145 6067static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6068{
b6b8a145
JK		 6069 int r;
6070
95ba8273 6071 /* try to reinject previous events if any */
b59bb7bd 6072 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6073 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6074 vcpu->arch.exception.has_error_code,
6075 vcpu->arch.exception.error_code);
d6e8c854
NA		 6076
6077 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6078 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6079 X86_EFLAGS_RF);
6080
6bdf0662
NA		 6081 if (vcpu->arch.exception.nr == DB_VECTOR &&
6082 (vcpu->arch.dr7 & DR7_GD)) {
6083 vcpu->arch.dr7 &= ~DR7_GD;
6084 kvm_update_dr7(vcpu);
6085 }
6086
b59bb7bd
GN		 6087 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6088 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6089 vcpu->arch.exception.error_code,
6090 vcpu->arch.exception.reinject);
b6b8a145 6091 return 0;
b59bb7bd
GN		 6092 }
6093
95ba8273
GN		 6094 if (vcpu->arch.nmi_injected) {
6095 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6096 return 0;
95ba8273
GN		 6097 }
6098
6099 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6100 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6101 return 0;
6102 }
6103
6104 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6105 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6106 if (r != 0)
6107 return r;
95ba8273
GN		 6108 }
6109
6110 /* try to inject new event if pending */
321c5658
YS		 6111 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6112 --vcpu->arch.nmi_pending;
6113 vcpu->arch.nmi_injected = true;
6114 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6115 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6116 /*
6117 * Because interrupts can be injected asynchronously, we are
6118 * calling check_nested_events again here to avoid a race condition.
6119 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6120 * proposal and current concerns. Perhaps we should be setting
6121 * KVM_REQ_EVENT only on certain events and not unconditionally?
6122 */
6123 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6124 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6125 if (r != 0)
6126 return r;
6127 }
95ba8273 6128 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6129 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6130 false);
6131 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6132 }
6133 }
b6b8a145 6134 return 0;
95ba8273
GN		 6135}
6136
7460fb4a
AK		 6137static void process_nmi(struct kvm_vcpu *vcpu)
6138{
6139 unsigned limit = 2;
6140
6141 /*
6142 * x86 is limited to one NMI running, and one NMI pending after it.
6143 * If an NMI is already in progress, limit further NMIs to just one.
6144 * Otherwise, allow two (and we'll inject the first one immediately).
6145 */
6146 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6147 limit = 1;
6148
6149 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6150 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6151 kvm_make_request(KVM_REQ_EVENT, vcpu);
6152}
6153
660a5d51
PB		 6154#define put_smstate(type, buf, offset, val) \
6155 *(type *)((buf) + (offset) - 0x7e00) = val
6156
6157static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6158{
6159 u32 flags = 0;
6160 flags |= seg->g << 23;
6161 flags |= seg->db << 22;
6162 flags |= seg->l << 21;
6163 flags |= seg->avl << 20;
6164 flags |= seg->present << 15;
6165 flags |= seg->dpl << 13;
6166 flags |= seg->s << 12;
6167 flags |= seg->type << 8;
6168 return flags;
6169}
6170
6171static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6172{
6173 struct kvm_segment seg;
6174 int offset;
6175
6176 kvm_get_segment(vcpu, &seg, n);
6177 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6178
6179 if (n < 3)
6180 offset = 0x7f84 + n * 12;
6181 else
6182 offset = 0x7f2c + (n - 3) * 12;
6183
6184 put_smstate(u32, buf, offset + 8, seg.base);
6185 put_smstate(u32, buf, offset + 4, seg.limit);
6186 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6187}
6188
efbb288a 6189#ifdef CONFIG_X86_64
660a5d51
PB		 6190static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6191{
6192 struct kvm_segment seg;
6193 int offset;
6194 u16 flags;
6195
6196 kvm_get_segment(vcpu, &seg, n);
6197 offset = 0x7e00 + n * 16;
6198
6199 flags = process_smi_get_segment_flags(&seg) >> 8;
6200 put_smstate(u16, buf, offset, seg.selector);
6201 put_smstate(u16, buf, offset + 2, flags);
6202 put_smstate(u32, buf, offset + 4, seg.limit);
6203 put_smstate(u64, buf, offset + 8, seg.base);
6204}
efbb288a 6205#endif
660a5d51
PB		 6206
6207static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6208{
6209 struct desc_ptr dt;
6210 struct kvm_segment seg;
6211 unsigned long val;
6212 int i;
6213
6214 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6215 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6216 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6217 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6218
6219 for (i = 0; i < 8; i++)
6220 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6221
6222 kvm_get_dr(vcpu, 6, &val);
6223 put_smstate(u32, buf, 0x7fcc, (u32)val);
6224 kvm_get_dr(vcpu, 7, &val);
6225 put_smstate(u32, buf, 0x7fc8, (u32)val);
6226
6227 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6228 put_smstate(u32, buf, 0x7fc4, seg.selector);
6229 put_smstate(u32, buf, 0x7f64, seg.base);
6230 put_smstate(u32, buf, 0x7f60, seg.limit);
6231 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6232
6233 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6234 put_smstate(u32, buf, 0x7fc0, seg.selector);
6235 put_smstate(u32, buf, 0x7f80, seg.base);
6236 put_smstate(u32, buf, 0x7f7c, seg.limit);
6237 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6238
6239 kvm_x86_ops->get_gdt(vcpu, &dt);
6240 put_smstate(u32, buf, 0x7f74, dt.address);
6241 put_smstate(u32, buf, 0x7f70, dt.size);
6242
6243 kvm_x86_ops->get_idt(vcpu, &dt);
6244 put_smstate(u32, buf, 0x7f58, dt.address);
6245 put_smstate(u32, buf, 0x7f54, dt.size);
6246
6247 for (i = 0; i < 6; i++)
6248 process_smi_save_seg_32(vcpu, buf, i);
6249
6250 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6251
6252 /* revision id */
6253 put_smstate(u32, buf, 0x7efc, 0x00020000);
6254 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6255}
6256
6257static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6258{
6259#ifdef CONFIG_X86_64
6260 struct desc_ptr dt;
6261 struct kvm_segment seg;
6262 unsigned long val;
6263 int i;
6264
6265 for (i = 0; i < 16; i++)
6266 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6267
6268 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6269 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6270
6271 kvm_get_dr(vcpu, 6, &val);
6272 put_smstate(u64, buf, 0x7f68, val);
6273 kvm_get_dr(vcpu, 7, &val);
6274 put_smstate(u64, buf, 0x7f60, val);
6275
6276 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6277 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6278 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6279
6280 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6281
6282 /* revision id */
6283 put_smstate(u32, buf, 0x7efc, 0x00020064);
6284
6285 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6286
6287 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6288 put_smstate(u16, buf, 0x7e90, seg.selector);
6289 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6290 put_smstate(u32, buf, 0x7e94, seg.limit);
6291 put_smstate(u64, buf, 0x7e98, seg.base);
6292
6293 kvm_x86_ops->get_idt(vcpu, &dt);
6294 put_smstate(u32, buf, 0x7e84, dt.size);
6295 put_smstate(u64, buf, 0x7e88, dt.address);
6296
6297 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6298 put_smstate(u16, buf, 0x7e70, seg.selector);
6299 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6300 put_smstate(u32, buf, 0x7e74, seg.limit);
6301 put_smstate(u64, buf, 0x7e78, seg.base);
6302
6303 kvm_x86_ops->get_gdt(vcpu, &dt);
6304 put_smstate(u32, buf, 0x7e64, dt.size);
6305 put_smstate(u64, buf, 0x7e68, dt.address);
6306
6307 for (i = 0; i < 6; i++)
6308 process_smi_save_seg_64(vcpu, buf, i);
6309#else
6310 WARN_ON_ONCE(1);
6311#endif
6312}
6313
64d60670
PB		 6314static void process_smi(struct kvm_vcpu *vcpu)
6315{
660a5d51 6316 struct kvm_segment cs, ds;
18c3626e 6317 struct desc_ptr dt;
660a5d51
PB		 6318 char buf[512];
6319 u32 cr0;
6320
64d60670
PB		 6321 if (is_smm(vcpu)) {
6322 vcpu->arch.smi_pending = true;
6323 return;
6324 }
6325
660a5d51
PB		 6326 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6327 vcpu->arch.hflags |= HF_SMM_MASK;
6328 memset(buf, 0, 512);
6329 if (guest_cpuid_has_longmode(vcpu))
6330 process_smi_save_state_64(vcpu, buf);
6331 else
6332 process_smi_save_state_32(vcpu, buf);
6333
54bf36aa 6334 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6335
6336 if (kvm_x86_ops->get_nmi_mask(vcpu))
6337 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6338 else
6339 kvm_x86_ops->set_nmi_mask(vcpu, true);
6340
6341 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6342 kvm_rip_write(vcpu, 0x8000);
6343
6344 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6345 kvm_x86_ops->set_cr0(vcpu, cr0);
6346 vcpu->arch.cr0 = cr0;
6347
6348 kvm_x86_ops->set_cr4(vcpu, 0);
6349
18c3626e
PB		 6350 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6351 dt.address = dt.size = 0;
6352 kvm_x86_ops->set_idt(vcpu, &dt);
6353
660a5d51
PB		 6354 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6355
6356 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6357 cs.base = vcpu->arch.smbase;
6358
6359 ds.selector = 0;
6360 ds.base = 0;
6361
6362 cs.limit = ds.limit = 0xffffffff;
6363 cs.type = ds.type = 0x3;
6364 cs.dpl = ds.dpl = 0;
6365 cs.db = ds.db = 0;
6366 cs.s = ds.s = 1;
6367 cs.l = ds.l = 0;
6368 cs.g = ds.g = 1;
6369 cs.avl = ds.avl = 0;
6370 cs.present = ds.present = 1;
6371 cs.unusable = ds.unusable = 0;
6372 cs.padding = ds.padding = 0;
6373
6374 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6375 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6376 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6377 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6378 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6379 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6380
6381 if (guest_cpuid_has_longmode(vcpu))
6382 kvm_x86_ops->set_efer(vcpu, 0);
6383
6384 kvm_update_cpuid(vcpu);
6385 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6386}
6387
2860c4b1
PB		 6388void kvm_make_scan_ioapic_request(struct kvm *kvm)
6389{
6390 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6391}
6392
3d81bc7e 6393static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6394{
5c919412
AS		 6395 u64 eoi_exit_bitmap[4];
6396
3d81bc7e
YZ		 6397 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6398 return;
c7c9c56c 6399
6308630b 6400 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6401
b053b2ae 6402 if (irqchip_split(vcpu->kvm))
6308630b 6403 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6404 else {
d62caabb
AS		 6405 if (vcpu->arch.apicv_active)
6406 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6407 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6408 }
5c919412
AS		 6409 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6410 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6411 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6412}
6413
a70656b6
RK		 6414static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6415{
6416 ++vcpu->stat.tlb_flush;
6417 kvm_x86_ops->tlb_flush(vcpu);
6418}
6419
4256f43f
TC		 6420void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6421{
c24ae0dc
TC		 6422 struct page *page = NULL;
6423
35754c98 6424 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6425 return;
6426
4256f43f
TC		 6427 if (!kvm_x86_ops->set_apic_access_page_addr)
6428 return;
6429
c24ae0dc 6430 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6431 if (is_error_page(page))
6432 return;
c24ae0dc
TC		 6433 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6434
6435 /*
6436 * Do not pin apic access page in memory, the MMU notifier
6437 * will call us again if it is migrated or swapped out.
6438 */
6439 put_page(page);
4256f43f
TC		 6440}
6441EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6442
fe71557a
TC		 6443void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6444 unsigned long address)
6445{
c24ae0dc
TC		 6446 /*
6447 * The physical address of apic access page is stored in the VMCS.
6448 * Update it when it becomes invalid.
6449 */
6450 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6451 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6452}
6453
9357d939 6454/*
362c698f 6455 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6456 * exiting to the userspace. Otherwise, the value will be returned to the
6457 * userspace.
6458 */
851ba692 6459static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6460{
6461 int r;
62a193ed
MG		 6462 bool req_int_win =
6463 dm_request_for_irq_injection(vcpu) &&
6464 kvm_cpu_accept_dm_intr(vcpu);
6465
730dca42 6466 bool req_immediate_exit = false;
b6c7a5dc 6467
3e007509 6468 if (vcpu->requests) {
a8eeb04a 6469 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6470 kvm_mmu_unload(vcpu);
a8eeb04a 6471 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6472 __kvm_migrate_timers(vcpu);
d828199e
MT		 6473 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6474 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6475 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6476 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6477 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6478 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6479 if (unlikely(r))
6480 goto out;
6481 }
a8eeb04a 6482 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6483 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6484 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6485 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6486 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6487 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6488 r = 0;
6489 goto out;
6490 }
a8eeb04a 6491 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6492 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6493 r = 0;
6494 goto out;
6495 }
a8eeb04a 6496 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6497 vcpu->fpu_active = 0;
6498 kvm_x86_ops->fpu_deactivate(vcpu);
6499 }
af585b92
GN		 6500 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6501 /* Page is swapped out. Do synthetic halt */
6502 vcpu->arch.apf.halted = true;
6503 r = 1;
6504 goto out;
6505 }
c9aaa895
GC		 6506 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6507 record_steal_time(vcpu);
64d60670
PB		 6508 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6509 process_smi(vcpu);
7460fb4a
AK		 6510 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6511 process_nmi(vcpu);
f5132b01 6512 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6513 kvm_pmu_handle_event(vcpu);
f5132b01 6514 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6515 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6516 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6517 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6518 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6519 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6520 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6521 vcpu->run->eoi.vector =
6522 vcpu->arch.pending_ioapic_eoi;
6523 r = 0;
6524 goto out;
6525 }
6526 }
3d81bc7e
YZ		 6527 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6528 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6529 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6530 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6531 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6532 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6533 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6534 r = 0;
6535 goto out;
6536 }
e516cebb
AS		 6537 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6538 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6539 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6540 r = 0;
6541 goto out;
6542 }
db397571
AS		 6543 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6544 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6545 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6546 r = 0;
6547 goto out;
6548 }
f3b138c5
AS		 6549
6550 /*
6551 * KVM_REQ_HV_STIMER has to be processed after
6552 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6553 * depend on the guest clock being up-to-date
6554 */
1f4b34f8
AS		 6555 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6556 kvm_hv_process_stimers(vcpu);
2f52d58c 6557 }
b93463aa 6558
bf9f6ac8
FW		 6559 /*
6560 * KVM_REQ_EVENT is not set when posted interrupts are set by
6561 * VT-d hardware, so we have to update RVI unconditionally.
6562 */
6563 if (kvm_lapic_enabled(vcpu)) {
6564 /*
6565 * Update architecture specific hints for APIC
6566 * virtual interrupt delivery.
6567 */
d62caabb 6568 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6569 kvm_x86_ops->hwapic_irr_update(vcpu,
6570 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6571 }
b93463aa 6572
b463a6f7 6573 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6574 kvm_apic_accept_events(vcpu);
6575 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6576 r = 1;
6577 goto out;
6578 }
6579
b6b8a145
JK		 6580 if (inject_pending_event(vcpu, req_int_win) != 0)
6581 req_immediate_exit = true;
b463a6f7 6582 /* enable NMI/IRQ window open exits if needed */
321c5658
YS		 6583 else {
6584 if (vcpu->arch.nmi_pending)
6585 kvm_x86_ops->enable_nmi_window(vcpu);
6586 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6587 kvm_x86_ops->enable_irq_window(vcpu);
6588 }
b463a6f7
AK		 6589
6590 if (kvm_lapic_enabled(vcpu)) {
6591 update_cr8_intercept(vcpu);
6592 kvm_lapic_sync_to_vapic(vcpu);
6593 }
6594 }
6595
d8368af8
AK		 6596 r = kvm_mmu_reload(vcpu);
6597 if (unlikely(r)) {
d905c069 6598 goto cancel_injection;
d8368af8
AK		 6599 }
6600
b6c7a5dc
HB		 6601 preempt_disable();
6602
6603 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6604 if (vcpu->fpu_active)
6605 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6606 vcpu->mode = IN_GUEST_MODE;
6607
01b71917
MT		 6608 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6609
0f127d12
LT		 6610 /*
6611 * We should set ->mode before check ->requests,
6612 * Please see the comment in kvm_make_all_cpus_request.
6613 * This also orders the write to mode from any reads
6614 * to the page tables done while the VCPU is running.
6615 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6616 */
01b71917 6617 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6618
d94e1dc9 6619 local_irq_disable();
32f88400 6620
6b7e2d09 6621 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6622 || need_resched() || signal_pending(current)) {
6b7e2d09 6623 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6624 smp_wmb();
6c142801
AK		 6625 local_irq_enable();
6626 preempt_enable();
01b71917 6627 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6628 r = 1;
d905c069 6629 goto cancel_injection;
6c142801
AK		 6630 }
6631
fc5b7f3b
DM		 6632 kvm_load_guest_xcr0(vcpu);
6633
d6185f20
NHE		 6634 if (req_immediate_exit)
6635 smp_send_reschedule(vcpu->cpu);
6636
8b89fe1f
PB		 6637 trace_kvm_entry(vcpu->vcpu_id);
6638 wait_lapic_expire(vcpu);
ccf73aaf 6639 __kvm_guest_enter();
b6c7a5dc 6640
42dbaa5a 6641 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6642 set_debugreg(0, 7);
6643 set_debugreg(vcpu->arch.eff_db[0], 0);
6644 set_debugreg(vcpu->arch.eff_db[1], 1);
6645 set_debugreg(vcpu->arch.eff_db[2], 2);
6646 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6647 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6648 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6649 }
b6c7a5dc 6650
851ba692 6651 kvm_x86_ops->run(vcpu);
b6c7a5dc 6652
c77fb5fe
PB		 6653 /*
6654 * Do this here before restoring debug registers on the host. And
6655 * since we do this before handling the vmexit, a DR access vmexit
6656 * can (a) read the correct value of the debug registers, (b) set
6657 * KVM_DEBUGREG_WONT_EXIT again.
6658 */
6659 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6660 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6661 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6662 kvm_update_dr0123(vcpu);
6663 kvm_update_dr6(vcpu);
6664 kvm_update_dr7(vcpu);
6665 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6666 }
6667
24f1e32c
FW		 6668 /*
6669 * If the guest has used debug registers, at least dr7
6670 * will be disabled while returning to the host.
6671 * If we don't have active breakpoints in the host, we don't
6672 * care about the messed up debug address registers. But if
6673 * we have some of them active, restore the old state.
6674 */
59d8eb53 6675 if (hw_breakpoint_active())
24f1e32c 6676 hw_breakpoint_restore();
42dbaa5a 6677
4ba76538 6678 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6679
6b7e2d09 6680 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6681 smp_wmb();
a547c6db 6682
fc5b7f3b
DM		 6683 kvm_put_guest_xcr0(vcpu);
6684
a547c6db
YZ		 6685 /* Interrupt is enabled by handle_external_intr() */
6686 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6687
6688 ++vcpu->stat.exits;
6689
6690 /*
6691 * We must have an instruction between local_irq_enable() and
6692 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6693 * the interrupt shadow. The stat.exits increment will do nicely.
6694 * But we need to prevent reordering, hence this barrier():
6695 */
6696 barrier();
6697
6698 kvm_guest_exit();
6699
6700 preempt_enable();
6701
f656ce01 6702 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6703
b6c7a5dc
HB		 6704 /*
6705 * Profile KVM exit RIPs:
6706 */
6707 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6708 unsigned long rip = kvm_rip_read(vcpu);
6709 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6710 }
6711
cc578287
ZA		 6712 if (unlikely(vcpu->arch.tsc_always_catchup))
6713 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6714
5cfb1d5a
MT		 6715 if (vcpu->arch.apic_attention)
6716 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6717
851ba692 6718 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6719 return r;
6720
6721cancel_injection:
6722 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6723 if (unlikely(vcpu->arch.apic_attention))
6724 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6725out:
6726 return r;
6727}
b6c7a5dc 6728
362c698f
PB		 6729static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6730{
bf9f6ac8
FW		 6731 if (!kvm_arch_vcpu_runnable(vcpu) &&
6732 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6733 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6734 kvm_vcpu_block(vcpu);
6735 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6736
6737 if (kvm_x86_ops->post_block)
6738 kvm_x86_ops->post_block(vcpu);
6739
9c8fd1ba
PB		 6740 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6741 return 1;
6742 }
362c698f
PB		 6743
6744 kvm_apic_accept_events(vcpu);
6745 switch(vcpu->arch.mp_state) {
6746 case KVM_MP_STATE_HALTED:
6747 vcpu->arch.pv.pv_unhalted = false;
6748 vcpu->arch.mp_state =
6749 KVM_MP_STATE_RUNNABLE;
6750 case KVM_MP_STATE_RUNNABLE:
6751 vcpu->arch.apf.halted = false;
6752 break;
6753 case KVM_MP_STATE_INIT_RECEIVED:
6754 break;
6755 default:
6756 return -EINTR;
6757 break;
6758 }
6759 return 1;
6760}
09cec754 6761
5d9bc648
PB		 6762static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6763{
6764 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6765 !vcpu->arch.apf.halted);
6766}
6767
362c698f 6768static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6769{
6770 int r;
f656ce01 6771 struct kvm *kvm = vcpu->kvm;
d7690175 6772
f656ce01 6773 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6774
362c698f 6775 for (;;) {
58f800d5 6776 if (kvm_vcpu_running(vcpu)) {
851ba692 6777 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6778 } else {
362c698f 6779 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6780 }
6781
09cec754
GN		 6782 if (r <= 0)
6783 break;
6784
6785 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6786 if (kvm_cpu_has_pending_timer(vcpu))
6787 kvm_inject_pending_timer_irqs(vcpu);
6788
782d422b
MG		 6789 if (dm_request_for_irq_injection(vcpu) &&
6790 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6791 r = 0;
6792 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6793 ++vcpu->stat.request_irq_exits;
362c698f 6794 break;
09cec754 6795 }
af585b92
GN		 6796
6797 kvm_check_async_pf_completion(vcpu);
6798
09cec754
GN		 6799 if (signal_pending(current)) {
6800 r = -EINTR;
851ba692 6801 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6802 ++vcpu->stat.signal_exits;
362c698f 6803 break;
09cec754
GN		 6804 }
6805 if (need_resched()) {
f656ce01 6806 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6807 cond_resched();
f656ce01 6808 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6809 }
b6c7a5dc
HB		 6810 }
6811
f656ce01 6812 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6813
6814 return r;
6815}
6816
716d51ab
GN		 6817static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6818{
6819 int r;
6820 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6821 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6822 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6823 if (r != EMULATE_DONE)
6824 return 0;
6825 return 1;
6826}
6827
6828static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6829{
6830 BUG_ON(!vcpu->arch.pio.count);
6831
6832 return complete_emulated_io(vcpu);
6833}
6834
f78146b0
AK		 6835/*
6836 * Implements the following, as a state machine:
6837 *
6838 * read:
6839 * for each fragment
87da7e66
XG		 6840 * for each mmio piece in the fragment
6841 * write gpa, len
6842 * exit
6843 * copy data
f78146b0
AK		 6844 * execute insn
6845 *
6846 * write:
6847 * for each fragment
87da7e66
XG		 6848 * for each mmio piece in the fragment
6849 * write gpa, len
6850 * copy data
6851 * exit
f78146b0 6852 */
716d51ab 6853static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6854{
6855 struct kvm_run *run = vcpu->run;
f78146b0 6856 struct kvm_mmio_fragment *frag;
87da7e66 6857 unsigned len;
5287f194 6858
716d51ab 6859 BUG_ON(!vcpu->mmio_needed);
5287f194 6860
716d51ab 6861 /* Complete previous fragment */
87da7e66
XG		 6862 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6863 len = min(8u, frag->len);
716d51ab 6864 if (!vcpu->mmio_is_write)
87da7e66
XG		 6865 memcpy(frag->data, run->mmio.data, len);
6866
6867 if (frag->len <= 8) {
6868 /* Switch to the next fragment. */
6869 frag++;
6870 vcpu->mmio_cur_fragment++;
6871 } else {
6872 /* Go forward to the next mmio piece. */
6873 frag->data += len;
6874 frag->gpa += len;
6875 frag->len -= len;
6876 }
6877
a08d3b3b 6878 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6879 vcpu->mmio_needed = 0;
0912c977
PB		 6880
6881 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6882 if (vcpu->mmio_is_write)
716d51ab
GN		 6883 return 1;
6884 vcpu->mmio_read_completed = 1;
6885 return complete_emulated_io(vcpu);
6886 }
87da7e66 6887
716d51ab
GN		 6888 run->exit_reason = KVM_EXIT_MMIO;
6889 run->mmio.phys_addr = frag->gpa;
6890 if (vcpu->mmio_is_write)
87da7e66
XG		 6891 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6892 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6893 run->mmio.is_write = vcpu->mmio_is_write;
6894 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6895 return 0;
5287f194
AK		 6896}
6897
716d51ab 6898
b6c7a5dc
HB		 6899int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6900{
c5bedc68 6901 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6902 int r;
6903 sigset_t sigsaved;
6904
c4d72e2d 6905 fpu__activate_curr(fpu);
e5c30142 6906
ac9f6dc0
AK		 6907 if (vcpu->sigset_active)
6908 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6909
a4535290 6910 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6911 kvm_vcpu_block(vcpu);
66450a21 6912 kvm_apic_accept_events(vcpu);
d7690175 6913 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6914 r = -EAGAIN;
6915 goto out;
b6c7a5dc
HB		 6916 }
6917
b6c7a5dc 6918 /* re-sync apic's tpr */
35754c98 6919 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6920 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6921 r = -EINVAL;
6922 goto out;
6923 }
6924 }
b6c7a5dc 6925
716d51ab
GN		 6926 if (unlikely(vcpu->arch.complete_userspace_io)) {
6927 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6928 vcpu->arch.complete_userspace_io = NULL;
6929 r = cui(vcpu);
6930 if (r <= 0)
6931 goto out;
6932 } else
6933 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6934
362c698f 6935 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6936
6937out:
f1d86e46 6938 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6939 if (vcpu->sigset_active)
6940 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6941
b6c7a5dc
HB		 6942 return r;
6943}
6944
6945int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6946{
7ae441ea
GN		 6947 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6948 /*
6949 * We are here if userspace calls get_regs() in the middle of
6950 * instruction emulation. Registers state needs to be copied
4a969980 6951 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6952 * that usually, but some bad designed PV devices (vmware
6953 * backdoor interface) need this to work
6954 */
dd856efa 6955 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6956 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6957 }
5fdbf976
MT		 6958 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6959 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6960 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6961 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6962 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6963 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6964 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6965 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6966#ifdef CONFIG_X86_64
5fdbf976
MT		 6967 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6968 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6969 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6970 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6971 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6972 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6973 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6974 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6975#endif
6976
5fdbf976 6977 regs->rip = kvm_rip_read(vcpu);
91586a3b 6978 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6979
b6c7a5dc
HB		 6980 return 0;
6981}
6982
6983int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6984{
7ae441ea
GN		 6985 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6986 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6987
5fdbf976
MT		 6988 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6989 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6990 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6991 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6992 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6993 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6994 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6995 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6996#ifdef CONFIG_X86_64
5fdbf976
MT		 6997 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6998 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6999 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7000 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7001 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7002 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7003 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7004 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7005#endif
7006
5fdbf976 7007 kvm_rip_write(vcpu, regs->rip);
91586a3b 7008 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7009
b4f14abd
JK		 7010 vcpu->arch.exception.pending = false;
7011
3842d135
AK		 7012 kvm_make_request(KVM_REQ_EVENT, vcpu);
7013
b6c7a5dc
HB		 7014 return 0;
7015}
7016
b6c7a5dc
HB		 7017void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7018{
7019 struct kvm_segment cs;
7020
3e6e0aab 7021 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7022 *db = cs.db;
7023 *l = cs.l;
7024}
7025EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7026
7027int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7028 struct kvm_sregs *sregs)
7029{
89a27f4d 7030 struct desc_ptr dt;
b6c7a5dc 7031
3e6e0aab
GT		 7032 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7033 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7034 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7035 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7036 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7037 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7038
3e6e0aab
GT		 7039 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7040 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7041
7042 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7043 sregs->idt.limit = dt.size;
7044 sregs->idt.base = dt.address;
b6c7a5dc 7045 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7046 sregs->gdt.limit = dt.size;
7047 sregs->gdt.base = dt.address;
b6c7a5dc 7048
4d4ec087 7049 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7050 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7051 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7052 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7053 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7054 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7055 sregs->apic_base = kvm_get_apic_base(vcpu);
7056
923c61bb 7057 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7058
36752c9b 7059 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7060 set_bit(vcpu->arch.interrupt.nr,
7061 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7062
b6c7a5dc
HB		 7063 return 0;
7064}
7065
62d9f0db
MT		 7066int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7067 struct kvm_mp_state *mp_state)
7068{
66450a21 7069 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7070 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7071 vcpu->arch.pv.pv_unhalted)
7072 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7073 else
7074 mp_state->mp_state = vcpu->arch.mp_state;
7075
62d9f0db
MT		 7076 return 0;
7077}
7078
7079int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7080 struct kvm_mp_state *mp_state)
7081{
bce87cce 7082 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7083 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7084 return -EINVAL;
7085
7086 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7087 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7088 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7089 } else
7090 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7091 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7092 return 0;
7093}
7094
7f3d35fd
KW		 7095int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7096 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7097{
9d74191a 7098 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7099 int ret;
e01c2426 7100
8ec4722d 7101 init_emulate_ctxt(vcpu);
c697518a 7102
7f3d35fd 7103 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7104 has_error_code, error_code);
c697518a 7105
c697518a 7106 if (ret)
19d04437 7107 return EMULATE_FAIL;
37817f29 7108
9d74191a
TY		 7109 kvm_rip_write(vcpu, ctxt->eip);
7110 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7111 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7112 return EMULATE_DONE;
37817f29
IE		 7113}
7114EXPORT_SYMBOL_GPL(kvm_task_switch);
7115
b6c7a5dc
HB		 7116int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7117 struct kvm_sregs *sregs)
7118{
58cb628d 7119 struct msr_data apic_base_msr;
b6c7a5dc 7120 int mmu_reset_needed = 0;
63f42e02 7121 int pending_vec, max_bits, idx;
89a27f4d 7122 struct desc_ptr dt;
b6c7a5dc 7123
6d1068b3
PM		 7124 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7125 return -EINVAL;
7126
89a27f4d
GN		 7127 dt.size = sregs->idt.limit;
7128 dt.address = sregs->idt.base;
b6c7a5dc 7129 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7130 dt.size = sregs->gdt.limit;
7131 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7132 kvm_x86_ops->set_gdt(vcpu, &dt);
7133
ad312c7c 7134 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7135 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7136 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7137 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7138
2d3ad1f4 7139 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7140
f6801dff 7141 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7142 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7143 apic_base_msr.data = sregs->apic_base;
7144 apic_base_msr.host_initiated = true;
7145 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7146
4d4ec087 7147 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7148 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7149 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7150
fc78f519 7151 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7152 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7153 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7154 kvm_update_cpuid(vcpu);
63f42e02
XG		 7155
7156 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7157 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7158 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7159 mmu_reset_needed = 1;
7160 }
63f42e02 7161 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7162
7163 if (mmu_reset_needed)
7164 kvm_mmu_reset_context(vcpu);
7165
a50abc3b 7166 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7167 pending_vec = find_first_bit(
7168 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7169 if (pending_vec < max_bits) {
66fd3f7f 7170 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7171 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7172 }
7173
3e6e0aab
GT		 7174 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7175 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7176 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7177 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7178 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7179 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7180
3e6e0aab
GT		 7181 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7182 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7183
5f0269f5
ME		 7184 update_cr8_intercept(vcpu);
7185
9c3e4aab 7186 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7187 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7188 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7189 !is_protmode(vcpu))
9c3e4aab
MT		 7190 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7191
3842d135
AK		 7192 kvm_make_request(KVM_REQ_EVENT, vcpu);
7193
b6c7a5dc
HB		 7194 return 0;
7195}
7196
d0bfb940
JK		 7197int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7198 struct kvm_guest_debug *dbg)
b6c7a5dc 7199{
355be0b9 7200 unsigned long rflags;
ae675ef0 7201 int i, r;
b6c7a5dc 7202
4f926bf2
JK		 7203 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7204 r = -EBUSY;
7205 if (vcpu->arch.exception.pending)
2122ff5e 7206 goto out;
4f926bf2
JK		 7207 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7208 kvm_queue_exception(vcpu, DB_VECTOR);
7209 else
7210 kvm_queue_exception(vcpu, BP_VECTOR);
7211 }
7212
91586a3b
JK		 7213 /*
7214 * Read rflags as long as potentially injected trace flags are still
7215 * filtered out.
7216 */
7217 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7218
7219 vcpu->guest_debug = dbg->control;
7220 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7221 vcpu->guest_debug = 0;
7222
7223 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7224 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7225 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7226 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7227 } else {
7228 for (i = 0; i < KVM_NR_DB_REGS; i++)
7229 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7230 }
c8639010 7231 kvm_update_dr7(vcpu);
ae675ef0 7232
f92653ee
JK		 7233 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7234 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7235 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7236
91586a3b
JK		 7237 /*
7238 * Trigger an rflags update that will inject or remove the trace
7239 * flags.
7240 */
7241 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7242
a96036b8 7243 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7244
4f926bf2 7245 r = 0;
d0bfb940 7246
2122ff5e 7247out:
b6c7a5dc
HB		 7248
7249 return r;
7250}
7251
8b006791
ZX		 7252/*
7253 * Translate a guest virtual address to a guest physical address.
7254 */
7255int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7256 struct kvm_translation *tr)
7257{
7258 unsigned long vaddr = tr->linear_address;
7259 gpa_t gpa;
f656ce01 7260 int idx;
8b006791 7261
f656ce01 7262 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7263 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7264 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7265 tr->physical_address = gpa;
7266 tr->valid = gpa != UNMAPPED_GVA;
7267 tr->writeable = 1;
7268 tr->usermode = 0;
8b006791
ZX		 7269
7270 return 0;
7271}
7272
d0752060
HB		 7273int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7274{
c47ada30 7275 struct fxregs_state *fxsave =
7366ed77 7276 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7277
d0752060
HB		 7278 memcpy(fpu->fpr, fxsave->st_space, 128);
7279 fpu->fcw = fxsave->cwd;
7280 fpu->fsw = fxsave->swd;
7281 fpu->ftwx = fxsave->twd;
7282 fpu->last_opcode = fxsave->fop;
7283 fpu->last_ip = fxsave->rip;
7284 fpu->last_dp = fxsave->rdp;
7285 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7286
d0752060
HB		 7287 return 0;
7288}
7289
7290int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7291{
c47ada30 7292 struct fxregs_state *fxsave =
7366ed77 7293 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7294
d0752060
HB		 7295 memcpy(fxsave->st_space, fpu->fpr, 128);
7296 fxsave->cwd = fpu->fcw;
7297 fxsave->swd = fpu->fsw;
7298 fxsave->twd = fpu->ftwx;
7299 fxsave->fop = fpu->last_opcode;
7300 fxsave->rip = fpu->last_ip;
7301 fxsave->rdp = fpu->last_dp;
7302 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7303
d0752060
HB		 7304 return 0;
7305}
7306
0ee6a517 7307static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7308{
bf935b0b 7309 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7310 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7311 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7312 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7313
2acf923e
DC		 7314 /*
7315 * Ensure guest xcr0 is valid for loading
7316 */
d91cab78 7317 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7318
ad312c7c 7319 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7320}
d0752060
HB		 7321
7322void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7323{
2608d7a1 7324 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7325 return;
7326
2acf923e
DC		 7327 /*
7328 * Restore all possible states in the guest,
7329 * and assume host would use all available bits.
7330 * Guest xcr0 would be loaded later.
7331 */
d0752060 7332 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7333 __kernel_fpu_begin();
003e2e8b 7334 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7335 trace_kvm_fpu(1);
d0752060 7336}
d0752060
HB		 7337
7338void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7339{
653f52c3
RR		 7340 if (!vcpu->guest_fpu_loaded) {
7341 vcpu->fpu_counter = 0;
d0752060 7342 return;
653f52c3 7343 }
d0752060
HB		 7344
7345 vcpu->guest_fpu_loaded = 0;
4f836347 7346 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7347 __kernel_fpu_end();
f096ed85 7348 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7349 /*
7350 * If using eager FPU mode, or if the guest is a frequent user
7351 * of the FPU, just leave the FPU active for next time.
7352 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7353 * the FPU in bursts will revert to loading it on demand.
7354 */
5a5fbdc0 7355 if (!use_eager_fpu()) {
653f52c3
RR		 7356 if (++vcpu->fpu_counter < 5)
7357 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7358 }
0c04851c 7359 trace_kvm_fpu(0);
d0752060 7360}
e9b11c17
ZX		 7361
7362void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7363{
12f9a48f 7364 kvmclock_reset(vcpu);
7f1ea208 7365
f5f48ee1 7366 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7367 kvm_x86_ops->vcpu_free(vcpu);
7368}
7369
7370struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7371 unsigned int id)
7372{
c447e76b
LL		 7373 struct kvm_vcpu *vcpu;
7374
6755bae8
ZA		 7375 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7376 printk_once(KERN_WARNING
7377 "kvm: SMP vm created on host with unstable TSC; "
7378 "guest TSC will not be reliable\n");
c447e76b
LL		 7379
7380 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7381
c447e76b 7382 return vcpu;
26e5215f 7383}
e9b11c17 7384
26e5215f
AK		 7385int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7386{
7387 int r;
e9b11c17 7388
19efffa2 7389 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7390 r = vcpu_load(vcpu);
7391 if (r)
7392 return r;
d28bc9dd 7393 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7394 kvm_mmu_setup(vcpu);
e9b11c17 7395 vcpu_put(vcpu);
26e5215f 7396 return r;
e9b11c17
ZX		 7397}
7398
31928aa5 7399void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7400{
8fe8ab46 7401 struct msr_data msr;
332967a3 7402 struct kvm *kvm = vcpu->kvm;
42897d86 7403
31928aa5
DD		 7404 if (vcpu_load(vcpu))
7405 return;
8fe8ab46
WA		 7406 msr.data = 0x0;
7407 msr.index = MSR_IA32_TSC;
7408 msr.host_initiated = true;
7409 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7410 vcpu_put(vcpu);
7411
630994b3
MT		 7412 if (!kvmclock_periodic_sync)
7413 return;
7414
332967a3
AJ		 7415 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7416 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7417}
7418
d40ccc62 7419void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7420{
9fc77441 7421 int r;
344d9588
GN		 7422 vcpu->arch.apf.msr_val = 0;
7423
9fc77441
MT		 7424 r = vcpu_load(vcpu);
7425 BUG_ON(r);
e9b11c17
ZX		 7426 kvm_mmu_unload(vcpu);
7427 vcpu_put(vcpu);
7428
7429 kvm_x86_ops->vcpu_free(vcpu);
7430}
7431
d28bc9dd 7432void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7433{
e69fab5d
PB		 7434 vcpu->arch.hflags = 0;
7435
7460fb4a
AK		 7436 atomic_set(&vcpu->arch.nmi_queued, 0);
7437 vcpu->arch.nmi_pending = 0;
448fa4a9 7438 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7439 kvm_clear_interrupt_queue(vcpu);
7440 kvm_clear_exception_queue(vcpu);
448fa4a9 7441
42dbaa5a 7442 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7443 kvm_update_dr0123(vcpu);
6f43ed01 7444 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7445 kvm_update_dr6(vcpu);
42dbaa5a 7446 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7447 kvm_update_dr7(vcpu);
42dbaa5a 7448
1119022c
NA		 7449 vcpu->arch.cr2 = 0;
7450
3842d135 7451 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7452 vcpu->arch.apf.msr_val = 0;
c9aaa895 7453 vcpu->arch.st.msr_val = 0;
3842d135 7454
12f9a48f
GC		 7455 kvmclock_reset(vcpu);
7456
af585b92
GN		 7457 kvm_clear_async_pf_completion_queue(vcpu);
7458 kvm_async_pf_hash_reset(vcpu);
7459 vcpu->arch.apf.halted = false;
3842d135 7460
64d60670 7461 if (!init_event) {
d28bc9dd 7462 kvm_pmu_reset(vcpu);
64d60670
PB		 7463 vcpu->arch.smbase = 0x30000;
7464 }
f5132b01 7465
66f7b72e
JS		 7466 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7467 vcpu->arch.regs_avail = ~0;
7468 vcpu->arch.regs_dirty = ~0;
7469
d28bc9dd 7470 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7471}
7472
2b4a273b 7473void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7474{
7475 struct kvm_segment cs;
7476
7477 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7478 cs.selector = vector << 8;
7479 cs.base = vector << 12;
7480 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7481 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7482}
7483
13a34e06 7484int kvm_arch_hardware_enable(void)
e9b11c17 7485{
ca84d1a2
ZA		 7486 struct kvm *kvm;
7487 struct kvm_vcpu *vcpu;
7488 int i;
0dd6a6ed
ZA		 7489 int ret;
7490 u64 local_tsc;
7491 u64 max_tsc = 0;
7492 bool stable, backwards_tsc = false;
18863bdd
AK		 7493
7494 kvm_shared_msr_cpu_online();
13a34e06 7495 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7496 if (ret != 0)
7497 return ret;
7498
4ea1636b 7499 local_tsc = rdtsc();
0dd6a6ed
ZA		 7500 stable = !check_tsc_unstable();
7501 list_for_each_entry(kvm, &vm_list, vm_list) {
7502 kvm_for_each_vcpu(i, vcpu, kvm) {
7503 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7504 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7505 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7506 backwards_tsc = true;
7507 if (vcpu->arch.last_host_tsc > max_tsc)
7508 max_tsc = vcpu->arch.last_host_tsc;
7509 }
7510 }
7511 }
7512
7513 /*
7514 * Sometimes, even reliable TSCs go backwards. This happens on
7515 * platforms that reset TSC during suspend or hibernate actions, but
7516 * maintain synchronization. We must compensate. Fortunately, we can
7517 * detect that condition here, which happens early in CPU bringup,
7518 * before any KVM threads can be running. Unfortunately, we can't
7519 * bring the TSCs fully up to date with real time, as we aren't yet far
7520 * enough into CPU bringup that we know how much real time has actually
7521 * elapsed; our helper function, get_kernel_ns() will be using boot
7522 * variables that haven't been updated yet.
7523 *
7524 * So we simply find the maximum observed TSC above, then record the
7525 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7526 * the adjustment will be applied. Note that we accumulate
7527 * adjustments, in case multiple suspend cycles happen before some VCPU
7528 * gets a chance to run again. In the event that no KVM threads get a
7529 * chance to run, we will miss the entire elapsed period, as we'll have
7530 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7531 * loose cycle time. This isn't too big a deal, since the loss will be
7532 * uniform across all VCPUs (not to mention the scenario is extremely
7533 * unlikely). It is possible that a second hibernate recovery happens
7534 * much faster than a first, causing the observed TSC here to be
7535 * smaller; this would require additional padding adjustment, which is
7536 * why we set last_host_tsc to the local tsc observed here.
7537 *
7538 * N.B. - this code below runs only on platforms with reliable TSC,
7539 * as that is the only way backwards_tsc is set above. Also note
7540 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7541 * have the same delta_cyc adjustment applied if backwards_tsc
7542 * is detected. Note further, this adjustment is only done once,
7543 * as we reset last_host_tsc on all VCPUs to stop this from being
7544 * called multiple times (one for each physical CPU bringup).
7545 *
4a969980 7546 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7547 * will be compensated by the logic in vcpu_load, which sets the TSC to
7548 * catchup mode. This will catchup all VCPUs to real time, but cannot
7549 * guarantee that they stay in perfect synchronization.
7550 */
7551 if (backwards_tsc) {
7552 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7553 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7554 list_for_each_entry(kvm, &vm_list, vm_list) {
7555 kvm_for_each_vcpu(i, vcpu, kvm) {
7556 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7557 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7558 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7559 }
7560
7561 /*
7562 * We have to disable TSC offset matching.. if you were
7563 * booting a VM while issuing an S4 host suspend....
7564 * you may have some problem. Solving this issue is
7565 * left as an exercise to the reader.
7566 */
7567 kvm->arch.last_tsc_nsec = 0;
7568 kvm->arch.last_tsc_write = 0;
7569 }
7570
7571 }
7572 return 0;
e9b11c17
ZX		 7573}
7574
13a34e06 7575void kvm_arch_hardware_disable(void)
e9b11c17 7576{
13a34e06
RK		 7577 kvm_x86_ops->hardware_disable();
7578 drop_user_return_notifiers();
e9b11c17
ZX		 7579}
7580
7581int kvm_arch_hardware_setup(void)
7582{
9e9c3fe4
NA		 7583 int r;
7584
7585 r = kvm_x86_ops->hardware_setup();
7586 if (r != 0)
7587 return r;
7588
35181e86
HZ		 7589 if (kvm_has_tsc_control) {
7590 /*
7591 * Make sure the user can only configure tsc_khz values that
7592 * fit into a signed integer.
7593 * A min value is not calculated needed because it will always
7594 * be 1 on all machines.
7595 */
7596 u64 max = min(0x7fffffffULL,
7597 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7598 kvm_max_guest_tsc_khz = max;
7599
ad721883 7600 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7601 }
ad721883 7602
9e9c3fe4
NA		 7603 kvm_init_msr_list();
7604 return 0;
e9b11c17
ZX		 7605}
7606
7607void kvm_arch_hardware_unsetup(void)
7608{
7609 kvm_x86_ops->hardware_unsetup();
7610}
7611
7612void kvm_arch_check_processor_compat(void *rtn)
7613{
7614 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7615}
7616
7617bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7618{
7619 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7620}
7621EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7622
7623bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7624{
7625 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7626}
7627
3e515705
AK		 7628bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7629{
35754c98 7630 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7631}
7632
54e9818f 7633struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7634EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7635
e9b11c17
ZX		 7636int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7637{
7638 struct page *page;
7639 struct kvm *kvm;
7640 int r;
7641
7642 BUG_ON(vcpu->kvm == NULL);
7643 kvm = vcpu->kvm;
7644
d62caabb 7645 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7646 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7647 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7648 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7649 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7650 else
a4535290 7651 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7652
7653 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7654 if (!page) {
7655 r = -ENOMEM;
7656 goto fail;
7657 }
ad312c7c 7658 vcpu->arch.pio_data = page_address(page);
e9b11c17 7659
cc578287 7660 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7661
e9b11c17
ZX		 7662 r = kvm_mmu_create(vcpu);
7663 if (r < 0)
7664 goto fail_free_pio_data;
7665
7666 if (irqchip_in_kernel(kvm)) {
7667 r = kvm_create_lapic(vcpu);
7668 if (r < 0)
7669 goto fail_mmu_destroy;
54e9818f
GN		 7670 } else
7671 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7672
890ca9ae
HY		 7673 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7674 GFP_KERNEL);
7675 if (!vcpu->arch.mce_banks) {
7676 r = -ENOMEM;
443c39bc 7677 goto fail_free_lapic;
890ca9ae
HY		 7678 }
7679 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7680
f1797359
WY		 7681 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7682 r = -ENOMEM;
f5f48ee1 7683 goto fail_free_mce_banks;
f1797359 7684 }
f5f48ee1 7685
0ee6a517 7686 fx_init(vcpu);
66f7b72e 7687
ba904635 7688 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7689 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7690
7691 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7692 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7693
5a4f55cd
EK		 7694 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7695
74545705
RK		 7696 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7697
af585b92 7698 kvm_async_pf_hash_reset(vcpu);
f5132b01 7699 kvm_pmu_init(vcpu);
af585b92 7700
1c1a9ce9
SR		 7701 vcpu->arch.pending_external_vector = -1;
7702
5c919412
AS		 7703 kvm_hv_vcpu_init(vcpu);
7704
e9b11c17 7705 return 0;
0ee6a517 7706
f5f48ee1
SY		 7707fail_free_mce_banks:
7708 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7709fail_free_lapic:
7710 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7711fail_mmu_destroy:
7712 kvm_mmu_destroy(vcpu);
7713fail_free_pio_data:
ad312c7c 7714 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7715fail:
7716 return r;
7717}
7718
7719void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7720{
f656ce01
MT		 7721 int idx;
7722
1f4b34f8 7723 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7724 kvm_pmu_destroy(vcpu);
36cb93fd 7725 kfree(vcpu->arch.mce_banks);
e9b11c17 7726 kvm_free_lapic(vcpu);
f656ce01 7727 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7728 kvm_mmu_destroy(vcpu);
f656ce01 7729 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7730 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7731 if (!lapic_in_kernel(vcpu))
54e9818f 7732 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7733}
d19a9cd2 7734
e790d9ef
RK		 7735void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7736{
ae97a3b8 7737 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7738}
7739
e08b9637 7740int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7741{
e08b9637
CO		 7742 if (type)
7743 return -EINVAL;
7744
6ef768fa 7745 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7746 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7747 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7748 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7749 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7750
5550af4d
SY		 7751 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7752 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7753 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7754 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7755 &kvm->arch.irq_sources_bitmap);
5550af4d 7756
038f8c11 7757 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7758 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7759 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7760
7761 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7762
7e44e449 7763 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7764 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7765
0eb05bf2 7766 kvm_page_track_init(kvm);
13d268ca 7767 kvm_mmu_init_vm(kvm);
0eb05bf2 7768
03543133
SS		 7769 if (kvm_x86_ops->vm_init)
7770 return kvm_x86_ops->vm_init(kvm);
7771
d89f5eff 7772 return 0;
d19a9cd2
ZX		 7773}
7774
7775static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7776{
9fc77441
MT		 7777 int r;
7778 r = vcpu_load(vcpu);
7779 BUG_ON(r);
d19a9cd2
ZX		 7780 kvm_mmu_unload(vcpu);
7781 vcpu_put(vcpu);
7782}
7783
7784static void kvm_free_vcpus(struct kvm *kvm)
7785{
7786 unsigned int i;
988a2cae 7787 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7788
7789 /*
7790 * Unpin any mmu pages first.
7791 */
af585b92
GN		 7792 kvm_for_each_vcpu(i, vcpu, kvm) {
7793 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7794 kvm_unload_vcpu_mmu(vcpu);
af585b92 7795 }
988a2cae
GN		 7796 kvm_for_each_vcpu(i, vcpu, kvm)
7797 kvm_arch_vcpu_free(vcpu);
7798
7799 mutex_lock(&kvm->lock);
7800 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7801 kvm->vcpus[i] = NULL;
d19a9cd2 7802
988a2cae
GN		 7803 atomic_set(&kvm->online_vcpus, 0);
7804 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7805}
7806
ad8ba2cd
SY		 7807void kvm_arch_sync_events(struct kvm *kvm)
7808{
332967a3 7809 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7810 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7811 kvm_free_all_assigned_devices(kvm);
aea924f6 7812 kvm_free_pit(kvm);
ad8ba2cd
SY		 7813}
7814
1d8007bd 7815int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7816{
7817 int i, r;
25188b99 7818 unsigned long hva;
f0d648bd
PB		 7819 struct kvm_memslots *slots = kvm_memslots(kvm);
7820 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7821
7822 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7823 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7824 return -EINVAL;
9da0e4d5 7825
f0d648bd
PB		 7826 slot = id_to_memslot(slots, id);
7827 if (size) {
b21629da 7828 if (slot->npages)
f0d648bd
PB		 7829 return -EEXIST;
7830
7831 /*
7832 * MAP_SHARED to prevent internal slot pages from being moved
7833 * by fork()/COW.
7834 */
7835 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7836 MAP_SHARED | MAP_ANONYMOUS, 0);
7837 if (IS_ERR((void *)hva))
7838 return PTR_ERR((void *)hva);
7839 } else {
7840 if (!slot->npages)
7841 return 0;
7842
7843 hva = 0;
7844 }
7845
7846 old = *slot;
9da0e4d5 7847 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7848 struct kvm_userspace_memory_region m;
9da0e4d5 7849
1d8007bd
PB		 7850 m.slot = id | (i << 16);
7851 m.flags = 0;
7852 m.guest_phys_addr = gpa;
f0d648bd 7853 m.userspace_addr = hva;
1d8007bd 7854 m.memory_size = size;
9da0e4d5
PB		 7855 r = __kvm_set_memory_region(kvm, &m);
7856 if (r < 0)
7857 return r;
7858 }
7859
f0d648bd
PB		 7860 if (!size) {
7861 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7862 WARN_ON(r < 0);
7863 }
7864
9da0e4d5
PB		 7865 return 0;
7866}
7867EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7868
1d8007bd 7869int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7870{
7871 int r;
7872
7873 mutex_lock(&kvm->slots_lock);
1d8007bd 7874 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7875 mutex_unlock(&kvm->slots_lock);
7876
7877 return r;
7878}
7879EXPORT_SYMBOL_GPL(x86_set_memory_region);
7880
d19a9cd2
ZX		 7881void kvm_arch_destroy_vm(struct kvm *kvm)
7882{
27469d29
AH		 7883 if (current->mm == kvm->mm) {
7884 /*
7885 * Free memory regions allocated on behalf of userspace,
7886 * unless the the memory map has changed due to process exit
7887 * or fd copying.
7888 */
1d8007bd
PB		 7889 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7890 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7891 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7892 }
03543133
SS		 7893 if (kvm_x86_ops->vm_destroy)
7894 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7895 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7896 kfree(kvm->arch.vpic);
7897 kfree(kvm->arch.vioapic);
d19a9cd2 7898 kvm_free_vcpus(kvm);
1e08ec4a 7899 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7900 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7901}
0de10343 7902
5587027c 7903void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7904 struct kvm_memory_slot *dont)
7905{
7906 int i;
7907
d89cc617
TY		 7908 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7909 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7910 kvfree(free->arch.rmap[i]);
d89cc617 7911 free->arch.rmap[i] = NULL;
77d11309 7912 }
d89cc617
TY		 7913 if (i == 0)
7914 continue;
7915
7916 if (!dont || free->arch.lpage_info[i - 1] !=
7917 dont->arch.lpage_info[i - 1]) {
548ef284 7918 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7919 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7920 }
7921 }
21ebbeda
XG		 7922
7923 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7924}
7925
5587027c
AK		 7926int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7927 unsigned long npages)
db3fe4eb
TY		 7928{
7929 int i;
7930
d89cc617 7931 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7932 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7933 unsigned long ugfn;
7934 int lpages;
d89cc617 7935 int level = i + 1;
db3fe4eb
TY		 7936
7937 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7938 slot->base_gfn, level) + 1;
7939
d89cc617
TY		 7940 slot->arch.rmap[i] =
7941 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7942 if (!slot->arch.rmap[i])
77d11309 7943 goto out_free;
d89cc617
TY		 7944 if (i == 0)
7945 continue;
77d11309 7946
92f94f1e
XG		 7947 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7948 if (!linfo)
db3fe4eb
TY		 7949 goto out_free;
7950
92f94f1e
XG		 7951 slot->arch.lpage_info[i - 1] = linfo;
7952
db3fe4eb 7953 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7954 linfo[0].disallow_lpage = 1;
db3fe4eb 7955 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7956 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7957 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7958 /*
7959 * If the gfn and userspace address are not aligned wrt each
7960 * other, or if explicitly asked to, disable large page
7961 * support for this slot
7962 */
7963 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7964 !kvm_largepages_enabled()) {
7965 unsigned long j;
7966
7967 for (j = 0; j < lpages; ++j)
92f94f1e 7968 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7969 }
7970 }
7971
21ebbeda
XG		 7972 if (kvm_page_track_create_memslot(slot, npages))
7973 goto out_free;
7974
db3fe4eb
TY		 7975 return 0;
7976
7977out_free:
d89cc617 7978 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7979 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7980 slot->arch.rmap[i] = NULL;
7981 if (i == 0)
7982 continue;
7983
548ef284 7984 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7985 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7986 }
7987 return -ENOMEM;
7988}
7989
15f46015 7990void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7991{
e6dff7d1
TY		 7992 /*
7993 * memslots->generation has been incremented.
7994 * mmio generation may have reached its maximum value.
7995 */
54bf36aa 7996 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7997}
7998
f7784b8e
MT		 7999int kvm_arch_prepare_memory_region(struct kvm *kvm,
8000 struct kvm_memory_slot *memslot,
09170a49 8001 const struct kvm_userspace_memory_region *mem,
7b6195a9 8002 enum kvm_mr_change change)
0de10343 8003{
f7784b8e
MT		 8004 return 0;
8005}
8006
88178fd4
KH		 8007static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8008 struct kvm_memory_slot *new)
8009{
8010 /* Still write protect RO slot */
8011 if (new->flags & KVM_MEM_READONLY) {
8012 kvm_mmu_slot_remove_write_access(kvm, new);
8013 return;
8014 }
8015
8016 /*
8017 * Call kvm_x86_ops dirty logging hooks when they are valid.
8018 *
8019 * kvm_x86_ops->slot_disable_log_dirty is called when:
8020 *
8021 * - KVM_MR_CREATE with dirty logging is disabled
8022 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8023 *
8024 * The reason is, in case of PML, we need to set D-bit for any slots
8025 * with dirty logging disabled in order to eliminate unnecessary GPA
8026 * logging in PML buffer (and potential PML buffer full VMEXT). This
8027 * guarantees leaving PML enabled during guest's lifetime won't have
8028 * any additonal overhead from PML when guest is running with dirty
8029 * logging disabled for memory slots.
8030 *
8031 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8032 * to dirty logging mode.
8033 *
8034 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8035 *
8036 * In case of write protect:
8037 *
8038 * Write protect all pages for dirty logging.
8039 *
8040 * All the sptes including the large sptes which point to this
8041 * slot are set to readonly. We can not create any new large
8042 * spte on this slot until the end of the logging.
8043 *
8044 * See the comments in fast_page_fault().
8045 */
8046 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8047 if (kvm_x86_ops->slot_enable_log_dirty)
8048 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8049 else
8050 kvm_mmu_slot_remove_write_access(kvm, new);
8051 } else {
8052 if (kvm_x86_ops->slot_disable_log_dirty)
8053 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8054 }
8055}
8056
f7784b8e 8057void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8058 const struct kvm_userspace_memory_region *mem,
8482644a 8059 const struct kvm_memory_slot *old,
f36f3f28 8060 const struct kvm_memory_slot *new,
8482644a 8061 enum kvm_mr_change change)
f7784b8e 8062{
8482644a 8063 int nr_mmu_pages = 0;
f7784b8e 8064
48c0e4e9
XG		 8065 if (!kvm->arch.n_requested_mmu_pages)
8066 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8067
48c0e4e9 8068 if (nr_mmu_pages)
0de10343 8069 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8070
3ea3b7fa
WL		 8071 /*
8072 * Dirty logging tracks sptes in 4k granularity, meaning that large
8073 * sptes have to be split. If live migration is successful, the guest
8074 * in the source machine will be destroyed and large sptes will be
8075 * created in the destination. However, if the guest continues to run
8076 * in the source machine (for example if live migration fails), small
8077 * sptes will remain around and cause bad performance.
8078 *
8079 * Scan sptes if dirty logging has been stopped, dropping those
8080 * which can be collapsed into a single large-page spte. Later
8081 * page faults will create the large-page sptes.
8082 */
8083 if ((change != KVM_MR_DELETE) &&
8084 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8085 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8086 kvm_mmu_zap_collapsible_sptes(kvm, new);
8087
c972f3b1 8088 /*
88178fd4 8089 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8090 *
88178fd4
KH		 8091 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8092 * been zapped so no dirty logging staff is needed for old slot. For
8093 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8094 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8095 *
8096 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8097 */
88178fd4 8098 if (change != KVM_MR_DELETE)
f36f3f28 8099 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8100}
1d737c8a 8101
2df72e9b 8102void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8103{
6ca18b69 8104 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8105}
8106
2df72e9b
MT		 8107void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8108 struct kvm_memory_slot *slot)
8109{
6ca18b69 8110 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8111}
8112
5d9bc648
PB		 8113static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8114{
8115 if (!list_empty_careful(&vcpu->async_pf.done))
8116 return true;
8117
8118 if (kvm_apic_has_events(vcpu))
8119 return true;
8120
8121 if (vcpu->arch.pv.pv_unhalted)
8122 return true;
8123
8124 if (atomic_read(&vcpu->arch.nmi_queued))
8125 return true;
8126
73917739
PB		 8127 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8128 return true;
8129
5d9bc648
PB		 8130 if (kvm_arch_interrupt_allowed(vcpu) &&
8131 kvm_cpu_has_interrupt(vcpu))
8132 return true;
8133
1f4b34f8
AS		 8134 if (kvm_hv_has_stimer_pending(vcpu))
8135 return true;
8136
5d9bc648
PB		 8137 return false;
8138}
8139
1d737c8a
ZX		 8140int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8141{
b6b8a145
JK		 8142 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8143 kvm_x86_ops->check_nested_events(vcpu, false);
8144
5d9bc648 8145 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8146}
5736199a 8147
b6d33834 8148int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8149{
b6d33834 8150 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8151}
78646121
GN		 8152
8153int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8154{
8155 return kvm_x86_ops->interrupt_allowed(vcpu);
8156}
229456fc 8157
82b32774 8158unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8159{
82b32774
NA		 8160 if (is_64_bit_mode(vcpu))
8161 return kvm_rip_read(vcpu);
8162 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8163 kvm_rip_read(vcpu));
8164}
8165EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8166
82b32774
NA		 8167bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8168{
8169 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8170}
8171EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8172
94fe45da
JK		 8173unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8174{
8175 unsigned long rflags;
8176
8177 rflags = kvm_x86_ops->get_rflags(vcpu);
8178 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8179 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8180 return rflags;
8181}
8182EXPORT_SYMBOL_GPL(kvm_get_rflags);
8183
6addfc42 8184static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8185{
8186 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8187 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8188 rflags |= X86_EFLAGS_TF;
94fe45da 8189 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8190}
8191
8192void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8193{
8194 __kvm_set_rflags(vcpu, rflags);
3842d135 8195 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8196}
8197EXPORT_SYMBOL_GPL(kvm_set_rflags);
8198
56028d08
GN		 8199void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8200{
8201 int r;
8202
fb67e14f 8203 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8204 work->wakeup_all)
56028d08
GN		 8205 return;
8206
8207 r = kvm_mmu_reload(vcpu);
8208 if (unlikely(r))
8209 return;
8210
fb67e14f
XG		 8211 if (!vcpu->arch.mmu.direct_map &&
8212 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8213 return;
8214
56028d08
GN		 8215 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8216}
8217
af585b92
GN		 8218static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8219{
8220 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8221}
8222
8223static inline u32 kvm_async_pf_next_probe(u32 key)
8224{
8225 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8226}
8227
8228static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8229{
8230 u32 key = kvm_async_pf_hash_fn(gfn);
8231
8232 while (vcpu->arch.apf.gfns[key] != ~0)
8233 key = kvm_async_pf_next_probe(key);
8234
8235 vcpu->arch.apf.gfns[key] = gfn;
8236}
8237
8238static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8239{
8240 int i;
8241 u32 key = kvm_async_pf_hash_fn(gfn);
8242
8243 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8244 (vcpu->arch.apf.gfns[key] != gfn &&
8245 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8246 key = kvm_async_pf_next_probe(key);
8247
8248 return key;
8249}
8250
8251bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8252{
8253 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8254}
8255
8256static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8257{
8258 u32 i, j, k;
8259
8260 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8261 while (true) {
8262 vcpu->arch.apf.gfns[i] = ~0;
8263 do {
8264 j = kvm_async_pf_next_probe(j);
8265 if (vcpu->arch.apf.gfns[j] == ~0)
8266 return;
8267 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8268 /*
8269 * k lies cyclically in ]i,j]
8270 * | i.k.j |
8271 * |....j i.k.| or |.k..j i...|
8272 */
8273 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8274 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8275 i = j;
8276 }
8277}
8278
7c90705b
GN		 8279static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8280{
8281
8282 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8283 sizeof(val));
8284}
8285
af585b92
GN		 8286void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8287 struct kvm_async_pf *work)
8288{
6389ee94
AK		 8289 struct x86_exception fault;
8290
7c90705b 8291 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8292 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8293
8294 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8295 (vcpu->arch.apf.send_user_only &&
8296 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8297 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8298 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8299 fault.vector = PF_VECTOR;
8300 fault.error_code_valid = true;
8301 fault.error_code = 0;
8302 fault.nested_page_fault = false;
8303 fault.address = work->arch.token;
8304 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8305 }
af585b92
GN		 8306}
8307
8308void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8309 struct kvm_async_pf *work)
8310{
6389ee94
AK		 8311 struct x86_exception fault;
8312
7c90705b 8313 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8314 if (work->wakeup_all)
7c90705b
GN		 8315 work->arch.token = ~0; /* broadcast wakeup */
8316 else
8317 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8318
8319 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8320 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8321 fault.vector = PF_VECTOR;
8322 fault.error_code_valid = true;
8323 fault.error_code = 0;
8324 fault.nested_page_fault = false;
8325 fault.address = work->arch.token;
8326 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8327 }
e6d53e3b 8328 vcpu->arch.apf.halted = false;
a4fa1635 8329 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8330}
8331
8332bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8333{
8334 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8335 return true;
8336 else
8337 return !kvm_event_needs_reinjection(vcpu) &&
8338 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8339}
8340
5544eb9b
PB		 8341void kvm_arch_start_assignment(struct kvm *kvm)
8342{
8343 atomic_inc(&kvm->arch.assigned_device_count);
8344}
8345EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8346
8347void kvm_arch_end_assignment(struct kvm *kvm)
8348{
8349 atomic_dec(&kvm->arch.assigned_device_count);
8350}
8351EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8352
8353bool kvm_arch_has_assigned_device(struct kvm *kvm)
8354{
8355 return atomic_read(&kvm->arch.assigned_device_count);
8356}
8357EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8358
e0f0bbc5
AW		 8359void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8360{
8361 atomic_inc(&kvm->arch.noncoherent_dma_count);
8362}
8363EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8364
8365void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8366{
8367 atomic_dec(&kvm->arch.noncoherent_dma_count);
8368}
8369EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8370
8371bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8372{
8373 return atomic_read(&kvm->arch.noncoherent_dma_count);
8374}
8375EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8376
14717e20
AW		 8377bool kvm_arch_has_irq_bypass(void)
8378{
8379 return kvm_x86_ops->update_pi_irte != NULL;
8380}
8381
87276880
FW		 8382int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8383 struct irq_bypass_producer *prod)
8384{
8385 struct kvm_kernel_irqfd *irqfd =
8386 container_of(cons, struct kvm_kernel_irqfd, consumer);
8387
14717e20 8388 irqfd->producer = prod;
87276880 8389
14717e20
AW		 8390 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8391 prod->irq, irqfd->gsi, 1);
87276880
FW		 8392}
8393
8394void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8395 struct irq_bypass_producer *prod)
8396{
8397 int ret;
8398 struct kvm_kernel_irqfd *irqfd =
8399 container_of(cons, struct kvm_kernel_irqfd, consumer);
8400
87276880
FW		 8401 WARN_ON(irqfd->producer != prod);
8402 irqfd->producer = NULL;
8403
8404 /*
8405 * When producer of consumer is unregistered, we change back to
8406 * remapped mode, so we can re-use the current implementation
8407 * when the irq is masked/disabed or the consumer side (KVM
8408 * int this case doesn't want to receive the interrupts.
8409 */
8410 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8411 if (ret)
8412 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8413 " fails: %d\n", irqfd->consumer.token, ret);
8414}
8415
8416int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8417 uint32_t guest_irq, bool set)
8418{
8419 if (!kvm_x86_ops->update_pi_irte)
8420 return -EINVAL;
8421
8422 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8423}
8424
52004014
FW		 8425bool kvm_vector_hashing_enabled(void)
8426{
8427 return vector_hashing;
8428}
8429EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8430
229456fc 8431EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8432EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8433EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8434EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8435EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8436EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8437EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8440EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8441EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8442EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8443EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8444EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)